From 5d187430a055d62f17ca84d75e7245439d1f7e75 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 6 Jul 2007 11:48:24 +0200 Subject: ppc4xx: Update lwmon5 board Add unlock=yes environment variable to default variables to unlock the CFI flash by default. Signed-off-by: Stefan Roese --- include/configs/lwmon5.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/configs') diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index 1d87c73c71..01adef1d6e 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -162,6 +162,7 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "hostname=lwmon5\0" \ "netdev=eth0\0" \ + "unlock=yes\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ "nfsroot=${serverip}:${rootpath}\0" \ "ramargs=setenv bootargs root=/dev/ram rw\0" \ -- cgit From 334043f601a90ac53e5ecc846fbb73a1ef38cb1f Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 6 Jul 2007 12:26:51 +0200 Subject: ppc4xx: Update lwmon5 default environment Signed-off-by: Stefan Roese --- include/configs/lwmon5.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include/configs') diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index 01adef1d6e..c4b7c4ee50 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -184,6 +184,8 @@ "update=protect off FFF80000 FFFFFFFF;era FFF80000 FFFFFFFF;" \ "cp.b 200000 FFF80000 80000\0" \ "upd=run load;run update\0" \ + "lwe_env=tftp 200000 /tftpboot.dev/lwmon5/env_uboot.bin;" \ + "autoscr 200000\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" -- cgit From 2a49fc17d09020e7ebd9536694d99d20e419fcb8 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 16 Jul 2007 10:01:38 +0200 Subject: ppc4xx: AMCC Luan uses the new boardspecific DDR2 controller setup Signed-off-by: Stefan Roese --- include/configs/luan.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include/configs') diff --git a/include/configs/luan.h b/include/configs/luan.h index cbb59c50ea..e192d06923 100644 --- a/include/configs/luan.h +++ b/include/configs/luan.h @@ -136,7 +136,6 @@ #define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */ #define SPD_EEPROM_ADDRESS {0x53, 0x52} /* SPD i2c spd addresses*/ #define CONFIG_DDR_ECC 1 /* with ECC support */ -#define CFG_44x_DDR2_CKTR_180 1 /* use 180 deg advance */ /*----------------------------------------------------------------------- * I2C -- cgit From 531e3e8b831f357056448fa573137d5fb37000fd Mon Sep 17 00:00:00 2001 From: Pavel Kolesnikov Date: Fri, 20 Jul 2007 15:03:03 +0200 Subject: POST: Add ECC POST for the lwmon5 board This patch adds ECC Post test for the Lwmon5 board based on PPC440EPx to U-Boot. Signed-off-by: Pavel Kolesnikov Acked-by: Yuri Tikhonov Acked-by: Stefan Roese --- include/configs/lwmon5.h | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'include/configs') diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index c4b7c4ee50..36ead23016 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -74,11 +74,13 @@ /* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */ #define CFG_INIT_RAM_OCM 1 /* OCM as init ram */ #define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */ +#define CFG_OCM_DATA_ADDR CFG_OCM_BASE #define CFG_INIT_RAM_END (4 << 10) #define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET +#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4) +#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR /*----------------------------------------------------------------------- * Serial Port @@ -133,6 +135,10 @@ #define CONFIG_DDR_DATA_EYE 1 /* use DDR2 optimization */ #if 0 /* test-only: disable ECC for now */ #define CONFIG_DDR_ECC 1 /* enable ECC */ + +/* POST support */ +#define CONFIG_POST (CFG_POST_ECC) + #endif /*----------------------------------------------------------------------- -- cgit From 9f24a808f17fc0f37b7fb4805f734741335caecc Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Tue, 24 Jul 2007 09:52:52 +0200 Subject: ppc4xx: lwmon5: Support for 128 MByte NOR FLASH added The used Intel NOR FLASH chips have internally two dies, and are now treated as two seperate chips. Signed-off-by: Stefan Roese --- include/configs/lwmon5.h | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) (limited to 'include/configs') diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index 36ead23016..55e2c94d6d 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -46,7 +46,7 @@ #define CFG_BOOT_BASE_ADDR 0xf0000000 #define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ -#define CFG_FLASH_BASE 0xfc000000 /* start of FLASH */ +#define CFG_FLASH_BASE 0xf8000000 /* start of FLASH */ #define CFG_MONITOR_BASE TEXT_BASE #define CFG_LIME_BASE_0 0xc0000000 #define CFG_LIME_BASE_1 0xc1000000 @@ -105,9 +105,11 @@ #define CFG_FLASH_CFI /* The flash is CFI compatible */ #define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ -#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } +#define CFG_FLASH0 0xFC000000 +#define CFG_FLASH1 0xF8000000 +#define CFG_FLASH_BANKS_LIST { CFG_FLASH1, CFG_FLASH0 } -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ #define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ @@ -319,7 +321,7 @@ /* Memory Bank 0 (NOR-FLASH) initialization */ #define CFG_EBC_PB0AP 0x03050200 -#define CFG_EBC_PB0CR (CFG_FLASH | 0xdc000) +#define CFG_EBC_PB0CR (CFG_FLASH | 0xfc000) /* Memory Bank 1 (Lime) initialization */ #define CFG_EBC_PB1AP 0x01004380 -- cgit From b66091de6c7390620312c2501db23d8391e7cabb Mon Sep 17 00:00:00 2001 From: Anatolij Gustschin Date: Thu, 26 Jul 2007 15:08:01 +0200 Subject: ppc4xx: lwmon5: Update Lime initialization Change Lime SDRAM initialization to now support 100MHz and 133MHz (if enabled). Also the framebuffer is initialized to display a blue rectangle with a white border. Signed-off-by: Anatolij Gustschin Signed-off-by: Stefan Roese --- include/configs/lwmon5.h | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) (limited to 'include/configs') diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index 55e2c94d6d..b09b47830a 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -341,14 +341,24 @@ * Graphics (Fujitsu Lime) *----------------------------------------------------------------------*/ /* SDRAM Clock frequency adjustment register */ -#define CFG_LIME_SDRAM_CLOCK 0xC1FC0000 -/* Lime Clock frequency is to set 133MHz */ +#define CFG_LIME_SDRAM_CLOCK 0xC1FC0038 +/* Lime Clock frequency is to set 100MHz */ +#define CFG_LIME_CLOCK_100MHZ 0x00000 +#if 0 +/* Lime Clock frequency for 133MHz */ #define CFG_LIME_CLOCK_133MHZ 0x10000 +#endif /* SDRAM Parameter register */ #define CFG_LIME_MMR 0xC1FCFFFC -/* SDRAM parameter value */ +/* SDRAM parameter value; was 0x414FB7F2, caused several vertical bars + and pixel flare on display when 133MHz was configured. According to + SDRAM chip datasheet CAS Latency is 3 for 133MHz and -75 Speed Grade */ +#ifdef CFG_LIME_CLOCK_133MHZ +#define CFG_LIME_MMR_VALUE 0x414FB7F3 +#else #define CFG_LIME_MMR_VALUE 0x414FB7F2 +#endif /*----------------------------------------------------------------------- * GPIO Setup -- cgit From d4024bb72dd81695ec099b2199eda0d27c623e62 Mon Sep 17 00:00:00 2001 From: John Otken Date: Thu, 26 Jul 2007 17:49:11 +0200 Subject: ppc4xx: Add support for AMCC 405EP Taihu board Signed-off-by: John Otken --- include/configs/taihu.h | 473 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 473 insertions(+) create mode 100644 include/configs/taihu.h (limited to 'include/configs') diff --git a/include/configs/taihu.h b/include/configs/taihu.h new file mode 100644 index 0000000000..61814a8096 --- /dev/null +++ b/include/configs/taihu.h @@ -0,0 +1,473 @@ +/* + * (C) Copyright 2000-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2005-2007 + * Beijing UD Technology Co., Ltd., taihusupport@amcc.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + + +#define CONFIG_405EP 1 /* this is a PPC405 CPU */ +#define CONFIG_4xx 1 /* member of PPC4xx family */ +#define CONFIG_TAIHU 1 /* on a taihu board */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f */ + +#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */ + +#define CONFIG_NO_SERIAL_EEPROM + +/*----------------------------------------------------------------------------*/ +#ifdef CONFIG_NO_SERIAL_EEPROM + +/* +!------------------------------------------------------------------------------- +! PLL settings for 333MHz CPU, 111MHz PLB/SDRAM, 55MHz EBC, 33MHz PCI, +! assuming a 33MHz input clock to the 405EP from the C9531. +!------------------------------------------------------------------------------- +*/ +#define PLLMR0_333_111_55_37 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \ + PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \ + PLL_MALDIV_1 | PLL_PCIDIV_3) +#define PLLMR1_333_111_55_37 (PLL_FBKDIV_10 | \ + PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI) +#define PLLMR0_333_111_55_111 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \ + PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \ + PLL_MALDIV_1 | PLL_PCIDIV_1) +#define PLLMR1_333_111_55_111 (PLL_FBKDIV_10 | \ + PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI) + +#define PLLMR0_DEFAULT PLLMR0_333_111_55_37 +#define PLLMR1_DEFAULT PLLMR1_333_111_55_37 +#define PLLMR0_DEFAULT_PCI66 PLLMR0_333_111_55_111 +#define PLLMR1_DEFAULT_PCI66 PLLMR1_333_111_55_111 + +#endif +/*----------------------------------------------------------------------------*/ + +#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ + +#define CONFIG_ENV_OVERWRITE 1 +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS +#define CONFIG_EXTRA_ENV_SETTINGS \ + "bootfile=/tftpboot/taihu/uImage\0" \ + "rootpath=/opt/eldk/ppc_4xx\0" \ + "netdev=eth0\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ + "flash_nfs=run nfsargs addip addtty;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip addtty;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ + "bootm\0" \ + "kernel_addr=FC000000\0" \ + "ramdisk_addr=FC180000\0" \ + "load=tftp 200000 /tftpboot/taihu/u-boot.bin\0" \ + "update=protect off FFFC0000 FFFFFFFF;era FFFC0000 FFFFFFFF;" \ + "cp.b 200000 FFFC0000 40000\0" \ + "upd=run load;run update\0" \ + "" +#define CONFIG_BOOTCOMMAND "run flash_self" + +#if 0 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#endif + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_ADDR 0x14 /* PHY address */ +#define CONFIG_HAS_ETH1 +#define CONFIG_PHY1_ADDR 0x10 /* EMAC1 PHY address */ +#define CONFIG_NET_MULTI 1 +#define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */ +#define CONFIG_PHY_RESET 1 + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_CACHE | \ + CFG_CMD_DHCP | \ + CFG_CMD_EEPROM | \ + CFG_CMD_ELF | \ + CFG_CMD_I2C | \ + CFG_CMD_SPI | \ + CFG_CMD_IRQ | \ + CFG_CMD_MII | \ + CFG_CMD_NET | \ + CFG_CMD_PCI | \ + CFG_CMD_PING | \ + CFG_CMD_REGINFO | \ + CFG_CMD_SDRAM ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#undef CONFIG_SPD_EEPROM /* use SPD EEPROM for setup */ +#define CFG_SDRAM_SIZE_PER_BANK 0x04000000 /* 64MB */ +#define CFG_SDRAM_BANKS 2 + +/* + * SDRAM configuration (please see cpu/ppc/sdram.[ch]) + */ +#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ +#define CONFIG_SDRAM_BANK1 1 /* init onboard SDRAM bank 1 */ + +/* SDRAM timings used in datasheet */ +#define CFG_SDRAM_CL 3 /* CAS latency */ +#define CFG_SDRAM_tRP 20 /* PRECHARGE command period */ +#define CFG_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE command period */ +#define CFG_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */ +#define CFG_SDRAM_tRFC 66 /* Auto refresh period */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* print buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +/* + * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1. + * If CFG_405_UART_ERRATA_59, then UART divisor is 31. + * Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value. + * The Linux BASE_BAUD define should match this configuration. + * baseBaud = cpuClock/(uartDivisor*16) + * If CFG_405_UART_ERRATA_59 and 200MHz CPU clock, + * set Linux BASE_BAUD to 403200. + */ +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */ +#undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ +#define CFG_BASE_BAUD 691200 + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_UART1_CONSOLE 1 + + +/* The following table includes the supported baudrates */ +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ +#define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + +/*----------------------------------------------------------------------- + * I2C stuff + *----------------------------------------------------------------------- + */ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +#define CFG_I2C_NOPROBES { 0x69 } /* avoid iprobe hangup (why?) */ +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 6 /* 24C02 requires 5ms delay */ + +#if (CONFIG_COMMANDS & CFG_CMD_EEPROM) +#define CFG_I2C_EEPROM_ADDR 0x50 /* I2C boot EEPROM (24C02W) */ +#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ +#endif + + +#define CONFIG_SOFT_SPI +#define SPI_SCL spi_scl +#define SPI_SDA spi_sda +#define SPI_READ spi_read() +#define SPI_DELAY udelay(2) +#ifndef __ASSEMBLY__ +void spi_scl(int); +void spi_sda(int); +unsigned char spi_read(void); +#endif + +/* standard dtt sensor configuration */ +#define CONFIG_DTT_DS1775 1 +#define CONFIG_DTT_SENSORS { 0 } + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------- + */ +#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ +#define PCI_HOST_FORCE 1 /* configure as pci host */ +#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ + +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + /* resource configuration */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ + +#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ +#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ +#define CFG_PCI_CLASSCODE 0x0600 /* PCI Class Code: bridge/host */ +#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ +#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ +#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ +#define CFG_PCI_PTM2LA 0x00000000 /* disabled */ +#define CFG_PCI_PTM2MS 0x00000000 /* disabled */ +#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ +#define CONFIG_EEPRO100 1 + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0xFFE00000 +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ +#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN) + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ + +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_FLASH_ADDR0 0x555 +#define CFG_FLASH_ADDR1 0x2aa +#define CFG_FLASH_WORD_SIZE unsigned short + +#ifdef CFG_ENV_IS_IN_FLASH +#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ +#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) +#endif /* CFG_ENV_IS_IN_FLASH */ + +/*----------------------------------------------------------------------- + * NVRAM organization + */ +#define CFG_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */ +#define CFG_NVRAM_SIZE 0x1ff8 /* NVRAM size */ + +#ifdef CFG_ENV_IS_IN_NVRAM +#define CFG_ENV_SIZE 0x0ff8 /* Size of Environment vars */ +#define CFG_ENV_ADDR \ + (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) /* Env*/ +#endif + +/*----------------------------------------------------------------------- + * PPC405 GPIO Configuration + */ +#define CFG_440_GPIO_TABLE { /* GPIO Alternate1 */ \ +{ \ +/* GPIO Core 0 */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast SPI CS */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO5 TS3 */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO6 TS4 */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO7 TS5 */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO9 TrcClk */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 SPI SCLK */ \ +{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 SPI DI */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 SPI DO */ \ +{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 PCI INTA */ \ +{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 PCI INTB */ \ +{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 PCI INTC */ \ +{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 PCI INTD */ \ +{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 USB */ \ +{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 EBC */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 unused */ \ +{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD UART1 */ \ +{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \ +{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \ +{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx UART0 */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 User LED1 */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 User LED2 */ \ +} \ +} + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 16384 /* For IBM 405EP CPU */ +#define CFG_CACHELINE_SIZE 32 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Init Memory Controller: + * + * BR0/1 and OR0/1 (FLASH) + */ + +#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */ +#define FLASH_BASE1_PRELIM 0xFC000000 /* FLASH bank #1 */ + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in data cache) + */ +/* use on chip memory (OCM) for temperary stack until sdram is tested */ +#define CFG_TEMP_STACK_OCM 1 + +/* On Chip Memory location */ +#define CFG_OCM_DATA_ADDR 0xF8000000 +#define CFG_OCM_DATA_SIZE 0x1000 +#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */ +#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ + +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * External Bus Controller (EBC) Setup + */ + +/* Memory Bank 0 (Flash/SRAM) initialization */ +#define CFG_EBC_PB0AP 0x03815600 +#define CFG_EBC_PB0CR 0xFFE3A000 /* BAS=0xFFE,BS=2MB,BU=R/W,BW=16bit */ + +/* Memory Bank 1 (NVRAM/RTC) initialization */ +#define CFG_EBC_PB1AP 0x05815600 +#define CFG_EBC_PB1CR 0xFC0BA000 /* BAS=0xFc0,BS=32MB,BU=R/W,BW=16bit */ + +/* Memory Bank 2 (USB device) initialization */ +#define CFG_EBC_PB2AP 0x03016600 +#define CFG_EBC_PB2CR 0x50018000 /* BAS=0x500,BS=1MB,BU=R/W,BW=8bit */ + +/* Memory Bank 3 (LCM and D-flip-flop) initialization */ +#define CFG_EBC_PB3AP 0x158FF600 +#define CFG_EBC_PB3CR 0x50118000 /* BAS=0x501,BS=1MB,BU=R/W,BW=8bit */ + +/* Memory Bank 4 (not install) initialization */ +#define CFG_EBC_PB4AP 0x158FF600 +#define CFG_EBC_PB4CR 0x5021A000 + +/*----------------------------------------------------------------------- + * Definitions for GPIO setup (PPC405EP specific) + * + * GPIO0[0] - External Bus Controller BLAST output + * GPIO0[1-9] - Instruction trace outputs + * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs + * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs + * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs + * GPIO0[24-27] - UART0 control signal inputs/outputs + * GPIO0[28-29] - UART1 data signal input/output + * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs + */ +#define CFG_GPIO0_OSRH 0x15555550 /* output select high/low */ +#define CFG_GPIO0_OSRL 0x00000110 +#define CFG_GPIO0_ISR1H 0x00000001 /* input select high/low */ +#define CFG_GPIO0_ISR1L 0x15545440 +#define CFG_GPIO0_TSRH 0x00000000 /* three-state select high/low */ +#define CFG_GPIO0_TSRL 0x00000000 +#define CFG_GPIO0_TCR 0xFFFE8117 /* three-state control */ +#define CFG_GPIO0_ODR 0x00000000 /* open drain */ + +#define GPIO0 0 /* GPIO controller 0 */ + +/* the GPIO macros in include/ppc405.h for High/Low registers are backwards */ + +#define GPIOx_OSL (GPIO0_OSRH-GPIO_BASE) +#define GPIOx_TSL (GPIO0_TSRH-GPIO_BASE) +#define GPIOx_IS1L (GPIO0_ISR1H-GPIO_BASE) +#define GPIOx_IS2L (GPIO0_ISR1H-GPIO_BASE) +#define GPIOx_IS3L (GPIO0_ISR1H-GPIO_BASE) + +#define GPIO_OS(x) (x+GPIOx_OSL) /* GPIO output select */ +#define GPIO_TS(x) (x+GPIOx_TSL) /* GPIO three-state select */ +#define GPIO_IS1(x) (x+GPIOx_IS1L) /* GPIO input select */ +#define GPIO_IS2(x) (x+GPIOx_IS1L) +#define GPIO_IS3(x) (x+GPIOx_IS1L) + +#define CPLD_REG0_ADDR 0x50100000 +#define CPLD_REG1_ADDR 0x50100001 +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +#endif /* __CONFIG_H */ -- cgit From ea9f6bce383cc9fbcdee28b5836109b1a6dba574 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Tue, 31 Jul 2007 08:37:01 +0200 Subject: ppc4xx: Update 440EPx lwmon5 board support - Clear ECC status regs after ECC POST test - Set dcbz for ECC generation with caches enabled as default - Code cleanup Signed-off-by: Stefan Roese --- include/configs/lwmon5.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include/configs') diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index b09b47830a..5ebe4404d9 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -140,7 +140,6 @@ /* POST support */ #define CONFIG_POST (CFG_POST_ECC) - #endif /*----------------------------------------------------------------------- -- cgit From d2f68006627eda6cb6c7f364bddf621dbfd2fc68 Mon Sep 17 00:00:00 2001 From: Eugene OBrien Date: Tue, 31 Jul 2007 10:24:56 +0200 Subject: ppc4xx: Update AMCC Bamboo 440EP support Changed storage type of cfg_simulate_spd_eeprom to const Changed storage type of gpio_tab to stack storage (Cannot access global data declarations in .bss until afer code relocation) Improved SDRAM tests to catch problems where data is not uniquely addressable (e.g. incorrectly programmed SDRAM row or columns) Added CONFIG_PROG_SDRAM_TLB to support Bamboo SIMM/DIMM modules Fixed AM29LV320DT (OpCode Flash) sector map Signed-off-by: Eugene OBrien Signed-off-by: Stefan Roese --- include/configs/bamboo.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include/configs') diff --git a/include/configs/bamboo.h b/include/configs/bamboo.h index d58344d717..4e00b9f77d 100644 --- a/include/configs/bamboo.h +++ b/include/configs/bamboo.h @@ -222,6 +222,8 @@ #define CFG_SIMULATE_SPD_EEPROM 0xff /* simulate spd eeprom on this address */ #define SPD_EEPROM_ADDRESS {CFG_SIMULATE_SPD_EEPROM, 0x50, 0x51} #define CFG_MBYTES_SDRAM (64) /* 64MB fixed size for early-sdram-init */ +#define CONFIG_PROG_SDRAM_TLB +#undef CFG_DRAM_TEST /*----------------------------------------------------------------------- * I2C -- cgit From 3e4c90c6233618fc1806e63fde68df5f3d6a0171 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 10 Aug 2007 08:42:55 +0200 Subject: ppc4xx: Update lwmon5 POST configuration Signed-off-by: Stefan Roese --- include/configs/lwmon5.h | 21 +++++++++++++++++++-- 1 file changed, 19 insertions(+), 2 deletions(-) (limited to 'include/configs') diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index 5ebe4404d9..52db71e89d 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -137,10 +137,25 @@ #define CONFIG_DDR_DATA_EYE 1 /* use DDR2 optimization */ #if 0 /* test-only: disable ECC for now */ #define CONFIG_DDR_ECC 1 /* enable ECC */ +#define CFG_POST_ECC_ON CFG_POST_ECC +#else +#define CFG_POST_ECC_ON 0 +#endif /* POST support */ -#define CONFIG_POST (CFG_POST_ECC) -#endif +#define CONFIG_POST (CFG_POST_MEMORY | \ + CFG_POST_ECC_ON | \ + CFG_POST_CPU | \ + CFG_POST_UART | \ + CFG_POST_I2C | \ + CFG_POST_CACHE | \ + CFG_POST_FPU | \ + CFG_POST_ETHER | \ + CFG_POST_SPR) + +#define CFG_POST_CACHE_ADDR 0x10000000 /* free virtual address */ +#define CONFIG_LOGBUFFER +#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */ /*----------------------------------------------------------------------- * I2C @@ -170,6 +185,7 @@ "hostname=lwmon5\0" \ "netdev=eth0\0" \ "unlock=yes\0" \ + "logversion=2\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ "nfsroot=${serverip}:${rootpath}\0" \ "ramargs=setenv bootargs root=/dev/ram rw\0" \ @@ -244,6 +260,7 @@ CFG_CMD_EEPROM | \ CFG_CMD_ELF | \ CFG_CMD_FAT | \ + CFG_CMD_LOG | \ CFG_CMD_I2C | \ CFG_CMD_IRQ | \ CFG_CMD_MII | \ -- cgit From 714bc55b35b6f6a65cc8740a3842a543e88cdef2 Mon Sep 17 00:00:00 2001 From: Niklaus Giger Date: Fri, 27 Jul 2007 11:27:15 +0200 Subject: Add PPC4xx-HCU4 and HCU5 boards: HCU4 config Signed-off-by: Niklaus Giger --- include/configs/hcu4.h | 343 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 343 insertions(+) create mode 100644 include/configs/hcu4.h (limited to 'include/configs') diff --git a/include/configs/hcu4.h b/include/configs/hcu4.h new file mode 100644 index 0000000000..8779db9afe --- /dev/null +++ b/include/configs/hcu4.h @@ -0,0 +1,343 @@ +/* + *(C) Copyright 2005-2007 Netstal Maschinen AG + * Niklaus Giger (Niklaus.Giger@netstal.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************************************ + * hcu4.h - configuration for HCU4 board (similar to hcu5.h) + ***********************************************************************/ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/*----------------------------------------------------------------------- + * High Level Configuration Options + *----------------------------------------------------------------------*/ +#define CONFIG_HCU4 1 /* Board is HCU4 */ +#define CONFIG_4xx 1 /* ... PPC4xx family */ +#define CONFIG_405GPr 1 /* HCU4 has a 405GPr */ +#define CONFIG_405GP 1 +#define CONFIG_4xx 1 + +#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ +#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ + +/*----------------------------------------------------------------------- + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) +*----------------------------------------------------------------------*/ +#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */ +#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ + + +#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ +#define CFG_FLASH_BASE 0xfff80000 /* start of FLASH */ +#define CFG_MONITOR_BASE TEXT_BASE + +/* ... with on-chip memory here (4KBytes) */ +#define CFG_OCM_DATA_ADDR 0xF4000000 +#define CFG_OCM_DATA_SIZE 0x00001000 +/* Do not set up locked dcache as init ram. */ +#undef CFG_INIT_DCACHE_CS + +/* Use the On-Chip-Memory (OCM) as a temporary stack for the startup code. */ +#define CFG_TEMP_STACK_OCM 1 + +#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* OCM */ +#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE +#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Serial Port + *----------------------------------------------------------------------*/ +/* + * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1. + * If CFG_405_UART_ERRATA_59, then UART divisor is 31. + * Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value. + * The Linux BASE_BAUD define should match this configuration. + * baseBaud = cpuClock/(uartDivisor*16) + * If CFG_405_UART_ERRATA_59 and 200MHz CPU clock, + * set Linux BASE_BAUD to 403200. + */ +#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */ +#undef CONFIG_SERIAL_MULTI /* needed to be able to define + CONFIG_SERIAL_SOFTWARE_FIFO */ +#undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ +#define CFG_BASE_BAUD 691200 + +/* Size (bytes) of interrupt driven serial port buffer. + * Set to 0 to use polling instead of interrupts. + * Setting to 0 will also disable RTS/CTS handshaking. + */ +#undef CONFIG_SERIAL_SOFTWARE_FIFO + +/* Set console baudrate to 9600 */ +#define CONFIG_BAUDRATE 9600 + + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +/*----------------------------------------------------------------------- + * Environment + *----------------------------------------------------------------------*/ + +#undef CFG_ENV_IS_IN_NVRAM +#undef CFG_ENV_IS_IN_FLASH +#define CFG_ENV_IS_IN_EEPROM +#undef CFG_ENV_IS_NOWHERE + +#ifdef CFG_ENV_IS_IN_EEPROM +/* Put the environment after the SDRAM configuration */ +#define PROM_SIZE 2048 +#define CFG_ENV_OFFSET 512 +#define CFG_ENV_SIZE (PROM_SIZE-CFG_ENV_OFFSET) +#endif + +#ifdef CFG_ENV_IS_IN_FLASH +/* Put the environment in Flash */ +#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ +#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) +#endif + +/*----------------------------------------------------------------------- + * I2C stuff for a ATMEL AT24C16 (2kB holding ENV, we are using the + * the first internal I2C controller of the PPC440EPx + *----------------------------------------------------------------------*/ +#define CFG_SPD_BUS_NUM 0 + +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +/* This is the 7bit address of the device, not including P. */ +#define CFG_I2C_EEPROM_ADDR 0x50 +#define CFG_I2C_EEPROM_ADDR_LEN 1 + +/* The EEPROM can do 16byte ( 1 << 4 ) page writes. */ +#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 +#define CFG_EEPROM_PAGE_WRITE_BITS 4 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 +#define CFG_EEPROM_PAGE_WRITE_ENABLE +#undef CFG_I2C_MULTI_EEPROMS + + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + +/* Setup some board specific values for the default environment variables */ +#define CONFIG_HOSTNAME hcu4 +#define CONFIG_IPADDR 172.25.1.42 +#define CONFIG_ETHADDR 00:60:13:00:00:00 /* Netstal Machines AG MAC */ +#define CONFIG_OVERWRITE_ETHADDR_ONCE +#define CONFIG_SERVERIP 172.25.1.3 + +#define CFG_TFTP_LOADADDR 0x01000000 /* @16 MB */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "loadaddr=0x01000000\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ + "nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ + "bootm\0" \ + "rootpath=/home/diagnose/eldk/ppc_4xx\0" \ + "bootfile=/tftpboot/hcu4/uImage\0" \ + "load=tftp 100000 hcu4/u-boot.bin\0" \ + "update=protect off FFFa0000 FFFFFFFF;era FFFa0000 FFFFFFFF;" \ + "cp.b 100000 FFFa0000 60000\0" \ + "upd=run load;run update\0" \ + "vx=tftp ${loadaddr} hcu4_vx_rom;" \ + "setenv bootargs emac(0,0)hcu4_vx_rom e=${ipaddr} " \ + " h=${serverip} u=dpu pw=netstal8752 tn=hcu4 f=0x3008;" \ + "bootvx ${loadaddr}\0" \ + "" +#define CONFIG_BOOTCOMMAND "run vx" + +#if 0 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#endif + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_ADDR 1 /* PHY address */ + +#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ + +#define CONFIG_HAS_ETH0 +#define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */ +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_BSP | \ + CFG_CMD_CACHE | \ + CFG_CMD_DHCP | \ + CFG_CMD_DIAG | \ + CFG_CMD_EEPROM | \ + CFG_CMD_ELF | \ + CFG_CMD_FLASH | \ + CFG_CMD_I2C | \ + CFG_CMD_IMMAP | \ + CFG_CMD_IRQ | \ + CFG_CMD_MII | \ + CFG_CMD_NET | \ + CFG_CMD_PING | \ + CFG_CMD_REGINFO | \ + CFG_CMD_SDRAM \ + ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* SPD EEPROM (sdram speed config) disabled */ +#define CONFIG_SPD_EEPROM 1 +#define SPD_EEPROM_ADDRESS 0x50 + +/*----------------------------------------------------------------------- + * Miscellaneous configurable options + *----------------------------------------------------------------------*/ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else + #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + +/*----------------------------------------------------------------------- + * External Bus Controller (EBC) Setup + */ + +/* Memory Bank 0 (Flash Bank 0) initialization */ +#define CFG_EBC_PB0AP 0x02005400 +#define CFG_EBC_PB0CR 0xFFF18000 /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit */ + +#define CFG_EBC_PB1AP 0x03041200 +#define CFG_EBC_PB1CR 0x7009A000 /* BAS=,BS=MB,BU=R/W,BW=bit */ + +#define CFG_EBC_PB2AP 0x02054500 +#define CFG_EBC_PB2CR 0x78018000 /* BAS=,BS=MB,BU=R/W,BW=bit */ + +#define CFG_EBC_PB3AP 0x01840300 +#define CFG_EBC_PB3CR 0x7c0ba000 /* BAS=,BS=MB,BU=R/W,BW=bit */ + +#define CFG_EBC_PB4AP 0x01800300 +#define CFG_EBC_PB4CR 0x7e0ba000 /* BAS=,BS=MB,BU=R/W,BW=bit */ + +#define CFG_GPIO0_TCR 0x7ffe0000 /* GPIO value */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ + + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +/* Init Memory Controller: + * + * BR0/1 and OR0/1 (FLASH) + */ + +#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */ +#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */ + + +/* Configuration Port location */ +#define CONFIG_PORT_ADDR 0xF0000500 + + + + +/*----------------------------------------------------------------------- + * Cache Configuration + *----------------------------------------------------------------------*/ +#define CFG_DCACHE_SIZE 16384 /* For IBM 405GPr CPUs */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#define CFG_HUSH_PARSER /* use "hush" command parser */ +#ifdef CFG_HUSH_PARSER + #define CFG_PROMPT_HUSH_PS2 "> " +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif +#endif /* __CONFIG_H */ -- cgit From 137fdd9f474ecb853efdace5200576308c67f18d Mon Sep 17 00:00:00 2001 From: Niklaus Giger Date: Fri, 27 Jul 2007 11:28:03 +0200 Subject: Add PPC4xx-HCU4 and HCU5 boards: HCU5 config Signed-off-by: Niklaus Giger --- include/configs/hcu5.h | 392 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 392 insertions(+) create mode 100644 include/configs/hcu5.h (limited to 'include/configs') diff --git a/include/configs/hcu5.h b/include/configs/hcu5.h new file mode 100644 index 0000000000..87f6948df0 --- /dev/null +++ b/include/configs/hcu5.h @@ -0,0 +1,392 @@ +/* + * (C) Copyright 2007 Netstal Maschinen AG + * Niklaus Giger (Niklaus.Giger@netstal.com) + * + * (C) Copyright 2006-2007 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * (C) Copyright 2006 + * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com + * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************************************ + * hcu5.h - configuration for HCU5 board (derived from sequoia.h) + ***********************************************************************/ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/*----------------------------------------------------------------------- + * High Level Configuration Options + *----------------------------------------------------------------------*/ +#define CONFIG_HCU5 1 /* Board is HCU5 */ +#define CONFIG_440EPX 1 /* Specific PPC440EPx */ +#define CONFIG_440 1 /* ... PPC440 family */ +#define CONFIG_4xx 1 /* ... PPC4xx family */ +#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ +#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ +#define CONFIG_ADD_RAM_INFO 1 /* Print additional info */ + +/*----------------------------------------------------------------------- + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + *----------------------------------------------------------------------*/ +#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */ +#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ + +#define CFG_BOOT_BASE_ADDR 0xfff00000 +#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ +#define CFG_FLASH_BASE 0xfff80000 /* start of FLASH */ +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_OCM_BASE 0xe0010000 /* ocm */ +#define CFG_PCI_BASE 0xe0000000 /* Internal PCI regs */ +#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */ +#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000 +#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000 +#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000 + +/* Don't change either of these */ +#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals */ + +#define CFG_USB2D0_BASE 0xe0000100 +#define CFG_USB_DEVICE 0xe0000000 +#define CFG_USB_HOST 0xe0000400 + +/*----------------------------------------------------------------------- + * Initial RAM & stack pointer + *----------------------------------------------------------------------*/ +/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */ +#define CFG_INIT_RAM_OCM 1 /* OCM as init ram */ +#define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */ + +#define CFG_INIT_RAM_END (4 << 10) +#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Serial Port + *----------------------------------------------------------------------*/ +#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */ +#define CONFIG_BAUDRATE 9600 +#undef CONFIG_SERIAL_MULTI /* needed to be able to define + CONFIG_SERIAL_SOFTWARE_FIFO, but + CONFIG_SERIAL_SOFTWARE_FIFO (16) does not work */ +/* Size (bytes) of interrupt driven serial port buffer. + * Set to 0 to use polling instead of interrupts. + * Setting to 0 will also disable RTS/CTS handshaking. + */ +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#undef CONFIG_UART1_CONSOLE + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +/*----------------------------------------------------------------------- + * Environment + *----------------------------------------------------------------------*/ + +#undef CFG_ENV_IS_IN_NVRAM +#undef CFG_ENV_IS_IN_FLASH +#define CFG_ENV_IS_IN_EEPROM +#undef CFG_ENV_IS_NOWHERE + +#ifdef CFG_ENV_IS_IN_EEPROM +/* Put the environment after the SDRAM and bootstrap configuration */ +#define PROM_SIZE 2048 +#define CFG_BOOSTRAP_OPTION_OFFSET 512 +#define CFG_ENV_OFFSET (CFG_BOOSTRAP_OPTION_OFFSET + 0x10) +#define CFG_ENV_SIZE (PROM_SIZE-CFG_ENV_OFFSET) +#endif + +#ifdef CFG_ENV_IS_IN_FLASH +/* Put the environment in Flash */ +#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ +#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) +#endif + +/*----------------------------------------------------------------------- + * DDR SDRAM + *----------------------------------------------------------------------*/ +#define CFG_MBYTES_SDRAM (128) /* 128 MB or 256 MB */ +#define CFG_DDR_CACHED_ADDR 0x40000000 /* setup 2nd TLB cached here */ +#undef CONFIG_DDR_DATA_EYE /* Do not use DDR2 optimization */ +#define CONFIG_DDR_ECC 1 /* enable ECC */ + +/*----------------------------------------------------------------------- + * I2C stuff for a ATMEL AT24C16 (2kB holding ENV, we are using the + * the second internal I2C controller of the PPC440EPx + *----------------------------------------------------------------------*/ +#define CFG_SPD_BUS_NUM 1 + +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +/* This is the 7bit address of the device, not including P. */ +#define CFG_I2C_EEPROM_ADDR 0x50 +#define CFG_I2C_EEPROM_ADDR_LEN 1 + +/* The EEPROM can do 16byte ( 1 << 4 ) page writes. */ +#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 +#define CFG_EEPROM_PAGE_WRITE_BITS 4 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 +#define CFG_EEPROM_PAGE_WRITE_ENABLE +#undef CFG_I2C_MULTI_EEPROMS + + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run nfs\" to mount Linux root filesystem over NFS;"\ + "echo" + +#undef CONFIG_BOOTARGS + +/* Setup some board specific values for the default environment variables */ +#define CONFIG_HOSTNAME hcu5 +#define CONFIG_IPADDR 172.25.1.42 +#define CONFIG_ETHADDR 00:60:13:00:00:00 /* Netstal Machines AG MAC */ +#define CONFIG_OVERWRITE_ETHADDR_ONCE +#define CONFIG_SERVERIP 172.25.1.3 + +#define CFG_TFTP_LOADADDR 0x01000000 /* @16 MB */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "loadaddr=0x01000000\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ + "nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ + "bootm\0" \ + "bootfile=hcu5/uImage\0" \ + "rootpath=/home/hcu/eldk/ppc_4xxFP\0" \ + "load=tftp 100000 hcu5/u-boot.bin\0" \ + "update=protect off FFFa0000 FFFFFFFF;era FFFa0000 FFFFFFFF;" \ + "cp.b 100000 FFFa0000 60000\0" \ + "upd=run load;run update\0" \ + "vx=tftp ${loadaddr} hcu5/hcu5_vx_rom;" \ + "setenv bootargs emac(0,0)hcu5_vx_rom e=${ipaddr} " \ + " h=${serverip} u=dpu pw=netstal8752 tn=hcu5 f=0x3008;" \ + "bootvx ${loadaddr}\0" \ + "" +#define CONFIG_BOOTCOMMAND "run vx" + +#if 0 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#endif + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_M88E1111_PHY 1 +#define CONFIG_IBM_EMAC4_V4 1 +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */ + +#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ + +#define CONFIG_HAS_ETH0 +#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ + +#define CONFIG_NET_MULTI 1 +#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ +#define CONFIG_PHY1_ADDR 1 + +/* USB */ +#define CONFIG_USB_OHCI +#define CONFIG_USB_STORAGE + +/* Comment this out to enable USB 1.1 device */ +#define USB_2_0_DEVICE + +#define CMD_USB CFG_CMD_USB + +/* Partitions */ +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION +#define CONFIG_ISO_PARTITION + +// CFG_CMD_FLASH | + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_BSP | \ + CFG_CMD_DHCP | \ + CFG_CMD_DIAG | \ + CFG_CMD_EEPROM | \ + CFG_CMD_ELF | \ + CFG_CMD_FAT | \ + CFG_CMD_I2C | \ + CFG_CMD_IMMAP | \ + CFG_CMD_IRQ | \ + CFG_CMD_MII | \ + CFG_CMD_NET | \ + CFG_CMD_NFS | \ + CFG_CMD_PCI | \ + CFG_CMD_PING | \ + CFG_CMD_REGINFO | \ + CFG_CMD_SDRAM | \ + CMD_USB) + +#define CONFIG_SUPPORT_VFAT + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/*----------------------------------------------------------------------- + * Miscellaneous configurable options + *----------------------------------------------------------------------*/ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------*/ +/* General PCI */ +#define CONFIG_PCI /* include pci support */ +#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/ + +/* Board-specific PCI */ +#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ +#define CFG_PCI_TARGET_INIT +#define CFG_PCI_MASTER_INIT + +#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ +#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * External Bus Controller (EBC) Setup + *----------------------------------------------------------------------*/ +#define CFG_FLASH CFG_FLASH_BASE +#define CFG_CS_1 0xC8000000 /* CAN */ +#define CFG_CS_2 0xCC000000 /* CPLD and IMC-Bus Standard */ +#define CFG_CPLD CFG_CS_2 +#define CFG_CS_3 0xCD000000 /* CPLD and IMC-Bus Fast */ + +/*----------------------------------------------------------------------- + * FLASH organization + * Memory Bank 0 (BOOT-FLASH) initialization + */ +#define CFG_BOOTFLASH_CS 0 /* Boot Flash chip connected to CSx */ +#define CFG_EBC_PB0AP 0x02005400 +#define CFG_EBC_PB0CR 0xFFF18000 /* (CFG_FLASH | 0xda000) */ +#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 32 /* max number of sectors on one chip */ + + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +/* Memory Bank 1 CAN-Chips initialization */ +#define CFG_EBC_PB1AP 0x02054500 +#define CFG_EBC_PB1CR 0xC8018000 + +/* Memory Bank 2 CPLD/IMC-Bus standard initialization */ +#define CFG_EBC_PB2AP 0x01840300 +#define CFG_EBC_PB2CR 0xCC0BA000 + +/* Memory Bank 3 IMC-Bus fast mode initialization */ +#define CFG_EBC_PB3AP 0x01800300 +#define CFG_EBC_PB3CR 0xCE0BA000 + +/* Memory Bank 4 (not used) initialization */ +#undef CFG_EBC_PB4AP +#undef CFG_EBC_PB4CR + +/* Memory Bank 5 (not used) initialization */ +#undef CFG_EBC_PB5AP +#undef CFG_EBC_PB5CR + +#define HCU_CPLD_VERSION_REGISTER ( CFG_CPLD + 0x0F00000 ) +#define HCU_HW_VERSION_REGISTER ( CFG_CPLD + 0x1400000 ) + +/*----------------------------------------------------------------------- + * Cache Configuration + *----------------------------------------------------------------------*/ +#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#define CFG_HUSH_PARSER /* use "hush" command parser */ +#ifdef CFG_HUSH_PARSER + #define CFG_PROMPT_HUSH_PS2 "> " +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif +#endif /* __CONFIG_H */ + -- cgit From 35d22f957a85a22bb3cd1ad084fa5404620d1c42 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 10 Aug 2007 10:42:25 +0200 Subject: Coding style cleanup Signed-off-by: Stefan Roese --- include/configs/hcu4.h | 4 +--- include/configs/hcu5.h | 4 ---- 2 files changed, 1 insertion(+), 7 deletions(-) (limited to 'include/configs') diff --git a/include/configs/hcu4.h b/include/configs/hcu4.h index 8779db9afe..9e45e903d2 100644 --- a/include/configs/hcu4.h +++ b/include/configs/hcu4.h @@ -312,8 +312,6 @@ #define CONFIG_PORT_ADDR 0xF0000500 - - /*----------------------------------------------------------------------- * Cache Configuration *----------------------------------------------------------------------*/ @@ -333,7 +331,7 @@ #define CFG_HUSH_PARSER /* use "hush" command parser */ #ifdef CFG_HUSH_PARSER - #define CFG_PROMPT_HUSH_PS2 "> " +#define CFG_PROMPT_HUSH_PS2 "> " #endif #if (CONFIG_COMMANDS & CFG_CMD_KGDB) diff --git a/include/configs/hcu5.h b/include/configs/hcu5.h index 87f6948df0..fa6ca37534 100644 --- a/include/configs/hcu5.h +++ b/include/configs/hcu5.h @@ -236,8 +236,6 @@ #define CONFIG_DOS_PARTITION #define CONFIG_ISO_PARTITION -// CFG_CMD_FLASH | - #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ CFG_CMD_ASKENV | \ CFG_CMD_BSP | \ @@ -301,7 +299,6 @@ #define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/ /* Board-specific PCI */ -#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ #define CFG_PCI_TARGET_INIT #define CFG_PCI_MASTER_INIT @@ -389,4 +386,3 @@ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif #endif /* __CONFIG_H */ - -- cgit From 779e975117a75e91fcebe226a63104dbfb924ab1 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Tue, 14 Aug 2007 14:44:41 +0200 Subject: ppc4xx: Add initial Zeus (PPC405EP) board support Signed-off-by: Stefan Roese --- include/configs/zeus.h | 375 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 375 insertions(+) create mode 100644 include/configs/zeus.h (limited to 'include/configs') diff --git a/include/configs/zeus.h b/include/configs/zeus.h new file mode 100644 index 0000000000..86a16e77a5 --- /dev/null +++ b/include/configs/zeus.h @@ -0,0 +1,375 @@ +/* + * (C) Copyright 2007 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************************************ + * zeus.h - configuration for Zeus board + ***********************************************************************/ +#ifndef __CONFIG_H +#define __CONFIG_H + +/*----------------------------------------------------------------------- + * High Level Configuration Options + *----------------------------------------------------------------------*/ +#define CONFIG_ZEUS 1 /* Board is Zeus */ +#define CONFIG_4xx 1 /* ... PPC4xx family */ +#define CONFIG_405EP 1 /* Specifc 405EP support*/ + +#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ +#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ + +#define PLLMR0_DEFAULT PLLMR0_333_111_55_111 +#define PLLMR1_DEFAULT PLLMR1_333_111_55_111 + +#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ + +#define CONFIG_OVERWRITE_ETHADDR_ONCE 1 + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_ADDR 0x01 /* PHY address */ +#define CONFIG_HAS_ETH1 1 +#define CONFIG_PHY1_ADDR 0x11 /* EMAC1 PHY address */ +#define CONFIG_NET_MULTI 1 +#define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */ +#define CONFIG_PHY_RESET 1 +#define CONFIG_PHY_RESET_DELAY 300 /* PHY RESET recovery delay */ + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_CACHE | \ + CFG_CMD_DHCP | \ + CFG_CMD_DIAG | \ + CFG_CMD_EEPROM | \ + CFG_CMD_ELF | \ + CFG_CMD_I2C | \ + CFG_CMD_IRQ | \ + CFG_CMD_LOG | \ + CFG_CMD_MII | \ + CFG_CMD_NET | \ + CFG_CMD_NFS | \ + CFG_CMD_PING | \ + CFG_CMD_REGINFO) + +/* POST support */ +#define CONFIG_POST (CFG_POST_MEMORY | \ + CFG_POST_CPU | \ + CFG_POST_CACHE | \ + CFG_POST_UART | \ + CFG_POST_ETHER) + +#define CFG_POST_ETHER_EXT_LOOPBACK /* eth POST using ext loopack connector */ + +/* Define here the base-addresses of the UARTs to test in POST */ +#define CFG_POST_UART_TABLE {UART0_BASE} + +#define CONFIG_LOGBUFFER +#define CFG_POST_CACHE_ADDR 0x00800000 /* free virtual address */ + +#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */ + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/*----------------------------------------------------------------------- + * SDRAM + *----------------------------------------------------------------------*/ +/* + * SDRAM configuration (please see cpu/ppc/sdram.[ch]) + */ +#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ +#define CONFIG_SDRAM_BANK1 1 /* init onboard SDRAM bank 1 */ + +/* SDRAM timings used in datasheet */ +#define CFG_SDRAM_CL 3 /* CAS latency */ +#define CFG_SDRAM_tRP 20 /* PRECHARGE command period */ +#define CFG_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE command period */ +#define CFG_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */ +#define CFG_SDRAM_tRFC 66 /* Auto refresh period */ + +/*----------------------------------------------------------------------- + * Serial Port + *----------------------------------------------------------------------*/ +#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */ +#define CFG_BASE_BAUD 691200 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SERIAL_MULTI + +/* The following table includes the supported baudrates */ +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} + +/*----------------------------------------------------------------------- + * Miscellaneous configurable options + *----------------------------------------------------------------------*/ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + +/*----------------------------------------------------------------------- + * I2C + *----------------------------------------------------------------------*/ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +/* these are for the ST M24C02 2kbit serial i2c eeprom */ +#define CFG_I2C_EEPROM_ADDR 0x50 /* base address */ +#define CFG_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */ +/* mask of address bits that overflow into the "EEPROM chip address" */ +#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 + +#define CFG_EEPROM_PAGE_WRITE_ENABLE 1 /* write eeprom in pages */ +#define CFG_EEPROM_PAGE_WRITE_BITS 3 /* 8 byte write page size */ +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ + +/* + * The layout of the I2C EEPROM, used for bootstrap setup and for board- + * specific values, like ethaddr... that can be restored via the sw-reset + * button + */ +#define FACTORY_RESET_I2C_EEPROM 0x50 +#define FACTORY_RESET_ENV_OFFS 0x80 +#define FACTORY_RESET_ENV_SIZE 0x80 + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0xFF000000 +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ +#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN) + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_FLASH_CFI /* The flash is CFI compatible */ +#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ + +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } + +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ +#define CFG_FLASH_PROTECTION 1 /* use hardware flash protection */ + +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ +#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */ + +#ifdef CFG_ENV_IS_IN_FLASH +#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ +#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) +#endif + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 16384 /* For IBM 405EP CPU */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in data cache) + */ +/* use on chip memory (OCM) for temperary stack until sdram is tested */ +#define CFG_TEMP_STACK_OCM 1 + +/* On Chip Memory location */ +#define CFG_OCM_DATA_ADDR 0xF8000000 +#define CFG_OCM_DATA_SIZE 0x1000 +#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of OCM */ +#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ + +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +/* reserve some memory for POST and BOOT limit info */ +#define CFG_INIT_SP_OFFSET (CFG_GBL_DATA_OFFSET - 16) + +/* extra data in OCM */ +#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 4) +#define CFG_POST_MAGIC (CFG_OCM_DATA_ADDR + CFG_GBL_DATA_OFFSET - 8) +#define CFG_POST_VAL (CFG_OCM_DATA_ADDR + CFG_GBL_DATA_OFFSET - 12) + +/*----------------------------------------------------------------------- + * External Bus Controller (EBC) Setup + */ + +/* Memory Bank 0 (Flash 16M) initialization */ +#define CFG_EBC_PB0AP 0x05815600 +#define CFG_EBC_PB0CR 0xFF09A000 /* BAS=0xFF0,BS=16MB,BU=R/W,BW=16bit */ + +/*----------------------------------------------------------------------- + * Definitions for GPIO setup (PPC405EP specific) + * + * GPIO0[0] - External Bus Controller BLAST output + * GPIO0[1-9] - Instruction trace outputs + * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs + * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs + * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs + * GPIO0[24-27] - UART0 control signal inputs/outputs + * GPIO0[28-29] - UART1 data signal input/output + * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs + */ +#define CFG_GPIO0_OSRH 0x15555550 /* Chip selects */ +#define CFG_GPIO0_OSRL 0x00000110 /* UART_DTR-pin 27 alt out */ +#define CFG_GPIO0_ISR1H 0x10000041 /* Pin 2, 12 is input */ +#define CFG_GPIO0_ISR1L 0x15505440 /* OUT: LEDs 22/23; IN: pin12,2, NVALID# */ +#define CFG_GPIO0_TSRH 0x00000000 +#define CFG_GPIO0_TSRL 0x00000000 +#define CFG_GPIO0_TCR 0xBFF68317 /* 3-state OUT: 22/23/29; 12,2 is not 3-state */ +#define CFG_GPIO0_ODR 0x00000000 + +#define CFG_GPIO_SW_RESET 1 +#define CFG_GPIO_ZEUS_PE 12 +#define CFG_GPIO_LED_RED 22 +#define CFG_GPIO_LED_GREEN 23 + +/* Time in milli-seconds */ +#define CFG_TIME_POST 5000 +#define CFG_TIME_FACTORY_RESET 10000 + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* ENVIRONMENT VARS */ + +#define CONFIG_PREBOOT "echo;echo Welcome to Bulletendpoints board v1.1;echo" +#define CONFIG_IPADDR 192.168.1.10 +#define CONFIG_SERVERIP 192.168.1.100 +#define CONFIG_GATEWAYIP 192.168.1.100 +#define CONFIG_ETHADDR 50:00:00:00:06:00 +#define CONFIG_ETH1ADDR 50:00:00:00:06:01 +#if 0 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else +#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */ +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "logversion=2\0" \ + "hostname=zeus\0" \ + "netdev=eth0\0" \ + "ethact=ppc_4xx_eth0\0" \ + "netmask=255.255.255.0\0" \ + "ramdisk_size=50000\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw" \ + " nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw" \ + " ramdisk=${ramdisk_size}\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0," \ + "${baudrate}\0" \ + "net_nfs=tftp ${kernel_mem_addr} ${file_kernel};" \ + "run nfsargs addip addtty;bootm\0" \ + "net_ram=tftp ${kernel_mem_addr} ${file_kernel};" \ + "tftp ${ramdisk_mem_addr} ${file_fs};" \ + "run ramargs addip addtty;" \ + "bootm ${kernel_mem_addr} ${ramdisk_mem_addr}\0" \ + "rootpath=/target_fs/zeus\0" \ + "kernel_fl_addr=ff000000\0" \ + "kernel_mem_addr=200000\0" \ + "ramdisk_fl_addr=ff300000\0" \ + "ramdisk_mem_addr=4000000\0" \ + "uboot_fl_addr=fffc0000\0" \ + "uboot_mem_addr=100000\0" \ + "file_uboot=/zeus/u-boot.bin\0" \ + "tftp_uboot=tftp 100000 ${file_uboot}\0" \ + "update_uboot=protect off fffc0000 ffffffff;" \ + "era fffc0000 ffffffff;cp.b 100000 fffc0000 40000;" \ + "protect on fffc0000 ffffffff\0" \ + "upd_uboot=run tftp_uboot;run update_uboot\0" \ + "file_kernel=/zeus/uImage_ba\0" \ + "tftp_kernel=tftp 100000 ${file_kernel}\0" \ + "update_kernel=protect off ff000000 ff17ffff;" \ + "era ff000000 ff17ffff;cp.b 100000 ff000000 180000\0" \ + "upd_kernel=run tftp_kernel;run update_kernel\0" \ + "file_fs=/zeus/rootfs_ba.img\0" \ + "tftp_fs=tftp 100000 ${file_fs}\0" \ + "update_fs=protect off ff300000 ff87ffff;era ff300000 ff87ffff;"\ + "cp.b 100000 ff300000 580000\0" \ + "upd_fs=run tftp_fs;run update_fs\0" \ + "bootcmd=chkreset;run ramargs addip addtty addmisc;" \ + "bootm ${kernel_fl_addr} ${ramdisk_fl_addr}\0" \ + "" + +#endif /* __CONFIG_H */ -- cgit