From 73ccb3410a0785593cda7aee455dfc51f790e281 Mon Sep 17 00:00:00 2001 From: Gary Jennejohn Date: Mon, 28 Apr 2008 14:04:32 +0200 Subject: ppc4xx: Add the Harris QUAD100HD AMCC 405EP-based board Signed-off-by: Gary Jennejohn Signed-off-by: Stefan Roese --- include/configs/quad100hd.h | 293 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 293 insertions(+) create mode 100644 include/configs/quad100hd.h (limited to 'include/configs') diff --git a/include/configs/quad100hd.h b/include/configs/quad100hd.h new file mode 100644 index 0000000000..00f80e4316 --- /dev/null +++ b/include/configs/quad100hd.h @@ -0,0 +1,293 @@ +/* + * (C) Copyright 2008 + * Gary Jennejohn, DENX Software Engineering GmbH, garyj@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************************************ + * quad100hd.h - configuration for Quad100hd board + ***********************************************************************/ +#ifndef __CONFIG_H +#define __CONFIG_H + +/*----------------------------------------------------------------------- + * High Level Configuration Options + *----------------------------------------------------------------------*/ +#define CONFIG_QUAD100HD 1 /* Board is Quad100hd */ +#define CONFIG_4xx 1 /* ... PPC4xx family */ +#define CONFIG_405EP 1 /* Specifc 405EP support*/ + +#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ + +#define PLLMR0_DEFAULT PLLMR0_266_133_66 /* no PCI */ +#define PLLMR1_DEFAULT PLLMR1_266_133_66 /* no PCI */ + +#define CFG_ENV_IS_IN_EEPROM 1 /* use the EEPROM for environment vars */ + +#define CONFIG_NET_MULTI 1 +#define CONFIG_HAS_ETH1 1 +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_ADDR 0x01 /* PHY address */ +#define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */ +#define CONFIG_PHY_RESET 1 +#define CONFIG_PHY_RESET_DELAY 300 /* PHY RESET recovery delay */ + +/* + * Command line configuration. + */ +#include + +#undef CONFIG_CMD_ASKENV +#undef CONFIG_CMD_CACHE +#define CONFIG_CMD_DHCP +#undef CONFIG_CMD_DIAG +#define CONFIG_CMD_EEPROM +#undef CONFIG_CMD_ELF +#define CONFIG_CMD_I2C +#undef CONFIG_CMD_IRQ +#define CONFIG_CMD_JFFS2 +#undef CONFIG_CMD_LOG +#undef CONFIG_CMD_MII +#define CONFIG_CMD_NAND +#undef CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/*----------------------------------------------------------------------- + * SDRAM + *----------------------------------------------------------------------*/ +/* + * SDRAM configuration (please see cpu/ppc/sdram.[ch]) + */ +#define CONFIG_SDRAM_BANK0 1 +#define CFG_SDRAM_SIZE 0x02000000 /* 32 MB */ + +/* FIX! SDRAM timings used in datasheet */ +#define CFG_SDRAM_CL 3 /* CAS latency */ +#define CFG_SDRAM_tRP 20 /* PRECHARGE command period */ +#define CFG_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE command period */ +#define CFG_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */ +#define CFG_SDRAM_tRFC 66 /* Auto refresh period */ + +/* + * JFFS2 + */ +#define CFG_JFFS2_FIRST_BANK 0 +#ifdef CFG_KERNEL_IN_JFFS2 +#define CFG_JFFS2_FIRST_SECTOR 0 /* JFFS starts at block 0 */ +#else /* kernel not in JFFS */ +#define CFG_JFFS2_FIRST_SECTOR 8 /* block 0-7 is kernel (1MB = 8 sectors) */ +#endif +#define CFG_JFFS2_NUM_BANKS 1 + +/*----------------------------------------------------------------------- + * Serial Port + *----------------------------------------------------------------------*/ +#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */ +#define CFG_BASE_BAUD 691200 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SERIAL_MULTI + +/* The following table includes the supported baudrates */ +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} + +/*----------------------------------------------------------------------- + * Miscellaneous configurable options + *----------------------------------------------------------------------*/ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if defined(CONFIG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_info (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + +/*----------------------------------------------------------------------- + * I2C + *----------------------------------------------------------------------*/ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +#define CFG_I2C_EEPROM_ADDR 0x50 /* base address */ +#define CFG_I2C_EEPROM_ADDR_LEN 2 /* bytes of address */ + +#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* 8 byte write page size */ +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ +#define CFG_EEPROM_SIZE 0x2000 + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0xFFC00000 +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ +#define CFG_MONITOR_BASE (TEXT_BASE) + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_FLASH_CFI /* The flash is CFI compatible */ +#define CFG_FLASH_CFI_DRIVER + +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } + +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ +#define CFG_FLASH_INCREMENT 0 /* there is only one bank */ + +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ +#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */ + +#ifdef CFG_ENV_IS_IN_FLASH +#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ +#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ +#define CFG_ENV_OFFSET 0x00050000 /* Offset of Environment Sector */ +#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) +#endif + +#ifdef CFG_ENV_IS_IN_EEPROM +#define CFG_ENV_SIZE 0x400 /* Size of Environment vars */ +#define CFG_ENV_OFFSET 0x00000000 +#define CFG_ENABLE_CRC_16 1 /* Intrinsyc formatting used crc16 */ +#endif + +/* partly from PPCBoot */ +/* NAND */ +#define CONFIG_NAND +#ifdef CONFIG_NAND +#define CFG_NAND_BASE 0x60000000 +#define CFG_NAND_CS 10 /* our CS is GPIO10 */ +#define CFG_NAND_RDY 23 /* our RDY is GPIO23 */ +#define CFG_NAND_CE 24 /* our CE is GPIO24 */ +#define CFG_NAND_CLE 31 /* our CLE is GPIO31 */ +#define CFG_NAND_ALE 30 /* our ALE is GPIO30 */ +#define NAND_MAX_CHIPS 1 +#define CFG_MAX_NAND_DEVICE 1 +#endif + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in data cache) + */ +/* use on chip memory (OCM) for temperary stack until sdram is tested */ +/* see ./cpu/ppc4xx/start.S */ +#define CFG_TEMP_STACK_OCM 1 + +/* On Chip Memory location */ +#define CFG_OCM_DATA_ADDR 0xF8000000 +#define CFG_OCM_DATA_SIZE 0x1000 +#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of OCM */ +#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ + +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * External Bus Controller (EBC) Setup + * Taken from PPCBoot board/icecube/icecube.h + */ + +/* see ./cpu/ppc4xx/cpu_init.c ./cpu/ppc4xx/ndfc.c */ +#define CFG_EBC_PB0AP 0x04002480 +/* AMD NOR flash - this corresponds to FLASH_BASE so may be correct */ +#define CFG_EBC_PB0CR 0xFFC5A000 +#define CFG_EBC_PB1AP 0x04005480 +#define CFG_EBC_PB1CR 0x60018000 +#define CFG_EBC_PB2AP 0x00000000 +#define CFG_EBC_PB2CR 0x00000000 +#define CFG_EBC_PB3AP 0x00000000 +#define CFG_EBC_PB3CR 0x00000000 +#define CFG_EBC_PB4AP 0x00000000 +#define CFG_EBC_PB4CR 0x00000000 + +/*----------------------------------------------------------------------- + * Definitions for GPIO setup (PPC405EP specific) + * + * Taken in part from PPCBoot board/icecube/icecube.h + */ +/* see ./cpu/ppc4xx/cpu_init.c ./cpu/ppc4xx/start.S */ +#define CFG_GPIO0_OSRH 0x55555550 +#define CFG_GPIO0_OSRL 0x00000110 +#define CFG_GPIO0_ISR1H 0x00000000 +#define CFG_GPIO0_ISR1L 0x15555445 +#define CFG_GPIO0_TSRH 0x00000000 +#define CFG_GPIO0_TSRL 0x00000000 +#define CFG_GPIO0_TCR 0xFFFF8097 +#define CFG_GPIO0_ODR 0x00000000 + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* ENVIRONMENT VARS */ + +#define CONFIG_IPADDR 192.168.1.67 +#define CONFIG_SERVERIP 192.168.1.50 +#define CONFIG_GATEWAYIP 192.168.1.1 +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_LOADADDR 300000 +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 + +#endif /* __CONFIG_H */ -- cgit From 567fb852178dbf59529d7301620a3f3732a4b02d Mon Sep 17 00:00:00 2001 From: Stelian Pop Date: Thu, 8 May 2008 22:52:09 +0200 Subject: Fix @ -> substitution When applying the AT91CAP9 patches upstream, something transformed the '@' character into the ' ' sequence. The patch below restores the original form in all the places where it has been modified (the AT91CAP9 files, the AT91SAM9260 files which were copied from AT91CAP9, and a couple of other files where the ' ' sequence was present). Signed-off-by: Stelian Pop Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- include/configs/at91cap9adk.h | 2 +- include/configs/at91sam9260ek.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'include/configs') diff --git a/include/configs/at91cap9adk.h b/include/configs/at91cap9adk.h index dab21d0c0a..c891fa80ed 100644 --- a/include/configs/at91cap9adk.h +++ b/include/configs/at91cap9adk.h @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop leadtechdesign.com> + * Stelian Pop * Lead Tech Design * * Configuation settings for the AT91CAP9ADK board. diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h index 96d1b8dff3..41c418f9ab 100644 --- a/include/configs/at91sam9260ek.h +++ b/include/configs/at91sam9260ek.h @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop leadtechdesign.com> + * Stelian Pop * Lead Tech Design * * Configuation settings for the AT91SAM9260EK board. -- cgit From 1c90df3e148ce0a3e2c86c63b38b19d47772f2a0 Mon Sep 17 00:00:00 2001 From: Stelian Pop Date: Thu, 8 May 2008 20:52:14 +0200 Subject: AT91CAP9ADK: Handle 8 or 16 bit NAND The Atmel boards can handle 8 or 16 bit NAND memories. This patch makes the support configurable in the board config header file (CFG_NAND_DBW_8 or CFG_NAND_DBW_16). Signed-off-by: Stelian Pop Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- include/configs/at91cap9adk.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/configs') diff --git a/include/configs/at91cap9adk.h b/include/configs/at91cap9adk.h index c891fa80ed..7887b36db0 100644 --- a/include/configs/at91cap9adk.h +++ b/include/configs/at91cap9adk.h @@ -110,6 +110,7 @@ #define NAND_MAX_CHIPS 1 #define CFG_MAX_NAND_DEVICE 1 #define CFG_NAND_BASE 0x40000000 +#define CFG_NAND_DBW_8 1 /* Ethernet */ #define CONFIG_MACB 1 -- cgit From 93da48b910511911ce110656e17ed733c8ac4c45 Mon Sep 17 00:00:00 2001 From: Stelian Pop Date: Thu, 8 May 2008 20:52:15 +0200 Subject: AT91CAP9ADK: Normalize SPI timings This patch changes the SPI timings to closely match the ones used by the Linux kernel and the Atmel's own bootstrap project. Signed-off-by: Stelian Pop Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- include/configs/at91cap9adk.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'include/configs') diff --git a/include/configs/at91cap9adk.h b/include/configs/at91cap9adk.h index 7887b36db0..588f45d623 100644 --- a/include/configs/at91cap9adk.h +++ b/include/configs/at91cap9adk.h @@ -94,9 +94,9 @@ #define CFG_SPI_WRITE_TOUT (5*CFG_HZ) #define CFG_MAX_DATAFLASH_BANKS 1 #define CFG_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ -#define AT91_SPI_CLK 20000000 -#define DATAFLASH_TCSS (0xFA << 16) -#define DATAFLASH_TCHS (0x8 << 24) +#define AT91_SPI_CLK 15000000 +#define DATAFLASH_TCSS (0x1a << 16) +#define DATAFLASH_TCHS (0x1 << 24) /* NOR flash */ #define CFG_FLASH_CFI 1 -- cgit From 3267508ec4c9e74c39ee41c9ae6951ad185fe270 Mon Sep 17 00:00:00 2001 From: Stelian Pop Date: Thu, 8 May 2008 20:52:16 +0200 Subject: AT91CAP9ADK: Normalize BOOTARGS This patch adapts CONFIG_BOOTARGS to the chosen boot method (boot from DataFlash or from NAND), and gives to Linux a fully specified mtdparts variable. Signed-off-by: Stelian Pop Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- include/configs/at91cap9adk.h | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) (limited to 'include/configs') diff --git a/include/configs/at91cap9adk.h b/include/configs/at91cap9adk.h index 588f45d623..a8f8d7d96d 100644 --- a/include/configs/at91cap9adk.h +++ b/include/configs/at91cap9adk.h @@ -56,8 +56,6 @@ #define CONFIG_USART3 1 /* USART 3 is DBGU */ #define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ - "root=/dev/mtdblock1 rw rootfstype=jffs2" /* #define CONFIG_ENV_OVERWRITE 1 */ @@ -145,6 +143,11 @@ #define CFG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CFG_ENV_OFFSET) #define CFG_ENV_SIZE 0x4200 #define CONFIG_BOOTCOMMAND "cp.b 0xC003DE00 0x72000000 0x200040; bootm" +#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ + "root=/dev/mtdblock1 " \ + "mtdparts=physmap-flash.0:-(nor);" \ + "at91_nand:-(root) " \ + "rw rootfstype=jffs2" #else @@ -155,6 +158,12 @@ #define CFG_ENV_ADDR (PHYS_FLASH_1 + CFG_ENV_OFFSET) #define CFG_ENV_SIZE 0x4000 #define CONFIG_BOOTCOMMAND "cp.b 0x10040000 0x72000000 0x200000; bootm" +#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ + "root=/dev/mtdblock4 " \ + "mtdparts=physmap-flash.0:16k(bootstrap)ro,"\ + "16k(env),224k(uboot)ro,-(linux);" \ + "at91_nand:-(root) " \ + "rw rootfstype=jffs2" #endif -- cgit From ab52640fc01624e208424e527af0b7b3a5a65a12 Mon Sep 17 00:00:00 2001 From: Stelian Pop Date: Thu, 8 May 2008 20:52:17 +0200 Subject: AT91CAP9ADK: Fix dataflash offsets in CONFIG_BOOTCOMMAND This patch fixes the dataflash offsets used in CONFIG_BOOTCOMMAND in order to cope with the changes in DataFlash partitionning scheme (cset c3a60cb3). Signed-off-by: Stelian Pop Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- include/configs/at91cap9adk.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include/configs') diff --git a/include/configs/at91cap9adk.h b/include/configs/at91cap9adk.h index a8f8d7d96d..5e13309614 100644 --- a/include/configs/at91cap9adk.h +++ b/include/configs/at91cap9adk.h @@ -142,7 +142,7 @@ #define CFG_ENV_OFFSET 0x4200 #define CFG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CFG_ENV_OFFSET) #define CFG_ENV_SIZE 0x4200 -#define CONFIG_BOOTCOMMAND "cp.b 0xC003DE00 0x72000000 0x200040; bootm" +#define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x72000000 0x210000; bootm" #define CONFIG_BOOTARGS "console=ttyS0,115200 " \ "root=/dev/mtdblock1 " \ "mtdparts=physmap-flash.0:-(nor);" \ -- cgit From c1212b2f5c5ed440bf8e9ebc8e4fd7488858b935 Mon Sep 17 00:00:00 2001 From: Stelian Pop Date: Thu, 8 May 2008 20:52:18 +0200 Subject: AT91SAM9260EK: Handle 8 or 16 bit NAND The Atmel boards can handle 8 or 16 bit NAND memories. This patch makes the support configurable in the board config header file (CFG_NAND_DBW_8 or CFG_NAND_DBW_16). Signed-off-by: Stelian Pop Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- include/configs/at91sam9260ek.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/configs') diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h index 41c418f9ab..784b9e5e63 100644 --- a/include/configs/at91sam9260ek.h +++ b/include/configs/at91sam9260ek.h @@ -104,6 +104,7 @@ #define NAND_MAX_CHIPS 1 #define CFG_MAX_NAND_DEVICE 1 #define CFG_NAND_BASE 0x40000000 +#define CFG_NAND_DBW_8 1 /* NOR flash - no real flash on this board */ #define CFG_NO_FLASH 1 -- cgit From 79f0cb6e9c54d31a1d9e3f5e226a9bebc3c3a47a Mon Sep 17 00:00:00 2001 From: Stelian Pop Date: Thu, 8 May 2008 20:52:19 +0200 Subject: AT91SAM9260EK: Normalize SPI timings This patch changes the SPI timings to closely match the ones used by the Linux kernel and the Atmel's own bootstrap project. Signed-off-by: Stelian Pop Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- include/configs/at91sam9260ek.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include/configs') diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h index 784b9e5e63..1aa40efa3d 100644 --- a/include/configs/at91sam9260ek.h +++ b/include/configs/at91sam9260ek.h @@ -96,7 +96,7 @@ #define CFG_MAX_DATAFLASH_BANKS 2 #define CFG_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ #define CFG_DATAFLASH_LOGIC_ADDR_CS1 0xD0000000 /* CS1 */ -#define AT91_SPI_CLK 33000000 +#define AT91_SPI_CLK 15000000 #define DATAFLASH_TCSS (0x1a << 16) #define DATAFLASH_TCHS (0x1 << 24) -- cgit From 96996ac25d5222611a8888968db6e53a6d3726da Mon Sep 17 00:00:00 2001 From: Stelian Pop Date: Thu, 8 May 2008 20:52:20 +0200 Subject: AT91SAM9260EK: Normalize BOOTARGS This patch adapts CONFIG_BOOTARGS to the chosen boot method (boot from DataFlash or from NAND), and gives to Linux a fully specified mtdparts variable. Signed-off-by: Stelian Pop Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- include/configs/at91sam9260ek.h | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) (limited to 'include/configs') diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h index 1aa40efa3d..cd5f161cbc 100644 --- a/include/configs/at91sam9260ek.h +++ b/include/configs/at91sam9260ek.h @@ -56,8 +56,6 @@ #define CONFIG_USART3 1 /* USART 3 is DBGU */ #define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ - "root=/dev/mtdblock0 rw rootfstype=jffs2" /* #define CONFIG_ENV_OVERWRITE 1 */ @@ -144,6 +142,10 @@ #define CFG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CFG_ENV_OFFSET) #define CFG_ENV_SIZE 0x4200 #define CONFIG_BOOTCOMMAND "cp.b 0xC003DE00 0x22000000 0x200040; bootm" +#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ + "root=/dev/mtdblock0 " \ + "mtdparts=at91_nand:-(root) " \ + "rw rootfstype=jffs2" #elif CFG_USE_DATAFLASH_CS1 @@ -154,6 +156,10 @@ #define CFG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS1 + CFG_ENV_OFFSET) #define CFG_ENV_SIZE 0x4200 #define CONFIG_BOOTCOMMAND "cp.b 0xD003DE00 0x22000000 0x200040; bootm" +#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ + "root=/dev/mtdblock0 " \ + "mtdparts=at91_nand:-(root) " \ + "rw rootfstype=jffs2" #else /* CFG_USE_NANDFLASH */ @@ -163,6 +169,12 @@ #define CFG_ENV_OFFSET_REDUND 0x80000 #define CFG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ #define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm" +#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ + "root=/dev/mtdblock5 " \ + "mtdparts=at91_nand:128k(bootstrap)ro," \ + "256k(uboot)ro,128k(env1)ro," \ + "128k(env2)ro,2M(linux),-(root) " \ + "rw rootfstype=jffs2" #endif -- cgit From 86c8c8a414988c50104a3b02c29f50af2be738c0 Mon Sep 17 00:00:00 2001 From: Stelian Pop Date: Thu, 8 May 2008 20:52:21 +0200 Subject: AT91SAM9260EK: Fix dataflash offsets in CONFIG_BOOTCOMMAND This patch fixes the dataflash offsets used in CONFIG_BOOTCOMMAND in order to cope with the changes in DataFlash partitionning scheme (cset c3a60cb3). Signed-off-by: Stelian Pop Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- include/configs/at91sam9260ek.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'include/configs') diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h index cd5f161cbc..f68e055008 100644 --- a/include/configs/at91sam9260ek.h +++ b/include/configs/at91sam9260ek.h @@ -141,7 +141,7 @@ #define CFG_ENV_OFFSET 0x4200 #define CFG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CFG_ENV_OFFSET) #define CFG_ENV_SIZE 0x4200 -#define CONFIG_BOOTCOMMAND "cp.b 0xC003DE00 0x22000000 0x200040; bootm" +#define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x22000000 0x210000; bootm" #define CONFIG_BOOTARGS "console=ttyS0,115200 " \ "root=/dev/mtdblock0 " \ "mtdparts=at91_nand:-(root) " \ @@ -155,7 +155,7 @@ #define CFG_ENV_OFFSET 0x4200 #define CFG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS1 + CFG_ENV_OFFSET) #define CFG_ENV_SIZE 0x4200 -#define CONFIG_BOOTCOMMAND "cp.b 0xD003DE00 0x22000000 0x200040; bootm" +#define CONFIG_BOOTCOMMAND "cp.b 0xD0042000 0x22000000 0x210000; bootm" #define CONFIG_BOOTARGS "console=ttyS0,115200 " \ "root=/dev/mtdblock0 " \ "mtdparts=at91_nand:-(root) " \ -- cgit From d99a8ff66d8ae87e5c87590ed2e4ead629540607 Mon Sep 17 00:00:00 2001 From: Stelian Pop Date: Thu, 8 May 2008 20:52:22 +0200 Subject: AT91SAM9261EK support This patch adds support for the AT91SAM9261 chip and the AT91SAM9261EK board. Signed-off-by: Stelian Pop Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- include/configs/at91sam9261ek.h | 191 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 191 insertions(+) create mode 100644 include/configs/at91sam9261ek.h (limited to 'include/configs') diff --git a/include/configs/at91sam9261ek.h b/include/configs/at91sam9261ek.h new file mode 100644 index 0000000000..96fc6afcfe --- /dev/null +++ b/include/configs/at91sam9261ek.h @@ -0,0 +1,191 @@ +/* + * (C) Copyright 2007-2008 + * Stelian Pop + * Lead Tech Design + * + * Configuation settings for the AT91SAM9261EK board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* ARM asynchronous clock */ +#define AT91_MAIN_CLOCK 198656000 /* from 18.432 MHz crystal */ +#define AT91_MASTER_CLOCK 99328000 /* peripheral = main / 2 */ +#define CFG_HZ 1000000 /* 1us resolution */ + +#define AT91_SLOW_CLOCK 32768 /* slow clock */ + +#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ +#define CONFIG_AT91SAM9261 1 /* It's an Atmel AT91SAM9261 SoC*/ +#define CONFIG_AT91SAM9261EK 1 /* on an AT91SAM9261EK Board */ +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SKIP_RELOCATE_UBOOT + +/* + * Hardware drivers + */ +#define CONFIG_ATMEL_USART 1 +#undef CONFIG_USART0 +#undef CONFIG_USART1 +#undef CONFIG_USART2 +#define CONFIG_USART3 1 /* USART 3 is DBGU */ + +#define CONFIG_BOOTDELAY 3 + +/* #define CONFIG_ENV_OVERWRITE 1 */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE 1 +#define CONFIG_BOOTP_BOOTPATH 1 +#define CONFIG_BOOTP_GATEWAY 1 +#define CONFIG_BOOTP_HOSTNAME 1 + +/* + * Command line configuration. + */ +#include +#undef CONFIG_CMD_BDI +#undef CONFIG_CMD_IMI +#undef CONFIG_CMD_AUTOSCRIPT +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_LOADS +#undef CONFIG_CMD_IMLS + +#define CONFIG_CMD_PING 1 +#define CONFIG_CMD_DHCP 1 +#define CONFIG_CMD_NAND 1 +#define CONFIG_CMD_USB 1 + +/* SDRAM */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM 0x20000000 +#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */ + +/* DataFlash */ +#define CONFIG_HAS_DATAFLASH 1 +#define CFG_SPI_WRITE_TOUT (5*CFG_HZ) +#define CFG_MAX_DATAFLASH_BANKS 2 +#define CFG_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ +#define CFG_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 /* CS3 */ +#define AT91_SPI_CLK 15000000 +#define DATAFLASH_TCSS (0x1a << 16) +#define DATAFLASH_TCHS (0x1 << 24) + +/* NAND flash */ +#define NAND_MAX_CHIPS 1 +#define CFG_MAX_NAND_DEVICE 1 +#define CFG_NAND_BASE 0x40000000 +#define CFG_NAND_DBW_8 1 + +/* NOR flash - no real flash on this board */ +#define CFG_NO_FLASH 1 + +/* Ethernet */ +#define CONFIG_DRIVER_DM9000 1 +#define CONFIG_DM9000_BASE 0x30000000 +#define DM9000_IO CONFIG_DM9000_BASE +#define DM9000_DATA (CONFIG_DM9000_BASE + 4) +#define CONFIG_DM9000_USE_16BIT 1 +#define CONFIG_NET_RETRY_COUNT 20 +#define CONFIG_RESET_PHY_R 1 + +/* USB */ +#define CONFIG_USB_OHCI_NEW 1 +#define LITTLEENDIAN 1 +#define CONFIG_DOS_PARTITION 1 +#define CFG_USB_OHCI_CPU_INIT 1 +#define CFG_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9261_UHP_BASE */ +#define CFG_USB_OHCI_SLOT_NAME "at91sam9261" +#define CFG_USB_OHCI_MAX_ROOT_PORTS 2 +#define CONFIG_USB_STORAGE 1 + +#define CFG_LOAD_ADDR 0x22000000 /* load address */ + +#define CFG_MEMTEST_START PHYS_SDRAM +#define CFG_MEMTEST_END 0x23e00000 + +#define CFG_USE_DATAFLASH_CS0 1 +#undef CFG_USE_NANDFLASH + +#ifdef CFG_USE_DATAFLASH_CS0 + +/* bootstrap + u-boot + env + linux in dataflash on CS0 */ +#define CFG_ENV_IS_IN_DATAFLASH 1 +#define CFG_MONITOR_BASE (CFG_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400) +#define CFG_ENV_OFFSET 0x4200 +#define CFG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CFG_ENV_OFFSET) +#define CFG_ENV_SIZE 0x4200 +#define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x22000000 0x210000; bootm" +#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ + "root=/dev/mtdblock0 " \ + "mtdparts=at91_nand:-(root) " \ + "rw rootfstype=jffs2" + +#else /* CFG_USE_NANDFLASH */ + +/* bootstrap + u-boot + env + linux in nandflash */ +#define CFG_ENV_IS_IN_NAND 1 +#define CFG_ENV_OFFSET 0x60000 +#define CFG_ENV_OFFSET_REDUND 0x80000 +#define CFG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ +#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm" +#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ + "root=/dev/mtdblock5 " \ + "mtdparts=at91_nand:128k(bootstrap)ro," \ + "256k(uboot)ro,128k(env1)ro," \ + "128k(env2)ro,2M(linux),-(root) " \ + "rw rootfstype=jffs2" + +#endif + +#define CONFIG_BAUDRATE 115200 +#define CFG_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } + +#define CFG_PROMPT "U-Boot> " +#define CFG_CBSIZE 256 +#define CFG_MAXARGS 16 +#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) +#define CFG_LONGHELP 1 +#define CONFIG_CMDLINE_EDITING 1 + +#define ROUND(A, B) (((A) + (B)) & ~((B) - 1)) +/* + * Size of malloc() pool + */ +#define CFG_MALLOC_LEN ROUND(3 * CFG_ENV_SIZE + 128*1024, 0x1000) +#define CFG_GBL_DATA_SIZE 128 /* 128 bytes for initial data */ + +#define CONFIG_STACKSIZE (32*1024) /* regular stack */ + +#ifdef CONFIG_USE_IRQ +#error CONFIG_USE_IRQ not supported +#endif + +#endif -- cgit From 8e429b3eee23927c1222679f6b6f53667b21595c Mon Sep 17 00:00:00 2001 From: Stelian Pop Date: Thu, 8 May 2008 18:52:23 +0200 Subject: AT91SAM9263EK support This patch adds support for the AT91SAM9263 chip and the AT91SAM9263EK board. Signed-off-by: Stelian Pop Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- include/configs/at91sam9263ek.h | 195 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 195 insertions(+) create mode 100644 include/configs/at91sam9263ek.h (limited to 'include/configs') diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h new file mode 100644 index 0000000000..d28f7d8aab --- /dev/null +++ b/include/configs/at91sam9263ek.h @@ -0,0 +1,195 @@ +/* + * (C) Copyright 2007-2008 + * Stelian Pop + * Lead Tech Design + * + * Configuation settings for the AT91SAM9263EK board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* ARM asynchronous clock */ +#define AT91_MAIN_CLOCK 199919000 /* from 16.367 MHz crystal */ +#define AT91_MASTER_CLOCK 99959500 /* peripheral = main / 2 */ +#define CFG_HZ 1000000 /* 1us resolution */ + +#define AT91_SLOW_CLOCK 32768 /* slow clock */ + +#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ +#define CONFIG_AT91SAM9263 1 /* It's an Atmel AT91SAM9263 SoC*/ +#define CONFIG_AT91SAM9263EK 1 /* on an AT91SAM9263EK Board */ +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SKIP_RELOCATE_UBOOT + +/* + * Hardware drivers + */ +#define CONFIG_ATMEL_USART 1 +#undef CONFIG_USART0 +#undef CONFIG_USART1 +#undef CONFIG_USART2 +#define CONFIG_USART3 1 /* USART 3 is DBGU */ + +#define CONFIG_BOOTDELAY 3 + +/* #define CONFIG_ENV_OVERWRITE 1 */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE 1 +#define CONFIG_BOOTP_BOOTPATH 1 +#define CONFIG_BOOTP_GATEWAY 1 +#define CONFIG_BOOTP_HOSTNAME 1 + +/* + * Command line configuration. + */ +#include +#undef CONFIG_CMD_BDI +#undef CONFIG_CMD_IMI +#undef CONFIG_CMD_AUTOSCRIPT +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_LOADS +#undef CONFIG_CMD_IMLS + +#define CONFIG_CMD_PING 1 +#define CONFIG_CMD_DHCP 1 +#define CONFIG_CMD_NAND 1 +#define CONFIG_CMD_USB 1 + +/* SDRAM */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM 0x20000000 +#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */ + +/* DataFlash */ +#define CONFIG_HAS_DATAFLASH 1 +#define CFG_SPI_WRITE_TOUT (5*CFG_HZ) +#define CFG_MAX_DATAFLASH_BANKS 1 +#define CFG_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ +#define AT91_SPI_CLK 15000000 +#define DATAFLASH_TCSS (0x1a << 16) +#define DATAFLASH_TCHS (0x1 << 24) + +/* NOR flash, if populated */ +#if 1 +#define CFG_NO_FLASH 1 +#else +#define CFG_FLASH_CFI 1 +#define CFG_FLASH_CFI_DRIVER 1 +#define PHYS_FLASH_1 0x10000000 +#define CFG_FLASH_BASE PHYS_FLASH_1 +#define CFG_MAX_FLASH_SECT 256 +#define CFG_MAX_FLASH_BANKS 1 +#endif + +/* NAND flash */ +#define NAND_MAX_CHIPS 1 +#define CFG_MAX_NAND_DEVICE 1 +#define CFG_NAND_BASE 0x40000000 +#define CFG_NAND_DBW_8 1 + +/* Ethernet */ +#define CONFIG_MACB 1 +#define CONFIG_RMII 1 +#define CONFIG_NET_MULTI 1 +#define CONFIG_NET_RETRY_COUNT 20 +#define CONFIG_RESET_PHY_R 1 + +/* USB */ +#define CONFIG_USB_OHCI_NEW 1 +#define LITTLEENDIAN 1 +#define CONFIG_DOS_PARTITION 1 +#define CFG_USB_OHCI_CPU_INIT 1 +#define CFG_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */ +#define CFG_USB_OHCI_SLOT_NAME "at91sam9263" +#define CFG_USB_OHCI_MAX_ROOT_PORTS 2 +#define CONFIG_USB_STORAGE 1 + +#define CFG_LOAD_ADDR 0x22000000 /* load address */ + +#define CFG_MEMTEST_START PHYS_SDRAM +#define CFG_MEMTEST_END 0x23e00000 + +#define CFG_USE_DATAFLASH 1 +#undef CFG_USE_NANDFLASH + +#ifdef CFG_USE_DATAFLASH + +/* bootstrap + u-boot + env + linux in dataflash on CS0 */ +#define CFG_ENV_IS_IN_DATAFLASH 1 +#define CFG_MONITOR_BASE (CFG_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400) +#define CFG_ENV_OFFSET 0x4200 +#define CFG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CFG_ENV_OFFSET) +#define CFG_ENV_SIZE 0x4200 +#define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x22000000 0x210000; bootm" +#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ + "root=/dev/mtdblock0 " \ + "mtdparts=at91_nand:-(root) "\ + "rw rootfstype=jffs2" + +#else /* CFG_USE_NANDFLASH */ + +/* bootstrap + u-boot + env + linux in nandflash */ +#define CFG_ENV_IS_IN_NAND 1 +#define CFG_ENV_OFFSET 0x60000 +#define CFG_ENV_OFFSET_REDUND 0x80000 +#define CFG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ +#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm" +#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ + "root=/dev/mtdblock5 " \ + "mtdparts=at91_nand:128k(bootstrap)ro,256k(uboot)ro,128k(env1)ro,128k(env2)ro,2M(linux),-(root) " \ + "rw rootfstype=jffs2" + +#endif + +#define CONFIG_BAUDRATE 115200 +#define CFG_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } + +#define CFG_PROMPT "U-Boot> " +#define CFG_CBSIZE 256 +#define CFG_MAXARGS 16 +#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) +#define CFG_LONGHELP 1 +#define CONFIG_CMDLINE_EDITING 1 + +#define ROUND(A, B) (((A) + (B)) & ~((B) - 1)) +/* + * Size of malloc() pool + */ +#define CFG_MALLOC_LEN ROUND(3 * CFG_ENV_SIZE + 128*1024, 0x1000) +#define CFG_GBL_DATA_SIZE 128 /* 128 bytes for initial data */ + +#define CONFIG_STACKSIZE (32*1024) /* regular stack */ + +#ifdef CONFIG_USE_IRQ +#error CONFIG_USE_IRQ not supported +#endif + +#endif -- cgit From 2118ebb44dc40f8117c94950fd95799a9ef821b2 Mon Sep 17 00:00:00 2001 From: Stelian Pop Date: Thu, 8 May 2008 18:52:25 +0200 Subject: AT91SAM9RLEK support This patch adds support for the AT91SAM9RL chip and the AT91SAM9RLEK board. Signed-off-by: Stelian Pop Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- include/configs/at91sam9rlek.h | 164 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 164 insertions(+) create mode 100644 include/configs/at91sam9rlek.h (limited to 'include/configs') diff --git a/include/configs/at91sam9rlek.h b/include/configs/at91sam9rlek.h new file mode 100644 index 0000000000..773f954ddc --- /dev/null +++ b/include/configs/at91sam9rlek.h @@ -0,0 +1,164 @@ +/* + * (C) Copyright 2007-2008 + * Stelian Pop + * Lead Tech Design + * + * Configuation settings for the AT91SAM9RLEK board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* ARM asynchronous clock */ +#define AT91_MAIN_CLOCK 200000000 /* from 12.000 MHz crystal */ +#define AT91_MASTER_CLOCK 100000000 /* peripheral = main / 2 */ +#define CFG_HZ 1000000 /* 1us resolution */ + +#define AT91_SLOW_CLOCK 32768 /* slow clock */ + +#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ +#define CONFIG_AT91SAM9RL 1 /* It's an Atmel AT91SAM9RL SoC*/ +#define CONFIG_AT91SAM9RLEK 1 /* on an AT91SAM9RLEK Board */ +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SKIP_RELOCATE_UBOOT + +/* + * Hardware drivers + */ +#define CONFIG_ATMEL_USART 1 +#undef CONFIG_USART0 +#undef CONFIG_USART1 +#undef CONFIG_USART2 +#define CONFIG_USART3 1 /* USART 3 is DBGU */ + +#define CONFIG_BOOTDELAY 3 + +/* #define CONFIG_ENV_OVERWRITE 1 */ + +/* + * Command line configuration. + */ +#include +#undef CONFIG_CMD_BDI +#undef CONFIG_CMD_IMI +#undef CONFIG_CMD_AUTOSCRIPT +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_LOADS +#undef CONFIG_CMD_IMLS +#undef CONFIG_CMD_NET +#undef CONFIG_CMD_USB + +#define CONFIG_CMD_NAND 1 + +/* SDRAM */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM 0x20000000 +#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */ + +/* DataFlash */ +#define CONFIG_HAS_DATAFLASH 1 +#define CFG_SPI_WRITE_TOUT (5*CFG_HZ) +#define CFG_MAX_DATAFLASH_BANKS 1 +#define CFG_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ +#define AT91_SPI_CLK 15000000 +#define DATAFLASH_TCSS (0x1a << 16) +#define DATAFLASH_TCHS (0x1 << 24) + +/* NOR flash - not present */ +#define CFG_NO_FLASH 1 + +/* NAND flash */ +#define NAND_MAX_CHIPS 1 +#define CFG_MAX_NAND_DEVICE 1 +#define CFG_NAND_BASE 0x40000000 +#define CFG_NAND_DBW_8 1 + +/* Ethernet - not present */ + +/* USB - not supported */ + +#define CFG_LOAD_ADDR 0x22000000 /* load address */ + +#define CFG_MEMTEST_START PHYS_SDRAM +#define CFG_MEMTEST_END 0x23e00000 + +#define CFG_USE_DATAFLASH 1 +#undef CFG_USE_NANDFLASH + +#ifdef CFG_USE_DATAFLASH + +/* bootstrap + u-boot + env + linux in dataflash on CS0 */ +#define CFG_ENV_IS_IN_DATAFLASH 1 +#define CFG_MONITOR_BASE (CFG_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400) +#define CFG_ENV_OFFSET 0x4200 +#define CFG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CFG_ENV_OFFSET) +#define CFG_ENV_SIZE 0x4200 +#define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x22000000 0x210000; bootm" +#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ + "root=/dev/mtdblock0 " \ + "mtdparts=at91_nand:-(root) "\ + "rw rootfstype=jffs2" + +#else /* CFG_USE_NANDFLASH */ + +/* bootstrap + u-boot + env + linux in nandflash */ +#define CFG_ENV_IS_IN_NAND 1 +#define CFG_ENV_OFFSET 0x60000 +#define CFG_ENV_OFFSET_REDUND 0x80000 +#define CFG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ +#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm" +#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ + "root=/dev/mtdblock5 " \ + "mtdparts=at91_nand:128k(bootstrap)ro,256k(uboot)ro,128k(env1)ro,128k(env2)ro,2M(linux),-(root) " \ + "rw rootfstype=jffs2" + +#endif + +#define CONFIG_BAUDRATE 115200 +#define CFG_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } + +#define CFG_PROMPT "U-Boot> " +#define CFG_CBSIZE 256 +#define CFG_MAXARGS 16 +#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) +#define CFG_LONGHELP 1 +#define CONFIG_CMDLINE_EDITING 1 + +#define ROUND(A, B) (((A) + (B)) & ~((B) - 1)) +/* + * Size of malloc() pool + */ +#define CFG_MALLOC_LEN ROUND(3 * CFG_ENV_SIZE + 128*1024, 0x1000) +#define CFG_GBL_DATA_SIZE 128 /* 128 bytes for initial data */ + +#define CONFIG_STACKSIZE (32*1024) /* regular stack */ + +#ifdef CONFIG_USE_IRQ +#error CONFIG_USE_IRQ not supported +#endif + +#endif -- cgit From c139b17d20c8371c1e0a8d7fb27c11050cf86304 Mon Sep 17 00:00:00 2001 From: Stelian Pop Date: Thu, 8 May 2008 14:52:29 +0200 Subject: AT91CAP9ADK: hook up the ATMEL LCD driver This patch makes the necessary adaptations (PIO configurations and defines in config header file) to hook up the Atmel LCD driver to the AT91CAP9ADK board. Signed-off-by: Stelian Pop Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- include/configs/at91cap9adk.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'include/configs') diff --git a/include/configs/at91cap9adk.h b/include/configs/at91cap9adk.h index 5e13309614..03c0e589f6 100644 --- a/include/configs/at91cap9adk.h +++ b/include/configs/at91cap9adk.h @@ -28,6 +28,7 @@ #define __CONFIG_H /* ARM asynchronous clock */ +#define AT91_CPU_NAME "AT91CAP9" #define AT91_MAIN_CLOCK 200000000 /* from 12 MHz crystal */ #define AT91_MASTER_CLOCK 100000000 /* peripheral = main / 2 */ #define CFG_HZ 1000000 /* 1us resolution */ @@ -55,6 +56,18 @@ #undef CONFIG_USART2 #define CONFIG_USART3 1 /* USART 3 is DBGU */ +/* LCD */ +#define CONFIG_LCD 1 +#define LCD_BPP LCD_COLOR8 +#define CONFIG_LCD_LOGO 1 +#undef LCD_TEST_PATTERN +#define CONFIG_LCD_INFO 1 +#define CONFIG_LCD_INFO_BELOW_LOGO 1 +#define CFG_WHITE_ON_BLACK 1 +#define CONFIG_ATMEL_LCD 1 +#define CONFIG_ATMEL_LCD_BGR555 1 +#define CFG_CONSOLE_IS_IN_ENV 1 + #define CONFIG_BOOTDELAY 3 /* #define CONFIG_ENV_OVERWRITE 1 */ -- cgit From 820f2a958325061a446115f3035e48e4726b3390 Mon Sep 17 00:00:00 2001 From: Stelian Pop Date: Thu, 8 May 2008 14:52:30 +0200 Subject: AT91SAM9261EK: hook up the ATMEL LCD driver This patch makes the necessary adaptations (PIO configurations and defines in config header file) to hook up the Atmel LCD driver to the AT91SAM9261EK board. Signed-off-by: Stelian Pop Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- include/configs/at91sam9261ek.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'include/configs') diff --git a/include/configs/at91sam9261ek.h b/include/configs/at91sam9261ek.h index 96fc6afcfe..df46268eb0 100644 --- a/include/configs/at91sam9261ek.h +++ b/include/configs/at91sam9261ek.h @@ -28,6 +28,7 @@ #define __CONFIG_H /* ARM asynchronous clock */ +#define AT91_CPU_NAME "AT91SAM9261" #define AT91_MAIN_CLOCK 198656000 /* from 18.432 MHz crystal */ #define AT91_MASTER_CLOCK 99328000 /* peripheral = main / 2 */ #define CFG_HZ 1000000 /* 1us resolution */ @@ -55,6 +56,18 @@ #undef CONFIG_USART2 #define CONFIG_USART3 1 /* USART 3 is DBGU */ +/* LCD */ +#define CONFIG_LCD 1 +#define LCD_BPP LCD_COLOR8 +#define CONFIG_LCD_LOGO 1 +#undef LCD_TEST_PATTERN +#define CONFIG_LCD_INFO 1 +#define CONFIG_LCD_INFO_BELOW_LOGO 1 +#define CFG_WHITE_ON_BLACK 1 +#define CONFIG_ATMEL_LCD 1 +#define CONFIG_ATMEL_LCD_BGR555 1 +#define CFG_CONSOLE_IS_IN_ENV 1 + #define CONFIG_BOOTDELAY 3 /* #define CONFIG_ENV_OVERWRITE 1 */ -- cgit From 56a2479cd7fecabdd91348a775b2801dd2e65c7f Mon Sep 17 00:00:00 2001 From: Stelian Pop Date: Thu, 8 May 2008 14:52:31 +0200 Subject: AT91SAM9263EK: hook up the ATMEL LCD driver This patch makes the necessary adaptations (PIO configurations and defines in config header file) to hook up the Atmel LCD driver to the AT91SAM9263EK board. Signed-off-by: Stelian Pop Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- include/configs/at91sam9263ek.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'include/configs') diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h index d28f7d8aab..1c50134cd5 100644 --- a/include/configs/at91sam9263ek.h +++ b/include/configs/at91sam9263ek.h @@ -28,6 +28,7 @@ #define __CONFIG_H /* ARM asynchronous clock */ +#define AT91_CPU_NAME "AT91SAM9263" #define AT91_MAIN_CLOCK 199919000 /* from 16.367 MHz crystal */ #define AT91_MASTER_CLOCK 99959500 /* peripheral = main / 2 */ #define CFG_HZ 1000000 /* 1us resolution */ @@ -55,6 +56,18 @@ #undef CONFIG_USART2 #define CONFIG_USART3 1 /* USART 3 is DBGU */ +/* LCD */ +#define CONFIG_LCD 1 +#define LCD_BPP LCD_COLOR8 +#define CONFIG_LCD_LOGO 1 +#undef LCD_TEST_PATTERN +#define CONFIG_LCD_INFO 1 +#define CONFIG_LCD_INFO_BELOW_LOGO 1 +#define CFG_WHITE_ON_BLACK 1 +#define CONFIG_ATMEL_LCD 1 +#define CONFIG_ATMEL_LCD_BGR555 1 +#define CFG_CONSOLE_IS_IN_ENV 1 + #define CONFIG_BOOTDELAY 3 /* #define CONFIG_ENV_OVERWRITE 1 */ -- cgit From 761c70b80cdd3bead40146b96a8e713d6ae01632 Mon Sep 17 00:00:00 2001 From: Stelian Pop Date: Thu, 8 May 2008 14:52:32 +0200 Subject: AT91SAM9RLEK: hook up the ATMEL LCD driver This patch makes the necessary adaptations (PIO configurations and defines in config header file) to hook up the Atmel LCD driver to the AT91SAM9RLEK board. Signed-off-by: Stelian Pop Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- include/configs/at91sam9rlek.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'include/configs') diff --git a/include/configs/at91sam9rlek.h b/include/configs/at91sam9rlek.h index 773f954ddc..33d934f08c 100644 --- a/include/configs/at91sam9rlek.h +++ b/include/configs/at91sam9rlek.h @@ -28,6 +28,7 @@ #define __CONFIG_H /* ARM asynchronous clock */ +#define AT91_CPU_NAME "AT91SAM9RL" #define AT91_MAIN_CLOCK 200000000 /* from 12.000 MHz crystal */ #define AT91_MASTER_CLOCK 100000000 /* peripheral = main / 2 */ #define CFG_HZ 1000000 /* 1us resolution */ @@ -55,6 +56,18 @@ #undef CONFIG_USART2 #define CONFIG_USART3 1 /* USART 3 is DBGU */ +/* LCD */ +#define CONFIG_LCD 1 +#define LCD_BPP LCD_COLOR8 +#define CONFIG_LCD_LOGO 1 +#undef LCD_TEST_PATTERN +#define CONFIG_LCD_INFO 1 +#define CONFIG_LCD_INFO_BELOW_LOGO 1 +#define CFG_WHITE_ON_BLACK 1 +#define CONFIG_ATMEL_LCD 1 +#define CONFIG_ATMEL_LCD_RGB565 1 +#define CFG_CONSOLE_IS_IN_ENV 1 + #define CONFIG_BOOTDELAY 3 /* #define CONFIG_ENV_OVERWRITE 1 */ -- cgit From 67e3beb52c320b0a31cf030716c99392cde2d532 Mon Sep 17 00:00:00 2001 From: Stelian Pop Date: Fri, 9 May 2008 21:46:51 +0200 Subject: AT91: Cleanup unused config header file definitions. CONFIG_ENV_OVERWRITE is commented out in the config header files, so let's cleanup the files by removing the whole definition. Signed-off-by: Stelian Pop Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- include/configs/at91cap9adk.h | 2 -- include/configs/at91sam9260ek.h | 2 -- include/configs/at91sam9261ek.h | 2 -- include/configs/at91sam9263ek.h | 2 -- include/configs/at91sam9rlek.h | 2 -- 5 files changed, 10 deletions(-) (limited to 'include/configs') diff --git a/include/configs/at91cap9adk.h b/include/configs/at91cap9adk.h index 03c0e589f6..342ce2a649 100644 --- a/include/configs/at91cap9adk.h +++ b/include/configs/at91cap9adk.h @@ -70,8 +70,6 @@ #define CONFIG_BOOTDELAY 3 -/* #define CONFIG_ENV_OVERWRITE 1 */ - /* * BOOTP options */ diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h index f68e055008..675224e0ba 100644 --- a/include/configs/at91sam9260ek.h +++ b/include/configs/at91sam9260ek.h @@ -57,8 +57,6 @@ #define CONFIG_BOOTDELAY 3 -/* #define CONFIG_ENV_OVERWRITE 1 */ - /* * BOOTP options */ diff --git a/include/configs/at91sam9261ek.h b/include/configs/at91sam9261ek.h index df46268eb0..e53a23f33f 100644 --- a/include/configs/at91sam9261ek.h +++ b/include/configs/at91sam9261ek.h @@ -70,8 +70,6 @@ #define CONFIG_BOOTDELAY 3 -/* #define CONFIG_ENV_OVERWRITE 1 */ - /* * BOOTP options */ diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h index 1c50134cd5..a8194b564d 100644 --- a/include/configs/at91sam9263ek.h +++ b/include/configs/at91sam9263ek.h @@ -70,8 +70,6 @@ #define CONFIG_BOOTDELAY 3 -/* #define CONFIG_ENV_OVERWRITE 1 */ - /* * BOOTP options */ diff --git a/include/configs/at91sam9rlek.h b/include/configs/at91sam9rlek.h index 33d934f08c..2ad8d05eb0 100644 --- a/include/configs/at91sam9rlek.h +++ b/include/configs/at91sam9rlek.h @@ -70,8 +70,6 @@ #define CONFIG_BOOTDELAY 3 -/* #define CONFIG_ENV_OVERWRITE 1 */ - /* * Command line configuration. */ -- cgit From 0c11935cd62ca1f65eeb228ff4c848440d4553bf Mon Sep 17 00:00:00 2001 From: Gary Jennejohn Date: Wed, 14 May 2008 13:39:22 +0200 Subject: ppc4xx: QUAD100HD: Allow the environment to be put into flash. After moving TEXT_BASE the value for CFG_ENV_ADDR was incorrect. Also use a redundant environment. Signed-off-by: Gary Jennejohn --- include/configs/quad100hd.h | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) (limited to 'include/configs') diff --git a/include/configs/quad100hd.h b/include/configs/quad100hd.h index 00f80e4316..622a5d4ccc 100644 --- a/include/configs/quad100hd.h +++ b/include/configs/quad100hd.h @@ -41,7 +41,9 @@ #define PLLMR0_DEFAULT PLLMR0_266_133_66 /* no PCI */ #define PLLMR1_DEFAULT PLLMR1_266_133_66 /* no PCI */ -#define CFG_ENV_IS_IN_EEPROM 1 /* use the EEPROM for environment vars */ +/* the environment is in the EEPROM by default */ +#define CFG_ENV_IS_IN_EEPROM +#undef CFG_ENV_IS_IN_FLASH #define CONFIG_NET_MULTI 1 #define CONFIG_HAS_ETH1 1 @@ -198,9 +200,12 @@ #ifdef CFG_ENV_IS_IN_FLASH #define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ -#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ -#define CFG_ENV_OFFSET 0x00050000 /* Offset of Environment Sector */ -#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) +/* the environment is located before u-boot */ +#define CFG_ENV_ADDR (TEXT_BASE - CFG_ENV_SECT_SIZE) + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR - CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SECT_SIZE) #endif #ifdef CFG_ENV_IS_IN_EEPROM -- cgit From 2c289e320dcfb3760e99cf1d765cb067194a1202 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Mon, 19 May 2008 09:47:25 -0500 Subject: mpc86xx: Removed unused and unconfigured memory test code. Besides, other common code exists. Signed-off-by: Jon Loeliger --- include/configs/MPC8610HPCD.h | 2 -- include/configs/MPC8641HPCN.h | 1 - 2 files changed, 3 deletions(-) (limited to 'include/configs') diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h index 585411c4e2..ed75357d2c 100644 --- a/include/configs/MPC8610HPCD.h +++ b/include/configs/MPC8610HPCD.h @@ -71,10 +71,8 @@ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ #define CONFIG_MISC_INIT_R 1 -#undef CFG_DRAM_TEST /* memory test, takes time */ #define CFG_MEMTEST_START 0x00200000 /* memtest region */ #define CFG_MEMTEST_END 0x00400000 -#define CFG_ALT_MEMTEST /* * Base addresses -- Note these are effective addresses where the diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index a8d0077ca3..d7a7f9087f 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -86,7 +86,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ -#undef CFG_DRAM_TEST /* memory test, takes time */ #define CFG_MEMTEST_START 0x00200000 /* memtest region */ #define CFG_MEMTEST_END 0x00400000 -- cgit From 55ac7a7490b55da56659f95d82a0c83b9756df27 Mon Sep 17 00:00:00 2001 From: David Brownell Date: Fri, 22 Feb 2008 12:54:39 -0800 Subject: avr32: stk1002 and ngw100 convergence Make STK1002 and NGW100 boards act more alike: - STK boards can use as many arguments as NGW - STK boards don't need to manage FPGAs either - NGW commands should match STK ones Also spell U-Boot right in prompts for STK1002 and NGW100. Signed-off-by: David Brownell [haavard.skinnemoen@atmel.com: update STK100[34] as well] Signed-off-by: Haavard Skinnemoen --- include/configs/atngw100.h | 5 ++++- include/configs/atstk1002.h | 6 +++--- include/configs/atstk1003.h | 2 +- include/configs/atstk1004.h | 2 +- 4 files changed, 9 insertions(+), 6 deletions(-) (limited to 'include/configs') diff --git a/include/configs/atngw100.h b/include/configs/atngw100.h index 5aad043d89..313298a5c7 100644 --- a/include/configs/atngw100.h +++ b/include/configs/atngw100.h @@ -112,8 +112,11 @@ #define CONFIG_CMD_FAT #define CONFIG_CMD_JFFS2 #define CONFIG_CMD_MMC + +#undef CONFIG_CMD_AUTOSCRIPT #undef CONFIG_CMD_FPGA #undef CONFIG_CMD_SETGETDCR +#undef CONFIG_CMD_XIMG #define CONFIG_ATMEL_USART 1 #define CONFIG_MACB 1 @@ -164,7 +167,7 @@ #define CFG_BOOTPARAMS_LEN (16 * 1024) /* Other configuration settings that shouldn't have to change all that often */ -#define CFG_PROMPT "Uboot> " +#define CFG_PROMPT "U-Boot> " #define CFG_CBSIZE 256 #define CFG_MAXARGS 16 #define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) diff --git a/include/configs/atstk1002.h b/include/configs/atstk1002.h index 95aeab6d4e..f652b28710 100644 --- a/include/configs/atstk1002.h +++ b/include/configs/atstk1002.h @@ -139,9 +139,9 @@ #define CONFIG_CMD_FAT #define CONFIG_CMD_JFFS2 #define CONFIG_CMD_MMC -#define CONFIG_CMD_REGINFO #undef CONFIG_CMD_AUTOSCRIPT +#undef CONFIG_CMD_FPGA #undef CONFIG_CMD_SETGETDCR #undef CONFIG_CMD_XIMG @@ -189,9 +189,9 @@ #define CFG_BOOTPARAMS_LEN (16 * 1024) /* Other configuration settings that shouldn't have to change all that often */ -#define CFG_PROMPT "Uboot> " +#define CFG_PROMPT "U-Boot> " #define CFG_CBSIZE 256 -#define CFG_MAXARGS 8 +#define CFG_MAXARGS 16 #define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) #define CFG_LONGHELP 1 diff --git a/include/configs/atstk1003.h b/include/configs/atstk1003.h index 194788b18d..2d981ccbad 100644 --- a/include/configs/atstk1003.h +++ b/include/configs/atstk1003.h @@ -171,7 +171,7 @@ #define CFG_BOOTPARAMS_LEN (16 * 1024) /* Other configuration settings that shouldn't have to change all that often */ -#define CFG_PROMPT "Uboot> " +#define CFG_PROMPT "U-Boot> " #define CFG_CBSIZE 256 #define CFG_MAXARGS 16 #define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) diff --git a/include/configs/atstk1004.h b/include/configs/atstk1004.h index b81fc21270..235c1cc9df 100644 --- a/include/configs/atstk1004.h +++ b/include/configs/atstk1004.h @@ -172,7 +172,7 @@ #define CFG_BOOTPARAMS_LEN (16 * 1024) /* Other configuration settings that shouldn't have to change all that often */ -#define CFG_PROMPT "Uboot> " +#define CFG_PROMPT "U-Boot> " #define CFG_CBSIZE 256 #define CFG_MAXARGS 16 #define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) -- cgit From 0a2e48792dd372c90b80059f3235e67a567e16fc Mon Sep 17 00:00:00 2001 From: Haavard Skinnemoen Date: Thu, 22 Nov 2007 12:14:11 +0100 Subject: avr32: Add support for the ATSTK1006 board This is a replacement for ATSTK1002 with 64MB SDRAM and NAND flash on board. It's currently in production and will be available soon. Signed-off-by: Haavard Skinnemoen --- include/configs/atstk1006.h | 202 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 202 insertions(+) create mode 100644 include/configs/atstk1006.h (limited to 'include/configs') diff --git a/include/configs/atstk1006.h b/include/configs/atstk1006.h new file mode 100644 index 0000000000..c606d5dcc2 --- /dev/null +++ b/include/configs/atstk1006.h @@ -0,0 +1,202 @@ +/* + * Copyright (C) 2005-2006 Atmel Corporation + * + * Configuration settings for the ATSTK1002 CPU daughterboard + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_AVR32 1 +#define CONFIG_AT32AP 1 +#define CONFIG_AT32AP7000 1 +#define CONFIG_ATSTK1006 1 +#define CONFIG_ATSTK1000 1 + +#define CONFIG_ATSTK1000_EXT_FLASH 1 + +/* + * Timer clock frequency. We're using the CPU-internal COUNT register + * for this, so this is equivalent to the CPU core clock frequency + */ +#define CFG_HZ 1000 + +/* + * Set up the PLL to run at 140 MHz, the CPU to run at the PLL + * frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the + * PLL frequency. + * (CFG_OSC0_HZ * CFG_PLL0_MUL) / CFG_PLL0_DIV = PLL MHz + */ +#define CONFIG_PLL 1 +#define CFG_POWER_MANAGER 1 +#define CFG_OSC0_HZ 20000000 +#define CFG_PLL0_DIV 1 +#define CFG_PLL0_MUL 7 +#define CFG_PLL0_SUPPRESS_CYCLES 16 +/* + * Set the CPU running at: + * PLL / (2^CFG_CLKDIV_CPU) = CPU MHz + */ +#define CFG_CLKDIV_CPU 0 +/* + * Set the HSB running at: + * PLL / (2^CFG_CLKDIV_HSB) = HSB MHz + */ +#define CFG_CLKDIV_HSB 1 +/* + * Set the PBA running at: + * PLL / (2^CFG_CLKDIV_PBA) = PBA MHz + */ +#define CFG_CLKDIV_PBA 2 +/* + * Set the PBB running at: + * PLL / (2^CFG_CLKDIV_PBB) = PBB MHz + */ +#define CFG_CLKDIV_PBB 1 + +/* + * The PLLOPT register controls the PLL like this: + * icp = PLLOPT<2> + * ivco = PLLOPT<1:0> + * + * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz). + */ +#define CFG_PLL0_OPT 0x04 + +#undef CONFIG_USART0 +#define CONFIG_USART1 1 +#undef CONFIG_USART2 +#undef CONFIG_USART3 + +/* User serviceable stuff */ +#define CONFIG_DOS_PARTITION 1 + +#define CONFIG_CMDLINE_TAG 1 +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +#define CONFIG_STACKSIZE (2048) + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_BOOTARGS \ + "console=ttyS0 root=mtd3 fbmem=2400k" + +#define CONFIG_BOOTCOMMAND \ + "fsload; bootm $(fileaddr)" + +/* + * Only interrupt autoboot if is pressed. Otherwise, garbage + * data on the serial line may interrupt the boot sequence. + */ +#define CONFIG_BOOTDELAY 1 +#define CONFIG_AUTOBOOT 1 +#define CONFIG_AUTOBOOT_KEYED 1 +#define CONFIG_AUTOBOOT_PROMPT \ + "Press SPACE to abort autoboot in %d seconds\n" +#define CONFIG_AUTOBOOT_DELAY_STR "d" +#define CONFIG_AUTOBOOT_STOP_STR " " + +/* + * After booting the board for the first time, new ethernet addresses + * should be generated and assigned to the environment variables + * "ethaddr" and "eth1addr". This is normally done during production. + */ +#define CONFIG_OVERWRITE_ETHADDR_ONCE 1 +#define CONFIG_NET_MULTI 1 + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY + + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_MMC + +#undef CONFIG_CMD_AUTOSCRIPT +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_SETGETDCR +#undef CONFIG_CMD_XIMG + +#define CONFIG_ATMEL_USART 1 +#define CONFIG_MACB 1 +#define CONFIG_PIO2 1 +#define CFG_NR_PIOS 5 +#define CFG_HSDRAMC 1 +#define CONFIG_MMC 1 + +#define CFG_DCACHE_LINESZ 32 +#define CFG_ICACHE_LINESZ 32 + +#define CONFIG_NR_DRAM_BANKS 1 + +/* External flash on STK1000 */ +#if 0 +#define CFG_FLASH_CFI 1 +#define CFG_FLASH_CFI_DRIVER 1 +#endif + +#define CFG_FLASH_BASE 0x00000000 +#define CFG_FLASH_SIZE 0x800000 +#define CFG_MAX_FLASH_BANKS 1 +#define CFG_MAX_FLASH_SECT 135 + +#define CFG_MONITOR_BASE CFG_FLASH_BASE + +#define CFG_INTRAM_BASE 0x24000000 +#define CFG_INTRAM_SIZE 0x8000 + +#define CFG_SDRAM_BASE 0x10000000 + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SIZE 65536 +#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_FLASH_SIZE - CFG_ENV_SIZE) + +#define CFG_INIT_SP_ADDR (CFG_INTRAM_BASE + CFG_INTRAM_SIZE) + +#define CFG_MALLOC_LEN (256*1024) +#define CFG_DMA_ALLOC_LEN (16384) + +/* Allow 4MB for the kernel run-time image */ +#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x00400000) +#define CFG_BOOTPARAMS_LEN (16 * 1024) + +/* Other configuration settings that shouldn't have to change all that often */ +#define CFG_PROMPT "U-Boot> " +#define CFG_CBSIZE 256 +#define CFG_MAXARGS 16 +#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) +#define CFG_LONGHELP 1 + +#define CFG_MEMTEST_START CFG_SDRAM_BASE +#define CFG_MEMTEST_END (CFG_MEMTEST_START + 0x3f00000) +#define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 } + +#endif /* __CONFIG_H */ -- cgit From a23e277c4a3a2bbc42d237aae29da3a8971e757f Mon Sep 17 00:00:00 2001 From: Haavard Skinnemoen Date: Mon, 19 May 2008 11:36:28 +0200 Subject: avr32: Rework SDRAM initialization code This cleans up the SDRAM initialization and related code a bit, and allows faster booting. * Add definitions for EBI and internal SRAM to asm/arch/memory-map.h * Remove memory test from sdram_init() and make caller responsible for verifying the SDRAM and determining its size. * Remove base_address member from struct sdram_config (was sdram_info) * Add data_bits member to struct sdram_config and kill CFG_SDRAM_16BIT * Add support for a common STK1000 hack: 16MB SDRAM instead of 8. Signed-off-by: Haavard Skinnemoen --- include/configs/atngw100.h | 21 +++++++-------------- include/configs/atstk1002.h | 13 +++++++------ include/configs/atstk1003.h | 13 +++++++------ include/configs/atstk1004.h | 14 +++++++------- include/configs/atstk1006.h | 13 +++++++------ 5 files changed, 35 insertions(+), 39 deletions(-) (limited to 'include/configs') diff --git a/include/configs/atngw100.h b/include/configs/atngw100.h index 313298a5c7..3fc9975637 100644 --- a/include/configs/atngw100.h +++ b/include/configs/atngw100.h @@ -24,6 +24,8 @@ #ifndef __CONFIG_H #define __CONFIG_H +#include + #define CONFIG_AVR32 1 #define CONFIG_AT32AP 1 #define CONFIG_AT32AP7000 1 @@ -140,11 +142,9 @@ #define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_INTRAM_BASE 0x24000000 -#define CFG_INTRAM_SIZE 0x8000 - -#define CFG_SDRAM_BASE 0x10000000 -#define CFG_SDRAM_16BIT 1 +#define CFG_INTRAM_BASE INTERNAL_SRAM_BASE +#define CFG_INTRAM_SIZE INTERNAL_SRAM_SIZE +#define CFG_SDRAM_BASE EBI_SDRAM_BASE #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_SIZE 65536 @@ -153,17 +153,10 @@ #define CFG_INIT_SP_ADDR (CFG_INTRAM_BASE + CFG_INTRAM_SIZE) #define CFG_MALLOC_LEN (256*1024) -#define CFG_MALLOC_END \ - ({ \ - DECLARE_GLOBAL_DATA_PTR; \ - CFG_SDRAM_BASE + gd->sdram_size; \ - }) -#define CFG_MALLOC_START (CFG_MALLOC_END - CFG_MALLOC_LEN) - #define CFG_DMA_ALLOC_LEN (16384) /* Allow 4MB for the kernel run-time image */ -#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x00400000) +#define CFG_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000) #define CFG_BOOTPARAMS_LEN (16 * 1024) /* Other configuration settings that shouldn't have to change all that often */ @@ -173,7 +166,7 @@ #define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) #define CFG_LONGHELP 1 -#define CFG_MEMTEST_START CFG_SDRAM_BASE +#define CFG_MEMTEST_START EBI_SDRAM_BASE #define CFG_MEMTEST_END (CFG_MEMTEST_START + 0x1f00000) #define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 } diff --git a/include/configs/atstk1002.h b/include/configs/atstk1002.h index f652b28710..ba18eb63c7 100644 --- a/include/configs/atstk1002.h +++ b/include/configs/atstk1002.h @@ -24,6 +24,8 @@ #ifndef __CONFIG_H #define __CONFIG_H +#include + #define CONFIG_AVR32 1 #define CONFIG_AT32AP 1 #define CONFIG_AT32AP7000 1 @@ -170,10 +172,9 @@ #define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_INTRAM_BASE 0x24000000 -#define CFG_INTRAM_SIZE 0x8000 - -#define CFG_SDRAM_BASE 0x10000000 +#define CFG_INTRAM_BASE INTERNAL_SRAM_BASE +#define CFG_INTRAM_SIZE INTERNAL_SRAM_SIZE +#define CFG_SDRAM_BASE EBI_SDRAM_BASE #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_SIZE 65536 @@ -185,7 +186,7 @@ #define CFG_DMA_ALLOC_LEN (16384) /* Allow 4MB for the kernel run-time image */ -#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x00400000) +#define CFG_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000) #define CFG_BOOTPARAMS_LEN (16 * 1024) /* Other configuration settings that shouldn't have to change all that often */ @@ -195,7 +196,7 @@ #define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) #define CFG_LONGHELP 1 -#define CFG_MEMTEST_START CFG_SDRAM_BASE +#define CFG_MEMTEST_START EBI_SDRAM_BASE #define CFG_MEMTEST_END (CFG_MEMTEST_START + 0x700000) #define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 } diff --git a/include/configs/atstk1003.h b/include/configs/atstk1003.h index 2d981ccbad..a528ddfb0e 100644 --- a/include/configs/atstk1003.h +++ b/include/configs/atstk1003.h @@ -24,6 +24,8 @@ #ifndef __CONFIG_H #define __CONFIG_H +#include + #define CONFIG_AVR32 1 #define CONFIG_AT32AP 1 #define CONFIG_AT32AP7001 1 @@ -153,10 +155,9 @@ #define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_INTRAM_BASE 0x24000000 -#define CFG_INTRAM_SIZE 0x8000 - -#define CFG_SDRAM_BASE 0x10000000 +#define CFG_INTRAM_BASE INTERNAL_SRAM_BASE +#define CFG_INTRAM_SIZE INTERNAL_SRAM_SIZE +#define CFG_SDRAM_BASE EBI_SDRAM_BASE #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_SIZE 65536 @@ -167,7 +168,7 @@ #define CFG_MALLOC_LEN (256*1024) /* Allow 4MB for the kernel run-time image */ -#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x00400000) +#define CFG_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000) #define CFG_BOOTPARAMS_LEN (16 * 1024) /* Other configuration settings that shouldn't have to change all that often */ @@ -177,7 +178,7 @@ #define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) #define CFG_LONGHELP 1 -#define CFG_MEMTEST_START CFG_SDRAM_BASE +#define CFG_MEMTEST_START EBI_SDRAM_BASE #define CFG_MEMTEST_END (CFG_MEMTEST_START + 0x700000) #define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 } diff --git a/include/configs/atstk1004.h b/include/configs/atstk1004.h index 235c1cc9df..fc9585e84d 100644 --- a/include/configs/atstk1004.h +++ b/include/configs/atstk1004.h @@ -24,6 +24,8 @@ #ifndef __CONFIG_H #define __CONFIG_H +#include + #define CONFIG_AVR32 1 #define CONFIG_AT32AP 1 #define CONFIG_AT32AP7002 1 @@ -153,11 +155,9 @@ #define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_INTRAM_BASE 0x24000000 -#define CFG_INTRAM_SIZE 0x8000 - -#define CFG_SDRAM_BASE 0x10000000 -#define CFG_SDRAM_16BIT 1 +#define CFG_INTRAM_BASE INTERNAL_SRAM_BASE +#define CFG_INTRAM_SIZE INTERNAL_SRAM_SIZE +#define CFG_SDRAM_BASE EBI_SDRAM_BASE #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_SIZE 65536 @@ -168,7 +168,7 @@ #define CFG_MALLOC_LEN (256*1024) /* Allow 2MB for the kernel run-time image */ -#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x00200000) +#define CFG_LOAD_ADDR (EBI_SDRAM_BASE + 0x00200000) #define CFG_BOOTPARAMS_LEN (16 * 1024) /* Other configuration settings that shouldn't have to change all that often */ @@ -178,7 +178,7 @@ #define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) #define CFG_LONGHELP 1 -#define CFG_MEMTEST_START CFG_SDRAM_BASE +#define CFG_MEMTEST_START EBI_SDRAM_BASE #define CFG_MEMTEST_END (CFG_MEMTEST_START + 0x700000) #define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 } diff --git a/include/configs/atstk1006.h b/include/configs/atstk1006.h index c606d5dcc2..9fd49a53a3 100644 --- a/include/configs/atstk1006.h +++ b/include/configs/atstk1006.h @@ -24,6 +24,8 @@ #ifndef __CONFIG_H #define __CONFIG_H +#include + #define CONFIG_AVR32 1 #define CONFIG_AT32AP 1 #define CONFIG_AT32AP7000 1 @@ -170,10 +172,9 @@ #define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_INTRAM_BASE 0x24000000 -#define CFG_INTRAM_SIZE 0x8000 - -#define CFG_SDRAM_BASE 0x10000000 +#define CFG_INTRAM_BASE INTERNAL_SRAM_BASE +#define CFG_INTRAM_SIZE INTERNAL_SRAM_SIZE +#define CFG_SDRAM_BASE EBI_SDRAM_BASE #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_SIZE 65536 @@ -185,7 +186,7 @@ #define CFG_DMA_ALLOC_LEN (16384) /* Allow 4MB for the kernel run-time image */ -#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x00400000) +#define CFG_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000) #define CFG_BOOTPARAMS_LEN (16 * 1024) /* Other configuration settings that shouldn't have to change all that often */ @@ -195,7 +196,7 @@ #define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) #define CFG_LONGHELP 1 -#define CFG_MEMTEST_START CFG_SDRAM_BASE +#define CFG_MEMTEST_START EBI_SDRAM_BASE #define CFG_MEMTEST_END (CFG_MEMTEST_START + 0x3f00000) #define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 } -- cgit From 31d826722434931e1152a09d140187dcf72f8aac Mon Sep 17 00:00:00 2001 From: Becky Bruce Date: Thu, 8 May 2008 19:02:12 -0500 Subject: PPC: Create and use CONFIG_HIGH_BATS Change all code that conditionally operates on high bat registers (that is, BATs 4-7) to look at CONFIG_HIGH_BATS instead of the myriad ways this is done now. Define the option for every config for which high bats are supported (and enabled by early boot, on parts where they're not always enabled) Signed-off-by: Becky Bruce --- include/configs/Alaska8220.h | 2 ++ include/configs/BC3450.h | 2 ++ include/configs/CPCI750.h | 2 ++ include/configs/IceCube.h | 2 ++ include/configs/MPC8313ERDB.h | 2 ++ include/configs/MPC8315ERDB.h | 1 + include/configs/MPC8323ERDB.h | 1 + include/configs/MPC832XEMDS.h | 2 ++ include/configs/MPC8349EMDS.h | 1 + include/configs/MPC8349ITX.h | 1 + include/configs/MPC8360EMDS.h | 2 ++ include/configs/MPC8360ERDK.h | 2 ++ include/configs/MPC837XEMDS.h | 1 + include/configs/MPC837XERDB.h | 2 ++ include/configs/MPC8610HPCD.h | 1 + include/configs/MPC8641HPCN.h | 1 + include/configs/PM520.h | 2 ++ include/configs/TB5200.h | 2 ++ include/configs/TOP5200.h | 2 ++ include/configs/TQM5200.h | 2 ++ include/configs/TQM834x.h | 2 ++ include/configs/Total5200.h | 2 ++ include/configs/Yukon8220.h | 2 ++ include/configs/ads5121.h | 2 ++ include/configs/aev.h | 2 ++ include/configs/canmb.h | 2 ++ include/configs/cm5200.h | 2 ++ include/configs/cpci5200.h | 2 ++ include/configs/hmi1001.h | 2 ++ include/configs/inka4x0.h | 2 ++ include/configs/jupiter.h | 2 ++ include/configs/mcc200.h | 2 ++ include/configs/mecp5200.h | 2 ++ include/configs/motionpro.h | 1 + include/configs/mpc7448hpc2.h | 2 +- include/configs/munices.h | 1 + include/configs/o2dnt.h | 2 ++ include/configs/p3mx.h | 1 + include/configs/pf5200.h | 1 + include/configs/sbc8349.h | 2 ++ include/configs/smmaco4.h | 2 ++ include/configs/sorcery.h | 2 ++ include/configs/spieval.h | 2 ++ include/configs/uc101.h | 2 ++ include/configs/v38b.h | 2 ++ 45 files changed, 78 insertions(+), 1 deletion(-) (limited to 'include/configs') diff --git a/include/configs/Alaska8220.h b/include/configs/Alaska8220.h index 3f2f6140f6..38b962f823 100644 --- a/include/configs/Alaska8220.h +++ b/include/configs/Alaska8220.h @@ -31,6 +31,8 @@ #define CONFIG_MPC8220 1 #define CONFIG_ALASKA8220 1 /* ... on Alaska board */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* Input clock running at 30Mhz, read Hid1 for the CPU multiplier to determine the CPU speed. */ #define CFG_MPC8220_CLKIN 30000000/* ... running at 30MHz */ diff --git a/include/configs/BC3450.h b/include/configs/BC3450.h index 706c13efad..b7574bf149 100644 --- a/include/configs/BC3450.h +++ b/include/configs/BC3450.h @@ -61,6 +61,8 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* * Serial console configuration */ diff --git a/include/configs/CPCI750.h b/include/configs/CPCI750.h index 48e29a2087..89edbde1de 100644 --- a/include/configs/CPCI750.h +++ b/include/configs/CPCI750.h @@ -61,6 +61,8 @@ #undef CONFIG_ECC /* enable ECC support */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* which initialization functions to call for this board */ #define CONFIG_MISC_INIT_R #define CONFIG_BOARD_PRE_INIT diff --git a/include/configs/IceCube.h b/include/configs/IceCube.h index f85cff7abf..3a347eac55 100644 --- a/include/configs/IceCube.h +++ b/include/configs/IceCube.h @@ -37,6 +37,8 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* * Serial console configuration */ diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h index 610151f586..d547681c3d 100644 --- a/include/configs/MPC8313ERDB.h +++ b/include/configs/MPC8313ERDB.h @@ -469,6 +469,8 @@ #define CFG_HID2 HID2_HBE +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* DDR @ 0x00000000 */ #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10) #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index e0a887c7e6..7a5d0aa1dd 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -453,6 +453,7 @@ /* * MMU Setup */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ /* DDR: cache cacheable */ #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index 32f57ac7da..977c041dca 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -468,6 +468,7 @@ /* * MMU Setup */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ /* DDR: cache cacheable */ #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index 1276a124c9..9ca2a2be04 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -483,6 +483,8 @@ * MMU Setup */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* DDR: cache cacheable */ #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 119e7ac7c6..bd77540003 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -626,6 +626,7 @@ #define CFG_HID2 HID2_HBE +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ /* DDR @ 0x00000000 */ #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index c72de03c01..38410a1764 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -555,6 +555,7 @@ boards, we say we have two, but don't display a message if we find only one. */ #define CFG_HID0_FINAL CFG_HID0_INIT #define CFG_HID2 HID2_HBE +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ /* DDR */ #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h index 983575eb0c..fcfbe6f821 100644 --- a/include/configs/MPC8360EMDS.h +++ b/include/configs/MPC8360EMDS.h @@ -515,6 +515,8 @@ * MMU Setup */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* DDR: cache cacheable */ #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) diff --git a/include/configs/MPC8360ERDK.h b/include/configs/MPC8360ERDK.h index 7b7d6f50c0..adedcb95af 100644 --- a/include/configs/MPC8360ERDK.h +++ b/include/configs/MPC8360ERDK.h @@ -419,6 +419,8 @@ * MMU Setup */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* DDR: cache cacheable */ #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index e92493ae4d..4e159a0b46 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -502,6 +502,7 @@ /* * MMU Setup */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ /* DDR: cache cacheable */ #define CFG_SDRAM_LOWER CFG_SDRAM_BASE diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index f7e6fd2c52..29c2490e6b 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -524,6 +524,8 @@ * MMU Setup */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* DDR: cache cacheable */ #define CFG_SDRAM_LOWER CFG_SDRAM_BASE #define CFG_SDRAM_UPPER (CFG_SDRAM_BASE + 0x10000000) diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h index 15ff0eacf2..a051b6d39b 100644 --- a/include/configs/MPC8610HPCD.h +++ b/include/configs/MPC8610HPCD.h @@ -55,6 +55,7 @@ #define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported & enabled */ #define CONFIG_ALTIVEC 1 /* diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index 9acc3da54a..49ee7ffd3a 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -67,6 +67,7 @@ #define BANK_INTERLEAVING 0x22000000 #define SUPER_BANK_INTERLEAVING 0x23000000 +#define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */ #define CONFIG_ALTIVEC 1 diff --git a/include/configs/PM520.h b/include/configs/PM520.h index 6eb6444925..259178f857 100644 --- a/include/configs/PM520.h +++ b/include/configs/PM520.h @@ -40,6 +40,8 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* * Serial console configuration */ diff --git a/include/configs/TB5200.h b/include/configs/TB5200.h index 6cb3022b93..d21783b838 100644 --- a/include/configs/TB5200.h +++ b/include/configs/TB5200.h @@ -42,6 +42,8 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* * Serial console configuration */ diff --git a/include/configs/TOP5200.h b/include/configs/TOP5200.h index 71fa36baae..4c447356a4 100644 --- a/include/configs/TOP5200.h +++ b/include/configs/TOP5200.h @@ -50,6 +50,8 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* * Serial console configuration */ diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h index bff2edf769..bfb478a868 100644 --- a/include/configs/TQM5200.h +++ b/include/configs/TQM5200.h @@ -47,6 +47,8 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* * Serial console configuration */ diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index a86939e097..89fc465416 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -423,6 +423,8 @@ extern int tqm834x_num_flash_banks; #define CFG_HID0_FINAL CFG_HID0_INIT #define CFG_HID2 HID2_HBE +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* DDR 0 - 512M */ #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) diff --git a/include/configs/Total5200.h b/include/configs/Total5200.h index 31f10dd87c..598fe7bf27 100644 --- a/include/configs/Total5200.h +++ b/include/configs/Total5200.h @@ -48,6 +48,8 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* * Serial console configuration */ diff --git a/include/configs/Yukon8220.h b/include/configs/Yukon8220.h index 00c4ff093a..1b4195a08f 100644 --- a/include/configs/Yukon8220.h +++ b/include/configs/Yukon8220.h @@ -31,6 +31,8 @@ #define CONFIG_MPC8220 1 #define CONFIG_YUKON8220 1 /* ... on Yukon board */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* Input clock running at 30Mhz, read Hid1 for the CPU multiplier to determine the CPU speed. */ #define CFG_MPC8220_CLKIN 30000000/* ... running at 30MHz */ diff --git a/include/configs/ads5121.h b/include/configs/ads5121.h index c975a249c7..4226529eb7 100644 --- a/include/configs/ads5121.h +++ b/include/configs/ads5121.h @@ -372,6 +372,8 @@ #define CFG_HID0_FINAL HID0_ENABLE_MACHINE_CHECK #define CFG_HID2 HID2_HBE +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* * Internal Definitions * diff --git a/include/configs/aev.h b/include/configs/aev.h index e3f810c5c8..c5e475921c 100644 --- a/include/configs/aev.h +++ b/include/configs/aev.h @@ -41,6 +41,8 @@ #define CONFIG_AEVFIFO 1 #define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ diff --git a/include/configs/canmb.h b/include/configs/canmb.h index 0f7bb619ce..f097e2c2f0 100644 --- a/include/configs/canmb.h +++ b/include/configs/canmb.h @@ -40,6 +40,8 @@ #define CONFIG_BOARD_EARLY_INIT_R +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* * Serial console configuration */ diff --git a/include/configs/cm5200.h b/include/configs/cm5200.h index d554348021..ef50c7cabb 100644 --- a/include/configs/cm5200.h +++ b/include/configs/cm5200.h @@ -31,6 +31,8 @@ #define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ #define CONFIG_CM5200 1 /* ... on CM5200 platform */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* * Supported commands */ diff --git a/include/configs/cpci5200.h b/include/configs/cpci5200.h index 1b30e51a3f..fffd1fe1fa 100644 --- a/include/configs/cpci5200.h +++ b/include/configs/cpci5200.h @@ -50,6 +50,8 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* * Serial console configuration */ diff --git a/include/configs/hmi1001.h b/include/configs/hmi1001.h index e5a8897744..ad7cf76869 100644 --- a/include/configs/hmi1001.h +++ b/include/configs/hmi1001.h @@ -40,6 +40,8 @@ #define CONFIG_BOARD_EARLY_INIT_R +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* * Serial console configuration */ diff --git a/include/configs/inka4x0.h b/include/configs/inka4x0.h index c89f041ee4..6ec92c38c5 100644 --- a/include/configs/inka4x0.h +++ b/include/configs/inka4x0.h @@ -40,6 +40,8 @@ #define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* * Serial console configuration */ diff --git a/include/configs/jupiter.h b/include/configs/jupiter.h index 980e9fe9ce..c9859270c0 100644 --- a/include/configs/jupiter.h +++ b/include/configs/jupiter.h @@ -41,6 +41,8 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* * Serial console configuration */ diff --git a/include/configs/mcc200.h b/include/configs/mcc200.h index a9c86f9e3f..e4c3f7239b 100644 --- a/include/configs/mcc200.h +++ b/include/configs/mcc200.h @@ -40,6 +40,8 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* * Serial console configuration * diff --git a/include/configs/mecp5200.h b/include/configs/mecp5200.h index 5218d9ca97..8dfb9aa8a9 100644 --- a/include/configs/mecp5200.h +++ b/include/configs/mecp5200.h @@ -50,6 +50,8 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* * Serial console configuration */ diff --git a/include/configs/motionpro.h b/include/configs/motionpro.h index 1503598166..b6843af3dc 100644 --- a/include/configs/motionpro.h +++ b/include/configs/motionpro.h @@ -35,6 +35,7 @@ #define CONFIG_MPC5200 1 /* More exactly a MPC5200 */ #define CONFIG_MOTIONPRO 1 /* ... on Promess Motion-PRO board */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ /* * BOOTP options diff --git a/include/configs/mpc7448hpc2.h b/include/configs/mpc7448hpc2.h index f614e679f9..a218f7576c 100644 --- a/include/configs/mpc7448hpc2.h +++ b/include/configs/mpc7448hpc2.h @@ -39,7 +39,7 @@ #define CONFIG_MPC7448HPC2 #define CONFIG_74xx -#define CONFIG_750FX /* this option to enable init of extended BATs */ +#define CONFIG_HIGH_BATS /* High BATs supported */ #define CONFIG_ALTIVEC /* undef to disable */ #define CFG_BOARD_NAME "MPC7448 HPC II" diff --git a/include/configs/munices.h b/include/configs/munices.h index 38b27bb3a7..e0046ec2d3 100644 --- a/include/configs/munices.h +++ b/include/configs/munices.h @@ -35,6 +35,7 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ #define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ /* * Command line configuration. diff --git a/include/configs/o2dnt.h b/include/configs/o2dnt.h index 8dde1ef391..88bdb03e67 100644 --- a/include/configs/o2dnt.h +++ b/include/configs/o2dnt.h @@ -37,6 +37,8 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* * Serial console configuration */ diff --git a/include/configs/p3mx.h b/include/configs/p3mx.h index 0dac5161ba..0913b14a4c 100644 --- a/include/configs/p3mx.h +++ b/include/configs/p3mx.h @@ -42,6 +42,7 @@ #if defined (CONFIG_P3M750) #define CONFIG_750FX /* 750GL/GX/FX */ +#define CONFIG_HIGH_BATS /* High BATs supported */ #define CFG_BOARD_NAME "P3M750" #define CFG_BUS_HZ 100000000 #define CFG_BUS_CLK CFG_BUS_HZ diff --git a/include/configs/pf5200.h b/include/configs/pf5200.h index 2ce39c913c..c065d3328c 100644 --- a/include/configs/pf5200.h +++ b/include/configs/pf5200.h @@ -49,6 +49,7 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ /* * Serial console configuration */ diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index 0ebc674a69..74815567ff 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -570,6 +570,8 @@ #define CFG_HID2 HID2_HBE +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* DDR @ 0x00000000 */ #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) diff --git a/include/configs/smmaco4.h b/include/configs/smmaco4.h index 4578cae7d6..3e47eb88a7 100644 --- a/include/configs/smmaco4.h +++ b/include/configs/smmaco4.h @@ -42,6 +42,8 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* * Serial console configuration */ diff --git a/include/configs/sorcery.h b/include/configs/sorcery.h index c62b9775c6..18f5533737 100644 --- a/include/configs/sorcery.h +++ b/include/configs/sorcery.h @@ -31,6 +31,8 @@ #define CONFIG_MPC8220 1 #define CONFIG_SORCERY 1 /* Sorcery board */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* Input clock running at 60Mhz, read Hid1 for the CPU multiplier to determine the CPU speed. */ #define CFG_MPC8220_CLKIN 60000000 /* ... running at 60MHz */ diff --git a/include/configs/spieval.h b/include/configs/spieval.h index 49213dc67a..69d2d67ab1 100644 --- a/include/configs/spieval.h +++ b/include/configs/spieval.h @@ -44,6 +44,8 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* * Serial console configuration */ diff --git a/include/configs/uc101.h b/include/configs/uc101.h index dc1d7e1b3d..042750e2fe 100644 --- a/include/configs/uc101.h +++ b/include/configs/uc101.h @@ -40,6 +40,8 @@ #define CONFIG_BOARD_EARLY_INIT_R +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* * Serial console configuration */ diff --git a/include/configs/v38b.h b/include/configs/v38b.h index e24d6f77ae..c203522552 100644 --- a/include/configs/v38b.h +++ b/include/configs/v38b.h @@ -46,6 +46,8 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* * Serial console configuration */ -- cgit From 8a24c07ba5da2c72ad1f05e3eb8a463750200c98 Mon Sep 17 00:00:00 2001 From: Grant Erickson Date: Thu, 22 May 2008 14:44:24 -0700 Subject: ppc4xx: Enable Primordial Stack for 40x and Unify ECC Handling This patch (Part 2 of 2): * Rolls up a suite of changes to enable correct primordial stack and global data handling when the data cache is used for such a purpose for PPC40x-variants (i.e. CFG_INIT_DCACHE_CS). * Related to the first, unifies DDR2 SDRAM and ECC initialization by eliminating redundant ECC initialization implementations and moving redundant SDRAM initialization out of board code into shared 4xx code. * Enables MCSR visibility on the 405EX(r). * Enables the use of the data cache for initial RAM on both AMCC's Kilauea and Makalu and removes a redundant CFG_POST_MEMORY flag from each board's CONFIG_POST value. - Removed, per Stefan Roese's request, defunct memory.c file for Makalu and rolled sdram_init from it into makalu.c. With respect to the 4xx DDR initialization and ECC unification, there is certainly more work that can and should be done (file renaming, etc.). However, that can be handled at a later date on a second or third pass. As it stands, this patch moves things forward in an incremental yet positive way for those platforms that utilize this code and the features associated with it. Signed-off-by: Grant Erickson Signed-off-by: Stefan Roese --- include/configs/kilauea.h | 108 +++++++++++++++++++++++++++++++++++++------ include/configs/makalu.h | 114 ++++++++++++++++++++++++++++++++++++++++------ 2 files changed, 195 insertions(+), 27 deletions(-) (limited to 'include/configs') diff --git a/include/configs/kilauea.h b/include/configs/kilauea.h index a59676870f..035a40e3b5 100644 --- a/include/configs/kilauea.h +++ b/include/configs/kilauea.h @@ -1,4 +1,7 @@ /* + * Copyright (c) 2008 Nuovation System Designs, LLC + * Grant Erickson + * * (C) Copyright 2007 * Stefan Roese, DENX Software Engineering, sr@denx.de. * @@ -54,20 +57,56 @@ #define CFG_MONITOR_BASE (TEXT_BASE) /*----------------------------------------------------------------------- - * Initial RAM & stack pointer - *----------------------------------------------------------------------*/ -#define CFG_INIT_RAM_ADDR 0x02000000 /* inside of SDRAM */ -#define CFG_INIT_RAM_END (4 << 10) + * Initial RAM & Stack Pointer Configuration Options + * + * There are traditionally three options for the primordial + * (i.e. initial) stack usage on the 405-series: + * + * 1) On-chip Memory (OCM) (i.e. SRAM) + * 2) Data cache + * 3) SDRAM + * + * For the 405EX(r), there is no OCM, so we are left with (2) or (3) + * the latter of which is less than desireable since it requires + * setting up the SDRAM and ECC in assembly code. + * + * To use (2), define 'CFG_INIT_DCACHE_CS' to be an unused chip + * select on the External Bus Controller (EBC) and then select a + * value for 'CFG_INIT_RAM_ADDR' outside of the range of valid, + * physical SDRAM. Otherwise, undefine 'CFG_INIT_DCACHE_CS' and + * select a value for 'CFG_INIT_RAM_ADDR' within the range of valid, + * physical SDRAM to use (3). + *-----------------------------------------------------------------------*/ + +#define CFG_INIT_DCACHE_CS 4 + +#if defined(CFG_INIT_DCACHE_CS) +#define CFG_INIT_RAM_ADDR (CFG_SDRAM_BASE + ( 1 << 30)) /* 1 GiB */ +#else +#define CFG_INIT_RAM_ADDR (CFG_SDRAM_BASE + (32 << 20)) /* 32 MiB */ +#endif /* defined(CFG_INIT_DCACHE_CS) */ + +#define CFG_INIT_RAM_END (4 << 10) /* 4 KiB */ #define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -/* reserve some memory for POST and BOOT limit info */ -#define CFG_INIT_SP_OFFSET (CFG_GBL_DATA_OFFSET - 16) -/* extra data in init-ram */ -#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 4) -#define CFG_POST_MAGIC (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET - 8) -#define CFG_POST_VAL (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET - 12) -#define CFG_OCM_DATA_ADDR CFG_INIT_RAM_ADDR /* for commproc.c */ +/* + * If the data cache is being used for the primordial stack and global + * data area, the POST word must be placed somewhere else. The General + * Purpose Timer (GPT) is unused by u-boot and the kernel and preserves + * its compare and mask register contents across reset, so it is used + * for the POST word. + */ + +#if defined(CFG_INIT_DCACHE_CS) +# define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET +# define CFG_POST_ALT_WORD_ADDR (CFG_PERIPHERAL_BASE + GPT0_COMP6) +#else +# define CFG_INIT_EXTRA_SIZE 16 +# define CFG_INIT_SP_OFFSET (CFG_GBL_DATA_OFFSET - CFG_INIT_EXTRA_SIZE) +# define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 4) +# define CFG_OCM_DATA_ADDR CFG_INIT_RAM_ADDR +#endif /* defined(CFG_INIT_DCACHE_CS) */ /*----------------------------------------------------------------------- * Serial Port @@ -187,6 +226,50 @@ *----------------------------------------------------------------------*/ #define CFG_MBYTES_SDRAM (256) /* 256MB */ +#define CFG_SDRAM0_MB0CF_BASE (( 0 << 20) + CFG_SDRAM_BASE) + +/* DDR1/2 SDRAM Device Control Register Data Values */ +#define CFG_SDRAM0_MB0CF ((CFG_SDRAM0_MB0CF_BASE >> 3) | \ + SDRAM_RXBAS_SDSZ_256MB | \ + SDRAM_RXBAS_SDAM_MODE7 | \ + SDRAM_RXBAS_SDBE_ENABLE) +#define CFG_SDRAM0_MB1CF SDRAM_RXBAS_SDBE_DISABLE +#define CFG_SDRAM0_MB2CF SDRAM_RXBAS_SDBE_DISABLE +#define CFG_SDRAM0_MB3CF SDRAM_RXBAS_SDBE_DISABLE +#define CFG_SDRAM0_MCOPT1 0x04322000 +#define CFG_SDRAM0_MCOPT2 0x00000000 +#define CFG_SDRAM0_MODT0 0x01800000 +#define CFG_SDRAM0_MODT1 0x00000000 +#define CFG_SDRAM0_CODT 0x0080f837 +#define CFG_SDRAM0_RTR 0x06180000 +#define CFG_SDRAM0_INITPLR0 0xa8380000 +#define CFG_SDRAM0_INITPLR1 0x81900400 +#define CFG_SDRAM0_INITPLR2 0x81020000 +#define CFG_SDRAM0_INITPLR3 0x81030000 +#define CFG_SDRAM0_INITPLR4 0x81010404 +#define CFG_SDRAM0_INITPLR5 0x81000542 +#define CFG_SDRAM0_INITPLR6 0x81900400 +#define CFG_SDRAM0_INITPLR7 0x8D080000 +#define CFG_SDRAM0_INITPLR8 0x8D080000 +#define CFG_SDRAM0_INITPLR9 0x8D080000 +#define CFG_SDRAM0_INITPLR10 0x8D080000 +#define CFG_SDRAM0_INITPLR11 0x81000442 +#define CFG_SDRAM0_INITPLR12 0x81010780 +#define CFG_SDRAM0_INITPLR13 0x81010400 +#define CFG_SDRAM0_INITPLR14 0x00000000 +#define CFG_SDRAM0_INITPLR15 0x00000000 +#define CFG_SDRAM0_RQDC 0x80000038 +#define CFG_SDRAM0_RFDC 0x00000209 +#define CFG_SDRAM0_RDCC 0x40000000 +#define CFG_SDRAM0_DLCR 0x030000a5 +#define CFG_SDRAM0_CLKTR 0x80000000 +#define CFG_SDRAM0_WRDTR 0x00000000 +#define CFG_SDRAM0_SDTR1 0x80201000 +#define CFG_SDRAM0_SDTR2 0x32204232 +#define CFG_SDRAM0_SDTR3 0x080b0d1a +#define CFG_SDRAM0_MMODE 0x00000442 +#define CFG_SDRAM0_MEMODE 0x00000404 + /*----------------------------------------------------------------------- * I2C *----------------------------------------------------------------------*/ @@ -319,8 +402,7 @@ #define CONFIG_CMD_SNTP /* POST support */ -#define CONFIG_POST (CFG_POST_MEMORY | \ - CFG_POST_CACHE | \ +#define CONFIG_POST (CFG_POST_CACHE | \ CFG_POST_CPU | \ CFG_POST_ETHER | \ CFG_POST_I2C | \ diff --git a/include/configs/makalu.h b/include/configs/makalu.h index af066f3a8a..566e611c79 100644 --- a/include/configs/makalu.h +++ b/include/configs/makalu.h @@ -1,4 +1,7 @@ /* + * Copyright (c) 2008 Nuovation System Designs, LLC + * Grant Erickson + * * (C) Copyright 2007-2008 * Stefan Roese, DENX Software Engineering, sr@denx.de. * @@ -52,20 +55,56 @@ #define CFG_MONITOR_BASE (TEXT_BASE) /*----------------------------------------------------------------------- - * Initial RAM & stack pointer - *----------------------------------------------------------------------*/ -#define CFG_INIT_RAM_ADDR 0x02000000 /* inside of SDRAM */ -#define CFG_INIT_RAM_END (4 << 10) + * Initial RAM & Stack Pointer Configuration Options + * + * There are traditionally three options for the primordial + * (i.e. initial) stack usage on the 405-series: + * + * 1) On-chip Memory (OCM) (i.e. SRAM) + * 2) Data cache + * 3) SDRAM + * + * For the 405EX(r), there is no OCM, so we are left with (2) or (3) + * the latter of which is less than desireable since it requires + * setting up the SDRAM and ECC in assembly code. + * + * To use (2), define 'CFG_INIT_DCACHE_CS' to be an unused chip + * select on the External Bus Controller (EBC) and then select a + * value for 'CFG_INIT_RAM_ADDR' outside of the range of valid, + * physical SDRAM. Otherwise, undefine 'CFG_INIT_DCACHE_CS' and + * select a value for 'CFG_INIT_RAM_ADDR' within the range of valid, + * physical SDRAM to use (3). + *-----------------------------------------------------------------------*/ + +#define CFG_INIT_DCACHE_CS 4 + +#if defined(CFG_INIT_DCACHE_CS) +#define CFG_INIT_RAM_ADDR (CFG_SDRAM_BASE + ( 1 << 30)) /* 1 GiB */ +#else +#define CFG_INIT_RAM_ADDR (CFG_SDRAM_BASE + (32 << 20)) /* 32 MiB */ +#endif /* defined(CFG_INIT_DCACHE_CS) */ + +#define CFG_INIT_RAM_END (4 << 10) /* 4 KiB */ #define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -/* reserve some memory for POST and BOOT limit info */ -#define CFG_INIT_SP_OFFSET (CFG_GBL_DATA_OFFSET - 16) -/* extra data in init-ram */ -#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 4) -#define CFG_POST_MAGIC (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET - 8) -#define CFG_POST_VAL (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET - 12) -#define CFG_OCM_DATA_ADDR CFG_INIT_RAM_ADDR /* for commproc.c */ +/* + * If the data cache is being used for the primordial stack and global + * data area, the POST word must be placed somewhere else. The General + * Purpose Timer (GPT) is unused by u-boot and the kernel and preserves + * its compare and mask register contents across reset, so it is used + * for the POST word. + */ + +#if defined(CFG_INIT_DCACHE_CS) +# define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET +# define CFG_POST_ALT_WORD_ADDR (CFG_PERIPHERAL_BASE + GPT0_COMP6) +#else +# define CFG_INIT_EXTRA_SIZE 16 +# define CFG_INIT_SP_OFFSET (CFG_GBL_DATA_OFFSET - CFG_INIT_EXTRA_SIZE) +# define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 4) +# define CFG_OCM_DATA_ADDR CFG_INIT_RAM_ADDR +#endif /* defined(CFG_INIT_DCACHE_CS) */ /*----------------------------------------------------------------------- * Serial Port @@ -113,7 +152,55 @@ /*----------------------------------------------------------------------- * DDR SDRAM *----------------------------------------------------------------------*/ -#define CFG_MBYTES_SDRAM 256 +#define CFG_MBYTES_SDRAM (256) /* 256MB */ + +#define CFG_SDRAM0_MB0CF_BASE (( 0 << 20) + CFG_SDRAM_BASE) +#define CFG_SDRAM0_MB1CF_BASE ((128 << 20) + CFG_SDRAM_BASE) + +/* DDR1/2 SDRAM Device Control Register Data Values */ +#define CFG_SDRAM0_MB0CF ((CFG_SDRAM0_MB0CF_BASE >> 3) | \ + SDRAM_RXBAS_SDSZ_128MB | \ + SDRAM_RXBAS_SDAM_MODE2 | \ + SDRAM_RXBAS_SDBE_ENABLE) +#define CFG_SDRAM0_MB1CF ((CFG_SDRAM0_MB1CF_BASE >> 3) | \ + SDRAM_RXBAS_SDSZ_128MB | \ + SDRAM_RXBAS_SDAM_MODE2 | \ + SDRAM_RXBAS_SDBE_ENABLE) +#define CFG_SDRAM0_MB2CF SDRAM_RXBAS_SDBE_DISABLE +#define CFG_SDRAM0_MB3CF SDRAM_RXBAS_SDBE_DISABLE +#define CFG_SDRAM0_MCOPT1 0x04322000 +#define CFG_SDRAM0_MCOPT2 0x00000000 +#define CFG_SDRAM0_MODT0 0x01800000 +#define CFG_SDRAM0_MODT1 0x00000000 +#define CFG_SDRAM0_CODT 0x0080f837 +#define CFG_SDRAM0_RTR 0x06180000 +#define CFG_SDRAM0_INITPLR0 0xa8380000 +#define CFG_SDRAM0_INITPLR1 0x81900400 +#define CFG_SDRAM0_INITPLR2 0x81020000 +#define CFG_SDRAM0_INITPLR3 0x81030000 +#define CFG_SDRAM0_INITPLR4 0x81010404 +#define CFG_SDRAM0_INITPLR5 0x81000542 +#define CFG_SDRAM0_INITPLR6 0x81900400 +#define CFG_SDRAM0_INITPLR7 0x8D080000 +#define CFG_SDRAM0_INITPLR8 0x8D080000 +#define CFG_SDRAM0_INITPLR9 0x8D080000 +#define CFG_SDRAM0_INITPLR10 0x8D080000 +#define CFG_SDRAM0_INITPLR11 0x81000442 +#define CFG_SDRAM0_INITPLR12 0x81010780 +#define CFG_SDRAM0_INITPLR13 0x81010400 +#define CFG_SDRAM0_INITPLR14 0x00000000 +#define CFG_SDRAM0_INITPLR15 0x00000000 +#define CFG_SDRAM0_RQDC 0x80000038 +#define CFG_SDRAM0_RFDC 0x00000209 +#define CFG_SDRAM0_RDCC 0x40000000 +#define CFG_SDRAM0_DLCR 0x030000a5 +#define CFG_SDRAM0_CLKTR 0x80000000 +#define CFG_SDRAM0_WRDTR 0x00000000 +#define CFG_SDRAM0_SDTR1 0x80201000 +#define CFG_SDRAM0_SDTR2 0x32204232 +#define CFG_SDRAM0_SDTR3 0x080b0d1a +#define CFG_SDRAM0_MMODE 0x00000442 +#define CFG_SDRAM0_MEMODE 0x00000404 /*----------------------------------------------------------------------- * I2C @@ -244,8 +331,7 @@ #define CONFIG_CMD_SNTP /* POST support */ -#define CONFIG_POST (CFG_POST_MEMORY | \ - CFG_POST_CACHE | \ +#define CONFIG_POST (CFG_POST_CACHE | \ CFG_POST_CPU | \ CFG_POST_ETHER | \ CFG_POST_I2C | \ -- cgit From ec724f883ee3f3925e6c55027e8ffa70ada83303 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 2 Jun 2008 17:13:55 +0200 Subject: ppc4xx: Change Kilauea to use the common DDR2 init function This patch changes the kilauea and kilauea_nand (for NAND booting) board port to not use a board specific DDR2 init routine anymore. Now the common code from cpu/ppc4xx is used. Thanks to Grant Erickson for all his basic work on this 405EX early bootup. Signed-off-by: Stefan Roese --- include/configs/kilauea.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'include/configs') diff --git a/include/configs/kilauea.h b/include/configs/kilauea.h index 035a40e3b5..205577faa6 100644 --- a/include/configs/kilauea.h +++ b/include/configs/kilauea.h @@ -170,9 +170,9 @@ * This NAND U-Boot (NUB) is a special U-Boot version which can be started * from RAM. Therefore it mustn't (re-)configure the SDRAM controller. * - * On 440EPx the SPL is copied to SDRAM before the NAND controller is - * set up. While still running from cache, I experienced problems accessing - * the NAND controller. sr - 2006-08-25 + * On 405EX the SPL is copied to SDRAM before the NAND controller is + * set up. While still running from location 0xfffff000...0xffffffff the + * NAND controller cannot be accessed since it is attached to CS0 too. */ #define CFG_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */ #define CFG_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */ @@ -511,7 +511,7 @@ /* Memory Bank 2 (FPGA) initialization */ #define CFG_EBC_PB2AP 0x9400C800 -#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0x800,BS=1MB,BU=R/W,BW=8bit */ +#define CFG_EBC_PB2CR (CFG_FPGA_BASE | 0x18000) #define CFG_EBC_CFG 0x7FC00000 /* EBC0_CFG */ -- cgit From 3c1de1a6d36be9eee284a6c596a86e94f19cc5b2 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 19 May 2008 11:34:53 +0200 Subject: ppc4xx: Remove implementations of testdram() This patch removes the used testdram() implementations of the board that are maintained by myself. Signed-off-by: Stefan Roese --- include/configs/alpr.h | 1 - include/configs/bamboo.h | 1 - include/configs/ebony.h | 1 - include/configs/katmai.h | 1 - include/configs/luan.h | 1 - include/configs/ocotea.h | 1 - include/configs/taishan.h | 1 - include/configs/yucca.h | 1 - 8 files changed, 8 deletions(-) (limited to 'include/configs') diff --git a/include/configs/alpr.h b/include/configs/alpr.h index 3e906c4251..fb6feb5274 100644 --- a/include/configs/alpr.h +++ b/include/configs/alpr.h @@ -33,7 +33,6 @@ #define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ #define CONFIG_LAST_STAGE_INIT 1 /* call last_stage_init() */ -#undef CFG_DRAM_TEST /* Disable-takes long time! */ #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ #define CONFIG_4xx_DCACHE /* Enable i- and d-cache */ diff --git a/include/configs/bamboo.h b/include/configs/bamboo.h index 2f0df8ad2d..8d77164059 100644 --- a/include/configs/bamboo.h +++ b/include/configs/bamboo.h @@ -223,7 +223,6 @@ #define SPD_EEPROM_ADDRESS {CFG_SIMULATE_SPD_EEPROM, 0x50, 0x51} #define CFG_MBYTES_SDRAM (64) /* 64MB fixed size for early-sdram-init */ #define CONFIG_PROG_SDRAM_TLB -#undef CFG_DRAM_TEST /*----------------------------------------------------------------------- * I2C diff --git a/include/configs/ebony.h b/include/configs/ebony.h index ba68fd4b96..b41fa175fe 100644 --- a/include/configs/ebony.h +++ b/include/configs/ebony.h @@ -35,7 +35,6 @@ #define CONFIG_440 1 /* ... PPC440 family */ #define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ -#undef CFG_DRAM_TEST /* Disable-takes long time! */ #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ /* diff --git a/include/configs/katmai.h b/include/configs/katmai.h index cce883fd85..3c8186289a 100644 --- a/include/configs/katmai.h +++ b/include/configs/katmai.h @@ -37,7 +37,6 @@ #define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_440 1 /* ... PPC440 family */ #define CONFIG_440SPE 1 /* Specifc SPe support */ -#undef CFG_DRAM_TEST /* Disable-takes long time */ #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ diff --git a/include/configs/luan.h b/include/configs/luan.h index 37151d31fd..41999d32f9 100644 --- a/include/configs/luan.h +++ b/include/configs/luan.h @@ -68,7 +68,6 @@ #define CFG_FLASH_BASE CFG_SMALL_FLASH #endif -#undef CFG_DRAM_TEST #if CFG_SRAM_BASE #define CFG_KBYTES_SDRAM 1024*2 #else diff --git a/include/configs/ocotea.h b/include/configs/ocotea.h index be2b3ec7ef..1ec7a253fc 100644 --- a/include/configs/ocotea.h +++ b/include/configs/ocotea.h @@ -44,7 +44,6 @@ #define CONFIG_440 1 /* ... PPC440 family */ #define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ -#undef CFG_DRAM_TEST /* Disable-takes long time! */ #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ /*----------------------------------------------------------------------- diff --git a/include/configs/taishan.h b/include/configs/taishan.h index 1879d38522..7b084cb78e 100644 --- a/include/configs/taishan.h +++ b/include/configs/taishan.h @@ -32,7 +32,6 @@ #define CONFIG_440GX 1 /* Specifc GX support */ #define CONFIG_440 1 /* ... PPC440 family */ #define CONFIG_4xx 1 /* ... PPC4xx family */ -#undef CFG_DRAM_TEST /* Disable-takes long time! */ #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ diff --git a/include/configs/yucca.h b/include/configs/yucca.h index 6f9d3e3c6f..9a0813f6cf 100644 --- a/include/configs/yucca.h +++ b/include/configs/yucca.h @@ -38,7 +38,6 @@ #define CONFIG_440 1 /* ... PPC440 family */ #define CONFIG_440SPE 1 /* Specifc SPe support */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ -#undef CFG_DRAM_TEST /* Disable-takes long time */ #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ #define EXTCLK_33_33 33333333 #define EXTCLK_66_66 66666666 -- cgit From d255bb0e78d1cac5b7c8c98cb77a095f5f16de0d Mon Sep 17 00:00:00 2001 From: Haavard Skinnemoen Date: Fri, 16 May 2008 11:10:31 +0200 Subject: SPI API improvements This patch gets rid of the spi_chipsel table and adds a handful of new functions that makes the SPI layer cleaner and more flexible. Instead of the spi_chipsel table, each board that wants to use SPI gets to implement three hooks: * spi_cs_activate(): Activates the chipselect for a given slave * spi_cs_deactivate(): Deactivates the chipselect for a given slave * spi_cs_is_valid(): Determines if the given bus/chipselect combination can be activated. Not all drivers may need those extra functions however. If that's the case, the board code may just leave them out (assuming they know what the driver needs) or rely on the linker to strip them out (assuming --gc-sections is being used.) To set up communication parameters for a given slave, the driver needs to call spi_setup_slave(). This returns a pointer to an opaque spi_slave struct which must be passed as a parameter to subsequent SPI calls. This struct can be freed by calling spi_free_slave(), but most driver probably don't want to do this. Before starting one or more SPI transfers, the driver must call spi_claim_bus() to gain exclusive access to the SPI bus and initialize the hardware. When all transfers are done, the driver must call spi_release_bus() to make the bus available to others, and possibly shut down the SPI controller hardware. spi_xfer() behaves mostly the same as before, but it now takes a spi_slave parameter instead of a spi_chipsel function pointer. It also got a new parameter, flags, which is used to specify chip select behaviour. This may be extended with other flags in the future. This patch has been build-tested on all powerpc and arm boards involved. I have not tested NIOS since I don't have a toolchain for it installed, so I expect some breakage there even though I've tried fixing up everything I could find by visual inspection. I have run-time tested this on AVR32 ATNGW100 using the atmel_spi and DataFlash drivers posted as a follow-up. I'd like some help testing other boards that use the existing SPI API. But most of all, I'd like some comments on the new API. Is this stuff usable for everyone? If not, why? Changed in v4: - Build fixes for various boards, drivers and commands - Provide common struct spi_slave definition that can be extended by drivers - Pass a struct spi_slave * to spi_cs_activate and spi_cs_deactivate - Make default bus and mode build-time configurable - Override default SPI bus ID and mode on mx32ads and imx31_litekit. Changed in v3: - Add opaque struct spi_slave for controller-specific data associated with a slave. - Add spi_claim_bus() and spi_release_bus() - Add spi_free_slave() - spi_setup() is now called spi_setup_slave() and returns a struct spi_slave - soft_spi now supports four SPI modes (CPOL|CPHA) - Add bus parameter to spi_setup_slave() - Convert the new i.MX32 SPI driver - Convert the new MC13783 RTC driver Changed in v2: - Convert the mpc8xxx_spi driver and the mpc8349emds board to the new API. Signed-off-by: Haavard Skinnemoen Tested-by: Guennadi Liakhovetski --- include/configs/imx31_litekit.h | 3 ++- include/configs/mx31ads.h | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) (limited to 'include/configs') diff --git a/include/configs/imx31_litekit.h b/include/configs/imx31_litekit.h index 4281d73c90..ec4ed1eeb6 100644 --- a/include/configs/imx31_litekit.h +++ b/include/configs/imx31_litekit.h @@ -65,7 +65,8 @@ #define CONFIG_HARD_SPI 1 #define CONFIG_MXC_SPI 1 -#define CONFIG_MXC_SPI_IFACE 1 +#define CONFIG_DEFAULT_SPI_BUS 1 +#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_2 | SPI_CS_HIGH) #define CONFIG_RTC_MC13783 1 diff --git a/include/configs/mx31ads.h b/include/configs/mx31ads.h index 2ea48a6da9..37ba872a43 100644 --- a/include/configs/mx31ads.h +++ b/include/configs/mx31ads.h @@ -62,7 +62,8 @@ #define CONFIG_HARD_SPI 1 #define CONFIG_MXC_SPI 1 -#define CONFIG_MXC_SPI_IFACE 1 /* Default SPI interface number */ +#define CONFIG_DEFAULT_SPI_BUS 1 +#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_2 | SPI_CS_HIGH) #define CONFIG_RTC_MC13783 1 -- cgit From de5bfcf7b0425e032be12698252dbaa6b65a28c0 Mon Sep 17 00:00:00 2001 From: Matthias Fuchs Date: Fri, 30 May 2008 16:55:06 +0200 Subject: ppc4xx: Cleanup CPCI405 variant's config file This patch removes some dead code from CPCI405 board's config files. JFFS2 support is also removed. It's not used and CPCI4052 does not build anymore without some size reduction. Signed-off-by: Matthias Fuchs --- include/configs/CPCI4052.h | 38 -------------------------------------- include/configs/CPCI405AB.h | 22 ---------------------- include/configs/CPCI405DT.h | 33 --------------------------------- 3 files changed, 93 deletions(-) (limited to 'include/configs') diff --git a/include/configs/CPCI4052.h b/include/configs/CPCI4052.h index b248639fd0..fd49f569ae 100644 --- a/include/configs/CPCI4052.h +++ b/include/configs/CPCI4052.h @@ -88,32 +88,17 @@ #define CONFIG_CMD_FAT #define CONFIG_CMD_ELF #define CONFIG_CMD_DATE -#define CONFIG_CMD_JFFS2 #define CONFIG_CMD_I2C #define CONFIG_CMD_MII #define CONFIG_CMD_PING #define CONFIG_CMD_BSP #define CONFIG_CMD_EEPROM - -#if 0 /* test-only */ -#define CONFIG_NETCONSOLE -#define CONFIG_NET_MULTI - -#ifdef CONFIG_NET_MULTI -#define CONFIG_PHY1_ADDR 1 /* PHY address: for NetConsole */ -#endif -#endif - #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION #define CONFIG_SUPPORT_VFAT -#if 0 /* test-only */ -#define CONFIG_AUTO_UPDATE 1 /* autoupdate via compactflash */ -#endif - #undef CONFIG_WATCHDOG /* watchdog disabled */ #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ @@ -256,29 +241,6 @@ #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -/* - * JFFS2 partitions - */ - -/* No command line, one static partition, use whole device */ -#undef CONFIG_JFFS2_CMDLINE -#define CONFIG_JFFS2_DEV "nor0" -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 - -/* mtdparts command line support */ - -/* Use first bank for JFFS2, second bank contains U-Boot. - * - * Note: fake mtd_id's used, no linux mtd map file. - */ -/* -#define CONFIG_JFFS2_CMDLINE -#define MTDIDS_DEFAULT "nor0=cpci4052-0" -#define MTDPARTS_DEFAULT "mtdparts=cpci4052-0:-(jffs2)" -*/ - #if 0 /* Use NVRAM for environment variables */ /*----------------------------------------------------------------------- * NVRAM organization diff --git a/include/configs/CPCI405AB.h b/include/configs/CPCI405AB.h index 1e9597dc61..55dd6296de 100644 --- a/include/configs/CPCI405AB.h +++ b/include/configs/CPCI405AB.h @@ -88,7 +88,6 @@ #define CONFIG_CMD_FAT #define CONFIG_CMD_ELF #define CONFIG_CMD_DATE -#define CONFIG_CMD_JFFS2 #define CONFIG_CMD_I2C #define CONFIG_CMD_MII #define CONFIG_CMD_PING @@ -238,27 +237,6 @@ #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ -/* - * JFFS2 partitions - */ -/* No command line, one static partition */ -#undef CONFIG_JFFS2_CMDLINE -#define CONFIG_JFFS2_DEV "nor0" -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 - -/* mtdparts command line support */ - -/* Use first bank for JFFS2, second bank contains U-Boot. - * - * Note: fake mtd_id's used, no linux mtd map file. - */ -/* -#define CONFIG_JFFS2_CMDLINE -#define MTDIDS_DEFAULT "nor0=cpci405ab-0" -#define MTDPARTS_DEFAULT "mtdparts=cpci405ab-0:-(jffs2)" -*/ - /*----------------------------------------------------------------------- * I2C EEPROM (CAT24WC32) for environment */ diff --git a/include/configs/CPCI405DT.h b/include/configs/CPCI405DT.h index a8029eae9d..6b585bed5f 100644 --- a/include/configs/CPCI405DT.h +++ b/include/configs/CPCI405DT.h @@ -87,23 +87,12 @@ #define CONFIG_CMD_FAT #define CONFIG_CMD_ELF #define CONFIG_CMD_DATE -#define CONFIG_CMD_JFFS2 #define CONFIG_CMD_I2C #define CONFIG_CMD_MII #define CONFIG_CMD_PING #define CONFIG_CMD_BSP #define CONFIG_CMD_EEPROM - -#if 0 /* test-only */ -#define CONFIG_NETCONSOLE -#define CONFIG_NET_MULTI - -#ifdef CONFIG_NET_MULTI -#define CONFIG_PHY1_ADDR 1 /* PHY address: for NetConsole */ -#endif -#endif - #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION @@ -260,27 +249,6 @@ #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ -/* - * JFFS2 partitions - */ -/* No command line, one static partition */ -#undef CONFIG_JFFS2_CMDLINE -#define CONFIG_JFFS2_DEV "nor0" -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 - -/* mtdparts command line support */ - -/* Use first bank for JFFS2, second bank contains U-Boot. - * - * Note: fake mtd_id's used, no linux mtd map file. - */ -/* -#define CONFIG_JFFS2_CMDLINE -#define MTDIDS_DEFAULT "nor0=cpci405dt-0" -#define MTDPARTS_DEFAULT "mtdparts=cpci405dt-0:-(jffs2)" -*/ - #if 0 /* Use NVRAM for environment variables */ /*----------------------------------------------------------------------- * NVRAM organization @@ -416,7 +384,6 @@ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - /* * Internal Definitions * -- cgit From 9ef1cbef1a649e3779298b0e663be4865cbbbfbc Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Tue, 27 May 2008 14:19:30 +0200 Subject: Socrates: Fix PCI bus frequency report Signed-off-by: Sergei Poselenov --- include/configs/socrates.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'include/configs') diff --git a/include/configs/socrates.h b/include/configs/socrates.h index 23ed87f338..6dc9effde4 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -227,7 +227,8 @@ */ #define CFG_PCI_PHYS 0x80000000 /* 1G PCI TLB */ - +/* PCI is clocked by the external source at 33 MHz */ +#define CONFIG_PCI_CLK_FREQ 33000000 #define CFG_PCI1_MEM_BASE 0x80000000 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ -- cgit From a101361bfe23c120321e45d114c0603b8e0763e9 Mon Sep 17 00:00:00 2001 From: Remy Bohmer Date: Tue, 3 Jun 2008 15:26:21 +0200 Subject: DM9000: Add data bus-width auto detection. The U-boot DM9000x driver contains a compile time bus-width definition for the databus connected to the network controller. This compile check makes the code unclear, inflexible and is unneccessary. It can be asked to the network controller what its bus-width is by reading bits 6 and 7 of the interrupt status register. The linux kernel already uses a runtime mechanism to determine this bus-width, so the implementation below looks somewhat like that implementation. This change has been tested with DM9000A, DM9000E, DM9000EP. Signed-off-by: Remy Bohmer Signed-off-by: Ben Warren --- include/configs/scb9328.h | 4 ---- include/configs/trizepsiv.h | 4 ---- 2 files changed, 8 deletions(-) (limited to 'include/configs') diff --git a/include/configs/scb9328.h b/include/configs/scb9328.h index d140241bff..4ae25adde0 100644 --- a/include/configs/scb9328.h +++ b/include/configs/scb9328.h @@ -256,14 +256,10 @@ #define CFG_CS5U_VAL 0x00008400 #define CFG_CS5L_VAL 0x00000D03 -#define CONFIG_DRIVER_DM9000 1 #define CONFIG_DRIVER_DM9000 1 #define CONFIG_DM9000_BASE 0x16000000 #define DM9000_IO CONFIG_DM9000_BASE #define DM9000_DATA (CONFIG_DM9000_BASE+4) -/* #define CONFIG_DM9000_USE_8BIT */ -#define CONFIG_DM9000_USE_16BIT -/* #define CONFIG_DM9000_USE_32BIT */ /* f_{dpll}=2*f{ref}*(MFI+MFN/(MFD+1))/(PD+1) f_ref=16,777MHz diff --git a/include/configs/trizepsiv.h b/include/configs/trizepsiv.h index 25155ad349..f77dd14f1a 100644 --- a/include/configs/trizepsiv.h +++ b/include/configs/trizepsiv.h @@ -275,14 +275,10 @@ #define CFG_MCIO0_VAL 0x00008407 #define CFG_MCIO1_VAL 0x0000c108 -#define CONFIG_DRIVER_DM9000 1 #define CONFIG_DRIVER_DM9000 1 #define CONFIG_DM9000_BASE 0x08000000 #define DM9000_IO CONFIG_DM9000_BASE #define DM9000_DATA (CONFIG_DM9000_BASE+0x8004) -/* #define CONFIG_DM9000_USE_8BIT */ -/* #define CONFIG_DM9000_USE_16BIT */ -#define CONFIG_DM9000_USE_32BIT #define CONFIG_USB_OHCI_NEW 1 #define CFG_USB_OHCI_BOARD_INIT 1 -- cgit From a55d48174cfd1a5bc184159513f48dcbbe409c83 Mon Sep 17 00:00:00 2001 From: Shinya Kuribayashi Date: Thu, 5 Jun 2008 22:29:00 +0900 Subject: [MIPS] lib_mips/time.c: Fix CP0 count register usage and timer routines MIPS port has two problems in timer routines. One is now we assume CFG_HZ equals to CP0 counter frequency, but this is wrong. CFG_HZ has to be 1000 in the U-Boot system. The other is we don't have a proper time management counter like timestamp other ARCHs have. We need the 32-bit millisecond clock counter. This patch introduces timestamp and CYCLES_PER_JIFFY. timestamp is a 32-bit non-overflowing CFG_HZ counter, and CYCLES_PER_JIFFY is the number of calculated CP0 counter cycles in a CFG_HZ. STRATEGY: * Fix improper CFG_HZ value to have 1000 * Use CFG_MIPS_TIMER_FREQ for timer counter frequency, instead. * timer_init: initialize timestamp and set up the first timer expiration. Note that we don't need to initialize CP0 count/compare registers here as they have been already zeroed out on the system reset. Leave them as they are. * get_timer: calculate how many timestamps have been passed, then return base-relative timestamp. Make sure we can easily count missed timestamps regardless of CP0 count/compare value. * get_ticks: return the current timestamp, that is get_timer(0). Most parts are from good old Linux v2.6.16 kernel. v2: - Remove FIXME comments as they turned out to be trivial. - Use CP0 compare register as a global variable for expirelo. - Kill a global variable 'cycles_per_jiffy'. Use #define CYCLES_PER_JIFFY instead. Signed-off-by: Shinya Kuribayashi --- include/configs/dbau1x00.h | 4 +++- include/configs/gth2.h | 4 +++- include/configs/incaip.h | 4 +++- include/configs/pb1x00.h | 4 +++- include/configs/purple.h | 3 ++- include/configs/qemu-mips.h | 4 +++- include/configs/tb0229.h | 4 +++- 7 files changed, 20 insertions(+), 7 deletions(-) (limited to 'include/configs') diff --git a/include/configs/dbau1x00.h b/include/configs/dbau1x00.h index b2f606f498..45ff1e7305 100644 --- a/include/configs/dbau1x00.h +++ b/include/configs/dbau1x00.h @@ -148,7 +148,9 @@ #error "Invalid CPU frequency - must be multiple of 12!" #endif -#define CFG_HZ (CFG_MHZ * 1000000) /* FIXME causes overflow in net.c */ +#define CFG_MIPS_TIMER_FREQ (CFG_MHZ * 1000000) + +#define CFG_HZ 1000 #define CFG_SDRAM_BASE 0x80000000 /* Cached addr */ diff --git a/include/configs/gth2.h b/include/configs/gth2.h index c2a50c1f47..23618db667 100644 --- a/include/configs/gth2.h +++ b/include/configs/gth2.h @@ -118,7 +118,9 @@ #define CFG_MHZ 500 -#define CFG_HZ (CFG_MHZ * 1000000) /* FIXME causes overflow in net.c */ +#define CFG_MIPS_TIMER_FREQ (CFG_MHZ * 1000000) + +#define CFG_HZ 1000 #define CFG_SDRAM_BASE 0x80000000 /* Cached addr */ diff --git a/include/configs/incaip.h b/include/configs/incaip.h index 5ca00b3734..2e4ee66cf6 100644 --- a/include/configs/incaip.h +++ b/include/configs/incaip.h @@ -118,7 +118,9 @@ #define CFG_BOOTPARAMS_LEN 128*1024 -#define CFG_HZ (incaip_get_cpuclk() / 2) +#define CFG_MIPS_TIMER_FREQ (incaip_get_cpuclk() / 2) + +#define CFG_HZ 1000 #define CFG_SDRAM_BASE 0x80000000 diff --git a/include/configs/pb1x00.h b/include/configs/pb1x00.h index 810e0f0462..181cd11b86 100644 --- a/include/configs/pb1x00.h +++ b/include/configs/pb1x00.h @@ -81,7 +81,9 @@ #define CFG_BOOTPARAMS_LEN 128*1024 -#define CFG_HZ 396000000 /* FIXME causes overflow in net.c */ +#define CFG_MIPS_TIMER_FREQ 396000000 + +#define CFG_HZ 1000 #define CFG_SDRAM_BASE 0x80000000 /* Cached addr */ diff --git a/include/configs/purple.h b/include/configs/purple.h index 1be4e055f9..ef92637127 100644 --- a/include/configs/purple.h +++ b/include/configs/purple.h @@ -114,7 +114,8 @@ #define CFG_PROMPT "PURPLE # " /* Monitor Command Prompt */ #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_HZ (CPU_CLOCK_RATE/2) +#define CFG_MIPS_TIMER_FREQ (CPU_CLOCK_RATE/2) +#define CFG_HZ 1000 #define CFG_MAXARGS 16 /* max number of command args*/ #define CFG_LOAD_ADDR 0x80500000 /* default load address */ diff --git a/include/configs/qemu-mips.h b/include/configs/qemu-mips.h index d6bcc8e3b1..3dfd2181f4 100644 --- a/include/configs/qemu-mips.h +++ b/include/configs/qemu-mips.h @@ -120,7 +120,9 @@ #define CFG_MHZ 132 -#define CFG_HZ (CFG_MHZ * 1000000) +#define CFG_MIPS_TIMER_FREQ (CFG_MHZ * 1000000) + +#define CFG_HZ 1000 #define CFG_SDRAM_BASE 0x80000000 /* Cached addr */ diff --git a/include/configs/tb0229.h b/include/configs/tb0229.h index dadf5d3329..fc2357d406 100644 --- a/include/configs/tb0229.h +++ b/include/configs/tb0229.h @@ -122,7 +122,9 @@ #define CFG_BOOTPARAMS_LEN 128*1024 -#define CFG_HZ (CPU_TCLOCK_RATE/4) +#define CFG_MIPS_TIMER_FREQ (CPU_TCLOCK_RATE/4) + +#define CFG_HZ 1000 #define CFG_SDRAM_BASE 0x80000000 -- cgit From a8a11a9ed046b480a16e47a158f8f5300028dfa6 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 6 Jun 2008 15:54:31 +0200 Subject: ppc4xx: Unify AMCC's board config files (part 1/3) This patch series unifies the AMCC eval board ports by introducing a common include header for all AMCC eval boards: include/configs/amcc-common.h This header now includes all common configuration options/defines which are removed from the board specific headers. The reason for this is ease of maintenance and unified look and feel of all AMCC boards. Signed-off-by: Stefan Roese --- include/configs/amcc-common.h | 259 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 259 insertions(+) create mode 100644 include/configs/amcc-common.h (limited to 'include/configs') diff --git a/include/configs/amcc-common.h b/include/configs/amcc-common.h new file mode 100644 index 0000000000..1f27d785b8 --- /dev/null +++ b/include/configs/amcc-common.h @@ -0,0 +1,259 @@ +/* + * (C) Copyright 2008 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * Common configuration options for all AMCC boards + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __AMCC_COMMON_H +#define __AMCC_COMMON_H + +#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ +#define CFG_MONITOR_BASE TEXT_BASE /* Start of U-Boot */ +#define CFG_MONITOR_LEN (0xFFFFFFFF - CFG_MONITOR_BASE + 1) +#define CFG_MALLOC_LEN (1 << 20) /* Reserved for malloc */ + +/* + * UART + */ +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SERIAL_MULTI +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} + +/* + * I2C + */ +#define CONFIG_HARD_I2C /* I2C with hardware support */ +#define CFG_I2C_SLAVE 0x7F + +/* + * Ethernet/EMAC/PHY + */ +#define CONFIG_MII /* MII PHY management */ +#define CONFIG_NET_MULTI +#define CONFIG_NETCONSOLE /* include NetConsole support */ +#if defined(CONFIG_440) +#define CFG_RX_ETH_BUFFER 32 /* number of eth rx buffers */ +#else +#define CFG_RX_ETH_BUFFER 16 /* number of eth rx buffers */ +#endif + +/* + * Commands + */ +#include + +#define CONFIG_CMD_ASKENV +#if defined(CONFIG_440) +#define CONFIG_CMD_CACHE +#endif +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DIAG +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_ELF +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO + +/* + * Miscellaneous configurable options + */ +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if defined(CONFIG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO /* To use extended board_into (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_CMDLINE_EDITING /* add command line history */ +#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ +#define CONFIG_LOOPW /* enable loopw command */ +#define CONFIG_MX_CYCLIC /* enable mdc/mwc commands */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_VERSION_VARIABLE /* include version env variable */ +#define CFG_CONSOLE_INFO_QUIET /* don't print console @ startup*/ + +#define CFG_HUSH_PARSER /* Use the HUSH parser */ +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +#define CONFIG_LOADS_ECHO /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE /* allow baudrate change */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_SUBNETMASK + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/* + * Internal Definitions + */ +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port*/ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Pass open firmware flat tree + */ +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP + +/* + * Booting and default environment + */ +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" +#define CONFIG_BOOTCOMMAND "run flash_self" + +/* + * Only very few boards have default console not on ttyS0 (like Taishan) + */ +#if !defined(CONFIG_USE_TTY) +#define CONFIG_USE_TTY ttyS0 +#endif + +/* + * Only some 4xx PPC's are equipped with an FPU + */ +#if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT) +#define CONFIG_AMCC_DEF_ENV_ROOTPATH "rootpath=/opt/eldk/ppc_4xxFP\0" +#else +#define CONFIG_AMCC_DEF_ENV_ROOTPATH "rootpath=/opt/eldk/ppc_4xx\0" +#endif + +/* + * Only some boards need to extend the bootargs by some additional + * parameters (like Makalu) + */ +#if !defined(CONFIG_ADDMISC) +#define CONFIG_ADDMISC "addmisc=setenv bootargs ${bootargs}\0" +#endif + +#define xstr(s) str(s) +#define str(s) #s + +/* + * General common environment variables shared on all AMCC eval boards + */ +#define CONFIG_AMCC_DEF_ENV \ + "netdev=eth0\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs}" \ + " console=" xstr(CONFIG_USE_TTY) ",${baudrate}\0" \ + CONFIG_ADDMISC \ + "initrd_high=30000000\0" \ + "kernel_addr_r=400000\0" \ + "fdt_addr_r=800000\0" \ + "hostname=" xstr(CONFIG_HOSTNAME) "\0" \ + "bootfile=" xstr(CONFIG_HOSTNAME) "/uImage\0" \ + CONFIG_AMCC_DEF_ENV_ROOTPATH + +/* + * Default environment for arch/powerpc booting + * for boards that are ported to arch/powerpc + */ +#define CONFIG_AMCC_DEF_ENV_POWERPC \ + "flash_self=run ramargs addip addtty addmisc;" \ + "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ + "flash_nfs=run nfsargs addip addtty addmisc;" \ + "bootm ${kernel_addr} - ${fdt_addr}\0" \ + "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ + "tftp ${fdt_addr_r} ${fdt_file}; " \ + "run nfsargs addip addtty addmisc;" \ + "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ + "fdt_file=" xstr(CONFIG_HOSTNAME) "/" xstr(CONFIG_HOSTNAME) ".dtb\0" + +/* + * Default environment for arch/ppc booting, + * for boards that are not ported to arch/powerpc yet + */ +#define CONFIG_AMCC_DEF_ENV_PPC \ + "flash_self=run ramargs addip addtty addmisc;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "flash_nfs=run nfsargs addip addtty addmisc;" \ + "bootm ${kernel_addr}\0" \ + "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ + "run nfsargs addip addtty addmisc;" \ + "bootm ${kernel_addr_r}\0" + +/* + * Default environment for arch/ppc booting (old version), + * for boards that are ported to arch/ppc and arch/powerpc + */ +#define CONFIG_AMCC_DEF_ENV_PPC_OLD \ + "flash_self_old=run ramargs addip addtty addmisc;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "flash_nfs_old=run nfsargs addip addtty addmisc;" \ + "bootm ${kernel_addr}\0" \ + "net_nfs_old=tftp ${kernel_addr_r} ${bootfile};" \ + "run nfsargs addip addtty addmisc;" \ + "bootm ${kernel_addr_r}\0" + +#define CONFIG_AMCC_DEF_ENV_NOR_UPD \ + "load=tftp 200000 " xstr(CONFIG_HOSTNAME) "/u-boot.bin\0" \ + "update=protect off " xstr(CFG_MONITOR_BASE) " FFFFFFFF;" \ + "era " xstr(CFG_MONITOR_BASE) " FFFFFFFF;" \ + "cp.b ${fileaddr} " xstr(CFG_MONITOR_BASE) " ${filesize};" \ + "setenv filesize;saveenv\0" \ + "upd=run load update\0" \ + +#define CONFIG_AMCC_DEF_ENV_NAND_UPD \ + "nload=tftp 200000 " xstr(CONFIG_HOSTNAME) "/u-boot-nand.bin\0" \ + "nupdate=nand erase 0 100000;nand write 200000 0 100000;" \ + "setenv filesize;saveenv\0" \ + "nupd=run nload nupdate\0" + +#endif /* __AMCC_COMMON_H */ -- cgit From 490f204096d6e2c9940f67816f154a8125bab116 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 6 Jun 2008 15:55:03 +0200 Subject: ppc4xx: Unify AMCC's board config files (part 2/3) This patch series unifies the AMCC eval board ports by introducing a common include header for all AMCC eval boards: include/configs/amcc-common.h This header now includes all common configuration options/defines which are removed from the board specific headers. The reason for this is ease of maintenance and unified look and feel of all AMCC boards. Signed-off-by: Stefan Roese --- include/configs/acadia.h | 169 ++++------------------------------------- include/configs/bamboo.h | 168 ++++++---------------------------------- include/configs/bubinga.h | 150 ++++-------------------------------- include/configs/canyonlands.h | 173 +++++------------------------------------- include/configs/ebony.h | 151 ++++-------------------------------- include/configs/katmai.h | 162 ++++----------------------------------- include/configs/kilauea.h | 160 ++++---------------------------------- include/configs/luan.h | 147 ++++------------------------------- include/configs/makalu.h | 158 ++++---------------------------------- 9 files changed, 140 insertions(+), 1298 deletions(-) (limited to 'include/configs') diff --git a/include/configs/acadia.h b/include/configs/acadia.h index bbf726dc62..9092a7c096 100644 --- a/include/configs/acadia.h +++ b/include/configs/acadia.h @@ -34,6 +34,13 @@ #define CONFIG_ACADIA 1 /* Board is Acadia */ #define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_405EZ 1 /* Specifc 405EZ support*/ + +/* + * Include common defines/options for all AMCC eval boards + */ +#define CONFIG_HOSTNAME acadia +#include "amcc-common.h" + /* Detect Acadia PLL input clock automatically via CPLD bit */ #define CONFIG_SYS_CLK_FREQ ((in8(CFG_CPLD_BASE + 0) == 0x0c) ? \ 66666666 : 33333000) @@ -59,16 +66,11 @@ * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) *----------------------------------------------------------------------*/ -#define CFG_SDRAM_BASE 0x00000000 #define CFG_FLASH_BASE 0xfe000000 #define CFG_CPLD_BASE 0x80000000 #define CFG_NAND_ADDR 0xd0000000 #define CFG_USB_HOST 0xef603000 /* USB OHCI 1.1 controller */ -#define CFG_MONITOR_BASE TEXT_BASE -#define CFG_MONITOR_LEN (0xFFFFFFFF - CFG_MONITOR_BASE + 1) -#define CFG_MALLOC_LEN (512 * 1024)/* Reserve 512 kB for malloc() */ - /*----------------------------------------------------------------------- * Initial RAM & stack pointer *----------------------------------------------------------------------*/ @@ -89,12 +91,6 @@ *----------------------------------------------------------------------*/ #undef CFG_EXT_SERIAL_CLOCK /* external serial clock */ #define CFG_BASE_BAUD 691200 -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SERIAL_MULTI 1 - -/* The following table includes the supported baudrates */ -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} /*----------------------------------------------------------------------- * Environment @@ -202,10 +198,7 @@ /*----------------------------------------------------------------------- * I2C *----------------------------------------------------------------------*/ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F #define CFG_I2C_MULTI_EEPROMS #define CFG_I2C_EEPROM_ADDR (0xa8>>1) @@ -222,77 +215,24 @@ #define CFG_DTT_LOW_TEMP -30 #define CFG_DTT_HYSTERESIS 3 -#if 0 /* test-only... */ -/*----------------------------------------------------------------------- - * SPI stuff - Define to include SPI control - *----------------------------------------------------------------------- - */ -#define CONFIG_SPI -#endif - /*----------------------------------------------------------------------- * Ethernet *----------------------------------------------------------------------*/ -#define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 0 /* PHY address */ -#define CONFIG_NET_MULTI 1 -#define CFG_RX_ETH_BUFFER 16 /* # of rx buffers & descriptors*/ #define CONFIG_HAS_ETH0 1 -#define CONFIG_NETCONSOLE /* include NetConsole support */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define xstr(s) str(s) -#define str(s) #s - +/* + * Default environment variables + */ #define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "hostname=acadia\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ - "flash_nfs=run nfsargs addip addtty;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ - "bootm\0" \ - "rootpath=/opt/eldk/ppc_4xx\0" \ - "bootfile=acadia/uImage\0" \ + CONFIG_AMCC_DEF_ENV \ + CONFIG_AMCC_DEF_ENV_PPC \ + CONFIG_AMCC_DEF_ENV_NOR_UPD \ + CONFIG_AMCC_DEF_ENV_NAND_UPD \ "kernel_addr=fff10000\0" \ "ramdisk_addr=fff20000\0" \ - "initrd_high=30000000\0" \ - "load=tftp 200000 acadia/u-boot.bin\0" \ - "update=protect off " xstr(CFG_MONITOR_BASE) " FFFFFFFF;" \ - "era " xstr(CFG_MONITOR_BASE) " FFFFFFFF;" \ - "cp.b ${fileaddr} " xstr(CFG_MONITOR_BASE) " ${filesize};" \ - "setenv filesize;saveenv\0" \ - "upd=run load update\0" \ - "nload=tftp 200000 acadia/u-boot-nand.bin\0" \ - "nupdate=nand erase 0 60000;nand write 200000 0 60000;" \ - "setenv filesize;saveenv\0" \ - "nupd=run nload nupdate\0" \ "kozio=bootm ffc60000\0" \ "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ #define CONFIG_USB_OHCI #define CONFIG_USB_STORAGE @@ -305,35 +245,10 @@ #define CONFIG_SUPPORT_VFAT /* - * BOOTP options + * Commands additional to the ones defined in amcc-common.h */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DHCP #define CONFIG_CMD_DTT -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_ELF -#define CONFIG_CMD_FAT -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_MII #define CONFIG_CMD_NAND -#define CONFIG_CMD_NET -#define CONFIG_CMD_NFS -#define CONFIG_CMD_PCI -#define CONFIG_CMD_PING -#define CONFIG_CMD_REGINFO #define CONFIG_CMD_USB /* @@ -344,43 +259,6 @@ #undef CONFIG_CMD_IMLS #endif -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/*----------------------------------------------------------------------- - * Miscellaneous configurable options - *----------------------------------------------------------------------*/ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_LOOPW 1 /* enable loopw command */ -#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - /*----------------------------------------------------------------------- * NAND FLASH *----------------------------------------------------------------------*/ @@ -493,21 +371,4 @@ #define CFG_GPIO1_TSRL 0x00000000 #define CFG_GPIO1_TSRH 0x00000000 -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#if defined(CONFIG_CMD_KGDB) - #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ - #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 - #endif /* __CONFIG_H */ diff --git a/include/configs/bamboo.h b/include/configs/bamboo.h index 8d77164059..41058f88cf 100644 --- a/include/configs/bamboo.h +++ b/include/configs/bamboo.h @@ -36,6 +36,12 @@ #define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ +/* + * Include common defines/options for all AMCC eval boards + */ +#define CONFIG_HOSTNAME bamboo +#include "amcc-common.h" + #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ /* @@ -49,10 +55,6 @@ * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) *----------------------------------------------------------------------*/ -#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */ -#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ -#define CFG_MONITOR_BASE TEXT_BASE -#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ #define CFG_FLASH_BASE 0xfff00000 /* start of FLASH */ #define CFG_PCI_MEMBASE 0xa0000000 /* mapped pci memory*/ #define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000 @@ -84,14 +86,9 @@ * Serial Port *----------------------------------------------------------------------*/ #define CFG_EXT_SERIAL_CLOCK 11059200 /* use external 11.059MHz clk */ -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SERIAL_MULTI 1 /* define this if you want console on UART1 */ #undef CONFIG_UART1_CONSOLE -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - /*----------------------------------------------------------------------- * NVRAM/RTC * @@ -227,10 +224,7 @@ /*----------------------------------------------------------------------- * I2C *----------------------------------------------------------------------*/ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F #define CFG_I2C_MULTI_EEPROMS #define CFG_I2C_EEPROM_ADDR (0xa8>>1) @@ -244,54 +238,20 @@ #define CFG_ENV_OFFSET 0x0 #endif /* CFG_ENV_IS_IN_EEPROM */ -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - +/* + * Default environment variables + */ #define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "hostname=bamboo\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ - "flash_nfs=run nfsargs addip addtty;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ - "bootm\0" \ - "rootpath=/opt/eldk/ppc_4xx\0" \ - "bootfile=/tftpboot/bamboo/uImage\0" \ + CONFIG_AMCC_DEF_ENV \ + CONFIG_AMCC_DEF_ENV_POWERPC \ + CONFIG_AMCC_DEF_ENV_PPC_OLD \ + CONFIG_AMCC_DEF_ENV_NOR_UPD \ + CONFIG_AMCC_DEF_ENV_NAND_UPD \ "kernel_addr=fff00000\0" \ "ramdisk_addr=fff10000\0" \ - "initrd_high=30000000\0" \ - "load=tftp 100000 /tftpboot/bamboo/u-boot.bin\0" \ - "update=protect off fffa0000 ffffffff;era fffa0000 ffffffff;" \ - "cp.b 100000 fffa0000 60000;" \ - "setenv filesize;saveenv\0" \ - "upd=run load update\0" \ "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ #define CONFIG_HAS_ETH0 -#define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */ #define CONFIG_PHY1_ADDR 1 @@ -299,16 +259,6 @@ #define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ #endif /* CONFIG_BAMBOO_NAND */ -#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ - -#define CONFIG_NETCONSOLE /* include NetConsole support */ -#define CONFIG_NET_MULTI 1 /* required for netconsole */ - -/* Partitions */ -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION -#define CONFIG_ISO_PARTITION - #ifdef CONFIG_440EP /* USB */ #define CONFIG_USB_OHCI @@ -318,77 +268,27 @@ #define USB_2_0_DEVICE #endif /*CONFIG_440EP*/ - /* - * BOOTP options + * Commands additional to the ones defined in amcc-common.h */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - - -#define CONFIG_CMD_ASKENV #define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_ELF -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_MII -#define CONFIG_CMD_NET -#define CONFIG_CMD_NFS +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT #define CONFIG_CMD_PCI -#define CONFIG_CMD_PING -#define CONFIG_CMD_REGINFO #define CONFIG_CMD_SDRAM -#define CONFIG_CMD_USB -#define CONFIG_CMD_FAT -#define CONFIG_CMD_EXT2 #define CONFIG_CMD_SNTP +#define CONFIG_CMD_USB #ifdef CONFIG_BAMBOO_NAND #define CONFIG_CMD_NAND #endif - #define CONFIG_SUPPORT_VFAT -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ -#define CONFIG_LYNXKDI 1 /* support kdi files */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_LOOPW 1 /* enable loopw command */ -#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ +/* Partitions */ +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION +#define CONFIG_ISO_PARTITION /*----------------------------------------------------------------------- * PCI stuff @@ -407,28 +307,4 @@ #define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ #define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */ -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 - #endif /* __CONFIG_H */ diff --git a/include/configs/bubinga.h b/include/configs/bubinga.h index 75dd4e7e67..acce82f621 100644 --- a/include/configs/bubinga.h +++ b/include/configs/bubinga.h @@ -37,6 +37,12 @@ #define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_BUBINGA 1 /* ...on a BUBINGA board */ +/* + * Include common defines/options for all AMCC eval boards + */ +#define CONFIG_HOSTNAME bubinga +#include "amcc-common.h" + #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ @@ -80,117 +86,34 @@ #define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */ #endif -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - +/* + * Default environment variables + */ #define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "hostname=bubinga\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ - "flash_nfs=run nfsargs addip addtty;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ - "bootm\0" \ - "rootpath=/opt/eldk/ppc_4xx\0" \ - "bootfile=/tftpboot/bubinga/uImage\0" \ + CONFIG_AMCC_DEF_ENV \ + CONFIG_AMCC_DEF_ENV_PPC \ + CONFIG_AMCC_DEF_ENV_NOR_UPD \ "kernel_addr=fff80000\0" \ "ramdisk_addr=fff90000\0" \ - "initrd_high=30000000\0" \ - "load=tftp 100000 /tftpboot/bubinga/u-boot.bin\0" \ - "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ - "cp.b 100000 fffc0000 40000;" \ - "setenv filesize;saveenv\0" \ - "upd=run load update\0" \ "" -#define CONFIG_BOOTCOMMAND "run net_nfs" - -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#define CONFIG_BAUDRATE 115200 -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 1 /* PHY address */ #define CONFIG_HAS_ETH0 #define CONFIG_HAS_ETH1 #define CONFIG_PHY1_ADDR 2 /* EMAC1 PHY address */ -#define CONFIG_NET_MULTI 1 -#define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */ - -#define CONFIG_NETCONSOLE /* include NetConsole support */ #define CONFIG_RTC_DS174x 1 /* use DS1743 RTC in Bubinga */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - /* - * Command line configuration. + * Commands additional to the ones defined in amcc-common.h */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_CACHE #define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_ELF -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_MII -#define CONFIG_CMD_NET #define CONFIG_CMD_PCI -#define CONFIG_CMD_PING -#define CONFIG_CMD_REGINFO #define CONFIG_CMD_SDRAM #define CONFIG_CMD_SNTP - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - #define CONFIG_SPD_EEPROM 1 /* use SPD EEPROM for setup */ -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - /* * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1. * If CFG_405_UART_ERRATA_59, then UART divisor is 31. @@ -205,29 +128,11 @@ #undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ #define CFG_BASE_BAUD 691200 -/* The following table includes the supported baudrates */ -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_LOOPW 1 /* enable loopw command */ -#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ - /*----------------------------------------------------------------------- * I2C stuff *----------------------------------------------------------------------- */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F #define CFG_I2C_NOPROBES { 0x69 } /* avoid iprobe hangup (why?) */ #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 6 /* 24C02 requires 5ms delay */ @@ -272,21 +177,9 @@ /*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 */ -#define CFG_SDRAM_BASE 0x00000000 #define CFG_SRAM_BASE 0xFFF00000 #define CFG_FLASH_BASE 0xFFF80000 -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ -#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN) - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ /*----------------------------------------------------------------------- * FLASH organization @@ -423,21 +316,4 @@ #define FPGA_REG1_OFFB_FLASH 0x02 /* Off board flash */ #define FPGA_REG1_SRAM_BOOT 0x01 /* SRAM at 0xFFF80000 not Flash */ -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 - #endif /* __CONFIG_H */ diff --git a/include/configs/canyonlands.h b/include/configs/canyonlands.h index 3dd577aae7..ac2e5d99e0 100644 --- a/include/configs/canyonlands.h +++ b/include/configs/canyonlands.h @@ -30,12 +30,19 @@ /* This config file is used for Canyonlands (460EX) and Glacier (460GT) */ #ifndef CONFIG_CANYONLANDS #define CONFIG_460GT 1 /* Specific PPC460GT */ +#define CONFIG_HOSTNAME glacier #else #define CONFIG_460EX 1 /* Specific PPC460EX */ +#define CONFIG_HOSTNAME canyonlands #endif #define CONFIG_440 1 #define CONFIG_4xx 1 /* ... PPC4xx family */ +/* + * Include common defines/options for all AMCC eval boards + */ +#include "amcc-common.h" + #define CONFIG_SYS_CLK_FREQ 66666667 /* external freq to pll */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ @@ -47,8 +54,6 @@ * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) *----------------------------------------------------------------------*/ -#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ - #define CFG_PCI_MEMBASE 0x80000000 /* mapped PCI memory */ #define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */ #define CFG_PCI_TARGBASE CFG_PCI_MEMBASE @@ -86,10 +91,6 @@ #define CFG_AHB_BASE 0xE2000000 /* internal AHB peripherals */ -#define CFG_MONITOR_BASE TEXT_BASE -#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */ -#define CFG_MALLOC_LEN (512 * 1024) /* Reserve 512 kB for malloc()*/ - /*----------------------------------------------------------------------- * Initial RAM & stack pointer (placed in OCM) *----------------------------------------------------------------------*/ @@ -102,13 +103,8 @@ /*----------------------------------------------------------------------- * Serial Port *----------------------------------------------------------------------*/ -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SERIAL_MULTI 1 #undef CONFIG_UART1_CONSOLE /* define this if you want console on UART1 */ -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - /*----------------------------------------------------------------------- * Environment *----------------------------------------------------------------------*/ @@ -242,10 +238,7 @@ /*----------------------------------------------------------------------- * I2C *----------------------------------------------------------------------*/ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_SPEED 400000 /* I2C speed */ #define CFG_I2C_MULTI_EEPROMS #define CFG_I2C_EEPROM_ADDR (0xa8>>1) @@ -270,7 +263,6 @@ * Ethernet *----------------------------------------------------------------------*/ #define CONFIG_IBM_EMAC4_V4 1 -#define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */ #define CONFIG_PHY1_ADDR 1 #define CONFIG_HAS_ETH0 @@ -282,14 +274,11 @@ #define CONFIG_HAS_ETH2 #define CONFIG_HAS_ETH3 #endif -#define CONFIG_NET_MULTI 1 #define CONFIG_PHY_RESET 1 /* reset phy upon startup */ #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ #define CONFIG_PHY_DYNAMIC_ANEG 1 -#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ - /*----------------------------------------------------------------------- * USB-OHCI *----------------------------------------------------------------------*/ @@ -305,104 +294,30 @@ #define CFG_USB_OHCI_MAX_ROOT_PORTS 15 #endif -/*----------------------------------------------------------------------- - * Default environment - *----------------------------------------------------------------------*/ -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -/* Setup some board specific values for the default environment variables */ -#ifdef CONFIG_CANYONLANDS -#define CONFIG_HOSTNAME canyonlands -#define CFG_BOOTFILE "bootfile=canyonlands/uImage\0" -#define CFG_DTBFILE "fdt_file=canyonlands/canyonlands.dtb\0" -#define CFG_ROOTPATH "rootpath=/opt/eldk/ppc_4xxFP\0" -#else -#define CONFIG_HOSTNAME glacier -#define CFG_BOOTFILE "bootfile=glacier/uImage\0" -#define CFG_DTBFILE "fdt_file=glacier/glacier.dtb\0" -#define CFG_ROOTPATH "rootpath=/opt/eldk/ppc_4xx\0" -#endif - +/* + * Default environment variables + */ #define CONFIG_EXTRA_ENV_SETTINGS \ - CFG_BOOTFILE \ - CFG_DTBFILE \ - CFG_ROOTPATH \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ - "flash_self=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ - "flash_nfs=run nfsargs addip addtty;" \ - "bootm ${kernel_addr} - ${fdt_addr}\0" \ - "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ - "tftp ${fdt_addr_r} ${fdt_file}; " \ - "run nfsargs addip addtty;" \ - "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ - "kernel_addr_r=400000\0" \ - "fdt_addr_r=800000\0" \ + CONFIG_AMCC_DEF_ENV \ + CONFIG_AMCC_DEF_ENV_POWERPC \ + CONFIG_AMCC_DEF_ENV_NOR_UPD \ + CONFIG_AMCC_DEF_ENV_NAND_UPD \ "kernel_addr=fc000000\0" \ "fdt_addr=fc1e0000\0" \ "ramdisk_addr=fc200000\0" \ - "initrd_high=30000000\0" \ - "load=tftp 200000 ${hostname}/u-boot.bin\0" \ - "update=protect off fffa0000 ffffffff;era fffa0000 ffffffff;" \ - "cp.b ${fileaddr} fffa0000 ${filesize};" \ - "setenv filesize;saveenv\0" \ - "upd=run load update\0" \ - "nload=tftp 200000 ${hostname}/u-boot-nand.bin\0" \ - "nupdate=nand erase 0 100000;nand write 200000 0 100000;" \ - "setenv filesize;saveenv\0" \ - "nupd=run nload nupdate\0" \ "pciconfighost=1\0" \ "pcie_mode=RP:RP\0" \ "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE /* allow baudrate change */ /* - * BOOTP options + * Commands additional to the ones defined in amcc-common.h */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_SUBNETMASK - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV #define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP #define CONFIG_CMD_DTT -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_ELF -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_MII #define CONFIG_CMD_NAND -#define CONFIG_CMD_NET -#define CONFIG_CMD_NFS #define CONFIG_CMD_PCI -#define CONFIG_CMD_PING -#define CONFIG_CMD_REGINFO #define CONFIG_CMD_SDRAM +#define CONFIG_CMD_SNTP #ifdef CONFIG_460EX #define CONFIG_CMD_EXT2 #define CONFIG_CMD_FAT @@ -414,41 +329,6 @@ #define CONFIG_DOS_PARTITION #define CONFIG_ISO_PARTITION -/*----------------------------------------------------------------------- - * Miscellaneous configurable options - *----------------------------------------------------------------------*/ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ -#define CONFIG_LOOPW 1 /* enable loopw command */ -#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ -#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ - -#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - /*----------------------------------------------------------------------- * PCI stuff *----------------------------------------------------------------------*/ @@ -465,21 +345,6 @@ #define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */ #define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * Internal Definitions - */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - /*----------------------------------------------------------------------- * External Bus Controller (EBC) Setup *----------------------------------------------------------------------*/ @@ -671,8 +536,4 @@ } #endif -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 - #endif /* __CONFIG_H */ diff --git a/include/configs/ebony.h b/include/configs/ebony.h index b41fa175fe..df444d8e96 100644 --- a/include/configs/ebony.h +++ b/include/configs/ebony.h @@ -37,6 +37,12 @@ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ +/* + * Include common defines/options for all AMCC eval boards + */ +#define CONFIG_HOSTNAME ebony +#include "amcc-common.h" + /* * Define here the location of the environment variables (FLASH or NVRAM). * Note: DENX encourages to use redundant environment in FLASH. NVRAM is only @@ -54,7 +60,6 @@ *----------------------------------------------------------------------*/ #define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ #define CFG_FLASH_BASE 0xff800000 /* start of FLASH */ -#define CFG_MONITOR_BASE 0xfffc0000 /* start of monitor */ #define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */ #define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */ #define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */ @@ -73,18 +78,11 @@ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/ - /*----------------------------------------------------------------------- * Serial Port *----------------------------------------------------------------------*/ #undef CONFIG_SERIAL_SOFTWARE_FIFO #define CFG_EXT_SERIAL_CLOCK (1843200 * 6) /* Ext clk @ 11.059 MHz */ -#define CONFIG_BAUDRATE 115200 - -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400} /*----------------------------------------------------------------------- * NVRAM/RTC @@ -140,10 +138,7 @@ /*----------------------------------------------------------------------- * I2C *----------------------------------------------------------------------*/ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F #define CFG_I2C_MULTI_EEPROMS #define CFG_I2C_EEPROM_ADDR (0xa8>>1) @@ -152,125 +147,31 @@ #define CFG_EEPROM_PAGE_WRITE_BITS 3 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - +/* + * Default environment variables + */ #define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "hostname=ebony\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ - "flash_nfs=run nfsargs addip addtty;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ - "bootm\0" \ - "rootpath=/opt/eldk/ppc_4xx\0" \ - "bootfile=/tftpboot/ebony/uImage\0" \ + CONFIG_AMCC_DEF_ENV \ + CONFIG_AMCC_DEF_ENV_POWERPC \ + CONFIG_AMCC_DEF_ENV_PPC_OLD \ + CONFIG_AMCC_DEF_ENV_NOR_UPD \ "kernel_addr=ff800000\0" \ "ramdisk_addr=ff810000\0" \ - "initrd_high=30000000\0" \ - "load=tftp 100000 /tftpboot/ebony/u-boot.bin\0" \ - "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ - "cp.b 100000 fffc0000 40000;" \ - "setenv filesize;saveenv\0" \ - "upd=run load update\0" \ "" -#define CONFIG_BOOTCOMMAND "run flash_self" -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 8 /* PHY address */ #define CONFIG_HAS_ETH0 #define CONFIG_HAS_ETH1 #define CONFIG_PHY1_ADDR 9 /* EMAC1 PHY address */ -#define CONFIG_NET_MULTI 1 -#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ - -#define CONFIG_NETCONSOLE /* include NetConsole support */ - /* - * BOOTP options + * Commands additional to the ones defined in amcc-common.h */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV #define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_ELF -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_MII -#define CONFIG_CMD_NET -#define CONFIG_CMD_NFS #define CONFIG_CMD_PCI -#define CONFIG_CMD_PING -#define CONFIG_CMD_REGINFO #define CONFIG_CMD_SDRAM #define CONFIG_CMD_SNTP - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_LOOPW 1 /* enable loopw command */ -#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ - /*----------------------------------------------------------------------- * PCI stuff *----------------------------------------------------------------------- @@ -287,28 +188,4 @@ #define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ #define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 - #endif /* __CONFIG_H */ diff --git a/include/configs/katmai.h b/include/configs/katmai.h index 3c8186289a..d3789bd67a 100644 --- a/include/configs/katmai.h +++ b/include/configs/katmai.h @@ -38,6 +38,13 @@ #define CONFIG_440 1 /* ... PPC440 family */ #define CONFIG_440SPE 1 /* Specifc SPe support */ #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ +#define CFG_4xx_RESET_TYPE 0x2 /* use chip reset on this board */ + +/* + * Include common defines/options for all AMCC eval boards + */ +#define CONFIG_HOSTNAME katmai +#include "amcc-common.h" #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ #define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */ @@ -47,7 +54,6 @@ * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) *----------------------------------------------------------------------*/ -#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ #define CFG_FLASH_BASE 0xff000000 /* start of FLASH */ #define CFG_PERIPHERAL_BASE 0xa0000000 /* internal peripherals */ #define CFG_ISRAM_BASE 0x90000000 /* internal SRAM */ @@ -77,10 +83,6 @@ #define CFG_ACE_BASE 0xfe000000 /* Xilinx ACE controller - Compact Flash */ -#define CFG_MONITOR_BASE TEXT_BASE -#define CFG_MONITOR_LEN (0xFFFFFFFF - CFG_MONITOR_BASE + 1) -#define CFG_MALLOC_LEN (512 * 1024) /* Reserve 512 kB for malloc */ - /*----------------------------------------------------------------------- * Initial RAM & stack pointer (placed in internal SRAM) *----------------------------------------------------------------------*/ @@ -97,12 +99,8 @@ /*----------------------------------------------------------------------- * Serial Port *----------------------------------------------------------------------*/ -#define CONFIG_SERIAL_MULTI 1 #undef CONFIG_UART1_CONSOLE #undef CFG_EXT_SERIAL_CLOCK -#define CONFIG_BAUDRATE 115200 -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} /*----------------------------------------------------------------------- * DDR SDRAM @@ -116,10 +114,7 @@ /*----------------------------------------------------------------------- * I2C *----------------------------------------------------------------------*/ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 100000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F #define CONFIG_I2C_MULTI_BUS #define CONFIG_I2C_CMD_TREE @@ -171,139 +166,36 @@ *----------------------------------------------------------------------*/ #define CFG_ENV_IS_IN_FLASH 1 /* Environment uses flash */ -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define xstr(s) str(s) -#define str(s) #s - +/* + * Default environment variables + */ #define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "hostname=katmai\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ - "flash_nfs=run nfsargs addip addtty;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ - "bootm\0" \ - "net_nfs_fdt=tftp 200000 ${bootfile};" \ - "tftp ${fdt_addr} ${fdt_file};" \ - "run nfsargs addip addtty;" \ - "bootm 200000 - ${fdt_addr}\0" \ - "rootpath=/opt/eldk/ppc_4xx\0" \ - "bootfile=katmai/uImage\0" \ - "fdt_file=katmai/katmai.dtb\0" \ - "fdt_addr=400000\0" \ + CONFIG_AMCC_DEF_ENV \ + CONFIG_AMCC_DEF_ENV_POWERPC \ + CONFIG_AMCC_DEF_ENV_PPC_OLD \ + CONFIG_AMCC_DEF_ENV_NOR_UPD \ "kernel_addr=fff10000\0" \ "ramdisk_addr=fff20000\0" \ - "initrd_high=30000000\0" \ - "load=tftp 200000 katmai/u-boot.bin\0" \ - "update=protect off " xstr(CFG_MONITOR_BASE) " FFFFFFFF;" \ - "era " xstr(CFG_MONITOR_BASE) " FFFFFFFF;" \ - "cp.b ${fileaddr} " xstr(CFG_MONITOR_BASE) " ${filesize};" \ - "setenv filesize;saveenv\0" \ - "upd=run load update\0" \ "kozio=bootm ffc60000\0" \ "pciconfighost=1\0" \ "pcie_mode=RP:RP:RP\0" \ "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - /* - * Command line configuration. + * Commands additional to the ones defined in amcc-common.h */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_EEPROM #define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_DTT -#define CONFIG_CMD_ELF -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_MII -#define CONFIG_CMD_NET -#define CONFIG_CMD_NFS #define CONFIG_CMD_PCI -#define CONFIG_CMD_PING -#define CONFIG_CMD_REGINFO #define CONFIG_CMD_SDRAM #define CONFIG_CMD_SNTP #define CONFIG_IBM_EMAC4_V4 1 /* 440SPe has this EMAC version */ -#define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */ #define CONFIG_HAS_ETH0 #define CONFIG_PHY_RESET 1 /* reset phy upon startup */ #define CONFIG_PHY_RESET_DELAY 1000 #define CONFIG_CIS8201_PHY 1 /* Enable 'special' RGMII mode for Cicada phy */ #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ -#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ - -#define CONFIG_NETCONSOLE /* include NetConsole support */ -#define CONFIG_NET_MULTI /* needed for NetConsole */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#if defined(CONFIG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_LOOPW 1 /* enable loopw command */ -#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ - -#define CFG_4xx_RESET_TYPE 0x2 /* use chip reset on this board */ /*----------------------------------------------------------------------- * FLASH related @@ -435,28 +327,4 @@ #define CFG_GPIO_TCR GPIO_VAL(CFG_GPIO_RS232_FORCEOFF) #define CFG_GPIO_ODR 0 -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /*Initial Memory map for Linux*/ - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 - #endif /* __CONFIG_H */ diff --git a/include/configs/kilauea.h b/include/configs/kilauea.h index 205577faa6..9c1a3a4c1e 100644 --- a/include/configs/kilauea.h +++ b/include/configs/kilauea.h @@ -39,6 +39,12 @@ #define CONFIG_405EX 1 /* Specifc 405EX support*/ #define CONFIG_SYS_CLK_FREQ 33333333 /* ext frequency to pll */ +/* + * Include common defines/options for all AMCC eval boards + */ +#define CONFIG_HOSTNAME kilauea +#include "amcc-common.h" + #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ #define CONFIG_BOARD_EMAC_COUNT @@ -47,14 +53,10 @@ * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) *----------------------------------------------------------------------*/ -#define CFG_SDRAM_BASE 0x00000000 #define CFG_FLASH_BASE 0xFC000000 #define CFG_NAND_ADDR 0xF8000000 #define CFG_FPGA_BASE 0xF0000000 #define CFG_PERIPHERAL_BASE 0xEF600000 /* internal peripherals*/ -#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */ -#define CFG_MALLOC_LEN (512 * 1024) /* Reserve 512 kB for malloc() */ -#define CFG_MONITOR_BASE (TEXT_BASE) /*----------------------------------------------------------------------- * Initial RAM & Stack Pointer Configuration Options @@ -112,14 +114,9 @@ * Serial Port *----------------------------------------------------------------------*/ #define CFG_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */ -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SERIAL_MULTI 1 /* define this if you want console on UART1 */ #undef CONFIG_UART1_CONSOLE -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - /*----------------------------------------------------------------------- * Environment *----------------------------------------------------------------------*/ @@ -273,9 +270,7 @@ /*----------------------------------------------------------------------- * I2C *----------------------------------------------------------------------*/ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 6 /* 24C02 requires 5ms delay */ #define CFG_I2C_EEPROM_ADDR 0x52 /* I2C boot EEPROM (24C02BN) */ @@ -295,7 +290,6 @@ *----------------------------------------------------------------------*/ #define CONFIG_M88E1111_PHY 1 #define CONFIG_IBM_EMAC4_V4 1 -#define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */ #define CONFIG_PHY_RESET 1 /* reset phy upon startup */ @@ -303,102 +297,33 @@ #define CONFIG_HAS_ETH0 1 -#define CONFIG_NET_MULTI 1 #define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ #define CONFIG_PHY1_ADDR 2 -#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - +/* + * Default environment variables + */ #define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_AMCC_DEF_ENV \ + CONFIG_AMCC_DEF_ENV_POWERPC \ + CONFIG_AMCC_DEF_ENV_PPC_OLD \ + CONFIG_AMCC_DEF_ENV_NOR_UPD \ + CONFIG_AMCC_DEF_ENV_NAND_UPD \ "logversion=2\0" \ - "netdev=eth0\0" \ - "hostname=kilauea\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ - "flash_self_old=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "flash_self=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ - "flash_nfs_old=run nfsargs addip addtty;" \ - "bootm ${kernel_addr}\0" \ - "flash_nfs=run nfsargs addip addtty;" \ - "bootm ${kernel_addr} - ${fdt_addr}\0" \ - "net_nfs_old=tftp ${kernel_addr_r} ${bootfile};" \ - "run nfsargs addip addtty;bootm ${kernel_addr_r}\0" \ - "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ - "tftp ${fdt_addr_r} ${fdt_file}; " \ - "run nfsargs addip addtty;" \ - "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ - "rootpath=/opt/eldk/ppc_4xx\0" \ - "bootfile=kilauea/uImage\0" \ - "fdt_file=kilauea/kilauea.dtb\0" \ - "kernel_addr_r=400000\0" \ - "fdt_addr_r=800000\0" \ "kernel_addr=fc000000\0" \ "fdt_addr=fc1e0000\0" \ "ramdisk_addr=fc200000\0" \ - "initrd_high=30000000\0" \ - "load=tftp 200000 kilauea/u-boot.bin\0" \ - "update=protect off fffa0000 ffffffff;era fffa0000 ffffffff;" \ - "cp.b ${fileaddr} fffa0000 ${filesize};" \ - "setenv filesize;saveenv\0" \ - "upd=run load update\0" \ - "nload=tftp 200000 kilauea/u-boot-nand.bin\0" \ - "nupdate=nand erase 0 60000;nand write 200000 0 60000;" \ - "setenv filesize;saveenv\0" \ - "nupd=run nload nupdate\0" \ "pciconfighost=1\0" \ "pcie_mode=RP:RP\0" \ "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE /* allow baudrate change */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_SUBNETMASK /* - * Command line configuration. + * Commands additional to the ones defined in amcc-common.h */ -#include - -#define CONFIG_CMD_ASKENV #define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_DTT -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_ELF -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IRQ #define CONFIG_CMD_LOG -#define CONFIG_CMD_MII #define CONFIG_CMD_NAND -#define CONFIG_CMD_NET -#define CONFIG_CMD_NFS #define CONFIG_CMD_PCI -#define CONFIG_CMD_PING -#define CONFIG_CMD_REGINFO #define CONFIG_CMD_SNTP /* POST support */ @@ -417,37 +342,6 @@ #define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */ -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/*----------------------------------------------------------------------- - * Miscellaneous configurable options - *----------------------------------------------------------------------*/ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_LOOPW 1 /* enable loopw command */ -#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ -#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ - /*----------------------------------------------------------------------- * PCI stuff *----------------------------------------------------------------------*/ @@ -476,13 +370,6 @@ /* base address of inbound PCIe window */ #define CFG_PCIE_INBOUND_BASE 0x0000000000000000ULL -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - /*----------------------------------------------------------------------- * External Bus Controller (EBC) Setup *----------------------------------------------------------------------*/ @@ -556,19 +443,6 @@ } \ } -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - /*----------------------------------------------------------------------- * Some Kilauea stuff..., mainly fpga registers */ @@ -604,8 +478,4 @@ #define CFG_FPGA_USER_LED0 0x00000200 #define CFG_FPGA_USER_LED1 0x00000100 -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 - #endif /* __CONFIG_H */ diff --git a/include/configs/luan.h b/include/configs/luan.h index 41999d32f9..805cc59b30 100644 --- a/include/configs/luan.h +++ b/include/configs/luan.h @@ -37,6 +37,12 @@ #define CONFIG_440 1 #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ +/* + * Include common defines/options for all AMCC eval boards + */ +#define CONFIG_HOSTNAME luan +#include "amcc-common.h" + #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ @@ -44,11 +50,6 @@ * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) *----------------------------------------------------------------------*/ -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ -#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc */ -#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN) -#define CFG_SDRAM_BASE 0x00000000 /* MUST be zero */ - #define CFG_LARGE_FLASH 0xffc00000 /* 4MB flash address CS0 */ #define CFG_SMALL_FLASH 0xff900000 /* 1MB flash address CS2 */ #define CFG_SRAM_BASE 0xff800000 /* 1MB SRAM address CS2 */ @@ -87,13 +88,8 @@ * Serial Port *----------------------------------------------------------------------*/ #define CFG_EXT_SERIAL_CLOCK 11059200 /* external 11.059MHz clk */ -#define CONFIG_BAUDRATE 115200 -#undef CONFIG_SERIAL_MULTI #undef CONFIG_UART1_CONSOLE /* define if you want console on UART1 */ -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - /*----------------------------------------------------------------------- * Environment *----------------------------------------------------------------------*/ @@ -138,10 +134,7 @@ /*----------------------------------------------------------------------- * I2C *----------------------------------------------------------------------*/ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F #define CFG_I2C_MULTI_EEPROMS #define CFG_I2C_EEPROM_ADDR (0xa8>>1) @@ -150,61 +143,22 @@ #define CFG_EEPROM_PAGE_WRITE_BITS 3 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "hostname=luan\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$(serverip):$(rootpath)\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs $(bootargs) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ - ":$(hostname):$(netdev):off panic=1\0" \ - "addtty=setenv bootargs $(bootargs) console=ttyS0,$(baudrate)\0"\ - "flash_nfs=run nfsargs addip addtty;" \ - "bootm $(kernel_addr)\0" \ - "flash_self=run ramargs addip addtty;" \ - "bootm $(kernel_addr) $(ramdisk_addr)\0" \ - "net_nfs=tftp 200000 $(bootfile);run nfsargs addip addtty;" \ - "bootm\0" \ - "rootpath=/opt/eldk/ppc_4xx\0" \ - "bootfile=/tftpboot/luan/uImage\0" \ +/* + * Default environment variables + */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_AMCC_DEF_ENV \ + CONFIG_AMCC_DEF_ENV_PPC \ + CONFIG_AMCC_DEF_ENV_NOR_UPD \ "kernel_addr=fc000000\0" \ "ramdisk_addr=fc100000\0" \ - "initrd_high=30000000\0" \ - "load=tftp 100000 /tftpboot/luan/u-boot.bin\0" \ - "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ - "cp.b 100000 fffc0000 40000;" \ - "setenv filesize;saveenv\0" \ - "upd=run load update\0" \ "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ #define CONFIG_HAS_ETH0 -#define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 1 #define CONFIG_CIS8201_PHY 1 /* Enable 'special' RGMII mode for Cicada phy */ #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ -#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ - -#define CONFIG_NETCONSOLE /* include NetConsole support */ -#define CONFIG_NET_MULTI /* needed for NetConsole */ - #ifdef DEBUG #define CONFIG_PANIC_HANG #else @@ -212,60 +166,11 @@ #endif /* - * BOOTP options + * Commands additional to the ones defined in amcc-common.h */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_MII -#define CONFIG_CMD_NET -#define CONFIG_CMD_NFS #define CONFIG_CMD_PCI -#define CONFIG_CMD_PING -#define CONFIG_CMD_REGINFO #define CONFIG_CMD_SDRAM -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ -#undef CONFIG_LYNXKDI /* support kdi files */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_LOOPW 1 /* enable loopw command */ -#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ - /*----------------------------------------------------------------------- * PCI stuff *----------------------------------------------------------------------- @@ -286,28 +191,4 @@ #endif -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 - #endif /* __CONFIG_H */ diff --git a/include/configs/makalu.h b/include/configs/makalu.h index 566e611c79..65b240e0f1 100644 --- a/include/configs/makalu.h +++ b/include/configs/makalu.h @@ -39,6 +39,13 @@ #define CONFIG_405EX 1 /* Specifc 405EX support*/ #define CONFIG_SYS_CLK_FREQ 33330000 /* ext frequency to pll */ +/* + * Include common defines/options for all AMCC eval boards + */ +#define CONFIG_HOSTNAME makalu +#define CONFIG_ADDMISC "addmisc=setenv bootargs ${bootargs} rtc-x1205.probe=0,0x6f\0" +#include "amcc-common.h" + #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ @@ -46,13 +53,9 @@ * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) *----------------------------------------------------------------------*/ -#define CFG_SDRAM_BASE 0x00000000 #define CFG_FLASH_BASE 0xFC000000 #define CFG_FPGA_BASE 0xF0000000 #define CFG_PERIPHERAL_BASE 0xEF600000 /* internal peripherals*/ -#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */ -#define CFG_MALLOC_LEN (512 * 1024) /* Reserve 512 kB for malloc() */ -#define CFG_MONITOR_BASE (TEXT_BASE) /*----------------------------------------------------------------------- * Initial RAM & Stack Pointer Configuration Options @@ -110,14 +113,9 @@ * Serial Port *----------------------------------------------------------------------*/ #undef CFG_EXT_SERIAL_CLOCK /* no ext. clk */ -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SERIAL_MULTI 1 /* define this if you want console on UART1 */ #undef CONFIG_UART1_CONSOLE -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - /*----------------------------------------------------------------------- * Environment *----------------------------------------------------------------------*/ @@ -205,9 +203,7 @@ /*----------------------------------------------------------------------- * I2C *----------------------------------------------------------------------*/ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 6 /* 24C02 requires 5ms delay */ #define CFG_I2C_EEPROM_ADDR 0x52 /* I2C boot EEPROM (24C02BN) */ @@ -227,7 +223,6 @@ *----------------------------------------------------------------------*/ #define CONFIG_M88E1111_PHY 1 #define CONFIG_IBM_EMAC4_V4 1 -#define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 6 /* PHY address, See schematics */ #define CONFIG_PHY_RESET 1 /* reset phy upon startup */ @@ -235,99 +230,31 @@ #define CONFIG_HAS_ETH0 1 -#define CONFIG_NET_MULTI 1 #define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ #define CONFIG_PHY1_ADDR 0 -#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - +/* + * Default environment variables + */ #define CONFIG_EXTRA_ENV_SETTINGS \ - "logversion=2\0" \ - "netdev=eth0\0" \ - "hostname=makalu\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ - "addmisc=setenv bootargs ${bootargs} rtc-x1205.probe=0,0x6f\0" \ - "flash_self_old=run ramargs addip addtty addmisc;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "flash_self=run ramargs addip addtty addmisc;" \ - "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ - "flash_nfs_old=run nfsargs addip addtty addmisc;" \ - "bootm ${kernel_addr}\0" \ - "flash_nfs=run nfsargs addip addtty addmisc;" \ - "bootm ${kernel_addr} - ${fdt_addr}\0" \ - "net_nfs_old=tftp ${kernel_addr_r} ${bootfile};" \ - "run nfsargs addip addtty addmisc;" \ - "bootm ${kernel_addr_r}\0" \ - "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ - "tftp ${fdt_addr_r} ${fdt_file}; " \ - "run nfsargs addip addtty addmisc;" \ - "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ - "rootpath=/opt/eldk/ppc_4xx\0" \ - "bootfile=makalu/uImage\0" \ - "fdt_file=makalu/makalu.dtb\0" \ - "kernel_addr_r=400000\0" \ - "fdt_addr_r=800000\0" \ + CONFIG_AMCC_DEF_ENV \ + CONFIG_AMCC_DEF_ENV_POWERPC \ + CONFIG_AMCC_DEF_ENV_PPC_OLD \ + CONFIG_AMCC_DEF_ENV_NOR_UPD \ "kernel_addr=fc000000\0" \ "fdt_addr=fc1e0000\0" \ "ramdisk_addr=fc200000\0" \ - "initrd_high=30000000\0" \ - "load=tftp 200000 makalu/u-boot.bin\0" \ - "update=protect off fffa0000 ffffffff;era fffa0000 ffffffff;" \ - "cp.b ${fileaddr} fffa0000 ${filesize};" \ - "setenv filesize;saveenv\0" \ - "upd=run load update\0" \ "pciconfighost=1\0" \ "pcie_mode=RP:RP\0" \ "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE /* allow baudrate change */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_SUBNETMASK /* - * Command line configuration. + * Commands additional to the ones defined in amcc-common.h */ -#include - -#define CONFIG_CMD_ASKENV #define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DIAG #define CONFIG_CMD_DTT -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_ELF -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IRQ #define CONFIG_CMD_LOG -#define CONFIG_CMD_MII -#define CONFIG_CMD_NET -#define CONFIG_CMD_NFS #define CONFIG_CMD_PCI -#define CONFIG_CMD_PING -#define CONFIG_CMD_REGINFO #define CONFIG_CMD_SNTP /* POST support */ @@ -346,37 +273,6 @@ #define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */ -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/*----------------------------------------------------------------------- - * Miscellaneous configurable options - *----------------------------------------------------------------------*/ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_LOOPW 1 /* enable loopw command */ -#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ -#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ - /*----------------------------------------------------------------------- * PCI stuff *----------------------------------------------------------------------*/ @@ -405,13 +301,6 @@ /* base address of inbound PCIe window */ #define CFG_PCIE_INBOUND_BASE 0x0000000000000000ULL -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - /*----------------------------------------------------------------------- * External Bus Controller (EBC) Setup *----------------------------------------------------------------------*/ @@ -470,21 +359,4 @@ #define CFG_GPIO_PCIE_CLKREQ 27 #define CFG_GPIO_PCIE_WAKE 28 -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 - #endif /* __CONFIG_H */ -- cgit From 72675dc6c06a48846d180106161d49dd714383cc Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 6 Jun 2008 15:55:21 +0200 Subject: ppc4xx: Unify AMCC's board config files (part 3/3) This patch series unifies the AMCC eval board ports by introducing a common include header for all AMCC eval boards: include/configs/amcc-common.h This header now includes all common configuration options/defines which are removed from the board specific headers. The reason for this is ease of maintenance and unified look and feel of all AMCC boards. Signed-off-by: Stefan Roese --- include/configs/ocotea.h | 151 ++++----------------------------------- include/configs/sequoia.h | 173 +++++---------------------------------------- include/configs/taihu.h | 146 ++++---------------------------------- include/configs/taishan.h | 160 ++++------------------------------------- include/configs/walnut.h | 155 ++++------------------------------------ include/configs/yosemite.h | 164 ++++-------------------------------------- include/configs/yucca.h | 151 ++++----------------------------------- 7 files changed, 101 insertions(+), 999 deletions(-) (limited to 'include/configs') diff --git a/include/configs/ocotea.h b/include/configs/ocotea.h index 1ec7a253fc..407aae7210 100644 --- a/include/configs/ocotea.h +++ b/include/configs/ocotea.h @@ -46,13 +46,17 @@ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ +/* + * Include common defines/options for all AMCC eval boards + */ +#define CONFIG_HOSTNAME ocotea +#include "amcc-common.h" + /*----------------------------------------------------------------------- * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) *----------------------------------------------------------------------*/ -#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ #define CFG_FLASH_BASE 0xff800000 /* start of FLASH */ -#define CFG_MONITOR_BASE 0xfffc0000 /* start of monitor */ #define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */ #define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */ #define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */ @@ -74,18 +78,11 @@ #define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4) #define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/ - /*----------------------------------------------------------------------- * Serial Port *----------------------------------------------------------------------*/ #undef CONFIG_SERIAL_SOFTWARE_FIFO #define CFG_EXT_SERIAL_CLOCK (1843200 * 6) /* Ext clk @ 11.059 MHz */ -#define CONFIG_BAUDRATE 115200 - -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} /*----------------------------------------------------------------------- * Environment @@ -155,10 +152,7 @@ /*----------------------------------------------------------------------- * I2C *----------------------------------------------------------------------*/ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F #define CFG_I2C_MULTI_EEPROMS #define CFG_I2C_EEPROM_ADDR (0xa8>>1) @@ -167,54 +161,17 @@ #define CFG_EEPROM_PAGE_WRITE_BITS 3 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - +/* + * Default environment variables + */ #define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "hostname=ocotea\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ - "flash_nfs=run nfsargs addip addtty;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ - "bootm\0" \ - "rootpath=/opt/eldk/ppc_4xx\0" \ - "bootfile=/tftpboot/ocotea/uImage\0" \ + CONFIG_AMCC_DEF_ENV \ + CONFIG_AMCC_DEF_ENV_PPC \ + CONFIG_AMCC_DEF_ENV_NOR_UPD \ "kernel_addr=fff00000\0" \ "ramdisk_addr=fff10000\0" \ - "initrd_high=30000000\0" \ - "load=tftp 100000 /tftpboot/ocotea/u-boot.bin\0" \ - "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ - "cp.b 100000 fffc0000 40000;" \ - "setenv filesize;saveenv\0" \ - "upd=run load update\0" \ "" -#define CONFIG_BOOTCOMMAND "run flash_self" -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_NET_MULTI 1 #define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */ #define CONFIG_PHY1_ADDR 2 #define CONFIG_PHY2_ADDR 0x10 @@ -227,73 +184,15 @@ #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ #define CONFIG_PHY_RESET 1 /* reset phy upon startup */ #define CONFIG_PHY_RESET_DELAY 1000 -#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ - -#define CONFIG_NETCONSOLE /* include NetConsole support */ - /* - * BOOTP options + * Commands additional to the ones defined in amcc-common.h */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV #define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_ELF -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_MII -#define CONFIG_CMD_NET -#define CONFIG_CMD_NFS #define CONFIG_CMD_PCI -#define CONFIG_CMD_PING -#define CONFIG_CMD_REGINFO #define CONFIG_CMD_SDRAM #define CONFIG_CMD_SNTP - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_LOOPW 1 /* enable loopw command */ -#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ - /*----------------------------------------------------------------------- * PCI stuff *----------------------------------------------------------------------- @@ -310,28 +209,4 @@ #define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ #define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 - #endif /* __CONFIG_H */ diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h index 48251f3948..f4eefae2f4 100644 --- a/include/configs/sequoia.h +++ b/include/configs/sequoia.h @@ -34,11 +34,19 @@ /* This config file is used for Sequoia (440EPx) and Rainier (440GRx) */ #ifndef CONFIG_RAINIER #define CONFIG_440EPX 1 /* Specific PPC440EPx */ +#define CONFIG_HOSTNAME sequoia #else #define CONFIG_440GRX 1 /* Specific PPC440GRx */ +#define CONFIG_HOSTNAME rainier #endif #define CONFIG_440 1 /* ... PPC440 family */ #define CONFIG_4xx 1 /* ... PPC4xx family */ + +/* + * Include common defines/options for all AMCC eval boards + */ +#include "amcc-common.h" + /* Detect Sequoia PLL input clock automatically via CPLD bit */ #define CONFIG_SYS_CLK_FREQ ((in8(CFG_BCSR_BASE + 3) & 0x80) ? \ 33333333 : 33000000) @@ -64,19 +72,9 @@ * Base addresses -- Note these are effective addresses where the actual * resources get mapped (not physical addresses). */ -#ifndef CONFIG_VIDEO -#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kiB for Monitor */ -#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kiB for malloc() */ -#else -#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */ -#define CFG_MALLOC_LEN (1024 * 1024) /* Reserve 1024 kB for malloc() */ -#endif - #define CFG_TLB_FOR_BOOT_FLASH 0x0003 #define CFG_BOOT_BASE_ADDR 0xf0000000 -#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ #define CFG_FLASH_BASE 0xfc000000 /* start of FLASH */ -#define CFG_MONITOR_BASE TEXT_BASE #define CFG_NAND_ADDR 0xd0000000 /* NAND Flash */ #define CFG_OCM_BASE 0xe0010000 /* ocm */ #define CFG_OCM_DATA_ADDR CFG_OCM_BASE @@ -108,14 +106,9 @@ * Serial Port */ #define CFG_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */ -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SERIAL_MULTI 1 /* define this if you want console on UART1 */ #undef CONFIG_UART1_CONSOLE -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - /* * Environment */ @@ -227,10 +220,7 @@ /* * I2C */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F #define CFG_I2C_MULTI_EEPROMS #define CFG_I2C_EEPROM_ADDR (0xa8>>1) @@ -247,80 +237,27 @@ #define CFG_DTT_LOW_TEMP -30 #define CFG_DTT_HYSTERESIS 3 -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -/* Setup some board specific values for the default environment variables */ -#ifndef CONFIG_RAINIER -#define CONFIG_HOSTNAME sequoia -#define CFG_BOOTFILE "bootfile=sequoia/uImage\0" -#define CFG_DTBFILE "fdt_file=sequoia/sequoia.dtb\0" -#define CFG_ROOTPATH "rootpath=/opt/eldk/ppc_4xxFP\0" -#else -#define CONFIG_HOSTNAME rainier -#define CFG_BOOTFILE "bootfile=rainier/uImage\0" -#define CFG_DTBFILE "fdt_file=rainier/rainier.dtb\0" -#define CFG_ROOTPATH "rootpath=/opt/eldk/ppc_4xx\0" -#endif - +/* + * Default environment variables + */ #define CONFIG_EXTRA_ENV_SETTINGS \ - CFG_BOOTFILE \ - CFG_ROOTPATH \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ - "addmisc=setenv bootargs ${bootargs}\0" \ - "flash_nfs=run nfsargs addip addtty addmisc;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addtty addmisc;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};" \ - "run nfsargs addip addtty addmisc;" \ - "bootm\0" \ - "fdt_file=sequoia/sequoia.dtb\0" \ - "fdt_addr=400000\0" \ - "net_nfs_fdt=tftp 200000 ${bootfile};" \ - "tftp ${fdt_addr} ${fdt_file};" \ - "run nfsargs addip addtty addmisc;" \ - "bootm 200000 - ${fdt_addr}\0" \ + CONFIG_AMCC_DEF_ENV \ + CONFIG_AMCC_DEF_ENV_POWERPC \ + CONFIG_AMCC_DEF_ENV_PPC_OLD \ + CONFIG_AMCC_DEF_ENV_NOR_UPD \ + CONFIG_AMCC_DEF_ENV_NAND_UPD \ "kernel_addr=FC000000\0" \ "ramdisk_addr=FC180000\0" \ - "load=tftp 200000 /tftpboot/${hostname}/u-boot.bin\0" \ - "update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;" \ - "cp.b 200000 FFFA0000 60000\0" \ - "upd=run load update\0" \ "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ #define CONFIG_M88E1111_PHY 1 #define CONFIG_IBM_EMAC4_V4 1 -#define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */ #define CONFIG_PHY_RESET 1 /* reset phy upon startup */ #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ #define CONFIG_HAS_ETH0 -#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx */ - /* buffers & descriptors */ -#define CONFIG_NET_MULTI 1 #define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ #define CONFIG_PHY1_ADDR 1 @@ -347,35 +284,12 @@ #define CONFIG_ISO_PARTITION /* - * BOOTP options + * Commands additional to the ones defined in amcc-common.h */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_SUBNETMASK - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DHCP #define CONFIG_CMD_DTT -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_ELF #define CONFIG_CMD_FAT -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_MII #define CONFIG_CMD_NAND -#define CONFIG_CMD_NET -#define CONFIG_CMD_NFS #define CONFIG_CMD_PCI -#define CONFIG_CMD_PING -#define CONFIG_CMD_REGINFO #define CONFIG_CMD_SDRAM #ifdef CONFIG_440EPX @@ -406,35 +320,6 @@ #define CONFIG_SUPPORT_VFAT -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) - /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_LOOPW 1 /* enable loopw command */ -#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ - /* * PCI stuff */ @@ -452,13 +337,6 @@ #define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ #define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */ -/* - * For booting Linux, the board info and command line data have to be in the - * first 8 MB of memory, since this is the maximum mapped by the Linux kernel - * during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - /* * External Bus Controller (EBC) Setup */ @@ -577,23 +455,6 @@ } \ } -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 - #ifdef CONFIG_VIDEO #define CONFIG_BIOSEMU /* x86 bios emulator for vga bios */ #define CONFIG_ATI_RADEON_FB /* use radeon framebuffer driver */ diff --git a/include/configs/taihu.h b/include/configs/taihu.h index c060b1e340..86f776df20 100644 --- a/include/configs/taihu.h +++ b/include/configs/taihu.h @@ -32,6 +32,12 @@ #define CONFIG_4xx 1 /* member of PPC4xx family */ #define CONFIG_TAIHU 1 /* on a taihu board */ +/* + * Include common defines/options for all AMCC eval boards + */ +#define CONFIG_HOSTNAME taihu +#include "amcc-common.h" + #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f */ #define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */ @@ -70,87 +76,31 @@ #define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ -#define CONFIG_ENV_OVERWRITE 1 -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS -#define CONFIG_EXTRA_ENV_SETTINGS \ - "bootfile=/tftpboot/taihu/uImage\0" \ - "rootpath=/opt/eldk/ppc_4xx\0" \ - "netdev=eth0\0" \ - "hostname=taihu\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ - "flash_nfs=run nfsargs addip addtty;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ - "bootm\0" \ +/* + * Default environment variables + */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_AMCC_DEF_ENV \ + CONFIG_AMCC_DEF_ENV_PPC \ + CONFIG_AMCC_DEF_ENV_NOR_UPD \ "kernel_addr=FC000000\0" \ "ramdisk_addr=FC180000\0" \ - "load=tftp 200000 /tftpboot/taihu/u-boot.bin\0" \ - "update=protect off FFFC0000 FFFFFFFF;era FFFC0000 FFFFFFFF;" \ - "cp.b 200000 FFFC0000 40000\0" \ - "upd=run load update\0" \ "" -#define CONFIG_BOOTCOMMAND "run flash_self" -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 0x14 /* PHY address */ #define CONFIG_HAS_ETH0 #define CONFIG_HAS_ETH1 #define CONFIG_PHY1_ADDR 0x10 /* EMAC1 PHY address */ -#define CONFIG_NET_MULTI 1 -#define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */ #define CONFIG_PHY_RESET 1 /* - * BOOTP options + * Commands additional to the ones defined in amcc-common.h */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV #define CONFIG_CMD_CACHE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_ELF -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_MII -#define CONFIG_CMD_NET #define CONFIG_CMD_PCI -#define CONFIG_CMD_PING -#define CONFIG_CMD_REGINFO #define CONFIG_CMD_SDRAM #define CONFIG_CMD_SPI -#undef CONFIG_WATCHDOG /* watchdog disabled */ - #undef CONFIG_SPD_EEPROM /* use SPD EEPROM for setup */ #define CFG_SDRAM_SIZE_PER_BANK 0x04000000 /* 64MB */ #define CFG_SDRAM_BANKS 2 @@ -168,23 +118,6 @@ #define CFG_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */ #define CFG_SDRAM_tRFC 66 /* Auto refresh period */ -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* print buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - /* * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1. * If CFG_405_UART_ERRATA_59, then UART divisor is 31. @@ -198,35 +131,13 @@ #undef CFG_EXT_SERIAL_CLOCK /* external serial clock */ #undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ #define CFG_BASE_BAUD 691200 - -#define CONFIG_BAUDRATE 115200 - #define CONFIG_UART1_CONSOLE 1 -/* The following table includes the supported baudrates */ -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_LOOPW 1 /* enable loopw command */ -#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ -#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ - /*----------------------------------------------------------------------- * I2C stuff *----------------------------------------------------------------------- */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F #define CFG_I2C_NOPROBES { 0x69 } /* avoid iprobe hangup (why?) */ #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 6 /* 24C02 requires 5ms delay */ @@ -278,25 +189,12 @@ unsigned char spi_read(void); /*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 */ -#define CFG_SDRAM_BASE 0x00000000 #define CFG_FLASH_BASE 0xFFE00000 -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ -#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN) - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ /*----------------------------------------------------------------------- * FLASH organization */ - #define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ #define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ @@ -421,21 +319,5 @@ unsigned char spi_read(void); #define CPLD_REG0_ADDR 0x50100000 #define CPLD_REG1_ADDR 0x50100001 -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 #endif /* __CONFIG_H */ diff --git a/include/configs/taishan.h b/include/configs/taishan.h index 7b084cb78e..ba421925ed 100644 --- a/include/configs/taishan.h +++ b/include/configs/taishan.h @@ -34,6 +34,13 @@ #define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ +/* + * Include common defines/options for all AMCC eval boards + */ +#define CONFIG_HOSTNAME taishan +#define CONFIG_USE_TTY ttyS1 +#include "amcc-common.h" + #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ @@ -41,9 +48,7 @@ * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) *----------------------------------------------------------------------*/ -#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ #define CFG_FLASH_BASE 0xfc000000 /* start of FLASH */ -#define CFG_MONITOR_BASE 0xfffc0000 /* start of monitor */ #define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */ #define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */ #define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */ @@ -69,19 +74,11 @@ #define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4) #define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon*/ -#define CFG_MALLOC_LEN (1024 * 1024) /* Reserve 1024 kB for malloc*/ - /*----------------------------------------------------------------------- * Serial Port *----------------------------------------------------------------------*/ #define CONFIG_UART1_CONSOLE 1 /* use of UART1 as console */ -#define CONFIG_SERIAL_MULTI 1 /* enable serial multi support */ #define CFG_EXT_SERIAL_CLOCK (1843200 * 6) /* Ext clk @ 11.059 MHz */ -#define CONFIG_BAUDRATE 115200 - -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} /*----------------------------------------------------------------------- * Environment @@ -137,10 +134,7 @@ /*----------------------------------------------------------------------- * I2C *----------------------------------------------------------------------*/ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F #undef CFG_I2C_MULTI_EEPROMS #define CFG_I2C_EEPROM_ADDR 0x50 @@ -158,65 +152,23 @@ #define CFG_DTT_LOW_TEMP -30 #define CFG_DTT_HYSTERESIS 3 -/*----------------------------------------------------------------------- - * Environment - *----------------------------------------------------------------------*/ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - +/* + * Default environment variables + */ #define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "hostname=taishan\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0"\ - "flash_nfs=run nfsargs addip addtty;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ - "bootm\0" \ - "rootpath=/opt/eldk/ppc_4xx\0" \ - "bootfile=/tftpboot/taishan/uImage\0" \ + CONFIG_AMCC_DEF_ENV \ + CONFIG_AMCC_DEF_ENV_POWERPC \ + CONFIG_AMCC_DEF_ENV_PPC_OLD \ + CONFIG_AMCC_DEF_ENV_NOR_UPD \ "kernel_addr=fc000000\0" \ "ramdisk_addr=fc180000\0" \ - "initrd_high=30000000\0" \ - "load=tftp 100000 /tftpboot/taishan/u-boot.bin\0" \ - "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ - "cp.b 100000 fffc0000 40000;" \ - "setenv filesize;saveenv\0" \ - "upd=run load update\0" \ - "fixedip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip):" \ - "$(gatewayip):$(netmask):$(hostname):$(netdev):off panic=1\0" \ - "dhcp=setenv bootargs $(bootargs) ip=dhcp\0" \ "kozio=bootm 0xffe00000\0" \ "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#define CONFIG_BAUDRATE 115200 -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ /*----------------------------------------------------------------------- * Networking *----------------------------------------------------------------------*/ #define CONFIG_EMAC_NR_START 2 /* start with EMAC 2 (skip 0&1) */ -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_NET_MULTI 1 #define CONFIG_PHY_ADDR 0xff /* no phy on EMAC0 */ #define CONFIG_PHY1_ADDR 0xff /* no phy on EMAC1 */ #define CONFIG_PHY2_ADDR 0x1 @@ -229,70 +181,12 @@ #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ #define CONFIG_PHY_RESET 1 /* reset phy upon startup */ #define CONFIG_PHY_RESET_DELAY 1000 -#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ - -#define CONFIG_NETCONSOLE /* include NetConsole support */ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - /* - * Command line configuration. + * Commands additional to the ones defined in amcc-common.h */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DIAG #define CONFIG_CMD_DTT -#define CONFIG_CMD_ELF -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_MII -#define CONFIG_CMD_NET -#define CONFIG_CMD_NFS #define CONFIG_CMD_PCI -#define CONFIG_CMD_PING -#define CONFIG_CMD_REGINFO - - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/*----------------------------------------------------------------------- - * Miscellaneous configurable options - *----------------------------------------------------------------------*/ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_LOOPW 1 /* enable loopw command */ -#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ /*----------------------------------------------------------------------- * PCI stuff @@ -311,28 +205,4 @@ #define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ #define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 - #endif /* __CONFIG_H */ diff --git a/include/configs/walnut.h b/include/configs/walnut.h index adc420b9ad..e19c5f3482 100644 --- a/include/configs/walnut.h +++ b/include/configs/walnut.h @@ -38,121 +38,43 @@ #define CONFIG_WALNUT 1 /* ...on a WALNUT board */ /* ...and on a SYCAMORE board */ +/* + * Include common defines/options for all AMCC eval boards + */ +#define CONFIG_HOSTNAME walnut +#include "amcc-common.h" + #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "hostname=walnut\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ - "flash_nfs=run nfsargs addip addtty;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ - "bootm\0" \ - "rootpath=/opt/eldk/ppc_4xx\0" \ - "bootfile=/tftpboot/walnut/uImage\0" \ +/* + * Default environment variables + */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_AMCC_DEF_ENV \ + CONFIG_AMCC_DEF_ENV_POWERPC \ + CONFIG_AMCC_DEF_ENV_PPC_OLD \ + CONFIG_AMCC_DEF_ENV_NOR_UPD \ "kernel_addr=fff80000\0" \ "ramdisk_addr=fff80000\0" \ - "initrd_high=30000000\0" \ - "load=tftp 100000 /tftpboot/walnut/u-boot.bin\0" \ - "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ - "cp.b 100000 fffc0000 40000;" \ - "setenv filesize;saveenv\0" \ - "upd=run load update\0" \ "" -#define CONFIG_BOOTCOMMAND "run net_nfs" - -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ -#define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 1 /* PHY address */ - -#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ #define CONFIG_HAS_ETH0 1 -#define CONFIG_NETCONSOLE /* include NetConsole support */ -#define CONFIG_NET_MULTI /* needed for NetConsole */ - #define CONFIG_RTC_DS174x 1 /* use DS1743 RTC in Walnut */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - /* - * Command line configuration. + * Commands additional to the ones defined in amcc-common.h */ -#include - -#define CONFIG_CMD_ASKENV #define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_ELF -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_MII -#define CONFIG_CMD_NET -#define CONFIG_CMD_NFS #define CONFIG_CMD_PCI -#define CONFIG_CMD_PING -#define CONFIG_CMD_REGINFO #define CONFIG_CMD_SDRAM #define CONFIG_CMD_SNTP - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - #define CONFIG_SPD_EEPROM 1 /* use SPD EEPROM for setup */ -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - /* * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1. * If CFG_405_UART_ERRATA_59, then UART divisor is 31. @@ -167,29 +89,11 @@ #undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ #define CFG_BASE_BAUD 691200 -/* The following table includes the supported baudrates */ -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_LOOPW 1 /* enable loopw command */ -#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ - /*----------------------------------------------------------------------- * I2C stuff *----------------------------------------------------------------------- */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F #define CFG_I2C_MULTI_EEPROMS #define CFG_I2C_EEPROM_ADDR (0xa8>>1) @@ -224,13 +128,8 @@ /*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 */ -#define CFG_SDRAM_BASE 0x00000000 #define CFG_FLASH_BASE 0xFFF80000 -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ -#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN) /* * Define here the location of the environment variables (FLASH or NVRAM). @@ -243,13 +142,6 @@ #define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */ #endif -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - /*----------------------------------------------------------------------- * FLASH organization */ @@ -335,21 +227,4 @@ */ #define SPD_EEPROM_ADDRESS 0x50 -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 - #endif /* __CONFIG_H */ diff --git a/include/configs/yosemite.h b/include/configs/yosemite.h index f22e79824c..891b515d4e 100644 --- a/include/configs/yosemite.h +++ b/include/configs/yosemite.h @@ -42,6 +42,11 @@ #define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */ +/* + * Include common defines/options for all AMCC eval boards + */ +#include "amcc-common.h" + #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ #define CONFIG_BOARD_RESET 1 /* call board_reset() */ @@ -50,10 +55,6 @@ * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) *----------------------------------------------------------------------*/ -#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */ -#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ -#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN) -#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ #define CFG_FLASH_BASE 0xfc000000 /* start of FLASH */ #define CFG_PCI_MEMBASE 0xa0000000 /* mapped pci memory*/ #define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000 @@ -84,14 +85,9 @@ * Serial Port *----------------------------------------------------------------------*/ #define CFG_EXT_SERIAL_CLOCK 11059200 /* use external 11.059MHz clk */ -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SERIAL_MULTI 1 /*define this if you want console on UART1*/ #undef CONFIG_UART1_CONSOLE -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - /*----------------------------------------------------------------------- * Environment *----------------------------------------------------------------------*/ @@ -142,10 +138,7 @@ /*----------------------------------------------------------------------- * I2C *----------------------------------------------------------------------*/ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F #define CFG_I2C_MULTI_EEPROMS #define CFG_I2C_EEPROM_ADDR (0xa8>>1) @@ -167,72 +160,22 @@ #define CFG_DTT_LOW_TEMP -30 #define CFG_DTT_HYSTERESIS 3 -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -/* Setup some board specific values for the default environment variables */ -#ifndef CONFIG_YELLOWSTONE -#define CONFIG_HOSTNAME yosemite -#define CFG_BOOTFILE "bootfile=/tftpboot/yosemite/uImage\0" -#define CFG_ROOTPATH "rootpath=/opt/eldk/ppc_4xxFP\0" -#else -#define CONFIG_HOSTNAME yellowstone -#define CFG_BOOTFILE "bootfile=/tftpboot/yellowstone/uImage\0" -#define CFG_ROOTPATH "rootpath=/opt/eldk/ppc_4xx\0" -#endif - +/* + * Default environment variables + */ #define CONFIG_EXTRA_ENV_SETTINGS \ - CFG_BOOTFILE \ - CFG_ROOTPATH \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ - "flash_nfs=run nfsargs addip addtty;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ - "bootm\0" \ - "bootfile=/tftpboot/${hostname}/uImage\0" \ + CONFIG_AMCC_DEF_ENV \ + CONFIG_AMCC_DEF_ENV_POWERPC \ + CONFIG_AMCC_DEF_ENV_PPC_OLD \ + CONFIG_AMCC_DEF_ENV_NOR_UPD \ "kernel_addr=fc000000\0" \ "ramdisk_addr=fc180000\0" \ - "load=tftp 200000 /tftpboot/${hostname}/u-boot.bin\0" \ - "update=protect off fff80000 ffffffff;era fff80000 ffffffff;" \ - "cp.b 200000 fff80000 80000;" \ - "setenv filesize;saveenv\0" \ - "upd=run load update\0" \ "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_NET_MULTI 1 /* required for netconsole */ -#define CONFIG_PHY1_ADDR 3 #define CONFIG_HAS_ETH0 1 /* add support for "ethaddr" */ #define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ #define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */ - -#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ - -#define CONFIG_NETCONSOLE /* include NetConsole support */ +#define CONFIG_PHY1_ADDR 3 /* Partitions */ #define CONFIG_MAC_PARTITION @@ -263,36 +206,11 @@ #define CONFIG_HW_WATCHDOG /* watchdog */ #endif - /* - * BOOTP options + * Commands additional to the ones defined in amcc-common.h */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DIAG #define CONFIG_CMD_DTT -#define CONFIG_CMD_ELF -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_MII -#define CONFIG_CMD_NET -#define CONFIG_CMD_NFS #define CONFIG_CMD_PCI -#define CONFIG_CMD_PING -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_SDRAM #ifdef CONFIG_440EP #define CONFIG_CMD_USB @@ -300,36 +218,6 @@ #define CONFIG_CMD_EXT2 #endif - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ -#define CONFIG_LYNXKDI 1 /* support kdi files */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_LOOPW 1 /* enable loopw command */ -#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ - /*----------------------------------------------------------------------- * PCI stuff *----------------------------------------------------------------------- @@ -347,13 +235,6 @@ #define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ #define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */ -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - /*----------------------------------------------------------------------- * External Bus Controller (EBC) Setup *----------------------------------------------------------------------*/ @@ -370,21 +251,4 @@ #define CFG_BCSR5_PCI66EN 0x80 -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 - #endif /* __CONFIG_H */ diff --git a/include/configs/yucca.h b/include/configs/yucca.h index 9a0813f6cf..026fef67ce 100644 --- a/include/configs/yucca.h +++ b/include/configs/yucca.h @@ -44,6 +44,12 @@ #define EXTCLK_50 50000000 #define EXTCLK_83 83333333 +/* + * Include common defines/options for all AMCC eval boards + */ +#define CONFIG_HOSTNAME yucca +#include "amcc-common.h" + #define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */ #undef CONFIG_SHOW_BOOT_PROGRESS #undef CONFIG_STRESS @@ -52,9 +58,7 @@ * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) *----------------------------------------------------------------------*/ -#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ #define CFG_FLASH_BASE 0xfff00000 /* start of FLASH */ -#define CFG_MONITOR_BASE 0xfffb0000 /* start of monitor */ #define CFG_PERIPHERAL_BASE 0xa0000000 /* internal peripherals */ #define CFG_ISRAM_BASE 0x90000000 /* internal SRAM */ @@ -98,24 +102,15 @@ #define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4) #define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR -#define CFG_MONITOR_LEN (320 * 1024) /* Reserve 320 kB for Mon */ -#define CFG_MALLOC_LEN (512 * 1024) /* Reserve 512 kB for malloc */ - /*----------------------------------------------------------------------- * Serial Port *----------------------------------------------------------------------*/ -#define CONFIG_SERIAL_MULTI 1 #undef CONFIG_UART1_CONSOLE #undef CONFIG_SERIAL_SOFTWARE_FIFO #undef CFG_EXT_SERIAL_CLOCK /* #define CFG_EXT_SERIAL_CLOCK (1843200 * 6) */ /* Ext clk @ 11.059 MHz */ -#define CONFIG_BAUDRATE 115200 - -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - /*----------------------------------------------------------------------- * DDR SDRAM *----------------------------------------------------------------------*/ @@ -126,10 +121,7 @@ /*----------------------------------------------------------------------- * I2C *----------------------------------------------------------------------*/ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F #define IIC0_BOOTPROM_ADDR 0x50 #define IIC0_ALT_BOOTPROM_ADDR 0x54 @@ -152,123 +144,32 @@ #undef CFG_ENV_IS_IN_EEPROM /* ... not in EEPROM */ #define CONFIG_ENV_OVERWRITE 1 -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - +/* + * Default environment variables + */ #define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "hostname=yucca\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ - "flash_nfs=run nfsargs addip addtty;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ - "bootm\0" \ - "rootpath=/opt/eldk/ppc_4xx\0" \ - "bootfile=yucca/uImage\0" \ + CONFIG_AMCC_DEF_ENV \ + CONFIG_AMCC_DEF_ENV_PPC \ + CONFIG_AMCC_DEF_ENV_NOR_UPD \ "kernel_addr=E7F10000\0" \ "ramdisk_addr=E7F20000\0" \ - "initrd_high=30000000\0" \ - "load=tftp 100000 yuca/u-boot.bin\0" \ - "update=protect off 2:4-7;era 2:4-7;" \ - "cp.b ${fileaddr} FFFB0000 ${filesize};" \ - "setenv filesize;saveenv\0" \ - "upd=run load update\0" \ "pciconfighost=1\0" \ "pcie_mode=RP:EP:EP\0" \ "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - /* - * BOOTP options + * Commands additional to the ones defined in amcc-common.h */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_ELF -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_MII -#define CONFIG_CMD_NET -#define CONFIG_CMD_NFS #define CONFIG_CMD_PCI -#define CONFIG_CMD_PING -#define CONFIG_CMD_REGINFO #define CONFIG_CMD_SDRAM - #define CONFIG_IBM_EMAC4_V4 1 -#define CONFIG_MII 1 /* MII PHY management */ -#undef CONFIG_NET_MULTI #define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */ #define CONFIG_HAS_ETH0 #define CONFIG_PHY_RESET 1 /* reset phy upon startup */ #define CONFIG_PHY_RESET_DELAY 1000 #define CONFIG_CIS8201_PHY 1 /* Enable 'special' RGMII mode for Cicada phy */ #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ -#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ - -#define CONFIG_NETCONSOLE /* include NetConsole support */ -#define CONFIG_NET_MULTI /* needed for NetConsole */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#if defined(CONFIG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_LOOPW 1 /* enable loopw command */ -#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ /*----------------------------------------------------------------------- * FLASH related @@ -317,26 +218,6 @@ /* Support for Intel 82557/82559/82559ER chips. */ #define CONFIG_EEPRO100 -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /*Initial Memory map for Linux*/ - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - /* FB Divisor selection */ #define FPGA_FB_DIV_6 6 #define FPGA_FB_DIV_10 10 @@ -538,10 +419,4 @@ #define PERIOD_33_33MHZ 30000 /* 30ns */ #define PERIOD_25_00MHZ 40000 /* 40ns */ -/*---------------------------------------------------------------------------*/ - -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 - #endif /* __CONFIG_H */ -- cgit From 8bde63eb3f79d68f693201528dafc8ae7aa087de Mon Sep 17 00:00:00 2001 From: Shinya Kuribayashi Date: Sat, 7 Jun 2008 20:51:56 +0900 Subject: [MIPS] Rename Alchemy processor configs into CONFIG_SOC_* CONFIG_SOC_AU1X00 Common Alchemy Au1x00 stuff. All Alchemy processor based machines need to have this config as a system type specifier. CONFIG_SOC_AU1000, CONFIG_SOC_AU1100, CONFIG_SOC_AU1200, CONFIG_SOC_AU1500, CONFIG_SOC_AU1550 Machine type specifiers. Each port should have one of aboves. Signed-off-by: Shinya Kuribayashi --- include/configs/dbau1x00.h | 10 +++++----- include/configs/gth2.h | 4 ++-- include/configs/pb1x00.h | 8 ++++---- 3 files changed, 11 insertions(+), 11 deletions(-) (limited to 'include/configs') diff --git a/include/configs/dbau1x00.h b/include/configs/dbau1x00.h index 45ff1e7305..0e10396dfa 100644 --- a/include/configs/dbau1x00.h +++ b/include/configs/dbau1x00.h @@ -30,21 +30,21 @@ #define CONFIG_MIPS32 1 /* MIPS32 CPU core */ #define CONFIG_DBAU1X00 1 -#define CONFIG_AU1X00 1 /* alchemy series cpu */ +#define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */ #ifdef CONFIG_DBAU1000 /* Also known as Merlot */ -#define CONFIG_AU1000 1 +#define CONFIG_SOC_AU1000 1 #else #ifdef CONFIG_DBAU1100 -#define CONFIG_AU1100 1 +#define CONFIG_SOC_AU1100 1 #else #ifdef CONFIG_DBAU1500 -#define CONFIG_AU1500 1 +#define CONFIG_SOC_AU1500 1 #else #ifdef CONFIG_DBAU1550 /* Cabernet */ -#define CONFIG_AU1550 1 +#define CONFIG_SOC_AU1550 1 #else #error "No valid board set" #endif diff --git a/include/configs/gth2.h b/include/configs/gth2.h index 23618db667..c2d6ca70a5 100644 --- a/include/configs/gth2.h +++ b/include/configs/gth2.h @@ -30,9 +30,9 @@ #define CONFIG_MIPS32 1 /* MIPS32 CPU core */ #define CONFIG_GTH2 1 -#define CONFIG_AU1X00 1 /* alchemy series cpu */ +#define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */ -#define CONFIG_AU1000 1 +#define CONFIG_SOC_AU1000 1 #define CONFIG_MISC_INIT_R 1 diff --git a/include/configs/pb1x00.h b/include/configs/pb1x00.h index 181cd11b86..2caa64173c 100644 --- a/include/configs/pb1x00.h +++ b/include/configs/pb1x00.h @@ -30,16 +30,16 @@ #define CONFIG_MIPS32 1 /* MIPS32 CPU core */ #define CONFIG_PB1X00 1 -#define CONFIG_AU1X00 1 /* alchemy series cpu */ +#define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */ #ifdef CONFIG_PB1000 -#define CONFIG_AU1000 1 +#define CONFIG_SOC_AU1000 1 #else #ifdef CONFIG_PB1100 -#define CONFIG_AU1100 1 +#define CONFIG_SOC_AU1100 1 #else #ifdef CONFIG_PB1500 -#define CONFIG_AU1500 1 +#define CONFIG_SOC_AU1500 1 #else #error "No valid board set" #endif -- cgit From 7faddaecea52f585f538fdf9c2e61f85a789b19c Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Mon, 9 Jun 2008 13:39:57 +0900 Subject: sh: Renesas Solutions SH7763RDP board support SH7763RDP has SCIF, NOR Flash, Ethernet, USB host, LCDC and MMC. In this patch, support SCIF, NOR Flash, and Ethernet. Signed-off-by: Nobuhiro Iwamatsu Signed-off-by: Nobuhiro Iwamatsu --- include/configs/sh7763rdp.h | 126 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 126 insertions(+) create mode 100644 include/configs/sh7763rdp.h (limited to 'include/configs') diff --git a/include/configs/sh7763rdp.h b/include/configs/sh7763rdp.h new file mode 100644 index 0000000000..d537071a07 --- /dev/null +++ b/include/configs/sh7763rdp.h @@ -0,0 +1,126 @@ +/* + * Configuation settings for the Renesas SH7763RDP board + * + * Copyright (C) 2008 Renesas Solutions Corp. + * Copyright (C) 2008 Nobuhiro Iwamatsu + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __SH7763RDP_H +#define __SH7763RDP_H + +#define CONFIG_SH 1 +#define CONFIG_SH4 1 +#define CONFIG_CPU_SH7763 1 +#define CONFIG_SH7763RDP 1 +#define __LITTLE_ENDIAN 1 + +/* + * Command line configuration. + */ +#define CONFIG_CMD_SDRAM +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_NET +#define CONFIG_CMD_PING +#define CONFIG_CMD_ENV +#define CONFIG_CMD_NFS +#define CONFIG_CMD_JFFS2 + +#define CONFIG_BOOTDELAY -1 +#define CONFIG_BOOTARGS "console=ttySC2,115200 root=1f01" +#define CONFIG_ENV_OVERWRITE 1 + +#define CONFIG_VERSION_VARIABLE +#undef CONFIG_SHOW_BOOT_PROGRESS + +/* SCIF */ +#define CFG_SCIF_CONSOLE 1 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_CONS_SCIF2 1 + +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Buffer size for input from the Console */ +#define CFG_PBSIZE 256 /* Buffer size for Console output */ +#define CFG_MAXARGS 16 /* max args accepted for monitor commands */ +#define CFG_BARGSIZE 512 /* Buffer size for Boot Arguments + passed to kernel */ +#define CFG_BAUDRATE_TABLE { 115200 } /* List of legal baudrate + settings for this board */ + +/* Ethernet */ +#define CONFIG_SH_ETHER 1 +#define CONFIG_SH_ETHER_USE_PORT (1) +#define CONFIG_SH_ETHER_PHY_ADDR (0x01) +#define CFG_RX_ETH_BUFFER (8) + +/* SDRAM */ +#define CFG_SDRAM_BASE (0x8C000000) +#define CFG_SDRAM_SIZE (64 * 1024 * 1024) +#define CFG_MEMTEST_START (CFG_SDRAM_BASE) +#define CFG_MEMTEST_END (CFG_MEMTEST_START + (60 * 1024 * 1024)) + +/* Flash(NOR) */ +#define CFG_FLASH_BASE (0xA0000000) +#define CFG_FLASH_CFI_WIDTH (FLASH_CFI_16BIT) +#define CFG_MAX_FLASH_BANKS (1) +#define CFG_MAX_FLASH_SECT (520) + +/* U-boot setting */ +#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 4 * 1024 * 1024) +#define CFG_MONITOR_BASE (CFG_FLASH_BASE) +#define CFG_MONITOR_LEN (128 * 1024) +/* Size of DRAM reserved for malloc() use */ +#define CFG_MALLOC_LEN (1024 * 1024) +/* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_SIZE (256) +#define CFG_BOOTMAPSZ (8 * 1024 * 1024) + +#define CFG_FLASH_CFI +#define CFG_FLASH_CFI_DRIVER +#undef CFG_FLASH_QUIET_TEST +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ +/* Timeout for Flash erase operations (in ms) */ +#define CFG_FLASH_ERASE_TOUT (3 * 1000) +/* Timeout for Flash write operations (in ms) */ +#define CFG_FLASH_WRITE_TOUT (3 * 1000) +/* Timeout for Flash set sector lock bit operations (in ms) */ +#define CFG_FLASH_LOCK_TOUT (3 * 1000) +/* Timeout for Flash clear lock bit operations (in ms) */ +#define CFG_FLASH_UNLOCK_TOUT (3 * 1000) +/* Use hardware flash sectors protection instead of U-Boot software protection */ +#undef CFG_FLASH_PROTECTION +#undef CFG_DIRECT_FLASH_TFTP +#define CFG_ENV_IS_IN_FLASH +#define CFG_ENV_SECT_SIZE (128 * 1024) +#define CFG_ENV_SIZE (CFG_ENV_SECT_SIZE) +#define CFG_ENV_ADDR (CFG_FLASH_BASE + (1 * CFG_ENV_SECT_SIZE)) +/* Offset of env Flash sector relative to CFG_FLASH_BASE */ +#define CFG_ENV_OFFSET (CFG_ENV_ADDR - CFG_FLASH_BASE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SECT_SIZE) +#define CFG_ENV_ADDR_REDUND (CFG_FLASH_BASE + (2 * CFG_ENV_SECT_SIZE)) + +/* Clock */ +#define CONFIG_SYS_CLK_FREQ 66666666 +#define TMU_CLK_DIVIDER (4) /* 4 (default), 16, 64, 256 or 1024 */ +#define CFG_HZ (CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER) + +#endif /* __SH7763RDP_H */ -- cgit From 589c04271d129729a8b01391453851ab9cc4069c Mon Sep 17 00:00:00 2001 From: Gerald Van Baren Date: Tue, 3 Jun 2008 20:24:58 -0400 Subject: Convert mpc7448hpc2 to CONFIG_OF_LIBFDT This was configured to use the deprecated CONFIG_OF_FLAT_TREE, change to CONFIG_OF_LIBFDT. WARNING: This conversion is untested because I do not have a board to test it on. NOTE: The FDT blob (DTS) must have an /aliases/ethernet0 and (optionally) /aliases/ethernet1 property for the ethernet to work. Signed-off-by: Gerald Van Baren --- include/configs/mpc7448hpc2.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include/configs') diff --git a/include/configs/mpc7448hpc2.h b/include/configs/mpc7448hpc2.h index a218f7576c..3d71e229d9 100644 --- a/include/configs/mpc7448hpc2.h +++ b/include/configs/mpc7448hpc2.h @@ -75,7 +75,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " /* Pass open firmware flat tree */ -#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_LIBFDT 1 #define CONFIG_OF_BOARD_SETUP 1 #define OF_CPU "PowerPC,7448@0" -- cgit From 62bcdda293efa752f8281fbd9da03822b27ce82f Mon Sep 17 00:00:00 2001 From: Gerald Van Baren Date: Tue, 3 Jun 2008 20:26:29 -0400 Subject: Change the stxxst to CONFIG_OF_LIBFDT This was configured to use the deprecated CONFIG_OF_FLAT_TREE, change to CONFIG_OF_LIBFDT. WARNING: It appears that this board lost its ability to boot via a flattened device tree prior to this changeset. WARNING: This conversion was untested because I do not have a board to test it on. Signed-off-by: Gerald Van Baren --- include/configs/stxxtc.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'include/configs') diff --git a/include/configs/stxxtc.h b/include/configs/stxxtc.h index 97a1032af0..fcafba5937 100644 --- a/include/configs/stxxtc.h +++ b/include/configs/stxxtc.h @@ -590,8 +590,8 @@ typedef unsigned int led_id_t; /*****************************************************************************/ -/* pass open firmware flat tree */ -#define CONFIG_OF_FLAT_TREE 1 +/* pass open firmware flattened device tree */ +#define CONFIG_OF_LIBFDT 1 #define OF_CPU "PowerPC,MPC870@0" #define OF_TBCLK (MPC8XX_HZ / 16) -- cgit From fec6d9ee7c10443f65ce1788ef818919167bbf2e Mon Sep 17 00:00:00 2001 From: Gerald Van Baren Date: Tue, 3 Jun 2008 20:34:45 -0400 Subject: Remove the deprecated CONFIG_OF_FLAT_TREE Use CONFIG_OF_LIBFDT instead to support flattened device trees. It is cleaner, has better functionality, and is better supported. Signed-off-by: Gerald Van Baren --- include/configs/mpc7448hpc2.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/configs') diff --git a/include/configs/mpc7448hpc2.h b/include/configs/mpc7448hpc2.h index 3d71e229d9..2f24967405 100644 --- a/include/configs/mpc7448hpc2.h +++ b/include/configs/mpc7448hpc2.h @@ -58,6 +58,7 @@ #define CONFIG_BOARD_EARLY_INIT_R #define CONFIG_MISC_INIT_R +#define CONFIG_HAS_ETH0 #define CONFIG_HAS_ETH1 #define CONFIG_ENV_OVERWRITE -- cgit From f9023afbdfd9f27e7c38f3cce965746e56d62dd3 Mon Sep 17 00:00:00 2001 From: Anton Vorontsov Date: Thu, 29 May 2008 18:14:56 +0400 Subject: 83xx/85xx: further localbus cleanups move the BRx_* and ORx_* left behind in mpc85xx.h The same is needed for mpc8xx.h and mpc8260.h (defines are almost the same, just few differences which needs some attention though). But the bad news for mpc8xx and mpc8260 is that there are a lot of users of these defines. So this cleanup I'll leave for the "better times". Signed-off-by: Anton Vorontsov Signed-off-by: Kim Phillips --- include/configs/MPC8315ERDB.h | 2 +- include/configs/MPC8349EMDS.h | 2 +- include/configs/MPC8349ITX.h | 4 ++-- include/configs/MPC8360EMDS.h | 2 +- include/configs/MPC8360ERDK.h | 2 +- include/configs/MPC837XEMDS.h | 2 +- include/configs/TQM834x.h | 2 +- 7 files changed, 8 insertions(+), 8 deletions(-) (limited to 'include/configs') diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index 7a5d0aa1dd..095f6658c1 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -203,7 +203,7 @@ #define CFG_OR0_PRELIM ( (~(CFG_FLASH_SIZE - 1) << 20) \ | OR_UPM_XAM \ | OR_GPCM_CSNT \ - | OR_GPCM_ACS_0b11 \ + | OR_GPCM_ACS_DIV2 \ | OR_GPCM_XACS \ | OR_GPCM_SCY_15 \ | OR_GPCM_TRLX \ diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index bd77540003..37e3ca40b3 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -157,7 +157,7 @@ (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ BR_V) /* valid */ #define CFG_OR0_PRELIM ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \ - OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \ + OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \ OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) #define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* window base at flash base */ #define CFG_LBLAWAR0_PRELIM 0x80000018 /* 32 MB window size */ diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index 38410a1764..82d06867be 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -211,7 +211,7 @@ boards, we say we have two, but don't display a message if we find only one. */ #define CFG_BR0_PRELIM (CFG_FLASH_BASE | BR_PS_16 | BR_V) #define CFG_OR0_PRELIM ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \ - OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \ + OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \ OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) #define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE #define CFG_LBLAWAR0_PRELIM (LBLAWAR_EN | (0x13 + CFG_FLASH_SIZE_SHIFT)) @@ -236,7 +236,7 @@ boards, we say we have two, but don't display a message if we find only one. */ #define CFG_LED_BASE 0xF9000000 #define CFG_BR2_PRELIM (CFG_LED_BASE | BR_PS_8 | BR_V) -#define CFG_OR2_PRELIM (OR_AM_2MB | OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | \ +#define CFG_OR2_PRELIM (OR_AM_2MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ OR_GPCM_XACS | OR_GPCM_SCY_9 | OR_GPCM_TRLX | \ OR_GPCM_EHTR | OR_GPCM_EAD) diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h index fcfbe6f821..b4bff9a2be 100644 --- a/include/configs/MPC8360EMDS.h +++ b/include/configs/MPC8360EMDS.h @@ -203,7 +203,7 @@ (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ BR_V) /* valid */ #define CFG_OR0_PRELIM ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \ - OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \ + OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \ OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) #define CFG_MAX_FLASH_BANKS 1 /* number of banks */ diff --git a/include/configs/MPC8360ERDK.h b/include/configs/MPC8360ERDK.h index adedcb95af..ca8d53cf25 100644 --- a/include/configs/MPC8360ERDK.h +++ b/include/configs/MPC8360ERDK.h @@ -195,7 +195,7 @@ (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ BR_V) /* valid */ #define CFG_OR0_PRELIM ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \ - OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | \ + OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ OR_GPCM_XACS | OR_GPCM_SCY_15 | \ OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index 4e159a0b46..0dd02795a6 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -239,7 +239,7 @@ #define CFG_OR0_PRELIM ( (~(CFG_FLASH_SIZE - 1) << 20) \ | OR_UPM_XAM \ | OR_GPCM_CSNT \ - | OR_GPCM_ACS_0b11 \ + | OR_GPCM_ACS_DIV2 \ | OR_GPCM_XACS \ | OR_GPCM_SCY_15 \ | OR_GPCM_TRLX \ diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index 89fc465416..0d2ca7225b 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -113,7 +113,7 @@ extern int tqm834x_num_flash_banks; BR_MS_GPCM | BR_PS_32 | BR_V) /* FLASH timing (0x0000_0c54) */ -#define CFG_OR_TIMING_FLASH (OR_GPCM_CSNT | OR_GPCM_ACS_0b10 | \ +#define CFG_OR_TIMING_FLASH (OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | \ OR_GPCM_SCY_5 | OR_GPCM_TRLX) #define CFG_PRELIM_OR_AM 0xc0000000 /* OR addr mask: 1 GiB */ -- cgit From c005b93925ba49f07da2aa748527996d927e172f Mon Sep 17 00:00:00 2001 From: Andre Schwarz Date: Tue, 10 Jun 2008 09:13:16 +0200 Subject: add MPC8343 based board mvBlueLYNX-M7 (doc+config) Add MPC8343 based board mvBlueLYNX-M7. It's a single board stereo camera system. Please read doc/README.mvblm7 for details. Signed-off-by: Andre Schwarz Signed-off-by: Kim Phillips --- include/configs/MVBLM7.h | 479 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 479 insertions(+) create mode 100644 include/configs/MVBLM7.h (limited to 'include/configs') diff --git a/include/configs/MVBLM7.h b/include/configs/MVBLM7.h new file mode 100644 index 0000000000..658433f906 --- /dev/null +++ b/include/configs/MVBLM7.h @@ -0,0 +1,479 @@ +/* + * Copyright (C) Matrix Vision GmbH 2008 + * + * Matrix Vision mvBlueLYNX-M7 configuration file + * based on Freescale's MPC8349ITX. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define MV_VERSION "v1.0.1" + +/* + * High Level Configuration Options + */ +#define CONFIG_E300 1 +#define CONFIG_MPC83XX 1 +#define CONFIG_MPC834X 1 +#define CONFIG_MPC8343 1 + +#define CFG_IMMR 0xE0000000 + +#define CONFIG_PCI +#define CONFIG_83XX_GENERIC_PCI +#define CONFIG_PCI_SKIP_HOST_BRIDGE +#define CONFIG_HARD_I2C +#define CONFIG_TSEC_ENET +#define CONFIG_MPC8XXX_SPI +#define CONFIG_HARD_SPI +#define MVBLM7_MMC_CS 0x04000000 + +/* I2C */ +#undef CONFIG_SOFT_I2C + +#define CONFIG_FSL_I2C +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_I2C_CMD_TREE +#define CFG_I2C_OFFSET 0x3000 +#define CFG_I2C2_OFFSET 0x3100 + +#define CFG_I2C_SPEED 100000 +#define CFG_I2C_SLAVE 0x7F + +/* + * DDR Setup + */ +#define CFG_DDR_BASE 0x00000000 +#define CFG_SDRAM_BASE CFG_DDR_BASE +#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE +#define CFG_83XX_DDR_USES_CS0 1 +#define CFG_MEMTEST_START (60<<20) +#define CFG_MEMTEST_END (70<<20) + +#define CFG_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ + DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 + +#define CFG_DDR_SIZE 256 + +/* HC, 75Ohm, DDR-II, DRQ */ +#define CFG_DDRCDR 0x80000001 +/* EN, ODT_WR, 3BA, 14row, 10col */ +#define CFG_DDR_CS0_CONFIG 0x80014102 +#define CFG_DDR_CS1_CONFIG 0x0 +#define CFG_DDR_CS2_CONFIG 0x0 +#define CFG_DDR_CS3_CONFIG 0x0 + +#define CFG_DDR_CS0_BNDS 0x0000000f +#define CFG_DDR_CS1_BNDS 0x0 +#define CFG_DDR_CS2_BNDS 0x0 +#define CFG_DDR_CS3_BNDS 0x0 + +#define CFG_DDR_CLK_CNTL 0x02000000 + +#define CFG_DDR_TIMING_0 0x00260802 +#define CFG_DDR_TIMING_1 0x2625b221 +#define CFG_DDR_TIMING_2 0x1f9820c7 +#define CFG_DDR_TIMING_3 0x00000000 + +/* ~MEM_EN, SREN, DDR-II, 32_BE */ +#define CFG_DDR_SDRAM_CFG 0x43080000 +#define CFG_DDR_SDRAM_CFG2 0x00401000 +#define CFG_DDR_INTERVAL 0x04060100 + +#define CFG_DDR_MODE 0x078e0232 + +/* Flash */ +#define CFG_FLASH_CFI +#define CFG_FLASH_CFI_DRIVER +#define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT + +#define CFG_FLASH_BASE 0xFF800000 +#define CFG_FLASH_SIZE 8 +#define CFG_FLASH_SIZE_SHIFT 3 +#define CFG_FLASH_EMPTY_INFO +#define CFG_FLASH_ERASE_TOUT 60000 +#define CFG_FLASH_WRITE_TOUT 500 +#define CFG_MAX_FLASH_BANKS 1 +#define CFG_MAX_FLASH_SECT 256 + +#define CFG_BR0_PRELIM (CFG_FLASH_BASE | BR_PS_16 | BR_V) +#define CFG_OR0_PRELIM ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \ + OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS|\ + OR_GPCM_SCY_15 | OR_GPCM_TRLX | OR_GPCM_EHTR | \ + OR_GPCM_EAD) +#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE +#define CFG_LBLAWAR0_PRELIM (LBLAWAR_EN | (0x13 + CFG_FLASH_SIZE_SHIFT)) + +/* + * U-Boot memory configuration + */ +#define CFG_MONITOR_BASE TEXT_BASE +#undef CFG_RAMBOOT + +#define CONFIG_L1_INIT_RAM +#define CFG_INIT_RAM_LOCK +#define CFG_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ +#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/ + +#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/* CFG_MONITOR_LEN must be a multiple of CFG_ENV_SECT_SIZE */ +#define CFG_MONITOR_LEN (512 * 1024) +#define CFG_MALLOC_LEN (512 * 1024) + +/* + * Local Bus LCRR and LBCR regs + * LCRR: DLL bypass, Clock divider is 4 + * External Local Bus rate is + * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV + */ +#define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) +#define CFG_LBC_LBCR 0x00000000 + +/* LB sdram refresh timer, about 6us */ +#define CFG_LBC_LSRT 0x32000000 +/* LB refresh timer prescal, 266MHz/32*/ +#define CFG_LBC_MRTPR 0x20000000 + +/* + * Serial Port + */ +#define CONFIG_CONS_INDEX 1 +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE 1 +#define CFG_NS16550_CLK get_bus_freq(0) + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} + +#define CONFIG_CONSOLE ttyS0 +#define CONFIG_BAUDRATE 115200 + +#define CFG_NS16550_COM1 (CFG_IMMR + 0x4500) +#define CFG_NS16550_COM2 (CFG_IMMR + 0x4600) + +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_OF_STDOUT_VIA_ALIAS 1 +#define MV_DTB_NAME "mvblm7.dtb" + +/* + * PCI + */ +#define CFG_PCI1_MEM_BASE 0x80000000 +#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE +#define CFG_PCI1_MEM_SIZE 0x10000000 +#define CFG_PCI1_MMIO_BASE (CFG_PCI1_MEM_BASE + CFG_PCI1_MEM_SIZE) +#define CFG_PCI1_MMIO_PHYS CFG_PCI1_MMIO_BASE +#define CFG_PCI1_MMIO_SIZE 0x10000000 +#define CFG_PCI1_IO_BASE 0x00000000 +#define CFG_PCI1_IO_PHYS 0xE2000000 +#define CFG_PCI1_IO_SIZE 0x01000000 + +#define _IO_BASE 0x00000000 + +#define CONFIG_NET_MULTI 1 +#define CONFIG_NET_RETRY_COUNT 3 + +#define PCI_66M +#define CONFIG_83XX_CLKIN 66666667 +#define CONFIG_PCI_PNP +#define CONFIG_PCI_SCAN_SHOW + +/* TSEC */ +#define CONFIG_GMII +#define CFG_VSC8601_SKEWFIX +#define CFG_VSC8601_SKEW_TX 3 +#define CFG_VSC8601_SKEW_RX 3 + +#define CONFIG_TSEC1 +#define CONFIG_TSEC2 + +#define CONFIG_HAS_ETH0 +#define CONFIG_TSEC1_NAME "TSEC0" +#define CONFIG_FEC1_PHY_NORXERR +#define CFG_TSEC1_OFFSET 0x24000 +#define CFG_TSEC1 (CFG_IMMR+CFG_TSEC1_OFFSET) +#define TSEC1_PHY_ADDR 0x10 +#define TSEC1_PHYIDX 0 +#define TSEC1_FLAGS (TSEC_GIGABIT|TSEC_REDUCED) + +#define CONFIG_HAS_ETH1 +#define CONFIG_TSEC2_NAME "TSEC1" +#define CONFIG_FEC2_PHY_NORXERR +#define CFG_TSEC2_OFFSET 0x25000 +#define CFG_TSEC2 (CFG_IMMR+CFG_TSEC2_OFFSET) +#define TSEC2_PHY_ADDR 0x11 +#define TSEC2_PHYIDX 0 +#define TSEC2_FLAGS (TSEC_GIGABIT|TSEC_REDUCED) + +#define CONFIG_ETHPRIME "TSEC0" + +#define CONFIG_BOOTP_VENDOREX +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_NTPSERVER +#define CONFIG_BOOTP_RANDOM_DELAY +#define CONFIG_BOOTP_SEND_HOSTNAME + +/* USB */ +#define CONFIG_HAS_FSL_DR_USB + +/* + * Environment + */ +#undef CFG_FLASH_PROTECTION +#define CONFIG_ENV_OVERWRITE + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR 0xFF800000 +#define CFG_ENV_SIZE 0x2000 +#define CFG_ENV_SECT_SIZE 0x2000 +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR+CFG_ENV_SIZE) +#define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE + +#define CONFIG_LOADS_ECHO +#define CFG_LOADS_BAUD_CHANGE + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_NET +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_SDRAM +#define CONFIG_CMD_PCI +#define CONFIG_CMD_I2C +#define CONFIG_CMD_FPGA + +#undef CONFIG_WATCHDOG + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP +#define CONFIG_CMDLINE_EDITING +#define CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " + +/* default load address */ +#define CFG_LOAD_ADDR 0x2000000 +/* default location for tftp and bootm */ +#define CONFIG_LOADADDR 0x200000 + +#define CFG_PROMPT "mvBL-M7> " +#define CFG_CBSIZE 256 + +#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) +#define CFG_MAXARGS 16 +#define CFG_BARGSIZE CFG_CBSIZE +#define CFG_HZ 1000 + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ + +#define CFG_HRCW_LOW 0x0 +#define CFG_HRCW_HIGH 0x0 + +/* + * System performance + */ +#define CFG_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ +#define CFG_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ +#define CFG_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ +#define CFG_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ + +/* clocking */ +#define CFG_SCCR_ENCCM 0 +#define CFG_SCCR_USBMPHCM 0 +#define CFG_SCCR_USBDRCM 2 +#define CFG_SCCR_TSEC1CM 1 +#define CFG_SCCR_TSEC2CM 1 + +#define CFG_SICRH 0x1fff8003 +#define CFG_SICRL (SICRL_LDP_A | SICRL_USB1 | SICRL_USB0) + +#define CFG_HID0_INIT 0x000000000 +#define CFG_HID0_FINAL CFG_HID0_INIT + +#define CFG_HID2 HID2_HBE + +/* DDR */ +#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) + +/* PCI */ +#define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_IBAT2L (CFG_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT |\ + BATL_GUARDEDSTORAGE) +#define CFG_IBAT2U (CFG_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) + +/* no PCI2 */ +#define CFG_IBAT3L 0 +#define CFG_IBAT3U 0 +#define CFG_IBAT4L 0 +#define CFG_IBAT4U 0 + +/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ +#define CFG_IBAT5L (CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | \ + BATL_GUARDEDSTORAGE) +#define CFG_IBAT5U (CFG_IMMR | BATU_BL_256M | BATU_VS | BATU_VP) + +/* stack in DCACHE 0xFDF00000 & FLASH @ 0xFF800000 */ +#define CFG_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_IBAT7L 0 +#define CFG_IBAT7U 0 + +#define CFG_DBAT0L CFG_IBAT0L +#define CFG_DBAT0U CFG_IBAT0U +#define CFG_DBAT1L CFG_IBAT1L +#define CFG_DBAT1U CFG_IBAT1U +#define CFG_DBAT2L CFG_IBAT2L +#define CFG_DBAT2U CFG_IBAT2U +#define CFG_DBAT3L CFG_IBAT3L +#define CFG_DBAT3U CFG_IBAT3U +#define CFG_DBAT4L CFG_IBAT4L +#define CFG_DBAT4U CFG_IBAT4U +#define CFG_DBAT5L CFG_IBAT5L +#define CFG_DBAT5U CFG_IBAT5U +#define CFG_DBAT6L CFG_IBAT6L +#define CFG_DBAT6U CFG_IBAT6U +#define CFG_DBAT7L CFG_IBAT7L +#define CFG_DBAT7U CFG_IBAT7U + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + + +/* + * Environment Configuration + */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_NETDEV eth0 + +/* Default path and filenames */ +#define CONFIG_BOOTDELAY 5 +#define CONFIG_AUTOBOOT_KEYED +#define CONFIG_AUTOBOOT_STOP_STR "s" +#define CONFIG_ZERO_BOOTDELAY_CHECK +#define CONFIG_RESET_TO_RETRY 1000 + +#define MV_CI "mvBL-M7" +#define MV_VCI "mvBL-M7" +#define MV_FPGA_DATA "0xfff80000" +#define MV_FPGA_SIZE "0x76ca2" +#define MV_KERNEL_ADDR "0xff810000" +#define MV_INITRD_ADDR "0xffc00000" +#define MV_AUTOSCR_ADDR "0xff804000" +#define MV_AUTOSCR_ADDR2 "0xff806000" +#define MV_DTB_ADDR "0xff808000" +#define MV_INITRD_LENGTH "0x00300000" + +#define CONFIG_SHOW_BOOT_PROGRESS 1 + +#define MV_KERNEL_ADDR_RAM "0x00100000" +#define MV_DTB_ADDR_RAM "0x00600000" +#define MV_INITRD_ADDR_RAM "0x01000000" + +#define CONFIG_BOOTCOMMAND "if imi ${autoscr_addr}; \ + then autoscr ${autoscr_addr}; \ + else autoscr ${autoscr_addr2}; \ + fi;" +#define CONFIG_BOOTARGS "root=/dev/ram ro rootfstype=squashfs" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "console_nr=0\0" \ + "stdin=serial\0" \ + "stdout=serial\0" \ + "stderr=serial\0" \ + "fpga=0\0" \ + "fpgadata=" MV_FPGA_DATA "\0" \ + "fpgadatasize=" MV_FPGA_SIZE "\0" \ + "autoscr_addr=" MV_AUTOSCR_ADDR "\0" \ + "autoscr_addr2=" MV_AUTOSCR_ADDR2 "\0" \ + "mv_kernel_addr=" MV_KERNEL_ADDR "\0" \ + "mv_kernel_addr_ram=" MV_KERNEL_ADDR_RAM "\0" \ + "mv_initrd_addr=" MV_INITRD_ADDR "\0" \ + "mv_initrd_addr_ram=" MV_INITRD_ADDR_RAM "\0" \ + "mv_initrd_length=" MV_INITRD_LENGTH "\0" \ + "mv_dtb_addr=" MV_DTB_ADDR "\0" \ + "mv_dtb_addr_ram=" MV_DTB_ADDR_RAM "\0" \ + "dtb_name=" MV_DTB_NAME "\0" \ + "mv_version=" MV_VERSION "\0" \ + "dhcp_client_id=" MV_CI "\0" \ + "dhcp_vendor-class-identifier=" MV_VCI "\0" \ + "netretry=no\0" \ + "use_static_ipaddr=no\0" \ + "static_ipaddr=192.168.90.10\0" \ + "static_netmask=255.255.255.0\0" \ + "static_gateway=0.0.0.0\0" \ + "initrd_name=uInitrd.mvblm7-xenorfs\0" \ + "zcip=no\0" \ + "netboot=yes\0" \ + "mvtest=Ff\0" \ + "tried_bootfromflash=no\0" \ + "tried_bootfromnet=no\0" \ + "bootfile=mvblm72625.boot\0" \ + "use_dhcp=yes\0" \ + "gev_start=yes\0" \ + "mvbcdma_debug=0\0" \ + "mvbcia_debug=0\0" \ + "propdev_debug=0\0" \ + "gevss_debug=0\0" \ + "watchdog=0\0" \ + "usb_dr_mode=host\0" \ + "" + +#define CONFIG_FPGA_COUNT 1 +#define CONFIG_FPGA CFG_ALTERA_CYCLON2 +#define CONFIG_FPGA_ALTERA +#define CONFIG_FPGA_CYCLON2 + +#endif -- cgit From 2329fe113d847e43cca8e4a0e4edd613b50b8492 Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Tue, 10 Jun 2008 13:25:24 -0500 Subject: mpc83xx: MVBLM7: minor build fixups Signed-off-by: Kim Phillips --- include/configs/MVBLM7.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include/configs') diff --git a/include/configs/MVBLM7.h b/include/configs/MVBLM7.h index 658433f906..349ca14bba 100644 --- a/include/configs/MVBLM7.h +++ b/include/configs/MVBLM7.h @@ -118,7 +118,7 @@ #define CFG_BR0_PRELIM (CFG_FLASH_BASE | BR_PS_16 | BR_V) #define CFG_OR0_PRELIM ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \ - OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS|\ + OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS|\ OR_GPCM_SCY_15 | OR_GPCM_TRLX | OR_GPCM_EHTR | \ OR_GPCM_EAD) #define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE -- cgit From c8c5fc266e4499e283c293ccb972863156aa4134 Mon Sep 17 00:00:00 2001 From: Anton Vorontsov Date: Thu, 29 May 2008 18:14:56 +0400 Subject: 83xx/85xx: further localbus cleanups Merge mpc85xx.h's LBC defines to fsl_lbc.h. Also, adopt ACS names from mpc85xx.h, so ACS_0b10 renamed to ACS_DIV4, ACS_0b11 to ACS_DIV2. Signed-off-by: Anton Vorontsov --- include/configs/MPC8315ERDB.h | 2 +- include/configs/MPC8349EMDS.h | 2 +- include/configs/MPC8349ITX.h | 4 ++-- include/configs/MPC8360EMDS.h | 2 +- include/configs/MPC8360ERDK.h | 2 +- include/configs/MPC837XEMDS.h | 2 +- include/configs/TQM834x.h | 2 +- 7 files changed, 8 insertions(+), 8 deletions(-) (limited to 'include/configs') diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index 7a5d0aa1dd..095f6658c1 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -203,7 +203,7 @@ #define CFG_OR0_PRELIM ( (~(CFG_FLASH_SIZE - 1) << 20) \ | OR_UPM_XAM \ | OR_GPCM_CSNT \ - | OR_GPCM_ACS_0b11 \ + | OR_GPCM_ACS_DIV2 \ | OR_GPCM_XACS \ | OR_GPCM_SCY_15 \ | OR_GPCM_TRLX \ diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index bd77540003..37e3ca40b3 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -157,7 +157,7 @@ (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ BR_V) /* valid */ #define CFG_OR0_PRELIM ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \ - OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \ + OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \ OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) #define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* window base at flash base */ #define CFG_LBLAWAR0_PRELIM 0x80000018 /* 32 MB window size */ diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index 38410a1764..82d06867be 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -211,7 +211,7 @@ boards, we say we have two, but don't display a message if we find only one. */ #define CFG_BR0_PRELIM (CFG_FLASH_BASE | BR_PS_16 | BR_V) #define CFG_OR0_PRELIM ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \ - OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \ + OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \ OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) #define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE #define CFG_LBLAWAR0_PRELIM (LBLAWAR_EN | (0x13 + CFG_FLASH_SIZE_SHIFT)) @@ -236,7 +236,7 @@ boards, we say we have two, but don't display a message if we find only one. */ #define CFG_LED_BASE 0xF9000000 #define CFG_BR2_PRELIM (CFG_LED_BASE | BR_PS_8 | BR_V) -#define CFG_OR2_PRELIM (OR_AM_2MB | OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | \ +#define CFG_OR2_PRELIM (OR_AM_2MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ OR_GPCM_XACS | OR_GPCM_SCY_9 | OR_GPCM_TRLX | \ OR_GPCM_EHTR | OR_GPCM_EAD) diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h index fcfbe6f821..b4bff9a2be 100644 --- a/include/configs/MPC8360EMDS.h +++ b/include/configs/MPC8360EMDS.h @@ -203,7 +203,7 @@ (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ BR_V) /* valid */ #define CFG_OR0_PRELIM ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \ - OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \ + OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \ OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) #define CFG_MAX_FLASH_BANKS 1 /* number of banks */ diff --git a/include/configs/MPC8360ERDK.h b/include/configs/MPC8360ERDK.h index adedcb95af..ca8d53cf25 100644 --- a/include/configs/MPC8360ERDK.h +++ b/include/configs/MPC8360ERDK.h @@ -195,7 +195,7 @@ (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ BR_V) /* valid */ #define CFG_OR0_PRELIM ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \ - OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | \ + OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ OR_GPCM_XACS | OR_GPCM_SCY_15 | \ OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index 4e159a0b46..0dd02795a6 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -239,7 +239,7 @@ #define CFG_OR0_PRELIM ( (~(CFG_FLASH_SIZE - 1) << 20) \ | OR_UPM_XAM \ | OR_GPCM_CSNT \ - | OR_GPCM_ACS_0b11 \ + | OR_GPCM_ACS_DIV2 \ | OR_GPCM_XACS \ | OR_GPCM_SCY_15 \ | OR_GPCM_TRLX \ diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index 89fc465416..0d2ca7225b 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -113,7 +113,7 @@ extern int tqm834x_num_flash_banks; BR_MS_GPCM | BR_PS_32 | BR_V) /* FLASH timing (0x0000_0c54) */ -#define CFG_OR_TIMING_FLASH (OR_GPCM_CSNT | OR_GPCM_ACS_0b10 | \ +#define CFG_OR_TIMING_FLASH (OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | \ OR_GPCM_SCY_5 | OR_GPCM_TRLX) #define CFG_PRELIM_OR_AM 0xc0000000 /* OR addr mask: 1 GiB */ -- cgit From b99ba1679e8cd51b023e67098c89e606e47137d2 Mon Sep 17 00:00:00 2001 From: Wolfgang Grandegger Date: Thu, 5 Jun 2008 13:12:00 +0200 Subject: TQM85xx: Various coding style fixes Signed-off-by: Wolfgang Grandegger --- include/configs/TQM85xx.h | 88 ++++++++++++++++++++++------------------------- 1 file changed, 42 insertions(+), 46 deletions(-) (limited to 'include/configs') diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h index fca5f74df7..f0e73184f4 100644 --- a/include/configs/TQM85xx.h +++ b/include/configs/TQM85xx.h @@ -50,7 +50,7 @@ #define CONFIG_CPM2 1 /* has CPM2 */ #endif -#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ +#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ /* * sysclk for MPC85xx @@ -102,11 +102,11 @@ /* TQM8540 & 8560 need DLL-override */ #define CONFIG_DDR_DLL /* DLL fix needed */ #define CONFIG_DDR_DEFAULT_CL 25 /* CAS latency 2,5 */ -#endif /* defined(CONFIG_TQM8540) || defined(CONFIG_TQM8560) */ +#endif /* CONFIG_TQM8540 || CONFIG_TQM8560 */ #if defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555) #define CONFIG_DDR_DEFAULT_CL 30 /* CAS latency 3 */ -#endif /* defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555) */ +#endif /* CONFIG_TQM8541 || CONFIG_TQM8555 */ /* * Flash on the Local Bus @@ -116,51 +116,51 @@ #define CFG_FLASH_BANKS_LIST { CFG_FLASH1, CFG_FLASH0 } #define CFG_LBC_FLASH_BASE CFG_FLASH1 /* Localbus flash start */ -#define CFG_FLASH_BASE CFG_LBC_FLASH_BASE /* start of FLASH */ +#define CFG_FLASH_BASE CFG_LBC_FLASH_BASE /* start of FLASH */ #define CFG_BR0_PRELIM 0xfc001801 /* port size 32bit */ #define CFG_OR0_PRELIM 0xfc000040 /* 64MB Flash */ #define CFG_BR1_PRELIM 0xf8001801 /* port size 32bit */ #define CFG_OR1_PRELIM 0xfc000040 /* 64MB Flash */ -#define CFG_FLASH_CFI /* flash is CFI compat. */ -#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver*/ +#define CFG_FLASH_CFI /* flash is CFI compat. */ +#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector */ #define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash*/ -#define CFG_MAX_FLASH_BANKS 2 /* number of banks */ -#define CFG_MAX_FLASH_SECT 512 /* sectors per device */ +#define CFG_MAX_FLASH_BANKS 2 /* number of banks */ +#define CFG_MAX_FLASH_SECT 512 /* sectors per device */ #undef CFG_FLASH_CHECKSUM #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ -#define CFG_LBC_LCRR 0x00030008 /* LB clock ratio reg */ -#define CFG_LBC_LBCR 0x00000000 /* LB config reg */ -#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ -#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/ +#define CFG_LBC_LCRR 0x00030008 /* LB clock ratio reg */ +#define CFG_LBC_LBCR 0x00000000 /* LB config reg */ +#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ +#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/ #define CONFIG_L1_INIT_RAM #define CFG_INIT_RAM_LOCK 1 #define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ #define CFG_INIT_RAM_END 0x4000 /* End used area in RAM */ -#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data*/ +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256kB for Mon*/ +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256kB for Mon */ #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ /* Serial Port */ #if defined(CONFIG_TQM8560) -#define CONFIG_CONS_ON_SCC /* define if console on SCC */ -#undef CONFIG_CONS_NONE /* define if console on something else */ -#define CONFIG_CONS_INDEX 1 /* which serial channel for console */ +#define CONFIG_CONS_ON_SCC /* define if console on SCC */ +#undef CONFIG_CONS_NONE /* define if console on something else */ +#define CONFIG_CONS_INDEX 1 /* which serial channel for console */ -#else /* ! TQM8560 */ +#else /* !CONFIG_TQM8560 */ #define CONFIG_CONS_INDEX 1 #undef CONFIG_SERIAL_SOFTWARE_FIFO @@ -173,20 +173,18 @@ #define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) /* PS/2 Keyboard */ -#if !defined(CONFIG_TQM8560) #define CONFIG_PS2KBD /* AT-PS/2 Keyboard */ #define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */ #define CONFIG_PS2SERIAL 2 /* .. on DUART2 */ #define CONFIG_PS2MULT_DELAY (CFG_HZ/2) /* Initial delay */ #define CONFIG_BOARD_EARLY_INIT_R 1 -#endif /* !CONFIG_TQM8560 */ #endif /* CONFIG_TQM8560 */ -#define CONFIG_BAUDRATE 115200 +#define CONFIG_BAUDRATE 115200 -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ #define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ @@ -194,11 +192,10 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif - /* * I2C */ -#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ #define CONFIG_HARD_I2C /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ @@ -219,7 +216,7 @@ #define CFG_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */ #define CFG_EEPROM_PAGE_WRITE_ENABLE #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20 -#define CFG_I2C_MULTI_EEPROMS 1 /* more than one eeprom */ +#define CFG_I2C_MULTI_EEPROMS 1 /* more than one eeprom */ /* I2C SYSMON (LM75) */ #define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ @@ -242,7 +239,7 @@ #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ #define CFG_PCI1_IO_BASE 0xe2000000 #define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE -#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ +#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ #if defined(CONFIG_PCI) @@ -254,8 +251,7 @@ #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ -#endif /* CONFIG_PCI */ - +#endif /* CONFIG_PCI */ #define CONFIG_NET_MULTI 1 @@ -305,7 +301,7 @@ * FCC2: a - c (X50.2 - 1) */ #define CONFIG_ETHER_ON_FCC -#define CONFIG_ETHER_INDEX 1 /* FCC channel for ethernet */ +#define CONFIG_ETHER_INDEX 1 /* FCC channel for ethernet */ #endif #if defined(CONFIG_TQM8560) @@ -321,12 +317,13 @@ * FCC3: a - d (X50.2 - 3) */ #define CONFIG_ETHER_ON_FCC -#define CONFIG_ETHER_INDEX 3 /* FCC channel for ethernet */ +#define CONFIG_ETHER_INDEX 3 /* FCC channel for ethernet */ #endif #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1) #define CONFIG_ETHER_ON_FCC1 -#define CFG_CMXFCR_MASK1 (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK) +#define CFG_CMXFCR_MASK1 (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | \ + CMXFCR_TF1CS_MSK) #define CFG_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK12) #define CFG_CPMFCR_RAMTYPE 0 #define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) @@ -334,7 +331,8 @@ #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2) #define CONFIG_ETHER_ON_FCC2 -#define CFG_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) +#define CFG_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | \ + CMXFCR_TF2CS_MSK) #define CFG_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK16 | CMXFCR_TF2CS_CLK13) #define CFG_CPMFCR_RAMTYPE 0 #define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) @@ -342,7 +340,8 @@ #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3) #define CONFIG_ETHER_ON_FCC3 -#define CFG_CMXFCR_MASK3 (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK) +#define CFG_CMXFCR_MASK3 (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | \ + CMXFCR_TF3CS_MSK) #define CFG_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15 | CMXFCR_TF3CS_CLK14) #define CFG_CPMFCR_RAMTYPE 0 #define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) @@ -353,7 +352,7 @@ */ #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x20000) -#define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ +#define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ #define CFG_ENV_SIZE 0x2000 #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) @@ -361,8 +360,7 @@ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ -#define CONFIG_TIMESTAMP /* Print image info with ts */ - +#define CONFIG_TIMESTAMP /* Print image info with ts */ /* * BOOTP options @@ -372,7 +370,6 @@ #define CONFIG_BOOTP_GATEWAY #define CONFIG_BOOTP_HOSTNAME - /* * Command line configuration. */ @@ -389,10 +386,9 @@ #define CONFIG_CMD_MII #if defined(CONFIG_PCI) - #define CONFIG_CMD_PCI +#define CONFIG_CMD_PCI #endif - #undef CONFIG_WATCHDOG /* watchdog disabled */ /* @@ -403,12 +399,13 @@ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) - #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else - #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ #endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buf Size */ +#define CFG_PBSIZE (CFG_CBSIZE + \ + sizeof(CFG_PROMPT) + 16) /* Print Buf Size */ #define CFG_MAXARGS 16 /* max number of command args */ #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ @@ -433,7 +430,6 @@ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif - #define CONFIG_LOADADDR 200000 /* default addr for tftp & bootm*/ #define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */ @@ -467,10 +463,10 @@ "ramdisk_addr=FE180000\0" \ "load=tftp 100000 /tftpboot/$hostname/u-boot.bin\0" \ "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ - "cp.b 100000 fffc0000 40000;" \ + "cp.b 100000 fffc0000 40000;" \ "setenv filesize;saveenv\0" \ "upd=run load update\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" -#endif /* __CONFIG_H */ +#endif /* __CONFIG_H */ -- cgit From 46346f27cda6fd025a496bde8f2d4aeee04aca5f Mon Sep 17 00:00:00 2001 From: Wolfgang Grandegger Date: Thu, 5 Jun 2008 13:12:02 +0200 Subject: TQM85xx: Support for Spansion 'N' type flashes added The 'N' type Spansion flashes (S29GLxxxN series) have bigger sectors, than the formerly used 'M' types (S29GLxxxM series), so the flash layout needs to be changed -> new start address of the environment. The macro definition CONFIG_TQM_FLASH_N_TYPE is undefined by default and must be defined for boards with 'N' type flashes. Signed-off-by: Martin Krause Signed-off-by: Wolfgang Grandegger --- include/configs/TQM85xx.h | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) (limited to 'include/configs') diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h index f0e73184f4..432c155a85 100644 --- a/include/configs/TQM85xx.h +++ b/include/configs/TQM85xx.h @@ -108,6 +108,13 @@ #define CONFIG_DDR_DEFAULT_CL 30 /* CAS latency 3 */ #endif /* CONFIG_TQM8541 || CONFIG_TQM8555 */ +/* + * Old TQM85xx boards have 'M' type Spansion Flashes from the S29GLxxxM + * series while new boards have 'N' type Flashes from the S29GLxxxN + * series, which have bigger sectors: 2 x 128 instead of 2 x 64 KB. + */ +#undef CONFIG_TQM_FLASH_N_TYPE + /* * Flash on the Local Bus */ @@ -151,7 +158,7 @@ #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256kB for Mon */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ +#define CFG_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ /* Serial Port */ #if defined(CONFIG_TQM8560) @@ -351,10 +358,15 @@ * Environment */ #define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x20000) -#define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ + +#ifdef CONFIG_TQM_FLASH_N_TYPE +#define CFG_ENV_SECT_SIZE 0x40000 /* 256K (one sector) for env */ +#else /* !CONFIG_TQM_FLASH_N_TYPE */ +#define CFG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) for env */ +#endif /* CONFIG_TQM_FLASH_N_TYPE */ +#define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SECT_SIZE) #define CFG_ENV_SIZE 0x2000 -#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR - CFG_ENV_SECT_SIZE) #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -- cgit From d9ee843d54c54776e1fdb86336ce554906a87331 Mon Sep 17 00:00:00 2001 From: Wolfgang Grandegger Date: Thu, 5 Jun 2008 13:12:05 +0200 Subject: TQM85xx: Support for Intel 82527 compatible CAN controller This patch adds initialization of the UPMC RAM to support up to two Intel 82527 compatible CAN controller on the TQM85xx modules. Signed-off-by: Thomas Waehner Signed-off-by: Wolfgang Grandegger --- include/configs/TQM85xx.h | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'include/configs') diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h index 432c155a85..17df118561 100644 --- a/include/configs/TQM85xx.h +++ b/include/configs/TQM85xx.h @@ -52,6 +52,8 @@ #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ +#undef CONFIG_CAN_DRIVER /* CAN Driver support */ + /* * sysclk for MPC85xx * @@ -199,6 +201,15 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif +/* CAN */ +#ifdef CONFIG_CAN_DRIVER +#define CFG_CAN_BASE 0xE3000000 /* CAN base address */ +#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 KiB address mask */ +#define CFG_OR2_CAN (CFG_CAN_OR_AM | OR_UPM_BI) +#define CFG_BR2_CAN ((CFG_CAN_BASE & BR_BA) | \ + BR_PS_8 | BR_MS_UPMC | BR_V) +#endif /* CONFIG_CAN_DRIVER */ + /* * I2C */ -- cgit From 25991353204c78b094c3c1fec90182dcd607ab8f Mon Sep 17 00:00:00 2001 From: Wolfgang Grandegger Date: Thu, 5 Jun 2008 13:12:06 +0200 Subject: TQM85xx: Support for Flat Device Tree This patch adds support for Linux kernels using the Flat Device Tree. It also re-defines the default environment settings for booting Linux with the FDT blob. Signed-off-by: Wolfgang Grandegger --- include/configs/TQM85xx.h | 50 ++++++++++++++++++++++++++++++++++++----------- 1 file changed, 39 insertions(+), 11 deletions(-) (limited to 'include/configs') diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h index 17df118561..6320f00524 100644 --- a/include/configs/TQM85xx.h +++ b/include/configs/TQM85xx.h @@ -201,6 +201,11 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_OF_STDOUT_VIA_ALIAS 1 + /* CAN */ #ifdef CONFIG_CAN_DRIVER #define CFG_CAN_BASE 0xE3000000 /* CAN base address */ @@ -463,10 +468,26 @@ #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ + +/* + * Setup some board specific values for the default environment variables + */ +#ifdef CONFIG_CPM2 +#define CFG_ENV_CONSDEV "consdev=ttyCPM0\0" +#else +#define CFG_ENV_CONSDEV "consdev=ttyS0\0" +#endif +#define CFG_ENV_FDT_FILE "fdt_file="MK_STR(CONFIG_HOSTNAME)"/" \ + MK_STR(CONFIG_HOSTNAME)".dtb\0" +#define CFG_ENV_BOOTFILE "bootfile="MK_STR(CONFIG_HOSTNAME)"/uImage\0" +#define CFG_ENV_UBOOT "uboot="MK_STR(CONFIG_HOSTNAME)"/u-boot.bin\0" \ + "uboot_addr="MK_STR(TEXT_BASE)"\0" + #define CONFIG_EXTRA_ENV_SETTINGS \ - "bootfile="CFG_BOOTFILE_PATH"\0" \ + CFG_ENV_BOOTFILE \ + CFG_ENV_FDT_FILE \ + CFG_ENV_CONSDEV \ "netdev=eth0\0" \ - "consdev=ttyS0\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ "nfsroot=$serverip:$rootpath\0" \ "ramargs=setenv bootargs root=/dev/ram rw\0" \ @@ -476,17 +497,24 @@ "addcons=setenv bootargs $bootargs " \ "console=$consdev,$baudrate\0" \ "flash_nfs=run nfsargs addip addcons;" \ - "bootm $kernel_addr\0" \ + "bootm $kernel_addr - $fdt_addr\0" \ "flash_self=run ramargs addip addcons;" \ - "bootm $kernel_addr $ramdisk_addr\0" \ - "net_nfs=tftp $loadaddr $bootfile;" \ - "run nfsargs addip addcons;bootm\0" \ + "bootm $kernel_addr $ramdisk_addr $fdt_addr\0" \ + "net_nfs=tftp $kernel_addr_r $bootfile;" \ + "tftp $fdt_addr_r $fdt_file;" \ + "run nfsargs addip addcons;" \ + "bootm $kernel_addr_r - $fdt_addr_r\0" \ "rootpath=/opt/eldk/ppc_85xx\0" \ - "kernel_addr=FE000000\0" \ - "ramdisk_addr=FE180000\0" \ - "load=tftp 100000 /tftpboot/$hostname/u-boot.bin\0" \ - "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ - "cp.b 100000 fffc0000 40000;" \ + "fdt_addr_r=900000\0" \ + "kernel_addr_r=1000000\0" \ + "fdt_addr=ffec0000\0" \ + "kernel_addr=ffd00000\0" \ + "ramdisk_addr=ff800000\0" \ + CFG_ENV_UBOOT \ + "load=tftp 100000 $uboot\0" \ + "update=protect off $uboot_addr +$filesize;" \ + "erase $uboot_addr +$filesize;" \ + "cp.b 100000 $uboot_addr $filesize;" \ "setenv filesize;saveenv\0" \ "upd=run load update\0" \ "" -- cgit From 1287e0c55a2ee2c575ac9ce8e4302cd4085be876 Mon Sep 17 00:00:00 2001 From: Wolfgang Grandegger Date: Thu, 5 Jun 2008 13:12:07 +0200 Subject: TQM8548: Basic support for the TQM8548 modules This patch adds basic support for the TQM8548 module from TQ-Components (http://www.tqc.de/) including DDR2 SDRAM initialisation and support for eTSEC 3 and 4 Furthermore Flash buffer write has been enabled to speed up output to the Flash by approx. a factor of 10. Signed-off-by: Thomas Waehner Signed-off-by: Wolfgang Grandegger --- include/configs/TQM85xx.h | 71 +++++++++++++++++++++++++++++++++++++++++------ 1 file changed, 63 insertions(+), 8 deletions(-) (limited to 'include/configs') diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h index 6320f00524..a02d0018e3 100644 --- a/include/configs/TQM85xx.h +++ b/include/configs/TQM85xx.h @@ -1,4 +1,7 @@ /* + * (C) Copyright 2007 + * Thomas Waehner, TQ-System GmbH, thomas.waehner@tqs.de. + * * (C) Copyright 2005 * Stefan Roese, DENX Software Engineering, sr@denx.de. * @@ -27,7 +30,7 @@ */ /* - * TQM85xx (8560/40/55/41) board configuration file + * TQM85xx (8560/40/55/41/48) board configuration file */ #ifndef __CONFIG_H @@ -44,9 +47,9 @@ #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ /* - * Only MPC8540 doesn't have CPM module + * MPC8540 and MPC8548 don't have CPM module */ -#ifndef CONFIG_MPC8540 +#if !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8548) #define CONFIG_CPM2 1 /* has CPM2 */ #endif @@ -58,8 +61,8 @@ * sysclk for MPC85xx * * Two valid values are: - * 33000000 - * 66000000 + * 33333333 + * 66666666 * * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz * is likely the desired value here, so that is now the default. @@ -106,16 +109,19 @@ #define CONFIG_DDR_DEFAULT_CL 25 /* CAS latency 2,5 */ #endif /* CONFIG_TQM8540 || CONFIG_TQM8560 */ -#if defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555) +#if defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555) || \ + defined(CONFIG_TQM8548) #define CONFIG_DDR_DEFAULT_CL 30 /* CAS latency 3 */ -#endif /* CONFIG_TQM8541 || CONFIG_TQM8555 */ +#endif /* CONFIG_TQM8541 || CONFIG_TQM8555 || CONFIG_TQM8548 */ /* * Old TQM85xx boards have 'M' type Spansion Flashes from the S29GLxxxM * series while new boards have 'N' type Flashes from the S29GLxxxN * series, which have bigger sectors: 2 x 128 instead of 2 x 64 KB. */ -#undef CONFIG_TQM_FLASH_N_TYPE +#ifdef CONFIG_TQM8548 +#define CONFIG_TQM_FLASH_N_TYPE +#endif /* CONFIG_TQM8548 */ /* * Flash on the Local Bus @@ -127,6 +133,25 @@ #define CFG_LBC_FLASH_BASE CFG_FLASH1 /* Localbus flash start */ #define CFG_FLASH_BASE CFG_LBC_FLASH_BASE /* start of FLASH */ +/* Default ORx timings are for <= 41.7 MHz Local Bus Clock. + * + * Note: According to timing specifications external addr latch delay + * (EAD, bit #0) must be set if Local Bus Clock is > 83 MHz. + * + * For other Local Bus Clocks see following table: + * + * Clock/MHz CFG_ORx_PRELIM + * 166 0x.....CA5 + * 133 0x.....C85 + * 100 0x.....C65 + * 83 0x.....FA2 + * 66 0x.....C82 + * 50 0x.....C60 + * 42 0x.....040 + * 33 0x.....030 + * 25 0x.....020 + * + */ #define CFG_BR0_PRELIM 0xfc001801 /* port size 32bit */ #define CFG_OR0_PRELIM 0xfc000040 /* 64MB Flash */ #define CFG_BR1_PRELIM 0xf8001801 /* port size 32bit */ @@ -136,6 +161,7 @@ #define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector */ #define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash*/ +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* speed up output to Flash */ #define CFG_MAX_FLASH_BANKS 2 /* number of banks */ #define CFG_MAX_FLASH_SECT 512 /* sectors per device */ @@ -145,6 +171,14 @@ #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ +/* + * Note: when changing the Local Bus clock divider you have to + * change the timing values in CFG_ORx_PRELIM. + * + * LCRR[00:03] CLKDIV: System (CCB) clock divider. Valid values are 2, 4, 8. + * LCRR[16:17] EADC : External address delay cycles. It should be set to 2 + * for Local Bus Clock > 83.3 MHz. + */ #define CFG_LBC_LCRR 0x00030008 /* LB clock ratio reg */ #define CFG_LBC_LBCR 0x00000000 /* LB config reg */ #define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ @@ -296,6 +330,27 @@ #define CONFIG_HAS_ETH1 #define CONFIG_HAS_ETH2 +#ifdef CONFIG_TQM8548 +/* + * TQM8548 has 4 ethernet ports. 4 ETSEC's. + * + * On the STK85xx Starterkit the ETSEC3/4 ports are on an + * additional adapter (AIO) between module and Starterkit. + */ +#define CONFIG_TSEC3 1 +#define CONFIG_TSEC3_NAME "TSEC2" +#define CONFIG_TSEC4 1 +#define CONFIG_TSEC4_NAME "TSEC3" +#define TSEC3_PHY_ADDR 4 +#define TSEC4_PHY_ADDR 5 +#define TSEC3_PHYIDX 0 +#define TSEC4_PHYIDX 0 +#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define CONFIG_HAS_ETH3 +#define CONFIG_HAS_ETH4 +#endif /* CONFIG_TQM8548 */ + /* Options are TSEC[0-1], FEC */ #define CONFIG_ETHPRIME "TSEC0" -- cgit From b9e8078bb3f3c48111a7081e27279938c3a445e1 Mon Sep 17 00:00:00 2001 From: Wolfgang Grandegger Date: Thu, 5 Jun 2008 13:12:08 +0200 Subject: TQM8548: PCI express support This patch adds support for PCI express cards. The board support now uses common FSL PCI init code, for both, PCI and PCIe on all TQM85xx modules. Signed-off-by: Thomas Waehner Signed-off-by: Wolfgang Grandegger --- include/configs/TQM85xx.h | 35 ++++++++++++++++++++++++++++++++++- 1 file changed, 34 insertions(+), 1 deletion(-) (limited to 'include/configs') diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h index a02d0018e3..21551304ca 100644 --- a/include/configs/TQM85xx.h +++ b/include/configs/TQM85xx.h @@ -42,6 +42,14 @@ #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */ #define CONFIG_PCI +#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ +#define CONFIG_PCIX_CHECK /* PCIX olny works at 66 MHz */ +#ifdef CONFIG_TQM8548 +#define CONFIG_PCI1 +#define CONFIG_PCIE1 +#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ +#endif + #define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ @@ -97,6 +105,10 @@ #define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ +#define CFG_PCI1_ADDR (CFG_CCSRBAR + 0x8000) +#define CFG_PCI2_ADDR (CFG_CCSRBAR + 0x9000) +#define CFG_PCIE1_ADDR (CFG_CCSRBAR + 0xa000) + /* * DDR Setup */ @@ -282,10 +294,12 @@ #define CFG_DTT_LOW_TEMP -30 #define CFG_DTT_HYSTERESIS 3 +#ifndef CONFIG_PCIE1 /* RapidIO MMU */ #define CFG_RIO_MEM_BASE 0xc0000000 /* base address */ #define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE -#define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */ +#define CFG_RIO_MEM_SIZE 0x20000000 /* 512M */ +#endif /* CONFIG_PCIE1 */ /* * General PCI @@ -298,6 +312,25 @@ #define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE #define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ +/* PCI view of System Memory */ +#define CFG_PCI_MEMORY_BUS 0x00000000 +#define CFG_PCI_MEMORY_PHYS 0x00000000 +#define CFG_PCI_MEMORY_SIZE 0x80000000 + +#ifdef CONFIG_PCIE1 +/* + * General PCI express + * Addresses are mapped 1-1. + */ +#define CFG_PCIE1_MEM_BASE 0xc0000000 +#define CFG_PCIE1_MEM_PHYS CFG_PCIE1_MEM_BASE +#define CFG_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CFG_PCIE1_IO_BASE 0xef000000 +#define CFG_PCIE1_IO_PHYS CFG_PCIE1_IO_BASE +#define CFG_PCIE1_IO_SIZE 0x1000000 /* 16M */ + +#endif /* CONFIG_PCIE1 */ + #if defined(CONFIG_PCI) #define CONFIG_PCI_PNP /* do pci plug-and-play */ -- cgit From 1c2deff22cd6e2bf0e618fd6e09ca3eec5a8d051 Mon Sep 17 00:00:00 2001 From: Wolfgang Grandegger Date: Thu, 5 Jun 2008 13:12:09 +0200 Subject: TQM85xx: NAND support via local bus UPMB This patch adds support for NAND FLASH on the TQM8548. It is disabled by default and can be enabled for the TQM8548 modules. It is now based on the re-written FSL NAND UPM driver. A patch has been posted earlier today with the subject: "NAND FSL UPM: driver re-write using the hwcontrol callback" Note that the R/B pin is not supported by that module requiring to use the specified maximum delay time. Note: With NAND support enabled the size of the U-Boot image exceeds 256 KB and TEXT_BASE must therefore be set to 0xfff80000 in config.mk, doubling the image size :-(. Signed-off-by: Thomas Waehner Signed-off-by: Wolfgang Grandegger --- include/configs/TQM85xx.h | 81 +++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 78 insertions(+), 3 deletions(-) (limited to 'include/configs') diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h index 21551304ca..b188adf232 100644 --- a/include/configs/TQM85xx.h +++ b/include/configs/TQM85xx.h @@ -54,6 +54,14 @@ #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ +/* + * NAND flash support (disabled by default) + * + * Warning: NAND support will likely increase the U-Boot image size + * to more than 256 KB. Please adjust TEXT_BASE if necessary. + */ +#undef CONFIG_NAND + /* * MPC8540 and MPC8548 don't have CPM module */ @@ -205,8 +213,8 @@ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256kB for Mon */ -#define CFG_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ +#define CFG_MONITOR_LEN (~TEXT_BASE + 1)/* Reserved for Monitor */ +#define CFG_MALLOC_LEN (384 * 1024) /* Reserved for malloc */ /* Serial Port */ #if defined(CONFIG_TQM8560) @@ -253,8 +261,8 @@ #define CONFIG_OF_STDOUT_VIA_ALIAS 1 /* CAN */ -#ifdef CONFIG_CAN_DRIVER #define CFG_CAN_BASE 0xE3000000 /* CAN base address */ +#ifdef CONFIG_CAN_DRIVER #define CFG_CAN_OR_AM 0xFFFF8000 /* 32 KiB address mask */ #define CFG_OR2_CAN (CFG_CAN_OR_AM | OR_UPM_BI) #define CFG_BR2_CAN ((CFG_CAN_BASE & BR_BA) | \ @@ -301,6 +309,53 @@ #define CFG_RIO_MEM_SIZE 0x20000000 /* 512M */ #endif /* CONFIG_PCIE1 */ +/* NAND FLASH */ +#ifdef CONFIG_NAND + +#undef CFG_NAND_LEGACY + +#define CONFIG_NAND_FSL_UPM 1 + +#define CONFIG_MTD_NAND_ECC_JFFS2 1 /* use JFFS2 ECC */ + +/* address distance between chip selects */ +#define CFG_NAND_SELECT_DEVICE 1 +#define CFG_NAND_CS_DIST 0x200 + +#define CFG_NAND_SIZE 0x8000 +#define CFG_NAND0_BASE 0xE3010000 +#define CFG_NAND1_BASE (CFG_NAND0_BASE + CFG_NAND_CS_DIST) +#define CFG_NAND2_BASE (CFG_NAND1_BASE + CFG_NAND_CS_DIST) +#define CFG_NAND3_BASE (CFG_NAND2_BASE + CFG_NAND_CS_DIST) + +#define CFG_MAX_NAND_DEVICE 2 /* Max number of NAND devices */ +#define NAND_MAX_CHIPS 1 + +#if (CFG_MAX_NAND_DEVICE == 1) +#define CFG_NAND_BASE_LIST { CFG_NAND0_BASE } +#elif (CFG_MAX_NAND_DEVICE == 2) +#define CFG_NAND_QUIET_TEST 1 +#define CFG_NAND_BASE_LIST { CFG_NAND0_BASE, \ + CFG_NAND1_BASE, \ +} +#elif (CFG_MAX_NAND_DEVICE == 4) +#define CFG_NAND_QUIET_TEST 1 +#define CFG_NAND_BASE_LIST { CFG_NAND0_BASE, \ + CFG_NAND1_BASE, \ + CFG_NAND2_BASE, \ + CFG_NAND3_BASE, \ +} +#endif + +/* CS3 for NAND Flash */ +#define CFG_BR3_PRELIM ((CFG_NAND0_BASE & BR_BA) | BR_PS_8 | \ + BR_MS_UPMB | BR_V) +#define CFG_OR3_PRELIM (P2SZ_TO_AM(CFG_NAND_SIZE) | OR_UPM_BI) + +#define NAND_BIG_DELAY_US 25 /* max tR for Samsung devices */ + +#endif /* CONFIG_NAND */ + /* * General PCI * Addresses are mapped 1-1. @@ -486,6 +541,26 @@ #define CONFIG_BOOTP_GATEWAY #define CONFIG_BOOTP_HOSTNAME +#ifdef CONFIG_NAND +/* + * Use NAND-FLash as JFFS2 device + */ +#define CONFIG_CMD_NAND +#define CONFIG_CMD_JFFS2 + +#define CONFIG_JFFS2_NAND 1 + +#ifdef CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nand0=TQM85xx-nand" +#define MTDPARTS_DEFAULT "mtdparts=TQM85xx-nand:-" +#else +#define CONFIG_JFFS2_DEV "nand0" /* NAND device jffs2 lives on */ +#define CONFIG_JFFS2_PART_OFFSET 0 /* start of jffs2 partition */ +#define CONFIG_JFFS2_PART_SIZE 0x200000 /* size of jffs2 partition */ +#endif /* CONFIG_JFFS2_CMDLINE */ + +#endif /* CONFIG_NAND */ + /* * Command line configuration. */ -- cgit From e8cc3f04b124f757af4528206e60d8eb715ae083 Mon Sep 17 00:00:00 2001 From: Wolfgang Grandegger Date: Thu, 5 Jun 2008 13:12:10 +0200 Subject: TQM85xx: Change memory map to support Flash memory > 128 MiB Some TQM85xx boards could be equipped with up to 1 GiB (NOR) Flash memory. The current memory map only supports up to 128 MiB Flash. This patch adds the configuration option CONFIG_TQM_BIGFLASH. If set, up to 1 GiB flash is supported. To achieve this, the memory map has to be adjusted in great parts (for example the CCSRBAR is moved from 0xE0000000 to 0xA0000000). If you want to boot Linux with CONFIG_TQM_BIGFLASH set, the new memory map also has to be considered in the kernel (changed CCSRBAR address, changed PCI IO base address, ...). Please use an appropriate Flat Device Tree blob (tqm8548.dtb). Signed-off-by: Martin Krause Signed-off-by: Wolfgang Grandegger --- include/configs/TQM85xx.h | 52 ++++++++++++++++++++++++++++++++++++++++------- 1 file changed, 45 insertions(+), 7 deletions(-) (limited to 'include/configs') diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h index b188adf232..d18f2346c6 100644 --- a/include/configs/TQM85xx.h +++ b/include/configs/TQM85xx.h @@ -54,6 +54,16 @@ #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ + /* + * Configuration for big NOR Flashes + * + * Define CONFIG_TQM_BIGFLASH for boards with more than 128 MiB NOR Flash. + * Please be aware, that this changes the whole memory map (new CCSRBAR + * address, etc). You have to use an adapted Linux kernel or FDT blob + * if this option is set. + */ +#undef CONFIG_TQM_BIGFLASH + /* * NAND flash support (disabled by default) * @@ -109,7 +119,11 @@ * actual resources get mapped (not physical addresses) */ #define CFG_CCSRBAR_DEFAULT 0xFF700000 /* CCSRBAR Default */ +#ifdef CONFIG_TQM_BIGFLASH +#define CFG_CCSRBAR 0xA0000000 /* relocated CCSRBAR */ +#else /* !CONFIG_TQM_BIGFLASH */ #define CFG_CCSRBAR 0xE0000000 /* relocated CCSRBAR */ +#endif /* CONFIG_TQM_BIGFLASH */ #define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ @@ -146,8 +160,13 @@ /* * Flash on the Local Bus */ +#ifdef CONFIG_TQM_BIGFLASH +#define CFG_FLASH0 0xE0000000 +#define CFG_FLASH1 0xC0000000 +#else /* !CONFIG_TQM_BIGFLASH */ #define CFG_FLASH0 0xFC000000 #define CFG_FLASH1 0xF8000000 +#endif /* CONFIG_TQM_BIGFLASH */ #define CFG_FLASH_BANKS_LIST { CFG_FLASH1, CFG_FLASH0 } #define CFG_LBC_FLASH_BASE CFG_FLASH1 /* Localbus flash start */ @@ -172,10 +191,17 @@ * 25 0x.....020 * */ +#ifdef CONFIG_TQM_BIGFLASH +#define CFG_BR0_PRELIM 0xE0001801 /* port size 32bit */ +#define CFG_OR0_PRELIM 0xE0000040 /* 512MB Flash */ +#define CFG_BR1_PRELIM 0xC0001801 /* port size 32bit */ +#define CFG_OR1_PRELIM 0xE0000040 /* 512MB Flash */ +#else /* !CONFIG_TQM_BIGFLASH */ #define CFG_BR0_PRELIM 0xfc001801 /* port size 32bit */ #define CFG_OR0_PRELIM 0xfc000040 /* 64MB Flash */ #define CFG_BR1_PRELIM 0xf8001801 /* port size 32bit */ #define CFG_OR1_PRELIM 0xfc000040 /* 64MB Flash */ +#endif /* CONFIG_TQM_BIGFLASH */ #define CFG_FLASH_CFI /* flash is CFI compat. */ #define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ @@ -206,7 +232,8 @@ #define CONFIG_L1_INIT_RAM #define CFG_INIT_RAM_LOCK 1 -#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ +#define CFG_INIT_RAM_ADDR (CFG_CCSRBAR \ + + 0x04010000) /* Initial RAM address */ #define CFG_INIT_RAM_END 0x4000 /* End used area in RAM */ #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ @@ -261,7 +288,8 @@ #define CONFIG_OF_STDOUT_VIA_ALIAS 1 /* CAN */ -#define CFG_CAN_BASE 0xE3000000 /* CAN base address */ +#define CFG_CAN_BASE (CFG_CCSRBAR \ + + 0x03000000) /* CAN base address */ #ifdef CONFIG_CAN_DRIVER #define CFG_CAN_OR_AM 0xFFFF8000 /* 32 KiB address mask */ #define CFG_OR2_CAN (CFG_CAN_OR_AM | OR_UPM_BI) @@ -304,9 +332,14 @@ #ifndef CONFIG_PCIE1 /* RapidIO MMU */ +#ifdef CONFIG_TQM_BIGFLASH +#define CFG_RIO_MEM_BASE 0xb0000000 /* base address */ +#define CFG_RIO_MEM_SIZE 0x10000000 /* 256M */ +#else /* !CONFIG_TQM_BIGFLASH */ #define CFG_RIO_MEM_BASE 0xc0000000 /* base address */ -#define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE #define CFG_RIO_MEM_SIZE 0x20000000 /* 512M */ +#endif /* CONFIG_TQM_BIGFLASH */ +#define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE #endif /* CONFIG_PCIE1 */ /* NAND FLASH */ @@ -323,7 +356,7 @@ #define CFG_NAND_CS_DIST 0x200 #define CFG_NAND_SIZE 0x8000 -#define CFG_NAND0_BASE 0xE3010000 +#define CFG_NAND0_BASE (CFG_CCSRBAR + 0x03010000) #define CFG_NAND1_BASE (CFG_NAND0_BASE + CFG_NAND_CS_DIST) #define CFG_NAND2_BASE (CFG_NAND1_BASE + CFG_NAND_CS_DIST) #define CFG_NAND3_BASE (CFG_NAND2_BASE + CFG_NAND_CS_DIST) @@ -363,7 +396,7 @@ #define CFG_PCI1_MEM_BASE 0x80000000 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI1_IO_BASE 0xe2000000 +#define CFG_PCI1_IO_BASE (CFG_CCSRBAR + 0x02000000) #define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE #define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ @@ -377,13 +410,18 @@ * General PCI express * Addresses are mapped 1-1. */ +#ifdef CONFIG_TQM_BIGFLASH +#define CFG_PCIE1_MEM_BASE 0xb0000000 +#define CFG_PCIE1_MEM_SIZE 0x10000000 /* 512M */ +#define CFG_PCIE1_IO_BASE 0xaf000000 +#else /* !CONFIG_TQM_BIGFLASH */ #define CFG_PCIE1_MEM_BASE 0xc0000000 -#define CFG_PCIE1_MEM_PHYS CFG_PCIE1_MEM_BASE #define CFG_PCIE1_MEM_SIZE 0x20000000 /* 512M */ #define CFG_PCIE1_IO_BASE 0xef000000 +#endif /* CONFIG_TQM_BIGFLASH */ +#define CFG_PCIE1_MEM_PHYS CFG_PCIE1_MEM_BASE #define CFG_PCIE1_IO_PHYS CFG_PCIE1_IO_BASE #define CFG_PCIE1_IO_SIZE 0x1000000 /* 16M */ - #endif /* CONFIG_PCIE1 */ #if defined(CONFIG_PCI) -- cgit From d39e68514ff943930ee692cff3fde03532eb7fec Mon Sep 17 00:00:00 2001 From: Sergei Poselenov Date: Fri, 6 Jun 2008 15:42:39 +0200 Subject: Socrates: config file cleanup. Signed-off-by: Sergei Poselenov --- include/configs/socrates.h | 12 +++--------- 1 file changed, 3 insertions(+), 9 deletions(-) (limited to 'include/configs') diff --git a/include/configs/socrates.h b/include/configs/socrates.h index 6dc9effde4..6012a99d12 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -238,13 +238,7 @@ #if defined(CONFIG_PCI) #define CONFIG_PCI_PNP /* do pci plug-and-play */ - -#define CONFIG_EEPRO100 -#undef CONFIG_TULIP - -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ - +#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #endif /* CONFIG_PCI */ @@ -390,10 +384,10 @@ "tftp ${fdt_addr_r} ${fdt_file}; " \ "run nfsargs addip addcons;" \ "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ - "fdt_file=$hostname/socrates.dtb\0" \ + "fdt_file=$hostname/socrates.dtb\0" \ "fdt_addr_r=B00000\0" \ "fdt_addr=FC1E0000\0" \ - "rootpath=/opt/eldk/ppc_85xx\0" \ + "rootpath=/opt/eldk/ppc_85xxDP\0" \ "kernel_addr=FC000000\0" \ "kernel_addr_r=200000\0" \ "ramdisk_addr=FC200000\0" \ -- cgit From 59abd15b43cab7a4d19de4ba0943837d9555f7ba Mon Sep 17 00:00:00 2001 From: Sergei Poselenov Date: Fri, 6 Jun 2008 15:42:41 +0200 Subject: Socrates: Added FPGA mapping. LAWs and TLBs cleanup. Signed-off-by: Sergei Poselenov --- include/configs/socrates.h | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) (limited to 'include/configs') diff --git a/include/configs/socrates.h b/include/configs/socrates.h index 6012a99d12..499f41ceb1 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -216,11 +216,6 @@ #define CFG_EEPROM_PAGE_WRITE_ENABLE /* necessary for the LM75 chip */ #define CFG_EEPROM_PAGE_WRITE_BITS 4 -/* RapidIO MMU */ -#define CFG_RIO_MEM_BASE 0xc0000000 /* base address */ -#define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE -#define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */ - /* * General PCI * Memory space is mapped 1-1. @@ -414,4 +409,8 @@ #define CONFIG_DOS_PARTITION 1 #define CONFIG_USB_STORAGE 1 +/* FPGA and NAND */ +#define CFG_FPGA_BASE 0xc0000000 +#define CFG_BR3_PRELIM 0xc0001881 /* UPMA, 32-bit */ +#define CFG_OR3_PRELIM 0xfff00000 /* 1 MB */ #endif /* __CONFIG_H */ -- cgit From fd51b0e0e620b8bc9fd4f6daa3a4fa6f5e1316f4 Mon Sep 17 00:00:00 2001 From: Sergei Poselenov Date: Fri, 6 Jun 2008 15:42:44 +0200 Subject: Socrates: NAND support added. Changed the U-Boot base address and Signed-off-by: Sergei Poselenov --- include/configs/socrates.h | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'include/configs') diff --git a/include/configs/socrates.h b/include/configs/socrates.h index 499f41ceb1..16274137dc 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -165,7 +165,7 @@ #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256kB for Mon*/ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ +#define CFG_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ /* Serial Port */ @@ -413,4 +413,10 @@ #define CFG_FPGA_BASE 0xc0000000 #define CFG_BR3_PRELIM 0xc0001881 /* UPMA, 32-bit */ #define CFG_OR3_PRELIM 0xfff00000 /* 1 MB */ + +#define CFG_NAND_BASE (CFG_FPGA_BASE + 0x70) +#define CFG_MAX_NAND_DEVICE 1 +#define NAND_MAX_CHIPS 1 +#define CONFIG_CMD_NAND + #endif /* __CONFIG_H */ -- cgit From 978e81604c1b28526ed580df0fbe64eb8384e94f Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Mon, 9 Jun 2008 13:37:24 -0500 Subject: 85xx: Remove unused and unconfigured memory test code. Remove unused and unconfigured DDR test code from FSL 85xx boards. Besides, other common code exists. Signed-off-by: Kumar Gala --- include/configs/MPC8540ADS.h | 1 - include/configs/MPC8541CDS.h | 1 - include/configs/MPC8544DS.h | 2 -- include/configs/MPC8548CDS.h | 1 - include/configs/MPC8555CDS.h | 1 - include/configs/MPC8560ADS.h | 1 - include/configs/MPC8568MDS.h | 1 - 7 files changed, 8 deletions(-) (limited to 'include/configs') diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index 5719759808..37f062f947 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -89,7 +89,6 @@ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ -#undef CFG_DRAM_TEST /* memory test, takes time */ #define CFG_MEMTEST_START 0x00200000 /* memtest region */ #define CFG_MEMTEST_END 0x00400000 diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index 5b3ea05e63..65a34cc33b 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -75,7 +75,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ -#undef CFG_DRAM_TEST /* memory test, takes time */ #define CFG_MEMTEST_START 0x00200000 /* memtest works on */ #define CFG_MEMTEST_END 0x00400000 diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index ffe9e0089d..d5006b5236 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -86,10 +86,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ -#undef CFG_DRAM_TEST /* memory test, takes time */ #define CFG_MEMTEST_START 0x00200000 /* memtest works on */ #define CFG_MEMTEST_END 0x00400000 -#define CFG_ALT_MEMTEST #define CONFIG_PANIC_HANG /* do not reset board on panic */ /* diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index fc8ad8813f..51c9064c65 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -89,7 +89,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ -#undef CFG_DRAM_TEST /* memory test, takes time */ #define CFG_MEMTEST_START 0x00200000 /* memtest works on */ #define CFG_MEMTEST_END 0x00400000 diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h index e8383455c4..797644f0d3 100644 --- a/include/configs/MPC8555CDS.h +++ b/include/configs/MPC8555CDS.h @@ -75,7 +75,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ -#undef CFG_DRAM_TEST /* memory test, takes time */ #define CFG_MEMTEST_START 0x00200000 /* memtest works on */ #define CFG_MEMTEST_END 0x00400000 diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h index 9c95cc6567..52e9362eac 100644 --- a/include/configs/MPC8560ADS.h +++ b/include/configs/MPC8560ADS.h @@ -84,7 +84,6 @@ #define CFG_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */ -#undef CFG_DRAM_TEST /* memory test, takes time */ #define CFG_MEMTEST_START 0x00200000 /* memtest region */ #define CFG_MEMTEST_END 0x00400000 diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index a7c69d293c..9e6bb44ff9 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -80,7 +80,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ -#undef CFG_DRAM_TEST /* memory test, takes time */ #define CFG_MEMTEST_START 0x00200000 /* memtest works on */ #define CFG_MEMTEST_END 0x00400000 -- cgit From 81e56e9af0d43712db8efb843606a8d62eab454f Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Mon, 9 Jun 2008 18:55:38 -0500 Subject: MPC8544DS: Update config.h * Enable flash progress * remove CLEAR_LAW0 since we dont really use it Signed-off-by: Kumar Gala --- include/configs/MPC8544DS.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include/configs') diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index d5006b5236..acb16829fb 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -77,7 +77,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_L2_CACHE /* toggle L2 cache */ #define CONFIG_BTB /* toggle branch predition */ #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ -#define CONFIG_CLEAR_LAW0 /* Clear LAW0 in cpu_init_r */ /* * Only possible on E500 Version 2 or newer cores. @@ -169,6 +168,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #undef CFG_FLASH_CHECKSUM #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ +#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ -- cgit From ddde74a159caa6e18b481fec01d40b885aebb566 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Mon, 9 Jun 2008 22:31:57 -0500 Subject: 85xx: remove dummy board_early_init_f A number of board ports have empty version of board_early_init_f for no reason since we control its via CONFIG_BOARD_EARLY_INIT_F. Signed-off-by: Kumar Gala --- include/configs/MPC8540ADS.h | 2 -- include/configs/MPC8541CDS.h | 2 -- include/configs/MPC8544DS.h | 2 -- include/configs/MPC8548CDS.h | 2 -- include/configs/MPC8555CDS.h | 2 -- include/configs/MPC8560ADS.h | 2 -- 6 files changed, 12 deletions(-) (limited to 'include/configs') diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index 37f062f947..d1d3cc3606 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -87,8 +87,6 @@ #define CONFIG_BTB /* toggle branch predition */ #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ - #define CFG_MEMTEST_START 0x00200000 /* memtest region */ #define CFG_MEMTEST_END 0x00400000 diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index 65a34cc33b..a64565db93 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -73,8 +73,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_BTB /* toggle branch predition */ #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ - #define CFG_MEMTEST_START 0x00200000 /* memtest works on */ #define CFG_MEMTEST_END 0x00400000 diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index acb16829fb..669f4d7c8b 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -83,8 +83,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); */ #define CONFIG_ENABLE_36BIT_PHYS 1 -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ - #define CFG_MEMTEST_START 0x00200000 /* memtest works on */ #define CFG_MEMTEST_END 0x00400000 #define CONFIG_PANIC_HANG /* do not reset board on panic */ diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 51c9064c65..acf6f0dce6 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -87,8 +87,6 @@ extern unsigned long get_clock_freq(void); */ #define CONFIG_ENABLE_36BIT_PHYS 1 -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ - #define CFG_MEMTEST_START 0x00200000 /* memtest works on */ #define CFG_MEMTEST_END 0x00400000 diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h index 797644f0d3..1948c0d276 100644 --- a/include/configs/MPC8555CDS.h +++ b/include/configs/MPC8555CDS.h @@ -73,8 +73,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_BTB /* toggle branch predition */ #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ - #define CFG_MEMTEST_START 0x00200000 /* memtest works on */ #define CFG_MEMTEST_END 0x00400000 diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h index 52e9362eac..a3fcad35d2 100644 --- a/include/configs/MPC8560ADS.h +++ b/include/configs/MPC8560ADS.h @@ -80,8 +80,6 @@ #define CONFIG_BTB /* toggle branch predition */ #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ - #define CFG_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */ #define CFG_MEMTEST_START 0x00200000 /* memtest region */ -- cgit From f060054dadbbe7027ca088eed806a3ef1f82fdb7 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 11 Jun 2008 00:44:10 -0500 Subject: FSL LAW: Keep track of LAW allocations Make it so we keep track of which LAWs have allocated and provide a function (set_next_law) which can allocate a LAW for us if one is free. In the future we will move to doing more "dynamic" LAW allocation since the majority of users dont really care about what LAW number they are at. Also, add CONFIG_MPC8540 or CONFIG_MPC8560 to those boards which needed them Signed-off-by: Kumar Gala Signed-off-by: Andy Fleming --- include/configs/MPC8560ADS.h | 1 + include/configs/SBC8540.h | 1 + include/configs/sbc8560.h | 1 + include/configs/stxgp3.h | 1 + include/configs/stxssa.h | 1 + 5 files changed, 5 insertions(+) (limited to 'include/configs') diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h index a3fcad35d2..edf8525179 100644 --- a/include/configs/MPC8560ADS.h +++ b/include/configs/MPC8560ADS.h @@ -40,6 +40,7 @@ #define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ #define CONFIG_CPM2 1 /* has CPM2 */ #define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific */ +#define CONFIG_MPC8560 1 #define CONFIG_PCI #define CONFIG_TSEC_ENET /* tsec ethernet support */ diff --git a/include/configs/SBC8540.h b/include/configs/SBC8540.h index ff64378f20..8a53fdd0cb 100644 --- a/include/configs/SBC8540.h +++ b/include/configs/SBC8540.h @@ -49,6 +49,7 @@ #define CONFIG_CPM2 1 /* has CPM2 */ #define CONFIG_SBC8540 1 /* configuration for SBC8560 board */ +#define CONFIG_MPC8540 1 #define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific (supplement) */ diff --git a/include/configs/sbc8560.h b/include/configs/sbc8560.h index 81a1e072c6..146eafe9cc 100644 --- a/include/configs/sbc8560.h +++ b/include/configs/sbc8560.h @@ -42,6 +42,7 @@ #define CONFIG_CPM2 1 /* has CPM2 */ #define CONFIG_SBC8560 1 /* configuration for SBC8560 board */ +#define CONFIG_MPC8560 1 /* XXX flagging this as something I might want to delete */ #define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific */ diff --git a/include/configs/stxgp3.h b/include/configs/stxgp3.h index ec04a30bec..6e8213d72a 100644 --- a/include/configs/stxgp3.h +++ b/include/configs/stxgp3.h @@ -41,6 +41,7 @@ #define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ #define CONFIG_CPM2 1 /* has CPM2 */ #define CONFIG_STXGP3 1 /* Silicon Tx GPPP board specific*/ +#define CONFIG_MPC8560 1 #undef CONFIG_PCI /* pci ethernet support */ #define CONFIG_TSEC_ENET /* tsec ethernet support*/ diff --git a/include/configs/stxssa.h b/include/configs/stxssa.h index d033c866d7..a1e9789ea0 100644 --- a/include/configs/stxssa.h +++ b/include/configs/stxssa.h @@ -41,6 +41,7 @@ #define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ #define CONFIG_CPM2 1 /* has CPM2 */ #define CONFIG_STXSSA 1 /* Silicon Tx GPPP SSA board specific*/ +#define CONFIG_MPC8560 1 #define CONFIG_PCI /* PCI ethernet support */ #define CONFIG_TSEC_ENET /* tsec ethernet support*/ -- cgit From 5f723a3b98c630bde33de74351f2121691fdef14 Mon Sep 17 00:00:00 2001 From: Haavard Skinnemoen Date: Fri, 20 Jun 2008 10:41:05 +0200 Subject: avr32: Enable SPI flash support on ATNGW100 The ATNGW100 has 8MB DataFlash on board. Give users access to it through the new SPI flash framework. Signed-off-by: Haavard Skinnemoen --- include/configs/atngw100.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'include/configs') diff --git a/include/configs/atngw100.h b/include/configs/atngw100.h index 3fc9975637..7ac51b543c 100644 --- a/include/configs/atngw100.h +++ b/include/configs/atngw100.h @@ -114,6 +114,8 @@ #define CONFIG_CMD_FAT #define CONFIG_CMD_JFFS2 #define CONFIG_CMD_MMC +#define CONFIG_CMD_SF +#define CONFIG_CMD_SPI #undef CONFIG_CMD_AUTOSCRIPT #undef CONFIG_CMD_FPGA @@ -126,6 +128,10 @@ #define CFG_NR_PIOS 5 #define CFG_HSDRAMC 1 #define CONFIG_MMC 1 +#define CONFIG_ATMEL_SPI 1 + +#define CONFIG_SPI_FLASH 1 +#define CONFIG_SPI_FLASH_ATMEL 1 #define CFG_DCACHE_LINESZ 32 #define CFG_ICACHE_LINESZ 32 -- cgit From 6a19c46cae43c16c528eddefae3db97134f1915d Mon Sep 17 00:00:00 2001 From: Andre Schwarz Date: Mon, 23 Jun 2008 13:25:34 +0200 Subject: fix non-working mvBL-M7 Add missing #define CONFIG_HIGH_BATS in mvBL-M7 board config file. Signed-off-by: Andre Schwarz Signed-off-by: Kim Phillips --- include/configs/MVBLM7.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/configs') diff --git a/include/configs/MVBLM7.h b/include/configs/MVBLM7.h index 349ca14bba..021b72dc2b 100644 --- a/include/configs/MVBLM7.h +++ b/include/configs/MVBLM7.h @@ -336,6 +336,7 @@ #define CFG_HID0_FINAL CFG_HID0_INIT #define CFG_HID2 HID2_HBE +#define CONFIG_HIGH_BATS 1 /* DDR */ #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -- cgit From c7f879ec2b389c4f2bf726b293bd516f4c692e03 Mon Sep 17 00:00:00 2001 From: Hugo Villeneuve Date: Wed, 21 May 2008 13:58:41 -0400 Subject: ARM: Add support for Lyrtech SFF-SDR board (ARM926EJS) This patch adds support for the Lyrtech SFF-SDR board, based on the TI DaVinci architecture (ARM926EJS). Signed-off-by: Hugo Villeneuve Signed-off-by: Philip Balister Signed-off-by: Wolfgang Denk --- include/configs/davinci_sffsdr.h | 177 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 177 insertions(+) create mode 100644 include/configs/davinci_sffsdr.h (limited to 'include/configs') diff --git a/include/configs/davinci_sffsdr.h b/include/configs/davinci_sffsdr.h new file mode 100644 index 0000000000..41a6763e8f --- /dev/null +++ b/include/configs/davinci_sffsdr.h @@ -0,0 +1,177 @@ +/* + * Copyright (C) 2007 Sergey Kubushyn + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H +#include + +/*=======*/ +/* Board */ +/*=======*/ +#define SFFSDR +#define CFG_NAND_LARGEPAGE +#define CFG_USE_NAND +/*===================*/ +/* SoC Configuration */ +/*===================*/ +#define CONFIG_ARM926EJS /* arm926ejs CPU core */ +#define CONFIG_SYS_CLK_FREQ 297000000 /* Arm Clock frequency */ +#define CFG_TIMERBASE 0x01c21400 /* use timer 0 */ +#define CFG_HZ_CLOCK 27000000 /* Timer Input clock freq */ +#define CFG_HZ 1000 +/*==================================================*/ +/* EEPROM definitions for Atmel 24LC64 EEPROM chip */ +/*==================================================*/ +#define CFG_I2C_EEPROM_ADDR_LEN 2 +#define CFG_I2C_EEPROM_ADDR 0x50 +#define CFG_EEPROM_PAGE_WRITE_BITS 5 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20 +/*=============*/ +/* Memory Info */ +/*=============*/ +#define CFG_MALLOC_LEN (0x10000 + 256*1024) /* malloc() len */ +#define CFG_GBL_DATA_SIZE 128 /* reserved for initial data */ +#define CFG_MEMTEST_START 0x80000000 /* memtest start address */ +#define CFG_MEMTEST_END 0x81000000 /* 16MB RAM test */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define CONFIG_STACKSIZE (256*1024) /* regular stack */ +#define PHYS_SDRAM_1 0x80000000 /* DDR Start */ +#define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */ +#define DDR_4BANKS /* 4-bank DDR2 (128MB) */ +/*====================*/ +/* Serial Driver info */ +/*====================*/ +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE 4 /* NS16550 register size */ +#define CFG_NS16550_COM1 0x01c20000 /* Base address of UART0 */ +#define CFG_NS16550_CLK 27000000 /* Input clock to NS16550 */ +#define CONFIG_CONS_INDEX 1 /* use UART0 for console */ +#define CONFIG_BAUDRATE 115200 /* Default baud rate */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +/*===================*/ +/* I2C Configuration */ +/*===================*/ +#define CONFIG_HARD_I2C +#define CONFIG_DRIVER_DAVINCI_I2C +#define CFG_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */ +#define CFG_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ +/*==================================*/ +/* Network & Ethernet Configuration */ +/*==================================*/ +#define CONFIG_DRIVER_TI_EMAC +#define CONFIG_MII +#define CONFIG_BOOTP_DEFAULT +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_NET_RETRY_COUNT 10 +#define CONFIG_OVERWRITE_ETHADDR_ONCE +/*=====================*/ +/* Flash & Environment */ +/*=====================*/ +#undef CFG_ENV_IS_IN_FLASH +#define CFG_NO_FLASH +#define CFG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */ +#define CFG_ENV_SECT_SIZE 2048 /* Env sector Size */ +#define CFG_ENV_SIZE SZ_128K +#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */ +#define CONFIG_SKIP_RELOCATE_UBOOT /* to a proper address, init done */ +#define CFG_NAND_BASE 0x02000000 +#define CFG_NAND_HW_ECC +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define NAND_MAX_CHIPS 1 +#define CFG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ +/*=====================*/ +/* Board related stuff */ +/*=====================*/ +/*==========================================*/ +/* I2C switch definitions for PCA9543 chip */ +/* on Lyrtech SFF SDR board. */ +/* This chip has a single register. */ +/*==========================================*/ +#define CFG_I2C_PCA9543_ADDR 0x70 +#define CFG_I2C_PCA9543_ADDR_LEN 0 +#define CFG_I2C_PCA9543_ENABLE_CH0 0x01 /* Enable channel 0. */ +/*==============================*/ +/* U-Boot general configuration */ +/*==============================*/ +#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */ +#define CONFIG_MISC_INIT_R +#undef CONFIG_BOOTDELAY +#define CONFIG_BOOTFILE "uImage" /* Boot file name */ +#define CFG_PROMPT "U-Boot > " /* Monitor Command Prompt */ +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +/* Print buffer size */ +#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_LOAD_ADDR 0x80700000 /* Default Linux kernel + * load address. */ +#define CONFIG_VERSION_VARIABLE +#define CONFIG_AUTO_COMPLETE /* Won't work with hush so far, + * may be later */ +#define CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#define CONFIG_CMDLINE_EDITING +#define CFG_LONGHELP +#define CONFIG_CRC32_VERIFY +#define CONFIG_MX_CYCLIC +/* + * Define this to load an Integrity kernel. + * +#define CONFIG_CMD_ELF + */ + +/*===================*/ +/* Linux Information */ +/*===================*/ +#define LINUX_BOOT_PARAM_ADDR 0x80000100 +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_BOOTARGS \ + "mem=56M console=ttyS0,115200n8 root=/dev/hda1 rw noinitrd ip=dhcp" +#define CONFIG_BOOTCOMMAND "setenv setboot setenv bootargs \\$(bootargs) video=dm64xxfb:output=\\$(videostd);run setboot" + +/*=================*/ +/* U-Boot commands */ +/*=================*/ +#include +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DIAG +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_SAVES +#define CONFIG_CMD_NAND +#define CONFIG_CMD_EEPROM +#undef CONFIG_CMD_BDI +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_SETGETDCR +#undef CONFIG_CMD_FLASH +#undef CONFIG_CMD_IMLS +/*=======================*/ +/* KGDB support (if any) */ +/*=======================*/ +#ifdef CONFIG_CMD_KGDB +#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ +#endif +#endif /* __CONFIG_H */ -- cgit From e093a247628228100f405b6d7f6b1bfc16141938 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Sat, 28 Jun 2008 23:34:37 +0200 Subject: Coding Style Cleanup Signed-off-by: Wolfgang Denk --- include/configs/MVBLM7.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include/configs') diff --git a/include/configs/MVBLM7.h b/include/configs/MVBLM7.h index 349ca14bba..0b238bdb85 100644 --- a/include/configs/MVBLM7.h +++ b/include/configs/MVBLM7.h @@ -262,7 +262,7 @@ #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR+CFG_ENV_SIZE) #define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE -#define CONFIG_LOADS_ECHO +#define CONFIG_LOADS_ECHO #define CFG_LOADS_BAUD_CHANGE /* -- cgit From f8cc312bbee69257d741dc9f4062f4a0f5adf609 Mon Sep 17 00:00:00 2001 From: Ben Warren Date: Sun, 8 Jun 2008 23:28:33 -0700 Subject: Move conditional compilation of MPC8XXX SPI driver to Makefile Signed-off-by: Ben Warren --- include/configs/MPC8349EMDS.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include/configs') diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 37e3ca40b3..870583845d 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -355,7 +355,6 @@ /* SPI */ #define CONFIG_MPC8XXX_SPI -#define CONFIG_HARD_SPI /* SPI with hardware support */ #undef CONFIG_SOFT_SPI /* SPI bit-banged */ /* GPIOs. Used as SPI chip selects */ -- cgit From ced209c50e80c25f13c083099b05044048d21f4f Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Thu, 3 Jul 2008 22:39:21 +0200 Subject: sacsng board: fix warnings "suggest explicit braces to avoid ambiguous 'else'" Signed-off-by: Wolfgang Denk --- include/configs/sacsng.h | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) (limited to 'include/configs') diff --git a/include/configs/sacsng.h b/include/configs/sacsng.h index 4974fb43f7..2a398e8c45 100644 --- a/include/configs/sacsng.h +++ b/include/configs/sacsng.h @@ -272,10 +272,14 @@ #undef SPI_INIT /* no port initialization needed */ #define SPI_READ ((immr->im_ioport.iop_pdatd & I2C_MISO) != 0) -#define SPI_SDA(bit) if(bit) immr->im_ioport.iop_pdatd |= I2C_MOSI; \ - else immr->im_ioport.iop_pdatd &= ~I2C_MOSI -#define SPI_SCL(bit) if(bit) immr->im_ioport.iop_pdatd |= I2C_SCLK; \ - else immr->im_ioport.iop_pdatd &= ~I2C_SCLK +#define SPI_SDA(bit) do { \ + if(bit) immr->im_ioport.iop_pdatd |= I2C_MOSI; \ + else immr->im_ioport.iop_pdatd &= ~I2C_MOSI; \ + } while (0) +#define SPI_SCL(bit) do { \ + if(bit) immr->im_ioport.iop_pdatd |= I2C_SCLK; \ + else immr->im_ioport.iop_pdatd &= ~I2C_SCLK; \ + } while (0) #define SPI_DELAY /* No delay is needed */ #endif /* CONFIG_SOFT_SPI */ -- cgit From f16ed51702cb9fb6fa2e019bbc0fcd1466b57c3b Mon Sep 17 00:00:00 2001 From: Andre Schwarz Date: Wed, 2 Jul 2008 18:54:08 +0200 Subject: update mvBL-M7 board config update mvBL-M7 config file to use UBOOT_VERSION. Signed-off-by: Andre Schwarz Signed-off-by: Kim Phillips --- include/configs/MVBLM7.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'include/configs') diff --git a/include/configs/MVBLM7.h b/include/configs/MVBLM7.h index 021b72dc2b..50e188f88f 100644 --- a/include/configs/MVBLM7.h +++ b/include/configs/MVBLM7.h @@ -27,7 +27,7 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define MV_VERSION "v1.0.1" +#include /* * High Level Configuration Options @@ -447,7 +447,7 @@ "mv_dtb_addr=" MV_DTB_ADDR "\0" \ "mv_dtb_addr_ram=" MV_DTB_ADDR_RAM "\0" \ "dtb_name=" MV_DTB_NAME "\0" \ - "mv_version=" MV_VERSION "\0" \ + "mv_version=" U_BOOT_VERSION "\0" \ "dhcp_client_id=" MV_CI "\0" \ "dhcp_vendor-class-identifier=" MV_VCI "\0" \ "netretry=no\0" \ -- cgit From 9fea65a6c469b1b474b27446feb58738baba2d31 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 24 Jun 2008 09:54:09 +0200 Subject: ppc4xx: Rename CONFIG_XILINX_ML300 to CONFIG_XILINX_405 This change helps with better handling with others Xilinx based platform. Signed-off-by: Michal Simek Acked-by: Stefan Roese --- include/configs/ml300.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/configs') diff --git a/include/configs/ml300.h b/include/configs/ml300.h index 1945918300..319923ad6e 100644 --- a/include/configs/ml300.h +++ b/include/configs/ml300.h @@ -54,6 +54,7 @@ #define CONFIG_405 1 /* This is a PPC405 CPU */ #define CONFIG_4xx 1 /* ...member of PPC4xx family */ +#define CONFIG_XILINX_405 1 #define CONFIG_XILINX_ML300 1 /* ...on a Xilinx ML300 board */ #define CONFIG_SYSTEMACE 1 -- cgit From f9599eca7cb5ebe40e5305c8006dced6ecc5cd9e Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Tue, 17 Jun 2008 16:27:52 +0900 Subject: sh: Update Hitachi MS7722SE board Remove network setting from config file. Signed-off-by: Nobuhiro Iwamatsu Signed-off-by: Nobuhiro Iwamatsu --- include/configs/ms7722se.h | 4 ---- 1 file changed, 4 deletions(-) (limited to 'include/configs') diff --git a/include/configs/ms7722se.h b/include/configs/ms7722se.h index 8d92a13e1c..7298e55c70 100644 --- a/include/configs/ms7722se.h +++ b/include/configs/ms7722se.h @@ -40,10 +40,6 @@ #define CONFIG_BAUDRATE 115200 #define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTARGS "console=ttySC0,115200 root=1f01" -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_IPADDR 192.168.0.22 -#define CONFIG_SERVERIP 192.168.0.1 -#define CONFIG_GATEWAYIP 192.168.0.1 #define CONFIG_VERSION_VARIABLE #undef CONFIG_SHOW_BOOT_PROGRESS -- cgit From c001cd604e9f133743effbddb1c215b48e761c5a Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Tue, 17 Jun 2008 16:27:56 +0900 Subject: sh: Update Renesas Migo-R board Remove network setting from config file. Signed-off-by: Nobuhiro Iwamatsu Signed-off-by: Nobuhiro Iwamatsu --- include/configs/MigoR.h | 4 ---- 1 file changed, 4 deletions(-) (limited to 'include/configs') diff --git a/include/configs/MigoR.h b/include/configs/MigoR.h index 99e1179e68..fa0e5db021 100644 --- a/include/configs/MigoR.h +++ b/include/configs/MigoR.h @@ -45,10 +45,6 @@ #define CONFIG_BAUDRATE 115200 #define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTARGS "console=ttySC0,115200 root=1f01" -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_IPADDR 192.168.10.100 -#define CONFIG_SERVERIP 192.168.10.77 -#define CONFIG_GATEWAYIP 192.168.10.77 #define CONFIG_VERSION_VARIABLE #undef CONFIG_SHOW_BOOT_PROGRESS -- cgit From ec39d479d2003f15e86e23ebc4e02a1c9a3a181c Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Tue, 17 Jun 2008 16:28:01 +0900 Subject: sh: Update Renesas R7780MP board New NOR Flash board support and remove network setting from config file. Signed-off-by: Nobuhiro Iwamatsu Signed-off-by: Nobuhiro Iwamatsu --- include/configs/r7780mp.h | 41 +++++++++++++++++++++++------------------ 1 file changed, 23 insertions(+), 18 deletions(-) (limited to 'include/configs') diff --git a/include/configs/r7780mp.h b/include/configs/r7780mp.h index 4e895806ae..4c82c5a2fd 100644 --- a/include/configs/r7780mp.h +++ b/include/configs/r7780mp.h @@ -1,7 +1,7 @@ /* * Configuation settings for the Renesas R7780MP board * - * Copyright (C) 2007 Nobuhiro Iwamatsu + * Copyright (C) 2007,2008 Nobuhiro Iwamatsu * Copyright (C) 2008 Yusuke Goda * * See file CREDITS for list of people who contributed to this @@ -31,7 +31,8 @@ #define CONFIG_SH4A 1 #define CONFIG_CPU_SH7780 1 #define CONFIG_R7780MP 1 -#define __LITTLE_ENDIAN 1 +#define CFG_R7780MP_OLD_FLASH 1 +#define __LITTLE_ENDIAN__ 1 /* * Command line configuration. @@ -59,12 +60,6 @@ /* check for keypress on bootdelay==0 */ /*#define CONFIG_ZERO_BOOTDELAY_CHECK*/ -/* Network setting */ -#define CONFIG_NETMASK 255.0.0.0 -#define CONFIG_IPADDR 10.0.192.82 -#define CONFIG_SERVERIP 10.0.0.1 -#define CONFIG_GATEWAYIP 10.0.0.1 - #define CFG_SDRAM_BASE (0x08000000) #define CFG_SDRAM_SIZE (128 * 1024 * 1024) @@ -80,22 +75,30 @@ #define CFG_MEMTEST_START (CFG_SDRAM_BASE) #define CFG_MEMTEST_END (TEXT_BASE - 0x100000) -/* NOR Flash (S29PL127J60TFI130) */ +/* Flash board support */ #define CFG_FLASH_BASE (0xA0000000) -#define CFG_FLASH_CFI_WIDTH FLASH_CFI_32BIT -#define CFG_MAX_FLASH_BANKS (2) -#define CFG_MAX_FLASH_SECT 270 -#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE,\ +#ifdef CFG_R7780MP_OLD_FLASH +/* NOR Flash (S29PL127J60TFI130) */ +# define CFG_FLASH_CFI_WIDTH FLASH_CFI_32BIT +# define CFG_MAX_FLASH_BANKS (2) +# define CFG_MAX_FLASH_SECT 270 +# define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE,\ CFG_FLASH_BASE + 0x100000,\ CFG_FLASH_BASE + 0x400000,\ CFG_FLASH_BASE + 0x700000, } +#else /* CFG_R7780MP_OLD_FLASH */ +/* NOR Flash (Spantion S29GL256P) */ +# define CFG_MAX_FLASH_BANKS (1) +# define CFG_MAX_FLASH_SECT 256 +# define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } +#endif /* CFG_R7780MP_OLD_FLASH */ #define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 4 * 1024 * 1024) /* Address of u-boot image in Flash */ #define CFG_MONITOR_BASE (CFG_FLASH_BASE) -#define CFG_MONITOR_LEN (112 * 1024) +#define CFG_MONITOR_LEN (256 * 1024) /* Size of DRAM reserved for malloc() use */ -#define CFG_MALLOC_LEN (256 * 1024) +#define CFG_MALLOC_LEN (1204 * 1024) /* size in bytes reserved for initial data */ #define CFG_GBL_DATA_SIZE (256) @@ -110,7 +113,7 @@ #define CFG_FLASH_EMPTY_INFO #define CFG_ENV_IS_IN_FLASH -#define CFG_ENV_SECT_SIZE (16 * 1024) +#define CFG_ENV_SECT_SIZE (256 * 1024) #define CFG_ENV_SIZE (CFG_ENV_SECT_SIZE) #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) #define CFG_FLASH_ERASE_TOUT 120000 @@ -141,8 +144,10 @@ #endif /* CONFIG_CMD_PCI */ #if defined(CONFIG_CMD_NET) -/* #define CONFIG_NET_MULTI - #define CONFIG_RTL8169 */ +/* +#define CONFIG_NET_MULTI +#define CONFIG_RTL8169 +*/ /* AX88696L Support(NE2000 base chip) */ #define CONFIG_DRIVER_NE2000 #define CONFIG_DRIVER_AX88796L -- cgit From 873d97aabc0b1c8822ed1d87e8c5c8ae0a7e4ae9 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Tue, 17 Jun 2008 16:28:05 +0900 Subject: sh: Update Renesas R2DPlus board New NOR Flash board support and remove old type flash board config. And Remove network setting from config file. Signed-off-by: Nobuhiro Iwamatsu Signed-off-by: Nobuhiro Iwamatsu --- include/configs/r2dplus.h | 42 +++++++++--------------------------------- 1 file changed, 9 insertions(+), 33 deletions(-) (limited to 'include/configs') diff --git a/include/configs/r2dplus.h b/include/configs/r2dplus.h index c20bacad22..e269336e82 100644 --- a/include/configs/r2dplus.h +++ b/include/configs/r2dplus.h @@ -35,12 +35,6 @@ #define CONFIG_BOOTARGS "console=ttySC0,115200" #define CONFIG_ENV_OVERWRITE 1 -/* Network setting */ -#define CONFIG_NETMASK 255.0.0.0 -#define CONFIG_IPADDR 10.0.192.51 -#define CONFIG_SERVERIP 10.0.0.1 -#define CONFIG_GATEWAYIP 10.0.0.1 - /* SDRAM */ #define CFG_SDRAM_BASE (0x8C000000) #define CFG_SDRAM_SIZE (0x04000000) @@ -60,45 +54,27 @@ #define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 32 * 1024 * 1024) /* Address of u-boot image in Flash */ #define CFG_MONITOR_BASE (CFG_FLASH_BASE) -#define CFG_MONITOR_LEN (128 * 1024) +#define CFG_MONITOR_LEN (256 * 1024) /* Size of DRAM reserved for malloc() use */ -#define CFG_MALLOC_LEN (256 * 1024) +#define CFG_MALLOC_LEN (1024 * 1024) /* size in bytes reserved for initial data */ #define CFG_GBL_DATA_SIZE (256) #define CFG_BOOTMAPSZ (8 * 1024 * 1024) /* - * NOR Flash + * NOR Flash ( Spantion S29GL256P ) */ #define CFG_FLASH_CFI #define CFG_FLASH_CFI_DRIVER - -#if defined(CONFIG_R2DPLUS_OLD) -#define CFG_FLASH_BASE (0xA0000000) -#define CFG_MAX_FLASH_BANKS (1) /* Max number of - * Flash memory banks - */ -#define CFG_MAX_FLASH_SECT 142 -#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } - -#else /* CONFIG_R2DPLUS_OLD */ - #define CFG_FLASH_BASE (0xA0000000) -#define CFG_FLASH_CFI_WIDTH 0x04 /* 32bit */ -#define CFG_MAX_FLASH_BANKS (2) -#define CFG_MAX_FLASH_SECT 270 -#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE,\ - CFG_FLASH_BASE + 0x100000,\ - CFG_FLASH_BASE + 0x400000,\ - CFG_FLASH_BASE + 0x700000, } -#endif /* CONFIG_R2DPLUS_OLD */ +#define CFG_MAX_FLASH_BANKS (1) +#define CFG_MAX_FLASH_SECT 256 +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } #define CFG_ENV_IS_IN_FLASH -#define CFG_ENV_SECT_SIZE 0x20000 -#define CFG_ENV_SIZE (CFG_ENV_SECT_SIZE) -#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) -#define CFG_FLASH_ERASE_TOUT 120000 -#define CFG_FLASH_WRITE_TOUT 500 +#define CFG_ENV_SECT_SIZE 0x40000 +#define CFG_ENV_SIZE (CFG_ENV_SECT_SIZE) +#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) /* * SuperH Clock setting -- cgit From 689c1b30caacba3fbca0b1813facb3ab70b6cd63 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Mon, 7 Jul 2008 11:22:37 +0900 Subject: sh: Fix compile error sh7763rdp board Disable SH ether driver. Signed-off-by: Nobuhiro Iwamatsu --- include/configs/sh7763rdp.h | 10 ---------- 1 file changed, 10 deletions(-) (limited to 'include/configs') diff --git a/include/configs/sh7763rdp.h b/include/configs/sh7763rdp.h index d537071a07..7713eaaf59 100644 --- a/include/configs/sh7763rdp.h +++ b/include/configs/sh7763rdp.h @@ -38,11 +38,7 @@ #define CONFIG_CMD_SDRAM #define CONFIG_CMD_FLASH #define CONFIG_CMD_MEMORY -#define CONFIG_CMD_NET -#define CONFIG_CMD_PING #define CONFIG_CMD_ENV -#define CONFIG_CMD_NFS -#define CONFIG_CMD_JFFS2 #define CONFIG_BOOTDELAY -1 #define CONFIG_BOOTARGS "console=ttySC2,115200 root=1f01" @@ -66,12 +62,6 @@ #define CFG_BAUDRATE_TABLE { 115200 } /* List of legal baudrate settings for this board */ -/* Ethernet */ -#define CONFIG_SH_ETHER 1 -#define CONFIG_SH_ETHER_USE_PORT (1) -#define CONFIG_SH_ETHER_PHY_ADDR (0x01) -#define CFG_RX_ETH_BUFFER (8) - /* SDRAM */ #define CFG_SDRAM_BASE (0x8C000000) #define CFG_SDRAM_SIZE (64 * 1024 * 1024) -- cgit From 0e6989b9faf1588e8723535539e88a0df3c71356 Mon Sep 17 00:00:00 2001 From: Matvejchikov Ilya Date: Sun, 6 Jul 2008 13:57:00 +0400 Subject: FDT memory and pci node fixes for MPC8260ADS Signed-off-by: Matvejchikov Ilya --- include/configs/MPC8260ADS.h | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'include/configs') diff --git a/include/configs/MPC8260ADS.h b/include/configs/MPC8260ADS.h index 23508f9f5a..59d0bdbeb2 100644 --- a/include/configs/MPC8260ADS.h +++ b/include/configs/MPC8260ADS.h @@ -197,6 +197,13 @@ #define CONFIG_BAUDRATE 115200 +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 +#if defined(CONFIG_OF_LIBFDT) +#define OF_CPU "cpu@0" +#define OF_TBCLK (bd->bi_busfreq / 4) +#endif + /* * BOOTP options */ -- cgit From d2d54ea449639f3d1a6007e333ab9fcc609a18f0 Mon Sep 17 00:00:00 2001 From: Haavard Skinnemoen Date: Thu, 12 Jun 2008 19:27:57 +0200 Subject: avr32: Use CONFIG_ATMEL_MCI to select the atmel_mci driver After we move the atmel_mci driver into drivers/mmc, we can't select it with CONFIG_MMC anymore. Introduce a new symbol specifically for this driver so that there's no ambiguity. Signed-off-by: Haavard Skinnemoen Acked-by: Jean-Chritophe PLAGNIOL-VILLARD --- include/configs/atngw100.h | 1 + include/configs/atstk1002.h | 1 + include/configs/atstk1003.h | 1 + include/configs/atstk1004.h | 1 + include/configs/atstk1006.h | 1 + 5 files changed, 5 insertions(+) (limited to 'include/configs') diff --git a/include/configs/atngw100.h b/include/configs/atngw100.h index 7ac51b543c..84d235ea9d 100644 --- a/include/configs/atngw100.h +++ b/include/configs/atngw100.h @@ -128,6 +128,7 @@ #define CFG_NR_PIOS 5 #define CFG_HSDRAMC 1 #define CONFIG_MMC 1 +#define CONFIG_ATMEL_MCI 1 #define CONFIG_ATMEL_SPI 1 #define CONFIG_SPI_FLASH 1 diff --git a/include/configs/atstk1002.h b/include/configs/atstk1002.h index ba18eb63c7..90910bb98a 100644 --- a/include/configs/atstk1002.h +++ b/include/configs/atstk1002.h @@ -153,6 +153,7 @@ #define CFG_NR_PIOS 5 #define CFG_HSDRAMC 1 #define CONFIG_MMC 1 +#define CONFIG_ATMEL_MCI 1 #define CFG_DCACHE_LINESZ 32 #define CFG_ICACHE_LINESZ 32 diff --git a/include/configs/atstk1003.h b/include/configs/atstk1003.h index a528ddfb0e..03472a8869 100644 --- a/include/configs/atstk1003.h +++ b/include/configs/atstk1003.h @@ -136,6 +136,7 @@ #define CONFIG_PIO2 1 #define CFG_HSDRAMC 1 #define CONFIG_MMC 1 +#define CONFIG_ATMEL_MCI 1 #define CFG_DCACHE_LINESZ 32 #define CFG_ICACHE_LINESZ 32 diff --git a/include/configs/atstk1004.h b/include/configs/atstk1004.h index fc9585e84d..07add821a9 100644 --- a/include/configs/atstk1004.h +++ b/include/configs/atstk1004.h @@ -136,6 +136,7 @@ #define CONFIG_PIO2 1 #define CFG_HSDRAMC 1 #define CONFIG_MMC 1 +#define CONFIG_ATMEL_MCI 1 #define CFG_DCACHE_LINESZ 32 #define CFG_ICACHE_LINESZ 32 diff --git a/include/configs/atstk1006.h b/include/configs/atstk1006.h index 9fd49a53a3..f9af67540a 100644 --- a/include/configs/atstk1006.h +++ b/include/configs/atstk1006.h @@ -153,6 +153,7 @@ #define CFG_NR_PIOS 5 #define CFG_HSDRAMC 1 #define CONFIG_MMC 1 +#define CONFIG_ATMEL_MCI 1 #define CFG_DCACHE_LINESZ 32 #define CFG_ICACHE_LINESZ 32 -- cgit From 2b1fa9d383cbbb7d347c1583bd6ca4e181ba8e9e Mon Sep 17 00:00:00 2001 From: Hugo Villeneuve Date: Tue, 8 Jul 2008 11:02:05 -0400 Subject: ARM: Fix for wrong patch version applied for Lyrtech SFF-SDR board (ARM926EJS) ARM: Fix for incorrect version of patch applied when adding support for the Lyrtech SFF-SDR board. Signed-off-by: Hugo Villeneuve Signed-off-by: Philip Balister, OpenSDR --- include/configs/davinci_sffsdr.h | 69 ++++++++++++---------------------------- 1 file changed, 21 insertions(+), 48 deletions(-) (limited to 'include/configs') diff --git a/include/configs/davinci_sffsdr.h b/include/configs/davinci_sffsdr.h index 41a6763e8f..0e49e6c159 100644 --- a/include/configs/davinci_sffsdr.h +++ b/include/configs/davinci_sffsdr.h @@ -1,6 +1,9 @@ /* * Copyright (C) 2007 Sergey Kubushyn * + * Copyright (C) 2008 Lyrtech + * Copyright (C) 2008 Philip Balister, OpenSDR + * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of @@ -21,30 +24,24 @@ #define __CONFIG_H #include -/*=======*/ /* Board */ -/*=======*/ #define SFFSDR #define CFG_NAND_LARGEPAGE #define CFG_USE_NAND -/*===================*/ +#define CFG_USE_DSPLINK /* This is to prevent U-Boot from + * powering ON the DSP. */ /* SoC Configuration */ -/*===================*/ #define CONFIG_ARM926EJS /* arm926ejs CPU core */ #define CONFIG_SYS_CLK_FREQ 297000000 /* Arm Clock frequency */ #define CFG_TIMERBASE 0x01c21400 /* use timer 0 */ #define CFG_HZ_CLOCK 27000000 /* Timer Input clock freq */ #define CFG_HZ 1000 -/*==================================================*/ -/* EEPROM definitions for Atmel 24LC64 EEPROM chip */ -/*==================================================*/ +/* EEPROM definitions for Atmel 24LC64 EEPROM chip */ #define CFG_I2C_EEPROM_ADDR_LEN 2 #define CFG_I2C_EEPROM_ADDR 0x50 #define CFG_EEPROM_PAGE_WRITE_BITS 5 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20 -/*=============*/ /* Memory Info */ -/*=============*/ #define CFG_MALLOC_LEN (0x10000 + 256*1024) /* malloc() len */ #define CFG_GBL_DATA_SIZE 128 /* reserved for initial data */ #define CFG_MEMTEST_START 0x80000000 /* memtest start address */ @@ -54,9 +51,7 @@ #define PHYS_SDRAM_1 0x80000000 /* DDR Start */ #define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */ #define DDR_4BANKS /* 4-bank DDR2 (128MB) */ -/*====================*/ /* Serial Driver info */ -/*====================*/ #define CFG_NS16550 #define CFG_NS16550_SERIAL #define CFG_NS16550_REG_SIZE 4 /* NS16550 register size */ @@ -65,16 +60,12 @@ #define CONFIG_CONS_INDEX 1 /* use UART0 for console */ #define CONFIG_BAUDRATE 115200 /* Default baud rate */ #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } -/*===================*/ /* I2C Configuration */ -/*===================*/ #define CONFIG_HARD_I2C #define CONFIG_DRIVER_DAVINCI_I2C #define CFG_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */ #define CFG_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ -/*==================================*/ /* Network & Ethernet Configuration */ -/*==================================*/ #define CONFIG_DRIVER_TI_EMAC #define CONFIG_MII #define CONFIG_BOOTP_DEFAULT @@ -83,9 +74,7 @@ #define CONFIG_BOOTP_SEND_HOSTNAME #define CONFIG_NET_RETRY_COUNT 10 #define CONFIG_OVERWRITE_ETHADDR_ONCE -/*=====================*/ /* Flash & Environment */ -/*=====================*/ #undef CFG_ENV_IS_IN_FLASH #define CFG_NO_FLASH #define CFG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */ @@ -98,28 +87,19 @@ #define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ #define NAND_MAX_CHIPS 1 #define CFG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ -/*=====================*/ -/* Board related stuff */ -/*=====================*/ -/*==========================================*/ -/* I2C switch definitions for PCA9543 chip */ -/* on Lyrtech SFF SDR board. */ -/* This chip has a single register. */ -/*==========================================*/ +/* I2C switch definitions for PCA9543 chip */ #define CFG_I2C_PCA9543_ADDR 0x70 -#define CFG_I2C_PCA9543_ADDR_LEN 0 +#define CFG_I2C_PCA9543_ADDR_LEN 0 /* Single register. */ #define CFG_I2C_PCA9543_ENABLE_CH0 0x01 /* Enable channel 0. */ -/*==============================*/ /* U-Boot general configuration */ -/*==============================*/ -#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */ +#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */ #define CONFIG_MISC_INIT_R -#undef CONFIG_BOOTDELAY +#define CONFIG_BOOTDELAY 5 /* Autoboot after 5 seconds. */ #define CONFIG_BOOTFILE "uImage" /* Boot file name */ #define CFG_PROMPT "U-Boot > " /* Monitor Command Prompt */ #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -/* Print buffer size */ -#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) +#define CFG_PBSIZE \ + (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print buffer size */ #define CFG_MAXARGS 16 /* max number of command args */ #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ #define CFG_LOAD_ADDR 0x80700000 /* Default Linux kernel @@ -133,25 +113,20 @@ #define CFG_LONGHELP #define CONFIG_CRC32_VERIFY #define CONFIG_MX_CYCLIC -/* - * Define this to load an Integrity kernel. - * -#define CONFIG_CMD_ELF - */ - -/*===================*/ /* Linux Information */ -/*===================*/ #define LINUX_BOOT_PARAM_ADDR 0x80000100 #define CONFIG_CMDLINE_TAG #define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_BOOTARGS \ - "mem=56M console=ttyS0,115200n8 root=/dev/hda1 rw noinitrd ip=dhcp" -#define CONFIG_BOOTCOMMAND "setenv setboot setenv bootargs \\$(bootargs) video=dm64xxfb:output=\\$(videostd);run setboot" - -/*=================*/ +#define CONFIG_BOOTARGS \ + "mem=56M " \ + "console=ttyS0,115200n8 " \ + "root=/dev/nfs rw noinitrd ip=dhcp " \ + "nfsroot=${serverip}:/nfsroot/sffsdr " \ + "eth0=${ethaddr}" +#define CONFIG_BOOTCOMMAND \ + "nand read 87A00000 100000 300000;" \ + "bootelf 87A00000" /* U-Boot commands */ -/*=================*/ #include #define CONFIG_CMD_ASKENV #define CONFIG_CMD_DHCP @@ -167,9 +142,7 @@ #undef CONFIG_CMD_SETGETDCR #undef CONFIG_CMD_FLASH #undef CONFIG_CMD_IMLS -/*=======================*/ /* KGDB support (if any) */ -/*=======================*/ #ifdef CONFIG_CMD_KGDB #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ -- cgit