From 1d47273d46925929f8f2c1913cd96d7257aade88 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 18 Dec 2007 23:21:51 -0600 Subject: Use FSL Book-E MMU macros from Linux Kernel Grab the FSL Book-E MAS register macros from Linux. Also added defines for page sizes up to 4TB and removed SHAREN since it doesnt really exist. Signed-off-by: Kumar Gala --- include/e500.h | 12 +++--------- 1 file changed, 3 insertions(+), 9 deletions(-) (limited to 'include/e500.h') diff --git a/include/e500.h b/include/e500.h index 0d73260f40..983826d32c 100644 --- a/include/e500.h +++ b/include/e500.h @@ -50,10 +50,7 @@ typedef struct * nv(Next victim):0,1 */ #define TLB1_MAS0(tlbsel,esel,nv) \ - ((((tlbsel) << 28) & MAS0_TLBSEL) |\ - (((esel) << 16) & MAS0_ESEL ) |\ - (nv) ) - + (MAS0_TLBSEL(tlbsel) | MAS0_ESEL(esel) | MAS0_NV(nv)) /* MAS1 * v(TLB valid bit):0,1 @@ -65,10 +62,9 @@ typedef struct #define TLB1_MAS1(v,iprot,tid,ts,tsize) \ ((((v) << 31) & MAS1_VALID) |\ (((iprot) << 30) & MAS1_IPROT) |\ - (((tid) << 16) & MAS1_TID) |\ + (MAS1_TID(tid)) |\ (((ts) << 12) & MAS1_TS) |\ - (((tsize) << 8) & MAS1_TSIZE) ) - + (MAS1_TSIZE(tsize))) /* MAS2 * epn(effective page number):20bits @@ -79,7 +75,6 @@ typedef struct */ #define TLB1_MAS2(epn,sharen,x0,x1,w,i,m,g,e) \ ((((epn) << 12) & MAS2_EPN) |\ - (((sharen) << 9) & MAS2_SHAREN) |\ (((x0) << 6) & MAS2_X0) |\ (((x1) << 5) & MAS2_X1) |\ (((w) << 4) & MAS2_W) |\ @@ -88,7 +83,6 @@ typedef struct (((g) << 1) & MAS2_G) |\ (e) ) - /* MAS3 * rpn(real page number):20bits * u0-u3(user bits, useful for page table management in OS):0,1 -- cgit From 2146cf56821c3364786ca94a7306008c5824b238 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 19 Dec 2007 01:18:15 -0600 Subject: Reworked FSL Book-E TLB macros to be more readable The old macros made it difficult to know what WIMGE and perm bits were set for a TLB entry. Actually use the bit masks for these items since they are only a single bit. Also moved the macros into mmu.h out of e500.h since they aren't specific to e500. Signed-off-by: Kumar Gala --- include/e500.h | 88 ---------------------------------------------------------- 1 file changed, 88 deletions(-) (limited to 'include/e500.h') diff --git a/include/e500.h b/include/e500.h index 983826d32c..1971eee291 100644 --- a/include/e500.h +++ b/include/e500.h @@ -17,94 +17,6 @@ typedef struct #endif /* _ASMLANGUAGE */ -/* Motorola E500 core provides 16 TLB1 entries; they can be used for - * initial memory mapping like legacy BAT registers do. Usually we - * use four MAS registers(MAS0-3) to operate on TLB1 entries. - * - * While there are 16 Entries with variable Page Sizes in TLB1, - * there are also 256 Entries with fixed 4K pages in TLB0. - * - * We also need LAWs(Local Access Window) to associate a range of - * the local 32-bit address space with a particular target interface - * such as PCI/PCI-X, RapidIO, Local Bus and DDR SDRAM. - * - * We put TLB1/LAW code here because memory mapping is board-specific - * instead of cpu-specific. - * - * While these macros are all nominally for TLB1 by name, they can - * also be used for TLB0 as well. - */ - - -/* - * Convert addresses to Effective and Real Page Numbers. - * Grab the high 20-bits and shift 'em down, dropping the "byte offset". - */ -#define E500_TLB_EPN(addr) (((addr) >> 12) & 0xfffff) -#define E500_TLB_RPN(addr) (((addr) >> 12) & 0xfffff) - - -/* MAS0 - * tlbsel(TLB Select):0,1 - * esel(Entry Select): 0,1,2,...,15 for TLB1 - * nv(Next victim):0,1 - */ -#define TLB1_MAS0(tlbsel,esel,nv) \ - (MAS0_TLBSEL(tlbsel) | MAS0_ESEL(esel) | MAS0_NV(nv)) - -/* MAS1 - * v(TLB valid bit):0,1 - * iprot(invalidate protect):0,1 - * tid(translation identity):8bit to match process IDs - * ts(translation space,comparing with MSR[IS,DS]): 0,1 - * tsize(translation size):1,2,...,9(4K,16K,64K,256K,1M,4M,16M,64M,256M) - */ -#define TLB1_MAS1(v,iprot,tid,ts,tsize) \ - ((((v) << 31) & MAS1_VALID) |\ - (((iprot) << 30) & MAS1_IPROT) |\ - (MAS1_TID(tid)) |\ - (((ts) << 12) & MAS1_TS) |\ - (MAS1_TSIZE(tsize))) - -/* MAS2 - * epn(effective page number):20bits - * sharen(Shared cache state):0,1 - * x0,x1(implementation specific page attribute):0,1 - * w,i,m,g,e(write-through,cache-inhibited,memory coherency,guarded, - * endianness):0,1 - */ -#define TLB1_MAS2(epn,sharen,x0,x1,w,i,m,g,e) \ - ((((epn) << 12) & MAS2_EPN) |\ - (((x0) << 6) & MAS2_X0) |\ - (((x1) << 5) & MAS2_X1) |\ - (((w) << 4) & MAS2_W) |\ - (((i) << 3) & MAS2_I) |\ - (((m) << 2) & MAS2_M) |\ - (((g) << 1) & MAS2_G) |\ - (e) ) - -/* MAS3 - * rpn(real page number):20bits - * u0-u3(user bits, useful for page table management in OS):0,1 - * ux,sx,uw,sw,ur,sr(permission bits, user and supervisor read, - * write,execute permission). - */ -#define TLB1_MAS3(rpn,u0,u1,u2,u3,ux,sx,uw,sw,ur,sr) \ - ((((rpn) << 12) & MAS3_RPN) |\ - (((u0) << 9) & MAS3_U0) |\ - (((u1) << 8) & MAS3_U1) |\ - (((u2) << 7) & MAS3_U2) |\ - (((u3) << 6) & MAS3_U3) |\ - (((ux) << 5) & MAS3_UX) |\ - (((sx) << 4) & MAS3_SX) |\ - (((uw) << 3) & MAS3_UW) |\ - (((sw) << 2) & MAS3_SW) |\ - (((ur) << 1) & MAS3_UR) |\ - (sr) ) - - #define RESET_VECTOR 0xfffffffc -#define CACHELINE_MASK (CFG_CACHELINE_SIZE - 1) /* Address mask for cache - line aligned data. */ #endif /* __E500_H__ */ -- cgit