From d0fe1128c4451327b9cb0fac1a76efd194b078b5 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Wed, 26 May 2010 21:26:43 +0400 Subject: USB: fix create_pipe() create_pipe() can give wrong result if an expression is passed as the 'endpoint' argument -- due to missing parentheses. Thanks to Martin Mueller for finding the bug and providing the patch. Signed-off-by: Sergei Shtylyov --- include/usb.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/usb.h b/include/usb.h index a1f09d4d7a..bc4ccfe150 100644 --- a/include/usb.h +++ b/include/usb.h @@ -259,7 +259,7 @@ int usb_set_interface(struct usb_device *dev, int interface, int alternate); */ /* Create various pipes... */ #define create_pipe(dev,endpoint) \ - (((dev)->devnum << 8) | (endpoint << 15) | \ + (((dev)->devnum << 8) | ((endpoint) << 15) | \ ((dev)->speed << 26) | (dev)->maxpacketsize) #define default_pipe(dev) ((dev)->speed << 26) -- cgit From 1e8e9bad2db38e93c3bc9f4b6238b3d8be99e469 Mon Sep 17 00:00:00 2001 From: Thomas Chou Date: Fri, 30 Apr 2010 11:34:15 +0800 Subject: nios2: add gpio support to nios2-generic board This patch adds gpio support of Altera PIO component to the nios2-generic board. Though it drives only gpio_led at the moment, it supports bidirectional port to control bit-banging I2C, NAND flash busy status or button switches, etc. Signed-off-by: Thomas Chou Tested-by: Ian Abbott Signed-off-by: Scott McNutt --- include/configs/nios2-generic.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/include/configs/nios2-generic.h b/include/configs/nios2-generic.h index e83e1e391e..e4bf57b755 100644 --- a/include/configs/nios2-generic.h +++ b/include/configs/nios2-generic.h @@ -63,10 +63,10 @@ * STATUS LED */ #define CONFIG_STATUS_LED /* Enable status driver */ -#define CONFIG_EPLED /* Enable LED PIO driver */ -#define CONFIG_SYS_LEDPIO_ADDR LED_PIO_BASE +#define CONFIG_GPIO_LED /* Enable GPIO LED driver */ +#define CONFIG_GPIO /* Enable GPIO driver */ -#define STATUS_LED_BIT 1 /* Bit-0 on PIO */ +#define STATUS_LED_BIT 0 /* Bit-0 on GPIO */ #define STATUS_LED_STATE 1 /* Blinking */ #define STATUS_LED_PERIOD (500 / CONFIG_SYS_NIOS_TMRMS) /* 500 msec */ -- cgit From 1117cbf2adac59050af1751af6c6a524afa5c3ef Mon Sep 17 00:00:00 2001 From: Thomas Chou Date: Fri, 28 May 2010 10:56:50 +0800 Subject: nios: remove nios-32 arch The nios-32 arch is obsolete and broken. So it is removed. Signed-off-by: Thomas Chou --- include/configs/ADNPESC1.h | 689 ----------------------------------- include/configs/ADNPESC1_base_32.h | 431 ---------------------- include/configs/DK1C20.h | 555 ---------------------------- include/configs/DK1C20_safe_32.h | 34 -- include/configs/DK1C20_standard_32.h | 279 -------------- include/configs/DK1S10.h | 561 ---------------------------- include/configs/DK1S10_mtx_ldk_20.h | 187 ---------- include/configs/DK1S10_safe_32.h | 34 -- include/configs/DK1S10_standard_32.h | 274 -------------- include/image.h | 5 - include/nios-io.h | 183 ---------- include/nios.h | 77 ---- include/watchdog.h | 4 - 13 files changed, 3313 deletions(-) delete mode 100644 include/configs/ADNPESC1.h delete mode 100644 include/configs/ADNPESC1_base_32.h delete mode 100644 include/configs/DK1C20.h delete mode 100644 include/configs/DK1C20_safe_32.h delete mode 100644 include/configs/DK1C20_standard_32.h delete mode 100644 include/configs/DK1S10.h delete mode 100644 include/configs/DK1S10_mtx_ldk_20.h delete mode 100644 include/configs/DK1S10_safe_32.h delete mode 100644 include/configs/DK1S10_standard_32.h delete mode 100644 include/nios-io.h delete mode 100644 include/nios.h (limited to 'include') diff --git a/include/configs/ADNPESC1.h b/include/configs/ADNPESC1.h deleted file mode 100644 index 2d4fc77915..0000000000 --- a/include/configs/ADNPESC1.h +++ /dev/null @@ -1,689 +0,0 @@ -/* - * (C) Copyright 2004, Li-Pro.Net - * Stephan Linz - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/*********************************************************************** - * Include the whole NIOS CPU configuration. - * - * !!! HAVE TO BE HERE !!! DON'T MOVE THIS PART !!! - * - ***********************************************************************/ - -#if defined(CONFIG_NIOS_BASE_32) -#include -#else -#error *** CONFIG_SYS_ERROR: you have to setup right NIOS CPU configuration -#endif - -/*------------------------------------------------------------------------ - * BOARD/CPU -- TOP-LEVEL - *----------------------------------------------------------------------*/ -#define CONFIG_NIOS 1 /* NIOS-32 core */ -#define CONFIG_ADNPESC1 1 /* SSV ADNP/ESC1 board */ -#define CONFIG_SYS_CLK_FREQ CONFIG_SYS_NIOS_CPU_CLK/* 50 MHz core clock */ -#define CONFIG_SYS_HZ 1000 /* 1 msec time tick */ -#define CONFIG_BOARD_EARLY_INIT_F 1 /* enable early board-spec. init*/ - -/*------------------------------------------------------------------------ - * BASE ADDRESSES / SIZE (Flash, SRAM, SDRAM) - *----------------------------------------------------------------------*/ -#if (CONFIG_SYS_NIOS_CPU_SDRAM_SIZE != 0) - -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_NIOS_CPU_SDRAM_BASE -#define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_NIOS_CPU_SDRAM_SIZE - -#else -#error *** CONFIG_SYS_ERROR: you have to setup any SDRAM in NIOS CPU config -#endif - -#if defined(CONFIG_SYS_NIOS_CPU_SRAM_BASE) && defined(CONFIG_SYS_NIOS_CPU_SRAM_SIZE) - -#define CONFIG_SYS_SRAM_BASE CONFIG_SYS_NIOS_CPU_SRAM_BASE -#define CONFIG_SYS_SRAM_SIZE CONFIG_SYS_NIOS_CPU_SRAM_SIZE - -#else - -#undef CONFIG_SYS_SRAM_BASE -#undef CONFIG_SYS_SRAM_SIZE - -#endif - -#define CONFIG_SYS_VECT_BASE CONFIG_SYS_NIOS_CPU_VEC_BASE - -/*------------------------------------------------------------------------ - * MEMORY ORGANIZATION - For the most part, you can put things pretty - * much anywhere. This is pretty flexible for Nios. So here we make some - * arbitrary choices & assume that the monitor is placed at the end of - * a memory resource (so you must make sure TEXT_BASE is chosen - * appropriately -- this is very important if you plan to move your - * memory to another place as configured at this time !!!). - * - * -The heap is placed below the monitor. - * -Global data is placed below the heap. - * -The stack is placed below global data (&grows down). - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256k */ -#define CONFIG_SYS_GBL_DATA_SIZE 128 /* Global data size rsvd*/ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) - -#define CONFIG_SYS_MONITOR_BASE TEXT_BASE -#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN) -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_MALLOC_BASE - CONFIG_SYS_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP CONFIG_SYS_GBL_DATA_OFFSET - -/*------------------------------------------------------------------------ - * FLASH (AM29LV065D) - *----------------------------------------------------------------------*/ -#if (CONFIG_SYS_NIOS_CPU_FLASH_SIZE != 0) - -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_NIOS_CPU_FLASH_BASE -#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_NIOS_CPU_FLASH_SIZE -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* Max # sects per bank */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max # of flash banks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Erase timeout (msec) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 100 /* Write timeout (msec) */ -#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size */ - -#else -#error *** CONFIG_SYS_ERROR: you have to setup any Flash memory in NIOS CPU config -#endif - -/*------------------------------------------------------------------------ - * ENVIRONMENT - *----------------------------------------------------------------------*/ -#if (CONFIG_SYS_NIOS_CPU_FLASH_SIZE != 0) - -#define CONFIG_ENV_IS_IN_FLASH 1 /* Environment in flash */ - -/* Mem addr of environment */ -#if defined(CONFIG_NIOS_BASE_32) -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) -#else -#error *** CONFIG_SYS_ERROR: you have to setup the environment base address CONFIG_ENV_ADDR -#endif - -#define CONFIG_ENV_SIZE (64 * 1024) /* 64 KByte (1 sector) */ -#define CONFIG_ENV_OVERWRITE /* Serial/eth change Ok */ - -#else -#define CONFIG_ENV_IS_NOWHERE 1 /* NO Environment */ -#endif - -/*------------------------------------------------------------------------ - * NIOS APPLICATION CODE BASE AREA - *----------------------------------------------------------------------*/ -#if ((CONFIG_ENV_ADDR + CONFIG_ENV_SIZE) == 0x1050000) -#define CONFIG_SYS_ADNPESC1_UPDATE_LOAD_ADDR "0x2000100" -#define CONFIG_SYS_ADNPESC1_NIOS_APPL_ENTRY "0x1050000" -#define CONFIG_SYS_ADNPESC1_NIOS_APPL_IDENT "0x105000c" -#define CONFIG_SYS_ADNPESC1_NIOS_APPL_END "0x11fffff" -#define CONFIG_SYS_ADNPESC1_FILESYSTEM_BASE "0x1200000" -#define CONFIG_SYS_ADNPESC1_FILESYSTEM_END "0x17fffff" -#else -#error *** CONFIG_SYS_ERROR: missing right appl.code base configuration, expand your config.h -#endif -#define CONFIG_SYS_ADNPESC1_NIOS_IDENTIFIER "Nios" - -/*------------------------------------------------------------------------ - * BOOT ENVIRONMENT - *----------------------------------------------------------------------*/ -#ifdef CONFIG_DNPEVA2 /* DNP/EVA2 base board */ -#define CONFIG_SYS_ADNPESC1_SLED_BOOT_OFF "sled boot off; " -#define CONFIG_SYS_ADNPESC1_SLED_RED_BLINK "sled red blink; " -#else -#define CONFIG_SYS_ADNPESC1_SLED_BOOT_OFF -#define CONFIG_SYS_ADNPESC1_SLED_RED_BLINK -#endif - -#define CONFIG_BOOTDELAY 5 -#define CONFIG_BOOTCOMMAND \ - "if itest.s *$appl_ident_addr == \"$appl_ident_str\"; " \ - "then " \ - "wd off; " \ - CONFIG_SYS_ADNPESC1_SLED_BOOT_OFF \ - "go $appl_entry_addr; " \ - "else " \ - CONFIG_SYS_ADNPESC1_SLED_RED_BLINK \ - "echo *** missing \"$appl_ident_str\" at $appl_ident_addr; "\ - "echo *** invalid application at $appl_entry_addr; " \ - "echo *** stop bootup...; " \ - "fi" - -/*------------------------------------------------------------------------ - * EXTRA ENVIRONMENT - *----------------------------------------------------------------------*/ -#ifdef CONFIG_DNPEVA2 /* DNP/EVA2 base board */ -#define CONFIG_SYS_ADNPESC1_SLED_YELLO_ON "sled yellow on; " -#define CONFIG_SYS_ADNPESC1_SLED_YELLO_OFF "sled yellow off; " -#else -#define CONFIG_SYS_ADNPESC1_SLED_YELLO_ON -#define CONFIG_SYS_ADNPESC1_SLED_YELLO_OFF -#endif - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "update_allowed=0\0" \ - "update_load_addr=" CONFIG_SYS_ADNPESC1_UPDATE_LOAD_ADDR "\0" \ - "appl_entry_addr=" CONFIG_SYS_ADNPESC1_NIOS_APPL_ENTRY "\0" \ - "appl_end_addr=" CONFIG_SYS_ADNPESC1_NIOS_APPL_END "\0" \ - "appl_ident_addr=" CONFIG_SYS_ADNPESC1_NIOS_APPL_IDENT "\0" \ - "appl_ident_str=" CONFIG_SYS_ADNPESC1_NIOS_IDENTIFIER "\0" \ - "appl_name=ADNPESC1/base32/linux.bin\0" \ - "appl_update=" \ - "if itest.b $update_allowed != 0; " \ - "then " \ - CONFIG_SYS_ADNPESC1_SLED_YELLO_ON \ - "tftp $update_load_addr $appl_name; " \ - "protect off $appl_entry_addr $appl_end_addr; " \ - "era $appl_entry_addr $appl_end_addr; " \ - "cp.b $update_load_addr $appl_entry_addr $filesize; "\ - CONFIG_SYS_ADNPESC1_SLED_YELLO_OFF \ - "else " \ - "echo *** update not allowed (update_allowed=$update_allowed); "\ - "fi\0" \ - "fs_base_addr=" CONFIG_SYS_ADNPESC1_FILESYSTEM_BASE "\0" \ - "fs_end_addr=" CONFIG_SYS_ADNPESC1_FILESYSTEM_END "\0" \ - "fs_name=ADNPESC1/base32/romfs.img\0" \ - "fs_update=" \ - "if itest.b $update_allowed != 0; " \ - "then " \ - CONFIG_SYS_ADNPESC1_SLED_YELLO_ON \ - "tftp $update_load_addr $fs_name; " \ - "protect off $fs_base_addr $fs_end_addr; " \ - "era $fs_base_addr $fs_end_addr; " \ - "cp.b $update_load_addr $fs_base_addr $filesize; "\ - CONFIG_SYS_ADNPESC1_SLED_YELLO_OFF \ - "else " \ - "echo *** update not allowed (update_allowed=$update_allowed); "\ - "fi\0" \ - "uboot_name=ADNPESC1/base32/u-boot.bin\0" \ - "uboot_loadnrun=" \ - "if ping $serverip; " \ - "then " \ - CONFIG_SYS_ADNPESC1_SLED_YELLO_ON \ - "tftp $update_load_addr $uboot_name; " \ - "wd off; " \ - "go $update_load_addr; " \ - "else " \ - "echo *** missing connection to $serverip; " \ - "echo *** check your network and try again...; "\ - "fi\0" - -/*------------------------------------------------------------------------ - * CONSOLE - *----------------------------------------------------------------------*/ -#if (CONFIG_SYS_NIOS_CPU_UART_NUMS != 0) - -#define CONFIG_SYS_NIOS_CONSOLE CONFIG_SYS_NIOS_CPU_UART0 /* 1st UART is Cons. */ - -#if (CONFIG_SYS_NIOS_CPU_UART0_BR != 0) -#define CONFIG_SYS_NIOS_FIXEDBAUD 1 /* Baudrate is fixed */ -#define CONFIG_BAUDRATE CONFIG_SYS_NIOS_CPU_UART0_BR -#else -#undef CONFIG_SYS_NIOS_FIXEDBAUD -#define CONFIG_BAUDRATE 115200 -#endif - -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -#else -#error *** CONFIG_SYS_ERROR: you have to setup at least one UART in NIOS CPU config -#endif - -/*------------------------------------------------------------------------ - * TIMER FOR TIMEBASE -- Nios doesn't have the equivalent of ppc PIT, - * so an avalon bus timer is required. - *----------------------------------------------------------------------*/ -#if (CONFIG_SYS_NIOS_CPU_TIMER_NUMS != 0) && defined(CONFIG_SYS_NIOS_CPU_TICK_TIMER) - -#if (CONFIG_SYS_NIOS_CPU_TICK_TIMER == 0) - -#define CONFIG_SYS_NIOS_TMRBASE CONFIG_SYS_NIOS_CPU_TIMER0 /* TIMER0 as tick */ -#define CONFIG_SYS_NIOS_TMRIRQ CONFIG_SYS_NIOS_CPU_TIMER0_IRQ - -#if (CONFIG_SYS_NIOS_CPU_TIMER0_FP == 1) /* fixed period */ - -#if (CONFIG_SYS_NIOS_CPU_TIMER0_PER >= CONFIG_SYS_HZ) -#define CONFIG_SYS_NIOS_TMRMS (CONFIG_SYS_NIOS_CPU_TIMER0_PER / CONFIG_SYS_HZ) -#else -#error *** CONFIG_SYS_ERROR: you have to use a timer periode greater than CONFIG_SYS_HZ -#endif - -#undef CONFIG_SYS_NIOS_TMRCNT /* no preloadable counter value */ - -#elif (CONFIG_SYS_NIOS_CPU_TIMER0_FP == 0) /* variable period */ - -#if (CONFIG_SYS_HZ <= 1000) -#define CONFIG_SYS_NIOS_TMRMS (1000 / CONFIG_SYS_HZ) -#else -#error *** CONFIG_SYS_ERROR: sorry, CONFIG_SYS_HZ have to be less than 1000 -#endif - -#define CONFIG_SYS_NIOS_TMRCNT (CONFIG_SYS_CLK_FREQ / CONFIG_SYS_HZ) - -#else -#error *** CONFIG_SYS_ERROR: you have to define CONFIG_SYS_NIOS_CPU_TIMER0_FP correct -#endif - -#elif (CONFIG_SYS_NIOS_CPU_TICK_TIMER == 1) - -#define CONFIG_SYS_NIOS_TMRBASE CONFIG_SYS_NIOS_CPU_TIMER1 /* TIMER1 as tick */ -#define CONFIG_SYS_NIOS_TMRIRQ CONFIG_SYS_NIOS_CPU_TIMER1_IRQ - -#if (CONFIG_SYS_NIOS_CPU_TIMER1_FP == 1) /* fixed period */ - -#if (CONFIG_SYS_NIOS_CPU_TIMER1_PER >= CONFIG_SYS_HZ) -#define CONFIG_SYS_NIOS_TMRMS (CONFIG_SYS_NIOS_CPU_TIMER1_PER / CONFIG_SYS_HZ) -#else -#error *** CONFIG_SYS_ERROR: you have to use a timer periode greater than CONFIG_SYS_HZ -#endif - -#undef CONFIG_SYS_NIOS_TMRCNT /* no preloadable counter value */ - -#elif (CONFIG_SYS_NIOS_CPU_TIMER1_FP == 0) /* variable period */ - -#if (CONFIG_SYS_HZ <= 1000) -#define CONFIG_SYS_NIOS_TMRMS (1000 / CONFIG_SYS_HZ) -#else -#error *** CONFIG_SYS_ERROR: sorry, CONFIG_SYS_HZ have to be less than 1000 -#endif - -#define CONFIG_SYS_NIOS_TMRCNT (CONFIG_SYS_CLK_FREQ / CONFIG_SYS_HZ) - -#else -#error *** CONFIG_SYS_ERROR: you have to define CONFIG_SYS_NIOS_CPU_TIMER1_FP correct -#endif - -#endif /* CONFIG_SYS_NIOS_CPU_TICK_TIMER */ - -#else -#error *** CONFIG_SYS_ERROR: you have to setup at least one TIMER in NIOS CPU config -#endif - -/*------------------------------------------------------------------------ - * WATCHDOG (or better MAX823 supervisory circuite access) - *----------------------------------------------------------------------*/ -#define CONFIG_HW_WATCHDOG 1 /* board specific WD */ - -#ifdef CONFIG_HW_WATCHDOG - -/* MAX823 supervisor -- watchdog enable port at: */ -#if (CONFIG_SYS_NIOS_CPU_WDENA_PIO == 0) -#define CONFIG_HW_WDENA_BASE CONFIG_SYS_NIOS_CPU_PIO0 /* PIO0 */ -#elif (CONFIG_SYS_NIOS_CPU_WDENA_PIO == 1) -#define CONFIG_HW_WDENA_BASE CONFIG_SYS_NIOS_CPU_PIO1 /* PIO1 */ -#elif (CONFIG_SYS_NIOS_CPU_WDENA_PIO == 2) -#define CONFIG_HW_WDENA_BASE CONFIG_SYS_NIOS_CPU_PIO2 /* PIO2 */ -#elif (CONFIG_SYS_NIOS_CPU_WDENA_PIO == 3) -#define CONFIG_HW_WDENA_BASE CONFIG_SYS_NIOS_CPU_PIO3 /* PIO3 */ -#elif (CONFIG_SYS_NIOS_CPU_WDENA_PIO == 4) -#define CONFIG_HW_WDENA_BASE CONFIG_SYS_NIOS_CPU_PIO4 /* PIO4 */ -#elif (CONFIG_SYS_NIOS_CPU_WDENA_PIO == 5) -#define CONFIG_HW_WDENA_BASE CONFIG_SYS_NIOS_CPU_PIO5 /* PIO5 */ -#elif (CONFIG_SYS_NIOS_CPU_WDENA_PIO == 6) -#define CONFIG_HW_WDENA_BASE CONFIG_SYS_NIOS_CPU_PIO6 /* PIO6 */ -#elif (CONFIG_SYS_NIOS_CPU_WDENA_PIO == 7) -#define CONFIG_HW_WDENA_BASE CONFIG_SYS_NIOS_CPU_PIO7 /* PIO7 */ -#elif (CONFIG_SYS_NIOS_CPU_WDENA_PIO == 8) -#define CONFIG_HW_WDENA_BASE CONFIG_SYS_NIOS_CPU_PIO8 /* PIO8 */ -#elif (CONFIG_SYS_NIOS_CPU_WDENA_PIO == 9) -#define CONFIG_HW_WDENA_BASE CONFIG_SYS_NIOS_CPU_PIO9 /* PIO9 */ -#else -#error *** CONFIG_SYS_ERROR: you have to setup at least one WDENA_PIO in NIOS CPU config -#endif - -/* MAX823 supervisor -- watchdog trigger port at: */ -#if (CONFIG_SYS_NIOS_CPU_WDTOG_PIO == 0) -#define CONFIG_HW_WDTOG_BASE CONFIG_SYS_NIOS_CPU_PIO0 /* PIO0 */ -#elif (CONFIG_SYS_NIOS_CPU_WDTOG_PIO == 1) -#define CONFIG_HW_WDTOG_BASE CONFIG_SYS_NIOS_CPU_PIO1 /* PIO1 */ -#elif (CONFIG_SYS_NIOS_CPU_WDTOG_PIO == 2) -#define CONFIG_HW_WDTOG_BASE CONFIG_SYS_NIOS_CPU_PIO2 /* PIO2 */ -#elif (CONFIG_SYS_NIOS_CPU_WDTOG_PIO == 3) -#define CONFIG_HW_WDTOG_BASE CONFIG_SYS_NIOS_CPU_PIO3 /* PIO3 */ -#elif (CONFIG_SYS_NIOS_CPU_WDTOG_PIO == 4) -#define CONFIG_HW_WDTOG_BASE CONFIG_SYS_NIOS_CPU_PIO4 /* PIO4 */ -#elif (CONFIG_SYS_NIOS_CPU_WDTOG_PIO == 5) -#define CONFIG_HW_WDTOG_BASE CONFIG_SYS_NIOS_CPU_PIO5 /* PIO5 */ -#elif (CONFIG_SYS_NIOS_CPU_WDTOG_PIO == 6) -#define CONFIG_HW_WDTOG_BASE CONFIG_SYS_NIOS_CPU_PIO6 /* PIO6 */ -#elif (CONFIG_SYS_NIOS_CPU_WDTOG_PIO == 7) -#define CONFIG_HW_WDTOG_BASE CONFIG_SYS_NIOS_CPU_PIO7 /* PIO7 */ -#elif (CONFIG_SYS_NIOS_CPU_WDTOG_PIO == 8) -#define CONFIG_HW_WDTOG_BASE CONFIG_SYS_NIOS_CPU_PIO8 /* PIO8 */ -#elif (CONFIG_SYS_NIOS_CPU_WDTOG_PIO == 9) -#define CONFIG_HW_WDTOG_BASE CONFIG_SYS_NIOS_CPU_PIO9 /* PIO9 */ -#else -#error *** CONFIG_SYS_ERROR: you have to setup at least one WDTOG_PIO in NIOS CPU config -#endif - -#if defined(CONFIG_NIOS_BASE_32) /* NIOS CPU specifics */ -#define CONFIG_HW_WDENA_BIT 0 /* WD enable @ Bit 0 */ -#define CONFIG_HW_WDTOG_BIT 0 /* WD trigger @ Bit 0 */ -#define CONFIG_HW_WDPORT_WRONLY 1 /* each WD port wr/only*/ -#else -#error *** CONFIG_SYS_ERROR: missing watchdog bit configuration, expand your config.h -#endif - -#endif /* CONFIG_HW_WATCHDOG */ - -/*------------------------------------------------------------------------ - * SERIAL PERIPHAREL INTERFACE - *----------------------------------------------------------------------*/ -#if (CONFIG_SYS_NIOS_CPU_SPI_NUMS == 1) - -#define CONFIG_NIOS_SPI 1 /* SPI support active */ -#define CONFIG_SYS_NIOS_SPIBASE CONFIG_SYS_NIOS_CPU_SPI0 -#define CONFIG_SYS_NIOS_SPIBITS CONFIG_SYS_NIOS_CPU_SPI0_BITS - -#define CONFIG_RTC_DS1306 1 /* Dallas 1306 real time clock */ -#define CONFIG_SYS_SPI_RTC_DEVID 0 /* as 1st SPI device */ - -#else -#undef CONFIG_NIOS_SPI /* NO SPI support */ -#endif - -/*------------------------------------------------------------------------ - * Ethernet -- needs work! - *----------------------------------------------------------------------*/ -#if (CONFIG_SYS_NIOS_CPU_LAN_NUMS == 1) - -#if (CONFIG_SYS_NIOS_CPU_LAN0_TYPE == 0) /* LAN91C111 */ - -#define CONFIG_DRIVER_SMC91111 /* Using SMC91c111 */ -#undef CONFIG_SMC91111_EXT_PHY /* Internal PHY */ -#define CONFIG_SMC91111_BASE (CONFIG_SYS_NIOS_CPU_LAN0_BASE + CONFIG_SYS_NIOS_CPU_LAN0_OFFS) - -#if (CONFIG_SYS_NIOS_CPU_LAN0_BUSW == 32) -#define CONFIG_SMC_USE_32_BIT 1 -#else /* no */ -#undef CONFIG_SMC_USE_32_BIT -#endif - -#elif (CONFIG_SYS_NIOS_CPU_LAN0_TYPE == 1) /* CS8900A */ - - /********************************************/ - /* !!! CS8900 is __not__ tested on NIOS !!! */ - /********************************************/ -#define CONFIG_NET_MULTI -#define CONFIG_CS8900 /* Using CS8900 */ -#define CONFIG_CS8900_BASE (CONFIG_SYS_NIOS_CPU_LAN0_BASE + \ - CONFIG_SYS_NIOS_CPU_LAN0_OFFS) - -#if (CONFIG_SYS_NIOS_CPU_LAN0_BUSW == 32) -#undef CONFIG_CS8900_BUS16 -#define CONFIG_CS8900_BUS32 -#else /* no */ -#define CONFIG_CS8900_BUS16 -#undef CONFIG_CS8900_BUS32 -#endif - -#else -#error *** CONFIG_SYS_ERROR: invalid LAN0 chip type, check your NIOS CPU config -#endif - -#define CONFIG_ETHADDR 02:80:ae:20:60:6f -#define CONFIG_NETMASK 255.255.255.248 -#define CONFIG_IPADDR 192.168.161.84 -#define CONFIG_SERVERIP 192.168.161.85 - -#else -#error *** CONFIG_SYS_ERROR: you have to setup just one LAN only or expand your config.h -#endif - -/*------------------------------------------------------------------------ - * STATUS LEDs - *----------------------------------------------------------------------*/ -#if (CONFIG_SYS_NIOS_CPU_PIO_NUMS != 0) && defined(CONFIG_SYS_NIOS_CPU_LED_PIO) - -#if (CONFIG_SYS_NIOS_CPU_LED_PIO == 0) - -#define STATUS_LED_BASE CONFIG_SYS_NIOS_CPU_PIO0 -#define STATUS_LED_BITS CONFIG_SYS_NIOS_CPU_PIO0_BITS -#define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */ - -#if (CONFIG_SYS_NIOS_CPU_PIO0_TYPE == 1) -#define STATUS_LED_WRONLY 1 -#else -#undef STATUS_LED_WRONLY -#endif - -#elif (CONFIG_SYS_NIOS_CPU_LED_PIO == 1) - -#define STATUS_LED_BASE CONFIG_SYS_NIOS_CPU_PIO1 -#define STATUS_LED_BITS CONFIG_SYS_NIOS_CPU_PIO1_BITS -#define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */ - -#if (CONFIG_SYS_NIOS_CPU_PIO1_TYPE == 1) -#define STATUS_LED_WRONLY 1 -#else -#undef STATUS_LED_WRONLY -#endif - -#elif (CONFIG_SYS_NIOS_CPU_LED_PIO == 2) - -#define STATUS_LED_BASE CONFIG_SYS_NIOS_CPU_PIO2 -#define STATUS_LED_BITS CONFIG_SYS_NIOS_CPU_PIO2_BITS -#define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */ - -#if (CONFIG_SYS_NIOS_CPU_PIO2_TYPE == 1) -#define STATUS_LED_WRONLY 1 -#else -#undef STATUS_LED_WRONLY -#endif - -#elif (CONFIG_SYS_NIOS_CPU_LED_PIO == 3) - -#error *** CONFIG_SYS_ERROR: status LEDs at PIO3 not supported, expand your config.h - -#elif (CONFIG_SYS_NIOS_CPU_LED_PIO == 4) - -#error *** CONFIG_SYS_ERROR: status LEDs at PIO4 not supported, expand your config.h - -#elif (CONFIG_SYS_NIOS_CPU_LED_PIO == 5) - -#error *** CONFIG_SYS_ERROR: status LEDs at PIO5 not supported, expand your config.h - -#elif (CONFIG_SYS_NIOS_CPU_LED_PIO == 6) - -#error *** CONFIG_SYS_ERROR: status LEDs at PIO6 not supported, expand your config.h - -#elif (CONFIG_SYS_NIOS_CPU_LED_PIO == 7) - -#error *** CONFIG_SYS_ERROR: status LEDs at PIO7 not supported, expand your config.h - -#elif (CONFIG_SYS_NIOS_CPU_LED_PIO == 8) - -#error *** CONFIG_SYS_ERROR: status LEDs at PIO8 not supported, expand your config.h - -#elif (CONFIG_SYS_NIOS_CPU_LED_PIO == 9) - -#error *** CONFIG_SYS_ERROR: status LEDs at PIO9 not supported, expand your config.h - -#else -#error *** CONFIG_SYS_ERROR: you have to set CONFIG_SYS_NIOS_CPU_LED_PIO in right case -#endif - -#define CONFIG_STATUS_LED 1 /* enable status led driver */ - -#define STATUS_LED_BIT (1 << 0) /* LED[0] */ -#define STATUS_LED_STATE STATUS_LED_BLINKING -#define STATUS_LED_BOOT_STATE STATUS_LED_OFF -#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) /* ca. 1 Hz */ -#define STATUS_LED_BOOT 0 /* boot LED */ - -#if (STATUS_LED_BITS > 1) -#define STATUS_LED_BIT1 (1 << 1) /* LED[1] */ -#define STATUS_LED_STATE1 STATUS_LED_OFF -#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 10) /* ca. 5 Hz */ -#define STATUS_LED_RED 1 /* fail LED */ -#endif - -#if (STATUS_LED_BITS > 2) -#define STATUS_LED_BIT2 (1 << 2) /* LED[2] */ -#define STATUS_LED_STATE2 STATUS_LED_OFF -#define STATUS_LED_PERIOD2 (CONFIG_SYS_HZ / 2) /* ca. 1 Hz */ -#define STATUS_LED_YELLOW 2 /* info LED */ -#endif - -#if (STATUS_LED_BITS > 3) -#define STATUS_LED_BIT3 (1 << 3) /* LED[3] */ -#define STATUS_LED_STATE3 STATUS_LED_OFF -#define STATUS_LED_PERIOD3 (CONFIG_SYS_HZ / 2) /* ca. 1 Hz */ -#define STATUS_LED_GREEN 3 /* info LED */ -#endif - -#define STATUS_LED_PAR 1 /* makes status_led.h happy */ - -#endif /* CONFIG_SYS_NIOS_CPU_PIO_NUMS */ - -/*------------------------------------------------------------------------ - * Diagnostics / Power On Self Tests - *----------------------------------------------------------------------*/ -#define CONFIG_POST CONFIG_SYS_POST_RTC -#define CONFIG_SYS_NIOS_POST_WORD_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_BSP -#define CONFIG_CMD_CDP -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_DISPLAY -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_IMMAP -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_PING -#define CONFIG_CMD_PORTIO -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_REISER -#define CONFIG_CMD_SAVES -#define CONFIG_CMD_SDRAM -#define CONFIG_CMD_SNTP - -#undef CONFIG_CMD_NFS -#undef CONFIG_CMD_XIMG - -#if (CONFIG_SYS_NIOS_CPU_SPI_NUMS == 1) -#define CONFIG_CMD_DATE -#define CONFIG_CMD_SPI -#endif - -/*------------------------------------------------------------------------ - * KGDB - *----------------------------------------------------------------------*/ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 9600 -#endif - -/*------------------------------------------------------------------------ - * MISC - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser - undef to save memory */ -#define CONFIG_SYS_PROMPT "ADNPESC1 > " /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 64 /* max number of command args*/ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#ifdef CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT_HUSH_PS2 "[]> " -#endif - -/* Default load address */ -#if (CONFIG_SYS_SRAM_SIZE != 0) - -/* default in SRAM */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SRAM_BASE - -#elif (CONFIG_SYS_SDRAM_SIZE != 0) - -/* default in SDRAM */ -#if (CONFIG_SYS_SDRAM_BASE == CONFIG_SYS_NIOS_CPU_VEC_BASE) -#if 1 -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_NIOS_CPU_VEC_SIZE) -#else -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x400000) -#endif -#else -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE -#endif - -#else -#undef CONFIG_SYS_LOAD_ADDR /* force error break */ -#endif - -/* MEM test area */ -#if (CONFIG_SYS_SDRAM_SIZE != 0) - -/* SDRAM begin to stack area (1MB stack) */ -#if (CONFIG_SYS_SDRAM_BASE == CONFIG_SYS_NIOS_CPU_VEC_BASE) -#if 0 -#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_NIOS_CPU_VEC_SIZE) -#else -#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x400000) -#endif -#else -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#endif - -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_INIT_SP - (1024 * 1024)) -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_INIT_SP - (1024 * 1024)) - -#else -#undef CONFIG_SYS_MEMTEST_START /* force error break */ -#undef CONFIG_SYS_MEMTEST_END -#endif - -/* - * JFFS2 partitions - * - */ -/* No command line, one static partition */ -#undef CONFIG_CMD_MTDPARTS -#define CONFIG_JFFS2_DEV "nor" -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 - -/* mtdparts command line support */ -/* -#define CONFIG_CMD_MTDPARTS -#define MTDIDS_DEFAULT "" -#define MTDPARTS_DEFAULT "" -*/ - -#endif /* __CONFIG_H */ diff --git a/include/configs/ADNPESC1_base_32.h b/include/configs/ADNPESC1_base_32.h deleted file mode 100644 index 1fe8d095be..0000000000 --- a/include/configs/ADNPESC1_base_32.h +++ /dev/null @@ -1,431 +0,0 @@ -/* - * (C) Copyright 2004, Li-Pro.Net - * Stephan Linz - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_ADNPESC1_BASE_32_H -#define __CONFIG_ADNPESC1_BASE_32_H - -/* - * NIOS CPU configuration. (PART OF configs/ADNPESC1.h) - * - * Here we must define CPU dependencies. Any unsupported option have to - * be undefined or defined with zero, example CPU without data cache / OCI: - * - * #define CONFIG_SYS_NIOS_CPU_ICACHE 4096 - * #define CONFIG_SYS_NIOS_CPU_DCACHE 0 - * #undef CONFIG_SYS_NIOS_CPU_OCI_BASE - * #undef CONFIG_SYS_NIOS_CPU_OCI_SIZE - */ - -/* CPU core */ -#define CONFIG_SYS_NIOS_CPU_CLK 50000000 /* NIOS CPU clock */ -#define CONFIG_SYS_NIOS_CPU_ICACHE (0) /* instruction cache */ -#define CONFIG_SYS_NIOS_CPU_DCACHE (0) /* data cache */ -#define CONFIG_SYS_NIOS_CPU_REG_NUMS 512 /* number of register */ -#define CONFIG_SYS_NIOS_CPU_MUL 0 /* 16x16 MUL: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_MSTEP 1 /* 16x16 MSTEP: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_STACK 0x03000000 /* stack top addr */ -#define CONFIG_SYS_NIOS_CPU_VEC_BASE 0x02000000 /* IRQ vectors addr */ -#define CONFIG_SYS_NIOS_CPU_VEC_SIZE 256 /* size */ -#define CONFIG_SYS_NIOS_CPU_VEC_NUMS 64 /* numbers */ -#define CONFIG_SYS_NIOS_CPU_RST_VECT 0x00000000 /* RESET vector addr */ -#define CONFIG_SYS_NIOS_CPU_DBG_CORE 0 /* CPU debug: no(0) */ - /* yes(1) */ - -/* The offset address in flash to check for the Nios signature "Ni". - * (see GM_FlashExec in germs_monitor.s) */ -#define CONFIG_SYS_NIOS_CPU_EXES_OFFS 0x0C - -/* on-chip extensions */ -#undef CONFIG_SYS_NIOS_CPU_RAM_BASE /* on chip RAM addr */ -#undef CONFIG_SYS_NIOS_CPU_RAM_SIZE /* 64 KB size */ - -#define CONFIG_SYS_NIOS_CPU_ROM_BASE 0x00000000 /* on chip ROM addr */ -#define CONFIG_SYS_NIOS_CPU_ROM_SIZE (2 * 1024) /* 2 KB size */ - -#undef CONFIG_SYS_NIOS_CPU_OCI_BASE /* OCI core addr */ -#undef CONFIG_SYS_NIOS_CPU_OCI_SIZE /* size */ - -/* timer */ -#define CONFIG_SYS_NIOS_CPU_TIMER_NUMS 1 /* number of timer */ - -#define CONFIG_SYS_NIOS_CPU_TIMER0 0x00000840 /* TIMER0 addr */ -#define CONFIG_SYS_NIOS_CPU_TIMER0_IRQ 16 /* IRQ */ -#define CONFIG_SYS_NIOS_CPU_TIMER0_PER 1000 /* periode usec */ -#define CONFIG_SYS_NIOS_CPU_TIMER0_AR 0 /* always run: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_TIMER0_FP 0 /* fixed per: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_TIMER0_SS 1 /* snaphot: no(0) */ - /* yes(1) */ - -/* serial i/o */ -#define CONFIG_SYS_NIOS_CPU_UART_NUMS 2 /* number of uarts */ - -#define CONFIG_SYS_NIOS_CPU_UART0 0x00000800 /* UART0 addr */ -#define CONFIG_SYS_NIOS_CPU_UART0_IRQ 17 /* IRQ */ -#define CONFIG_SYS_NIOS_CPU_UART0_BR 115200 /* baudrate var(0) */ -#define CONFIG_SYS_NIOS_CPU_UART0_DB 8 /* data bit */ -#define CONFIG_SYS_NIOS_CPU_UART0_SB 1 /* stop bit */ -#define CONFIG_SYS_NIOS_CPU_UART0_PA 0 /* parity none(0) */ - /* odd(1) */ - /* even(2) */ -#define CONFIG_SYS_NIOS_CPU_UART0_HS 1 /* handshake: no(0) */ - /* crts(1) */ -#define CONFIG_SYS_NIOS_CPU_UART0_EOP 0 /* eop reg: no(0) */ - /* yes(1) */ - -#define CONFIG_SYS_NIOS_CPU_UART1 0x00000820 /* UART1 addr */ -#define CONFIG_SYS_NIOS_CPU_UART1_IRQ 18 /* IRQ */ -#define CONFIG_SYS_NIOS_CPU_UART1_BR 115200 /* baudrate var(0) */ -#define CONFIG_SYS_NIOS_CPU_UART1_DB 8 /* data bit */ -#define CONFIG_SYS_NIOS_CPU_UART1_SB 1 /* stop bit */ -#define CONFIG_SYS_NIOS_CPU_UART1_PA 0 /* parity none(0) */ - /* odd(1) */ - /* even(2) */ -#define CONFIG_SYS_NIOS_CPU_UART1_HS 0 /* handshake: no(0) */ - /* crts(1) */ -#define CONFIG_SYS_NIOS_CPU_UART1_EOP 0 /* eop reg: no(0) */ - /* yes(1) */ - -/* serial peripheral i/o */ -#define CONFIG_SYS_NIOS_CPU_SPI_NUMS 1 /* number of spis */ - -#define CONFIG_SYS_NIOS_CPU_SPI0 0x000008c0 /* SPI0 addr */ -#define CONFIG_SYS_NIOS_CPU_SPI0_IRQ 25 /* IRQ */ -#define CONFIG_SYS_NIOS_CPU_SPI0_BITS 16 /* data bit */ -#define CONFIG_SYS_NIOS_CPU_SPI0_MA 1 /* is master: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_SPI0_SLN 1 /* num slaves */ -#define CONFIG_SYS_NIOS_CPU_SPI0_TCLK 250000 /* clock (Hz) */ -#define CONFIG_SYS_NIOS_CPU_SPI0_TDELAY 2 /* delay (usec) */ -#define CONFIG_SYS_NIOS_CPU_SPI0_FB 0 /* first bit msb(0) */ - /* lsb(1) */ - -/* parallel i/o */ -#define CONFIG_SYS_NIOS_CPU_PIO_NUMS 14 /* number of parports */ - -#define CONFIG_SYS_NIOS_CPU_PIO0 0x00000860 /* PIO0 addr */ -#undef CONFIG_SYS_NIOS_CPU_PIO0_IRQ /* w/o IRQ */ -#define CONFIG_SYS_NIOS_CPU_PIO0_BITS 8 /* number of bits */ -#define CONFIG_SYS_NIOS_CPU_PIO0_TYPE 0 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CONFIG_SYS_NIOS_CPU_PIO0_CAP 0 /* capture: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_PIO0_EDGE 0 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CONFIG_SYS_NIOS_CPU_PIO0_ITYPE 0 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CONFIG_SYS_NIOS_CPU_PIO1 0x00000870 /* PIO1 addr */ -#undef CONFIG_SYS_NIOS_CPU_PIO1_IRQ /* w/o IRQ */ -#define CONFIG_SYS_NIOS_CPU_PIO1_BITS 8 /* number of bits */ -#define CONFIG_SYS_NIOS_CPU_PIO1_TYPE 0 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CONFIG_SYS_NIOS_CPU_PIO1_CAP 0 /* capture: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_PIO1_EDGE 0 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CONFIG_SYS_NIOS_CPU_PIO1_ITYPE 0 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CONFIG_SYS_NIOS_CPU_PIO2 0x00000880 /* PIO2 addr */ -#undef CONFIG_SYS_NIOS_CPU_PIO2_IRQ /* w/o IRQ */ -#define CONFIG_SYS_NIOS_CPU_PIO2_BITS 4 /* number of bits */ -#define CONFIG_SYS_NIOS_CPU_PIO2_TYPE 0 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CONFIG_SYS_NIOS_CPU_PIO2_CAP 0 /* capture: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_PIO2_EDGE 0 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CONFIG_SYS_NIOS_CPU_PIO2_ITYPE 0 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CONFIG_SYS_NIOS_CPU_PIO3 0x00000890 /* PIO3 addr */ -#undef CONFIG_SYS_NIOS_CPU_PIO3_IRQ /* w/o IRQ */ -#define CONFIG_SYS_NIOS_CPU_PIO3_BITS 1 /* number of bits */ -#define CONFIG_SYS_NIOS_CPU_PIO3_TYPE 2 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CONFIG_SYS_NIOS_CPU_PIO3_CAP 0 /* capture: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_PIO3_EDGE 0 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CONFIG_SYS_NIOS_CPU_PIO3_ITYPE 0 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CONFIG_SYS_NIOS_CPU_PIO3 0x00000890 /* PIO3 addr */ -#undef CONFIG_SYS_NIOS_CPU_PIO3_IRQ /* w/o IRQ */ -#define CONFIG_SYS_NIOS_CPU_PIO3_BITS 1 /* number of bits */ -#define CONFIG_SYS_NIOS_CPU_PIO3_TYPE 2 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CONFIG_SYS_NIOS_CPU_PIO3_CAP 0 /* capture: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_PIO3_EDGE 0 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CONFIG_SYS_NIOS_CPU_PIO3_ITYPE 0 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CONFIG_SYS_NIOS_CPU_PIO4 0x000008a0 /* PIO4 addr */ -#undef CONFIG_SYS_NIOS_CPU_PIO4_IRQ /* w/o IRQ */ -#define CONFIG_SYS_NIOS_CPU_PIO4_BITS 1 /* number of bits */ -#define CONFIG_SYS_NIOS_CPU_PIO4_TYPE 1 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CONFIG_SYS_NIOS_CPU_PIO4_CAP 0 /* capture: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_PIO4_EDGE 0 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CONFIG_SYS_NIOS_CPU_PIO4_ITYPE 0 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CONFIG_SYS_NIOS_CPU_PIO5 0x000008b0 /* PIO5 addr */ -#undef CONFIG_SYS_NIOS_CPU_PIO5_IRQ /* w/o IRQ */ -#define CONFIG_SYS_NIOS_CPU_PIO5_BITS 1 /* number of bits */ -#define CONFIG_SYS_NIOS_CPU_PIO5_TYPE 1 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CONFIG_SYS_NIOS_CPU_PIO5_CAP 0 /* capture: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_PIO5_EDGE 0 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CONFIG_SYS_NIOS_CPU_PIO5_ITYPE 0 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CONFIG_SYS_NIOS_CPU_PIO6 0x00000900 /* PIO6 addr */ -#define CONFIG_SYS_NIOS_CPU_PIO6_IRQ 20 /* IRQ */ -#define CONFIG_SYS_NIOS_CPU_PIO6_BITS 1 /* number of bits */ -#define CONFIG_SYS_NIOS_CPU_PIO6_TYPE 2 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CONFIG_SYS_NIOS_CPU_PIO6_CAP 1 /* capture: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_PIO6_EDGE 2 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CONFIG_SYS_NIOS_CPU_PIO6_ITYPE 1 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CONFIG_SYS_NIOS_CPU_PIO7 0x00000910 /* PIO7 addr */ -#define CONFIG_SYS_NIOS_CPU_PIO7_IRQ 31 /* IRQ */ -#define CONFIG_SYS_NIOS_CPU_PIO7_BITS 1 /* number of bits */ -#define CONFIG_SYS_NIOS_CPU_PIO7_TYPE 2 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CONFIG_SYS_NIOS_CPU_PIO7_CAP 1 /* capture: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_PIO7_EDGE 2 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CONFIG_SYS_NIOS_CPU_PIO7_ITYPE 1 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CONFIG_SYS_NIOS_CPU_PIO8 0x00000920 /* PIO8 addr */ -#define CONFIG_SYS_NIOS_CPU_PIO8_IRQ 32 /* IRQ */ -#define CONFIG_SYS_NIOS_CPU_PIO8_BITS 1 /* number of bits */ -#define CONFIG_SYS_NIOS_CPU_PIO8_TYPE 2 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CONFIG_SYS_NIOS_CPU_PIO8_CAP 1 /* capture: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_PIO8_EDGE 2 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CONFIG_SYS_NIOS_CPU_PIO8_ITYPE 1 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CONFIG_SYS_NIOS_CPU_PIO9 0x00000930 /* PIO9 addr */ -#define CONFIG_SYS_NIOS_CPU_PIO9_IRQ 33 /* IRQ */ -#define CONFIG_SYS_NIOS_CPU_PIO9_BITS 1 /* number of bits */ -#define CONFIG_SYS_NIOS_CPU_PIO9_TYPE 2 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CONFIG_SYS_NIOS_CPU_PIO9_CAP 1 /* capture: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_PIO9_EDGE 2 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CONFIG_SYS_NIOS_CPU_PIO9_ITYPE 1 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CONFIG_SYS_NIOS_CPU_PIO10 0x00000940 /* PIO10 addr */ -#define CONFIG_SYS_NIOS_CPU_PIO10_IRQ 34 /* IRQ */ -#define CONFIG_SYS_NIOS_CPU_PIO10_BITS 1 /* number of bits */ -#define CONFIG_SYS_NIOS_CPU_PIO10_TYPE 2 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CONFIG_SYS_NIOS_CPU_PIO10_CAP 1 /* capture: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_PIO10_EDGE 2 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CONFIG_SYS_NIOS_CPU_PIO10_ITYPE 1 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CONFIG_SYS_NIOS_CPU_PIO11 0x00000950 /* PIO11 addr */ -#define CONFIG_SYS_NIOS_CPU_PIO11_IRQ 35 /* IRQ */ -#define CONFIG_SYS_NIOS_CPU_PIO11_BITS 1 /* number of bits */ -#define CONFIG_SYS_NIOS_CPU_PIO11_TYPE 2 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CONFIG_SYS_NIOS_CPU_PIO11_CAP 1 /* capture: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_PIO11_EDGE 2 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CONFIG_SYS_NIOS_CPU_PIO11_ITYPE 1 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CONFIG_SYS_NIOS_CPU_PIO12 0x00000960 /* PIO12 addr */ -#define CONFIG_SYS_NIOS_CPU_PIO12_IRQ 36 /* IRQ */ -#define CONFIG_SYS_NIOS_CPU_PIO12_BITS 1 /* number of bits */ -#define CONFIG_SYS_NIOS_CPU_PIO12_TYPE 2 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CONFIG_SYS_NIOS_CPU_PIO12_CAP 1 /* capture: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_PIO12_EDGE 2 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CONFIG_SYS_NIOS_CPU_PIO12_ITYPE 1 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CONFIG_SYS_NIOS_CPU_PIO13 0x00000970 /* PIO113 addr */ -#define CONFIG_SYS_NIOS_CPU_PIO13_IRQ 37 /* IRQ */ -#define CONFIG_SYS_NIOS_CPU_PIO13_BITS 1 /* number of bits */ -#define CONFIG_SYS_NIOS_CPU_PIO13_TYPE 2 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CONFIG_SYS_NIOS_CPU_PIO13_CAP 1 /* capture: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_PIO13_EDGE 2 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CONFIG_SYS_NIOS_CPU_PIO13_ITYPE 1 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -/* IDE i/f */ -#define CONFIG_SYS_NIOS_CPU_IDE_NUMS 2 /* number of IDE contr. */ - -#define CONFIG_SYS_NIOS_CPU_IDE0 0x00001000 /* IDE0 addr */ -#define CONFIG_SYS_NIOS_CPU_IDE0_IRQ 36 /* IRQ */ - -#define CONFIG_SYS_NIOS_CPU_IDE1 0x00001020 /* IDE1 addr */ -#define CONFIG_SYS_NIOS_CPU_IDE1_IRQ 37 /* IRQ */ - -/* memory accessibility */ -#undef CONFIG_SYS_NIOS_CPU_SRAM_BASE /* board SRAM addr */ -#undef CONFIG_SYS_NIOS_CPU_SRAM_SIZE /* 1 MB size */ - -#define CONFIG_SYS_NIOS_CPU_SDRAM_BASE 0x02000000 /* board SDRAM addr */ -#define CONFIG_SYS_NIOS_CPU_SDRAM_SIZE (16*1024*1024) /* 16 MB size */ - -#define CONFIG_SYS_NIOS_CPU_FLASH_BASE 0x01000000 /* board Flash addr */ -#define CONFIG_SYS_NIOS_CPU_FLASH_SIZE (8*1024*1024) /* 8 MB size */ - -/* LAN */ -#define CONFIG_SYS_NIOS_CPU_LAN_NUMS 1 /* number of LAN i/f */ - -#define CONFIG_SYS_NIOS_CPU_LAN0_BASE 0x00010000 /* LAN0 addr */ -#define CONFIG_SYS_NIOS_CPU_LAN0_OFFS (0) /* offset */ -#define CONFIG_SYS_NIOS_CPU_LAN0_IRQ 20 /* IRQ */ -#define CONFIG_SYS_NIOS_CPU_LAN0_BUSW 16 /* buswidth*/ -#define CONFIG_SYS_NIOS_CPU_LAN0_TYPE 0 /* smc91111(0) */ - /* cs8900(1) */ - /* ex: openmac(2) */ - /* ex: alteramac(3) */ - -/* external extension */ -#define CONFIG_SYS_NIOS_CPU_CS0_BASE 0x40000000 /* board EXT0 addr */ -#define CONFIG_SYS_NIOS_CPU_CS0_SIZE (16*1024*1024) /* max. 16 MB size */ - -#define CONFIG_SYS_NIOS_CPU_CS1_BASE 0x41000000 /* board EXT1 addr */ -#define CONFIG_SYS_NIOS_CPU_CS1_SIZE (16*1024*1024) /* max. 16 MB size */ - -#define CONFIG_SYS_NIOS_CPU_CS2_BASE 0x42000000 /* board EXT2 addr */ -#define CONFIG_SYS_NIOS_CPU_CS2_SIZE (16*1024*1024) /* max. 16 MB size */ - -#define CONFIG_SYS_NIOS_CPU_CS3_BASE 0x43000000 /* board EXT3 addr */ -#define CONFIG_SYS_NIOS_CPU_CS3_SIZE (16*1024*1024) /* max. 16 MB size */ - -/* symbolic redefinition (undef, if not present) */ -#define CONFIG_SYS_NIOS_CPU_TICK_TIMER 0 /* TIMER0: tick (needed)*/ -#undef CONFIG_SYS_NIOS_CPU_USER_TIMER /* TIMERx: users choice */ - -#define CONFIG_SYS_NIOS_CPU_PORTA_PIO 0 /* PIO0: Port A */ -#define CONFIG_SYS_NIOS_CPU_PORTB_PIO 1 /* PIO1: Port D */ -#define CONFIG_SYS_NIOS_CPU_PORTC_PIO 2 /* PIO2: Port C */ -#define CONFIG_SYS_NIOS_CPU_RCM_PIO 3 /* PIO3: RCM jumper */ -#define CONFIG_SYS_NIOS_CPU_WDENA_PIO 4 /* PIO4: watchdog enable*/ -#define CONFIG_SYS_NIOS_CPU_WDTOG_PIO 5 /* PIO5: watchdog trigg.*/ - -/* PIOx: LED bar */ -#ifdef CONFIG_DNPEVA2 /* DNP/EVA2 base board */ -#define CONFIG_SYS_NIOS_CPU_LED_PIO CONFIG_SYS_NIOS_CPU_PORTA_PIO -#else -#undef CONFIG_SYS_NIOS_CPU_LED_PIO /* no LED bar */ -#endif - -#endif /* __CONFIG_ADNPESC1_BASE_32_H */ diff --git a/include/configs/DK1C20.h b/include/configs/DK1C20.h deleted file mode 100644 index cdc488b38e..0000000000 --- a/include/configs/DK1C20.h +++ /dev/null @@ -1,555 +0,0 @@ -/* - * (C) Copyright 2003, Psyent Corporation - * Scott McNutt - * Stephan Linz - * - * CompactFlash/IDE: - * (C) Copyright 2004, Shlomo Kut - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/*********************************************************************** - * Include the whole NIOS CPU configuration. - * - * !!! HAVE TO BE HERE !!! DON'T MOVE THIS PART !!! - * - ***********************************************************************/ - -#if defined(CONFIG_NIOS_SAFE_32) -#include -#elif defined(CONFIG_NIOS_STANDARD_32) -#include -#else -#error *** CONFIG_SYS_ERROR: you have to setup right NIOS CPU configuration -#endif - -/*------------------------------------------------------------------------ - * BOARD/CPU -- TOP-LEVEL - *----------------------------------------------------------------------*/ -#define CONFIG_NIOS 1 /* NIOS-32 core */ -#define CONFIG_DK1C20 1 /* Cyclone DK-1C20 board*/ -#define CONFIG_SYS_CLK_FREQ CONFIG_SYS_NIOS_CPU_CLK/* 50 MHz core clock */ -#define CONFIG_SYS_HZ 1000 /* 1 msec time tick */ -#define CONFIG_BOARD_EARLY_INIT_F 1 /* enable early board-spec. init*/ - -/*------------------------------------------------------------------------ - * BASE ADDRESSES / SIZE (Flash, SRAM, SDRAM) - *----------------------------------------------------------------------*/ -#if (CONFIG_SYS_NIOS_CPU_SDRAM_SIZE != 0) - -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_NIOS_CPU_SDRAM_BASE -#define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_NIOS_CPU_SDRAM_SIZE - -#else -#error *** CONFIG_SYS_ERROR: you have to setup any SDRAM in NIOS CPU config -#endif - -#define CONFIG_SYS_SRAM_BASE CONFIG_SYS_NIOS_CPU_SRAM_BASE -#define CONFIG_SYS_SRAM_SIZE CONFIG_SYS_NIOS_CPU_SRAM_SIZE -#define CONFIG_SYS_VECT_BASE CONFIG_SYS_NIOS_CPU_VEC_BASE - -/*------------------------------------------------------------------------ - * MEMORY ORGANIZATION - For the most part, you can put things pretty - * much anywhere. This is pretty flexible for Nios. So here we make some - * arbitrary choices & assume that the monitor is placed at the end of - * a memory resource (so you must make sure TEXT_BASE is chosen - * appropriately). - * - * -The heap is placed below the monitor. - * -Global data is placed below the heap. - * -The stack is placed below global data (&grows down). - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256k */ -#define CONFIG_SYS_GBL_DATA_SIZE 128 /* Global data size rsvd*/ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) - -#define CONFIG_SYS_MONITOR_BASE TEXT_BASE -#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN) -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_MALLOC_BASE - CONFIG_SYS_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP CONFIG_SYS_GBL_DATA_OFFSET - -/*------------------------------------------------------------------------ - * FLASH (AM29LV065D) - *----------------------------------------------------------------------*/ -#if (CONFIG_SYS_NIOS_CPU_FLASH_SIZE != 0) - -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_NIOS_CPU_FLASH_BASE -#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_NIOS_CPU_FLASH_SIZE -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* Max # sects per bank */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max # of flash banks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Erase timeout (msec) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 100 /* Write timeout (msec) */ -#define CONFIG_SYS_FLASH_WORD_SIZE unsigned char /* flash word size */ - -#else -#error *** CONFIG_SYS_ERROR: you have to setup any Flash memory in NIOS CPU config -#endif - -/*------------------------------------------------------------------------ - * ENVIRONMENT - *----------------------------------------------------------------------*/ -#if (CONFIG_SYS_NIOS_CPU_FLASH_SIZE != 0) - -#define CONFIG_ENV_IS_IN_FLASH 1 /* Environment in flash */ -#define CONFIG_ENV_ADDR CONFIG_SYS_FLASH_BASE /* Mem addr of env */ -#define CONFIG_ENV_SIZE (64 * 1024) /* 64 KByte (1 sector) */ -#define CONFIG_ENV_OVERWRITE /* Serial/eth change Ok */ - -#else -#define CONFIG_ENV_IS_NOWHERE 1 /* NO Environment */ -#endif - -/*------------------------------------------------------------------------ - * CONSOLE - *----------------------------------------------------------------------*/ -#if (CONFIG_SYS_NIOS_CPU_UART_NUMS != 0) - -#define CONFIG_SYS_NIOS_CONSOLE CONFIG_SYS_NIOS_CPU_UART0 /* 1st UART is Cons. */ - -#if (CONFIG_SYS_NIOS_CPU_UART0_BR != 0) -#define CONFIG_SYS_NIOS_FIXEDBAUD 1 /* Baudrate is fixed */ -#define CONFIG_BAUDRATE CONFIG_SYS_NIOS_CPU_UART0_BR -#else -#undef CONFIG_SYS_NIOS_FIXEDBAUD -#define CONFIG_BAUDRATE 115200 -#endif - -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -#else -#error *** CONFIG_SYS_ERROR: you have to setup at least one UART in NIOS CPU config -#endif - -/*------------------------------------------------------------------------ - * TIMER FOR TIMEBASE -- Nios doesn't have the equivalent of ppc PIT, - * so an avalon bus timer is required. - *----------------------------------------------------------------------*/ -#if (CONFIG_SYS_NIOS_CPU_TIMER_NUMS != 0) - -#if (CONFIG_SYS_NIOS_CPU_TICK_TIMER == 0) - -#define CONFIG_SYS_NIOS_TMRBASE CONFIG_SYS_NIOS_CPU_TIMER0 /* TIMER0 as tick */ -#define CONFIG_SYS_NIOS_TMRIRQ CONFIG_SYS_NIOS_CPU_TIMER0_IRQ - -#if (CONFIG_SYS_NIOS_CPU_TIMER0_FP == 1) /* fixed period */ - -#if (CONFIG_SYS_NIOS_CPU_TIMER0_PER >= CONFIG_SYS_HZ) -#define CONFIG_SYS_NIOS_TMRMS (CONFIG_SYS_NIOS_CPU_TIMER0_PER / CONFIG_SYS_HZ) -#else -#error *** CONFIG_SYS_ERROR: you have to use a timer periode greater than CONFIG_SYS_HZ -#endif - -#undef CONFIG_SYS_NIOS_TMRCNT /* no preloadable counter value */ - -#elif (CONFIG_SYS_NIOS_CPU_TIMER0_FP == 0) /* variable period */ - -#if (CONFIG_SYS_HZ <= 1000) -#define CONFIG_SYS_NIOS_TMRMS (1000 / CONFIG_SYS_HZ) -#else -#error *** CONFIG_SYS_ERROR: sorry, CONFIG_SYS_HZ have to be less than 1000 -#endif - -#define CONFIG_SYS_NIOS_TMRCNT (CONFIG_SYS_CLK_FREQ / CONFIG_SYS_HZ) - -#else -#error *** CONFIG_SYS_ERROR: you have to define CONFIG_SYS_NIOS_CPU_TIMER0_FP correct -#endif - -#elif (CONFIG_SYS_NIOS_CPU_TICK_TIMER == 1) - -#define CONFIG_SYS_NIOS_TMRBASE CONFIG_SYS_NIOS_CPU_TIMER1 /* TIMER1 as tick */ -#define CONFIG_SYS_NIOS_TMRIRQ CONFIG_SYS_NIOS_CPU_TIMER1_IRQ - -#if (CONFIG_SYS_NIOS_CPU_TIMER1_FP == 1) /* fixed period */ - -#if (CONFIG_SYS_NIOS_CPU_TIMER1_PER >= CONFIG_SYS_HZ) -#define CONFIG_SYS_NIOS_TMRMS (CONFIG_SYS_NIOS_CPU_TIMER1_PER / CONFIG_SYS_HZ) -#else -#error *** CONFIG_SYS_ERROR: you have to use a timer periode greater than CONFIG_SYS_HZ -#endif - -#undef CONFIG_SYS_NIOS_TMRCNT /* no preloadable counter value */ - -#elif (CONFIG_SYS_NIOS_CPU_TIMER1_FP == 0) /* variable period */ - -#if (CONFIG_SYS_HZ <= 1000) -#define CONFIG_SYS_NIOS_TMRMS (1000 / CONFIG_SYS_HZ) -#else -#error *** CONFIG_SYS_ERROR: sorry, CONFIG_SYS_HZ have to be less than 1000 -#endif - -#define CONFIG_SYS_NIOS_TMRCNT (CONFIG_SYS_CLK_FREQ / CONFIG_SYS_HZ) - -#else -#error *** CONFIG_SYS_ERROR: you have to define CONFIG_SYS_NIOS_CPU_TIMER1_FP correct -#endif - -#endif /* CONFIG_SYS_NIOS_CPU_TICK_TIMER */ - -#else -#error *** CONFIG_SYS_ERROR: you have to setup at least one TIMER in NIOS CPU config -#endif - -/*------------------------------------------------------------------------ - * Ethernet - *----------------------------------------------------------------------*/ -#if (CONFIG_SYS_NIOS_CPU_LAN_NUMS == 1) - -#if (CONFIG_SYS_NIOS_CPU_LAN0_TYPE == 0) /* LAN91C111 */ - -#define CONFIG_DRIVER_SMC91111 /* Using SMC91c111 */ -#undef CONFIG_SMC91111_EXT_PHY /* Internal PHY */ -#define CONFIG_SMC91111_BASE (CONFIG_SYS_NIOS_CPU_LAN0_BASE + CONFIG_SYS_NIOS_CPU_LAN0_OFFS) - -#if (CONFIG_SYS_NIOS_CPU_LAN0_BUSW == 32) -#define CONFIG_SMC_USE_32_BIT 1 -#else /* no */ -#undef CONFIG_SMC_USE_32_BIT -#endif - -#elif (CONFIG_SYS_NIOS_CPU_LAN0_TYPE == 1) /* CS8900A */ - - /********************************************/ - /* !!! CS8900 is __not__ tested on NIOS !!! */ - /********************************************/ -#define CONFIG_NET_MULTI -#define CONFIG_CS8900 /* Using CS8900 */ -#define CONFIG_CS8900_BASE (CONFIG_SYS_NIOS_CPU_LAN0_BASE + \ - CONFIG_SYS_NIOS_CPU_LAN0_OFFS) - -#if (CONFIG_SYS_NIOS_CPU_LAN0_BUSW == 32) -#undef CONFIG_CS8900_BUS16 -#define CONFIG_CS8900_BUS32 -#else /* no */ -#define CONFIG_CS8900_BUS16 -#undef CONFIG_CS8900_BUS32 -#endif - -#else -#error *** CONFIG_SYS_ERROR: invalid LAN0 chip type, check your NIOS CPU config -#endif - -#define CONFIG_ETHADDR 08:00:3e:26:0a:5b -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_IPADDR 192.168.2.21 -#define CONFIG_SERVERIP 192.168.2.16 - -#else -#error *** CONFIG_SYS_ERROR: you have to setup just one LAN only or expand your config.h -#endif - -/*------------------------------------------------------------------------ - * STATUS LEDs - *----------------------------------------------------------------------*/ -#if (CONFIG_SYS_NIOS_CPU_PIO_NUMS != 0) - -#if (CONFIG_SYS_NIOS_CPU_LED_PIO == 0) - -#error *** CONFIG_SYS_ERROR: status LEDs at PIO0 not supported, expand your config.h - -#elif (CONFIG_SYS_NIOS_CPU_LED_PIO == 1) - -#error *** CONFIG_SYS_ERROR: status LEDs at PIO1 not supported, expand your config.h - -#elif (CONFIG_SYS_NIOS_CPU_LED_PIO == 2) - -#define STATUS_LED_BASE CONFIG_SYS_NIOS_CPU_PIO2 -#define STATUS_LED_BITS CONFIG_SYS_NIOS_CPU_PIO2_BITS -#define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */ - -#if (CONFIG_SYS_NIOS_CPU_PIO2_TYPE == 1) -#define STATUS_LED_WRONLY 1 -#else -#undef STATUS_LED_WRONLY -#endif - -#elif (CONFIG_SYS_NIOS_CPU_LED_PIO == 3) - -#error *** CONFIG_SYS_ERROR: status LEDs at PIO3 not supported, expand your config.h - -#elif (CONFIG_SYS_NIOS_CPU_LED_PIO == 4) - -#error *** CONFIG_SYS_ERROR: status LEDs at PIO4 not supported, expand your config.h - -#elif (CONFIG_SYS_NIOS_CPU_LED_PIO == 5) - -#error *** CONFIG_SYS_ERROR: status LEDs at PIO5 not supported, expand your config.h - -#elif (CONFIG_SYS_NIOS_CPU_LED_PIO == 6) - -#error *** CONFIG_SYS_ERROR: status LEDs at PIO6 not supported, expand your config.h - -#elif (CONFIG_SYS_NIOS_CPU_LED_PIO == 7) - -#error *** CONFIG_SYS_ERROR: status LEDs at PIO7 not supported, expand your config.h - -#elif (CONFIG_SYS_NIOS_CPU_LED_PIO == 8) - -#error *** CONFIG_SYS_ERROR: status LEDs at PIO8 not supported, expand your config.h - -#elif (CONFIG_SYS_NIOS_CPU_LED_PIO == 9) - -#error *** CONFIG_SYS_ERROR: status LEDs at PIO9 not supported, expand your config.h - -#else -#error *** CONFIG_SYS_ERROR: you have to set CONFIG_SYS_NIOS_CPU_LED_PIO in right case -#endif - -#define CONFIG_STATUS_LED 1 /* enable status led driver */ - -#define STATUS_LED_BIT (1 << 0) /* LED[0] */ -#define STATUS_LED_STATE STATUS_LED_BLINKING -#define STATUS_LED_BOOT_STATE STATUS_LED_OFF -#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 10) /* ca. 1 Hz */ -#define STATUS_LED_BOOT 0 /* boot LED */ - -#if (STATUS_LED_BITS > 1) -#define STATUS_LED_BIT1 (1 << 1) /* LED[1] */ -#define STATUS_LED_STATE1 STATUS_LED_OFF -#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 50) /* ca. 5 Hz */ -#define STATUS_LED_RED 1 /* fail LED */ -#endif - -#if (STATUS_LED_BITS > 2) -#define STATUS_LED_BIT2 (1 << 2) /* LED[2] */ -#define STATUS_LED_STATE2 STATUS_LED_OFF -#define STATUS_LED_PERIOD2 (CONFIG_SYS_HZ / 10) /* ca. 1 Hz */ -#define STATUS_LED_YELLOW 2 /* info LED */ -#endif - -#if (STATUS_LED_BITS > 3) -#define STATUS_LED_BIT3 (1 << 3) /* LED[3] */ -#define STATUS_LED_STATE3 STATUS_LED_OFF -#define STATUS_LED_PERIOD3 (CONFIG_SYS_HZ / 10) /* ca. 1 Hz */ -#define STATUS_LED_GREEN 3 /* info LED */ -#endif - -#define STATUS_LED_PAR 1 /* makes status_led.h happy */ - -#endif /* CONFIG_SYS_NIOS_CPU_PIO_NUMS */ - -/*------------------------------------------------------------------------ - * SEVEN SEGMENT LED DISPLAY - *----------------------------------------------------------------------*/ -#if (CONFIG_SYS_NIOS_CPU_PIO_NUMS != 0) - -#if (CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO == 0) - -#error *** CONFIG_SYS_ERROR: seven segment display at PIO0 not supported, expand your config.h - -#elif (CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO == 1) - -#error *** CONFIG_SYS_ERROR: seven segment display at PIO1 not supported, expand your config.h - -#elif (CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO == 2) - -#error *** CONFIG_SYS_ERROR: seven segment display at PIO2 not supported, expand your config.h - -#elif (CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO == 3) - -#define SEVENSEG_BASE CONFIG_SYS_NIOS_CPU_PIO3 -#define SEVENSEG_BITS CONFIG_SYS_NIOS_CPU_PIO3_BITS -#define SEVENSEG_ACTIVE 0 /* LED on for bit == 1 */ - -#if (CONFIG_SYS_NIOS_CPU_PIO3_TYPE == 1) -#define SEVENSEG_WRONLY 1 -#else -#undef SEVENSEG_WRONLY -#endif - -#elif (CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO == 4) - -#error *** CONFIG_SYS_ERROR: seven segment display at PIO4 not supported, expand your config.h - -#elif (CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO == 5) - -#error *** CONFIG_SYS_ERROR: seven segment display at PIO5 not supported, expand your config.h - -#elif (CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO == 6) - -#error *** CONFIG_SYS_ERROR: seven segment display at PIO6 not supported, expand your config.h - -#elif (CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO == 7) - -#error *** CONFIG_SYS_ERROR: seven segment display at PIO7 not supported, expand your config.h - -#elif (CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO == 8) - -#error *** CONFIG_SYS_ERROR: seven segment display at PIO8 not supported, expand your config.h - -#elif (CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO == 9) - -#error *** CONFIG_SYS_ERROR: seven segment display at PIO9 not supported, expand your config.h - -#else -#error *** CONFIG_SYS_ERROR: you have to set CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO in right case -#endif - -#define CONFIG_SEVENSEG 1 /* enable seven segment led driver */ - -/* - * Dual 7-Segment Display pin assignment -- read more in your - * "Nios Development Board Reference Manual" - * - * - * (U8) HI:D[15..8] (U9) LO:D[7..0] - * ______ ______ - * | D14 | | D6 | - * | | | | - * D9| |D13 D1| |D5 - * |______| |______| ___ - * | D8 | | D0 | | A | - * | | | | F|___|B - * D10| |D12 D2| |D4 | G | - * |______| |______| E|___|C - * D11 * D3 * D * - * D15 D7 DP - * - */ -#define SEVENSEG_DIGIT_HI_LO_EQUAL 1 /* high nibble equal low nibble */ -#define SEVENSEG_DIGIT_A (1 << 6) /* bit 6 is segment A */ -#define SEVENSEG_DIGIT_B (1 << 5) /* bit 5 is segment B */ -#define SEVENSEG_DIGIT_C (1 << 4) /* bit 4 is segment C */ -#define SEVENSEG_DIGIT_D (1 << 3) /* bit 3 is segment D */ -#define SEVENSEG_DIGIT_E (1 << 2) /* bit 2 is segment E */ -#define SEVENSEG_DIGIT_F (1 << 1) /* bit 1 is segment F */ -#define SEVENSEG_DIGIT_G (1 << 0) /* bit 0 is segment G */ -#define SEVENSEG_DIGIT_DP (1 << 7) /* bit 7 is decimal point */ - -#endif /* CONFIG_SYS_NIOS_CPU_PIO_NUMS */ - -/*------------------------------------------------------------------------ - * ASMI - Active Serial Memory Interface. - * - * ASMI is for Cyclone devices only and only works when the configuration - * is loaded via JTAG or ASMI. Please see doc/README.dk1c20 for details. - *----------------------------------------------------------------------*/ -#define CONFIG_NIOS_ASMI /* Enable ASMI */ -#define CONFIG_SYS_NIOS_ASMIBASE CONFIG_SYS_NIOS_CPU_ASMI0 /* ASMI base address */ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_CDP -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_DISPLAY -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT -#define CONFIG_CMD_IDE -#define CONFIG_CMD_IMMAP -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_PING -#define CONFIG_CMD_PORTIO -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_SAVES -#define CONFIG_CMD_SDRAM -#define CONFIG_CMD_SNTP - -#undef CONFIG_CMD_NFS -#undef CONFIG_CMD_XIMG - -/*------------------------------------------------------------------------ - * COMPACT FLASH - *----------------------------------------------------------------------*/ -#if defined(CONFIG_CMD_IDE) -#define CONFIG_IDE_PREINIT /* Implement id_preinit */ -#define CONFIG_SYS_IDE_MAXBUS 1 /* 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_BASE_ADDR 0x00920a00 /* IDE/ATA base addr */ -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 /* IDE0 offset */ -#define CONFIG_SYS_ATA_DATA_OFFSET 0x0040 /* Data IO offset */ -#define CONFIG_SYS_ATA_REG_OFFSET 0x0040 /* Register offset */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 /* Alternate reg offset */ -#define CONFIG_SYS_ATA_STRIDE 4 /* Width betwix addrs */ -#define CONFIG_DOS_PARTITION - -/* Board-specific cf regs */ -#define CONFIG_SYS_CF_PRESENT 0x009209b0 /* CF Present PIO base */ -#define CONFIG_SYS_CF_POWER 0x009209c0 /* CF Power FET PIO base*/ -#define CONFIG_SYS_CF_ATASEL 0x009209d0 /* CF ATASEL PIO base */ - -#endif - -/*------------------------------------------------------------------------ - * KGDB - *----------------------------------------------------------------------*/ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 9600 -#endif - -/*------------------------------------------------------------------------ - * MISC - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "DK1C20 > " /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args*/ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#if (CONFIG_SYS_SRAM_SIZE != 0) -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SRAM_BASE /* Default load address */ -#else -#undef CONFIG_SYS_LOAD_ADDR -#endif - -#if (CONFIG_SYS_SDRAM_SIZE != 0) -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE /* SDRAM til stack area */ -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_INIT_SP - (1024 * 1024)) /* 1MB stack */ -#else -#undef CONFIG_SYS_MEMTEST_START -#undef CONFIG_SYS_MEMTEST_END -#endif - -/* - * JFFS2 partitions - * - */ -/* No command line, one static partition, whole device */ -#undef CONFIG_CMD_MTDPARTS -#define CONFIG_JFFS2_DEV "nor0" -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 - -/* mtdparts command line support */ -/* -#define CONFIG_CMD_MTDPARTS -#define MTDIDS_DEFAULT "" -#define MTDPARTS_DEFAULT "" -*/ - -#endif /* __CONFIG_H */ diff --git a/include/configs/DK1C20_safe_32.h b/include/configs/DK1C20_safe_32.h deleted file mode 100644 index 86e4869f13..0000000000 --- a/include/configs/DK1C20_safe_32.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * (C) Copyright 2003, Li-Pro.Net - * Stephan Linz - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_DK1C20_SAFE_32_H -#define __CONFIG_DK1C20_SAFE_32_H - -/* - * NIOS CPU configuration. (PART OF configs/DK1C20.h) - * - * !!! TODO !!! TODO !!! - */ -#error *** CONFIG_SYS_ERROR: DK1C20_safe_32 have to be defined (use DK1C20_standard_32 as template) - -#endif /* __CONFIG_DK1C20_SAFE_32_H */ diff --git a/include/configs/DK1C20_standard_32.h b/include/configs/DK1C20_standard_32.h deleted file mode 100644 index c08aaae019..0000000000 --- a/include/configs/DK1C20_standard_32.h +++ /dev/null @@ -1,279 +0,0 @@ -/* - * (C) Copyright 2003, Li-Pro.Net - * Stephan Linz - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_DK1C20_STANDARD_32_H -#define __CONFIG_DK1C20_STANDARD_32_H - -/* - * NIOS CPU configuration. (PART OF configs/DK1C20.h) - * - * Here we must define CPU dependencies. Any unsupported option have to - * be defined with zero, example CPU without data cache / OCI: - * - * #define CONFIG_SYS_NIOS_CPU_ICACHE 4096 - * #define CONFIG_SYS_NIOS_CPU_DCACHE 0 - * #define CONFIG_SYS_NIOS_CPU_OCI_BASE 0 - * #define CONFIG_SYS_NIOS_CPU_OCI_SIZE 0 - */ - -/* CPU core */ -#define CONFIG_SYS_NIOS_CPU_CLK 50000000 /* NIOS CPU clock */ -#define CONFIG_SYS_NIOS_CPU_ICACHE (4 * 1024) /* instruction cache */ -#define CONFIG_SYS_NIOS_CPU_DCACHE (4 * 1024) /* data cache */ -#define CONFIG_SYS_NIOS_CPU_REG_NUMS 256 /* number of register */ -#define CONFIG_SYS_NIOS_CPU_MUL 0 /* 16x16 MUL: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_MSTEP 1 /* 16x16 MSTEP: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_STACK 0x008fff00 /* stack top addr */ -#define CONFIG_SYS_NIOS_CPU_VEC_BASE 0x008fff00 /* IRQ vectors addr */ -#define CONFIG_SYS_NIOS_CPU_VEC_SIZE 256 /* size */ -#define CONFIG_SYS_NIOS_CPU_VEC_NUMS 64 /* numbers */ -#define CONFIG_SYS_NIOS_CPU_RST_VECT 0x00920000 /* RESET vector addr */ -#define CONFIG_SYS_NIOS_CPU_DBG_CORE 0 /* CPU debug: no(0) */ - /* yes(1) */ - -/* on-chip extensions */ -#define CONFIG_SYS_NIOS_CPU_RAM_BASE 0 /* on chip RAM addr */ -#define CONFIG_SYS_NIOS_CPU_RAM_SIZE 0 /* size */ - -#define CONFIG_SYS_NIOS_CPU_ROM_BASE 0x00920000 /* on chip ROM addr */ -#define CONFIG_SYS_NIOS_CPU_ROM_SIZE (2 * 1024) /* 2 KB size */ - -#define CONFIG_SYS_NIOS_CPU_OCI_BASE 0x00920800 /* OCI core addr */ -#define CONFIG_SYS_NIOS_CPU_OCI_SIZE 256 /* size */ - -/* timer */ -#define CONFIG_SYS_NIOS_CPU_TIMER_NUMS 2 /* number of timer */ - -#define CONFIG_SYS_NIOS_CPU_TIMER0 0x00920940 /* TIMER0 addr */ -#define CONFIG_SYS_NIOS_CPU_TIMER0_IRQ 16 /* IRQ */ -#define CONFIG_SYS_NIOS_CPU_TIMER0_PER 1000 /* periode usec */ -#define CONFIG_SYS_NIOS_CPU_TIMER0_AR 0 /* always run: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_TIMER0_FP 0 /* fixed per: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_TIMER0_SS 1 /* snaphot: no(0) */ - /* yes(1) */ - -#define CONFIG_SYS_NIOS_CPU_TIMER1 0x009209e0 /* TIMER1 addr */ -#define CONFIG_SYS_NIOS_CPU_TIMER1_IRQ 50 /* IRQ */ -#define CONFIG_SYS_NIOS_CPU_TIMER1_PER 10000 /* periode usec */ -#define CONFIG_SYS_NIOS_CPU_TIMER1_AR 1 /* always run: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_TIMER1_FP 1 /* fixed per: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_TIMER1_SS 0 /* snaphot: no(0) */ - /* yes(1) */ - -/* serial i/o */ -#define CONFIG_SYS_NIOS_CPU_UART_NUMS 1 /* number of uarts */ - -#define CONFIG_SYS_NIOS_CPU_UART0 0x00920900 /* UART0 addr */ -#define CONFIG_SYS_NIOS_CPU_UART0_IRQ 25 /* IRQ */ -#define CONFIG_SYS_NIOS_CPU_UART0_BR 115200 /* baudrate var(0) */ -#define CONFIG_SYS_NIOS_CPU_UART0_DB 8 /* data bit */ -#define CONFIG_SYS_NIOS_CPU_UART0_SB 1 /* stop bit */ -#define CONFIG_SYS_NIOS_CPU_UART0_PA 0 /* parity none(0) */ - /* odd(1) */ - /* even(2) */ -#define CONFIG_SYS_NIOS_CPU_UART0_HS 0 /* handshake: no(0) */ - /* crts(1) */ -#define CONFIG_SYS_NIOS_CPU_UART0_EOP 0 /* eop reg: no(0) */ - /* yes(1) */ - -/* parallel i/o */ -#define CONFIG_SYS_NIOS_CPU_PIO_NUMS 8 /* number of parports */ - -#define CONFIG_SYS_NIOS_CPU_PIO0 0x00920960 /* PIO0 addr */ -#define CONFIG_SYS_NIOS_CPU_PIO0_IRQ 40 /* IRQ */ -#define CONFIG_SYS_NIOS_CPU_PIO0_BITS 4 /* number of bits */ -#define CONFIG_SYS_NIOS_CPU_PIO0_TYPE 2 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CONFIG_SYS_NIOS_CPU_PIO0_CAP 1 /* capture: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_PIO0_EDGE 3 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CONFIG_SYS_NIOS_CPU_PIO0_ITYPE 2 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CONFIG_SYS_NIOS_CPU_PIO1 0x00920970 /* PIO1 addr */ -#undef CONFIG_SYS_NIOS_CPU_PIO1_IRQ /* w/o IRQ */ -#define CONFIG_SYS_NIOS_CPU_PIO1_BITS 11 /* number of bits */ -#define CONFIG_SYS_NIOS_CPU_PIO1_TYPE 0 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CONFIG_SYS_NIOS_CPU_PIO1_CAP 0 /* capture: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_PIO1_EDGE 0 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CONFIG_SYS_NIOS_CPU_PIO1_ITYPE 0 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CONFIG_SYS_NIOS_CPU_PIO2 0x00920980 /* PIO2 addr */ -#undef CONFIG_SYS_NIOS_CPU_PIO2_IRQ /* w/o IRQ */ -#define CONFIG_SYS_NIOS_CPU_PIO2_BITS 8 /* number of bits */ -#define CONFIG_SYS_NIOS_CPU_PIO2_TYPE 1 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CONFIG_SYS_NIOS_CPU_PIO2_CAP 0 /* capture: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_PIO2_EDGE 0 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CONFIG_SYS_NIOS_CPU_PIO2_ITYPE 0 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CONFIG_SYS_NIOS_CPU_PIO3 0x00920990 /* PIO3 addr */ -#undef CONFIG_SYS_NIOS_CPU_PIO3_IRQ /* w/o IRQ */ -#define CONFIG_SYS_NIOS_CPU_PIO3_BITS 16 /* number of bits */ -#define CONFIG_SYS_NIOS_CPU_PIO3_TYPE 1 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CONFIG_SYS_NIOS_CPU_PIO3_CAP 0 /* capture: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_PIO3_EDGE 0 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CONFIG_SYS_NIOS_CPU_PIO3_ITYPE 0 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CONFIG_SYS_NIOS_CPU_PIO4 0x009209a0 /* PIO4 addr */ -#undef CONFIG_SYS_NIOS_CPU_PIO4_IRQ /* w/o IRQ */ -#define CONFIG_SYS_NIOS_CPU_PIO4_BITS 1 /* number of bits */ -#define CONFIG_SYS_NIOS_CPU_PIO4_TYPE 0 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CONFIG_SYS_NIOS_CPU_PIO4_CAP 0 /* capture: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_PIO4_EDGE 0 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CONFIG_SYS_NIOS_CPU_PIO4_ITYPE 0 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CONFIG_SYS_NIOS_CPU_PIO5 0x009209b0 /* PIO5 addr */ -#define CONFIG_SYS_NIOS_CPU_PIO5_IRQ 35 /* IRQ */ -#define CONFIG_SYS_NIOS_CPU_PIO5_BITS 1 /* number of bits */ -#define CONFIG_SYS_NIOS_CPU_PIO5_TYPE 2 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CONFIG_SYS_NIOS_CPU_PIO5_CAP 1 /* capture: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_PIO5_EDGE 3 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CONFIG_SYS_NIOS_CPU_PIO5_ITYPE 2 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CONFIG_SYS_NIOS_CPU_PIO6 0x009209c0 /* PIO6 addr */ -#undef CONFIG_SYS_NIOS_CPU_PIO6_IRQ /* w/o IRQ */ -#define CONFIG_SYS_NIOS_CPU_PIO6_BITS 1 /* number of bits */ -#define CONFIG_SYS_NIOS_CPU_PIO6_TYPE 1 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CONFIG_SYS_NIOS_CPU_PIO6_CAP 0 /* capture: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_PIO6_EDGE 0 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CONFIG_SYS_NIOS_CPU_PIO6_ITYPE 0 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CONFIG_SYS_NIOS_CPU_PIO7 0x009209d0 /* PIO7 addr */ -#undef CONFIG_SYS_NIOS_CPU_PIO7_IRQ /* w/o IRQ */ -#define CONFIG_SYS_NIOS_CPU_PIO7_BITS 1 /* number of bits */ -#define CONFIG_SYS_NIOS_CPU_PIO7_TYPE 1 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CONFIG_SYS_NIOS_CPU_PIO7_CAP 0 /* capture: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_PIO7_EDGE 0 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CONFIG_SYS_NIOS_CPU_PIO7_ITYPE 0 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -/* IDE i/f */ -#define CONFIG_SYS_NIOS_CPU_IDE_NUMS 1 /* number of IDE contr. */ -#define CONFIG_SYS_NIOS_CPU_IDE0 0x00920a00 /* IDE0 addr */ - -/* active serial memory i/f */ -#define CONFIG_SYS_NIOS_CPU_ASMI_NUMS 1 /* number of ASMI */ -#define CONFIG_SYS_NIOS_CPU_ASMI0 0x00920b00 /* ASMI0 addr */ -#define CONFIG_SYS_NIOS_CPU_ASMI0_IRQ 45 /* IRQ */ - -/* memory accessibility */ -#define CONFIG_SYS_NIOS_CPU_SRAM_BASE 0x00800000 /* board SRAM addr */ -#define CONFIG_SYS_NIOS_CPU_SRAM_SIZE (1024 * 1024) /* 1 MB size */ - -#define CONFIG_SYS_NIOS_CPU_SDRAM_BASE 0x01000000 /* board SDRAM addr */ -#define CONFIG_SYS_NIOS_CPU_SDRAM_SIZE (16*1024*1024) /* 16 MB size */ - -#define CONFIG_SYS_NIOS_CPU_FLASH_BASE 0x00000000 /* board Flash addr */ -#define CONFIG_SYS_NIOS_CPU_FLASH_SIZE (8*1024*1024) /* 8 MB size */ - -/* LAN */ -#define CONFIG_SYS_NIOS_CPU_LAN_NUMS 1 /* number of LAN i/f */ - -#define CONFIG_SYS_NIOS_CPU_LAN0_BASE 0x00910000 /* LAN0 addr */ -#define CONFIG_SYS_NIOS_CPU_LAN0_OFFS 0x0300 /* offset */ -#define CONFIG_SYS_NIOS_CPU_LAN0_IRQ 30 /* IRQ */ -#define CONFIG_SYS_NIOS_CPU_LAN0_BUSW 32 /* buswidth*/ -#define CONFIG_SYS_NIOS_CPU_LAN0_TYPE 0 /* smc91111(0) */ - /* cs8900(1) */ - /* ex: alteramac(2) */ - -/* symbolic redefinition (undef, if not present) */ -#define CONFIG_SYS_NIOS_CPU_USER_TIMER 0 /* TIMER0: users choice */ -#define CONFIG_SYS_NIOS_CPU_TICK_TIMER 1 /* TIMER1: tick (needed)*/ - -#define CONFIG_SYS_NIOS_CPU_BUTTON_PIO 0 /* PIO0: buttons */ -#define CONFIG_SYS_NIOS_CPU_LCD_PIO 1 /* PIO1: ASCII LCD */ -#define CONFIG_SYS_NIOS_CPU_LED_PIO 2 /* PIO2: LED bar */ -#define CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO 3 /* PIO3: 7-seg. display */ -#define CONFIG_SYS_NIOS_CPU_RECONF_PIO 4 /* PIO4: reconf pin */ -#define CONFIG_SYS_NIOS_CPU_CFPRESENT_PIO 5 /* PIO5: CF present IRQ */ -#define CONFIG_SYS_NIOS_CPU_CFPOWER_PIO 6 /* PIO6: CF power/sw. */ -#define CONFIG_SYS_NIOS_CPU_CFATASEL_PIO 7 /* PIO7: CF ATA select */ - -#endif /* __CONFIG_DK1C20_STANDARD_32_H */ diff --git a/include/configs/DK1S10.h b/include/configs/DK1S10.h deleted file mode 100644 index 6e788610fd..0000000000 --- a/include/configs/DK1S10.h +++ /dev/null @@ -1,561 +0,0 @@ -/* - * (C) Copyright 2003, Li-Pro.Net - * Stephan Linz - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/*********************************************************************** - * Include the whole NIOS CPU configuration. - * - * !!! HAVE TO BE HERE !!! DON'T MOVE THIS PART !!! - * - ***********************************************************************/ - -#if defined(CONFIG_NIOS_SAFE_32) -#include -#elif defined(CONFIG_NIOS_STANDARD_32) -#include -#elif defined(CONFIG_NIOS_MTX_LDK_20) -#include -#else -#error *** CONFIG_SYS_ERROR: you have to setup right NIOS CPU configuration -#endif - -/*------------------------------------------------------------------------ - * BOARD/CPU -- TOP-LEVEL - *----------------------------------------------------------------------*/ -#define CONFIG_NIOS 1 /* NIOS-32 core */ -#define CONFIG_DK1S10 1 /* Stratix DK-1S10 board*/ -#define CONFIG_SYS_CLK_FREQ CONFIG_SYS_NIOS_CPU_CLK/* 50 MHz core clock */ -#define CONFIG_SYS_HZ 1000 /* 1 msec time tick */ -#define CONFIG_BOARD_EARLY_INIT_F 1 /* enable early board-spec. init*/ - -/*------------------------------------------------------------------------ - * BASE ADDRESSES / SIZE (Flash, SRAM, SDRAM) - *----------------------------------------------------------------------*/ -#if (CONFIG_SYS_NIOS_CPU_SDRAM_SIZE != 0) - -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_NIOS_CPU_SDRAM_BASE -#define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_NIOS_CPU_SDRAM_SIZE - -#else -#error *** CONFIG_SYS_ERROR: you have to setup any SDRAM in NIOS CPU config -#endif - -#if defined(CONFIG_SYS_NIOS_CPU_SRAM_BASE) && defined(CONFIG_SYS_NIOS_CPU_SRAM_SIZE) - -#define CONFIG_SYS_SRAM_BASE CONFIG_SYS_NIOS_CPU_SRAM_BASE -#define CONFIG_SYS_SRAM_SIZE CONFIG_SYS_NIOS_CPU_SRAM_SIZE - -#else - -#undef CONFIG_SYS_SRAM_BASE -#undef CONFIG_SYS_SRAM_SIZE - -#endif - -#define CONFIG_SYS_VECT_BASE CONFIG_SYS_NIOS_CPU_VEC_BASE - -/*------------------------------------------------------------------------ - * MEMORY ORGANIZATION - For the most part, you can put things pretty - * much anywhere. This is pretty flexible for Nios. So here we make some - * arbitrary choices & assume that the monitor is placed at the end of - * a memory resource (so you must make sure TEXT_BASE is chosen - * appropriately). - * - * -The heap is placed below the monitor. - * -Global data is placed below the heap. - * -The stack is placed below global data (&grows down). - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256k */ -#define CONFIG_SYS_GBL_DATA_SIZE 128 /* Global data size rsvd*/ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) - -#define CONFIG_SYS_MONITOR_BASE TEXT_BASE -#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN) -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_MALLOC_BASE - CONFIG_SYS_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP CONFIG_SYS_GBL_DATA_OFFSET - -/*------------------------------------------------------------------------ - * FLASH (AM29LV065D) - *----------------------------------------------------------------------*/ -#if (CONFIG_SYS_NIOS_CPU_FLASH_SIZE != 0) - -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_NIOS_CPU_FLASH_BASE -#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_NIOS_CPU_FLASH_SIZE -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* Max # sects per bank */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max # of flash banks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Erase timeout (msec) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 100 /* Write timeout (msec) */ -#define CONFIG_SYS_FLASH_WORD_SIZE unsigned char /* flash word size */ - -#else -#error *** CONFIG_SYS_ERROR: you have to setup any Flash memory in NIOS CPU config -#endif - -/*------------------------------------------------------------------------ - * ENVIRONMENT - *----------------------------------------------------------------------*/ -#if (CONFIG_SYS_NIOS_CPU_FLASH_SIZE != 0) - -#define CONFIG_ENV_IS_IN_FLASH 1 /* Environment in flash */ - -#if defined(CONFIG_NIOS_STANDARD_32) -#define CONFIG_ENV_ADDR CONFIG_SYS_FLASH_BASE /* Mem addr of env */ -#elif defined(CONFIG_NIOS_MTX_LDK_20) -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) -#else -#error *** CONFIG_SYS_ERROR: you have to setup the environment base address CONFIG_ENV_ADDR -#endif - -#define CONFIG_ENV_SIZE (64 * 1024) /* 64 KByte (1 sector) */ -#define CONFIG_ENV_OVERWRITE /* Serial/eth change Ok */ - -#else -#define CONFIG_ENV_IS_NOWHERE 1 /* NO Environment */ -#endif - -/*------------------------------------------------------------------------ - * CONSOLE - *----------------------------------------------------------------------*/ -#if (CONFIG_SYS_NIOS_CPU_UART_NUMS != 0) - -#define CONFIG_SYS_NIOS_CONSOLE CONFIG_SYS_NIOS_CPU_UART0 /* 1st UART is Cons. */ -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ - -#if (CONFIG_SYS_NIOS_CPU_UART0_BR != 0) -#define CONFIG_SYS_NIOS_FIXEDBAUD 1 /* Baudrate is fixed */ -#define CONFIG_BAUDRATE CONFIG_SYS_NIOS_CPU_UART0_BR -#else -#undef CONFIG_SYS_NIOS_FIXEDBAUD -#define CONFIG_BAUDRATE 115200 -#endif - -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -#else -#error *** CONFIG_SYS_ERROR: you have to setup at least one UART in NIOS CPU config -#endif - -/*------------------------------------------------------------------------ - * TIMER FOR TIMEBASE -- Nios doesn't have the equivalent of ppc PIT, - * so an avalon bus timer is required. - *----------------------------------------------------------------------*/ -#if (CONFIG_SYS_NIOS_CPU_TIMER_NUMS != 0) && defined(CONFIG_SYS_NIOS_CPU_TICK_TIMER) - -#if (CONFIG_SYS_NIOS_CPU_TICK_TIMER == 0) - -#define CONFIG_SYS_NIOS_TMRBASE CONFIG_SYS_NIOS_CPU_TIMER0 /* TIMER0 as tick */ -#define CONFIG_SYS_NIOS_TMRIRQ CONFIG_SYS_NIOS_CPU_TIMER0_IRQ - -#if (CONFIG_SYS_NIOS_CPU_TIMER0_FP == 1) /* fixed period */ - -#if (CONFIG_SYS_NIOS_CPU_TIMER0_PER >= CONFIG_SYS_HZ) -#define CONFIG_SYS_NIOS_TMRMS (CONFIG_SYS_NIOS_CPU_TIMER0_PER / CONFIG_SYS_HZ) -#else -#error *** CONFIG_SYS_ERROR: you have to use a timer periode greater than CONFIG_SYS_HZ -#endif - -#undef CONFIG_SYS_NIOS_TMRCNT /* no preloadable counter value */ - -#elif (CONFIG_SYS_NIOS_CPU_TIMER0_FP == 0) /* variable period */ - -#if (CONFIG_SYS_HZ <= 1000) -#define CONFIG_SYS_NIOS_TMRMS (1000 / CONFIG_SYS_HZ) -#else -#error *** CONFIG_SYS_ERROR: sorry, CONFIG_SYS_HZ have to be less than 1000 -#endif - -#define CONFIG_SYS_NIOS_TMRCNT (CONFIG_SYS_CLK_FREQ / CONFIG_SYS_HZ) - -#else -#error *** CONFIG_SYS_ERROR: you have to define CONFIG_SYS_NIOS_CPU_TIMER0_FP correct -#endif - -#elif (CONFIG_SYS_NIOS_CPU_TICK_TIMER == 1) - -#define CONFIG_SYS_NIOS_TMRBASE CONFIG_SYS_NIOS_CPU_TIMER1 /* TIMER1 as tick */ -#define CONFIG_SYS_NIOS_TMRIRQ CONFIG_SYS_NIOS_CPU_TIMER1_IRQ - -#if (CONFIG_SYS_NIOS_CPU_TIMER1_FP == 1) /* fixed period */ - -#if (CONFIG_SYS_NIOS_CPU_TIMER1_PER >= CONFIG_SYS_HZ) -#define CONFIG_SYS_NIOS_TMRMS (CONFIG_SYS_NIOS_CPU_TIMER1_PER / CONFIG_SYS_HZ) -#else -#error *** CONFIG_SYS_ERROR: you have to use a timer periode greater than CONFIG_SYS_HZ -#endif - -#undef CONFIG_SYS_NIOS_TMRCNT /* no preloadable counter value */ - -#elif (CONFIG_SYS_NIOS_CPU_TIMER1_FP == 0) /* variable period */ - -#if (CONFIG_SYS_HZ <= 1000) -#define CONFIG_SYS_NIOS_TMRMS (1000 / CONFIG_SYS_HZ) -#else -#error *** CONFIG_SYS_ERROR: sorry, CONFIG_SYS_HZ have to be less than 1000 -#endif - -#define CONFIG_SYS_NIOS_TMRCNT (CONFIG_SYS_CLK_FREQ / CONFIG_SYS_HZ) - -#else -#error *** CONFIG_SYS_ERROR: you have to define CONFIG_SYS_NIOS_CPU_TIMER1_FP correct -#endif - -#endif /* CONFIG_SYS_NIOS_CPU_TICK_TIMER */ - -#else -#error *** CONFIG_SYS_ERROR: you have to setup at least one TIMER in NIOS CPU config -#endif - -/*------------------------------------------------------------------------ - * Ethernet -- needs work! - *----------------------------------------------------------------------*/ -#if (CONFIG_SYS_NIOS_CPU_LAN_NUMS == 1) - -#if (CONFIG_SYS_NIOS_CPU_LAN0_TYPE == 0) /* LAN91C111 */ - -#define CONFIG_DRIVER_SMC91111 /* Using SMC91c111 */ -#undef CONFIG_SMC91111_EXT_PHY /* Internal PHY */ -#define CONFIG_SMC91111_BASE (CONFIG_SYS_NIOS_CPU_LAN0_BASE + CONFIG_SYS_NIOS_CPU_LAN0_OFFS) - -#if (CONFIG_SYS_NIOS_CPU_LAN0_BUSW == 32) -#define CONFIG_SMC_USE_32_BIT 1 -#else /* no */ -#undef CONFIG_SMC_USE_32_BIT -#endif - -#elif (CONFIG_SYS_NIOS_CPU_LAN0_TYPE == 1) /* CS8900A */ - - /********************************************/ - /* !!! CS8900 is __not__ tested on NIOS !!! */ - /********************************************/ -#define CONFIG_NET_MULTI -#define CONFIG_CS8900 /* Using CS8900 */ -#define CONFIG_CS8900_BASE (CONFIG_SYS_NIOS_CPU_LAN0_BASE + \ - CONFIG_SYS_NIOS_CPU_LAN0_OFFS) - -#if (CONFIG_SYS_NIOS_CPU_LAN0_BUSW == 32) -#undef CONFIG_CS8900_BUS16 -#define CONFIG_CS8900_BUS32 -#else /* no */ -#define CONFIG_CS8900_BUS16 -#undef CONFIG_CS8900_BUS32 -#endif - -#else -#error *** CONFIG_SYS_ERROR: invalid LAN0 chip type, check your NIOS CPU config -#endif - -#define CONFIG_ETHADDR 08:00:3e:26:0a:5b -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_IPADDR 192.168.2.21 -#define CONFIG_SERVERIP 192.168.2.16 - -#else -#error *** CONFIG_SYS_ERROR: you have to setup just one LAN only or expand your config.h -#endif - -/*------------------------------------------------------------------------ - * STATUS LEDs - *----------------------------------------------------------------------*/ -#if (CONFIG_SYS_NIOS_CPU_PIO_NUMS != 0) && defined(CONFIG_SYS_NIOS_CPU_LED_PIO) - -#if (CONFIG_SYS_NIOS_CPU_LED_PIO == 0) - -#error *** CONFIG_SYS_ERROR: status LEDs at PIO0 not supported, expand your config.h - -#elif (CONFIG_SYS_NIOS_CPU_LED_PIO == 1) - -#error *** CONFIG_SYS_ERROR: status LEDs at PIO1 not supported, expand your config.h - -#elif (CONFIG_SYS_NIOS_CPU_LED_PIO == 2) - -#define STATUS_LED_BASE CONFIG_SYS_NIOS_CPU_PIO2 -#define STATUS_LED_BITS CONFIG_SYS_NIOS_CPU_PIO2_BITS -#define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */ - -#if (CONFIG_SYS_NIOS_CPU_PIO2_TYPE == 1) -#define STATUS_LED_WRONLY 1 -#else -#undef STATUS_LED_WRONLY -#endif - -#elif (CONFIG_SYS_NIOS_CPU_LED_PIO == 3) - -#error *** CONFIG_SYS_ERROR: status LEDs at PIO3 not supported, expand your config.h - -#elif (CONFIG_SYS_NIOS_CPU_LED_PIO == 4) - -#error *** CONFIG_SYS_ERROR: status LEDs at PIO4 not supported, expand your config.h - -#elif (CONFIG_SYS_NIOS_CPU_LED_PIO == 5) - -#error *** CONFIG_SYS_ERROR: status LEDs at PIO5 not supported, expand your config.h - -#elif (CONFIG_SYS_NIOS_CPU_LED_PIO == 6) - -#error *** CONFIG_SYS_ERROR: status LEDs at PIO6 not supported, expand your config.h - -#elif (CONFIG_SYS_NIOS_CPU_LED_PIO == 7) - -#error *** CONFIG_SYS_ERROR: status LEDs at PIO7 not supported, expand your config.h - -#elif (CONFIG_SYS_NIOS_CPU_LED_PIO == 8) - -#error *** CONFIG_SYS_ERROR: status LEDs at PIO8 not supported, expand your config.h - -#elif (CONFIG_SYS_NIOS_CPU_LED_PIO == 9) - -#error *** CONFIG_SYS_ERROR: status LEDs at PIO9 not supported, expand your config.h - -#else -#error *** CONFIG_SYS_ERROR: you have to set CONFIG_SYS_NIOS_CPU_LED_PIO in right case -#endif - -#define CONFIG_STATUS_LED 1 /* enable status led driver */ - -#define STATUS_LED_BIT (1 << 0) /* LED[0] */ -#define STATUS_LED_STATE STATUS_LED_BLINKING -#define STATUS_LED_BOOT_STATE STATUS_LED_OFF -#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 10) /* ca. 1 Hz */ -#define STATUS_LED_BOOT 0 /* boot LED */ - -#if (STATUS_LED_BITS > 1) -#define STATUS_LED_BIT1 (1 << 1) /* LED[1] */ -#define STATUS_LED_STATE1 STATUS_LED_OFF -#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 50) /* ca. 5 Hz */ -#define STATUS_LED_RED 1 /* fail LED */ -#endif - -#if (STATUS_LED_BITS > 2) -#define STATUS_LED_BIT2 (1 << 2) /* LED[2] */ -#define STATUS_LED_STATE2 STATUS_LED_OFF -#define STATUS_LED_PERIOD2 (CONFIG_SYS_HZ / 10) /* ca. 1 Hz */ -#define STATUS_LED_YELLOW 2 /* info LED */ -#endif - -#if (STATUS_LED_BITS > 3) -#define STATUS_LED_BIT3 (1 << 3) /* LED[3] */ -#define STATUS_LED_STATE3 STATUS_LED_OFF -#define STATUS_LED_PERIOD3 (CONFIG_SYS_HZ / 10) /* ca. 1 Hz */ -#define STATUS_LED_GREEN 3 /* info LED */ -#endif - -#define STATUS_LED_PAR 1 /* makes status_led.h happy */ - -#endif /* CONFIG_SYS_NIOS_CPU_PIO_NUMS */ - -/*------------------------------------------------------------------------ - * SEVEN SEGMENT LED DISPLAY - *----------------------------------------------------------------------*/ -#if (CONFIG_SYS_NIOS_CPU_PIO_NUMS != 0) && defined(CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO) - -#if (CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO == 0) - -#error *** CONFIG_SYS_ERROR: seven segment display at PIO0 not supported, expand your config.h - -#elif (CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO == 1) - -#error *** CONFIG_SYS_ERROR: seven segment display at PIO1 not supported, expand your config.h - -#elif (CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO == 2) - -#error *** CONFIG_SYS_ERROR: seven segment display at PIO2 not supported, expand your config.h - -#elif (CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO == 3) - -#define SEVENSEG_BASE CONFIG_SYS_NIOS_CPU_PIO3 -#define SEVENSEG_BITS CONFIG_SYS_NIOS_CPU_PIO3_BITS -#define SEVENSEG_ACTIVE 0 /* LED on for bit == 1 */ - -#if (CONFIG_SYS_NIOS_CPU_PIO3_TYPE == 1) -#define SEVENSEG_WRONLY 1 -#else -#undef SEVENSEG_WRONLY -#endif - -#elif (CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO == 4) - -#error *** CONFIG_SYS_ERROR: seven segment display at PIO4 not supported, expand your config.h - -#elif (CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO == 5) - -#error *** CONFIG_SYS_ERROR: seven segment display at PIO5 not supported, expand your config.h - -#elif (CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO == 6) - -#error *** CONFIG_SYS_ERROR: seven segment display at PIO6 not supported, expand your config.h - -#elif (CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO == 7) - -#error *** CONFIG_SYS_ERROR: seven segment display at PIO7 not supported, expand your config.h - -#elif (CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO == 8) - -#error *** CONFIG_SYS_ERROR: seven segment display at PIO8 not supported, expand your config.h - -#elif (CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO == 9) - -#error *** CONFIG_SYS_ERROR: seven segment display at PIO9 not supported, expand your config.h - -#else -#error *** CONFIG_SYS_ERROR: you have to set CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO in right case -#endif - -#define CONFIG_SEVENSEG 1 /* enable seven segment led driver */ - -/* - * Dual 7-Segment Display pin assignment -- read more in your - * "Nios Development Board Reference Manual" - * - * - * (U8) HI:D[15..8] (U9) LO:D[7..0] - * ______ ______ - * | D14 | | D6 | - * | | | | - * D9| |D13 D1| |D5 - * |______| |______| ___ - * | D8 | | D0 | | A | - * | | | | F|___|B - * D10| |D12 D2| |D4 | G | - * |______| |______| E|___|C - * D11 * D3 * D * - * D15 D7 DP - * - */ -#define SEVENSEG_DIGIT_HI_LO_EQUAL 1 /* high nibble equal low nibble */ -#define SEVENSEG_DIGIT_A (1 << 6) /* bit 6 is segment A */ -#define SEVENSEG_DIGIT_B (1 << 5) /* bit 5 is segment B */ -#define SEVENSEG_DIGIT_C (1 << 4) /* bit 4 is segment C */ -#define SEVENSEG_DIGIT_D (1 << 3) /* bit 3 is segment D */ -#define SEVENSEG_DIGIT_E (1 << 2) /* bit 2 is segment E */ -#define SEVENSEG_DIGIT_F (1 << 1) /* bit 1 is segment F */ -#define SEVENSEG_DIGIT_G (1 << 0) /* bit 0 is segment G */ -#define SEVENSEG_DIGIT_DP (1 << 7) /* bit 7 is decimal point */ - -#endif /* CONFIG_SYS_NIOS_CPU_PIO_NUMS */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_CDP -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_DISPLAY -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_IMMAP -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_PING -#define CONFIG_CMD_PORTIO -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_REISER -#define CONFIG_CMD_SAVES -#define CONFIG_CMD_SDRAM -#define CONFIG_CMD_SNTP - -#undef CONFIG_CMD_NFS -#undef CONFIG_CMD_XIMG - -/*------------------------------------------------------------------------ - * KGDB - *----------------------------------------------------------------------*/ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 9600 -#endif - -/*------------------------------------------------------------------------ - * MISC - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "DK1S10 > " /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args*/ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -/* Default load address */ -#if (CONFIG_SYS_SRAM_SIZE != 0) - -/* default in SRAM */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SRAM_BASE - -#elif (CONFIG_SYS_SDRAM_SIZE != 0) - -/* default in SDRAM */ -#if (CONFIG_SYS_SDRAM_BASE == CONFIG_SYS_NIOS_CPU_VEC_BASE) -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_NIOS_CPU_VEC_SIZE) -#else -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE -#endif - -#else -#undef CONFIG_SYS_LOAD_ADDR /* force error break */ -#endif - - -/* MEM test area */ -#if (CONFIG_SYS_SDRAM_SIZE != 0) - -/* SDRAM begin to stack area (1MB stack) */ -#if (CONFIG_SYS_SDRAM_BASE == CONFIG_SYS_NIOS_CPU_VEC_BASE) -#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_NIOS_CPU_VEC_SIZE) -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_INIT_SP - (1024 * 1024)) -#else -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_INIT_SP - (1024 * 1024)) -#endif - -#else -#undef CONFIG_SYS_MEMTEST_START /* force error break */ -#undef CONFIG_SYS_MEMTEST_END -#endif - -/* - * JFFS2 partitions - * - */ -/* No command line, one static partition, whole device */ -#undef CONFIG_CMD_MTDPARTS -#define CONFIG_JFFS2_DEV "nor0" -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 - -/* mtdparts command line support */ -/* -#define CONFIG_CMD_MTDPARTS -#define MTDIDS_DEFAULT "" -#define MTDPARTS_DEFAULT "" -*/ - -#endif /* __CONFIG_H */ diff --git a/include/configs/DK1S10_mtx_ldk_20.h b/include/configs/DK1S10_mtx_ldk_20.h deleted file mode 100644 index 87a8a54380..0000000000 --- a/include/configs/DK1S10_mtx_ldk_20.h +++ /dev/null @@ -1,187 +0,0 @@ -/* - * (C) Copyright 2003, Li-Pro.Net - * Stephan Linz - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_DK1S10_MTX_LDK_20_H -#define __CONFIG_DK1S10_MTX_LDK_20_H - -/* - * NIOS CPU configuration. (PART OF configs/DK1S10.h) - * - * Here we must define CPU dependencies. Any unsupported option have to - * be defined with zero, example CPU without data cache / OCI: - * - * #define CONFIG_SYS_NIOS_CPU_ICACHE 4096 - * #define CONFIG_SYS_NIOS_CPU_DCACHE 0 - * #define CONFIG_SYS_NIOS_CPU_OCI_BASE 0 - * #define CONFIG_SYS_NIOS_CPU_OCI_SIZE 0 - */ - -/* CPU core */ -#define CONFIG_SYS_NIOS_CPU_CLK 75000000 /* NIOS CPU clock */ -#define CONFIG_SYS_NIOS_CPU_ICACHE (0) /* instruction cache */ -#define CONFIG_SYS_NIOS_CPU_DCACHE (0) /* data cache */ -#define CONFIG_SYS_NIOS_CPU_REG_NUMS 512 /* number of register */ -#define CONFIG_SYS_NIOS_CPU_MUL 0 /* 16x16 MUL: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_MSTEP 1 /* 16x16 MSTEP: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_STACK 0x02000000 /* stack top addr */ -#define CONFIG_SYS_NIOS_CPU_VEC_BASE 0x01000000 /* IRQ vectors addr */ -#define CONFIG_SYS_NIOS_CPU_VEC_SIZE 256 /* size */ -#define CONFIG_SYS_NIOS_CPU_VEC_NUMS 64 /* numbers */ -#define CONFIG_SYS_NIOS_CPU_RST_VECT 0x00000000 /* RESET vector addr */ -#define CONFIG_SYS_NIOS_CPU_DBG_CORE 0 /* CPU debug: no(0) */ - /* yes(1) */ - -/* The offset address in flash to check for the Nios signature "Ni". - * (see GM_FlashExec in germs_monitor.s) */ -#define CONFIG_SYS_NIOS_CPU_EXES_OFFS 0x0C - -/* on-chip extensions */ -#undef CONFIG_SYS_NIOS_CPU_RAM_BASE /* on chip RAM addr */ -#undef CONFIG_SYS_NIOS_CPU_RAM_SIZE /* 64 KB size */ - -#define CONFIG_SYS_NIOS_CPU_ROM_BASE 0x00000000 /* on chip ROM addr */ -#define CONFIG_SYS_NIOS_CPU_ROM_SIZE (2 * 1024) /* 2 KB size */ - -#undef CONFIG_SYS_NIOS_CPU_OCI_BASE /* OCI core addr */ -#undef CONFIG_SYS_NIOS_CPU_OCI_SIZE /* size */ - -/* timer */ -#define CONFIG_SYS_NIOS_CPU_TIMER_NUMS 1 /* number of timer */ - -#define CONFIG_SYS_NIOS_CPU_TIMER0 0x00000840 /* TIMER0 addr */ -#define CONFIG_SYS_NIOS_CPU_TIMER0_IRQ 16 /* IRQ */ -#define CONFIG_SYS_NIOS_CPU_TIMER0_PER 1000 /* periode usec */ -#define CONFIG_SYS_NIOS_CPU_TIMER0_AR 0 /* always run: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_TIMER0_FP 0 /* fixed per: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_TIMER0_SS 1 /* snaphot: no(0) */ - /* yes(1) */ - -/* serial i/o */ -#define CONFIG_SYS_NIOS_CPU_UART_NUMS 2 /* number of uarts */ - -#define CONFIG_SYS_NIOS_CPU_UART0 0x00000800 /* UART0 addr */ -#define CONFIG_SYS_NIOS_CPU_UART0_IRQ 17 /* IRQ */ -#define CONFIG_SYS_NIOS_CPU_UART0_BR 115200 /* baudrate var(0) */ -#define CONFIG_SYS_NIOS_CPU_UART0_DB 8 /* data bit */ -#define CONFIG_SYS_NIOS_CPU_UART0_SB 2 /* stop bit */ -#define CONFIG_SYS_NIOS_CPU_UART0_PA 0 /* parity none(0) */ - /* odd(1) */ - /* even(2) */ -#define CONFIG_SYS_NIOS_CPU_UART0_HS 0 /* handshake: no(0) */ - /* crts(1) */ -#define CONFIG_SYS_NIOS_CPU_UART0_EOP 0 /* eop reg: no(0) */ - /* yes(1) */ - -#define CONFIG_SYS_NIOS_CPU_UART1 0x000008a0 /* UART1 addr */ -#define CONFIG_SYS_NIOS_CPU_UART1_IRQ 18 /* IRQ */ -#define CONFIG_SYS_NIOS_CPU_UART1_BR 115200 /* baudrate var(0) */ -#define CONFIG_SYS_NIOS_CPU_UART1_DB 8 /* data bit */ -#define CONFIG_SYS_NIOS_CPU_UART1_SB 1 /* stop bit */ -#define CONFIG_SYS_NIOS_CPU_UART1_PA 0 /* parity none(0) */ - /* odd(1) */ - /* even(2) */ -#define CONFIG_SYS_NIOS_CPU_UART1_HS 0 /* handshake: no(0) */ - /* crts(1) */ -#define CONFIG_SYS_NIOS_CPU_UART1_EOP 0 /* eop reg: no(0) */ - /* yes(1) */ - -/* parallel i/o */ -#define CONFIG_SYS_NIOS_CPU_PIO_NUMS 2 /* number of parports */ - -#define CONFIG_SYS_NIOS_CPU_PIO0 0x00000860 /* PIO0 addr */ -#undef CONFIG_SYS_NIOS_CPU_PIO0_IRQ /* w/o IRQ */ -#define CONFIG_SYS_NIOS_CPU_PIO0_BITS 1 /* number of bits */ -#define CONFIG_SYS_NIOS_CPU_PIO0_TYPE 1 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CONFIG_SYS_NIOS_CPU_PIO0_CAP 0 /* capture: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_PIO0_EDGE 0 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CONFIG_SYS_NIOS_CPU_PIO0_ITYPE 0 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CONFIG_SYS_NIOS_CPU_PIO1 0x00000870 /* PIO1 addr */ -#undef CONFIG_SYS_NIOS_CPU_PIO1_IRQ /* w/o IRQ */ -#define CONFIG_SYS_NIOS_CPU_PIO1_BITS 4 /* number of bits */ -#define CONFIG_SYS_NIOS_CPU_PIO1_TYPE 2 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CONFIG_SYS_NIOS_CPU_PIO1_CAP 0 /* capture: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_PIO1_EDGE 0 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CONFIG_SYS_NIOS_CPU_PIO1_ITYPE 0 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -/* IDE i/f */ -#define CONFIG_SYS_NIOS_CPU_IDE_NUMS 1 /* number of IDE contr. */ -#define CONFIG_SYS_NIOS_CPU_IDE0 0x00000900 /* IDE0 addr */ -#define CONFIG_SYS_NIOS_CPU_IDE0_IRQ 25 /* IRQ */ - -/* memory accessibility */ -#undef CONFIG_SYS_NIOS_CPU_SRAM_BASE /* board SRAM addr */ -#undef CONFIG_SYS_NIOS_CPU_SRAM_SIZE /* 1 MB size */ - -#define CONFIG_SYS_NIOS_CPU_SDRAM_BASE 0x01000000 /* board SDRAM addr */ -#define CONFIG_SYS_NIOS_CPU_SDRAM_SIZE (16*1024*1024) /* 16 MB size */ - -#define CONFIG_SYS_NIOS_CPU_FLASH_BASE 0x00800000 /* board Flash addr */ -#define CONFIG_SYS_NIOS_CPU_FLASH_SIZE (8*1024*1024) /* 8 MB size */ - -/* LAN */ -#define CONFIG_SYS_NIOS_CPU_LAN_NUMS 1 /* number of LAN i/f */ - -#define CONFIG_SYS_NIOS_CPU_LAN0_BASE 0x00010000 /* LAN0 addr */ -#define CONFIG_SYS_NIOS_CPU_LAN0_OFFS 0x0300 /* offset */ -#define CONFIG_SYS_NIOS_CPU_LAN0_IRQ 20 /* IRQ */ -#define CONFIG_SYS_NIOS_CPU_LAN0_BUSW 32 /* buswidth*/ -#define CONFIG_SYS_NIOS_CPU_LAN0_TYPE 0 /* smc91111(0) */ - /* cs8900(1) */ - /* ex: openmac(2) */ - /* ex: alteramac(3) */ - -/* symbolic redefinition (undef, if not present) */ -#define CONFIG_SYS_NIOS_CPU_TICK_TIMER 0 /* TIMER0: tick (needed)*/ -#undef CONFIG_SYS_NIOS_CPU_USER_TIMER /* TIMERx: users choice */ - -#define CONFIG_SYS_NIOS_CPU_CFPOWER_PIO 0 /* PIO0: CF power/sw. */ -#define CONFIG_SYS_NIOS_CPU_BUTTON_PIO 1 /* PIO1: buttons */ -#undef CONFIG_SYS_NIOS_CPU_LCD_PIO /* PIOx: ASCII LCD */ -#undef CONFIG_SYS_NIOS_CPU_LED_PIO /* PIOx: LED bar */ -#undef CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO /* PIOx: 7-seg. display */ -#undef CONFIG_SYS_NIOS_CPU_RECONF_PIO /* PIOx: reconf pin */ -#undef CONFIG_SYS_NIOS_CPU_CFPRESENT_PIO /* PIOx: CF present IRQ */ -#undef CONFIG_SYS_NIOS_CPU_CFATASEL_PIO /* PIOx: CF ATA select */ - -#endif /* __CONFIG_DK1S10_MTX_LDK_20_H */ diff --git a/include/configs/DK1S10_safe_32.h b/include/configs/DK1S10_safe_32.h deleted file mode 100644 index ced4ef281c..0000000000 --- a/include/configs/DK1S10_safe_32.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * (C) Copyright 2003, Li-Pro.Net - * Stephan Linz - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_DK1S10_SAFE_32_H -#define __CONFIG_DK1S10_SAFE_32_H - -/* - * NIOS CPU configuration. (PART OF configs/DK1S10.h) - * - * !!! TODO !!! TODO !!! - */ -#error *** CONFIG_SYS_ERROR: DK1S10_safe_32 have to be defined (use DK1S10_standard_32 as template) - -#endif /* __CONFIG_DK1S10_SAFE_32_H */ diff --git a/include/configs/DK1S10_standard_32.h b/include/configs/DK1S10_standard_32.h deleted file mode 100644 index e6ccaf57ab..0000000000 --- a/include/configs/DK1S10_standard_32.h +++ /dev/null @@ -1,274 +0,0 @@ -/* - * (C) Copyright 2003, Li-Pro.Net - * Stephan Linz - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_DK1S10_STANDARD_32_H -#define __CONFIG_DK1S10_STANDARD_32_H - -/* - * NIOS CPU configuration. (PART OF configs/DK1S10.h) - * - * Here we must define CPU dependencies. Any unsupported option have to - * be defined with zero, example CPU without data cache / OCI: - * - * #define CONFIG_SYS_NIOS_CPU_ICACHE 4096 - * #define CONFIG_SYS_NIOS_CPU_DCACHE 0 - * #define CONFIG_SYS_NIOS_CPU_OCI_BASE 0 - * #define CONFIG_SYS_NIOS_CPU_OCI_SIZE 0 - */ - -/* CPU core */ -#define CONFIG_SYS_NIOS_CPU_CLK 50000000 /* NIOS CPU clock */ -#define CONFIG_SYS_NIOS_CPU_ICACHE (4 * 1024) /* instruction cache */ -#define CONFIG_SYS_NIOS_CPU_DCACHE (4 * 1024) /* data cache */ -#define CONFIG_SYS_NIOS_CPU_REG_NUMS 256 /* number of register */ -#define CONFIG_SYS_NIOS_CPU_MUL 0 /* 16x16 MUL: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_MSTEP 1 /* 16x16 MSTEP: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_STACK 0x008fff00 /* stack top addr */ -#define CONFIG_SYS_NIOS_CPU_VEC_BASE 0x008fff00 /* IRQ vectors addr */ -#define CONFIG_SYS_NIOS_CPU_VEC_SIZE 256 /* size */ -#define CONFIG_SYS_NIOS_CPU_VEC_NUMS 64 /* numbers */ -#define CONFIG_SYS_NIOS_CPU_RST_VECT 0x00920000 /* RESET vector addr */ -#define CONFIG_SYS_NIOS_CPU_DBG_CORE 0 /* CPU debug: no(0) */ - /* yes(1) */ - -/* on-chip extensions */ -#define CONFIG_SYS_NIOS_CPU_RAM_BASE 0x00900000 /* on chip RAM addr */ -#define CONFIG_SYS_NIOS_CPU_RAM_SIZE (64 * 1024) /* 64 KB size */ - -#define CONFIG_SYS_NIOS_CPU_ROM_BASE 0x00920000 /* on chip ROM addr */ -#define CONFIG_SYS_NIOS_CPU_ROM_SIZE (2 * 1024) /* 2 KB size */ - -#define CONFIG_SYS_NIOS_CPU_OCI_BASE 0x00920800 /* OCI core addr */ -#define CONFIG_SYS_NIOS_CPU_OCI_SIZE 256 /* size */ - -/* timer */ -#define CONFIG_SYS_NIOS_CPU_TIMER_NUMS 2 /* number of timer */ - -#define CONFIG_SYS_NIOS_CPU_TIMER0 0x00920940 /* TIMER0 addr */ -#define CONFIG_SYS_NIOS_CPU_TIMER0_IRQ 16 /* IRQ */ -#define CONFIG_SYS_NIOS_CPU_TIMER0_PER 1000 /* periode usec */ -#define CONFIG_SYS_NIOS_CPU_TIMER0_AR 0 /* always run: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_TIMER0_FP 0 /* fixed per: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_TIMER0_SS 1 /* snaphot: no(0) */ - /* yes(1) */ - -#define CONFIG_SYS_NIOS_CPU_TIMER1 0x009209e0 /* TIMER1 addr */ -#define CONFIG_SYS_NIOS_CPU_TIMER1_IRQ 50 /* IRQ */ -#define CONFIG_SYS_NIOS_CPU_TIMER1_PER 10000 /* periode usec */ -#define CONFIG_SYS_NIOS_CPU_TIMER1_AR 1 /* always run: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_TIMER1_FP 1 /* fixed per: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_TIMER1_SS 0 /* snaphot: no(0) */ - /* yes(1) */ - -/* serial i/o */ -#define CONFIG_SYS_NIOS_CPU_UART_NUMS 1 /* number of uarts */ - -#define CONFIG_SYS_NIOS_CPU_UART0 0x00920900 /* UART0 addr */ -#define CONFIG_SYS_NIOS_CPU_UART0_IRQ 25 /* IRQ */ -#define CONFIG_SYS_NIOS_CPU_UART0_BR 115200 /* baudrate var(0) */ -#define CONFIG_SYS_NIOS_CPU_UART0_DB 8 /* data bit */ -#define CONFIG_SYS_NIOS_CPU_UART0_SB 1 /* stop bit */ -#define CONFIG_SYS_NIOS_CPU_UART0_PA 0 /* parity none(0) */ - /* odd(1) */ - /* even(2) */ -#define CONFIG_SYS_NIOS_CPU_UART0_HS 0 /* handshake: no(0) */ - /* crts(1) */ -#define CONFIG_SYS_NIOS_CPU_UART0_EOP 0 /* eop reg: no(0) */ - /* yes(1) */ - -/* parallel i/o */ -#define CONFIG_SYS_NIOS_CPU_PIO_NUMS 8 /* number of parports */ - -#define CONFIG_SYS_NIOS_CPU_PIO0 0x00920960 /* PIO0 addr */ -#define CONFIG_SYS_NIOS_CPU_PIO0_IRQ 40 /* IRQ */ -#define CONFIG_SYS_NIOS_CPU_PIO0_BITS 4 /* number of bits */ -#define CONFIG_SYS_NIOS_CPU_PIO0_TYPE 2 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CONFIG_SYS_NIOS_CPU_PIO0_CAP 1 /* capture: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_PIO0_EDGE 3 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CONFIG_SYS_NIOS_CPU_PIO0_ITYPE 2 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CONFIG_SYS_NIOS_CPU_PIO1 0x00920970 /* PIO1 addr */ -#undef CONFIG_SYS_NIOS_CPU_PIO1_IRQ /* w/o IRQ */ -#define CONFIG_SYS_NIOS_CPU_PIO1_BITS 11 /* number of bits */ -#define CONFIG_SYS_NIOS_CPU_PIO1_TYPE 0 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CONFIG_SYS_NIOS_CPU_PIO1_CAP 0 /* capture: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_PIO1_EDGE 0 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CONFIG_SYS_NIOS_CPU_PIO1_ITYPE 0 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CONFIG_SYS_NIOS_CPU_PIO2 0x00920980 /* PIO2 addr */ -#undef CONFIG_SYS_NIOS_CPU_PIO2_IRQ /* w/o IRQ */ -#define CONFIG_SYS_NIOS_CPU_PIO2_BITS 8 /* number of bits */ -#define CONFIG_SYS_NIOS_CPU_PIO2_TYPE 1 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CONFIG_SYS_NIOS_CPU_PIO2_CAP 0 /* capture: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_PIO2_EDGE 0 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CONFIG_SYS_NIOS_CPU_PIO2_ITYPE 0 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CONFIG_SYS_NIOS_CPU_PIO3 0x00920990 /* PIO3 addr */ -#undef CONFIG_SYS_NIOS_CPU_PIO3_IRQ /* w/o IRQ */ -#define CONFIG_SYS_NIOS_CPU_PIO3_BITS 16 /* number of bits */ -#define CONFIG_SYS_NIOS_CPU_PIO3_TYPE 1 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CONFIG_SYS_NIOS_CPU_PIO3_CAP 0 /* capture: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_PIO3_EDGE 0 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CONFIG_SYS_NIOS_CPU_PIO3_ITYPE 0 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CONFIG_SYS_NIOS_CPU_PIO4 0x009209a0 /* PIO4 addr */ -#undef CONFIG_SYS_NIOS_CPU_PIO4_IRQ /* w/o IRQ */ -#define CONFIG_SYS_NIOS_CPU_PIO4_BITS 1 /* number of bits */ -#define CONFIG_SYS_NIOS_CPU_PIO4_TYPE 0 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CONFIG_SYS_NIOS_CPU_PIO4_CAP 0 /* capture: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_PIO4_EDGE 0 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CONFIG_SYS_NIOS_CPU_PIO4_ITYPE 0 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CONFIG_SYS_NIOS_CPU_PIO5 0x009209b0 /* PIO5 addr */ -#define CONFIG_SYS_NIOS_CPU_PIO5_IRQ 35 /* IRQ */ -#define CONFIG_SYS_NIOS_CPU_PIO5_BITS 1 /* number of bits */ -#define CONFIG_SYS_NIOS_CPU_PIO5_TYPE 2 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CONFIG_SYS_NIOS_CPU_PIO5_CAP 1 /* capture: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_PIO5_EDGE 3 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CONFIG_SYS_NIOS_CPU_PIO5_ITYPE 2 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CONFIG_SYS_NIOS_CPU_PIO6 0x009209c0 /* PIO6 addr */ -#undef CONFIG_SYS_NIOS_CPU_PIO6_IRQ /* w/o IRQ */ -#define CONFIG_SYS_NIOS_CPU_PIO6_BITS 1 /* number of bits */ -#define CONFIG_SYS_NIOS_CPU_PIO6_TYPE 1 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CONFIG_SYS_NIOS_CPU_PIO6_CAP 0 /* capture: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_PIO6_EDGE 0 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CONFIG_SYS_NIOS_CPU_PIO6_ITYPE 0 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CONFIG_SYS_NIOS_CPU_PIO7 0x009209d0 /* PIO7 addr */ -#undef CONFIG_SYS_NIOS_CPU_PIO7_IRQ /* w/o IRQ */ -#define CONFIG_SYS_NIOS_CPU_PIO7_BITS 1 /* number of bits */ -#define CONFIG_SYS_NIOS_CPU_PIO7_TYPE 1 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CONFIG_SYS_NIOS_CPU_PIO7_CAP 0 /* capture: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_PIO7_EDGE 0 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CONFIG_SYS_NIOS_CPU_PIO7_ITYPE 0 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -/* IDE i/f */ -#define CONFIG_SYS_NIOS_CPU_IDE_NUMS 1 /* number of IDE contr. */ -#define CONFIG_SYS_NIOS_CPU_IDE0 0x00920a00 /* IDE0 addr */ - -/* memory accessibility */ -#define CONFIG_SYS_NIOS_CPU_SRAM_BASE 0x00800000 /* board SRAM addr */ -#define CONFIG_SYS_NIOS_CPU_SRAM_SIZE (1024 * 1024) /* 1 MB size */ - -#define CONFIG_SYS_NIOS_CPU_SDRAM_BASE 0x01000000 /* board SDRAM addr */ -#define CONFIG_SYS_NIOS_CPU_SDRAM_SIZE (16*1024*1024) /* 16 MB size */ - -#define CONFIG_SYS_NIOS_CPU_FLASH_BASE 0x00000000 /* board Flash addr */ -#define CONFIG_SYS_NIOS_CPU_FLASH_SIZE (8*1024*1024) /* 8 MB size */ - -/* LAN */ -#define CONFIG_SYS_NIOS_CPU_LAN_NUMS 1 /* number of LAN i/f */ - -#define CONFIG_SYS_NIOS_CPU_LAN0_BASE 0x00910000 /* LAN0 addr */ -#define CONFIG_SYS_NIOS_CPU_LAN0_OFFS 0x0300 /* offset */ -#define CONFIG_SYS_NIOS_CPU_LAN0_IRQ 30 /* IRQ */ -#define CONFIG_SYS_NIOS_CPU_LAN0_BUSW 32 /* buswidth*/ -#define CONFIG_SYS_NIOS_CPU_LAN0_TYPE 0 /* smc91111(0) */ - /* cs8900(1) */ - /* ex: alteramac(2) */ - -/* symbolic redefinition (undef, if not present) */ -#define CONFIG_SYS_NIOS_CPU_USER_TIMER 0 /* TIMER0: users choice */ -#define CONFIG_SYS_NIOS_CPU_TICK_TIMER 1 /* TIMER1: tick (needed)*/ - -#define CONFIG_SYS_NIOS_CPU_BUTTON_PIO 0 /* PIO0: buttons */ -#define CONFIG_SYS_NIOS_CPU_LCD_PIO 1 /* PIO1: ASCII LCD */ -#define CONFIG_SYS_NIOS_CPU_LED_PIO 2 /* PIO2: LED bar */ -#define CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO 3 /* PIO3: 7-seg. display */ -#define CONFIG_SYS_NIOS_CPU_RECONF_PIO 4 /* PIO4: reconf pin */ -#define CONFIG_SYS_NIOS_CPU_CFPRESENT_PIO 5 /* PIO5: CF present IRQ */ -#define CONFIG_SYS_NIOS_CPU_CFPOWER_PIO 6 /* PIO6: CF power/sw. */ -#define CONFIG_SYS_NIOS_CPU_CFATASEL_PIO 7 /* PIO7: CF ATA select */ - -#endif /* __CONFIG_DK1S10_STANDARD_32_H */ diff --git a/include/image.h b/include/image.h index 541cac97fe..294eba5094 100644 --- a/include/image.h +++ b/include/image.h @@ -100,7 +100,6 @@ #define IH_ARCH_SPARC 10 /* Sparc */ #define IH_ARCH_SPARC64 11 /* Sparc 64 Bit */ #define IH_ARCH_M68K 12 /* M68K */ -#define IH_ARCH_NIOS 13 /* Nios-32 */ #define IH_ARCH_MICROBLAZE 14 /* MicroBlaze */ #define IH_ARCH_NIOS2 15 /* Nios-II */ #define IH_ARCH_BLACKFIN 16 /* Blackfin */ @@ -493,8 +492,6 @@ static inline int image_check_target_arch (const image_header_t *hdr) if (!image_check_arch (hdr, IH_ARCH_MICROBLAZE)) #elif defined(__mips__) if (!image_check_arch (hdr, IH_ARCH_MIPS)) -#elif defined(__nios__) - if (!image_check_arch (hdr, IH_ARCH_NIOS)) #elif defined(__nios2__) if (!image_check_arch (hdr, IH_ARCH_NIOS2)) #elif defined(__PPC__) @@ -647,8 +644,6 @@ static inline int fit_image_check_target_arch (const void *fdt, int node) if (!fit_image_check_arch (fdt, node, IH_ARCH_MICROBLAZE)) #elif defined(__mips__) if (!fit_image_check_arch (fdt, node, IH_ARCH_MIPS)) -#elif defined(__nios__) - if (!fit_image_check_arch (fdt, node, IH_ARCH_NIOS)) #elif defined(__nios2__) if (!fit_image_check_arch (fdt, node, IH_ARCH_NIOS2)) #elif defined(__PPC__) diff --git a/include/nios-io.h b/include/nios-io.h deleted file mode 100644 index dc7e127fe5..0000000000 --- a/include/nios-io.h +++ /dev/null @@ -1,183 +0,0 @@ -/* - * (C) Copyright 2003, Psyent Corporation - * Scott McNutt - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/************************************************************************* - * Altera Nios Standard Peripherals - ************************************************************************/ - -#ifndef __NIOSIO_H__ -#define __NIOSIO_H__ - -/*------------------------------------------------------------------------ - * UART (http://www.altera.com/literature/ds/ds_nios_uart.pdf) - *----------------------------------------------------------------------*/ -typedef volatile struct nios_uart_t { - unsigned rxdata; /* Rx data reg */ - unsigned txdata; /* Tx data reg */ - unsigned status; /* Status reg */ - unsigned control; /* Control reg */ - unsigned divisor; /* Baud rate divisor reg */ - unsigned endofpacket; /* End-of-packet reg */ -}nios_uart_t; - -/* status register */ -#define NIOS_UART_PE (1 << 0) /* parity error */ -#define NIOS_UART_FE (1 << 1) /* frame error */ -#define NIOS_UART_BRK (1 << 2) /* break detect */ -#define NIOS_UART_ROE (1 << 3) /* rx overrun */ -#define NIOS_UART_TOE (1 << 4) /* tx overrun */ -#define NIOS_UART_TMT (1 << 5) /* tx empty */ -#define NIOS_UART_TRDY (1 << 6) /* tx ready */ -#define NIOS_UART_RRDY (1 << 7) /* rx ready */ -#define NIOS_UART_E (1 << 8) /* exception */ -#define NIOS_UART_DCTS (1 << 10) /* cts change */ -#define NIOS_UART_CTS (1 << 11) /* cts */ -#define NIOS_UART_EOP (1 << 12) /* eop detected */ - -/* control register */ -#define NIOS_UART_IPE (1 << 0) /* parity error int ena*/ -#define NIOS_UART_IFE (1 << 1) /* frame error int ena */ -#define NIOS_UART_IBRK (1 << 2) /* break detect int ena */ -#define NIOS_UART_IROE (1 << 3) /* rx overrun int ena */ -#define NIOS_UART_ITOE (1 << 4) /* tx overrun int ena */ -#define NIOS_UART_ITMT (1 << 5) /* tx empty int ena */ -#define NIOS_UART_ITRDY (1 << 6) /* tx ready int ena */ -#define NIOS_UART_IRRDY (1 << 7) /* rx ready int ena */ -#define NIOS_UART_IE (1 << 8) /* exception int ena */ -#define NIOS_UART_TBRK (1 << 9) /* transmit break */ -#define NIOS_UART_IDCTS (1 << 10) /* cts change int ena */ -#define NIOS_UART_RTS (1 << 11) /* rts */ -#define NIOS_UART_IEOP (1 << 12) /* eop detected int ena */ - - -/*------------------------------------------------------------------------ - * TIMER (http://www.altera.com/literature/ds/ds_nios_timer.pdf) - *----------------------------------------------------------------------*/ -typedef volatile struct nios_timer_t { - unsigned status; /* Timer status reg */ - unsigned control; /* Timer control reg */ - unsigned periodl; /* Timeout period low */ - unsigned periodh; /* Timeout period high */ - unsigned snapl; /* Snapshot low */ - unsigned snaph; /* Snapshot high */ -}nios_timer_t; - -/* status register */ -#define NIOS_TIMER_TO (1 << 0) /* Timeout */ -#define NIOS_TIMER_RUN (1 << 1) /* Timer running */ - -/* control register */ -#define NIOS_TIMER_ITO (1 << 0) /* Timeout int ena */ -#define NIOS_TIMER_CONT (1 << 1) /* Continuous mode */ -#define NIOS_TIMER_START (1 << 2) /* Start timer */ -#define NIOS_TIMER_STOP (1 << 3) /* Stop timer */ - - -/*------------------------------------------------------------------------ - * PIO (http://www.altera.com/literature/ds/ds_nios_pio.pdf) - *----------------------------------------------------------------------*/ -typedef volatile struct nios_pio_t { - unsigned int data; /* Data value at each PIO in/out */ - unsigned int direction; /* Data direct. for each PIO bit */ - unsigned int interruptmask; /* Per-bit IRQ enable/disable */ - unsigned int edgecapture; /* Per-bit sync. edge detect & hold */ -}nios_pio_t; - -/* direction register */ -#define NIOS_PIO_OUT (1) /* PIO bit is output */ -#define NIOS_PIO_IN (0) /* PIO bit is input */ - - -/*------------------------------------------------------------------------ - * SPI (http://www.altera.com/literature/ds/ds_nios_spi.pdf) - *----------------------------------------------------------------------*/ -typedef volatile struct nios_spi_t { - unsigned rxdata; /* Rx data reg */ - unsigned txdata; /* Tx data reg */ - unsigned status; /* Status reg */ - unsigned control; /* Control reg */ - unsigned reserved; /* (master only) */ - unsigned slaveselect; /* SPI slave select mask (master only) */ -}nios_spi_t; - -/* status register */ -#define NIOS_SPI_ROE (1 << 3) /* rx overrun */ -#define NIOS_SPI_TOE (1 << 4) /* tx overrun */ -#define NIOS_SPI_TMT (1 << 5) /* tx empty */ -#define NIOS_SPI_TRDY (1 << 6) /* tx ready */ -#define NIOS_SPI_RRDY (1 << 7) /* rx ready */ -#define NIOS_SPI_E (1 << 8) /* exception */ - -/* control register */ -#define NIOS_SPI_IROE (1 << 3) /* rx overrun int ena */ -#define NIOS_SPI_ITOE (1 << 4) /* tx overrun int ena */ -#define NIOS_SPI_ITRDY (1 << 6) /* tx ready int ena */ -#define NIOS_SPI_IRRDY (1 << 7) /* rx ready int ena */ -#define NIOS_SPI_IE (1 << 8) /* exception int ena */ -#define NIOS_SPI_SSO (1 << 10) /* override SS_n output */ - -/*------------------------------------------------------------------------ - * ASMI - *----------------------------------------------------------------------*/ -typedef volatile struct nios_asmi_t { - unsigned rxdata; /* Rx data reg */ - unsigned txdata; /* Tx data reg */ - unsigned status; /* Status reg */ - unsigned control; /* Control reg */ - unsigned reserved; - unsigned slavesel; /* Slave select */ - unsigned endofpacket; /* End-of-packet reg */ -}nios_asmi_t; - -/* status register */ -#define NIOS_ASMI_ROE (1 << 3) /* rx overrun */ -#define NIOS_ASMI_TOE (1 << 4) /* tx overrun */ -#define NIOS_ASMI_TMT (1 << 5) /* tx empty */ -#define NIOS_ASMI_TRDY (1 << 6) /* tx ready */ -#define NIOS_ASMI_RRDY (1 << 7) /* rx ready */ -#define NIOS_ASMI_E (1 << 8) /* exception */ -#define NIOS_ASMI_EOP (1 << 9) /* eop detected */ - -/* control register */ -#define NIOS_ASMI_IROE (1 << 3) /* rx overrun int ena */ -#define NIOS_ASMI_ITOE (1 << 4) /* tx overrun int ena */ -#define NIOS_ASMI_ITRDY (1 << 6) /* tx ready int ena */ -#define NIOS_ASMI_IRRDY (1 << 7) /* rx ready int ena */ -#define NIOS_ASMI_IE (1 << 8) /* exception int ena */ -#define NIOS_ASMI_IEOP (1 << 9) /* rx eop int ena */ -#define NIOS_ASMI_SSO (1 << 10) /* slave select enable */ - -/*------------------------------------------------------------------------ - * JTAG UART - *----------------------------------------------------------------------*/ -typedef volatile struct nios_jtag_t { - unsigned short rxcntl; /* Rx data/cntl reg */ - unsigned short txcntl; /* Tx data/cntl reg */ - unsigned short errcntl; /* Err dta/cntl reg */ -}nios_jtag_t; - -/* status register */ -#define NIOS_JTAG_TRDY (1 << 8) /* tx ready bit */ -#define NIOS_JTAG_RRDY (1 << 8) /* rx ready bit */ - -#endif /* __NIOSIO_H__ */ diff --git a/include/nios.h b/include/nios.h deleted file mode 100644 index 46b685ab9d..0000000000 --- a/include/nios.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - * (C) Copyright 2003, Psyent Corporation - * Scott McNutt - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __NIOS_H__ -#define __NIOS_H__ - -/*------------------------------------------------------------------------ - * Control registers -- use with wrctl() & rdctl() - *----------------------------------------------------------------------*/ -#define CTL_STATUS 0x00 /* Processor status */ -#define CTL_ISTATUS 0x01 /* Saved status (exception) */ -#define CTL_WVALID 0x02 /* Valid window limit */ -#define CTL_ICACHE 0x05 /* I-cache line-invalidate */ -#define CTL_CPU_ID 0x06 /* CPU version id */ -#define CTL_DCACHE 0x07 /* D-cache line-invalidate */ -#define CTL_CLR_IE 0x08 /* Interrupt clear (disable) */ -#define CTL_SET_IE 0x09 /* Interrupt set (enable) */ - -/*------------------------------------------------------------------------ - * Access to control regs - *----------------------------------------------------------------------*/ -#define _str_(s) #s - -#define rdctl(reg)\ - ({unsigned int val;\ - asm volatile( "pfx " _str_(reg) "\n\t rdctl %0"\ - : "=r" (val) ); val;}) - -#define wrctl(reg,val)\ - asm volatile( "pfx " _str_(reg) "\n\t wrctl %0 \n\t nop"\ - : : "r" (val)) - -/*------------------------------------------------------------------------ - * Control reg bit masks - *----------------------------------------------------------------------*/ -#define STATUS_DC (1<<17) /* Data cache enable */ -#define STATUS_IC (1<<16) /* Instruction cache enable */ -#define STATUS_IE (1<<15) /* Interrupt enable */ -#define STATUS_IPRI (0x3f<<9) /* Interrupt priority */ -#define STATUS_CWP (0x1f<<4) /* Current window pointer */ -#define STATUS_N (1<<3) /* Condition code: negative */ -#define STATUS_V (1<<2) /* Condition code: overflow */ -#define STATUS_Z (1<<1) /* Condition code: zero */ -#define STATUS_C (1<<0) /* Condition code: carry/borrow */ - -static inline unsigned ipri( unsigned prio ) -{ - unsigned tmp; - unsigned status = rdctl(CTL_STATUS); - prio = (prio << 9) & STATUS_IPRI; - tmp = (status & ~STATUS_IPRI) | prio; - wrctl(CTL_STATUS,tmp); - return( (status & STATUS_IPRI) >> 9); -} - - -#endif /* __NIOS_H__ */ diff --git a/include/watchdog.h b/include/watchdog.h index ef2f5aac9b..b9599143af 100644 --- a/include/watchdog.h +++ b/include/watchdog.h @@ -31,10 +31,6 @@ # error "Configuration error: CONFIG_HW_WATCHDOG and CONFIG_WATCHDOG can't be used together." #endif -#if defined(__ASSEMBLY__) && defined(__NIOS__) -# error "Configuration error: WATCHDOG_RESET inside assembler not supported for Nios platforms." -#endif - /* * Hardware watchdog */ -- cgit From f986325dd569faeaec4186f678d113505c5c4828 Mon Sep 17 00:00:00 2001 From: Ron Madrid Date: Tue, 1 Jun 2010 17:00:49 -0700 Subject: Update SICRL_USBDR to reflect 4 different settings This patch changed the SICRL_USBDR define to reflect the 4 different bit settings for this two-bit field. The four different options are '00', '01', '10', and '11'. This patch also corrects the config file for SIMPC8313 and MPC8313ERDB for the appropriate fields. This change only affects the MPC8313 cpu. Signed-off-by: Ron Madrid Signed-off-by: Kim Phillips --- include/configs/MPC8313ERDB.h | 2 +- include/configs/SIMPC8313.h | 2 +- include/mpc83xx.h | 5 ++++- 3 files changed, 6 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h index 94695fc285..9a40adc355 100644 --- a/include/configs/MPC8313ERDB.h +++ b/include/configs/MPC8313ERDB.h @@ -513,7 +513,7 @@ /* System IO Config */ #define CONFIG_SYS_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */ -#define CONFIG_SYS_SICRL SICRL_USBDR /* Enable Internal USB Phy */ +#define CONFIG_SYS_SICRL SICRL_USBDR_10 /* Enable Internal USB Phy */ #define CONFIG_SYS_HID0_INIT 0x000000000 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ diff --git a/include/configs/SIMPC8313.h b/include/configs/SIMPC8313.h index 9104f1ad36..eb8657b6be 100644 --- a/include/configs/SIMPC8313.h +++ b/include/configs/SIMPC8313.h @@ -419,7 +419,7 @@ | SICRH_TSOBI1 \ | SICRH_TSOBI2 ) #define CONFIG_SYS_SICRL ( SICRL_LBC \ - | SICRL_USBDR \ + | SICRL_USBDR_10 \ | SICRL_ETSEC2_A ) #define CONFIG_SYS_HID0_INIT 0x000000000 diff --git a/include/mpc83xx.h b/include/mpc83xx.h index 44115c91b4..5214911d1c 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -206,7 +206,10 @@ #define SICRL_SPI_B 0x00C00000 #define SICRL_SPI_C 0x00300000 #define SICRL_SPI_D 0x000C0000 -#define SICRL_USBDR 0x00000C00 +#define SICRL_USBDR_11 0x00000C00 +#define SICRL_USBDR_10 0x00000800 +#define SICRL_USBDR_01 0x00000400 +#define SICRL_USBDR_00 0x00000000 #define SICRL_ETSEC1_A 0x0000000C #define SICRL_ETSEC2_A 0x00000003 -- cgit From b87996d24a41cfc15fea125e5c805163af4acba1 Mon Sep 17 00:00:00 2001 From: Cyril Chemparathy Date: Mon, 7 Jun 2010 14:13:27 -0400 Subject: ARM1176: Coexist with other ARM1176 platforms The current ARM1176 CPU specific code is too specific to the SMDK6400 architecture. The following changes were necessary prerequisites for the addition of other SoCs based on ARM1176. Existing board's (SMDK6400) configuration has been modified to keep behavior unchanged despite these changes. 1. Peripheral port remap configurability The earlier code had hardcoded remap values specific to s3c64xx in start.S. This change makes the peripheral port remap addresses and sizes configurable. 2. U-Boot code relocation support Most architectures allow u-boot code to run initially at a different address (possibly in NOR) and then get relocated to its final resting place in RAM. Added support for this capability in ARM1176 architecture. 3. Disable TCM if necessary If a ROM based bootloader happened to have initialized TCM, we disable it here to keep things sane. 4. Remove unnecessary SoC specific includes ARM1176 code does not really need this SoC specific include. The presence of this include prevents builds on other ARM1176 archs. 5. Modified virt-to-phys conversion during MMU disable The original MMU disable code masks out too many bits from the load address when it tries to figure out the physical address of the jump target label. Consequently, it ends up branching to the wrong address after disabling the MMU. Signed-off-by: Cyril Chemparathy Signed-off-by: Sandeep Paulraj --- include/configs/smdk6400.h | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/configs/smdk6400.h b/include/configs/smdk6400.h index f04feae219..624fe04b05 100644 --- a/include/configs/smdk6400.h +++ b/include/configs/smdk6400.h @@ -40,6 +40,12 @@ #define CONFIG_S3C64XX 1 /* in a SAMSUNG S3C64XX Family */ #define CONFIG_SMDK6400 1 /* on a SAMSUNG SMDK6400 Board */ +#define CONFIG_SKIP_RELOCATE_UBOOT + +#define CONFIG_PERIPORT_REMAP +#define CONFIG_PERIPORT_BASE 0x70000000 +#define CONFIG_PERIPORT_SIZE 0x13 + #define CONFIG_SYS_SDRAM_BASE 0x50000000 /* input clock of PLL: SMDK6400 has 12MHz input clock */ @@ -61,8 +67,6 @@ #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO -#undef CONFIG_SKIP_RELOCATE_UBOOT - /* * Size of malloc() pool */ -- cgit From 04cbc19fedb55265d08cddea294c3b6d9f8b2d18 Mon Sep 17 00:00:00 2001 From: Cyril Chemparathy Date: Mon, 7 Jun 2010 14:13:36 -0400 Subject: TI: TNETV107X EVM initial support TNETV107X is a Texas Instruments SoC based on an ARM1176 core, and with a bunch on on-chip integrated peripherals. This patch adds support for the TNETV107X EVM board. Signed-off-by: Cyril Chemparathy Signed-off-by: Sandeep Paulraj --- include/configs/tnetv107x_evm.h | 153 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 153 insertions(+) create mode 100644 include/configs/tnetv107x_evm.h (limited to 'include') diff --git a/include/configs/tnetv107x_evm.h b/include/configs/tnetv107x_evm.h new file mode 100644 index 0000000000..454e9b2f49 --- /dev/null +++ b/include/configs/tnetv107x_evm.h @@ -0,0 +1,153 @@ +/* + * Copyright (C) 2008 Texas Instruments, Inc + * + * Based on davinci_dvevm.h. Original Copyrights follow: + * + * Copyright (C) 2007 Sergey Kubushyn + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include +#include +#include + +/* Architecture, CPU, etc */ +#define CONFIG_ARM1176 +#define CONFIG_TNETV107X +#define CONFIG_TNETV107X_EVM +#define CONFIG_ARCH_CPU_INIT +#define CONFIG_SYS_UBOOT_BASE TEXT_BASE +#define CONFIG_DISABLE_TCM +#define CONFIG_PERIPORT_REMAP +#define CONFIG_PERIPORT_BASE 0x2000000 +#define CONFIG_PERIPORT_SIZE 0x10 +#define CONFIG_SYS_CLK_FREQ clk_get_rate(TNETV107X_LPSC_ARM) + +#define CONFIG_SYS_TIMERBASE TNETV107X_TIMER0_BASE +#define CONFIG_SYS_HZ_CLOCK clk_get_rate(TNETV107X_LPSC_TIMER0) +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_PLL_SYS_EXT_FREQ 25000000 +#define CONFIG_PLL_TDM_EXT_FREQ 19200000 +#define CONFIG_PLL_ETH_EXT_FREQ 25000000 + +/* Memory Info */ +#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) +#define CONFIG_SYS_GBL_DATA_SIZE 128 +#define PHYS_SDRAM_1 TNETV107X_DDR_EMIF_DATA_BASE +#define PHYS_SDRAM_1_SIZE 0x04000000 +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 +#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 16*1024*1024) +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_STACKSIZE (256*1024) + +/* Serial Driver Info */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE -4 +#define CONFIG_SYS_NS16550_COM1 TNETV107X_UART1_BASE +#define CONFIG_SYS_NS16550_CLK clk_get_rate(TNETV107X_LPSC_UART1) +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* Flash and environment info */ +#define CONFIG_SYS_NO_FLASH +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_NAND_DAVINCI +#define CONFIG_ENV_SIZE (SZ_128K) +#define CONFIG_SYS_NAND_HW_ECC +#define CONFIG_SYS_NAND_1BIT_ECC +#define CONFIG_SYS_NAND_CS 2 +#define CONFIG_SYS_NAND_USE_FLASH_BBT +#define CONFIG_SYS_NAND_BASE TNETV107X_ASYNC_EMIF_DATA_CE0_BASE +#define CONFIG_SYS_CLE_MASK 0x10 +#define CONFIG_SYS_ALE_MASK 0x8 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_MTDPARTS +#define CONFIG_MTD_DEVICE +#define CONFIG_JFFS2_NAND +#define NAND_MAX_CHIPS 1 +#define CONFIG_ENV_OFFSET 0x180000 +#define DEF_BOOTM "" + +/* + * davinci_nand is a bit of a misnomer since this particular EMIF block is + * commonly used across multiple TI devices. Unfortunately, this misnomer + * (amongst others) carries forward into the kernel too. Consequently, if we + * use a different device name here, the mtdparts variable won't be usable as + * a kernel command-line argument. + */ +#define MTDIDS_DEFAULT "nand0=davinci_nand.0" +#define MTDPARTS_DEFAULT "mtdparts=davinci_nand.0:" \ + "1536k(uboot)ro," \ + "128k(params)ro," \ + "4m(kernel)," \ + "-(filesystem)" + +/* General U-Boot configuration */ +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_SYS_PROMPT "U-Boot > " +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_VERSION_VARIABLE +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_LONGHELP +#define CONFIG_CRC32_VERIFY +#define CONFIG_MX_CYCLIC +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_MEMTEST_START + \ + 0x700000) +#define LINUX_BOOT_PARAM_ADDR (CONFIG_SYS_MEMTEST_START + 0x100) +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_BOOTARGS "mem=32M console=ttyS1,115200n8 " \ + "root=/dev/mmcblk0p1 rw noinitrd" +#define CONFIG_BOOTCOMMAND "" +#define CONFIG_BOOTDELAY 1 + +#define CONFIG_CMD_BDI +#define CONFIG_CMD_BOOTD +#define CONFIG_CMD_CONSOLE +#define CONFIG_CMD_ECHO +#define CONFIG_CMD_EDITENV +#define CONFIG_CMD_IMI +#define CONFIG_CMD_ITEST +#define CONFIG_CMD_LOADB +#define CONFIG_CMD_LOADS +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_MISC +#define CONFIG_CMD_RUN +#define CONFIG_CMD_SAVEENV +#define CONFIG_CMD_SOURCE +#define CONFIG_CMD_ENV +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_SAVES +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_NAND +#define CONFIG_CMD_JFFS2 + +#endif /* __CONFIG_H */ -- cgit From 7ca4766bd7f74e5f7371fb331b573ec384230c1d Mon Sep 17 00:00:00 2001 From: Vaibhav Hiremath Date: Mon, 7 Jun 2010 15:20:19 -0400 Subject: OMAP3EVM: Added NAND support The EVMS have been shipping with NAND (instead of OneNAND) as default. So, this patch sets NAND as default. To choose OneNAND, define CMD_ONENAND instead of CMD_NAND in the config file omap3_evm.h. Signed-off-by: Vaibhav Hiremath Signed-off-by: Sandeep Paulraj --- include/configs/omap3_evm.h | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h index 0d99f7df0c..88af49226c 100644 --- a/include/configs/omap3_evm.h +++ b/include/configs/omap3_evm.h @@ -151,7 +151,7 @@ #define CONFIG_CMD_I2C /* I2C serial bus support */ #define CONFIG_CMD_MMC /* MMC support */ -#define CONFIG_CMD_ONENAND /* ONENAND support */ +#define CONFIG_CMD_NAND /* NAND support */ #define CONFIG_CMD_DHCP #define CONFIG_CMD_PING @@ -306,7 +306,13 @@ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP +#if defined(CONFIG_CMD_NAND) +#define CONFIG_NAND_OMAP_GPMC +#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 +#define CONFIG_ENV_IS_IN_NAND +#elif defined(CONFIG_CMD_ONENAND) #define CONFIG_ENV_IS_IN_ONENAND 1 +#endif #define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ -- cgit From 8aa5c7cdc4e534df9129485ba317a2871c4f9880 Mon Sep 17 00:00:00 2001 From: Vaibhav Hiremath Date: Mon, 7 Jun 2010 15:20:34 -0400 Subject: omap3: Consolidate SDRC related operations Consolidated SDRC related functions into one file - sdrc.c And also replaced sdrc_init with generic memory init function (mem_init), this generalization of omap memory setup is necessary to support the new emif4 interface introduced in AM3517. Signed-off-by: Vaibhav Hiremath Signed-off-by: Sandeep Paulraj --- include/configs/devkit8000.h | 2 ++ include/configs/omap3_beagle.h | 2 ++ include/configs/omap3_evm.h | 2 ++ include/configs/omap3_overo.h | 2 ++ include/configs/omap3_pandora.h | 2 ++ include/configs/omap3_sdp3430.h | 2 ++ include/configs/omap3_zoom1.h | 2 ++ include/configs/omap3_zoom2.h | 2 ++ 8 files changed, 16 insertions(+) (limited to 'include') diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h index 7d1332f62c..1076de6fcd 100644 --- a/include/configs/devkit8000.h +++ b/include/configs/devkit8000.h @@ -38,6 +38,8 @@ #define CONFIG_OMAP3430 1 /* which is in a 3430 */ #define CONFIG_OMAP3_DEVKIT8000 1 /* working with DevKit8000 */ +#define CONFIG_SDRC /* The chip has SDRC controller */ + #include /* get chip and board defs */ #include diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index 08d79aca39..e018b217cf 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -37,6 +37,8 @@ #define CONFIG_OMAP3430 1 /* which is in a 3430 */ #define CONFIG_OMAP3_BEAGLE 1 /* working with BEAGLE */ +#define CONFIG_SDRC /* The chip has SDRC controller */ + #include /* get chip and board defs */ #include diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h index 88af49226c..af7c65ad30 100644 --- a/include/configs/omap3_evm.h +++ b/include/configs/omap3_evm.h @@ -42,6 +42,8 @@ #define CONFIG_OMAP3430 1 /* which is in a 3430 */ #define CONFIG_OMAP3_EVM 1 /* working with EVM */ +#define CONFIG_SDRC /* The chip has SDRC controller */ + #include /* get chip and board defs */ #include diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h index a43500b5f1..b4418319f1 100644 --- a/include/configs/omap3_overo.h +++ b/include/configs/omap3_overo.h @@ -29,6 +29,8 @@ #define CONFIG_OMAP3430 1 /* which is in a 3430 */ #define CONFIG_OMAP3_OVERO 1 /* working with overo */ +#define CONFIG_SDRC /* The chip has SDRC controller */ + #include /* get chip and board defs */ #include diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h index 945c053ab3..9eba003c21 100644 --- a/include/configs/omap3_pandora.h +++ b/include/configs/omap3_pandora.h @@ -32,6 +32,8 @@ #define CONFIG_OMAP3430 1 /* which is in a 3430 */ #define CONFIG_OMAP3_PANDORA 1 /* working with pandora */ +#define CONFIG_SDRC /* The chip has SDRC controller */ + #include /* get chip and board defs */ #include diff --git a/include/configs/omap3_sdp3430.h b/include/configs/omap3_sdp3430.h index b4919db087..d4482d3ae6 100644 --- a/include/configs/omap3_sdp3430.h +++ b/include/configs/omap3_sdp3430.h @@ -42,6 +42,8 @@ #define CONFIG_OMAP3430 1 /* which is in a 3430 */ #define CONFIG_OMAP3_3430SDP 1 /* working with SDP Rev2 */ +#define CONFIG_SDRC /* The chip has SDRC controller */ + #include /* get chip and board defs */ #include diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h index ae7ebf9ead..1e88dc02e0 100644 --- a/include/configs/omap3_zoom1.h +++ b/include/configs/omap3_zoom1.h @@ -38,6 +38,8 @@ #define CONFIG_OMAP3430 1 /* which is in a 3430 */ #define CONFIG_OMAP3_ZOOM1 1 /* working with Zoom MDK Rev1 */ +#define CONFIG_SDRC /* The chip has SDRC controller */ + #include /* get chip and board defs */ #include diff --git a/include/configs/omap3_zoom2.h b/include/configs/omap3_zoom2.h index c88c732a60..be9daf4fcd 100644 --- a/include/configs/omap3_zoom2.h +++ b/include/configs/omap3_zoom2.h @@ -39,6 +39,8 @@ #define CONFIG_OMAP3430 1 /* which is in a 3430 */ #define CONFIG_OMAP3_ZOOM2 1 /* working with Zoom II */ +#define CONFIG_SDRC /* The chip has SDRC controller */ + #include /* get chip and board defs */ #include -- cgit From 3d9f0ffddaf1ece95a826785b971860ebdadf424 Mon Sep 17 00:00:00 2001 From: Vaibhav Hiremath Date: Mon, 7 Jun 2010 15:20:43 -0400 Subject: AM35x: Add support for AM3517EVM This patch adds basic support for the AM3517EVM. It includes: - Board files (.c and .h) - Default configuration file - Updates for Makefile Signed-off-by: Vaibhav Hiremath Signed-off-by: Sanjeev Premi Signed-off-by: Sandeep Paulraj --- include/configs/am3517_evm.h | 296 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 296 insertions(+) create mode 100644 include/configs/am3517_evm.h (limited to 'include') diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h new file mode 100644 index 0000000000..595b99ce1d --- /dev/null +++ b/include/configs/am3517_evm.h @@ -0,0 +1,296 @@ +/* + * am3517_evm.h - Default configuration for AM3517 EVM board. + * + * Author: Vaibhav Hiremath + * + * Based on omap3_evm_config.h + * + * Copyright (C) 2010 Texas Instruments Incorporated + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */ +#define CONFIG_OMAP 1 /* in a TI OMAP core */ +#define CONFIG_OMAP34XX 1 /* which is a 34XX */ +#define CONFIG_OMAP3_AM3517EVM 1 /* working with AM3517EVM */ + +#define CONFIG_EMIF4 1 /* The chip has EMIF4 controller */ + +#include /* get chip and board defs */ +#include + +/* + * Display CPU and Board information + */ +#define CONFIG_DISPLAY_CPUINFO 1 +#define CONFIG_DISPLAY_BOARDINFO 1 + +/* Clock Defines */ +#define V_OSCK 26000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK >> 1) + +#undef CONFIG_USE_IRQ /* no support for IRQs */ +#define CONFIG_MISC_INIT_R + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 +#define CONFIG_REVISION_TAG 1 + +/* + * Size of malloc() pool + */ +#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */ + /* initial data */ +/* + * DDR related + */ +#define CONFIG_OMAP3_MICRON_DDR 1 /* Micron DDR */ +#define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024) + +/* + * Hardware drivers + */ + +/* + * NS16550 Configuration + */ +#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ + +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK + +/* + * select serial console configuration + */ +#define CONFIG_CONS_INDEX 3 +#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 +#define CONFIG_SERIAL3 3 /* UART3 on AM3517 EVM */ + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ + 115200} +#define CONFIG_MMC 1 +#define CONFIG_OMAP3_MMC 1 +#define CONFIG_DOS_PARTITION 1 + +/* commands to include */ +#include + +#define CONFIG_CMD_EXT2 /* EXT2 Support */ +#define CONFIG_CMD_FAT /* FAT support */ +#define CONFIG_CMD_JFFS2 /* JFFS2 Support */ + +#define CONFIG_CMD_I2C /* I2C serial bus support */ +#define CONFIG_CMD_MMC /* MMC support */ +#define CONFIG_CMD_NAND /* NAND support */ +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PING + +#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ +#undef CONFIG_CMD_FPGA /* FPGA configuration Support */ +#undef CONFIG_CMD_IMI /* iminfo */ +#undef CONFIG_CMD_IMLS /* List all found images */ + +#define CONFIG_SYS_NO_FLASH +#define CONFIG_HARD_I2C 1 +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_BUS 0 +#define CONFIG_SYS_I2C_BUS_SELECT 1 +#define CONFIG_DRIVER_OMAP34XX_I2C 1 + +#undef CONFIG_CMD_NET +/* + * Board NAND Info. + */ +#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ + /* to access nand */ +#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ + /* to access */ + /* nand at CS0 */ + +#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ + /* NAND devices */ +#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ + +#define CONFIG_JFFS2_NAND +/* nand device jffs2 lives on */ +#define CONFIG_JFFS2_DEV "nand0" +/* start of jffs2 partition */ +#define CONFIG_JFFS2_PART_OFFSET 0x680000 +#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */ + +/* Environment information */ +#define CONFIG_BOOTDELAY 10 + +#define CONFIG_BOOTFILE uImage + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loadaddr=0x82000000\0" \ + "console=ttyS2,115200n8\0" \ + "mmcargs=setenv bootargs console=${console} " \ + "root=/dev/mmcblk0p2 rw " \ + "rootfstype=ext3 rootwait\0" \ + "nandargs=setenv bootargs console=${console} " \ + "root=/dev/mtdblock4 rw " \ + "rootfstype=jffs2\0" \ + "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source ${loadaddr}\0" \ + "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "bootm ${loadaddr}\0" \ + "nandboot=echo Booting from nand ...; " \ + "run nandargs; " \ + "nand read ${loadaddr} 280000 400000; " \ + "bootm ${loadaddr}\0" \ + +#define CONFIG_BOOTCOMMAND \ + "if mmc init; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loaduimage; then " \ + "run mmcboot; " \ + "else run nandboot; " \ + "fi; " \ + "fi; " \ + "else run nandboot; fi" + +#define CONFIG_AUTO_COMPLETE 1 +/* + * Miscellaneous configurable options + */ +#define V_PROMPT "AM3517_EVM # " + +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_PROMPT V_PROMPT +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 32 /* max number of command */ + /* args */ +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) +/* memtest works on */ +#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) +#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ + 0x01F00000) /* 31MB */ + +#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ + /* address */ + +/* + * AM3517 has 12 GP timers, they can be driven by the system clock + * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). + * This rate is divided by a local divisor. + */ +#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 +#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ +#define CONFIG_SYS_HZ 1000 + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */ +#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */ +#endif + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ +#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 +#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ +#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 + +/* SDRAM Bank Allocation method */ +#define SDRC_R_B_C 1 + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ + +/* **** PISMO SUPPORT *** */ + +/* Configure the PISMO */ +#define PISMO1_NAND_SIZE GPMC_SIZE_128M +#define PISMO1_ONEN_SIZE GPMC_SIZE_128M + +#define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */ + /* on one chip */ +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ +#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ + +#define CONFIG_SYS_FLASH_BASE boot_flash_base + +/* Monitor at start of flash */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE + +#define CONFIG_NAND_OMAP_GPMC +#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 +#define CONFIG_ENV_IS_IN_NAND 1 +#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ + +#define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec +#define CONFIG_ENV_OFFSET boot_flash_off +#define CONFIG_ENV_ADDR boot_flash_env_addr + +/*----------------------------------------------------------------------- + * CFI FLASH driver setup + */ +/* timeout values are in ticks */ +#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) + +/* Flash banks JFFS2 should use */ +#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ + CONFIG_SYS_MAX_NAND_DEVICE) +#define CONFIG_SYS_JFFS2_MEM_NAND +/* use flash_info[2] */ +#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS +#define CONFIG_SYS_JFFS2_NUM_BANKS 1 + +#ifndef __ASSEMBLY__ +extern unsigned int boot_flash_base; +extern volatile unsigned int boot_flash_env_addr; +extern unsigned int boot_flash_off; +extern unsigned int boot_flash_sec; +extern unsigned int boot_flash_type; +#endif + +#endif /* __CONFIG_H */ -- cgit From 05ee415e316e3b1617aba06a747649f4d4053d41 Mon Sep 17 00:00:00 2001 From: Vaibhav Hiremath Date: Mon, 7 Jun 2010 15:20:53 -0400 Subject: AM35x: Add support for EMIF4 This patch adds support for the EMIF4 interface available in the AM35x processors. Signed-off-by: Vaibhav Hiremath Signed-off-by: Sanjeev Premi Signed-off-by: Sandeep Paulraj --- include/configs/am3517_evm.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h index 595b99ce1d..513d005ee4 100644 --- a/include/configs/am3517_evm.h +++ b/include/configs/am3517_evm.h @@ -33,7 +33,7 @@ #define CONFIG_OMAP34XX 1 /* which is a 34XX */ #define CONFIG_OMAP3_AM3517EVM 1 /* working with AM3517EVM */ -#define CONFIG_EMIF4 1 /* The chip has EMIF4 controller */ +#define CONFIG_EMIF4 /* The chip has EMIF4 controller */ #include /* get chip and board defs */ #include -- cgit From 89b765c7f6ddfde07ba673dd4adbeb5da391a81b Mon Sep 17 00:00:00 2001 From: Sudhakar Rajashekhara Date: Thu, 10 Jun 2010 15:18:15 +0530 Subject: TI: DaVinci: Add board specific code for da850 EVM Provides initial support for TI OMAP-L138/DA850 SoC devices on a Logic PD EVM board. Provides: Initial boot and configuration. Support for i2c. UART support (console). Signed-off-by: Sudhakar Rajashekhara Acked-by: Ben Gardiner Reviewed-by: Wolfgang Denk Signed-off-by: Sandeep Paulraj --- include/configs/da850evm.h | 140 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 140 insertions(+) create mode 100644 include/configs/da850evm.h (limited to 'include') diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h new file mode 100644 index 0000000000..357715d660 --- /dev/null +++ b/include/configs/da850evm.h @@ -0,0 +1,140 @@ +/* + * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ + * + * Based on davinci_dvevm.h. Original Copyrights follow: + * + * Copyright (C) 2007 Sergey Kubushyn + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * Board + */ + +/* + * SoC Configuration + */ +#define CONFIG_MACH_DAVINCI_DA850_EVM +#define CONFIG_ARM926EJS /* arm926ejs CPU core */ +#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */ +#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) +#define CONFIG_SYS_OSCIN_FREQ 24000000 +#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE +#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) +#define CONFIG_SYS_HZ 1000 +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SKIP_RELOCATE_UBOOT /* to a proper address, init done */ + +/* + * Memory Info + */ +#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* reserved for initial data */ +#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ +#define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */ + +/* memtest start addr */ +#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000) + +/* memtest will be run on 16MB */ +#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024) + +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define CONFIG_STACKSIZE (256*1024) /* regular stack */ + +/* + * Serial Driver info + */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */ +#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */ +#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) +#define CONFIG_CONS_INDEX 1 /* use UART0 for console */ +#define CONFIG_BAUDRATE 115200 /* Default baud rate */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * I2C Configuration + */ +#define CONFIG_HARD_I2C +#define CONFIG_DRIVER_DAVINCI_I2C +#define CONFIG_SYS_I2C_SPEED 25000 +#define CONFIG_SYS_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ + +/* + * U-Boot general configuration + */ +#define CONFIG_BOOTFILE "uImage" /* Boot file name */ +#define CONFIG_SYS_PROMPT "DA850-evm > " /* Command Prompt */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */ +#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000) +#define CONFIG_VERSION_VARIABLE +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_LONGHELP +#define CONFIG_CRC32_VERIFY +#define CONFIG_MX_CYCLIC + +/* + * Linux Information + */ +#define LINUX_BOOT_PARAM_ADDR (CONFIG_SYS_MEMTEST_START + 0x100) +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_BOOTARGS \ + "mem=32M console=ttyS2,115200n8 root=/dev/mtdblock2 rw noinitrd ip=dhcp" +#define CONFIG_BOOTDELAY 3 + +/* + * U-Boot commands + */ +#include +#define CONFIG_CMD_ENV +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DIAG +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_SAVES +#define CONFIG_CMD_MEMORY + +#ifndef CONFIG_DRIVER_TI_EMAC +#undef CONFIG_CMD_NET +#undef CONFIG_CMD_DHCP +#undef CONFIG_CMD_MII +#undef CONFIG_CMD_PING +#endif + +#if !defined(CONFIG_USE_NAND) && \ + !defined(CONFIG_USE_NOR) && \ + !defined(CONFIG_USE_SPIFLASH) +#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_SYS_NO_FLASH +#define CONFIG_ENV_SIZE (16 << 10) +#undef CONFIG_CMD_IMLS +#undef CONFIG_CMD_ENV +#endif + +#endif /* __CONFIG_H */ -- cgit From e2bee9e3c0f4bd363207ce5e496cef2134f67d28 Mon Sep 17 00:00:00 2001 From: Anatolij Gustschin Date: Wed, 26 May 2010 10:38:57 +0200 Subject: video: sm501: add support for SM501 chips on PCI bus Signed-off-by: Anatolij Gustschin --- include/pci_ids.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/pci_ids.h b/include/pci_ids.h index edfdc1e0ab..dcc381d301 100644 --- a/include/pci_ids.h +++ b/include/pci_ids.h @@ -1454,6 +1454,7 @@ #define PCI_DEVICE_ID_SMI_710 0x0710 #define PCI_DEVICE_ID_SMI_712 0x0712 #define PCI_DEVICE_ID_SMI_810 0x0810 +#define PCI_DEVICE_ID_SMI_501 0x0501 #define PCI_VENDOR_ID_HUGHES 0x1273 #define PCI_DEVICE_ID_HUGHES_DIRECPC 0x0002 -- cgit From ce9c227cc71afc3b4c78dcc0a565c40d4ad943e4 Mon Sep 17 00:00:00 2001 From: Albert Aribaud <[albert.aribaud@free.fr]> Date: Thu, 17 Jun 2010 19:38:21 +0530 Subject: Add support for the LaCie ED Mini V2 board This patch adds support for the LaCie ED Mini V2 product which is based on the Marvell Orion5x SoC. Signed-off-by: Albert Aribaud --- include/configs/edminiv2.h | 172 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 172 insertions(+) create mode 100644 include/configs/edminiv2.h (limited to 'include') diff --git a/include/configs/edminiv2.h b/include/configs/edminiv2.h new file mode 100644 index 0000000000..c3d95a04c4 --- /dev/null +++ b/include/configs/edminiv2.h @@ -0,0 +1,172 @@ +/* + * Copyright (C) 2010 Albert ARIBAUD + * + * Based on original Kirkwood support which is + * (C) Copyright 2009 + * Marvell Semiconductor + * Written-by: Prafulla Wadaskar + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef _CONFIG_EDMINIV2_H +#define _CONFIG_EDMINIV2_H + +/* + * Version number information + */ + +#define CONFIG_IDENT_STRING " EDMiniV2" + +/* + * High Level Configuration Options (easy to change) + */ + +#define CONFIG_MARVELL 1 +#define CONFIG_ARM926EJS 1 /* Basic Architecture */ +#define CONFIG_FEROCEON 1 /* CPU Core subversion */ +#define CONFIG_ORION5X 1 /* SOC Family Name */ +#define CONFIG_88F5182 1 /* SOC Name */ +#define CONFIG_MACH_EDMINIV2 1 /* Machine type */ + +/* + * CLKs configurations + */ + +#define CONFIG_SYS_HZ 1000 + +/* + * Board-specific values for Orion5x MPP low level init: + * - MPPs 12 to 15 are SATA LEDs (mode 5) + * - Others are GPIO/unused (mode 3 for MPP0, mode 5 for + * MPP16 to MPP19, mode 0 for others + */ + +#define ORION5X_MPP0_7 0x00000003 +#define ORION5X_MPP8_15 0x55550000 +#define ORION5X_MPP16_23 0x00000000 + +/* + * Board-specific values for Orion5x GPIO low level init: + * - GPIO3 is input (RTC interrupt) + * - GPIO16 is Power LED control (0 = on, 1 = off) + * - GPIO17 is Power LED source select (0 = CPLD, 1 = GPIO16) + * - GPIO18 is Power Button status (0 = Released, 1 = Pressed) + * - Last GPIO is 26, further bits are supposed to be 0. + * Enable mask has ones for INPUT, 0 for OUTPUT. + * Default is LED ON. + */ + +#define ORION5X_GPIO_OUT_ENABLE 0x03fcffff +#define ORION5X_GPIO_OUT_VALUE 0x03fcffff + +/* + * NS16550 Configuration + */ + +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK +#define CONFIG_SYS_NS16550_COM1 ORION5X_UART0_BASE + +/* + * Serial Port configuration + * The following definitions let you select what serial you want to use + * for your console driver. + */ + +#define CONFIG_CONS_INDEX 1 /*Console on UART0 */ +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE \ + { 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600 } + +/* + * FLASH configuration + */ + +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_FLASH_CFI_LEGACY +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 11 /* max num of sects on one chip */ +#define CONFIG_SYS_FLASH_BASE 0xfff80000 +#define CONFIG_SYS_FLASH_SECTSZ \ + {16384, 8192, 8192, 32768, \ + 65536, 65536, 65536, 65536, 65536, 65536, 65536} + +/* auto boot */ +#define CONFIG_BOOTDELAY 3 /* default enable autoboot */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_INITRD_TAG 1 /* enable INITRD tag */ +#define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */ + +#define CONFIG_SYS_PROMPT "EDMiniV2> " /* Command Prompt */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ + +sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buff */ +/* + * Commands configuration - using default command set for now + */ +#include +/* + * Disabling some default commands for staggered bring-up + */ +#undef CONFIG_CMD_BOOTD /* no bootd since no net */ +#undef CONFIG_CMD_NET /* no net since no eth */ +#undef CONFIG_CMD_NFS /* no NFS since no net */ + +/* + * Environment variables configurations + */ +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_SECT_SIZE 0x2000 /* 16K */ +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_OFFSET 0x4000 /* env starts here */ + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (1024 * 128) /* 128kB for malloc() */ +/* size in bytes reserved for initial data */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 + +/* + * Other required minimal configurations + */ +#define CONFIG_CONSOLE_INFO_QUIET /* some code reduction */ +#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */ +#define CONFIG_ARCH_MISC_INIT /* call arch_misc_init() */ +#define CONFIG_DISPLAY_CPUINFO /* Display cpu info */ +#define CONFIG_NR_DRAM_BANKS 1 + +#define CONFIG_STACKSIZE 0x00100000 +#define CONFIG_SYS_LOAD_ADDR 0x00800000 +#define CONFIG_SYS_MEMTEST_START 0x00400000 +#define CONFIG_SYS_MEMTEST_END 0x007fffff +#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 +#define CONFIG_SYS_MAXARGS 16 + +#endif /* _CONFIG_EDMINIV2_H */ -- cgit From 86caca1cd97ba71b7a7c82f2b0163682df35ce5d Mon Sep 17 00:00:00 2001 From: Anatolij Gustschin Date: Wed, 26 May 2010 10:38:59 +0200 Subject: ppc4xx: icon: add support for SM502 chip Adds initialization code for SM502 graphics controller and NL6448BC20-21D LCD panel. Signed-off-by: Anatolij Gustschin Cc: Stefan Roese --- include/configs/icon.h | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) (limited to 'include') diff --git a/include/configs/icon.h b/include/configs/icon.h index 3a57d695f9..7a4e60cbc0 100644 --- a/include/configs/icon.h +++ b/include/configs/icon.h @@ -142,6 +142,26 @@ #define CONFIG_SYS_I2C_RTC_ADDR 0x68 #define CONFIG_SYS_M41T11_BASE_YEAR 1900 /* play along with linux */ +/* + * Video options + */ +#define CONFIG_VIDEO + +#ifdef CONFIG_VIDEO +#define CONFIG_VIDEO_SM501 +#define CONFIG_VIDEO_SM501_32BPP +#define CONFIG_VIDEO_SM501_PCI +#define VIDEO_FB_LITTLE_ENDIAN +#define CONFIG_CFB_CONSOLE +#define CONFIG_VIDEO_LOGO +#define CONFIG_CONSOLE_EXTRA_INFO +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_VIDEO_SW_CURSOR +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_SPLASH_SCREEN +#define CFG_CONSOLE_IS_IN_ENV +#endif + /* * Environment */ @@ -171,6 +191,9 @@ #define CONFIG_CMD_PCI #define CONFIG_CMD_SDRAM #define CONFIG_CMD_SNTP +#ifdef CONFIG_VIDEO +#define CONFIG_CMD_BMP +#endif #define CONFIG_IBM_EMAC4_V4 /* 440SPe has this EMAC version */ #define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */ -- cgit From 9312bba01a41191f20821b66b84b3ff1d2902e8a Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Sun, 20 Jun 2010 02:16:44 +0200 Subject: include/compiler.h: remove redundant declaration of errno Commit 37566090 "compiler.h: unify system ifdef cruft here" added both a "#include " and a "extern int errno;" to include/compiler.h which is causing build warnings for some systems, for example for the "netstar" board: In file included from /home/wd/git/u-boot/work/lib/crc32.c:15: include/compiler.h:28: warning: function declaration isn't a prototype The declaration of "errno" should be redundant, as is supposed to provide a correct declaration, so drop it. Signed-off-by: Wolfgang Denk Cc: Mike Frysinger --- include/compiler.h | 2 -- 1 file changed, 2 deletions(-) (limited to 'include') diff --git a/include/compiler.h b/include/compiler.h index 8030bf6ed2..23f4b834d8 100644 --- a/include/compiler.h +++ b/include/compiler.h @@ -25,8 +25,6 @@ #include #include -extern int errno; - #if !defined(__WIN32__) && !defined(__MINGW32__) # include #endif -- cgit From e6441c4f4070aac6825f5b195f38dfe1da53675c Mon Sep 17 00:00:00 2001 From: Prakash PM Date: Tue, 22 Jun 2010 10:24:43 -0400 Subject: DaVinci: EMAC: Get EMAC_MDIO_PHY_NUM from config files Currently EMAC_MDIO_PHY_NUM is defined as 1 in emac_defs.h. Because of this, EMAC does not work on EVMs which do not have phy connected at 1. Moving the macro to board config file makes this configurable depending on where the phy is connected on the MDIO bus. This patch fixes the board reset issue observed during network access on DM365EVM. EMAC driver was assuming EMAC_MDIO_PHY_NUM as 1 but it is 0 on DM365EVM. This patch is verified on da830/omap-l137, dm365 and dm644x evms. Signed-off-by: Prakash PM Signed-off-by: Sandeep Paulraj --- include/configs/da830evm.h | 1 + include/configs/davinci_dm365evm.h | 1 + include/configs/davinci_dvevm.h | 1 + include/configs/davinci_schmoogie.h | 1 + include/configs/davinci_sffsdr.h | 1 + include/configs/davinci_sonata.h | 1 + 6 files changed, 6 insertions(+) (limited to 'include') diff --git a/include/configs/da830evm.h b/include/configs/da830evm.h index 0f58e11e74..160ece2bf9 100644 --- a/include/configs/da830evm.h +++ b/include/configs/da830evm.h @@ -87,6 +87,7 @@ * Network & Ethernet Configuration */ #ifdef CONFIG_DRIVER_TI_EMAC +#define CONFIG_EMAC_MDIO_PHY_NUM 1 #define CONFIG_MII #define CONFIG_BOOTP_DEFAULT #define CONFIG_BOOTP_DNS diff --git a/include/configs/davinci_dm365evm.h b/include/configs/davinci_dm365evm.h index 6f99ae087d..2c3d88dc17 100644 --- a/include/configs/davinci_dm365evm.h +++ b/include/configs/davinci_dm365evm.h @@ -58,6 +58,7 @@ /* Network Configuration */ #define CONFIG_DRIVER_TI_EMAC +#define CONFIG_EMAC_MDIO_PHY_NUM 0 #define CONFIG_MII #define CONFIG_BOOTP_DEFAULT #define CONFIG_BOOTP_DNS diff --git a/include/configs/davinci_dvevm.h b/include/configs/davinci_dvevm.h index 5774df5cfb..aab2afa962 100644 --- a/include/configs/davinci_dvevm.h +++ b/include/configs/davinci_dvevm.h @@ -102,6 +102,7 @@ /* Network & Ethernet Configuration */ /*==================================*/ #define CONFIG_DRIVER_TI_EMAC +#define CONFIG_EMAC_MDIO_PHY_NUM 1 #define CONFIG_MII #define CONFIG_BOOTP_DEFAULT #define CONFIG_BOOTP_DNS diff --git a/include/configs/davinci_schmoogie.h b/include/configs/davinci_schmoogie.h index 3972ebce6f..875dda4442 100644 --- a/include/configs/davinci_schmoogie.h +++ b/include/configs/davinci_schmoogie.h @@ -69,6 +69,7 @@ /* Network & Ethernet Configuration */ /*==================================*/ #define CONFIG_DRIVER_TI_EMAC +#define CONFIG_EMAC_MDIO_PHY_NUM 1 #define CONFIG_MII #define CONFIG_BOOTP_DEFAULT #define CONFIG_BOOTP_DNS diff --git a/include/configs/davinci_sffsdr.h b/include/configs/davinci_sffsdr.h index 94be9dcf44..f4e17f8cc2 100644 --- a/include/configs/davinci_sffsdr.h +++ b/include/configs/davinci_sffsdr.h @@ -66,6 +66,7 @@ #define CONFIG_SYS_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ /* Network & Ethernet Configuration */ #define CONFIG_DRIVER_TI_EMAC +#define CONFIG_EMAC_MDIO_PHY_NUM 1 #define CONFIG_MII #define CONFIG_BOOTP_DEFAULT #define CONFIG_BOOTP_DNS diff --git a/include/configs/davinci_sonata.h b/include/configs/davinci_sonata.h index 490821a0e3..4c0184415f 100644 --- a/include/configs/davinci_sonata.h +++ b/include/configs/davinci_sonata.h @@ -102,6 +102,7 @@ /* Network & Ethernet Configuration */ /*==================================*/ #define CONFIG_DRIVER_TI_EMAC +#define CONFIG_EMAC_MDIO_PHY_NUM 1 #define CONFIG_MII #define CONFIG_BOOTP_DEFAULT #define CONFIG_BOOTP_DNS -- cgit From ee80fa7b6e96a43d4270700cddc884e00cdd99fd Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Sun, 13 Jun 2010 18:38:23 +0200 Subject: Get rid of bogus CONFIG_SYS_BUS_HZ and CONFIG_SYS_CONFIG_BUS_CLK definitions CONFIG_SYS_BUS_HZ has not really been used anywhere except to be redined as CONFIG_SYS_BUS_CLK; in addition, the mpc7448hpc2 had the bogus CONFIG_SYS_CONFIG_BUS_CLK setting which duplicated the funtionality. Change all this to use CONFIG_SYS_BUS_CLK consistently. Signed-off-by: Wolfgang Denk Cc: Frank Gottschling Cc: Reinhard Arlt Cc: Eran Man Cc: Stefan Roese Cc: Nye Liu Cc: Roy Zang --- include/configs/BAB7xx.h | 5 ++--- include/configs/CPCI750.h | 3 +-- include/configs/DB64360.h | 3 +-- include/configs/DB64460.h | 3 +-- include/configs/ELPPC.h | 5 ++--- include/configs/EVB64260.h | 3 +-- include/configs/P3G4.h | 3 +-- include/configs/PCIPPC2.h | 3 +-- include/configs/PCIPPC6.h | 3 +-- include/configs/ZUMA.h | 4 +--- include/configs/mpc7448hpc2.h | 2 +- include/configs/p3mx.h | 6 ++---- include/configs/ppmc7xx.h | 4 +--- 13 files changed, 16 insertions(+), 31 deletions(-) (limited to 'include') diff --git a/include/configs/BAB7xx.h b/include/configs/BAB7xx.h index 40a1c40cc4..4d83786767 100644 --- a/include/configs/BAB7xx.h +++ b/include/configs/BAB7xx.h @@ -436,9 +436,8 @@ extern unsigned char scsi_sym53c8xx_ccf; extern unsigned long bab7xx_get_bus_freq (void); extern unsigned long bab7xx_get_gclk_freq (void); #endif -#define CONFIG_SYS_BUS_HZ bab7xx_get_bus_freq() -#define CONFIG_SYS_BUS_CLK CONFIG_SYS_BUS_HZ -#define CONFIG_SYS_CPU_CLK bab7xx_get_gclk_freq() +#define CONFIG_SYS_BUS_CLK bab7xx_get_bus_freq() +#define CONFIG_SYS_CPU_CLK bab7xx_get_gclk_freq() /* * For booting Linux, the board info and command line data diff --git a/include/configs/CPCI750.h b/include/configs/CPCI750.h index 1c8c68b3e4..f2d51f75ee 100644 --- a/include/configs/CPCI750.h +++ b/include/configs/CPCI750.h @@ -234,8 +234,7 @@ #define CONFIG_SYS_LOAD_ADDR 0x00300000 /* default load address */ #define CONFIG_SYS_HZ 1000 /* decr freq: 1ms ticks */ -#define CONFIG_SYS_BUS_HZ 133000000 /* 133 MHz (CPU = 5*Bus = 666MHz) */ -#define CONFIG_SYS_BUS_CLK CONFIG_SYS_BUS_HZ +#define CONFIG_SYS_BUS_CLK 133000000 /* 133 MHz (CPU = 5*Bus = 666MHz) */ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } diff --git a/include/configs/DB64360.h b/include/configs/DB64360.h index 160871b24e..910933ad58 100644 --- a/include/configs/DB64360.h +++ b/include/configs/DB64360.h @@ -318,8 +318,7 @@ ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0" #define CONFIG_SYS_HZ 1000 /* decr freq: 1ms ticks */ /*ronen - this the Sys clock (cpu bus,internal dram and SDRAM) */ -#define CONFIG_SYS_BUS_HZ 133000000 /* 133 MHz (CPU = 5*Bus = 666MHz) */ -#define CONFIG_SYS_BUS_CLK CONFIG_SYS_BUS_HZ +#define CONFIG_SYS_BUS_CLK 133000000 /* 133 MHz (CPU = 5*Bus = 666MHz) */ #define CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP 7 /* define the SDRAM cycle count */ #define CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_ROP 50 /* for 400MHZ -> 5.0 ns, for 133MHZ -> 7.50 ns */ diff --git a/include/configs/DB64460.h b/include/configs/DB64460.h index 06fd157ad2..765eaaf0fb 100644 --- a/include/configs/DB64460.h +++ b/include/configs/DB64460.h @@ -256,8 +256,7 @@ ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0" #define CONFIG_SYS_HZ 1000 /* decr freq: 1ms ticks */ /*ronen - this the Sys clock (cpu bus,internal dram and SDRAM) */ -#define CONFIG_SYS_BUS_HZ 133000000 /* 133 MHz (CPU = 5*Bus = 666MHz) */ -#define CONFIG_SYS_BUS_CLK CONFIG_SYS_BUS_HZ +#define CONFIG_SYS_BUS_CLK 133000000 /* 133 MHz (CPU = 5*Bus = 666MHz) */ #define CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP 7 /* define the SDRAM cycle count */ #define CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_ROP 50 /* for 200MHZ -> 5.0 ns, 166MHZ -> 6.0, 133MHZ -> 7.50 ns */ diff --git a/include/configs/ELPPC.h b/include/configs/ELPPC.h index d2aa8b92e4..84d27b67a9 100644 --- a/include/configs/ELPPC.h +++ b/include/configs/ELPPC.h @@ -314,9 +314,8 @@ /* * Speed settings are board specific */ -#define CONFIG_SYS_BUS_HZ 100000000 -#define CONFIG_SYS_CPU_CLK 400000000 -#define CONFIG_SYS_BUS_CLK CONFIG_SYS_BUS_HZ +#define CONFIG_SYS_BUS_CLK 100000000 +#define CONFIG_SYS_CPU_CLK 400000000 /* * For booting Linux, the board info and command line data diff --git a/include/configs/EVB64260.h b/include/configs/EVB64260.h index bf41c13bdf..0903536348 100644 --- a/include/configs/EVB64260.h +++ b/include/configs/EVB64260.h @@ -141,8 +141,7 @@ #define CONFIG_SYS_LOAD_ADDR 0x00300000 /* default load address */ #define CONFIG_SYS_HZ 1000 /* decr freq: 1ms ticks */ -#define CONFIG_SYS_BUS_HZ 100000000 /* 100 MHz */ -#define CONFIG_SYS_BUS_CLK CONFIG_SYS_BUS_HZ +#define CONFIG_SYS_BUS_CLK 100000000 /* 100 MHz */ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } diff --git a/include/configs/P3G4.h b/include/configs/P3G4.h index 971338a466..890170d1d4 100644 --- a/include/configs/P3G4.h +++ b/include/configs/P3G4.h @@ -168,8 +168,7 @@ #define CONFIG_SYS_LOAD_ADDR 0x00300000 /* default load address */ #define CONFIG_SYS_HZ 1000 /* decr freq: 1ms ticks */ -#define CONFIG_SYS_BUS_HZ 133000000 /* 133 MHz */ -#define CONFIG_SYS_BUS_CLK CONFIG_SYS_BUS_HZ +#define CONFIG_SYS_BUS_CLK 133000000 /* 133 MHz */ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } diff --git a/include/configs/PCIPPC2.h b/include/configs/PCIPPC2.h index 99a8c4a646..c30ac785a8 100644 --- a/include/configs/PCIPPC2.h +++ b/include/configs/PCIPPC2.h @@ -194,9 +194,8 @@ * For the detail description refer to the PCIPPC2 user's manual. */ #define CONFIG_SYS_HZ 1000 -#define CONFIG_SYS_BUS_HZ 100000000 /* bus speed - 100 mhz */ +#define CONFIG_SYS_BUS_CLK 100000000 /* bus speed - 100 mhz */ #define CONFIG_SYS_CPU_CLK 300000000 -#define CONFIG_SYS_BUS_CLK 100000000 /* * For booting Linux, the board info and command line data diff --git a/include/configs/PCIPPC6.h b/include/configs/PCIPPC6.h index 66e6d24817..bc67480449 100644 --- a/include/configs/PCIPPC6.h +++ b/include/configs/PCIPPC6.h @@ -196,9 +196,8 @@ * For the detail description refer to the PCIPPC2 user's manual. */ #define CONFIG_SYS_HZ 1000 -#define CONFIG_SYS_BUS_HZ 100000000 /* bus speed - 100 mhz */ +#define CONFIG_SYS_BUS_CLK 100000000 /* bus speed - 100 mhz */ #define CONFIG_SYS_CPU_CLK 300000000 -#define CONFIG_SYS_BUS_CLK 100000000 /* * For booting Linux, the board info and command line data diff --git a/include/configs/ZUMA.h b/include/configs/ZUMA.h index b73aaa817b..fcc47a99ec 100644 --- a/include/configs/ZUMA.h +++ b/include/configs/ZUMA.h @@ -164,9 +164,7 @@ #define CONFIG_SYS_HZ 1000 /* decr freq: 1ms ticks */ -#define CONFIG_SYS_BUS_HZ 133000000 /* 133 MHz */ - -#define CONFIG_SYS_BUS_CLK CONFIG_SYS_BUS_HZ +#define CONFIG_SYS_BUS_CLK 133000000 /* 133 MHz */ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } diff --git a/include/configs/mpc7448hpc2.h b/include/configs/mpc7448hpc2.h index be12186aca..497ea42206 100644 --- a/include/configs/mpc7448hpc2.h +++ b/include/configs/mpc7448hpc2.h @@ -46,7 +46,7 @@ #define CONFIG_IDENT_STRING " Freescale MPC7448 HPC II" #define CONFIG_SYS_OCN_CLK 133000000 /* 133 MHz */ -#define CONFIG_SYS_CONFIG_BUS_CLK 133000000 +#define CONFIG_SYS_BUS_CLK 133000000 #define CONFIG_SYS_CLK_SPREAD /* Enable Spread-Spectrum Clock generation */ diff --git a/include/configs/p3mx.h b/include/configs/p3mx.h index 0749037163..17ec08fdd6 100644 --- a/include/configs/p3mx.h +++ b/include/configs/p3mx.h @@ -44,14 +44,12 @@ #define CONFIG_750FX /* 750GL/GX/FX */ #define CONFIG_HIGH_BATS /* High BATs supported */ #define CONFIG_SYS_BOARD_NAME "P3M750" -#define CONFIG_SYS_BUS_HZ 100000000 -#define CONFIG_SYS_BUS_CLK CONFIG_SYS_BUS_HZ +#define CONFIG_SYS_BUS_CLK 100000000 #define CONFIG_SYS_TCLK 100000000 #elif defined (CONFIG_P3M7448) #define CONFIG_74xx #define CONFIG_SYS_BOARD_NAME "P3M7448" -#define CONFIG_SYS_BUS_HZ 133333333 -#define CONFIG_SYS_BUS_CLK CONFIG_SYS_BUS_HZ +#define CONFIG_SYS_BUS_CLK 133333333 #define CONFIG_SYS_TCLK 133333333 #endif #define CONFIG_SYS_GT_DUAL_CPU /* also for JTAG even with one cpu */ diff --git a/include/configs/ppmc7xx.h b/include/configs/ppmc7xx.h index 0fd8635681..04779c4058 100644 --- a/include/configs/ppmc7xx.h +++ b/include/configs/ppmc7xx.h @@ -355,12 +355,10 @@ /* * Clocks config * - * CONFIG_SYS_BUS_HZ - Bus clock frequency in Hz - * CONFIG_SYS_BUS_CLK - As above (?) + * CONFIG_SYS_BUS_CLK - Bus clock frequency in Hz * CONFIG_SYS_HZ - Decrementer freq in Hz */ -#define CONFIG_SYS_BUS_HZ CONFIG_BUS_CLK #define CONFIG_SYS_BUS_CLK CONFIG_BUS_CLK #define CONFIG_SYS_HZ 1000 -- cgit From 953b7e629198fe2eb0adf272fb9140f2a4a51826 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Sun, 13 Jun 2010 18:28:54 +0200 Subject: Remove AmigaOneG3SE board The AmigaOneG3SE board has been orphaned or a very long time, and broken for more than 12 releases resp. more than 3 years. As nobody seems to be interested any more in this stuff we may as well ged rid of it, especially as it clutters many areas of the code so it is a continuous pain for all kinds of ongoing work. Signed-off-by: Wolfgang Denk --- include/configs/AmigaOneG3SE.h | 404 ----------------------------------------- 1 file changed, 404 deletions(-) delete mode 100644 include/configs/AmigaOneG3SE.h (limited to 'include') diff --git a/include/configs/AmigaOneG3SE.h b/include/configs/AmigaOneG3SE.h deleted file mode 100644 index 0dfb23b310..0000000000 --- a/include/configs/AmigaOneG3SE.h +++ /dev/null @@ -1,404 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * - * Configuration settings for the AmigaOneG3SE board. - * - */ - -/* ------------------------------------------------------------------------- */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_AMIGAONEG3SE 1 - -#define CONFIG_BOARD_EARLY_INIT_F 1 -#define CONFIG_MISC_INIT_R 1 - -#define CONFIG_VERY_BIG_RAM 1 - -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 9600 -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -#undef CONFIG_CLOCKS_IN_MHZ /* clocks passed to Linux in Hz */ - -#define CONFIG_BOOTARGS "root=/dev/ram rw ramdisk_size=4096" - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION -#define CONFIG_AMIGA_PARTITION - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_BSP -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ELF -#define CONFIG_CMD_NET -#define CONFIG_CMD_IDE -#define CONFIG_CMD_FDC -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_CONSOLE -#define CONFIG_CMD_USB -#define CONFIG_CMD_BSP -#define CONFIG_CMD_PCI - - -#define CONFIG_PCI 1 -/* #define CONFIG_PCI_SCAN_SHOW 1 */ -#define CONFIG_PCI_PNP 1 /* PCI plug-and-play */ - -#define atoi(x) simple_strtoul(x,NULL,10) - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "] " /* Monitor Command Prompt */ - -#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */ -/* #undef CONFIG_SYS_HUSH_PARSER */ -#ifdef CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " -#endif -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ - -/* Print Buffer Size - */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) - -#define CONFIG_SYS_MAXARGS 64 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_LOAD_ADDR 0x00500000 /* Default load address */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0xFFF00000 -#define CONFIG_SYS_FLASH_MAX_SIZE 0x00080000 -/* Maximum amount of RAM. - */ -#define CONFIG_SYS_MAX_RAM_SIZE 0x80000000 /* 2G */ - -#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 - -#define CONFIG_SYS_MONITOR_BASE TEXT_BASE - -#define CONFIG_SYS_MONITOR_LEN (768 << 10) /* Reserve 512 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (2500 << 10) /* Reserve 128 kB for malloc() */ - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_SDRAM_BASE && \ - CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_MAX_RAM_SIZE -#define CONFIG_SYS_RAMBOOT -#else -#undef CONFIG_SYS_RAMBOOT -#endif - -#define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area - */ - -/* Size in bytes reserved for initial data - */ -/* HJF: used to be 0x400000 */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_END 0x8000 -#define CONFIG_SYS_GBL_DATA_SIZE 128 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_INIT_RAM_LOCK - -/* - * Temporary buffer for serial data until the real serial driver - * is initialised (memtest will destroy this buffer) - */ -#define CONFIG_SYS_SCONSOLE_ADDR CONFIG_SYS_INIT_RAM_ADDR -#define CONFIG_SYS_SCONSOLE_SIZE 0x0002000 - -/* SDRAM 0 - 256MB - */ - -/*HJF: #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_4M | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U*/ - -#define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_DBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -/* PCI Range - */ -#define CONFIG_SYS_DBAT1L (0x80000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT1U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT1L (0x80000000 | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT1U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) -/* HJF: -#define CONFIG_SYS_IBAT1L ((CONFIG_SYS_SDRAM_BASE+CONFIG_SYS_INIT_RAM_ADDR) | BATL_PP_RW) -#define CONFIG_SYS_IBAT1U ((CONFIG_SYS_SDRAM_BASE+CONFIG_SYS_INIT_RAM_ADDR) | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT1L ((CONFIG_SYS_SDRAM_BASE+CONFIG_SYS_INIT_RAM_ADDR + 0x20000) | BATL_PP_RW ) -#define CONFIG_SYS_DBAT1U ((CONFIG_SYS_SDRAM_BASE+CONFIG_SYS_INIT_RAM_ADDR + 0x20000) | BATU_BL_256M | BATU_VS | BATU_VP) -*/ - -/* Init RAM in the CPU DCache (no backing memory) - */ -#define CONFIG_SYS_DBAT2L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) -#define CONFIG_SYS_DBAT2U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) -/* This used to be commented out */ -#define CONFIG_SYS_IBAT2L CONFIG_SYS_DBAT2L -/* This here too */ -#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U - - -/* I/O and PCI memory at 0xf0000000 - */ -#define CONFIG_SYS_DBAT3L (0xf0000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT3U (0xf0000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CONFIG_SYS_IBAT3L (0xf0000000 | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT3U (0xf0000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - */ -#define CONFIG_SYS_HZ 1000 -#define CONFIG_SYS_BUS_HZ 133000000 /* bus speed - 100 mhz */ -#define CONFIG_SYS_CPU_CLK 133000000 -#define CONFIG_SYS_BUS_CLK 133000000 - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of flash banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 8 /* Max number of sectors in one bank */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ - -/* - * Environment is stored in NVRAM. - */ -#define CONFIG_ENV_IS_IN_NVRAM 1 -#define CONFIG_ENV_ADDR 0xFD0E0000 /* This should be 0xFD0E0000, but we skip bytes to - * protect softex's settings for now. - * Original 768 bytes where not enough. - */ -#define CONFIG_ENV_SIZE 0x8000 /* Size of the Environment. See comment above */ - -#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 /* stdin/stdout/stderr are in environment */ -#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 1 -#define CONFIG_ENV_OVERWRITE 1 - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * L2 cache - */ -#define CONFIG_SYS_L2 -#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ - L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) -#define L2_ENABLE (L2_INIT | L2CR_L2E) - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - - -/*----------------------------------------------------------------------- - * IDE ATAPI Configuration - */ - -#define CONFIG_ATAPI 1 -#define CONFIG_SYS_IDE_MAXBUS 2 -#define CONFIG_SYS_IDE_MAXDEVICE 4 -#define CONFIG_ISO_PARTITION 1 - -#define CONFIG_SYS_ATA_BASE_ADDR 0xFE000000 /* was: via_get_base_addr() */ -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x1F0 -#define CONFIG_SYS_ATA_IDE1_OFFSET 0x170 - -#define CONFIG_SYS_ATA_REG_OFFSET 0 -#define CONFIG_SYS_ATA_DATA_OFFSET 0 -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0200 - -/*----------------------------------------------------------------------- - * Disk-On-Chip configuration - */ - -#define CONFIG_SYS_MAX_DOC_DEVICE 1 /* Max number of DOC devices */ - -#define CONFIG_SYS_DOC_SUPPORT_2000 -#undef CONFIG_SYS_DOC_SUPPORT_MILLENNIUM - -/*----------------------------------------------------------------------- - RTC -*/ -#define CONFIG_RTC_MC146818 - -/*----------------------------------------------------------------------- - * NS16550 Configuration - */ - -#define CONFIG_SYS_NS16550 - -#define CONFIG_SYS_NS16550_COM1 0xFE0003F8 -#define CONFIG_SYS_NS16550_COM2 0xFE0002F8 - -#define CONFIG_SYS_NS16550_REG_SIZE 1 - -/* base address for ISA I/O - */ -#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0xFE000000 - -/* ISA Interrupt stuff (taken from JWL) */ - -#define ISA_INT1_OCW1 0x21 -#define ISA_INT2_OCW1 0xA1 -#define ISA_INT1_OCW2 0x20 -#define ISA_INT2_OCW2 0xA0 -#define ISA_INT1_OCW3 0x20 -#define ISA_INT2_OCW3 0xA0 - -#define ISA_INT1_ICW1 0x20 -#define ISA_INT2_ICW1 0xA0 -#define ISA_INT1_ICW2 0x21 -#define ISA_INT2_ICW2 0xA1 -#define ISA_INT1_ICW3 0x21 -#define ISA_INT2_ICW3 0xA1 -#define ISA_INT1_ICW4 0x21 -#define ISA_INT2_ICW4 0xA1 - - -/* - * misc - */ - -#define CONFIG_NET_MULTI -#define CONFIG_SYS_BOARD_ASM_INIT -#define CONFIG_LAST_STAGE_INIT - -/* #define CONFIG_ETHADDR 00:09:D2:10:00:76 */ -/* #define CONFIG_IPADDR 192.168.0.2 */ -/* #define CONFIG_NETMASK 255.255.255.240 */ -/* #define CONFIG_GATEWAYIP 192.168.0.3 */ - -#define CONFIG_3COM -/* #define CONFIG_BOOTP_RANDOM_DELAY */ - -/* - * USB configuration - */ -#define CONFIG_USB_UHCI 1 -#define CONFIG_USB_STORAGE 1 -#define CONFIG_USB_KEYBOARD 1 -#define CONFIG_SYS_STDIO_DEREGISTER 1 /* needed by CONFIG_USB_KEYBOARD */ - -/* - * Autoboot stuff - */ -#define CONFIG_BOOTDELAY 5 /* Boot automatically after five seconds */ -#define CONFIG_PREBOOT "" -#define CONFIG_BOOTCOMMAND "fdcboot; diskboot" -#define CONFIG_MENUPROMPT \ - "Press any key to interrupt autoboot: %2d ", bootdelay -#define CONFIG_MENUKEY ' ' -#define CONFIG_MENUCOMMAND "menu" -/* #define CONFIG_AUTOBOOT_KEYED */ - -/* - * Extra ENV stuff - */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "stdout=vga\0" \ - "stdin=ps2kbd\0" \ - "ide_doreset=on\0" \ - "ide_maxbus=2\0" \ - "ide_cd_timeout=30\0" \ - "menucmd=menu\0" \ - "pci_irqa=9\0" \ - "pci_irqa_select=edge\0" \ - "pci_irqb=10\0" \ - "pci_irqb_select=edge\0" \ - "pci_irqc=11\0" \ - "pci_irqc_select=edge\0" \ - "pci_irqd=7\0" \ - "pci_irqd_select=edge\0" - - -/* #define CONFIG_MII 1 */ -/* #define CONFIG_BITBANGMII 1 */ - - -#endif /* __CONFIG_H */ -- cgit From cdc6363f423900645265563d705a0a5a964ae40c Mon Sep 17 00:00:00 2001 From: Poonam Aggrwal Date: Wed, 23 Jun 2010 19:42:07 +0530 Subject: 85xx/p1_p2_rdb: not able to modify "$bootfile" environment variable Because the variable was getting defined twice. Signed-off-by: Poonam Aggrwal Acked-by: Andy Fleming --- include/configs/P1_P2_RDB.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include') diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h index a9b4004c36..125911f2f8 100644 --- a/include/configs/P1_P2_RDB.h +++ b/include/configs/P1_P2_RDB.h @@ -568,7 +568,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); "netdev=eth0\0" \ "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ "loadaddr=1000000\0" \ - "bootfile=uImage\0" \ "tftpflash=tftpboot $loadaddr $uboot; " \ "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ "erase " MK_STR(TEXT_BASE) " +$filesize; " \ -- cgit From 178e26d75212f5aba63116585ef8f67ca6854e85 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Sat, 26 Jun 2010 23:46:40 +0200 Subject: image.h: remove bogus ';' after function declarations ISO C does not allow extra ';' outside of a function Signed-off-by: Wolfgang Denk --- include/image.h | 44 ++++++++++++++++++++++---------------------- 1 file changed, 22 insertions(+), 22 deletions(-) (limited to 'include') diff --git a/include/image.h b/include/image.h index 294eba5094..366b622ccf 100644 --- a/include/image.h +++ b/include/image.h @@ -362,23 +362,23 @@ static inline uint32_t image_get_header_size (void) { \ return uimage_to_cpu (hdr->ih_##f); \ } -image_get_hdr_l (magic); /* image_get_magic */ -image_get_hdr_l (hcrc); /* image_get_hcrc */ -image_get_hdr_l (time); /* image_get_time */ -image_get_hdr_l (size); /* image_get_size */ -image_get_hdr_l (load); /* image_get_load */ -image_get_hdr_l (ep); /* image_get_ep */ -image_get_hdr_l (dcrc); /* image_get_dcrc */ +image_get_hdr_l (magic) /* image_get_magic */ +image_get_hdr_l (hcrc) /* image_get_hcrc */ +image_get_hdr_l (time) /* image_get_time */ +image_get_hdr_l (size) /* image_get_size */ +image_get_hdr_l (load) /* image_get_load */ +image_get_hdr_l (ep) /* image_get_ep */ +image_get_hdr_l (dcrc) /* image_get_dcrc */ #define image_get_hdr_b(f) \ static inline uint8_t image_get_##f(const image_header_t *hdr) \ { \ return hdr->ih_##f; \ } -image_get_hdr_b (os); /* image_get_os */ -image_get_hdr_b (arch); /* image_get_arch */ -image_get_hdr_b (type); /* image_get_type */ -image_get_hdr_b (comp); /* image_get_comp */ +image_get_hdr_b (os) /* image_get_os */ +image_get_hdr_b (arch) /* image_get_arch */ +image_get_hdr_b (type) /* image_get_type */ +image_get_hdr_b (comp) /* image_get_comp */ static inline char *image_get_name (const image_header_t *hdr) { @@ -420,23 +420,23 @@ static inline ulong image_get_image_end (const image_header_t *hdr) { \ hdr->ih_##f = cpu_to_uimage (val); \ } -image_set_hdr_l (magic); /* image_set_magic */ -image_set_hdr_l (hcrc); /* image_set_hcrc */ -image_set_hdr_l (time); /* image_set_time */ -image_set_hdr_l (size); /* image_set_size */ -image_set_hdr_l (load); /* image_set_load */ -image_set_hdr_l (ep); /* image_set_ep */ -image_set_hdr_l (dcrc); /* image_set_dcrc */ +image_set_hdr_l (magic) /* image_set_magic */ +image_set_hdr_l (hcrc) /* image_set_hcrc */ +image_set_hdr_l (time) /* image_set_time */ +image_set_hdr_l (size) /* image_set_size */ +image_set_hdr_l (load) /* image_set_load */ +image_set_hdr_l (ep) /* image_set_ep */ +image_set_hdr_l (dcrc) /* image_set_dcrc */ #define image_set_hdr_b(f) \ static inline void image_set_##f(image_header_t *hdr, uint8_t val) \ { \ hdr->ih_##f = val; \ } -image_set_hdr_b (os); /* image_set_os */ -image_set_hdr_b (arch); /* image_set_arch */ -image_set_hdr_b (type); /* image_set_type */ -image_set_hdr_b (comp); /* image_set_comp */ +image_set_hdr_b (os) /* image_set_os */ +image_set_hdr_b (arch) /* image_set_arch */ +image_set_hdr_b (type) /* image_set_type */ +image_set_hdr_b (comp) /* image_set_comp */ static inline void image_set_name (image_header_t *hdr, const char *name) { -- cgit From c987f4753b0afadb38acd7e61df7ba11e8a0203f Mon Sep 17 00:00:00 2001 From: Felix Radensky Date: Mon, 28 Jun 2010 01:57:39 +0300 Subject: tsec: Fix eTSEC2 link problem on P2020RDB On P2020RDB eTSEC2 is connected to Vitesse VSC8221 PHY via SGMII. Current TBI PHY settings for SGMII mode cause link problems on this platform, link never comes up. Fix this by making TBI PHY settings configurable and add a working configuration for P2020RDB. Signed-off-by: Felix Radensky Acked-by: Andy Fleming Acked-by: Peter Tyser Tested-by: Peter Tyser --- include/configs/P1_P2_RDB.h | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'include') diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h index 125911f2f8..b891730789 100644 --- a/include/configs/P1_P2_RDB.h +++ b/include/configs/P1_P2_RDB.h @@ -425,6 +425,15 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_ETHPRIME "eTSEC1" #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ + +/* TBI PHY configuration for SGMII mode */ +#define CONFIG_TSEC_TBICR_SETTINGS ( \ + TBICR_PHY_RESET \ + | TBICR_ANEG_ENABLE \ + | TBICR_FULL_DUPLEX \ + | TBICR_SPEED1_SET \ + ) + #endif /* CONFIG_TSEC_ENET */ /* -- cgit From 161e4ae46046282fde6a69a0f1f80965f2a1b6f4 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Thu, 17 Jun 2010 07:01:40 +0200 Subject: powerpc: fix wrong comment at GOT definitions r12 is used for accessing the GOT not r14. Fix this in the comment. Signed-off-by: Heiko Schocher --- include/ppc_asm.tmpl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/ppc_asm.tmpl b/include/ppc_asm.tmpl index 84de146e5d..2db4784d3b 100644 --- a/include/ppc_asm.tmpl +++ b/include/ppc_asm.tmpl @@ -35,7 +35,7 @@ * * Stolen from prepboot/bootldr.h, (C) 1998 Gabriel Paubert, paubert@iram.es * - * Uses r14 to access the GOT + * Uses r12 to access the GOT */ #define START_GOT \ -- cgit From fe7cca715c69f66efdc9c64462b0fd0a445331a5 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 19 May 2010 11:13:24 +0200 Subject: ppc4xx: Enable booting with Option E on 460EX/EXr/GT This patch enables booting with option E on the PPC460EX/EXr/GT. When booting with Option E, the PLL is in bypass, CPR0_PLLC[ENG]=0. The Software Boot Configuration Procedure is needed to engage the PLL and perform a chip reset. Signed-off-by: Stefan Roese --- include/ppc440.h | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'include') diff --git a/include/ppc440.h b/include/ppc440.h index 5f87d2c600..c807dda2ae 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -1719,6 +1719,13 @@ #define CPR0_PERD_PERDV0_MASK 0x07000000 #endif +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) +#define CPR0_ICFG_RLI_MASK 0x80000000 + +#define CPR0_PLLC_RST 0x80000000 +#define CPR0_PLLC_ENG 0x40000000 +#endif + /*----------------------------------------------------------------------------- | PCI Internal Registers et. al. (accessed via plb) +----------------------------------------------------------------------------*/ -- cgit From 273ed0370d71a91c4e7a047bcfce0df77812f55e Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 19 May 2010 11:11:15 +0200 Subject: ppc4xx: Add T3COPR board support (PPC460GT based) This patch adds support for the T3CORP board, based on the AppliedMicro (APM) PPC460GT. Signed-off-by: Stefan Roese --- include/configs/t3corp.h | 544 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 544 insertions(+) create mode 100644 include/configs/t3corp.h (limited to 'include') diff --git a/include/configs/t3corp.h b/include/configs/t3corp.h new file mode 100644 index 0000000000..0ecc5b10de --- /dev/null +++ b/include/configs/t3corp.h @@ -0,0 +1,544 @@ +/* + * (C) Copyright 2010 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * t3corp.h - configuration for T3CORP (460GT) + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_460GT 1 /* Specific PPC460GT */ +#define CONFIG_440 1 +#define CONFIG_4xx 1 /* ... PPC4xx family */ + +#define CONFIG_HOSTNAME t3corp + +/* + * Include common defines/options for all AMCC/APM eval boards + */ +#include "amcc-common.h" + +#define CONFIG_SYS_CLK_FREQ 66666667 /* external freq to pll */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ +#define CONFIG_BOARD_EARLY_INIT_R 1 /* Call board_early_init_r */ +#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ +#define CONFIG_BOARD_TYPES 1 /* support board types */ +#define CONFIG_FIT +#define CFG_ALT_MEMTEST + +/* + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + */ +#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped PCI memory */ +#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */ +#define CONFIG_SYS_PCI_TARGBASE CONFIG_SYS_PCI_MEMBASE + +#define CONFIG_SYS_PCIE_MEMBASE 0xb0000000 /* mapped PCIe mem */ +#define CONFIG_SYS_PCIE_MEMSIZE 0x08000000 /* incr for PCIe */ +#define CONFIG_SYS_PCIE_BASE 0xc4000000 /* PCIe UTL regs */ + +#define CONFIG_SYS_PCIE0_CFGBASE 0xc0000000 +#define CONFIG_SYS_PCIE1_CFGBASE 0xc1000000 +#define CONFIG_SYS_PCIE0_XCFGBASE 0xc3000000 +#define CONFIG_SYS_PCIE1_XCFGBASE 0xc3001000 + +#define CONFIG_SYS_PCIE0_UTLBASE 0xc08010000ULL /* 36bit phys addr */ + +/* base address of inbound PCIe window */ +#define CONFIG_SYS_PCIE_INBOUND_BASE 0x000000000ULL /* 36bit phys addr */ + +/* EBC stuff */ +#define CONFIG_SYS_FLASH_BASE 0xFC000000 /* later mapped here */ +#define CONFIG_SYS_FLASH_SIZE (64 << 20) + +#define CONFIG_SYS_FPGA1_BASE 0xe0000000 +#define CONFIG_SYS_FPGA2_BASE 0xe0100000 +#define CONFIG_SYS_FPGA3_BASE 0xe0200000 + +#define CONFIG_SYS_BOOT_BASE_ADDR 0xFF000000 /* EBC Boot Space */ +#define CONFIG_SYS_FLASH_BASE_PHYS_H 0x4 +#define CONFIG_SYS_FLASH_BASE_PHYS_L 0xCC000000 +#define CONFIG_SYS_FLASH_BASE_PHYS \ + (((u64)CONFIG_SYS_FLASH_BASE_PHYS_H << 32) \ + | (u64)CONFIG_SYS_FLASH_BASE_PHYS_L) + +#define CONFIG_SYS_OCM_BASE 0xE3000000 /* OCM: 64k */ +#define CONFIG_SYS_SRAM_BASE 0xE8000000 /* SRAM: 256k */ +#define CONFIG_SYS_LOCAL_CONF_REGS 0xEF000000 + +#define CONFIG_SYS_PERIPHERAL_BASE 0xEF600000 /* internal periph. */ + +#define CONFIG_SYS_AHB_BASE 0xE2000000 /* int. AHB periph. */ + +/* + * Initial RAM & stack pointer (placed in OCM) + */ +#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */ +#define CONFIG_SYS_INIT_RAM_END (4 << 10) +#define CONFIG_SYS_GBL_DATA_SIZE 256 /* num bytes initial data */ +#define CONFIG_SYS_GBL_DATA_OFFSET \ + (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +/* + * Serial Port + */ +#undef CONFIG_UART1_CONSOLE /* define this if you want console on UART1 */ + +/* + * Environment + */ +/* + * Define here the location of the environment variables (flash). + */ +#define CONFIG_ENV_IS_IN_FLASH /* use flash for environment vars */ + +/* + * Flash related + */ +#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ +#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ +#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1 /* Use AMD reset cmd */ + +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sectors p. chip*/ + +#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase/ms*/ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write/ms*/ + +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buff'd writes (20x faster)*/ +#define CONFIG_SYS_FLASH_EMPTY_INFO /* 'E' for empty sector on flinfo */ + +#define CONFIG_ENV_SECT_SIZE 0x20000 /* sector size */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - \ + CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE 0x4000 /* env sector size */ + +/* Address and size of Redundant Environment Sector */ +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) + +/* + * DDR2 SDRAM + */ +#define CONFIG_AUTOCALIB "silent\0" /* default is non-verbose */ +#define CONFIG_PPC4xx_DDR_AUTOCALIBRATION /* IBM DDR autocalibration */ +#define DEBUG_PPC4xx_DDR_AUTOCALIBRATION /* dynamic DDR autocal debug */ +#undef CONFIG_PPC4xx_DDR_METHOD_A + +/* DDR1/2 SDRAM Device Control Register Data Values */ +/* Memory Queue */ +#define CONFIG_SYS_SDRAM_R0BAS (SDRAM_RXBAS_SDBA_ENCODE(0) | \ + SDRAM_RXBAS_SDSZ_256) +#define CONFIG_SYS_SDRAM_R1BAS 0x00000000 +#define CONFIG_SYS_SDRAM_R2BAS 0x00000000 +#define CONFIG_SYS_SDRAM_R3BAS 0x00000000 +#define CONFIG_SYS_SDRAM_PLBADDULL 0x00000000 +#define CONFIG_SYS_SDRAM_PLBADDUHB 0x00000008 +#define CONFIG_SYS_SDRAM_CONF1LL 0x80001C00 +#define CONFIG_SYS_SDRAM_CONF1HB 0x80001C80 +#define CONFIG_SYS_SDRAM_CONFPATHB 0x10a68000 + +#define CONFIG_DDR_ECC +#define CONFIG_SYS_MBYTES_SDRAM 256 + +#define CAS_LATENCY JEDEC_MA_MR_CL_DDR2_5_0_CLK + +/* DDR1/2 SDRAM Device Control Register Data Values */ +#define CONFIG_SYS_SDRAM0_MB0CF (SDRAM_RXBAS_SDAM_MODE7 | \ + SDRAM_RXBAS_SDBE_ENABLE) +#define CONFIG_SYS_SDRAM0_MB1CF SDRAM_RXBAS_SDBE_DISABLE +#define CONFIG_SYS_SDRAM0_MB2CF SDRAM_RXBAS_SDBE_DISABLE +#define CONFIG_SYS_SDRAM0_MB3CF SDRAM_RXBAS_SDBE_DISABLE +#define CONFIG_SYS_SDRAM0_MCOPT1 (SDRAM_MCOPT1_MCHK_GEN | \ + SDRAM_MCOPT1_PMU_OPEN | \ + SDRAM_MCOPT1_DMWD_32 | \ + SDRAM_MCOPT1_8_BANKS | \ + SDRAM_MCOPT1_DDR2_TYPE | \ + SDRAM_MCOPT1_QDEP | \ + SDRAM_MCOPT1_RWOO_DISABLED | \ + SDRAM_MCOPT1_WOOO_DISABLED | \ + SDRAM_MCOPT1_DREF_NORMAL) +#define CONFIG_SYS_SDRAM0_MCOPT2 0x00000000 +#define CONFIG_SYS_SDRAM0_MODT0 SDRAM_MODT_EB0W_ENABLE +#define CONFIG_SYS_SDRAM0_MODT1 0x00000000 +#define CONFIG_SYS_SDRAM0_MODT2 0x00000000 +#define CONFIG_SYS_SDRAM0_MODT3 0x00000000 +#define CONFIG_SYS_SDRAM0_CODT (SDRAM_CODT_RK0R_ON | \ + SDRAM_CODT_DQS_1_8_V_DDR2 | \ + SDRAM_CODT_IO_NMODE) +#define CONFIG_SYS_SDRAM0_RTR SDRAM_RTR_RINT_ENCODE(1560) +#define CONFIG_SYS_SDRAM0_INITPLR0 \ + (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(80) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_NOP)) +#define CONFIG_SYS_SDRAM0_INITPLR1 \ + (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(3) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE) | \ + SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \ + SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL)) +#define CONFIG_SYS_SDRAM0_INITPLR2 \ + (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(2) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \ + SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR2) | \ + SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR2_TEMP_COMMERCIAL)) +#define CONFIG_SYS_SDRAM0_INITPLR3 \ + (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(2) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \ + SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR3) | \ + SDRAM_INITPLR_IMA_ENCODE(0)) +#define CONFIG_SYS_SDRAM0_INITPLR4 \ + (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(2) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \ + SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \ + SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_DQS_ENABLE | \ + JEDEC_MA_EMR_RTT_150OHM)) +#define CONFIG_SYS_SDRAM0_INITPLR5 \ + (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(200) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \ + SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \ + SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \ + CAS_LATENCY | \ + JEDEC_MA_MR_BLEN_4 | \ + JEDEC_MA_MR_DLL_RESET)) +#define CONFIG_SYS_SDRAM0_INITPLR6 \ + (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(3) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE) | \ + SDRAM_INITPLR_IBA_ENCODE(0x0) | \ + SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL)) +#define CONFIG_SYS_SDRAM0_INITPLR7 \ + (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(26) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH)) +#define CONFIG_SYS_SDRAM0_INITPLR8 \ + (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(26) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH)) +#define CONFIG_SYS_SDRAM0_INITPLR9 \ + (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(26) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH)) +#define CONFIG_SYS_SDRAM0_INITPLR10 \ + (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(26) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH)) +#define CONFIG_SYS_SDRAM0_INITPLR11 \ + (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(2) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \ + SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \ + SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \ + CAS_LATENCY | \ + JEDEC_MA_MR_BLEN_4)) +#define CONFIG_SYS_SDRAM0_INITPLR12 \ + (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(2) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \ + SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \ + SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_ENTER | \ + JEDEC_MA_EMR_RDQS_DISABLE | \ + JEDEC_MA_EMR_DQS_ENABLE | \ + JEDEC_MA_EMR_RTT_150OHM | \ + JEDEC_MA_EMR_ODS_NORMAL)) +#define CONFIG_SYS_SDRAM0_INITPLR13 \ + (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(2) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \ + SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \ + SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_EXIT | \ + JEDEC_MA_EMR_RDQS_DISABLE | \ + JEDEC_MA_EMR_DQS_ENABLE | \ + JEDEC_MA_EMR_RTT_150OHM | \ + JEDEC_MA_EMR_ODS_NORMAL)) +#define CONFIG_SYS_SDRAM0_INITPLR14 SDRAM_INITPLR_DISABLE +#define CONFIG_SYS_SDRAM0_INITPLR15 SDRAM_INITPLR_DISABLE +#define CONFIG_SYS_SDRAM0_RQDC (SDRAM_RQDC_RQDE_ENABLE | \ + SDRAM_RQDC_RQFD_ENCODE(56)) +#define CONFIG_SYS_SDRAM0_RFDC SDRAM_RFDC_RFFD_ENCODE(599) +#define CONFIG_SYS_SDRAM0_RDCC (SDRAM_RDCC_RDSS_T2) +#define CONFIG_SYS_SDRAM0_DLCR (SDRAM_DLCR_DCLM_AUTO | \ + SDRAM_DLCR_DLCS_CONT_DONE | \ + SDRAM_DLCR_DLCV_ENCODE(155)) +#define CONFIG_SYS_SDRAM0_CLKTR SDRAM_CLKTR_CLKP_90_DEG_ADV +#define CONFIG_SYS_SDRAM0_WRDTR SDRAM_WRDTR_WTR_90_DEG_ADV +#define CONFIG_SYS_SDRAM0_SDTR1 (SDRAM_SDTR1_LDOF_2_CLK | \ + SDRAM_SDTR1_RTW_2_CLK | \ + SDRAM_SDTR1_RTRO_1_CLK) +#define CONFIG_SYS_SDRAM0_SDTR2 (SDRAM_SDTR2_RCD_3_CLK | \ + SDRAM_SDTR2_WTR_2_CLK | \ + SDRAM_SDTR2_XSNR_32_CLK | \ + SDRAM_SDTR2_WPC_4_CLK | \ + SDRAM_SDTR2_RPC_2_CLK | \ + SDRAM_SDTR2_RP_3_CLK | \ + SDRAM_SDTR2_RRD_2_CLK) +#define CONFIG_SYS_SDRAM0_SDTR3 (SDRAM_SDTR3_RAS_ENCODE(8) | \ + SDRAM_SDTR3_RC_ENCODE(11) | \ + SDRAM_SDTR3_XCS | \ + SDRAM_SDTR3_RFC_ENCODE(26)) +#define CONFIG_SYS_SDRAM0_MMODE (SDRAM_MMODE_WR_DDR2_3_CYC | \ + CAS_LATENCY | \ + SDRAM_MMODE_BLEN_4) +#define CONFIG_SYS_SDRAM0_MEMODE (SDRAM_MEMODE_DQS_ENABLE | \ + SDRAM_MEMODE_RTT_150OHM) + +/* + * I2C + */ +#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed */ + +#define CONFIG_SYS_I2C_MULTI_EEPROMS +#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1) +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 + +/* I2C bootstrap EEPROM */ +#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x52 +#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0 +#define CONFIG_4xx_CONFIG_BLOCKSIZE 16 + +/* + * Ethernet + */ +#define CONFIG_IBM_EMAC4_V4 1 + +#define CONFIG_HAS_ETH0 + +#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */ +#define CONFIG_M88E1111_PHY +/* Disable fiber since fiber/copper auto-selection doesn't seem to work */ +#define CONFIG_M88E1111_DISABLE_FIBER + +#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ +#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ +#define CONFIG_PHY_DYNAMIC_ANEG 1 + +/* + * Default environment variables + */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_AMCC_DEF_ENV \ + CONFIG_AMCC_DEF_ENV_POWERPC \ + CONFIG_AMCC_DEF_ENV_NOR_UPD \ + "kernel_addr=fc000000\0" \ + "fdt_addr=fc1e0000\0" \ + "ramdisk_addr=fc200000\0" \ + "pciconfighost=1\0" \ + "pcie_mode=RP:RP\0" \ + "" + +/* + * Commands additional to the ones defined in amcc-common.h + */ +#define CONFIG_CMD_CHIP_CONFIG +#define CONFIG_CMD_PCI +#define CONFIG_CMD_SDRAM + +/* + * PCI stuff + */ +/* General PCI */ +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_PCI_CONFIG_HOST_BRIDGE + +/* Board-specific PCI, no PCI support, only PCIe */ +#undef CONFIG_SYS_PCI_TARGET_INIT +#undef CONFIG_SYS_PCI_MASTER_INIT + +#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* IBM */ +#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ + + +/* + * External Bus Controller (EBC) Setup + */ + +/* + * T3CORP has 64MBytes of NOR flash (Spansion 29GL512), but the + * boot EBC mapping only supports a maximum of 16MBytes + * (4.ff00.0000 - 4.ffff.ffff). + * To solve this problem, the flash has to get remapped to another + * EBC address which accepts bigger regions: + * + * 0xfc00.0000 -> 4.cc00.0000 + */ + +/* Memory Bank 0 (NOR-flash) */ +#define CONFIG_SYS_EBC_PB0AP (EBC_BXAP_BME_DISABLED | \ + EBC_BXAP_TWT_ENCODE(16) | \ + EBC_BXAP_BCE_DISABLE | \ + EBC_BXAP_BCT_2TRANS | \ + EBC_BXAP_CSN_ENCODE(1) | \ + EBC_BXAP_OEN_ENCODE(1) | \ + EBC_BXAP_WBN_ENCODE(1) | \ + EBC_BXAP_WBF_ENCODE(1) | \ + EBC_BXAP_TH_ENCODE(7) | \ + EBC_BXAP_RE_DISABLED | \ + EBC_BXAP_SOR_DELAYED | \ + EBC_BXAP_BEM_WRITEONLY | \ + EBC_BXAP_PEN_DISABLED) +#define CONFIG_SYS_EBC_PB0CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_BOOT_BASE_ADDR) | \ + EBC_BXCR_BS_16MB | \ + EBC_BXCR_BU_RW | \ + EBC_BXCR_BW_16BIT) + +/* Memory Bank 1 (FPGA 1) */ +#define CONFIG_SYS_EBC_PB1AP (EBC_BXAP_BME_DISABLED | \ + EBC_BXAP_TWT_ENCODE(5) | \ + EBC_BXAP_CSN_ENCODE(0) | \ + EBC_BXAP_OEN_ENCODE(4) | \ + EBC_BXAP_WBN_ENCODE(0) | \ + EBC_BXAP_WBF_ENCODE(0) | \ + EBC_BXAP_TH_ENCODE(1) | \ + EBC_BXAP_RE_DISABLED | \ + EBC_BXAP_SOR_DELAYED | \ + EBC_BXAP_BEM_RW | \ + EBC_BXAP_PEN_DISABLED) +#define CONFIG_SYS_EBC_PB1CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA1_BASE) | \ + EBC_BXCR_BS_1MB | \ + EBC_BXCR_BU_RW | \ + EBC_BXCR_BW_32BIT) + +/* Memory Bank 2 (FPGA 2) */ +#define CONFIG_SYS_EBC_PB2AP (EBC_BXAP_BME_DISABLED | \ + EBC_BXAP_TWT_ENCODE(5) | \ + EBC_BXAP_CSN_ENCODE(0) | \ + EBC_BXAP_OEN_ENCODE(4) | \ + EBC_BXAP_WBN_ENCODE(0) | \ + EBC_BXAP_WBF_ENCODE(0) | \ + EBC_BXAP_TH_ENCODE(1) | \ + EBC_BXAP_RE_DISABLED | \ + EBC_BXAP_SOR_DELAYED | \ + EBC_BXAP_BEM_RW | \ + EBC_BXAP_PEN_DISABLED) +#define CONFIG_SYS_EBC_PB2CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA2_BASE) | \ + EBC_BXCR_BS_1MB | \ + EBC_BXCR_BU_RW | \ + EBC_BXCR_BW_32BIT) + +/* Memory Bank 3 (FPGA 3) */ +#define CONFIG_SYS_EBC_PB3AP (EBC_BXAP_BME_DISABLED | \ + EBC_BXAP_TWT_ENCODE(5) | \ + EBC_BXAP_CSN_ENCODE(0) | \ + EBC_BXAP_OEN_ENCODE(4) | \ + EBC_BXAP_WBN_ENCODE(0) | \ + EBC_BXAP_WBF_ENCODE(0) | \ + EBC_BXAP_TH_ENCODE(1) | \ + EBC_BXAP_RE_DISABLED | \ + EBC_BXAP_SOR_DELAYED | \ + EBC_BXAP_BEM_RW | \ + EBC_BXAP_PEN_DISABLED) +#define CONFIG_SYS_EBC_PB3CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA3_BASE) | \ + EBC_BXCR_BS_1MB | \ + EBC_BXCR_BU_RW | \ + EBC_BXCR_BW_32BIT) + +/* + * PPC4xx GPIO Configuration + */ + +#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO Alternate1 Alternate2 Alternate3 */ \ +{ \ +/* GPIO Core 0 */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 GMC1TxD(0) USB2HostD(0) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 GMC1TxD(1) USB2HostD(1) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 GMC1TxD(2) USB2HostD(2) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 GMC1TxD(3) USB2HostD(3) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 GMC1TxD(4) USB2HostD(4) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 GMC1TxD(5) USB2HostD(5) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 GMC1TxD(6) USB2HostD(6) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 GMC1TxD(7) USB2HostD(7) */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 GMC1RxD(0) USB2OTGD(0) */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 GMC1RxD(1) USB2OTGD(1) */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 GMC1RxD(2) USB2OTGD(2) */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 GMC1RxD(3) USB2OTGD(3) */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO12 GMC1RxD(4) USB2OTGD(4) */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO13 GMC1RxD(5) USB2OTGD(5) */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO14 GMC1RxD(6) USB2OTGD(6) */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO15 GMC1RxD(7) USB2OTGD(7) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMC1TxER USB2HostStop */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMC1CD USB2HostNext */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMC1RxER USB2HostDir */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 GMC1TxEN USB2OTGStop */ \ +{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 GMC1CRS USB2OTGNext */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 GMC1RxDV USB2OTGDir */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO22 NFRDY */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 NFREN */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 NFWEN */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 NFCLE */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 NFALE */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO27 IRQ(0) */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO28 IRQ(1) */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO29 IRQ(2) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO30 PerPar0 DMAReq2 IRQ(7)*/ \ +{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO31 PerPar1 DMAAck2 IRQ(8)*/ \ +}, \ +{ \ +/* GPIO Core 1 */ \ +{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO32 PerPar2 EOT2/TC2 IRQ(9)*/ \ +{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO33 PerPar3 DMAReq3 IRQ(4)*/ \ +{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_1}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \ +{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \ +{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N DMAAck3 UART3_SIN*/ \ +{GPIO1_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N EOT3/TC3 UART3_SOUT*/ \ +{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \ +{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N UART1_SIN */ \ +{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 IRQ(3) */ \ +{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 CS(1) */ \ +{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 CS(2) */ \ +{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 CS(3) DMAReq1 IRQ(10)*/ \ +{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO44 CS(4) DMAAck1 IRQ(11)*/ \ +{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO45 CS(5) EOT/TC1 IRQ(12)*/ \ +{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 PerAddr(5) DMAReq0 IRQ(13)*/ \ +{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 PerAddr(6) DMAAck0 IRQ(14)*/ \ +{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 PerAddr(7) EOT/TC0 IRQ(15)*/ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \ +} \ +} + +#endif /* __CONFIG_H */ -- cgit From 0e70aaa485384fda5f757d5a1bd106b359c06e9c Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Sun, 20 Jun 2010 21:26:20 +0200 Subject: shannon/INFERNO: fix special handling of environment configuration Remove some INFERNO related #ifdef's from common environment code by fixing the board configuration settings (add CONFIG_ENV_SECT_SIZE). While we are at it, fix comment which incorrectly talks about 4 KB environment size, while it's actually 0x4000 = 16 KiB. Signed-off-by: Wolfgang Denk Cc: Rolf Offermanns --- include/configs/shannon.h | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/include/configs/shannon.h b/include/configs/shannon.h index 13cc5ff3b7..d848915d0e 100644 --- a/include/configs/shannon.h +++ b/include/configs/shannon.h @@ -161,12 +161,13 @@ #define CONFIG_ENV_IS_IN_FLASH 1 #ifdef CONFIG_INFERNO -/* we take the last sector, 128 KB in size, but we only use 4 KB of it for stack reasons */ +/* we take the last sector, 128 KB in size, but we only use 16 KB of it for stack reasons */ #define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x003E0000) /* Addr of Environment Sector */ -#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ +#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment */ +#define CONFIG_ENV_SECT_SIZE (128 << 10) /* size of environment sector */ #else #define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x1C000) /* Addr of Environment Sector */ -#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ +#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment */ #endif /*----------------------------------------------------------------------- -- cgit From d9c27253ce333e2086b2d758b42dc3ecb8b34c3d Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Sun, 20 Jun 2010 17:14:14 +0200 Subject: Make *printf() return "int" instead of "void" Change the return type of the *printf() functions to the standard "int"; no changes are needed but returning the already available length count. This will save a few additional strlen() calls later... Signed-off-by: Wolfgang Denk --- include/common.h | 8 ++++---- include/exports.h | 4 ++-- 2 files changed, 6 insertions(+), 6 deletions(-) (limited to 'include') diff --git a/include/common.h b/include/common.h index 8bca04fdd7..48f6a1a074 100644 --- a/include/common.h +++ b/include/common.h @@ -663,7 +663,7 @@ int disable_ctrlc (int); /* 1 to disable, 0 to enable Control-C detect */ * STDIO based functions (can always be used) */ /* serial stuff */ -void serial_printf (const char *fmt, ...) +int serial_printf (const char *fmt, ...) __attribute__ ((format (__printf__, 1, 2))); /* stdin */ int getc(void); @@ -672,9 +672,9 @@ int tstc(void); /* stdout */ void putc(const char c); void puts(const char *s); -void printf(const char *fmt, ...) +int printf(const char *fmt, ...) __attribute__ ((format (__printf__, 1, 2))); -void vprintf(const char *fmt, va_list args); +int vprintf(const char *fmt, va_list args); /* stderr */ #define eputc(c) fputc(stderr, c) @@ -689,7 +689,7 @@ void vprintf(const char *fmt, va_list args); #define stderr 2 #define MAX_FILES 3 -void fprintf(int file, const char *fmt, ...) +int fprintf(int file, const char *fmt, ...) __attribute__ ((format (__printf__, 2, 3))); void fputs(int file, const char *s); void fputc(int file, const char c); diff --git a/include/exports.h b/include/exports.h index c3a5d2f32e..9588bc94e4 100644 --- a/include/exports.h +++ b/include/exports.h @@ -11,14 +11,14 @@ int getc(void); int tstc(void); void putc(const char); void puts(const char*); -void printf(const char* fmt, ...); +int printf(const char* fmt, ...); void install_hdlr(int, interrupt_handler_t*, void*); void free_hdlr(int); void *malloc(size_t); void free(void*); void __udelay(unsigned long); unsigned long get_timer(unsigned long); -void vprintf(const char *, va_list); +int vprintf(const char *, va_list); void do_reset (void); unsigned long simple_strtoul(const char *cp,char **endp,unsigned int base); char *getenv (char *name); -- cgit From b218ccb5435e64ac2318bb8b6c9594ef1cc724cd Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Tue, 22 Jun 2010 15:44:16 +0200 Subject: Redundant environment: move flag definitions to header file Instead of defining the flags sevaral times in different source files (which is error prone), move them to a central place in a header file. Signed-off-by: Wolfgang Denk --- include/environment.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'include') diff --git a/include/environment.h b/include/environment.h index b9924fd778..203f731967 100644 --- a/include/environment.h +++ b/include/environment.h @@ -122,6 +122,9 @@ #ifdef CONFIG_SYS_REDUNDAND_ENVIRONMENT # define ENV_HEADER_SIZE (sizeof(uint32_t) + 1) + +# define ACTIVE_FLAG 1 +# define OBSOLETE_FLAG 0 #else # define ENV_HEADER_SIZE (sizeof(uint32_t)) #endif -- cgit From 54841ab50c20d6fa6c9cc3eb826989da3a22d934 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Mon, 28 Jun 2010 22:00:46 +0200 Subject: Make sure that argv[] argument pointers are not modified. The hush shell dynamically allocates (and re-allocates) memory for the argument strings in the "char *argv[]" argument vector passed to commands. Any code that modifies these pointers will cause serious corruption of the malloc data structures and crash U-Boot, so make sure the compiler can check that no such modifications are being done by changing the code into "char * const argv[]". This modification is the result of debugging a strange crash caused after adding a new command, which used the following argument processing code which has been working perfectly fine in all Unix systems since version 6 - but not so in U-Boot: int main (int argc, char **argv) { while (--argc > 0 && **++argv == '-') { /* ====> */ while (*++*argv) { switch (**argv) { case 'd': debug++; break; ... default: usage (); } } } ... } The line marked "====>" will corrupt the malloc data structures and usually cause U-Boot to crash when the next command gets executed by the shell. With the modification, the compiler will prevent this with an error: increment of read-only location '*argv' N.B.: The code above can be trivially rewritten like this: while (--argc > 0 && **++argv == '-') { char *arg = *argv; while (*++arg) { switch (*arg) { ... Signed-off-by: Wolfgang Denk Acked-by: Mike Frysinger --- include/bedbug/type.h | 2 +- include/command.h | 8 ++++---- include/common.h | 2 +- include/exports.h | 2 +- include/image.h | 4 ++-- include/kgdb.h | 2 +- include/vxworks.h | 2 +- 7 files changed, 11 insertions(+), 11 deletions(-) (limited to 'include') diff --git a/include/bedbug/type.h b/include/bedbug/type.h index 38ee9ded73..b7b447b1fe 100644 --- a/include/bedbug/type.h +++ b/include/bedbug/type.h @@ -15,7 +15,7 @@ typedef struct { int current_bp; struct pt_regs *regs; - void (*do_break) (cmd_tbl_t *, int, int, char *[]); + void (*do_break) (cmd_tbl_t *, int, int, char * const []); void (*break_isr) (struct pt_regs *); int (*find_empty) (void); int (*set) (int, unsigned long); diff --git a/include/command.h b/include/command.h index 55caa6eaf8..9144d69206 100644 --- a/include/command.h +++ b/include/command.h @@ -48,14 +48,14 @@ struct cmd_tbl_s { int maxargs; /* maximum number of arguments */ int repeatable; /* autorepeat allowed? */ /* Implementation function */ - int (*cmd)(struct cmd_tbl_s *, int, int, char *[]); + int (*cmd)(struct cmd_tbl_s *, int, int, char * const []); char *usage; /* Usage message (short) */ #ifdef CONFIG_SYS_LONGHELP char *help; /* Help message (long) */ #endif #ifdef CONFIG_AUTO_COMPLETE /* do auto completion on the arguments */ - int (*complete)(int argc, char *argv[], char last_char, int maxv, char *cmdv[]); + int (*complete)(int argc, char * const argv[], char last_char, int maxv, char *cmdv[]); #endif }; @@ -67,7 +67,7 @@ extern cmd_tbl_t __u_boot_cmd_end; /* common/command.c */ int _do_help (cmd_tbl_t *cmd_start, int cmd_items, cmd_tbl_t * cmdtp, int - flag, int argc, char *argv[]); + flag, int argc, char * const argv[]); cmd_tbl_t *find_cmd(const char *cmd); cmd_tbl_t *find_cmd_tbl (const char *cmd, cmd_tbl_t *table, int table_len); @@ -83,7 +83,7 @@ extern int cmd_auto_complete(const char *const prompt, char *buf, int *np, int * * * All commands use a common argument format: * - * void function (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); + * void function (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); */ typedef void command_t (cmd_tbl_t *, int, int, char *[]); diff --git a/include/common.h b/include/common.h index 48f6a1a074..eddec22752 100644 --- a/include/common.h +++ b/include/common.h @@ -718,7 +718,7 @@ void show_boot_progress(int val); int cpu_status(int nr); int cpu_reset(int nr); int cpu_disable(int nr); -int cpu_release(int nr, int argc, char *argv[]); +int cpu_release(int nr, int argc, char * const argv[]); #endif #endif /* __ASSEMBLY__ */ diff --git a/include/exports.h b/include/exports.h index 9588bc94e4..1d79a3162c 100644 --- a/include/exports.h +++ b/include/exports.h @@ -35,7 +35,7 @@ int i2c_read (uchar, uint, int , uchar* , int); #endif #include -void app_startup(char **); +void app_startup(char * const *); #endif /* ifndef __ASSEMBLY__ */ diff --git a/include/image.h b/include/image.h index 366b622ccf..bcc08d1a73 100644 --- a/include/image.h +++ b/include/image.h @@ -328,12 +328,12 @@ int genimg_get_format (void *img_addr); int genimg_has_config (bootm_headers_t *images); ulong genimg_get_image (ulong img_addr); -int boot_get_ramdisk (int argc, char *argv[], bootm_headers_t *images, +int boot_get_ramdisk (int argc, char * const argv[], bootm_headers_t *images, uint8_t arch, ulong *rd_start, ulong *rd_end); #ifdef CONFIG_OF_LIBFDT -int boot_get_fdt (int flag, int argc, char *argv[], bootm_headers_t *images, +int boot_get_fdt (int flag, int argc, char * const argv[], bootm_headers_t *images, char **of_flat_tree, ulong *of_size); int boot_relocate_fdt (struct lmb *lmb, ulong bootmap_base, char **of_flat_tree, ulong *of_size); diff --git a/include/kgdb.h b/include/kgdb.h index f543cd6e18..b6ba742ad3 100644 --- a/include/kgdb.h +++ b/include/kgdb.h @@ -55,7 +55,7 @@ extern int kgdb_getregs(struct pt_regs *, char *, int); extern void kgdb_putreg(struct pt_regs *, int, char *, int); extern void kgdb_putregs(struct pt_regs *, char *, int); extern int kgdb_trap(struct pt_regs *); -extern void kgdb_breakpoint(int argc, char *argv[]); +extern void kgdb_breakpoint(int argc, char * const argv[]); /* these functions are provided by the platform serial driver */ extern void kgdb_serial_init(void); diff --git a/include/vxworks.h b/include/vxworks.h index 1633904bd8..917a9ff856 100644 --- a/include/vxworks.h +++ b/include/vxworks.h @@ -24,7 +24,7 @@ #ifndef _VXWORKS_H_ #define _VXWORKS_H_ -int do_bootvx(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); +int do_bootvx(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); /* * Use bootaddr to find the location in memory that VxWorks -- cgit