From b209a114829dc8a7a0e39a9335b6e4aebf9742cb Mon Sep 17 00:00:00 2001 From: Dirk Eibach Date: Fri, 17 Jul 2009 14:16:40 +0200 Subject: ppc4xx: Add DL-Vision 405EP board support Board support for the Guntermann & Drunck DL-Vision. Signed-off-by: Dirk Eibach Signed-off-by: Stefan Roese --- include/configs/dlvision.h | 225 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 225 insertions(+) create mode 100644 include/configs/dlvision.h (limited to 'include') diff --git a/include/configs/dlvision.h b/include/configs/dlvision.h new file mode 100644 index 0000000000..4533799971 --- /dev/null +++ b/include/configs/dlvision.h @@ -0,0 +1,225 @@ +/* + * (C) Copyright 2009 + * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_405EP 1 /* this is a PPC405 CPU */ +#define CONFIG_4xx 1 /* member of PPC4xx family */ +#define CONFIG_DLVISION 1 /* on a Neo board */ + +/* + * Include common defines/options for all AMCC eval boards + */ +#define CONFIG_HOSTNAME dlvision +#define CONFIG_IDENT_STRING " dlvision 0.01" +#include "amcc-common.h" + +#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f */ +#define CONFIG_MISC_INIT_R /* call misc_init_r */ + +#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ + +/* + * Configure PLL + */ +#define PLLMR0_DEFAULT PLLMR0_266_133_66_33 +#define PLLMR1_DEFAULT PLLMR1_266_133_66_33 + +/* new uImage format support */ +#define CONFIG_FIT +#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ + +#define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */ + +/* + * Default environment variables + */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_AMCC_DEF_ENV \ + CONFIG_AMCC_DEF_ENV_POWERPC \ + CONFIG_AMCC_DEF_ENV_NOR_UPD \ + "kernel_addr=fc000000\0" \ + "fdt_addr=fc1e0000\0" \ + "ramdisk_addr=fc200000\0" \ + "" + +#define CONFIG_PHY_ADDR 4 /* PHY address */ +#define CONFIG_HAS_ETH0 +#define CONFIG_HAS_ETH1 +#define CONFIG_PHY1_ADDR 0xc /* EMAC1 PHY address */ +#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ + +/* + * Commands additional to the ones defined in amcc-common.h + */ +#define CONFIG_CMD_CACHE +#undef CONFIG_CMD_EEPROM + +/* + * SDRAM configuration (please see cpu/ppc/sdram.[ch]) + */ +#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ + +/* SDRAM timings used in datasheet */ +#define CONFIG_SYS_SDRAM_CL 3 /* CAS latency */ +#define CONFIG_SYS_SDRAM_tRP 20 /* PRECHARGE command period */ +#define CONFIG_SYS_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE period */ +#define CONFIG_SYS_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */ +#define CONFIG_SYS_SDRAM_tRFC 66 /* Auto refresh period */ + +/* + * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1. + * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31. + * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD. + * The Linux BASE_BAUD define should match this configuration. + * baseBaud = cpuClock/(uartDivisor*16) + * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock, + * set Linux BASE_BAUD to 403200. + */ +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */ +#undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ +#define CONFIG_SYS_BASE_BAUD 691200 + +/* + * I2C stuff + */ +#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address*/ + +/* + * FLASH organization + */ +#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ +#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ + +#define CONFIG_SYS_FLASH_BASE 0xFC000000 +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sectors per chip*/ + +#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase/ms */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write/ms */ + +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buff'd writes */ +#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protect */ + +#define CONFIG_SYS_FLASH_EMPTY_INFO /* 'E' for empty sector on flinfo */ +#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* no warn upon unknown flash */ + +#ifdef CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ +#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) +#endif + +/* + * PPC405 GPIO Configuration + */ +#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO Alternate1 */ \ +{ \ +/* GPIO Core 0 */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \ +{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO5 TS3 */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO6 TS4 */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO7 TS5 */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO9 TrcClk */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 */ \ +{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 */ \ +{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 */ \ +{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 */ \ +{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 */ \ +{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 */ \ +{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD */ \ +{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \ +{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \ +{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 */ \ +{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 */ \ +} \ +} + +/* + * Definitions for initial stack pointer and data area (in data cache) + */ +/* use on chip memory (OCM) for temperary stack until sdram is tested */ +#define CONFIG_SYS_TEMP_STACK_OCM 1 + +/* On Chip Memory location */ +#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 +#define CONFIG_SYS_OCM_DATA_SIZE 0x1000 +#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */ +#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area */ + +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size/bytes res'd for init data*/ +#define CONFIG_SYS_GBL_DATA_OFFSET \ + (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +/* + * External Bus Controller (EBC) Setup + */ + +/* Memory Bank 0 (NOR-FLASH) initialization */ +#define CONFIG_SYS_EBC_PB0AP 0x92015480 +/* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit */ +#define CONFIG_SYS_EBC_PB0CR 0xFC0DA000 + +/* Memory Bank 1 (NVRAM) initializatio */ +#define CONFIG_SYS_EBC_PB1AP 0x92015480 +/* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit */ +#define CONFIG_SYS_EBC_PB1CR 0xFB858000 + +/* Memory Bank 2 (UART) initialization */ +#define CONFIG_UART_BASE 0x7f100000 +#define CONFIG_SYS_EBC_PB2AP 0x92015480 +/* BAS=0x7f1,BS=1MB,BU=R/W,BW=8bit */ +#define CONFIG_SYS_EBC_PB2CR 0x7f118000 + +/* Memory Bank 3 (Latches) initialization */ +#define CONFIG_SYS_LATCH_BASE 0x7f200000 +#define CONFIG_SYS_EBC_PB3AP 0x92015480 +/* BAS=0x7f2,BS=1MB,BU=R/W,BW=16bit */ +#define CONFIG_SYS_EBC_PB3CR 0x7f21a000 + +#endif /* __CONFIG_H */ -- cgit From 11ad309c183b176d8866944026a63c0f1c626f56 Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Fri, 17 Jul 2009 19:01:03 -0500 Subject: xpedite1k: Use standard CFI flash driver Using the CFI flash driver will allow write access to the 16MB Intel StrataFlash present on the XPedite1000. The 512KB socketed (non CFI-compliant flash) will no longer be writable. The mapping of the 16MB Strata flash was moved to 0xff000000 and the 512KB AMD socketed flash was moved to 0xfe000000. Signed-off-by: Peter Tyser Signed-off-by: Stefan Roese --- include/configs/XPEDITE1K.h | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/include/configs/XPEDITE1K.h b/include/configs/XPEDITE1K.h index 74e55c91cb..1eb638b651 100644 --- a/include/configs/XPEDITE1K.h +++ b/include/configs/XPEDITE1K.h @@ -52,9 +52,9 @@ * actual resources get mapped (not physical addresses) *----------------------------------------------------------------------*/ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */ -#define CONFIG_SYS_FLASH_BASE 0xfff80000 /* start of FLASH */ +#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* start of monitor */ +#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ #define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */ #define CONFIG_SYS_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */ #define CONFIG_SYS_ISRAM_BASE 0xc0000000 /* internal SRAM */ @@ -128,7 +128,11 @@ extern void out32(unsigned int, unsigned long); * FLASH related *----------------------------------------------------------------------*/ #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 8 /* sectors per device */ +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} +#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE #undef CONFIG_SYS_FLASH_CHECKSUM #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -- cgit From c86d00a2ed923002f1ab0bfb0a925522628302e9 Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Fri, 17 Jul 2009 19:01:04 -0500 Subject: xpedite1k: Remove CONFIG_SYS_DRAM_TEST support POST or command line tests provide similar functionality Signed-off-by: Peter Tyser Signed-off-by: Stefan Roese --- include/configs/XPEDITE1K.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include') diff --git a/include/configs/XPEDITE1K.h b/include/configs/XPEDITE1K.h index 1eb638b651..57878a22fd 100644 --- a/include/configs/XPEDITE1K.h +++ b/include/configs/XPEDITE1K.h @@ -39,7 +39,6 @@ #define CONFIG_440GX 1 /* 440 GX */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ #define CONFIG_MISC_INIT_R -#undef CONFIG_SYS_DRAM_TEST /* Disable-takes long time! */ #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ -- cgit From 086ff34a3a7e5e595630d658c1c13778399452d1 Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Fri, 17 Jul 2009 19:01:06 -0500 Subject: xpedite1k: Remove support for reading MACs from EEPROM By default, the XPedite1000 comes installed with xMon, a proprietary bootloader. xMon stores its MAC address in an onboard EEPROM. Rather than requiring a non-standard location in the EEPROM to be reserved for MAC addresses, store the MAC addresses in U-Boot's standard environment. A U-Boot application or OS application can be used to migrate xMon MAC addresses to U-Boot's environment if necessary. Signed-off-by: Peter Tyser Signed-off-by: Stefan Roese --- include/configs/XPEDITE1K.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include') diff --git a/include/configs/XPEDITE1K.h b/include/configs/XPEDITE1K.h index 57878a22fd..93c4b0aeea 100644 --- a/include/configs/XPEDITE1K.h +++ b/include/configs/XPEDITE1K.h @@ -38,7 +38,6 @@ #define CONFIG_440 1 #define CONFIG_440GX 1 /* 440 GX */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ -#define CONFIG_MISC_INIT_R #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ -- cgit From e02990764c7415c84668823a0fc8c5b4dd8d8cf0 Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Fri, 17 Jul 2009 19:01:07 -0500 Subject: xpedite1k: Cleanup coding style Signed-off-by: Peter Tyser Signed-off-by: Stefan Roese --- include/configs/XPEDITE1K.h | 216 +++++++++++++++++++------------------------- 1 file changed, 91 insertions(+), 125 deletions(-) (limited to 'include') diff --git a/include/configs/XPEDITE1K.h b/include/configs/XPEDITE1K.h index 93c4b0aeea..f141398128 100644 --- a/include/configs/XPEDITE1K.h +++ b/include/configs/XPEDITE1K.h @@ -20,51 +20,48 @@ * MA 02111-1307 USA */ -/************************************************************************ +/* * config for XPedite1000 from XES Inc. * Ported from EBONY config by Travis B. Sawyer * (C) Copyright 2003 Sandburst Corporation * board/config_EBONY.h - configuration for AMCC 440GP Ref (Ebony) - ***********************************************************************/ + */ #ifndef __CONFIG_H #define __CONFIG_H -/*----------------------------------------------------------------------- - * High Level Configuration Options - *----------------------------------------------------------------------*/ +/* High Level Configuration Options */ #define CONFIG_XPEDITE1K 1 /* Board is XPedite 1000 */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ +#define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_440 1 #define CONFIG_440GX 1 /* 440 GX */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ - /* POST support */ -#define CONFIG_POST (CONFIG_SYS_POST_RTC | \ +#define CONFIG_POST (CONFIG_SYS_POST_RTC | \ CONFIG_SYS_POST_I2C) -/*----------------------------------------------------------------------- +/* * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */ -#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH */ + */ +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */ +#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH */ -#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ -#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */ -#define CONFIG_SYS_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */ -#define CONFIG_SYS_ISRAM_BASE 0xc0000000 /* internal SRAM */ -#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */ +#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ +#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */ +#define CONFIG_SYS_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */ +#define CONFIG_SYS_ISRAM_BASE 0xc0000000 /* internal SRAM */ +#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */ -#define CONFIG_SYS_NVRAM_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000) -#define CONFIG_SYS_GPIO_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000700) +#define CONFIG_SYS_NVRAM_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000) +#define CONFIG_SYS_GPIO_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000700) -#define USR_LED0 0x00000080 -#define USR_LED1 0x00000100 -#define USR_LED2 0x00000200 -#define USR_LED3 0x00000400 +#define USR_LED0 0x00000080 +#define USR_LED1 0x00000100 +#define USR_LED2 0x00000200 +#define USR_LED3 0x00000400 #ifndef __ASSEMBLY__ extern unsigned long in32(unsigned int); @@ -81,50 +78,34 @@ extern void out32(unsigned int, unsigned long); #define LED3_OFF() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) | USR_LED3)) #endif -/*----------------------------------------------------------------------- - * Initial RAM & stack pointer (placed in internal SRAM) - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_TEMP_STACK_OCM 1 -#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ - +/* Initial RAM & stack pointer (placed in internal SRAM) */ +#define CONFIG_SYS_TEMP_STACK_OCM 1 +#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE +#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */ +#define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in RAM */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) -#define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 0x4) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_POST_WORD_ADDR +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 0x4) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_POST_WORD_ADDR -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/ +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc */ -/*----------------------------------------------------------------------- - * Serial Port - *----------------------------------------------------------------------*/ +/* Serial Port */ #undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_BAUDRATE 9600 +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400} -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400} +/* RTC: STMicro M41T00 */ +#define CONFIG_RTC_M41T11 1 +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 +#define CONFIG_SYS_M41T11_BASE_YEAR 2000 -/*----------------------------------------------------------------------- - * NVRAM/RTC - * - * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located. - * The DS1743 code assumes this condition (i.e. -- it assumes the base - * address for the RTC registers is: - * - * CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_SIZE - * - *----------------------------------------------------------------------*/ -/* TBS: Xpedite 1000 has STMicro M41T00 via IIC */ -#define CONFIG_RTC_M41T11 1 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 -#define CONFIG_SYS_M41T11_BASE_YEAR 2000 - -/*----------------------------------------------------------------------- +/* * FLASH related - *----------------------------------------------------------------------*/ + */ #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ @@ -133,70 +114,60 @@ extern void out32(unsigned int, unsigned long); #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE #undef CONFIG_SYS_FLASH_CHECKSUM -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -/*----------------------------------------------------------------------- - * DDR SDRAM - *----------------------------------------------------------------------*/ -#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */ -#define SPD_EEPROM_ADDRESS {0x54} /* SPD i2c spd addresses */ -#define CONFIG_VERY_BIG_RAM 1 -/*----------------------------------------------------------------------- - * I2C - *----------------------------------------------------------------------*/ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +/* DDR SDRAM */ +#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */ +#define SPD_EEPROM_ADDRESS {0x54} /* SPD i2c spd addresses */ +#define CONFIG_VERY_BIG_RAM 1 + +/* I2C */ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7f -#define CONFIG_SYS_I2C_NOPROBES {0x55,0x56,0x57,0x58,0x59,0x5a,0x5b,0x5c,0x69} /* Don't probe these addrs */ +#define CONFIG_SYS_I2C_NOPROBES {0x55,0x56,0x57,0x58,0x59,0x5a,0x5b,0x5c,0x69} -/*----------------------------------------------------------------------- - * Environment - *----------------------------------------------------------------------*/ -#define CONFIG_ENV_IS_IN_EEPROM 1 -#define CONFIG_ENV_SIZE 0x100 /* Size of Environment vars */ +/* Environment */ +#define CONFIG_ENV_IS_IN_EEPROM 1 +#define CONFIG_ENV_SIZE 0x100 /* Size of Environment vars */ #define CONFIG_ENV_OFFSET 0x100 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* this is actually the second page of the eeprom */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 #define CONFIG_BOOTARGS "root=/dev/hda1 " -#define CONFIG_BOOTCOMMAND "bootm ffc00000" /* autoboot command */ -#define CONFIG_BOOTDELAY 5 /* disable autoboot */ +#define CONFIG_BOOTCOMMAND "bootm ffc00000" /* autoboot command */ +#define CONFIG_BOOTDELAY 5 /* disable autoboot */ #define CONFIG_BAUDRATE 9600 -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ #define CONFIG_PPC4xx_EMAC -#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 0 /* PHY address phy0 not populated */ #define CONFIG_PHY1_ADDR 1 /* PHY address phy1 not populated */ #define CONFIG_PHY2_ADDR 4 /* PHY address phy2 */ #define CONFIG_PHY3_ADDR 8 /* PHY address phy3 */ #define CONFIG_NET_MULTI 1 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ -#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ -#define CONFIG_SYS_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ - -#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ -#define CONFIG_HAS_ETH2 1 /* add support for "eth2addr" */ -#define CONFIG_HAS_ETH3 1 /* add support for "eth3addr" */ +#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ +#define CONFIG_SYS_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ +#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ +#define CONFIG_HAS_ETH2 1 /* add support for "eth2addr" */ +#define CONFIG_HAS_ETH3 1 /* add support for "eth3addr" */ -/* - * BOOTP options - */ +/* BOOTP options */ #define CONFIG_BOOTP_BOOTFILESIZE #define CONFIG_BOOTP_BOOTPATH #define CONFIG_BOOTP_GATEWAY #define CONFIG_BOOTP_HOSTNAME - /* - * Command line configuration. + * Command line configuration */ #include @@ -212,48 +183,45 @@ extern void out32(unsigned int, unsigned long); #define CONFIG_CMD_DIAG #define CONFIG_CMD_FAT - -#undef CONFIG_WATCHDOG /* watchdog disabled */ +#undef CONFIG_WATCHDOG /* watchdog disabled */ /* * Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ #endif #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ +#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- +/* + * PCI */ /* General PCI */ -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */ +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */ /* Board-specific PCI */ -#define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target */ - +#define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target */ #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* IBM */ #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ -#define CONFIG_SYS_PCI_FORCE_PCI_CONV /* Force PCI Conventional Mode */ +#define CONFIG_SYS_PCI_FORCE_PCI_CONV /* Force PCI Conventional Mode */ + /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is @@ -263,11 +231,9 @@ extern void out32(unsigned int, unsigned long); /* * Internal Definitions - * - * Boot Flags */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -- cgit From 42735815dd9ba39efe51203868aebce04053c8de Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Fri, 17 Jul 2009 19:01:08 -0500 Subject: xpedite1k: Add support for optional flashes The XPedite1000 can be built with 4 total flashes: - 512KB AMD socketed - 16MB Intel soldered - 2 x 32MB AMD MirrorBit flashes Add support for the optional 2 32MB CFI-compliant AMD flashes Signed-off-by: Peter Tyser Signed-off-by: Stefan Roese --- include/configs/XPEDITE1K.h | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/include/configs/XPEDITE1K.h b/include/configs/XPEDITE1K.h index f141398128..0aebe27d3a 100644 --- a/include/configs/XPEDITE1K.h +++ b/include/configs/XPEDITE1K.h @@ -106,12 +106,13 @@ extern void out32(unsigned int, unsigned long); /* * FLASH related */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ +#define CONFIG_SYS_MAX_FLASH_BANKS 3 +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, 0xf0000000, 0xf4000000 } +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */ #define CONFIG_FLASH_CFI_DRIVER #define CONFIG_SYS_FLASH_CFI #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE +#define CONFIG_SYS_FLASH_QUIET_TEST /* MirrorBit flashes are optional */ #undef CONFIG_SYS_FLASH_CHECKSUM #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -- cgit From 767e32ad369d83f55f950e6938e68b6dba7fa65f Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Fri, 17 Jul 2009 19:01:10 -0500 Subject: xpedite1k: Store environment in flash Previously an I2C EEPROM was used. The EEPROM had size, reliability, and access issues which are resolved by storing the environment in flash. Signed-off-by: Peter Tyser Signed-off-by: Stefan Roese --- include/configs/XPEDITE1K.h | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/include/configs/XPEDITE1K.h b/include/configs/XPEDITE1K.h index 0aebe27d3a..df02d7b4d1 100644 --- a/include/configs/XPEDITE1K.h +++ b/include/configs/XPEDITE1K.h @@ -129,10 +129,15 @@ extern void out32(unsigned int, unsigned long); #define CONFIG_SYS_I2C_SLAVE 0x7f #define CONFIG_SYS_I2C_NOPROBES {0x55,0x56,0x57,0x58,0x59,0x5a,0x5b,0x5c,0x69} -/* Environment */ -#define CONFIG_ENV_IS_IN_EEPROM 1 -#define CONFIG_ENV_SIZE 0x100 /* Size of Environment vars */ -#define CONFIG_ENV_OFFSET 0x100 +/* + * Environment Configuration + */ +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */ +#define CONFIG_ENV_SIZE 0x8000 +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - (256 * 1024)) + +/* EEPROM */ #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -- cgit From fbc7951ea84c2fe6da0f6007b672ed35bae91acb Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Fri, 17 Jul 2009 19:01:11 -0500 Subject: xpedite1k: Disable unused ethernet port 1 The XPedite1000 only has 2 available ethernet ports: ppc_4xx_eth2 (EMAC2) and ppc_4xx_eth3 (EMAC3) Signed-off-by: Peter Tyser Signed-off-by: Stefan Roese --- include/configs/XPEDITE1K.h | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'include') diff --git a/include/configs/XPEDITE1K.h b/include/configs/XPEDITE1K.h index df02d7b4d1..d8eccd8d60 100644 --- a/include/configs/XPEDITE1K.h +++ b/include/configs/XPEDITE1K.h @@ -153,8 +153,7 @@ extern void out32(unsigned int, unsigned long); #define CONFIG_PPC4xx_EMAC #define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0 /* PHY address phy0 not populated */ -#define CONFIG_PHY1_ADDR 1 /* PHY address phy1 not populated */ +#define CONFIG_PHY_ADDR 4 /* PHY address phy0 not populated */ #define CONFIG_PHY2_ADDR 4 /* PHY address phy2 */ #define CONFIG_PHY3_ADDR 8 /* PHY address phy3 */ #define CONFIG_NET_MULTI 1 @@ -162,7 +161,6 @@ extern void out32(unsigned int, unsigned long); #define CONFIG_PHY_RESET 1 /* reset phy upon startup */ #define CONFIG_SYS_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ -#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ #define CONFIG_HAS_ETH2 1 /* add support for "eth2addr" */ #define CONFIG_HAS_ETH3 1 /* add support for "eth3addr" */ -- cgit From c4ae1a0257a0f5008ee2686e8aa92fba3992f279 Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Fri, 17 Jul 2009 19:01:12 -0500 Subject: xpedite1k: Sync up commands and environment with other X-ES boards Signed-off-by: Peter Tyser Signed-off-by: Stefan Roese --- include/configs/XPEDITE1K.h | 122 +++++++++++++++++++++++++++++++++++++++----- 1 file changed, 110 insertions(+), 12 deletions(-) (limited to 'include') diff --git a/include/configs/XPEDITE1K.h b/include/configs/XPEDITE1K.h index d8eccd8d60..c67350af2e 100644 --- a/include/configs/XPEDITE1K.h +++ b/include/configs/XPEDITE1K.h @@ -143,11 +143,6 @@ extern void out32(unsigned int, unsigned long); #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 -#define CONFIG_BOOTARGS "root=/dev/hda1 " -#define CONFIG_BOOTCOMMAND "bootm ffc00000" /* autoboot command */ -#define CONFIG_BOOTDELAY 5 /* disable autoboot */ -#define CONFIG_BAUDRATE 9600 - #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ @@ -175,17 +170,21 @@ extern void out32(unsigned int, unsigned long); */ #include -#define CONFIG_CMD_PCI -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_I2C +#define CONFIG_CMD_ASKENV #define CONFIG_CMD_DATE -#define CONFIG_CMD_BEDBUG +#define CONFIG_CMD_DHCP #define CONFIG_CMD_EEPROM -#define CONFIG_CMD_PING #define CONFIG_CMD_ELF +#define CONFIG_CMD_SAVEENV +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_JFFS2 #define CONFIG_CMD_MII -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_FAT +#define CONFIG_CMD_NET +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PING +#define CONFIG_CMD_SNTP #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -243,4 +242,103 @@ extern void out32(unsigned int, unsigned long); #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif + +/* + * Flash memory map: + * fff80000 - ffffffff U-Boot (512 KB) + * fff40000 - fff7ffff U-Boot Environment (256 KB) + * fff00000 - fff3ffff FDT (256KB) + * ffc00000 - ffefffff OS image (3MB) + * ff000000 - ffbfffff OS Use/Filesystem (12MB) + */ + +#define CONFIG_UBOOT_ENV_ADDR MK_STR(TEXT_BASE) +#define CONFIG_FDT_ENV_ADDR MK_STR(0xfff00000) +#define CONFIG_OS_ENV_ADDR MK_STR(0xffc00000) + +#define CONFIG_PROG_UBOOT \ + "$download_cmd $loadaddr $ubootfile; " \ + "if test $? -eq 0; then " \ + "protect off "CONFIG_UBOOT_ENV_ADDR" +80000; " \ + "erase "CONFIG_UBOOT_ENV_ADDR" +80000; " \ + "cp.w $loadaddr "CONFIG_UBOOT_ENV_ADDR" 40000; " \ + "protect on "CONFIG_UBOOT_ENV_ADDR" +80000; " \ + "cmp.b $loadaddr "CONFIG_UBOOT_ENV_ADDR" 80000; " \ + "if test $? -ne 0; then " \ + "echo PROGRAM FAILED; " \ + "else; " \ + "echo PROGRAM SUCCEEDED; " \ + "fi; " \ + "else; " \ + "echo DOWNLOAD FAILED; " \ + "fi;" + +#define CONFIG_BOOT_OS_NET \ + "$download_cmd $osaddr $osfile; " \ + "if test $? -eq 0; then " \ + "if test -n $fdtaddr; then " \ + "$download_cmd $fdtaddr $fdtfile; " \ + "if test $? -eq 0; then " \ + "bootm $osaddr - $fdtaddr; " \ + "else; " \ + "echo FDT DOWNLOAD FAILED; " \ + "fi; " \ + "else; " \ + "bootm $osaddr; " \ + "fi; " \ + "else; " \ + "echo OS DOWNLOAD FAILED; " \ + "fi;" + +#define CONFIG_PROG_OS \ + "$download_cmd $osaddr $osfile; " \ + "if test $? -eq 0; then " \ + "erase "CONFIG_OS_ENV_ADDR" +$filesize; " \ + "cp.b $osaddr "CONFIG_OS_ENV_ADDR" $filesize; " \ + "cmp.b $osaddr "CONFIG_OS_ENV_ADDR" $filesize; " \ + "if test $? -ne 0; then " \ + "echo OS PROGRAM FAILED; " \ + "else; " \ + "echo OS PROGRAM SUCCEEDED; " \ + "fi; " \ + "else; " \ + "echo OS DOWNLOAD FAILED; " \ + "fi;" + +#define CONFIG_PROG_FDT \ + "$download_cmd $fdtaddr $fdtfile; " \ + "if test $? -eq 0; then " \ + "erase "CONFIG_FDT_ENV_ADDR" +$filesize;" \ + "cp.b $fdtaddr "CONFIG_FDT_ENV_ADDR" $filesize; " \ + "cmp.b $fdtaddr "CONFIG_FDT_ENV_ADDR" $filesize; " \ + "if test $? -ne 0; then " \ + "echo FDT PROGRAM FAILED; " \ + "else; " \ + "echo FDT PROGRAM SUCCEEDED; " \ + "fi; " \ + "else; " \ + "echo FDT DOWNLOAD FAILED; " \ + "fi;" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "autoload=yes\0" \ + "download_cmd=tftp\0" \ + "console_args=console=ttyS0,115200\0" \ + "root_args=root=/dev/nfs rw\0" \ + "misc_args=ip=on\0" \ + "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \ + "bootfile=/home/user/file\0" \ + "osfile=/home/user/uImage-XPedite1000\0" \ + "fdtfile=/home/user/xpedite1000.dtb\0" \ + "ubootfile=/home/user/u-boot.bin\0" \ + "fdtaddr=c00000\0" \ + "osaddr=0x1000000\0" \ + "loadaddr=0x1000000\0" \ + "prog_uboot="CONFIG_PROG_UBOOT"\0" \ + "prog_os="CONFIG_PROG_OS"\0" \ + "prog_fdt="CONFIG_PROG_FDT"\0" \ + "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \ + "bootcmd_flash=run set_bootargs; " \ + "bootm "CONFIG_OS_ENV_ADDR" - "CONFIG_FDT_ENV_ADDR"\0" \ + "bootcmd=run bootcmd_flash\0" #endif /* __CONFIG_H */ -- cgit From 4cdad5f43ae67e4ceeac69ef4af4392bd2f7381f Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Fri, 17 Jul 2009 19:01:13 -0500 Subject: xpedite1k: Sync organization of board config with other X-ES boards This change should have no functional effect Signed-off-by: Peter Tyser Signed-off-by: Stefan Roese --- include/configs/XPEDITE1K.h | 159 +++++++++++++++++++++++--------------------- 1 file changed, 85 insertions(+), 74 deletions(-) (limited to 'include') diff --git a/include/configs/XPEDITE1K.h b/include/configs/XPEDITE1K.h index c67350af2e..391d0419fa 100644 --- a/include/configs/XPEDITE1K.h +++ b/include/configs/XPEDITE1K.h @@ -38,26 +38,40 @@ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ -/* POST support */ -#define CONFIG_POST (CONFIG_SYS_POST_RTC | \ - CONFIG_SYS_POST_I2C) +/* + * DDR config + */ +#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */ +#define SPD_EEPROM_ADDRESS {0x54} /* SPD i2c spd addresses */ +#define CONFIG_VERY_BIG_RAM 1 /* * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */ -#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH */ - -#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ -#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */ -#define CONFIG_SYS_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */ -#define CONFIG_SYS_ISRAM_BASE 0xc0000000 /* internal SRAM */ -#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */ - +#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH */ +#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ +#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */ +#define CONFIG_SYS_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */ +#define CONFIG_SYS_ISRAM_BASE 0xc0000000 /* internal SRAM */ +#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */ #define CONFIG_SYS_NVRAM_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000) #define CONFIG_SYS_GPIO_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000700) +/* + * Diagnostics + */ +#define CONFIG_SYS_MEMTEST_START 0x0400000 +#define CONFIG_SYS_MEMTEST_END 0x0C00000 + +/* POST support */ +#define CONFIG_POST (CONFIG_SYS_POST_RTC | \ + CONFIG_SYS_POST_I2C) + +/* + * LED support + */ #define USR_LED0 0x00000080 #define USR_LED1 0x00000100 #define USR_LED2 0x00000200 @@ -78,13 +92,14 @@ extern void out32(unsigned int, unsigned long); #define LED3_OFF() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) | USR_LED3)) #endif -/* Initial RAM & stack pointer (placed in internal SRAM) */ +/* + * Use internal SRAM for initial stack + */ #define CONFIG_SYS_TEMP_STACK_OCM 1 #define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */ #define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in RAM */ #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ - #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) #define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 0x4) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_POST_WORD_ADDR @@ -92,19 +107,17 @@ extern void out32(unsigned int, unsigned long); #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc */ -/* Serial Port */ -#undef CONFIG_SERIAL_SOFTWARE_FIFO -#define CONFIG_BAUDRATE 9600 +/* + * Serial Port + */ #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400} - -/* RTC: STMicro M41T00 */ -#define CONFIG_RTC_M41T11 1 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 -#define CONFIG_SYS_M41T11_BASE_YEAR 2000 +#define CONFIG_BAUDRATE 9600 +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ /* - * FLASH related + * NOR flash configuration */ #define CONFIG_SYS_MAX_FLASH_BANKS 3 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, 0xf0000000, 0xf4000000 } @@ -118,45 +131,54 @@ extern void out32(unsigned int, unsigned long); #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ -/* DDR SDRAM */ -#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */ -#define SPD_EEPROM_ADDRESS {0x54} /* SPD i2c spd addresses */ -#define CONFIG_VERY_BIG_RAM 1 - -/* I2C */ +/* + * I2C + */ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7f #define CONFIG_SYS_I2C_NOPROBES {0x55,0x56,0x57,0x58,0x59,0x5a,0x5b,0x5c,0x69} -/* - * Environment Configuration - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */ -#define CONFIG_ENV_SIZE 0x8000 -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - (256 * 1024)) - -/* EEPROM */ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +/* I2C EEPROM */ +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ +/* I2C RTC: STMicro M41T00 */ +#define CONFIG_RTC_M41T11 1 +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 +#define CONFIG_SYS_M41T11_BASE_YEAR 2000 + +/* + * PCI + */ +/* General PCI */ +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */ + +/* Board-specific PCI */ +#define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target */ +#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* IBM */ +#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ +#define CONFIG_SYS_PCI_FORCE_PCI_CONV /* Force PCI Conventional Mode */ +/* + * Networking options + */ #define CONFIG_PPC4xx_EMAC -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 4 /* PHY address phy0 not populated */ -#define CONFIG_PHY2_ADDR 4 /* PHY address phy2 */ -#define CONFIG_PHY3_ADDR 8 /* PHY address phy3 */ -#define CONFIG_NET_MULTI 1 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ +#define CONFIG_NET_MULTI 1 +#define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_RESET 1 /* reset phy upon startup */ #define CONFIG_SYS_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ - +#define CONFIG_ETHPRIME "ppc_4xx_eth2" +#define CONFIG_PHY_ADDR 4 /* PHY address phy0 not populated */ +#define CONFIG_PHY2_ADDR 4 /* PHY address phy2 */ #define CONFIG_HAS_ETH2 1 /* add support for "eth2addr" */ +#define CONFIG_PHY3_ADDR 8 /* PHY address phy3 */ #define CONFIG_HAS_ETH3 1 /* add support for "eth3addr" */ /* BOOTP options */ @@ -166,7 +188,7 @@ extern void out32(unsigned int, unsigned long); #define CONFIG_BOOTP_HOSTNAME /* - * Command line configuration + * Command configuration */ #include @@ -175,7 +197,6 @@ extern void out32(unsigned int, unsigned long); #define CONFIG_CMD_DHCP #define CONFIG_CMD_EEPROM #define CONFIG_CMD_ELF -#define CONFIG_CMD_SAVEENV #define CONFIG_CMD_FLASH #define CONFIG_CMD_I2C #define CONFIG_CMD_IRQ @@ -184,14 +205,14 @@ extern void out32(unsigned int, unsigned long); #define CONFIG_CMD_NET #define CONFIG_CMD_PCI #define CONFIG_CMD_PING +#define CONFIG_CMD_SAVEENV #define CONFIG_CMD_SNTP -#undef CONFIG_WATCHDOG /* watchdog disabled */ - /* * Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ @@ -201,29 +222,8 @@ extern void out32(unsigned int, unsigned long); #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/* - * PCI - */ -/* General PCI */ -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */ - -/* Board-specific PCI */ -#define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target */ -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* IBM */ -#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ -#define CONFIG_SYS_PCI_FORCE_PCI_CONV /* Force PCI Conventional Mode */ +#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ /* * For booting Linux, the board info and command line data @@ -233,16 +233,27 @@ extern void out32(unsigned int, unsigned long); #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ /* - * Internal Definitions + * Boot Flags */ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ +/* + * KGDB configuration + */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif +/* + * Environment Configuration + */ +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */ +#define CONFIG_ENV_SIZE 0x8000 +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - (256 * 1024)) + /* * Flash memory map: * fff80000 - ffffffff U-Boot (512 KB) -- cgit From 9b4ef1f5dc0daab64f46249a32e67279c4d44fd2 Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Fri, 17 Jul 2009 19:01:14 -0500 Subject: xpedite1k: Sync up board config options with other X-ES boards Signed-off-by: Peter Tyser Signed-off-by: Stefan Roese --- include/configs/XPEDITE1K.h | 38 +++++++++++++++++++------------------- 1 file changed, 19 insertions(+), 19 deletions(-) (limited to 'include') diff --git a/include/configs/XPEDITE1K.h b/include/configs/XPEDITE1K.h index 391d0419fa..016fa8a882 100644 --- a/include/configs/XPEDITE1K.h +++ b/include/configs/XPEDITE1K.h @@ -62,6 +62,7 @@ /* * Diagnostics */ +#define CONFIG_SYS_ALT_MEMTEST #define CONFIG_SYS_MEMTEST_START 0x0400000 #define CONFIG_SYS_MEMTEST_END 0x0C00000 @@ -104,18 +105,24 @@ extern void out32(unsigned int, unsigned long); #define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 0x4) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_POST_WORD_ADDR -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc */ +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */ +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ /* * Serial Port */ #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400} -#define CONFIG_BAUDRATE 9600 +#define CONFIG_BAUDRATE 115200 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ +/* + * Use the HUSH parser + */ +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + /* * NOR flash configuration */ @@ -126,8 +133,6 @@ extern void out32(unsigned int, unsigned long); #define CONFIG_SYS_FLASH_CFI #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE #define CONFIG_SYS_FLASH_QUIET_TEST /* MirrorBit flashes are optional */ - -#undef CONFIG_SYS_FLASH_CHECKSUM #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ @@ -137,7 +142,7 @@ extern void out32(unsigned int, unsigned long); #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7f -#define CONFIG_SYS_I2C_NOPROBES {0x55,0x56,0x57,0x58,0x59,0x5a,0x5b,0x5c,0x69} +#define CONFIG_I2C_MULTI_BUS /* I2C EEPROM */ #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 @@ -214,16 +219,19 @@ extern void out32(unsigned int, unsigned long); #define CONFIG_SYS_LONGHELP /* undef to save memory */ #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ -#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ +#define CONFIG_CMDLINE_EDITING 1 /* Command-line editing */ +#define CONFIG_BOOTDELAY 3 /* -1 disables auto-boot */ +#define CONFIG_PANIC_HANG /* do not reset board on panic */ +#define CONFIG_PREBOOT /* enable preboot variable */ +#define CONFIG_FIT 1 +#define CONFIG_FIT_VERBOSE 1 +#define CONFIG_INTEGRITY /* support booting INTEGRITY OS */ +#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ /* * For booting Linux, the board info and command line data @@ -238,14 +246,6 @@ extern void out32(unsigned int, unsigned long); #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -/* - * KGDB configuration - */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - /* * Environment Configuration */ -- cgit From 54381b79d268e1bead5d78ed8423df31a3cb0e2c Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Fri, 17 Jul 2009 19:01:15 -0500 Subject: xpedite1k: Sync checkboard() with other X-ES boards Signed-off-by: Peter Tyser Signed-off-by: Stefan Roese --- include/configs/XPEDITE1K.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/XPEDITE1K.h b/include/configs/XPEDITE1K.h index 016fa8a882..bb6208cce9 100644 --- a/include/configs/XPEDITE1K.h +++ b/include/configs/XPEDITE1K.h @@ -32,6 +32,7 @@ /* High Level Configuration Options */ #define CONFIG_XPEDITE1K 1 /* Board is XPedite 1000 */ +#define CONFIG_SYS_BOARD_NAME "XPedite1000" #define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_440 1 #define CONFIG_440GX 1 /* 440 GX */ -- cgit From 10c1b218556ed9871f36bc0c407f4f2f6196353b Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Fri, 17 Jul 2009 19:01:16 -0500 Subject: xpedite1k: Move to X-ES vendor directory The XPedite1000 is an X-ES product thus it can be put in board/xes along with other X-ES boards. Along with the move, the board was renamed to XPedite1000 from XPedite1K to fit X-ES's standard naming convention. Maintainership was also transfered to Peter Tyser. Signed-off-by: Peter Tyser Signed-off-by: Stefan Roese --- include/configs/XPEDITE1000.h | 356 ++++++++++++++++++++++++++++++++++++++++++ include/configs/XPEDITE1K.h | 356 ------------------------------------------ 2 files changed, 356 insertions(+), 356 deletions(-) create mode 100644 include/configs/XPEDITE1000.h delete mode 100644 include/configs/XPEDITE1K.h (limited to 'include') diff --git a/include/configs/XPEDITE1000.h b/include/configs/XPEDITE1000.h new file mode 100644 index 0000000000..658e9473bc --- /dev/null +++ b/include/configs/XPEDITE1000.h @@ -0,0 +1,356 @@ +/* + * (C) Copyright 2002 Scott McNutt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * config for XPedite1000 from XES Inc. + * Ported from EBONY config by Travis B. Sawyer + * (C) Copyright 2003 Sandburst Corporation + * board/config_EBONY.h - configuration for AMCC 440GP Ref (Ebony) + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* High Level Configuration Options */ +#define CONFIG_XPEDITE1000 1 +#define CONFIG_SYS_BOARD_NAME "XPedite1000" +#define CONFIG_4xx 1 /* ... PPC4xx family */ +#define CONFIG_440 1 +#define CONFIG_440GX 1 /* 440 GX */ +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ +#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ + +/* + * DDR config + */ +#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */ +#define SPD_EEPROM_ADDRESS {0x54} /* SPD i2c spd addresses */ +#define CONFIG_VERY_BIG_RAM 1 + +/* + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + */ +#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH */ +#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ +#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */ +#define CONFIG_SYS_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */ +#define CONFIG_SYS_ISRAM_BASE 0xc0000000 /* internal SRAM */ +#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */ +#define CONFIG_SYS_NVRAM_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000) +#define CONFIG_SYS_GPIO_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000700) + +/* + * Diagnostics + */ +#define CONFIG_SYS_ALT_MEMTEST +#define CONFIG_SYS_MEMTEST_START 0x0400000 +#define CONFIG_SYS_MEMTEST_END 0x0C00000 + +/* POST support */ +#define CONFIG_POST (CONFIG_SYS_POST_RTC | \ + CONFIG_SYS_POST_I2C) + +/* + * LED support + */ +#define USR_LED0 0x00000080 +#define USR_LED1 0x00000100 +#define USR_LED2 0x00000200 +#define USR_LED3 0x00000400 + +#ifndef __ASSEMBLY__ +extern unsigned long in32(unsigned int); +extern void out32(unsigned int, unsigned long); + +#define LED0_ON() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) & ~USR_LED0)) +#define LED1_ON() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) & ~USR_LED1)) +#define LED2_ON() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) & ~USR_LED2)) +#define LED3_ON() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) & ~USR_LED3)) + +#define LED0_OFF() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) | USR_LED0)) +#define LED1_OFF() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) | USR_LED1)) +#define LED2_OFF() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) | USR_LED2)) +#define LED3_OFF() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) | USR_LED3)) +#endif + +/* + * Use internal SRAM for initial stack + */ +#define CONFIG_SYS_TEMP_STACK_OCM 1 +#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE +#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */ +#define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in RAM */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 0x4) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_POST_WORD_ADDR + +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */ +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ + +/* + * Serial Port + */ +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400} +#define CONFIG_BAUDRATE 115200 +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +/* + * Use the HUSH parser + */ +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +/* + * NOR flash configuration + */ +#define CONFIG_SYS_MAX_FLASH_BANKS 3 +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, 0xf0000000, 0xf4000000 } +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */ +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE +#define CONFIG_SYS_FLASH_QUIET_TEST /* MirrorBit flashes are optional */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +/* + * I2C + */ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_I2C_SLAVE 0x7f +#define CONFIG_I2C_MULTI_BUS + +/* I2C EEPROM */ +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 + +/* I2C RTC: STMicro M41T00 */ +#define CONFIG_RTC_M41T11 1 +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 +#define CONFIG_SYS_M41T11_BASE_YEAR 2000 + +/* + * PCI + */ +/* General PCI */ +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */ + +/* Board-specific PCI */ +#define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target */ +#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* IBM */ +#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ +#define CONFIG_SYS_PCI_FORCE_PCI_CONV /* Force PCI Conventional Mode */ + +/* + * Networking options + */ +#define CONFIG_PPC4xx_EMAC +#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ +#define CONFIG_NET_MULTI 1 +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ +#define CONFIG_SYS_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ +#define CONFIG_ETHPRIME "ppc_4xx_eth2" +#define CONFIG_PHY_ADDR 4 /* PHY address phy0 not populated */ +#define CONFIG_PHY2_ADDR 4 /* PHY address phy2 */ +#define CONFIG_HAS_ETH2 1 /* add support for "eth2addr" */ +#define CONFIG_PHY3_ADDR 8 /* PHY address phy3 */ +#define CONFIG_HAS_ETH3 1 /* add support for "eth3addr" */ + +/* BOOTP options */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/* + * Command configuration + */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_ELF +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PING +#define CONFIG_CMD_SAVEENV +#define CONFIG_CMD_SNTP + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ +#define CONFIG_CMDLINE_EDITING 1 /* Command-line editing */ +#define CONFIG_BOOTDELAY 3 /* -1 disables auto-boot */ +#define CONFIG_PANIC_HANG /* do not reset board on panic */ +#define CONFIG_PREBOOT /* enable preboot variable */ +#define CONFIG_FIT 1 +#define CONFIG_FIT_VERBOSE 1 +#define CONFIG_INTEGRITY /* support booting INTEGRITY OS */ +#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/* + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +/* + * Environment Configuration + */ +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */ +#define CONFIG_ENV_SIZE 0x8000 +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - (256 * 1024)) + +/* + * Flash memory map: + * fff80000 - ffffffff U-Boot (512 KB) + * fff40000 - fff7ffff U-Boot Environment (256 KB) + * fff00000 - fff3ffff FDT (256KB) + * ffc00000 - ffefffff OS image (3MB) + * ff000000 - ffbfffff OS Use/Filesystem (12MB) + */ + +#define CONFIG_UBOOT_ENV_ADDR MK_STR(TEXT_BASE) +#define CONFIG_FDT_ENV_ADDR MK_STR(0xfff00000) +#define CONFIG_OS_ENV_ADDR MK_STR(0xffc00000) + +#define CONFIG_PROG_UBOOT \ + "$download_cmd $loadaddr $ubootfile; " \ + "if test $? -eq 0; then " \ + "protect off "CONFIG_UBOOT_ENV_ADDR" +80000; " \ + "erase "CONFIG_UBOOT_ENV_ADDR" +80000; " \ + "cp.w $loadaddr "CONFIG_UBOOT_ENV_ADDR" 40000; " \ + "protect on "CONFIG_UBOOT_ENV_ADDR" +80000; " \ + "cmp.b $loadaddr "CONFIG_UBOOT_ENV_ADDR" 80000; " \ + "if test $? -ne 0; then " \ + "echo PROGRAM FAILED; " \ + "else; " \ + "echo PROGRAM SUCCEEDED; " \ + "fi; " \ + "else; " \ + "echo DOWNLOAD FAILED; " \ + "fi;" + +#define CONFIG_BOOT_OS_NET \ + "$download_cmd $osaddr $osfile; " \ + "if test $? -eq 0; then " \ + "if test -n $fdtaddr; then " \ + "$download_cmd $fdtaddr $fdtfile; " \ + "if test $? -eq 0; then " \ + "bootm $osaddr - $fdtaddr; " \ + "else; " \ + "echo FDT DOWNLOAD FAILED; " \ + "fi; " \ + "else; " \ + "bootm $osaddr; " \ + "fi; " \ + "else; " \ + "echo OS DOWNLOAD FAILED; " \ + "fi;" + +#define CONFIG_PROG_OS \ + "$download_cmd $osaddr $osfile; " \ + "if test $? -eq 0; then " \ + "erase "CONFIG_OS_ENV_ADDR" +$filesize; " \ + "cp.b $osaddr "CONFIG_OS_ENV_ADDR" $filesize; " \ + "cmp.b $osaddr "CONFIG_OS_ENV_ADDR" $filesize; " \ + "if test $? -ne 0; then " \ + "echo OS PROGRAM FAILED; " \ + "else; " \ + "echo OS PROGRAM SUCCEEDED; " \ + "fi; " \ + "else; " \ + "echo OS DOWNLOAD FAILED; " \ + "fi;" + +#define CONFIG_PROG_FDT \ + "$download_cmd $fdtaddr $fdtfile; " \ + "if test $? -eq 0; then " \ + "erase "CONFIG_FDT_ENV_ADDR" +$filesize;" \ + "cp.b $fdtaddr "CONFIG_FDT_ENV_ADDR" $filesize; " \ + "cmp.b $fdtaddr "CONFIG_FDT_ENV_ADDR" $filesize; " \ + "if test $? -ne 0; then " \ + "echo FDT PROGRAM FAILED; " \ + "else; " \ + "echo FDT PROGRAM SUCCEEDED; " \ + "fi; " \ + "else; " \ + "echo FDT DOWNLOAD FAILED; " \ + "fi;" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "autoload=yes\0" \ + "download_cmd=tftp\0" \ + "console_args=console=ttyS0,115200\0" \ + "root_args=root=/dev/nfs rw\0" \ + "misc_args=ip=on\0" \ + "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \ + "bootfile=/home/user/file\0" \ + "osfile=/home/user/uImage-XPedite1000\0" \ + "fdtfile=/home/user/xpedite1000.dtb\0" \ + "ubootfile=/home/user/u-boot.bin\0" \ + "fdtaddr=c00000\0" \ + "osaddr=0x1000000\0" \ + "loadaddr=0x1000000\0" \ + "prog_uboot="CONFIG_PROG_UBOOT"\0" \ + "prog_os="CONFIG_PROG_OS"\0" \ + "prog_fdt="CONFIG_PROG_FDT"\0" \ + "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \ + "bootcmd_flash=run set_bootargs; " \ + "bootm "CONFIG_OS_ENV_ADDR" - "CONFIG_FDT_ENV_ADDR"\0" \ + "bootcmd=run bootcmd_flash\0" +#endif /* __CONFIG_H */ diff --git a/include/configs/XPEDITE1K.h b/include/configs/XPEDITE1K.h deleted file mode 100644 index bb6208cce9..0000000000 --- a/include/configs/XPEDITE1K.h +++ /dev/null @@ -1,356 +0,0 @@ -/* - * (C) Copyright 2002 Scott McNutt - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * config for XPedite1000 from XES Inc. - * Ported from EBONY config by Travis B. Sawyer - * (C) Copyright 2003 Sandburst Corporation - * board/config_EBONY.h - configuration for AMCC 440GP Ref (Ebony) - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* High Level Configuration Options */ -#define CONFIG_XPEDITE1K 1 /* Board is XPedite 1000 */ -#define CONFIG_SYS_BOARD_NAME "XPedite1000" -#define CONFIG_4xx 1 /* ... PPC4xx family */ -#define CONFIG_440 1 -#define CONFIG_440GX 1 /* 440 GX */ -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ -#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ - -/* - * DDR config - */ -#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */ -#define SPD_EEPROM_ADDRESS {0x54} /* SPD i2c spd addresses */ -#define CONFIG_VERY_BIG_RAM 1 - -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH */ -#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ -#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */ -#define CONFIG_SYS_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */ -#define CONFIG_SYS_ISRAM_BASE 0xc0000000 /* internal SRAM */ -#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */ -#define CONFIG_SYS_NVRAM_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000) -#define CONFIG_SYS_GPIO_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000700) - -/* - * Diagnostics - */ -#define CONFIG_SYS_ALT_MEMTEST -#define CONFIG_SYS_MEMTEST_START 0x0400000 -#define CONFIG_SYS_MEMTEST_END 0x0C00000 - -/* POST support */ -#define CONFIG_POST (CONFIG_SYS_POST_RTC | \ - CONFIG_SYS_POST_I2C) - -/* - * LED support - */ -#define USR_LED0 0x00000080 -#define USR_LED1 0x00000100 -#define USR_LED2 0x00000200 -#define USR_LED3 0x00000400 - -#ifndef __ASSEMBLY__ -extern unsigned long in32(unsigned int); -extern void out32(unsigned int, unsigned long); - -#define LED0_ON() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) & ~USR_LED0)) -#define LED1_ON() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) & ~USR_LED1)) -#define LED2_ON() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) & ~USR_LED2)) -#define LED3_ON() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) & ~USR_LED3)) - -#define LED0_OFF() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) | USR_LED0)) -#define LED1_OFF() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) | USR_LED1)) -#define LED2_OFF() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) | USR_LED2)) -#define LED3_OFF() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) | USR_LED3)) -#endif - -/* - * Use internal SRAM for initial stack - */ -#define CONFIG_SYS_TEMP_STACK_OCM 1 -#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) -#define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 0x4) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_POST_WORD_ADDR - -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ - -/* - * Serial Port - */ -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400} -#define CONFIG_BAUDRATE 115200 -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -/* - * Use the HUSH parser - */ -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " - -/* - * NOR flash configuration - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 3 -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, 0xf0000000, 0xf4000000 } -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */ -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE -#define CONFIG_SYS_FLASH_QUIET_TEST /* MirrorBit flashes are optional */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -/* - * I2C - */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SLAVE 0x7f -#define CONFIG_I2C_MULTI_BUS - -/* I2C EEPROM */ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 - -/* I2C RTC: STMicro M41T00 */ -#define CONFIG_RTC_M41T11 1 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 -#define CONFIG_SYS_M41T11_BASE_YEAR 2000 - -/* - * PCI - */ -/* General PCI */ -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */ - -/* Board-specific PCI */ -#define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target */ -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* IBM */ -#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ -#define CONFIG_SYS_PCI_FORCE_PCI_CONV /* Force PCI Conventional Mode */ - -/* - * Networking options - */ -#define CONFIG_PPC4xx_EMAC -#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ -#define CONFIG_NET_MULTI 1 -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ -#define CONFIG_SYS_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ -#define CONFIG_ETHPRIME "ppc_4xx_eth2" -#define CONFIG_PHY_ADDR 4 /* PHY address phy0 not populated */ -#define CONFIG_PHY2_ADDR 4 /* PHY address phy2 */ -#define CONFIG_HAS_ETH2 1 /* add support for "eth2addr" */ -#define CONFIG_PHY3_ADDR 8 /* PHY address phy3 */ -#define CONFIG_HAS_ETH3 1 /* add support for "eth3addr" */ - -/* BOOTP options */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -/* - * Command configuration - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_ELF -#define CONFIG_CMD_FLASH -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_MII -#define CONFIG_CMD_NET -#define CONFIG_CMD_PCI -#define CONFIG_CMD_PING -#define CONFIG_CMD_SAVEENV -#define CONFIG_CMD_SNTP - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ -#define CONFIG_CMDLINE_EDITING 1 /* Command-line editing */ -#define CONFIG_BOOTDELAY 3 /* -1 disables auto-boot */ -#define CONFIG_PANIC_HANG /* do not reset board on panic */ -#define CONFIG_PREBOOT /* enable preboot variable */ -#define CONFIG_FIT 1 -#define CONFIG_FIT_VERBOSE 1 -#define CONFIG_INTEGRITY /* support booting INTEGRITY OS */ -#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -/* - * Environment Configuration - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */ -#define CONFIG_ENV_SIZE 0x8000 -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - (256 * 1024)) - -/* - * Flash memory map: - * fff80000 - ffffffff U-Boot (512 KB) - * fff40000 - fff7ffff U-Boot Environment (256 KB) - * fff00000 - fff3ffff FDT (256KB) - * ffc00000 - ffefffff OS image (3MB) - * ff000000 - ffbfffff OS Use/Filesystem (12MB) - */ - -#define CONFIG_UBOOT_ENV_ADDR MK_STR(TEXT_BASE) -#define CONFIG_FDT_ENV_ADDR MK_STR(0xfff00000) -#define CONFIG_OS_ENV_ADDR MK_STR(0xffc00000) - -#define CONFIG_PROG_UBOOT \ - "$download_cmd $loadaddr $ubootfile; " \ - "if test $? -eq 0; then " \ - "protect off "CONFIG_UBOOT_ENV_ADDR" +80000; " \ - "erase "CONFIG_UBOOT_ENV_ADDR" +80000; " \ - "cp.w $loadaddr "CONFIG_UBOOT_ENV_ADDR" 40000; " \ - "protect on "CONFIG_UBOOT_ENV_ADDR" +80000; " \ - "cmp.b $loadaddr "CONFIG_UBOOT_ENV_ADDR" 80000; " \ - "if test $? -ne 0; then " \ - "echo PROGRAM FAILED; " \ - "else; " \ - "echo PROGRAM SUCCEEDED; " \ - "fi; " \ - "else; " \ - "echo DOWNLOAD FAILED; " \ - "fi;" - -#define CONFIG_BOOT_OS_NET \ - "$download_cmd $osaddr $osfile; " \ - "if test $? -eq 0; then " \ - "if test -n $fdtaddr; then " \ - "$download_cmd $fdtaddr $fdtfile; " \ - "if test $? -eq 0; then " \ - "bootm $osaddr - $fdtaddr; " \ - "else; " \ - "echo FDT DOWNLOAD FAILED; " \ - "fi; " \ - "else; " \ - "bootm $osaddr; " \ - "fi; " \ - "else; " \ - "echo OS DOWNLOAD FAILED; " \ - "fi;" - -#define CONFIG_PROG_OS \ - "$download_cmd $osaddr $osfile; " \ - "if test $? -eq 0; then " \ - "erase "CONFIG_OS_ENV_ADDR" +$filesize; " \ - "cp.b $osaddr "CONFIG_OS_ENV_ADDR" $filesize; " \ - "cmp.b $osaddr "CONFIG_OS_ENV_ADDR" $filesize; " \ - "if test $? -ne 0; then " \ - "echo OS PROGRAM FAILED; " \ - "else; " \ - "echo OS PROGRAM SUCCEEDED; " \ - "fi; " \ - "else; " \ - "echo OS DOWNLOAD FAILED; " \ - "fi;" - -#define CONFIG_PROG_FDT \ - "$download_cmd $fdtaddr $fdtfile; " \ - "if test $? -eq 0; then " \ - "erase "CONFIG_FDT_ENV_ADDR" +$filesize;" \ - "cp.b $fdtaddr "CONFIG_FDT_ENV_ADDR" $filesize; " \ - "cmp.b $fdtaddr "CONFIG_FDT_ENV_ADDR" $filesize; " \ - "if test $? -ne 0; then " \ - "echo FDT PROGRAM FAILED; " \ - "else; " \ - "echo FDT PROGRAM SUCCEEDED; " \ - "fi; " \ - "else; " \ - "echo FDT DOWNLOAD FAILED; " \ - "fi;" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "autoload=yes\0" \ - "download_cmd=tftp\0" \ - "console_args=console=ttyS0,115200\0" \ - "root_args=root=/dev/nfs rw\0" \ - "misc_args=ip=on\0" \ - "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \ - "bootfile=/home/user/file\0" \ - "osfile=/home/user/uImage-XPedite1000\0" \ - "fdtfile=/home/user/xpedite1000.dtb\0" \ - "ubootfile=/home/user/u-boot.bin\0" \ - "fdtaddr=c00000\0" \ - "osaddr=0x1000000\0" \ - "loadaddr=0x1000000\0" \ - "prog_uboot="CONFIG_PROG_UBOOT"\0" \ - "prog_os="CONFIG_PROG_OS"\0" \ - "prog_fdt="CONFIG_PROG_FDT"\0" \ - "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \ - "bootcmd_flash=run set_bootargs; " \ - "bootm "CONFIG_OS_ENV_ADDR" - "CONFIG_FDT_ENV_ADDR"\0" \ - "bootcmd=run bootcmd_flash\0" -#endif /* __CONFIG_H */ -- cgit From 87c0b72908e05662b8b415e26e1042f4779629da Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 20 Jul 2009 06:57:27 +0200 Subject: Add "chip_config" command for PPC4xx bootstrap configuration This patch adds a generic command for programming I2C bootstrap eeproms on PPC4xx. An implementation for Canyonlands board is included. The command name is intentionally chosen not to be PPC4xx specific. This way other CPU's/SoC's can implement a similar command under the same name, perhaps with a different syntax. Usage on Canyonlands: => chip_config Available configurations (I2C address 0x52): 600-nor - NOR CPU: 600 PLB: 200 OPB: 100 EBC: 100 600-nand - NAND CPU: 600 PLB: 200 OPB: 100 EBC: 100 800-nor - NOR CPU: 800 PLB: 200 OPB: 100 EBC: 100 800-nand - NAND CPU: 800 PLB: 200 OPB: 100 EBC: 100 1000-nor - NOR CPU:1000 PLB: 200 OPB: 100 EBC: 100 1000-nand - NAND CPU:1000 PLB: 200 OPB: 100 EBC: 100 1066-nor - NOR CPU:1066 PLB: 266 OPB: 88 EBC: 88 *** 1066-nand - NAND CPU:1066 PLB: 266 OPB: 88 EBC: 88 => chip_config 600-nor Using configuration: 600-nor - NOR CPU: 600 PLB: 200 OPB: 100 EBC: 100 done (dump via 'i2c md 52 0.1 10') Reset the board for the changes to take effect Other 4xx boards will be migrated to use this command soon as well. Signed-off-by: Stefan Roese Signed-off-by: Dirk Eibach Acked-by: Matthias Fuchs --- include/asm-ppc/ppc4xx_config.h | 42 +++++++++++++++++++++++++++++++++++++++++ include/configs/canyonlands.h | 6 ++++++ 2 files changed, 48 insertions(+) create mode 100644 include/asm-ppc/ppc4xx_config.h (limited to 'include') diff --git a/include/asm-ppc/ppc4xx_config.h b/include/asm-ppc/ppc4xx_config.h new file mode 100644 index 0000000000..49acb60aed --- /dev/null +++ b/include/asm-ppc/ppc4xx_config.h @@ -0,0 +1,42 @@ +/* + * (C) Copyright 2008-2009 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * (C) Copyright 2009 + * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef __PPC4xx_CONFIG_H +#define __PPC4xx_CONFIG_H + +#include + +struct ppc4xx_config { + char label[16]; + char description[64]; + u8 val[CONFIG_4xx_CONFIG_BLOCKSIZE]; +}; + +extern struct ppc4xx_config ppc4xx_config_val[]; +extern int ppc4xx_config_count; + +#endif /* __PPC4xx_CONFIG_H */ diff --git a/include/configs/canyonlands.h b/include/configs/canyonlands.h index d22d4113de..217a8ee009 100644 --- a/include/configs/canyonlands.h +++ b/include/configs/canyonlands.h @@ -330,6 +330,11 @@ #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 +/* I2C bootstrap EEPROM */ +#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x52 +#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0 +#define CONFIG_4xx_CONFIG_BLOCKSIZE 16 + /* I2C SYSMON (LM75, AD7414 is almost compatible) */ #define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ #define CONFIG_DTT_AD7414 1 /* use AD7414 */ @@ -442,6 +447,7 @@ /* * Commands additional to the ones defined in amcc-common.h */ +#define CONFIG_CMD_CHIP_CONFIG #if defined(CONFIG_ARCHES) #define CONFIG_CMD_DTT #define CONFIG_CMD_PCI -- cgit From 58ea142fb2e969f32306c8da1dabfaebd6fa141a Mon Sep 17 00:00:00 2001 From: Matthias Fuchs Date: Wed, 22 Jul 2009 17:27:56 +0200 Subject: ppc4xx: Replace 4xx lowercase SPR references Signed-off-by: Matthias Fuchs Signed-off-by: Stefan Roese --- include/asm-ppc/processor.h | 46 ++++++++++++++++++++++ include/ppc405.h | 55 --------------------------- include/ppc440.h | 93 --------------------------------------------- 3 files changed, 46 insertions(+), 148 deletions(-) (limited to 'include') diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index 65546adbca..2c0c0cee40 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -96,6 +96,10 @@ #define CONFIG_BOOKE #endif +#define SPRN_CCR0 0x3B3 /* Core Configuration Register 0 */ +#ifdef CONFIG_BOOKE +#define SPRN_CCR1 0x378 /* Core Configuration Register for 440 only */ +#endif #define SPRN_CDBCR 0x3D7 /* Cache Debug Control Register */ #define SPRN_CTR 0x009 /* Count Register */ #define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */ @@ -166,6 +170,9 @@ #define SPRN_DBSR 0x3F0 /* Debug Status Register */ #else #define SPRN_DBCR1 0x135 /* Book E Debug Control Register 1 */ +#ifdef CONFIG_BOOKE +#define SPRN_DBDR 0x3f3 /* Debug Data Register */ +#endif #define SPRN_DBSR 0x130 /* Book E Debug Status Register */ #define DBSR_IC 0x08000000 /* Book E Instruction Completion */ #define DBSR_TIE 0x01000000 /* Book E Trap Instruction Event */ @@ -173,6 +180,10 @@ #define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */ #define DCCR_NOCACHE 0 /* Noncacheable */ #define DCCR_CACHE 1 /* Cacheable */ +#ifndef CONFIG_BOOKE +#define SPRN_DCDBTRL 0x39c /* Data Cache Debug Tag Register Low */ +#define SPRN_DCDBTRH 0x39d /* Data Cache Debug Tag Register High */ +#endif #define SPRN_DCMP 0x3D1 /* Data TLB Compare Register */ #define SPRN_DCWR 0x3BA /* Data Cache Write-thru Register */ #define DCWR_COPY 0 /* Copy-back */ @@ -184,7 +195,20 @@ #endif /* CONFIG_BOOKE */ #define SPRN_DEC 0x016 /* Decrement Register */ #define SPRN_DMISS 0x3D0 /* Data TLB Miss Register */ +#ifdef CONFIG_BOOKE +#define SPRN_DNV0 0x390 /* Data Cache Normal Victim 0 */ +#define SPRN_DNV1 0x391 /* Data Cache Normal Victim 1 */ +#define SPRN_DNV2 0x392 /* Data Cache Normal Victim 2 */ +#define SPRN_DNV3 0x393 /* Data Cache Normal Victim 3 */ +#endif #define SPRN_DSISR 0x012 /* Data Storage Interrupt Status Register */ +#ifdef CONFIG_BOOKE +#define SPRN_DTV0 0x394 /* Data Cache Transient Victim 0 */ +#define SPRN_DTV1 0x395 /* Data Cache Transient Victim 1 */ +#define SPRN_DTV2 0x396 /* Data Cache Transient Victim 2 */ +#define SPRN_DTV3 0x397 /* Data Cache Transient Victim 3 */ +#define SPRN_DVLIM 0x398 /* Data Cache Victim Limit */ +#endif #define SPRN_EAR 0x11A /* External Address Register */ #ifndef CONFIG_BOOKE #define SPRN_ESR 0x3D4 /* Exception Syndrome Register */ @@ -269,16 +293,34 @@ #define ICCR_NOCACHE 0 /* Noncacheable */ #define ICCR_CACHE 1 /* Cacheable */ #define SPRN_ICDBDR 0x3D3 /* Instruction Cache Debug Data Register */ +#ifdef CONFIG_BOOKE +#define SPRN_ICDBTRL 0x39e /* instruction cache debug tag register low */ +#define SPRN_ICDBTRH 0x39f /* instruction cache debug tag register high */ +#endif #define SPRN_ICMP 0x3D5 /* Instruction TLB Compare Register */ #define SPRN_ICTC 0x3FB /* Instruction Cache Throttling Control Reg */ #define SPRN_IMISS 0x3D4 /* Instruction TLB Miss Register */ #define SPRN_IMMR 0x27E /* Internal Memory Map Register */ +#ifdef CONFIG_BOOKE +#define SPRN_INV0 0x370 /* Instruction Cache Normal Victim 0 */ +#define SPRN_INV1 0x371 /* Instruction Cache Normal Victim 1 */ +#define SPRN_INV2 0x372 /* Instruction Cache Normal Victim 2 */ +#define SPRN_INV3 0x373 /* Instruction Cache Normal Victim 3 */ +#define SPRN_ITV0 0x374 /* Instruction Cache Transient Victim 0 */ +#define SPRN_ITV1 0x375 /* Instruction Cache Transient Victim 1 */ +#define SPRN_ITV2 0x376 /* Instruction Cache Transient Victim 2 */ +#define SPRN_ITV3 0x377 /* Instruction Cache Transient Victim 3 */ +#define SPRN_IVLIM 0x399 /* Instruction Cache Victim Limit */ +#endif #define SPRN_LDSTCR 0x3F8 /* Load/Store Control Register */ #define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Regsiter */ #define SPRN_LR 0x008 /* Link Register */ #define SPRN_MBAR 0x137 /* System memory base address */ #define SPRN_MMCR0 0x3B8 /* Monitor Mode Control Register 0 */ #define SPRN_MMCR1 0x3BC /* Monitor Mode Control Register 1 */ +#ifdef CONFIG_BOOKE +#define SPRN_MMUCR 0x3b2 /* MMU Control Register */ +#endif #define SPRN_PBL1 0x3FC /* Protection Bound Lower 1 */ #define SPRN_PBL2 0x3FE /* Protection Bound Lower 2 */ #define SPRN_PBU1 0x3FD /* Protection Bound Upper 1 */ @@ -297,6 +339,9 @@ #define SPRN_PMC4 0x3BE /* Performance Counter Register 4 */ #define SPRN_PVR 0x11F /* Processor Version Register */ #define SPRN_RPA 0x3D6 /* Required Physical Address Register */ +#ifdef CONFIG_BOOKE +#define SPRN_RSTCFG 0x39b /* Reset Configuration */ +#endif #define SPRN_SDA 0x3BF /* Sampled Data Address Register */ #define SPRN_SDR1 0x019 /* MMU Hash Base Register */ #define SPRN_SGR 0x3B9 /* Storage Guarded Register */ @@ -315,6 +360,7 @@ #define SPRN_SRR1 0x01B /* Save/Restore Register 1 */ #define SPRN_SRR2 0x3DE /* Save/Restore Register 2 */ #define SPRN_SRR3 0x3DF /* Save/Restore Register 3 */ + #ifdef CONFIG_BOOKE #define SPRN_SVR 0x3FF /* System Version Register */ #else diff --git a/include/ppc405.h b/include/ppc405.h index 917afecfa7..a17dd35950 100644 --- a/include/ppc405.h +++ b/include/ppc405.h @@ -32,61 +32,6 @@ #define CONFIG_SYS_DCACHE_SIZE (2 << 10) /* For PLX IOP480 (403) */ #endif -/*--------------------------------------------------------------------- */ -/* Special Purpose Registers */ -/*--------------------------------------------------------------------- */ - #define srr2 0x3de /* save/restore register 2 */ - #define srr3 0x3df /* save/restore register 3 */ - - /* - * 405 does not really have CSRR0/1 but SRR2/3 are used during critical - * exception for the exact same purposes - let's alias them and have a - * common handling in crit_return() and CRIT_EXCEPTION - */ - #define csrr0 srr2 - #define csrr1 srr3 - - #define dbsr 0x3f0 /* debug status register */ - #define dbcr0 0x3f2 /* debug control register 0 */ - #define dbcr1 0x3bd /* debug control register 1 */ - #define iac1 0x3f4 /* instruction address comparator 1 */ - #define iac2 0x3f5 /* instruction address comparator 2 */ - #define iac3 0x3b4 /* instruction address comparator 3 */ - #define iac4 0x3b5 /* instruction address comparator 4 */ - #define dac1 0x3f6 /* data address comparator 1 */ - #define dac2 0x3f7 /* data address comparator 2 */ - #define dccr 0x3fa /* data cache control register */ - #define iccr 0x3fb /* instruction cache control register */ - #define esr 0x3d4 /* execption syndrome register */ - #define dear 0x3d5 /* data exeption address register */ - #define evpr 0x3d6 /* exeption vector prefix register */ - #define tsr 0x3d8 /* timer status register */ - #define tcr 0x3da /* timer control register */ - #define pit 0x3db /* programmable interval timer */ - #define sgr 0x3b9 /* storage guarded reg */ - #define dcwr 0x3ba /* data cache write-thru reg*/ - #define sler 0x3bb /* storage little-endian reg */ - #define cdbcr 0x3d7 /* cache debug cntrl reg */ - #define icdbdr 0x3d3 /* instr cache dbug data reg*/ - #define ccr0 0x3b3 /* core configuration register */ - #define dvc1 0x3b6 /* data value compare register 1 */ - #define dvc2 0x3b7 /* data value compare register 2 */ - #define pid 0x3b1 /* process ID */ - #define su0r 0x3bc /* storage user-defined register 0 */ - #define zpr 0x3b0 /* zone protection regsiter */ - - #define tbl 0x11c /* time base lower - privileged write */ - #define tbu 0x11d /* time base upper - privileged write */ - - #define sprg4r 0x104 /* Special purpose general 4 - read only */ - #define sprg5r 0x105 /* Special purpose general 5 - read only */ - #define sprg6r 0x106 /* Special purpose general 6 - read only */ - #define sprg7r 0x107 /* Special purpose general 7 - read only */ - #define sprg4w 0x114 /* Special purpose general 4 - write only */ - #define sprg5w 0x115 /* Special purpose general 5 - write only */ - #define sprg6w 0x116 /* Special purpose general 6 - write only */ - #define sprg7w 0x117 /* Special purpose general 7 - write only */ - /****************************************************************************** * Special for PPC405GP ******************************************************************************/ diff --git a/include/ppc440.h b/include/ppc440.h index 01f6eaf35e..6ce53a6ef2 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -48,99 +48,6 @@ #define CONFIG_SYS_DCACHE_SIZE (32 << 10) /* For AMCC 440 CPUs */ -/*--------------------------------------------------------------------- */ -/* Special Purpose Registers */ -/*--------------------------------------------------------------------- */ -#define xer_reg 0x001 -#define lr_reg 0x008 -#define dec 0x016 /* decrementer */ -#define srr0 0x01a /* save/restore register 0 */ -#define srr1 0x01b /* save/restore register 1 */ -#define pid 0x030 /* process id */ -#define decar 0x036 /* decrementer auto-reload */ -#define csrr0 0x03a /* critical save/restore register 0 */ -#define csrr1 0x03b /* critical save/restore register 1 */ -#define dear 0x03d /* data exception address register */ -#define esr 0x03e /* exception syndrome register */ -#define ivpr 0x03f /* interrupt prefix register */ -#define usprg0 0x100 /* user special purpose register general 0 */ -#define usprg1 0x110 /* user special purpose register general 1 */ -#define tblr 0x10c /* time base lower, read only */ -#define tbur 0x10d /* time base upper, read only */ -#define sprg1 0x111 /* special purpose register general 1 */ -#define sprg2 0x112 /* special purpose register general 2 */ -#define sprg3 0x113 /* special purpose register general 3 */ -#define sprg4 0x114 /* special purpose register general 4 */ -#define sprg5 0x115 /* special purpose register general 5 */ -#define sprg6 0x116 /* special purpose register general 6 */ -#define sprg7 0x117 /* special purpose register general 7 */ -#define tbl 0x11c /* time base lower (supervisor)*/ -#define tbu 0x11d /* time base upper (supervisor)*/ -#define pir 0x11e /* processor id register */ -#define dbsr 0x130 /* debug status register */ -#define dbcr0 0x134 /* debug control register 0 */ -#define dbcr1 0x135 /* debug control register 1 */ -#define dbcr2 0x136 /* debug control register 2 */ -#define iac1 0x138 /* instruction address compare 1 */ -#define iac2 0x139 /* instruction address compare 2 */ -#define iac3 0x13a /* instruction address compare 3 */ -#define iac4 0x13b /* instruction address compare 4 */ -#define dac1 0x13c /* data address compare 1 */ -#define dac2 0x13d /* data address compare 2 */ -#define dvc1 0x13e /* data value compare 1 */ -#define dvc2 0x13f /* data value compare 2 */ -#define tsr 0x150 /* timer status register */ -#define tcr 0x154 /* timer control register */ -#define ivor0 0x190 /* interrupt vector offset register 0 */ -#define ivor1 0x191 /* interrupt vector offset register 1 */ -#define ivor2 0x192 /* interrupt vector offset register 2 */ -#define ivor3 0x193 /* interrupt vector offset register 3 */ -#define ivor4 0x194 /* interrupt vector offset register 4 */ -#define ivor5 0x195 /* interrupt vector offset register 5 */ -#define ivor6 0x196 /* interrupt vector offset register 6 */ -#define ivor7 0x197 /* interrupt vector offset register 7 */ -#define ivor8 0x198 /* interrupt vector offset register 8 */ -#define ivor9 0x199 /* interrupt vector offset register 9 */ -#define ivor10 0x19a /* interrupt vector offset register 10 */ -#define ivor11 0x19b /* interrupt vector offset register 11 */ -#define ivor12 0x19c /* interrupt vector offset register 12 */ -#define ivor13 0x19d /* interrupt vector offset register 13 */ -#define ivor14 0x19e /* interrupt vector offset register 14 */ -#define ivor15 0x19f /* interrupt vector offset register 15 */ -#if defined(CONFIG_440) -#define mcsrr0 0x23a /* machine check save/restore register 0 */ -#define mcsrr1 0x23b /* mahcine check save/restore register 1 */ -#define mcsr 0x23c /* machine check status register */ -#endif -#define inv0 0x370 /* instruction cache normal victim 0 */ -#define inv1 0x371 /* instruction cache normal victim 1 */ -#define inv2 0x372 /* instruction cache normal victim 2 */ -#define inv3 0x373 /* instruction cache normal victim 3 */ -#define itv0 0x374 /* instruction cache transient victim 0 */ -#define itv1 0x375 /* instruction cache transient victim 1 */ -#define itv2 0x376 /* instruction cache transient victim 2 */ -#define itv3 0x377 /* instruction cache transient victim 3 */ -#define dnv0 0x390 /* data cache normal victim 0 */ -#define dnv1 0x391 /* data cache normal victim 1 */ -#define dnv2 0x392 /* data cache normal victim 2 */ -#define dnv3 0x393 /* data cache normal victim 3 */ -#define dtv0 0x394 /* data cache transient victim 0 */ -#define dtv1 0x395 /* data cache transient victim 1 */ -#define dtv2 0x396 /* data cache transient victim 2 */ -#define dtv3 0x397 /* data cache transient victim 3 */ -#define dvlim 0x398 /* data cache victim limit */ -#define ivlim 0x399 /* instruction cache victim limit */ -#define rstcfg 0x39b /* reset configuration */ -#define dcdbtrl 0x39c /* data cache debug tag register low */ -#define dcdbtrh 0x39d /* data cache debug tag register high */ -#define icdbtrl 0x39e /* instruction cache debug tag register low */ -#define icdbtrh 0x39f /* instruction cache debug tag register high */ -#define mmucr 0x3b2 /* mmu control register */ -#define ccr0 0x3b3 /* core configuration register 0 */ -#define ccr1 0x378 /* core configuration for 440x5 only */ -#define icdbdr 0x3d3 /* instruction cache debug data register */ -#define dbdr 0x3f3 /* debug data register */ - /****************************************************************************** * DCRs & Related ******************************************************************************/ -- cgit From da799f66ad1d4fc36dd20cc2d7e584493fda8546 Mon Sep 17 00:00:00 2001 From: Matthias Fuchs Date: Mon, 20 Jul 2009 12:15:38 +0200 Subject: ppc4xx: Add struct for 4xx GPIO controller registers Signed-off-by: Matthias Fuchs Signed-off-by: Stefan Roese --- include/asm-ppc/gpio.h | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) (limited to 'include') diff --git a/include/asm-ppc/gpio.h b/include/asm-ppc/gpio.h index fc05dc0df7..23e29b195e 100644 --- a/include/asm-ppc/gpio.h +++ b/include/asm-ppc/gpio.h @@ -24,6 +24,8 @@ #ifndef __ASM_PPC_GPIO_H #define __ASM_PPC_GPIO_H +#include + /* 4xx PPC's have 2 GPIO controllers */ #if defined(CONFIG_405EZ) || \ defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ @@ -34,6 +36,28 @@ #define GPIO_GROUP_MAX 1 #endif +/* GPIO controller */ +struct ppc4xx_gpio { + u32 or; /* Output Control */ + u32 tcr; /* Tri-State Control */ + u32 osl; /* Output Select 16..31 */ + u32 osh; /* Output Select 0..15 */ + u32 tsl; /* Tri-State Select 16..31 */ + u32 tsh; /* Tri-State Select 0..15 */ + u32 odr; /* Open Drain */ + u32 ir; /* Input */ + u32 rr1; /* Receive Register 1 */ + u32 rr2; /* Receive Register 2 */ + u32 rr3; /* Receive Register 3 */ + u32 reserved; + u32 is1l; /* Input Select 1 16..31 */ + u32 is1h; /* Input Select 1 0..15 */ + u32 is2l; /* Input Select 2 16..31 */ + u32 is2h; /* Input Select 2 0..15 */ + u32 is3l; /* Input Select 3 16..31 */ + u32 is3h; /* Input Select 3 0..15 */ +}; + /* Offsets */ #define GPIOx_OR 0x00 /* GPIO Output Register */ #define GPIOx_TCR 0x04 /* GPIO Three-State Control Register */ -- cgit From 99d8b23bc7e2be04fcbf49c5cec9f5ae76df290c Mon Sep 17 00:00:00 2001 From: Matthias Fuchs Date: Wed, 22 Jul 2009 13:56:21 +0200 Subject: ppc4xx: Add 405EP based PMC405DE board Signed-off-by: Matthias Fuchs Signed-off-by: Stefan Roese --- include/configs/PMC405DE.h | 378 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 378 insertions(+) create mode 100644 include/configs/PMC405DE.h (limited to 'include') diff --git a/include/configs/PMC405DE.h b/include/configs/PMC405DE.h new file mode 100644 index 0000000000..5232745a0a --- /dev/null +++ b/include/configs/PMC405DE.h @@ -0,0 +1,378 @@ +/* + * (C) Copyright 2009 + * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd.eu + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_405EP 1 /* This is a PPC405 CPU */ +#define CONFIG_4xx 1 /* ...member of PPC4xx family */ +#define CONFIG_PMC405DE 1 /* ...on a PMC405DE board */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ +#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ +#define CONFIG_BOARD_TYPES 1 /* support board types */ + +#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */ + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ + +#undef CONFIG_BOOTARGS +#undef CONFIG_BOOTCOMMAND + +#define CONFIG_PREBOOT /* enable preboot variable */ + +#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change*/ + +#define CONFIG_NET_MULTI 1 +#define CONFIG_HAS_ETH1 + +#define CONFIG_PPC4xx_EMAC +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_ADDR 1 /* PHY address */ +#define CONFIG_PHY1_ADDR 2 /* 2nd PHY address */ + +#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_SEND_HOSTNAME + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_BSP +#define CONFIG_CMD_CHIP_CONFIG +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_ELF +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_MII +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PING + +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP + +#undef CONFIG_WATCHDOG /* watchdog disabled */ +#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ +#define CONFIG_PRAM 0 + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ + +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */ + +#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ +#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console info */ + +#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x3000000 /* 1 ... 48 MB in DRAM */ + +#undef CONFIG_SYS_EXT_SERIAL_CLOCK +#define CONFIG_SYS_BASE_BAUD 691200 +#define CONFIG_UART1_CONSOLE + +/* The following table includes the supported baudrates */ +#define CONFIG_SYS_BAUDRATE_TABLE \ + { 9600, 19200, 38400, 57600, 115200 } + +#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ +#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + +#define CONFIG_AUTOBOOT_KEYED 1 +#define CONFIG_AUTOBOOT_PROMPT \ + "Press SPACE to abort autoboot in %d seconds\n", bootdelay +#undef CONFIG_AUTOBOOT_DELAY_STR +#define CONFIG_AUTOBOOT_STOP_STR " " + +/* + * PCI stuff + */ +#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ +#define PCI_HOST_FORCE 1 /* configure as pci host */ +#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ + +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ +#define CONFIG_PCI_PNP /* do (not) pci plug-and-play */ + +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ + +/* + * PCI identification + */ +#define CONFIG_SYS_PCI_SUBSYS_VENDORID PCI_VENDOR_ID_ESDGMBH +#define CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH 0x040e /* Dev ID: Non-Monarch */ +#define CONFIG_SYS_PCI_SUBSYS_ID_MONARCH 0x040f /* Dev ID: Monarch */ +#define CONFIG_SYS_PCI_CLASSCODE_NONMONARCH PCI_CLASS_PROCESSOR_POWERPC +#define CONFIG_SYS_PCI_CLASSCODE_MONARCH PCI_CLASS_BRIDGE_HOST + +#define CONFIG_SYS_PCI_CLASSCODE CONFIG_SYS_PCI_CLASSCODE_MONARCH +#define CONFIG_SYS_PCI_SUBSYS_DEVICEID CONFIG_SYS_PCI_SUBSYS_ID_MONARCH + +#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ +#define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable=1 */ +#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ +#define CONFIG_SYS_PCI_PTM2LA 0xef000000 /* point to CPLD, GPIO */ +#define CONFIG_SYS_PCI_PTM2MS 0xff000001 /* 16MB, enable=1 */ +#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) +/* + * FLASH organization + */ +#define CONFIG_SYS_FLASH_CFI 1 /* CFI compatible */ +#define CONFIG_FLASH_CFI_DRIVER 1 /* Use common CFI driver */ + +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max. no. memory banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors per chip */ + +#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* erase timeout (in ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* write timeout (in ms) */ + +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* buffered writes (faster) */ +#define CONFIG_SYS_FLASH_PROTECTION 1 /* hardware flash protection */ + +#define CONFIG_SYS_FLASH_EMPTY_INFO 1 /* 'E' for empty sector (flinfo) */ +#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */ + + +/* + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 + */ +#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_FLASH_BASE 0xfe000000 +#define CONFIG_SYS_MONITOR_BASE TEXT_BASE +#define CONFIG_SYS_MONITOR_LEN (~(TEXT_BASE) + 1) +#define CONFIG_SYS_MALLOC_LEN (256 * 1024) + +/* + * Environment in EEPROM setup + */ +#define CONFIG_ENV_IS_IN_EEPROM 1 +#define CONFIG_ENV_OFFSET 0x100 +#define CONFIG_ENV_SIZE 0x700 + +/* + * I2C EEPROM (24W16) for environment + */ +#define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_I2C_SLAVE 0x7F + +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM 24W16 */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ +/* mask of address bits that overflow into the "EEPROM chip address" */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ + /* 16 byte page write mode using*/ + /* last 4 bits of the address */ +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ +#define CONFIG_SYS_EEPROM_WREN 1 + +#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x50 +#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0x40 +#define CONFIG_4xx_CONFIG_BLOCKSIZE 0x20 + +/* + * RTC + */ +#define CONFIG_RTC_RX8025 + +/* + * External Bus Controller (EBC) Setup + * (max. 55MHZ EBC clock) + */ +/* Memory Bank 0 (NOR flash) BAS=0xFE0,BS=32MB,BU=R/W,BW=16bit */ +#define CONFIG_SYS_EBC_PB0AP 0x03017200 +#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH_BASE | 0xba000) + +/* Memory Bank 1 (CPLD) BAS=0xEF0,BS=16MB,BU=R/W,BW=16bit */ +#define CONFIG_SYS_CPLD_BASE 0xef000000 +#define CONFIG_SYS_EBC_PB1AP 0x00800000 +#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_CPLD_BASE | 0x18000) + +/* + * Definitions for initial stack pointer and data area (in data cache) + */ +/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ +#define CONFIG_SYS_TEMP_STACK_OCM 1 + +/* On Chip Memory location */ +#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 +#define CONFIG_SYS_OCM_DATA_SIZE 0x1000 +/* inside SDRAM */ +#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR +/* End of used area in RAM */ +#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE + +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes res. for initial data */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \ + CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +/* + * GPIO Configuration + */ +#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO Alt1 */ \ +{ \ +/* GPIO Core 0 */ \ +{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast */ \ +{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \ +{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \ +{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \ +{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO5 TS3 */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO6 TS4 */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO7 TS5 */ \ +{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO9 TrcClk */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \ +{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \ +{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \ +{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 */ \ +{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 */ \ +{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 */ \ +{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 */ \ +{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 */ \ +{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 */ \ +{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 */ \ +{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 */ \ +{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \ +{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 */ \ +} \ +} + +#define CONFIG_SYS_GPIO_HWREV_MASK (0xf0000000 >> 1) /* GPIO1..4 */ +#define CONFIG_SYS_GPIO_HWREV_SHIFT 27 +#define CONFIG_SYS_GPIO_LEDRUN_N (0x80000000 >> 5) /* GPIO5 */ +#define CONFIG_SYS_GPIO_LEDA_N (0x80000000 >> 6) /* GPIO6 */ +#define CONFIG_SYS_GPIO_LEDB_N (0x80000000 >> 7) /* GPIO7 */ +#define CONFIG_SYS_GPIO_SELFRST_N (0x80000000 >> 8) /* GPIO8 */ +#define CONFIG_SYS_GPIO_EEPROM_WP (0x80000000 >> 9) /* GPIO9 */ +#define CONFIG_SYS_GPIO_MONARCH_N (0x80000000 >> 11) /* GPIO11 */ +#define CONFIG_SYS_GPIO_EREADY (0x80000000 >> 12) /* GPIO12 */ +#define CONFIG_SYS_GPIO_M66EN (0x80000000 >> 13) /* GPIO13 */ + +/* + * Default speed selection (cpu_plb_opb_ebc) in mhz. + * This value will be set if iic boot eprom is disabled. + */ +#undef CONFIG_SYS_FCPU333MHZ +#define CONFIG_SYS_FCPU266MHZ +#undef CONFIG_SYS_FCPU133MHZ + +#if defined(CONFIG_SYS_FCPU333MHZ) +/* + * CPU: 333MHz + * PLB/SDRAM/MAL: 111MHz + * OPB: 55MHz + * EBC: 55MHz + * PCI: 55MHz (111MHz on M66EN=1) + */ +#define PLLMR0_DEFAULT (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \ + PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \ + PLL_MALDIV_1 | PLL_PCIDIV_2) +#define PLLMR1_DEFAULT (PLL_FBKDIV_10 | \ + PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI) +#endif + +#if defined(CONFIG_SYS_FCPU266MHZ) +/* + * CPU: 266MHz + * PLB/SDRAM/MAL: 133MHz + * OPB: 66MHz + * EBC: 44MHz + * PCI: 44MHz (66MHz on M66EN=1) + */ +#define PLLMR0_DEFAULT (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ + PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \ + PLL_MALDIV_1 | PLL_PCIDIV_3) +#define PLLMR1_DEFAULT (PLL_FBKDIV_8 | \ + PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) +#endif + +#if defined(CONFIG_SYS_FCPU133MHZ) +/* + * CPU: 133MHz + * PLB/SDRAM/MAL: 133MHz + * OPB: 66MHz + * EBC: 44MHz + * PCI: 44MHz (66MHz on M66EN=1) + */ +#define PLLMR0_DEFAULT (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \ + PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \ + PLL_MALDIV_1 | PLL_PCIDIV_3) +#define PLLMR1_DEFAULT (PLL_FBKDIV_4 | \ + PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) +#endif + +#endif /* __CONFIG_H */ -- cgit From f6af8ce0c80327cb6aaa347642026ad838335c23 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Tue, 21 Jul 2009 14:33:52 +0200 Subject: ppc4xx: Fix EEPROM configuration on Kilauea Kilauea has an AT24C02 EEPROM which has an 8 byte page. Without defining CONFIG_SYS_EEPROM_PAGE_WRITE_BITS to 3 the "eeprom" command doesn't work correctly. Additionally the page write delay (CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS) is set to a more defensive value of 10ms. Signed-off-by: Stefan Roese --- include/configs/kilauea.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/kilauea.h b/include/configs/kilauea.h index df1b0612ce..1e7e731f94 100644 --- a/include/configs/kilauea.h +++ b/include/configs/kilauea.h @@ -374,9 +374,10 @@ *----------------------------------------------------------------------*/ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 6 /* 24C02 requires 5ms delay */ #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 /* I2C boot EEPROM (24C02BN) */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* Standard DTT sensor configuration */ #define CONFIG_DTT_DS1775 1 -- cgit From 4b1389e0ceb19e9b50b96fd3908483a6c2274fb0 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Tue, 21 Jul 2009 14:06:29 +0200 Subject: ppc4xx: Add chip_config command to AMCC Kilauea eval board This patch removes the "alterpll" command and replaces it with the now ppc4xx standard "chip_config" command to configure the I2C bootstrap EEPROM. Signed-off-by: Stefan Roese --- include/configs/kilauea.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'include') diff --git a/include/configs/kilauea.h b/include/configs/kilauea.h index 1e7e731f94..44bcbc0dc5 100644 --- a/include/configs/kilauea.h +++ b/include/configs/kilauea.h @@ -379,6 +379,11 @@ #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 +/* I2C bootstrap EEPROM */ +#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x52 +#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0 +#define CONFIG_4xx_CONFIG_BLOCKSIZE 16 + /* Standard DTT sensor configuration */ #define CONFIG_DTT_DS1775 1 #define CONFIG_DTT_SENSORS { 0 } @@ -427,6 +432,7 @@ /* * Commands additional to the ones defined in amcc-common.h */ +#define CONFIG_CMD_CHIP_CONFIG #define CONFIG_CMD_DATE #define CONFIG_CMD_LOG #define CONFIG_CMD_NAND -- cgit