From 41bbe4dd49a3825e024e874ee19c6527860a3f16 Mon Sep 17 00:00:00 2001 From: pekon gupta Date: Fri, 11 Apr 2014 12:55:30 +0530 Subject: mtd: nand: omap_elm: use bch_type instead of nibble count to differentiate between BCH4/BCH8/BCH16 ELM hardware engine support ECC error detection for multiple ECC strengths like +------+------------------------+ |Type | ECC syndrome length | +------+------------------------+ |BCH4 | 6.5 bytes = 13 nibbles | |BCH8 | 13 byte = 26 nibbles | |BCH16 | 26 bytes = 52 nibbles | +------+------------------------+ Current implementation of omap_elm driver uses ECC syndrom length (in 'nibbles') to differentiate between BCH4/BCH8/BCH16. This patch replaces it with 'bch_type' Signed-off-by: Pekon Gupta Reviewed-by: Stefan Roese --- include/linux/mtd/omap_elm.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/linux/mtd/omap_elm.h b/include/linux/mtd/omap_elm.h index 45454eaf0f..a6e9591d37 100644 --- a/include/linux/mtd/omap_elm.h +++ b/include/linux/mtd/omap_elm.h @@ -68,7 +68,7 @@ struct elm { struct location error_location[8]; /* 0x800 */ }; -int elm_check_error(u8 *syndrome, u32 nibbles, u32 *error_count, +int elm_check_error(u8 *syndrome, enum bch_level bch_type, u32 *error_count, u32 *error_locations); int elm_config(enum bch_level level); void elm_reset(void); -- cgit From 0439d752c5ad6cb95b1c8e1f922d74eee73d79a9 Mon Sep 17 00:00:00 2001 From: pekon gupta Date: Fri, 11 Apr 2014 12:55:31 +0530 Subject: mtd: nand: omap_elm: use macros for register definitions This patch adds macros for following parameters of ELM Hardware engine - ELM_MAX_CHANNELS: ELM can process 8 data streams simultaneously - ELM_MAX_ERRORS: ELM can detect upto 16 ECC error when using BCH16 scheme Signed-off-by: Pekon Gupta Reviewed-by: Stefan Roese --- include/linux/mtd/omap_elm.h | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/include/linux/mtd/omap_elm.h b/include/linux/mtd/omap_elm.h index a6e9591d37..b8096b02e3 100644 --- a/include/linux/mtd/omap_elm.h +++ b/include/linux/mtd/omap_elm.h @@ -24,6 +24,9 @@ #define ELM_LOCATION_STATUS_ECC_CORRECTABLE_MASK (0x100) #define ELM_LOCATION_STATUS_ECC_NB_ERRORS_MASK (0x1F) +#define ELM_MAX_CHANNELS 8 +#define ELM_MAX_ERROR_COUNT 16 + #ifndef __ASSEMBLY__ enum bch_level { @@ -43,7 +46,7 @@ struct syndrome { struct location { u32 location_status; /* 0x800 */ u8 res1[124]; /* 0x804 */ - u32 error_location_x[16]; /* 0x880.... */ + u32 error_location_x[ELM_MAX_ERROR_COUNT]; /* 0x880, 0x980, .. */ u8 res2[64]; /* 0x8c0 */ }; @@ -63,9 +66,9 @@ struct elm { u8 res2[92]; /* 0x024 */ u32 page_ctrl; /* 0x080 */ u8 res3[892]; /* 0x084 */ - struct syndrome syndrome_fragments[8]; /* 0x400 */ + struct syndrome syndrome_fragments[ELM_MAX_CHANNELS]; /* 0x400,0x420 */ u8 res4[512]; /* 0x600 */ - struct location error_location[8]; /* 0x800 */ + struct location error_location[ELM_MAX_CHANNELS]; /* 0x800,0x900 ... */ }; int elm_check_error(u8 *syndrome, enum bch_level bch_type, u32 *error_count, -- cgit From 27ce9e4290b168a1241699d411678959aaf9649b Mon Sep 17 00:00:00 2001 From: Brian Norris Date: Tue, 6 May 2014 00:46:17 +0530 Subject: mtd: nand: force NAND_CMD_READID onto 8-bit bus As per following Sections in ONFI Spec, NAND_CMD_READID should use only lower 8-bit for transfering command, address and data even on x16 NAND device. *Section: Target Initialization" "The Read ID and Read Parameter Page commands only use the lower 8-bits of the data bus. The host shall not issue commands that use a word data width on x16 devices until the host determines the device supports a 16-bit data bus width in the parameter page." *Section: Bus Width Requirements* "When the host supports a 16-bit bus width, only data is transferred at the 16-bit width. All address and command line transfers shall use only the lower 8-bits of the data bus. During command transfers, the host may place any value on the upper 8-bits of the data bus. During address transfers, the host shall set the upper 8-bits of the data bus to 00h." Thus porting following commit from linux-kernel to ensure that column address is not altered to align to x16 bus when issuing NAND_CMD_READID command. commit 3dad2344e92c6e1aeae42df1c4824f307c51bcc7 mtd: nand: force NAND_CMD_READID onto 8-bit bus Author: Brian Norris (preserving authorship) The NAND command helpers tend to automatically shift the column address for x16 bus devices, since most commands expect a word address, not a byte address. The Read ID command, however, expects an 8-bit address (i.e., 0x00, 0x20, or 0x40 should not be translated to 0x00, 0x10, or 0x20). This fixes the column address for a few drivers which imitate the nand_base defaults. Signed-off-by: Pekon Gupta --- include/linux/mtd/nand.h | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'include') diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h index 0546565593..4be885823c 100644 --- a/include/linux/mtd/nand.h +++ b/include/linux/mtd/nand.h @@ -719,4 +719,14 @@ static inline int onfi_get_sync_timing_mode(struct nand_chip *chip) } #endif +/** + * Check if the opcode's address should be sent only on the lower 8 bits + * @command: opcode to check + */ +static inline int nand_opcode_8bits(unsigned int command) +{ + return command == NAND_CMD_READID; +} + + #endif /* __LINUX_MTD_NAND_H */ -- cgit From 6e1899e633c2ac3f6da7101d4990361c6ff2a9d2 Mon Sep 17 00:00:00 2001 From: David Mosberger Date: Tue, 6 May 2014 00:46:18 +0530 Subject: mtd: nand: fix GET/SET_FEATURES address on 16-bit devices As per following Sections in ONFI Spec, GET_FEATURES and SET_FEATURES also need byte-addressing on 16-bit devices. *Section: Target Initialization" "The Read ID and Read Parameter Page commands only use the lower 8-bits of the data bus. The host shall not issue commands that use a word data width on x16 devices until the host determines the device supports a 16-bit data bus width in the parameter page." *Section: Bus Width Requirements* "When the host supports a 16-bit bus width, only data is transferred at the 16-bit width. All address and command line transfers shall use only the lower 8-bits of the data bus. During command transfers, the host may place any value on the upper 8-bits of the data bus. During address transfers, the host shall set the upper 8-bits of the data bus to 00h." So porting following commit from linux kernel commit e34fcb07a6d57411de6e15a47724fbe92c5caa42 Author: David Mosberger (preserving authorship) mtd: nand: fix GET/SET_FEATURES address on 16-bit devices Signed-off-by: Pekon Gupta --- include/linux/mtd/nand.h | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h index 4be885823c..991bd8e63e 100644 --- a/include/linux/mtd/nand.h +++ b/include/linux/mtd/nand.h @@ -725,7 +725,16 @@ static inline int onfi_get_sync_timing_mode(struct nand_chip *chip) */ static inline int nand_opcode_8bits(unsigned int command) { - return command == NAND_CMD_READID; + switch (command) { + case NAND_CMD_READID: + case NAND_CMD_PARAM: + case NAND_CMD_GET_FEATURES: + case NAND_CMD_SET_FEATURES: + return 1; + default: + break; + } + return 0; } -- cgit From b80a66033856cc89c62886ae3e5ba54a7faf31ae Mon Sep 17 00:00:00 2001 From: pekon gupta Date: Tue, 6 May 2014 00:46:19 +0530 Subject: mtd: nand: omap: add CONFIG_SYS_NAND_BUSWIDTH_16BIT to indicate NAND device bus-width GPMC controller needs to be configured based on bus-width of the NAND device connected to it. Also, dynamic detection of NAND bus-width from on-chip ONFI parameters is not possible in following situations: SPL: SPL NAND drivers does not support ONFI parameter reading. U-boot: GPMC controller iniitalization is done in omap_gpmc.c:board_nand_init() which is called before probing for devices, hence any ONFI parameter information is not available during GPMC initialization. Thus, OMAP NAND driver expected board developers to explicitely write GPMC configurations specific to NAND device attached on board in board files itself. But this was troublesome for board manufacturers as they need to dive into lengthy platform & SoC documents to find details of GPMC registers and appropriate configurations to get NAND device working. This patch instead adds existing CONFIG_SYS_NAND_BUSWIDTH_16BIT to board config hich indicates that connected NAND device has x16 bus-width. And then based on this config GPMC driver itself initializes itself based on NAND bus-width. This keeps board developers free from knowing GPMC controller specific internals. Signed-off-by: Pekon Gupta --- include/configs/am3517_crane.h | 1 + include/configs/devkit8000.h | 1 + include/configs/dig297.h | 1 + include/configs/omap3_beagle.h | 1 + include/configs/omap3_evm_common.h | 2 +- include/configs/omap3_igep00x0.h | 1 + include/configs/omap3_logic.h | 1 + include/configs/omap3_overo.h | 1 + include/configs/omap3_zoom1.h | 1 + include/configs/tam3517-common.h | 1 + include/configs/tao3530.h | 1 + 11 files changed, 11 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h index 4407b454dd..ad4cbd88b8 100644 --- a/include/configs/am3517_crane.h +++ b/include/configs/am3517_crane.h @@ -329,6 +329,7 @@ #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" /* NAND boot config */ +#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16 #define CONFIG_SYS_NAND_5_ADDR_CYCLE #define CONFIG_SYS_NAND_PAGE_COUNT 64 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h index 16a00ebe86..5308790fe6 100644 --- a/include/configs/devkit8000.h +++ b/include/configs/devkit8000.h @@ -314,6 +314,7 @@ #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* NAND boot config */ +#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16 #define CONFIG_SYS_NAND_5_ADDR_CYCLE #define CONFIG_SYS_NAND_PAGE_COUNT 64 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 diff --git a/include/configs/dig297.h b/include/configs/dig297.h index af6f56bb34..ce205e9b3e 100644 --- a/include/configs/dig297.h +++ b/include/configs/dig297.h @@ -138,6 +138,7 @@ * Board NAND Info. */ #define CONFIG_NAND_OMAP_GPMC +#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ /* to access nand */ #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index 0a7df60f28..c02348354a 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -295,6 +295,7 @@ #define CONFIG_SPL_OMAP3_ID_NAND /* NAND boot config */ +#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16 #define CONFIG_SYS_NAND_5_ADDR_CYCLE #define CONFIG_SYS_NAND_PAGE_COUNT 64 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 diff --git a/include/configs/omap3_evm_common.h b/include/configs/omap3_evm_common.h index 7f3424b4f0..ae4ce63f67 100644 --- a/include/configs/omap3_evm_common.h +++ b/include/configs/omap3_evm_common.h @@ -120,7 +120,7 @@ /* Max number of NAND devices */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 - +#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16 /* Timeout values (in ticks) */ #define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) #define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) diff --git a/include/configs/omap3_igep00x0.h b/include/configs/omap3_igep00x0.h index d56d5b00cc..79daabd6bb 100644 --- a/include/configs/omap3_igep00x0.h +++ b/include/configs/omap3_igep00x0.h @@ -187,6 +187,7 @@ /* NAND boot config */ #ifdef CONFIG_NAND +#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16 #define CONFIG_SYS_NAND_5_ADDR_CYCLE #define CONFIG_SYS_NAND_PAGE_COUNT 64 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h index 0d03c75ce3..8dcbba3c40 100644 --- a/include/configs/omap3_logic.h +++ b/include/configs/omap3_logic.h @@ -141,6 +141,7 @@ #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ /* NAND devices */ +#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16 #define CONFIG_JFFS2_NAND /* nand device jffs2 lives on */ #define CONFIG_JFFS2_DEV "nand0" diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h index 7b97be9ace..1a13633949 100644 --- a/include/configs/omap3_overo.h +++ b/include/configs/omap3_overo.h @@ -206,6 +206,7 @@ #define CONFIG_SYS_CACHELINE_SIZE 64 /* NAND boot config */ +#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16 #define CONFIG_SYS_NAND_5_ADDR_CYCLE #define CONFIG_SYS_NAND_PAGE_COUNT 64 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h index 7c5540ff66..3efe4cf815 100644 --- a/include/configs/omap3_zoom1.h +++ b/include/configs/omap3_zoom1.h @@ -98,6 +98,7 @@ #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ /* to access nand at */ /* CS0 */ +#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16 /* Environment information */ diff --git a/include/configs/tam3517-common.h b/include/configs/tam3517-common.h index 3522c1a07a..eda536b866 100644 --- a/include/configs/tam3517-common.h +++ b/include/configs/tam3517-common.h @@ -249,6 +249,7 @@ #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* NAND boot config */ +#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16 #define CONFIG_SYS_NAND_PAGE_COUNT 64 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 #define CONFIG_SYS_NAND_OOBSIZE 64 diff --git a/include/configs/tao3530.h b/include/configs/tao3530.h index 9c04c23ab7..4471935287 100644 --- a/include/configs/tao3530.h +++ b/include/configs/tao3530.h @@ -141,6 +141,7 @@ #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ /* devices */ +#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16 /* Environment information */ #define CONFIG_BOOTDELAY 3 -- cgit From 68128e0a86810c9ea9bebcb69451aeabfd44c491 Mon Sep 17 00:00:00 2001 From: pekon gupta Date: Tue, 6 May 2014 00:46:20 +0530 Subject: omap3: remove remnant macros GPMC_NAND_ECC_LP_x8_LAYOUT and GPMC_NAND_ECC_LP_x16_LAYOUT OMAP3 used GPMC_NAND_ECC_LP_x8_LAYOUT and GPMC_NAND_ECC_LP_x16_LAYOUT macros to configure GPMC controller for x7 or x8 bit device connected to its interface. Now this information is encoded in CONFIG_SYS_NAND_DEVICE_WIDTH macro, so above macros can be completely removed. Signed-off-by: Pekon Gupta --- include/configs/cm_t335.h | 1 - include/configs/cm_t35.h | 1 - include/configs/pengwyn.h | 1 - include/configs/tao3530.h | 1 - include/configs/tseries.h | 1 - 5 files changed, 5 deletions(-) (limited to 'include') diff --git a/include/configs/cm_t335.h b/include/configs/cm_t335.h index 26b615b8c5..4d1dd28a91 100644 --- a/include/configs/cm_t335.h +++ b/include/configs/cm_t335.h @@ -141,7 +141,6 @@ #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x200000 #define CONFIG_CMD_NAND -#define GPMC_NAND_ECC_LP_x8_LAYOUT #define MTDIDS_DEFAULT "nand0=nand" #define MTDPARTS_DEFAULT "mtdparts=nand:2m(spl)," \ "1m(u-boot),1m(u-boot-env)," \ diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h index aae05e0333..8c60e22c1d 100644 --- a/include/configs/cm_t35.h +++ b/include/configs/cm_t35.h @@ -158,7 +158,6 @@ /* CS0 */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ /* devices */ -#define GPMC_NAND_ECC_LP_x8_LAYOUT /* Environment information */ #define CONFIG_BOOTDELAY 3 diff --git a/include/configs/pengwyn.h b/include/configs/pengwyn.h index fc25966e0f..85104057a9 100644 --- a/include/configs/pengwyn.h +++ b/include/configs/pengwyn.h @@ -149,7 +149,6 @@ #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 -#define GPMC_NAND_ECC_LP_x8_LAYOUT 1 #define MTDIDS_DEFAULT "nand0=omap2-nand.0" #define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:128k(SPL)," \ "128k(SPL.backup1)," \ diff --git a/include/configs/tao3530.h b/include/configs/tao3530.h index 4471935287..1b0fee9a80 100644 --- a/include/configs/tao3530.h +++ b/include/configs/tao3530.h @@ -137,7 +137,6 @@ #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ /* to access nand at */ /* CS0 */ -#define GPMC_NAND_ECC_LP_x16_LAYOUT #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ /* devices */ diff --git a/include/configs/tseries.h b/include/configs/tseries.h index e550afad4f..1fd6e32baf 100644 --- a/include/configs/tseries.h +++ b/include/configs/tseries.h @@ -157,7 +157,6 @@ /* don't change OMAP_ELM, ECCSCHEME. ROM code only supports this */ #define CONFIG_NAND_OMAP_ELM #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW -#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 #define CONFIG_SYS_NAND_5_ADDR_CYCLE #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) #define CONFIG_SYS_NAND_PAGE_SIZE 2048 -- cgit From 8d13a730dea1b5b4d32b31b5584cb8fdea27a248 Mon Sep 17 00:00:00 2001 From: pekon gupta Date: Mon, 2 Jun 2014 17:14:41 +0530 Subject: mtd: nand: omap_gpmc: use macro for register definitions GPMC can support simultaneous processing of 8 512Byte data chunks, in parallel Signed-off-by: Pekon Gupta --- include/linux/mtd/omap_gpmc.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/linux/mtd/omap_gpmc.h b/include/linux/mtd/omap_gpmc.h index 22f6573969..d55fe328e6 100644 --- a/include/linux/mtd/omap_gpmc.h +++ b/include/linux/mtd/omap_gpmc.h @@ -11,6 +11,7 @@ #define GPMC_BUF_EMPTY 0 #define GPMC_BUF_FULL 1 +#define GPMC_MAX_SECTORS 8 enum omap_ecc { /* 1-bit ECC calculation by Software, Error detection by Software */ @@ -75,7 +76,7 @@ struct gpmc { u8 res7[12]; /* 0x224 */ u32 testmomde_ctrl; /* 0x230 */ u8 res8[12]; /* 0x234 */ - struct bch_res_0_3 bch_result_0_3[2]; /* 0x240 */ + struct bch_res_0_3 bch_result_0_3[GPMC_MAX_SECTORS]; /* 0x240,0x250, */ }; /* Used for board specific gpmc initialization */ -- cgit From 46840f66caf564866d191886d2bd86742f982010 Mon Sep 17 00:00:00 2001 From: pekon gupta Date: Mon, 2 Jun 2014 17:14:42 +0530 Subject: mtd: nand: omap: add support for BCH16_ECC - NAND driver updates This patch add support for BCH16_ECC to omap_gpmc driver. *need to BCH16 ECC scheme* With newer SLC Flash technologies and MLC NAND, and large densities, pagesizes Flash devices have become more suspectible to bit-flips. Thus stronger ECC schemes are required for protecting the data. But stronger ECC schemes have come with larger-sized ECC syndromes which require more space in OOB/Spare. This puts constrains like; (a) BCH16_ECC can correct 16 bit-flips per 512Bytes of data. (b) BCH16_ECC generates 26-bytes of ECC syndrome / 512B. Due to (b) this scheme can only be used with NAND devices which have enough OOB to satisfy following equation: OOBsize per page >= 26 * (page-size / 512) Signed-off-by: Pekon Gupta --- include/linux/mtd/omap_gpmc.h | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'include') diff --git a/include/linux/mtd/omap_gpmc.h b/include/linux/mtd/omap_gpmc.h index d55fe328e6..9a8658257f 100644 --- a/include/linux/mtd/omap_gpmc.h +++ b/include/linux/mtd/omap_gpmc.h @@ -27,6 +27,8 @@ enum omap_ecc { OMAP_ECC_BCH8_CODE_HW_DETECTION_SW, /* 8-bit ECC calculation by GPMC, Error detection by ELM */ OMAP_ECC_BCH8_CODE_HW, + /* 16-bit ECC calculation by GPMC, Error detection by ELM */ + OMAP_ECC_BCH16_CODE_HW, }; struct gpmc_cs { @@ -47,6 +49,10 @@ struct bch_res_0_3 { u32 bch_result_x[4]; }; +struct bch_res_4_6 { + u32 bch_result_x[3]; +}; + struct gpmc { u8 res1[0x10]; u32 sysconfig; /* 0x10 */ @@ -77,6 +83,8 @@ struct gpmc { u32 testmomde_ctrl; /* 0x230 */ u8 res8[12]; /* 0x234 */ struct bch_res_0_3 bch_result_0_3[GPMC_MAX_SECTORS]; /* 0x240,0x250, */ + u8 res9[16 * 4]; /* 0x2C0 - 0x2FF */ + struct bch_res_4_6 bch_result_4_6[GPMC_MAX_SECTORS]; /* 0x300,0x310, */ }; /* Used for board specific gpmc initialization */ -- cgit From 7a5f71bc4056591574ea122ba58c55d14145eeb0 Mon Sep 17 00:00:00 2001 From: Sourav Poddar Date: Mon, 19 May 2014 16:53:37 -0400 Subject: am43xx_evm: Add qspiboot target The ePOS EVM and EVM SK have QSPI as an option to boot. Add a qspiboot target that utilizes QSPI for env and so forth as an example of best practices. As QSPI is booted from directly we need to chang CONFIG_SYS_TEXT_BASE. Note that on ePOS EVM the QSPI and NAND are mutually exclusive choices we need to handle that elsewhere, once NAND support is also added. Signed-off-by: Sourav Poddar Signed-off-by: Tom Rini --- include/configs/am43xx_evm.h | 31 ++++++++++++++++++++++++++++--- include/configs/ti_armv7_common.h | 3 ++- 2 files changed, 30 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index d5e6c4b0dc..c1c0035d71 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -48,15 +48,15 @@ * Since SPL did pll and ddr initialization for us, * we don't need to do it twice. */ -#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NOR_BOOT) +#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_QSPI_BOOT) #define CONFIG_SKIP_LOWLEVEL_INIT #endif /* Now bring in the rest of the common code. */ #include -/* Always 128 KiB env size */ -#define CONFIG_ENV_SIZE (128 << 10) +/* Always 64 KiB env size */ +#define CONFIG_ENV_SIZE (64 << 10) #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG @@ -86,6 +86,30 @@ #define CONFIG_OMAP_USB_PHY #define CONFIG_AM437X_USB2PHY2_HOST +#ifdef CONFIG_QSPI_BOOT +#define CONFIG_SYS_TEXT_BASE 0x30000000 +#undef CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64 KB sectors */ +#define CONFIG_ENV_OFFSET 0x110000 +#define CONFIG_ENV_OFFSET_REDUND 0x120000 +#ifdef MTDIDS_DEFAULT +#undef MTDIDS_DEFAULT +#endif +#ifdef MTDPARTS_DEFAULT +#undef MTDPARTS_DEFAULT +#endif +#define MTDPARTS_DEFAULT "mtdparts=qspi.0:512k(QSPI.u-boot)," \ + "512k(QSPI.u-boot.backup)," \ + "512k(QSPI.u-boot-spl-os)," \ + "64k(QSPI.u-boot-env)," \ + "64k(QSPI.u-boot-env.backup)," \ + "8m(QSPI.kernel)," \ + "-(QSPI.file-system)" +#endif + /* SPI */ #undef CONFIG_OMAP3_SPI #define CONFIG_TI_QSPI @@ -94,6 +118,7 @@ #define CONFIG_CMD_SF #define CONFIG_CMD_SPI #define CONFIG_TI_SPI_MMAP +#define CONFIG_SPI_FLASH_BAR #define CONFIG_QSPI_SEL_GPIO 48 #define CONFIG_SF_DEFAULT_SPEED 48000000 #define CONFIG_DEFAULT_SPI_MODE SPI_MODE_3 diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h index 485427276a..698291852b 100644 --- a/include/configs/ti_armv7_common.h +++ b/include/configs/ti_armv7_common.h @@ -196,7 +196,8 @@ * under common/spl/. Given our generally common memory map, we set a * number of related defaults and sizes here. */ -#ifndef CONFIG_NOR_BOOT +#if !defined(CONFIG_NOR_BOOT) && \ + !(defined(CONFIG_QSPI_BOOT) && defined(CONFIG_AM43XX)) #define CONFIG_SPL #define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_OS_BOOT -- cgit From 196311dc728bbb9484356547b9daa731ca2feb8d Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 21 May 2014 12:57:22 -0400 Subject: arm:am33xx: Rework s_init and add board_early_init_f With the changes to the i2c framework (and adopting the omap24xx_i2c driver to them) we can no longer call i2c functions prior to gd having been set and cleared. When SPL booting, this is handled by setting gd to point to SRAM in s_init. However in the cases where we are loaded directly by ROM (memory mapped NOR or QSPI) we need to make use of the normal hooks to slightly delay these calls. Signed-off-by: Tom Rini --- include/configs/am43xx_evm.h | 9 +++++++++ include/configs/ti_am335x_common.h | 9 +++++++++ 2 files changed, 18 insertions(+) (limited to 'include') diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index c1c0035d71..8473b0bf5a 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -52,6 +52,15 @@ #define CONFIG_SKIP_LOWLEVEL_INIT #endif +/* + * When building U-Boot such that there is no previous loader + * we need to call board_early_init_f. This is taken care of in + * s_init when we have SPL used. + */ +#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && !defined(CONFIG_SPL) +#define CONFIG_BOARD_EARLY_INIT_F +#endif + /* Now bring in the rest of the common code. */ #include diff --git a/include/configs/ti_am335x_common.h b/include/configs/ti_am335x_common.h index 128b66edef..80976e7e3b 100644 --- a/include/configs/ti_am335x_common.h +++ b/include/configs/ti_am335x_common.h @@ -75,6 +75,15 @@ #define CONFIG_SKIP_LOWLEVEL_INIT #endif +/* + * When building U-Boot such that there is no previous loader + * we need to call board_early_init_f. This is taken care of in + * s_init when we have SPL used. + */ +#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && !defined(CONFIG_SPL) +#define CONFIG_BOARD_EARLY_INIT_F +#endif + #ifdef CONFIG_NAND #define CONFIG_SPL_NAND_AM33XX_BCH /* ELM support */ #endif -- cgit From afee59cd49449e7b7d538d919b6e8ab5184e5b93 Mon Sep 17 00:00:00 2001 From: Murali Karicheri Date: Thu, 29 May 2014 18:57:12 +0300 Subject: keystone: init: enable UART1 to be able use it from kernel Currently PWREMU_MGMT is not configured in the Linux generic UART driver as this register seems to be specific TI UART IP. So this needs to be enabled in u-boot to use UART1 from kernel space. Acked-By: Vitaly Andrianov Signed-off-by: Murali Karicheri Signed-off-by: Ivan Khoronzhuk --- include/configs/k2hk_evm.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/k2hk_evm.h b/include/configs/k2hk_evm.h index dde73298fc..998390e321 100644 --- a/include/configs/k2hk_evm.h +++ b/include/configs/k2hk_evm.h @@ -71,7 +71,8 @@ #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_MEM32 #define CONFIG_SYS_NS16550_REG_SIZE -4 -#define CONFIG_SYS_NS16550_COM1 K2HK_UART0_BASE +#define CONFIG_SYS_NS16550_COM1 KS2_UART0_BASE +#define CONFIG_SYS_NS16550_COM2 KS2_UART1_BASE #define CONFIG_SYS_NS16550_CLK clk_get_rate(K2HK_CLK1_6) #define CONFIG_CONS_INDEX 1 #define CONFIG_BAUDRATE 115200 -- cgit From 1dbb64dcf9d7b9894d3ed6a19a23ac4dbb2b1664 Mon Sep 17 00:00:00 2001 From: WingMan Kwok Date: Thu, 29 May 2014 18:58:16 +0300 Subject: keystone: k2hk: enable support of nand ecclayout command Enable support of nand ecclayout command. Acked-By: Murali Karicheri Acked-by: Vitaly Andrianov Signed-off-by: WingMan Kwok Signed-off-by: Ivan Khoronzhuk --- include/configs/k2hk_evm.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/k2hk_evm.h b/include/configs/k2hk_evm.h index 998390e321..6ba7e62e55 100644 --- a/include/configs/k2hk_evm.h +++ b/include/configs/k2hk_evm.h @@ -131,6 +131,7 @@ /* NAND Configuration */ #define CONFIG_NAND_DAVINCI +#define CONFIG_CMD_NAND_ECCLAYOUT #define CONFIG_SYS_NAND_CS 2 #define CONFIG_SYS_NAND_USE_FLASH_BBT #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST -- cgit From 0970051d13501c150841d7f6f0ecc7372ef619fd Mon Sep 17 00:00:00 2001 From: Jeroen Hofstee Date: Sat, 31 May 2014 17:08:30 +0200 Subject: tam3517: fix NAND detection commit a0a37183bd7 "ARM: omap: merge GPMC initialization code for all platform" needs CONFIG_NOR, CONFIG_NAND or CONFIG_CMD_ONENAND to be set to access flash. Add CONFIG_NAND for tam3517 derived boards to prevent the following error: "nand: error: Unable to find NAND settings in GPMC Configuration - quitting" cc: Stefano Babic Signed-off-by: Jeroen Hofstee --- include/configs/tam3517-common.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/tam3517-common.h b/include/configs/tam3517-common.h index eda536b866..0c2f0f19c8 100644 --- a/include/configs/tam3517-common.h +++ b/include/configs/tam3517-common.h @@ -185,6 +185,7 @@ /* Configure the PISMO */ #define PISMO1_NAND_SIZE GPMC_SIZE_128M +#define CONFIG_NAND #define CONFIG_NAND_OMAP_GPMC #define CONFIG_ENV_IS_IN_NAND #define SMNAND_ENV_OFFSET 0x180000 /* environment starts here */ -- cgit From fa03834fdf62eb40bc2d47c0e4289d6c250cb148 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Mon, 2 Jun 2014 10:45:38 +0530 Subject: ARM: AM43xx: Fix mmcboot command in EXTRA_ENV_SETTINGS loadbootenv expects devtype variable to be set. This is missing in mmcboot command. With this the following error comes: U-Boot# run mmcboot mmc0 is current device SD/MMC found on device 0 ** Bad device usb 0 ** ** Bad device usb 0 ** Fixing this by setting devtype as mmc. Reported-by: Tony Lindgren Signed-off-by: Lokesh Vutla --- include/configs/am43xx_evm.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index 8473b0bf5a..8359621247 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -179,6 +179,7 @@ "loadfdt=load ${devtype} ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \ "mmcboot=mmc dev ${mmcdev}; " \ "setenv devnum ${mmcdev}; " \ + "setenv devtype mmc; " \ "if mmc rescan; then " \ "echo SD/MMC found on device ${devnum};" \ "if run loadbootenv; then " \ -- cgit From 29a0d9c08eb653556eeb40b187325c0f57bf87dc Mon Sep 17 00:00:00 2001 From: Hannes Petermaier Date: Wed, 4 Jun 2014 10:22:07 +0200 Subject: board/BuR/common: introduce usage of CONFIG_SYS_GENERIC_BOARD Signed-off-by: Hannes Petermaier --- include/configs/bur_am335x_common.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/configs/bur_am335x_common.h b/include/configs/bur_am335x_common.h index 7adc8c0fd7..2edffea2e0 100644 --- a/include/configs/bur_am335x_common.h +++ b/include/configs/bur_am335x_common.h @@ -12,6 +12,8 @@ #ifndef __BUR_AM335X_COMMON_H__ #define __BUR_AM335X_COMMON_H__ /* ------------------------------------------------------------------------- */ +#define CONFIG_SYS_GENERIC_BOARD + #define CONFIG_AM33XX #define CONFIG_OMAP #define CONFIG_OMAP_COMMON -- cgit From 3e6a52c6ca0d1d3aee8eccb1a3ea19cc50919640 Mon Sep 17 00:00:00 2001 From: Hannes Petermaier Date: Wed, 4 Jun 2014 10:28:39 +0200 Subject: board/BuR/common: Add CONFIG_CMD_I2C in almost all cases we need the i2c commands within the u-boot shell. So we enable them within the common section. Cc: trini@ti.com Signed-off-by: Hannes Petermaier --- include/configs/bur_am335x_common.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/bur_am335x_common.h b/include/configs/bur_am335x_common.h index 2edffea2e0..5a37536b0a 100644 --- a/include/configs/bur_am335x_common.h +++ b/include/configs/bur_am335x_common.h @@ -96,7 +96,7 @@ #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 #define CONFIG_SYS_I2C_OMAP24XX - +#define CONFIG_CMD_I2C /* GPIO */ #define CONFIG_OMAP_GPIO #define CONFIG_CMD_GPIO -- cgit From 86db550b3864bcb3c9567fbdb67b49a244f5263e Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Thu, 5 Jun 2014 11:15:29 -0400 Subject: power: Add support for the TPS65218 PMIC Add a driver for the TPS65218 PMIC which is used by TI AM43xx SoCs and may be used by TI AM335x SoCs. Signed-off-by: Tom Rini --- include/power/tps65218.h | 63 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 63 insertions(+) create mode 100644 include/power/tps65218.h (limited to 'include') diff --git a/include/power/tps65218.h b/include/power/tps65218.h new file mode 100644 index 0000000000..67aa2f8c8d --- /dev/null +++ b/include/power/tps65218.h @@ -0,0 +1,63 @@ +/* + * (C) Copyright 2014 + * Texas Instruments, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __POWER_TPS65218_H__ +#define __POWER_TPS65218_H__ + +/* I2C chip address */ +#define TPS65218_CHIP_PM 0x24 + +/* Registers */ +enum { + TPS65218_CHIPID = 0x00, + TPS65218_INT1, + TPS65218_INT2, + TPS65218_INT_MASK1, + TPS65218_INT_MASK2, + TPS65218_STATUS, + TPS65218_CONTROL, + TPS65218_FLAG, + TPS65218_PASSWORD = 0x10, + TPS65218_ENABLE1, + TPS65218_ENABLE2, + TPS65218_CONFIG1, + TPS65218_CONFIG2, + TPS65218_CONFIG3, + TPS65218_DCDC1, + TPS65218_DCDC2, + TPS65218_DCDC3, + TPS65218_DCDC4, + TPS65218_SLEW, + TPS65218_LDO1, + TPS65218_SEQ1 = 0x20, + TPS65218_SEQ2, + TPS65218_SEQ3, + TPS65218_SEQ4, + TPS65218_SEQ5, + TPS65218_SEQ6, + TPS65218_SEQ7, + TPS65218_PMIC_NUM_OF_REGS, +}; + +#define TPS65218_PROT_LEVEL_NONE 0x00 +#define TPS65218_PROT_LEVEL_1 0x01 +#define TPS65218_PROT_LEVEL_2 0x02 + +#define TPS65218_PASSWORD_LOCK_FOR_WRITE 0x00 +#define TPS65218_PASSWORD_UNLOCK 0x7D + +#define TPS65218_DCDC_GO 0x80 + +#define TPS65218_MASK_ALL_BITS 0xFF + +#define TPS65218_DCDC_VOLT_SEL_1100MV 0x19 +#define TPS65218_DCDC_VOLT_SEL_1330MV 0x30 + +int tps65218_reg_write(uchar prot_level, uchar dest_reg, uchar dest_val, + uchar mask); +int tps65218_voltage_update(uchar dc_cntrl_reg, uchar volt_sel); +#endif /* __POWER_TPS65218_H__ */ -- cgit From 83bad1026b9e3a4f6b7783cc1cbb434c1bbd3fa2 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Thu, 5 Jun 2014 11:15:30 -0400 Subject: arm:am43xx: Add TPS65218 support to scale voltages up This family is supported by the TPS65218 PMIC. Implement a scale_vcores to set the MPU and CORE voltage correctly to the max frequency that is supported (and what we will be scaling them to in setup_dplls()). Signed-off-by: Tom Rini --- include/configs/am43xx_evm.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'include') diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index 8359621247..823cba6ff4 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -32,11 +32,15 @@ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 #define CONFIG_SYS_I2C_MULTI_EEPROMS +/* Power */ +#define CONFIG_POWER_TPS65218 + /* SPL defines. */ #define CONFIG_SPL_TEXT_BASE 0x40300350 #define CONFIG_SPL_MAX_SIZE (220 << 10) /* 220KB */ #define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \ (128 << 20)) +#define CONFIG_SPL_POWER_SUPPORT #define CONFIG_SPL_YMODEM_SUPPORT /* Enabling L2 Cache */ -- cgit