From 845c6c95dbfe6c915ce68a0a115852fa17932fb4 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Sat, 5 Jan 2008 09:12:41 +0100 Subject: ppc4xx: Update Katmai/44x_spd_ddr2.c code for optimal DDR2 setup On Katmai the complete auto-calibration somehow doesn't seem to produce the best results, meaning optimal values for RQFD/RFFD. This was discovered by GDA using a high bandwidth scope, analyzing the DDR2 signals. GDA provided a fixed value for RQFD, so now on Katmai "only" RFFD is auto-calibrated. This patch also adds RDCC calibration as mentioned on page 7 of the AMCC PowerPC440SP/SPe DDR2 application note: "DDR1/DDR2 Initialization Sequence and Dynamic Tuning" Signed-off-by: Stefan Roese --- include/configs/katmai.h | 1 + include/ppc440.h | 12 ++++++++++-- 2 files changed, 11 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/configs/katmai.h b/include/configs/katmai.h index 0aa4f2dcc0..78c794a05d 100644 --- a/include/configs/katmai.h +++ b/include/configs/katmai.h @@ -111,6 +111,7 @@ #define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */ #define SPD_EEPROM_ADDRESS {0x51, 0x52} /* SPD i2c spd addresses*/ #define CONFIG_DDR_ECC 1 /* with ECC support */ +#define CONFIG_DDR_RQDC_FIXED 0x80000038 /* optimal value found by GDA*/ #undef CONFIG_STRESS /*----------------------------------------------------------------------- diff --git a/include/ppc440.h b/include/ppc440.h index 90e56b0989..bfd1e10338 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -492,6 +492,7 @@ #define SDRAM_ECCCR 0x98 /* ECC error status */ #define SDRAM_CID 0xA4 /* core ID */ #define SDRAM_RID 0xA8 /* revision ID */ +#define SDRAM_RTSR 0xB1 /* run time status tracking */ /*-----------------------------------------------------------------------------+ | Memory Controller Status @@ -605,8 +606,8 @@ #define SDRAM_RFDC_ARSE_ENABLE 0x00000000 #define SDRAM_RFDC_RFOS_MASK 0x007F0000 #define SDRAM_RFDC_RFOS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16) -#define SDRAM_RFDC_RFFD_MASK 0x000003FF -#define SDRAM_RFDC_RFFD_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0) +#define SDRAM_RFDC_RFFD_MASK 0x000007FF +#define SDRAM_RFDC_RFFD_ENCODE(n) ((((unsigned long)(n))&0x7FF)<<0) #define SDRAM_RFDC_RFFD_MAX 0x7FF @@ -690,6 +691,7 @@ #define SDRAM_CLKTR_CLKP_MASK 0xC0000000 #define SDRAM_CLKTR_CLKP_0_DEG 0x00000000 #define SDRAM_CLKTR_CLKP_180_DEG_ADV 0x80000000 +#define SDRAM_CLKTR_CLKP_90_DEG_ADV 0x40000000 /*-----------------------------------------------------------------------------+ | SDRAM Write Timing Register @@ -790,6 +792,12 @@ #define SDRAM_BXCF_M_BE_DISABLE 0x00000000 /* Memory Bank Enable */ #define SDRAM_BXCF_M_BE_ENABLE 0x00000001 /* Memory Bank Enable */ +#define SDRAM_RTSR_TRK1SM_MASK 0xC0000000 /* Tracking State Mach 1*/ +#define SDRAM_RTSR_TRK1SM_ATBASE 0x00000000 /* atbase state */ +#define SDRAM_RTSR_TRK1SM_MISSED 0x40000000 /* missed state */ +#define SDRAM_RTSR_TRK1SM_ATPLS1 0x80000000 /* atpls1 state */ +#define SDRAM_RTSR_TRK1SM_RESET 0xC0000000 /* reset state */ + #define SDR0_MFR_FIXD 0x10000000 /* Workaround for PCI/DMA */ #endif /* CONFIG_440SPE */ -- cgit