From ccdb7c2255bde555bd0d4e104f8d228e25b76572 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Thu, 15 Nov 2018 11:04:50 +0530 Subject: armv7r: K3: Allow SPL to run only on core 0 Based on the MCU R5 efuse settings, R5F cores in MCU domain either work in split mode or in lock step mode. If efuse settings are in lockstep mode: ROM release R5 cores and SPL continues to run on the R5 core is lockstep mode. If efuse settings are in split mode: ROM releases both the R5 cores simultaneously and allow SPL to run on both the cores. In this case it is bootloader's responsibility to detect core 1 and park it. Else both the core will be running bootloader independently which might result in an unexpected behaviour. Signed-off-by: Lokesh Vutla Reviewed-by: Tom Rini --- include/configs/am65x_evm.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/configs/am65x_evm.h b/include/configs/am65x_evm.h index 484c5ef2fe..31749c6d06 100644 --- a/include/configs/am65x_evm.h +++ b/include/configs/am65x_evm.h @@ -29,7 +29,9 @@ #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "tispl.bin" #endif +#ifndef CONFIG_CPU_V7R #define CONFIG_SKIP_LOWLEVEL_INIT +#endif #define CONFIG_SPL_MAX_SIZE CONFIG_SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE + \ -- cgit