From c816dcb118e26ba17e7d73989514fec08a3823ac Mon Sep 17 00:00:00 2001 From: Magnus Lilja Date: Wed, 11 Nov 2009 20:18:42 +0100 Subject: MX31: Add struct definition for clock control module in i.MX31. Signed-off-by: Magnus Lilja --- include/asm-arm/arch-mx31/mx31-regs.h | 39 +++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) (limited to 'include') diff --git a/include/asm-arm/arch-mx31/mx31-regs.h b/include/asm-arm/arch-mx31/mx31-regs.h index 51b02a2a26..6f6e9a4048 100644 --- a/include/asm-arm/arch-mx31/mx31-regs.h +++ b/include/asm-arm/arch-mx31/mx31-regs.h @@ -24,6 +24,45 @@ #ifndef __ASM_ARCH_MX31_REGS_H #define __ASM_ARCH_MX31_REGS_H +#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) +#include + +/* Clock control module registers */ +struct clock_control_regs { + u32 ccmr; + u32 pdr0; + u32 pdr1; + u32 rcsr; + u32 mpctl; + u32 upctl; + u32 spctl; + u32 cosr; + u32 cgr0; + u32 cgr1; + u32 cgr2; + u32 wimr0; + u32 ldc; + u32 dcvr0; + u32 dcvr1; + u32 dcvr2; + u32 dcvr3; + u32 ltr0; + u32 ltr1; + u32 ltr2; + u32 ltr3; + u32 ltbr0; + u32 ltbr1; + u32 pmcr0; + u32 pmcr1; + u32 pdr2; +}; + +/* Bit definitions for RCSR register in CCM */ +#define CCM_RCSR_NF16B (1 << 31) +#define CCM_RCSR_NFMS (1 << 30) + +#endif + #define __REG(x) (*((volatile u32 *)(x))) #define __REG16(x) (*((volatile u16 *)(x))) #define __REG8(x) (*((volatile u8 *)(x))) -- cgit From 38a8b3eafb17d61690e5fc93e6dc45120f79d7d0 Mon Sep 17 00:00:00 2001 From: Magnus Lilja Date: Sun, 17 Jan 2010 17:46:11 +0100 Subject: MX31: Activate NAND environment on i.MX31 PDK board. Signed-off-by: Magnus Lilja --- include/configs/mx31pdk.h | 25 +++++++++++++++++++++---- 1 file changed, 21 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/include/configs/mx31pdk.h b/include/configs/mx31pdk.h index fb61432e7f..bee2f45a15 100644 --- a/include/configs/mx31pdk.h +++ b/include/configs/mx31pdk.h @@ -30,6 +30,8 @@ #ifndef __CONFIG_H #define __CONFIG_H +#include + /* High Level Configuration Options */ #define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */ #define CONFIG_MX31 1 /* in a mx31 */ @@ -51,7 +53,7 @@ /* * Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) +#define CONFIG_SYS_MALLOC_LEN (2*CONFIG_ENV_SIZE + 2 * 128 * 1024) /* Bytes reserved for initial data */ #define CONFIG_SYS_GBL_DATA_SIZE 128 @@ -89,6 +91,7 @@ #define CONFIG_CMD_PING #define CONFIG_CMD_SPI #define CONFIG_CMD_DATE +#define CONFIG_CMD_NAND /* * Disabled due to compilation errors in cmd_bootm.c (IMLS seems to require @@ -104,7 +107,10 @@ "ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \ "bootcmd=run bootcmd_net\0" \ "bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; " \ - "tftpboot 0x81000000 uImage-mx31; bootm\0" + "tftpboot 0x81000000 uImage-mx31; bootm\0" \ + "prg_uboot=tftpboot 0x81000000 u-boot-nand.bin; " \ + "nand erase 0x0 0x40000; " \ + "nand write 0x81000000 0x0 0x40000\0" #define CONFIG_NET_MULTI #define CONFIG_SMC911X 1 @@ -156,9 +162,20 @@ /* No NOR flash present */ #define CONFIG_SYS_NO_FLASH 1 -#define CONFIG_ENV_IS_NOWHERE 1 +#define CONFIG_ENV_IS_IN_NAND 1 +#define CONFIG_ENV_OFFSET 0x40000 +#define CONFIG_ENV_OFFSET_REDUND 0x60000 +#define CONFIG_ENV_SIZE (128 * 1024) -#define CONFIG_ENV_SIZE (128 * 1024) +/* + * NAND driver + */ +#define CONFIG_NAND_MXC +#define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR +#define CONFIG_MXC_NAND_HWECC +#define CONFIG_SYS_NAND_LARGEPAGE /* NAND configuration for the NAND_SPL */ -- cgit