From cd16c57bd0d6c498d5c180d70c6f0f690e9c32de Mon Sep 17 00:00:00 2001 From: Dario Binacchi Date: Mon, 13 Apr 2020 14:36:26 +0200 Subject: dm: test: clk: add the test for the ccf gated clock Unlike the other clock types, in the case of the gated clock, a new driver has been developed which does not use the registering routine provided by the common clock framework. The addition of the ecspi0 clock to sandbox therefore allows testing the ccf gate clock. Signed-off-by: Dario Binacchi Reviewed-by: Simon Glass --- test/dm/clk_ccf.c | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'test') diff --git a/test/dm/clk_ccf.c b/test/dm/clk_ccf.c index 050fa80453..960cb2db0d 100644 --- a/test/dm/clk_ccf.c +++ b/test/dm/clk_ccf.c @@ -39,6 +39,14 @@ static int dm_test_clk_ccf(struct unit_test_state *uts) rate = clk_get_parent_rate(clk); ut_asserteq(rate, 20000000); + /* test the gate of CCF */ + ret = clk_get_by_id(SANDBOX_CLK_ECSPI0, &clk); + ut_assertok(ret); + ut_asserteq_str("ecspi0", clk->dev->name); + + rate = clk_get_parent_rate(clk); + ut_asserteq(rate, 20000000); + /* Test the mux of CCF */ ret = clk_get_by_id(SANDBOX_CLK_USDHC1_SEL, &clk); ut_assertok(ret); -- cgit From 16bdc85b488dd2f9463a71d6aa09bdf5ea9a9978 Mon Sep 17 00:00:00 2001 From: Dario Binacchi Date: Mon, 13 Apr 2020 14:36:27 +0200 Subject: clk: set flags in the ccf registration routines The top-level framework flags are passed as parameter to the common clock framework (ccf) registration routines without being used. Checks of the flags setting added by the patch have been added in the ccf test. Signed-off-by: Dario Binacchi --- test/dm/clk_ccf.c | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'test') diff --git a/test/dm/clk_ccf.c b/test/dm/clk_ccf.c index 960cb2db0d..242d2d756f 100644 --- a/test/dm/clk_ccf.c +++ b/test/dm/clk_ccf.c @@ -30,11 +30,13 @@ static int dm_test_clk_ccf(struct unit_test_state *uts) ret = clk_get_by_id(SANDBOX_CLK_ECSPI_ROOT, &clk); ut_assertok(ret); ut_asserteq_str("ecspi_root", clk->dev->name); + ut_asserteq(CLK_SET_RATE_PARENT, clk->flags); /* Test for clk_get_parent_rate() */ ret = clk_get_by_id(SANDBOX_CLK_ECSPI1, &clk); ut_assertok(ret); ut_asserteq_str("ecspi1", clk->dev->name); + ut_asserteq(CLK_SET_RATE_PARENT, clk->flags); rate = clk_get_parent_rate(clk); ut_asserteq(rate, 20000000); @@ -43,6 +45,7 @@ static int dm_test_clk_ccf(struct unit_test_state *uts) ret = clk_get_by_id(SANDBOX_CLK_ECSPI0, &clk); ut_assertok(ret); ut_asserteq_str("ecspi0", clk->dev->name); + ut_asserteq(CLK_SET_RATE_PARENT, clk->flags); rate = clk_get_parent_rate(clk); ut_asserteq(rate, 20000000); @@ -51,6 +54,7 @@ static int dm_test_clk_ccf(struct unit_test_state *uts) ret = clk_get_by_id(SANDBOX_CLK_USDHC1_SEL, &clk); ut_assertok(ret); ut_asserteq_str("usdhc1_sel", clk->dev->name); + ut_asserteq(CLK_SET_RATE_NO_REPARENT, clk->flags); rate = clk_get_parent_rate(clk); ut_asserteq(rate, 60000000); @@ -58,17 +62,20 @@ static int dm_test_clk_ccf(struct unit_test_state *uts) ret = clk_get_by_id(SANDBOX_CLK_USDHC2_SEL, &clk); ut_assertok(ret); ut_asserteq_str("usdhc2_sel", clk->dev->name); + ut_asserteq(CLK_SET_RATE_NO_REPARENT, clk->flags); rate = clk_get_parent_rate(clk); ut_asserteq(rate, 80000000); pclk = clk_get_parent(clk); ut_asserteq_str("pll3_80m", pclk->dev->name); + ut_asserteq(CLK_SET_RATE_PARENT, pclk->flags); /* Test the composite of CCF */ ret = clk_get_by_id(SANDBOX_CLK_I2C, &clk); ut_assertok(ret); ut_asserteq_str("i2c", clk->dev->name); + ut_asserteq(CLK_SET_RATE_UNGATE, clk->flags); rate = clk_get_rate(clk); ut_asserteq(rate, 60000000); -- cgit From 12d152620d9de9ea966e1136b7f48f641c981bac Mon Sep 17 00:00:00 2001 From: Dario Binacchi Date: Wed, 3 Jun 2020 15:36:25 +0200 Subject: clk: ccf: mux: change the get_rate helper The previous version of the get_rate helper does not work if the mux clock parent is changed after the probe. This error has not been detected because this condition has not been tested. The error occurs because the set_parent helper does not change the parent of the clock device but only the clock selection register. Since changing the parent of a probed device can be tricky, the new version of the get_rate helper provides the rate of the selected clock and not that of the parent. Signed-off-by: Dario Binacchi --- test/dm/clk_ccf.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) (limited to 'test') diff --git a/test/dm/clk_ccf.c b/test/dm/clk_ccf.c index 242d2d756f..32bc4d2b8a 100644 --- a/test/dm/clk_ccf.c +++ b/test/dm/clk_ccf.c @@ -59,6 +59,18 @@ static int dm_test_clk_ccf(struct unit_test_state *uts) rate = clk_get_parent_rate(clk); ut_asserteq(rate, 60000000); + rate = clk_get_rate(clk); + ut_asserteq(rate, 60000000); + + ret = clk_get_by_id(SANDBOX_CLK_PLL3_80M, &pclk); + ut_assertok(ret); + + ret = clk_set_parent(clk, pclk); + ut_assertok(ret); + + rate = clk_get_rate(clk); + ut_asserteq(rate, 80000000); + ret = clk_get_by_id(SANDBOX_CLK_USDHC2_SEL, &clk); ut_assertok(ret); ut_asserteq_str("usdhc2_sel", clk->dev->name); @@ -71,6 +83,18 @@ static int dm_test_clk_ccf(struct unit_test_state *uts) ut_asserteq_str("pll3_80m", pclk->dev->name); ut_asserteq(CLK_SET_RATE_PARENT, pclk->flags); + rate = clk_get_rate(clk); + ut_asserteq(rate, 80000000); + + ret = clk_get_by_id(SANDBOX_CLK_PLL3_60M, &pclk); + ut_assertok(ret); + + ret = clk_set_parent(clk, pclk); + ut_assertok(ret); + + rate = clk_get_rate(clk); + ut_asserteq(rate, 60000000); + /* Test the composite of CCF */ ret = clk_get_by_id(SANDBOX_CLK_I2C, &clk); ut_assertok(ret); -- cgit