/* * Copyright (C) 2016 Google, Inc * Written by Simon Glass <sjg@chromium.org> * * SPDX-License-Identifier: GPL-2.0+ */ #include <config.h> #ifdef CONFIG_ROM_SIZE / { binman { filename = "u-boot.rom"; end-at-4gb; sort-by-pos; pad-byte = <0xff>; size = <CONFIG_ROM_SIZE>; #ifdef CONFIG_HAVE_INTEL_ME intel-descriptor { filename = CONFIG_FLASH_DESCRIPTOR_FILE; }; intel-me { filename = CONFIG_INTEL_ME_FILE; }; #endif #ifdef CONFIG_SPL u-boot-spl-with-ucode-ptr { pos = <CONFIG_SPL_TEXT_BASE>; }; u-boot-dtb-with-ucode2 { type = "u-boot-dtb-with-ucode"; }; u-boot { pos = <0xfff00000>; }; #else u-boot-with-ucode-ptr { pos = <CONFIG_SYS_TEXT_BASE>; }; #endif u-boot-dtb-with-ucode { }; u-boot-ucode { align = <16>; }; #ifdef CONFIG_HAVE_MRC intel-mrc { pos = <CONFIG_X86_MRC_ADDR>; }; #endif #ifdef CONFIG_HAVE_FSP intel-fsp { filename = CONFIG_FSP_FILE; pos = <CONFIG_FSP_ADDR>; }; #endif #ifdef CONFIG_HAVE_CMC intel-cmc { filename = CONFIG_CMC_FILE; pos = <CONFIG_CMC_ADDR>; }; #endif #ifdef CONFIG_HAVE_VGA_BIOS intel-vga { filename = CONFIG_VGA_BIOS_FILE; pos = <CONFIG_VGA_BIOS_ADDR>; }; #endif #ifdef CONFIG_HAVE_VBT intel-vbt { filename = CONFIG_VBT_FILE; pos = <CONFIG_VBT_ADDR>; }; #endif #ifdef CONFIG_HAVE_REFCODE intel-refcode { pos = <CONFIG_X86_REFCODE_ADDR>; }; #endif #ifdef CONFIG_SPL x86-start16-spl { pos = <CONFIG_SYS_X86_START16>; }; #else x86-start16 { pos = <CONFIG_SYS_X86_START16>; }; #endif }; }; #endif