/* * board.c * * Board functions for TI AM335X based boards * * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ * * SPDX-License-Identifier: GPL-2.0+ */ #include #include #include //#include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "board.h" DECLARE_GLOBAL_DATA_PTR; #if defined(CONFIG_SPL_BUILD) static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; #endif #ifndef CONFIG_SKIP_LOWLEVEL_INIT static const struct ddr_data ddr3_data = { .datardsratio0 = MT41K256M16HA125E_RD_DQS, .datawdsratio0 = MT41K256M16HA125E_WR_DQS, .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE, .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA, }; static const struct cmd_control ddr3_cmd_ctrl_data = { .cmd0csratio = MT41K256M16HA125E_RATIO, .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT, .cmd1csratio = MT41K256M16HA125E_RATIO, .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT, .cmd2csratio = MT41K256M16HA125E_RATIO, .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT, }; static struct emif_regs ddr3_emif_reg_data = { .sdram_config = MT41J512M8RH125_EMIF_SDCFG, .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF, .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1, .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2, .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3, .zq_config = MT41K256M16HA125E_ZQ_CFG, .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY, }; #define OSC (V_OSCK/1000000) const struct dpll_params dpll_ddr = { 400, OSC-1, 1, -1, -1, -1, -1}; // 303, OSC-1, 1, -1, -1, -1, -1}; void am33xx_spl_board_init(void) { /* Get the frequency */ dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev); /* Set CORE Frequencies to OPP100 */ do_setup_dpll(&dpll_core_regs, &dpll_core_opp100); /* Set MPU Frequency to what we detected now that voltages are set */ do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100); } const struct dpll_params *get_dpll_ddr_params(void) { return &dpll_ddr; } void set_uart_mux_conf(void) { enable_uart0_pin_mux(); } void set_mux_conf_regs(void) { enable_board_pin_mux(); } const struct ctrl_ioregs ioregs = { .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE, .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, }; void sdram_init(void) { config_ddr(400, &ioregs, &ddr3_data, &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); udelay(500); } #endif /* * Basic board specific setup. Pinmux has been handled already. */ int board_init(void) { #if defined(CONFIG_HW_WATCHDOG) hw_watchdog_init(); #endif gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; #if defined(CONFIG_NAND) gpmc_init(); #endif return 0; } #ifdef CONFIG_BOARD_LATE_INIT int board_late_init(void) { return 0; } #endif int ft_board_setup(void *fdt, struct bd_info *bd) { return 0; } int board_fit_config_name_match(const char *name) { if (!strcmp(name, "olimex,am335x_som")) return 0; return -1; } #if !CONFIG_IS_ENABLED(OF_CONTROL) static const struct omap_hsmmc_plat am335x_mmc0_platdata = { .base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE, .cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_4BIT, .cfg.f_min = 400000, .cfg.f_max = 52000000, .cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195, .cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT, }; U_BOOT_DEVICE(am335x_mmc0) = { .name = "omap_hsmmc", .platdata = &am335x_mmc0_platdata, }; static const struct omap_hsmmc_plat am335x_mmc1_platdata = { .base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE, .cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_8BIT, .cfg.f_min = 400000, .cfg.f_max = 52000000, .cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195, .cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT, }; U_BOOT_DEVICE(am335x_mmc1) = { .name = "omap_hsmmc", .platdata = &am335x_mmc1_platdata, }; #endif