// SPDX-License-Identifier: GPL-2.0+ /* * board/renesas/ebisu/ebisu.c * This file is Ebisu board support. * * Copyright (C) 2018 Marek Vasut */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include DECLARE_GLOBAL_DATA_PTR; void s_init(void) { } int board_early_init_f(void) { return 0; } int board_init(void) { /* adress of boot parameters */ gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000; return 0; } /* * If the firmware passed a device tree use it for U-Boot DRAM setup. */ extern u64 rcar_atf_boot_args[]; int dram_init(void) { const void *atf_fdt_blob = (const void *)(rcar_atf_boot_args[1]); const void *blob; /* Check if ATF passed us DTB. If not, fall back to builtin DTB. */ if (fdt_magic(atf_fdt_blob) == FDT_MAGIC) blob = atf_fdt_blob; else blob = gd->fdt_blob; return fdtdec_setup_mem_size_base_fdt(blob); } int dram_init_banksize(void) { const void *atf_fdt_blob = (const void *)(rcar_atf_boot_args[1]); const void *blob; /* Check if ATF passed us DTB. If not, fall back to builtin DTB. */ if (fdt_magic(atf_fdt_blob) == FDT_MAGIC) blob = atf_fdt_blob; else blob = gd->fdt_blob; fdtdec_setup_memory_banksize_fdt(blob); return 0; } #define RST_BASE 0xE6160000 #define RST_CA57RESCNT (RST_BASE + 0x40) #define RST_CA53RESCNT (RST_BASE + 0x44) #define RST_RSTOUTCR (RST_BASE + 0x58) #define RST_CA57_CODE 0xA5A5000F #define RST_CA53_CODE 0x5A5A000F void reset_cpu(ulong addr) { unsigned long midr, cputype; asm volatile("mrs %0, midr_el1" : "=r" (midr)); cputype = (midr >> 4) & 0xfff; if (cputype == 0xd03) writel(RST_CA53_CODE, RST_CA53RESCNT); else if (cputype == 0xd07) writel(RST_CA57_CODE, RST_CA57RESCNT); else hang(); }