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| author | Michael J. Chudobiak <mjc@avtechpulse.com> | 2016-04-25 10:00:44 -0400 |
|---|---|---|
| committer | Michael J. Chudobiak <mjc@avtechpulse.com> | 2016-04-25 10:00:44 -0400 |
| commit | a1df417e74aa6dae7352dc8cbb0ad471af5b7c69 (patch) | |
| tree | c34b2311e37ea31db153c90cb8f4570374d05e78 /linux/Documentation/ABI/testing/sysfs-driver-tegra-fuse | |
initial Olimex linux tree from Daniel, originally Feb 3, 2016
Diffstat (limited to 'linux/Documentation/ABI/testing/sysfs-driver-tegra-fuse')
| -rw-r--r-- | linux/Documentation/ABI/testing/sysfs-driver-tegra-fuse | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/linux/Documentation/ABI/testing/sysfs-driver-tegra-fuse b/linux/Documentation/ABI/testing/sysfs-driver-tegra-fuse new file mode 100644 index 00000000..69f5af63 --- /dev/null +++ b/linux/Documentation/ABI/testing/sysfs-driver-tegra-fuse @@ -0,0 +1,11 @@ +What: /sys/devices/*/<our-device>/fuse +Date: February 2014 +Contact: Peter De Schrijver <pdeschrijver@nvidia.com> +Description: read-only access to the efuses on Tegra20, Tegra30, Tegra114 + and Tegra124 SoC's from NVIDIA. The efuses contain write once + data programmed at the factory. The data is layed out in 32bit + words in LSB first format. Each bit represents a single value + as decoded from the fuse registers. Bits order/assignment + exactly matches the HW registers, including any unused bits. +Users: any user space application which wants to read the efuses on + Tegra SoC's |