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&am33xx_pinmux {
avtech_pins: pinmux_avtech_pins {
pinctrl-single,pins = <
0x7c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* csn */
0x94 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* oen */
0x98 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* wen */
0x00 (INPUT_EN | MUX_MODE0) /* d0 */
0x04 (INPUT_EN | MUX_MODE0) /* d1 */
0x08 (INPUT_EN | MUX_MODE0) /* d2 */
0x0c (INPUT_EN | MUX_MODE0) /* d3 */
0x10 (INPUT_EN | MUX_MODE0) /* d4 */
0x14 (INPUT_EN | MUX_MODE0) /* d5 */
0x18 (INPUT_EN | MUX_MODE0) /* d6 */
0x1c (INPUT_EN | MUX_MODE0) /* d7 */
0xa0 (PIN_OUTPUT_PULLUP | MUX_MODE1) /* a0 */
0xa4 (PIN_OUTPUT_PULLUP | MUX_MODE1) /* a1 */
0xa8 (PIN_OUTPUT_PULLUP | MUX_MODE1) /* a2 */
0xac (PIN_OUTPUT_PULLUP | MUX_MODE1) /* a3 */
0xb0 (PIN_OUTPUT_PULLUP | MUX_MODE1) /* a4 */
0xb4 (PIN_OUTPUT_PULLUP | MUX_MODE1) /* a5 */
0xb8 (PIN_OUTPUT_PULLUP | MUX_MODE1) /* a6 */
0xbc (PIN_OUTPUT_PULLUP | MUX_MODE1) /* a7 */
0x20 (PIN_OUTPUT | MUX_MODE7) /* Chain_Input gpio0_22*/
0x24 (PIN_OUTPUT | MUX_MODE7) /* Shift_Clock gpio0_23*/
0x28 (PIN_OUTPUT | MUX_MODE7) /* Load_Clock gpio0_26*/
0x3c (PIN_OUTPUT | MUX_MODE7) /* O.GATE gpio1_15 */
0x38 (PIN_OUTPUT | MUX_MODE7) /* OUT_RELAY gpio1_14*/
0x2c (PIN_OUTPUT | MUX_MODE7) /* PW_ENABLE gpio0_27*/
0x30 (PIN_INPUT | MUX_MODE7) /* POWER_FAIL gpio1_12*/
0x8c (PIN_OUTPUT | MUX_MODE7) /* RST_GPIB gpio2_1*/
>;
};
uart5full_pins: pinmux_uart5full_pins {
pinctrl-single,pins = <
0xc0 (PIN_OUTPUT | MUX_MODE4) /* txd */
0xc4 (PIN_INPUT_PULLUP | MUX_MODE4) /* rxd */
0xd8 (PIN_INPUT_PULLUP | MUX_MODE6) /* ctsn */
0xdc (PIN_OUTPUT | MUX_MODE6) /* rtsn */
>;
};
};
/ {
avtech {
compatible = "bone-pinmux-helper";
pinctrl-names = "default";
pinctrl-0 = <&avtech_pins>;
status = "okay";
};
};
&uart5 {
pinctrl-names = "default";
pinctrl-0 = <&uart5full_pins>;
status = "okay";
};
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