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authorPeng Fan <Peng.Fan@freescale.com>2015-01-04 17:07:14 +0800
committerJagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>2015-01-07 12:25:05 +0530
commita2358783875580fc7ad5e1554cb1a74a79360df6 (patch)
tree203679c0851ef260de4c1c0fe9f5a905b6ea4fe1 /.mailmap
parent653cda8f6605676504d03eb76f84932a20a6feb1 (diff)
spi:fsl-quadspi support bank register read write
To support bigger than 16MB size qspi flashes, spi framework uses bank switch to access higher bank or lower bank. In this patch, QSPI_CMD_BRRD, QSPI_CMD_BRWR, QSPI_CMD_WREAR, QSPI_CMD_RDEAR is initialized in LUT register with related pad and length configuration. qspi_op_pp is originally for page programming, this patch reuses this function for bank register switch and renamed it with qspi_op_write. Since bank or EAR register is only 1 byte length, however original qspi_op_pp or now renamed qspi_op_write only support 4 bytes lenght as the access unit, this will trigger data abort exception when access EAR or bank register. This is because upper framework passes a 1 bytes pointer to qspi_op_write, however qspi_op_write treat it as an int pointer. This patch fixes this for accessing EAR or bank register. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
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