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author | Jagan Teki <jagan@amarulasolutions.com> | 2019-07-15 23:51:04 +0530 |
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committer | Kever Yang <kever.yang@rock-chips.com> | 2019-07-19 11:11:09 +0800 |
commit | 9c4d517db8d15e56fe2316c0763bdc8009cac872 (patch) | |
tree | 430211fffba83c858370622973d220a12502b2ce /.travis.yml | |
parent | 30bd86a399a0d6af2307ee2eb035ac93ff571b93 (diff) |
ram: rk3399: Order tsel variables
Order tsel* variable declarations and assignment in proper
and meaningful way.
No functionality change.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Diffstat (limited to '.travis.yml')
0 files changed, 0 insertions, 0 deletions