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authorNeil Armstrong <narmstrong@baylibre.com>2018-08-06 14:49:20 +0200
committerTom Rini <trini@konsulko.com>2018-09-10 20:48:17 -0400
commitc8e570167f8a2eadbd5f3c7a2b38a9e3796cea19 (patch)
tree9062d050420c614bce2c23d6797b60c0143d2d29 /.travis.yml
parent8d5579ceff2403d78a7fed1e06c5f003b3bca12a (diff)
clk: clk_meson: Add mux and div support for reparent and rate setting
This patch adds support for : - Rate calculation through muxes and generic dividers - Basic gate setting propagation - Reparenting for muxes - Clock rate setting through generic dividers without reparenting Support is only added to the Composite VPU and VAPB clocks in order to support the Video Processing Unit Power Domain clock setup. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
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