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| author | Sanchayan Maity <maitysanchayan@gmail.com> | 2015-04-15 16:24:26 +0530 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2015-04-23 14:56:09 -0400 |
| commit | e7b860fa4dd4de736d887deca19ca540abea4239 (patch) | |
| tree | e87e02cde7cef75a7b4091c2995decb61d0fc96d /.travis.yml | |
| parent | 7a90a1f260908eb13b3948da0315a729795db1ab (diff) | |
ARM: vf610: Initial integration for Colibri VF50/VF61
This adds initial support for Colibri VF50/VF61 based on Freescale
Vybrid SoC.
- CPU clocked at 396/500 MHz
- DDR3 at 396MHz
- for VF50, use PLL2 as memory clock (synchronous mode)
- for VF61, use PLL1 as memory clock (asynchronous mode)
- Console on UART0 (Colibri UART_A)
- Ethernet on FEC1
- PLL5 based RMII clocking (E.g. No external crystal)
- UART_A and UART_C I/O muxing
- Boot from NAND by default
Tested on Colibri VF50/VF61 booting using serial loader over UART.
Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
Acked-by: Stefan Agner <stefan@agner.ch>
Diffstat (limited to '.travis.yml')
0 files changed, 0 insertions, 0 deletions