diff options
| author | Fabio Estevam <festevam@gmail.com> | 2018-09-04 10:23:11 -0300 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2018-09-14 15:04:24 +0200 |
| commit | 000829fdb8999a4085e45799e7dee73f27c7d3f0 (patch) | |
| tree | 62c3c8e0a1b03da7f2dc3ee7dca29b9bf9e175e0 | |
| parent | 558a37ce852077d01f56688af4d55ac5fa76a981 (diff) | |
pico-imx6ul: Add support for the 512MB module
Currently only the module with 256MB of RAM is supported.
Add support for the 512MB of RAM variant as well.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Fabio Berton <fabio.berton@ossystems.com.br>
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
| -rw-r--r-- | board/technexion/pico-imx6ul/spl.c | 27 |
1 files changed, 24 insertions, 3 deletions
diff --git a/board/technexion/pico-imx6ul/spl.c b/board/technexion/pico-imx6ul/spl.c index 78c731fe7c..1819722024 100644 --- a/board/technexion/pico-imx6ul/spl.c +++ b/board/technexion/pico-imx6ul/spl.c @@ -70,7 +70,6 @@ static struct mx6_ddr3_cfg mem_ddr = { .density = 2, .width = 16, .banks = 8, - .rowaddr = 14, .coladdr = 10, .pagesz = 2, .trcd = 1350, @@ -91,12 +90,34 @@ static void ccgr_init(void) writel(0xFFFFFFFF, &ccm->CCGR6); } -static void spl_dram_init(void) +static void imx6ul_spl_dram_cfg_size(u32 ram_size) { + if (ram_size == SZ_256M) + mem_ddr.rowaddr = 14; + else + mem_ddr.rowaddr = 15; + mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs); mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr); } +static void imx6ul_spl_dram_cfg(void) +{ + ulong ram_size_test, ram_size = 0; + + for (ram_size = SZ_512M; ram_size >= SZ_256M; ram_size >>= 1) { + imx6ul_spl_dram_cfg_size(ram_size); + ram_size_test = get_ram_size((long int *)PHYS_SDRAM, ram_size); + if (ram_size_test == ram_size) + break; + } + + if (ram_size < SZ_256M) { + puts("ERROR: DRAM size detection failed\n"); + hang(); + } +} + void board_init_f(ulong dummy) { ccgr_init(); @@ -104,7 +125,7 @@ void board_init_f(ulong dummy) board_early_init_f(); timer_init(); preloader_console_init(); - spl_dram_init(); + imx6ul_spl_dram_cfg(); memset(__bss_start, 0, __bss_end - __bss_start); board_init_r(NULL, 0); } |