ARM: uniphier: add ProXstream2 and PH1-LD6b support

The DDR SDRAM initialization code has not been mainlined yet, but
U-Boot proper should work.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

32 files changed, 733 insertions, 1 deletions

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 0a7d18431d..5f10243fe6 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -47,7 +47,9 @@ dtb-$(CONFIG_ARCH_UNIPHIER) += \
 	uniphier-ph1-pro4-ref.dtb \
 	uniphier-ph1-pro5-4kbox.dtb \
 	uniphier-ph1-sld3-ref.dtb \
-	uniphier-ph1-sld8-ref.dtb
+	uniphier-ph1-sld8-ref.dtb \
+	uniphier-proxstream2-gentil.dtb \
+	uniphier-proxstream2-vodka.dtb
 dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \
 	zynq-zc706.dtb \
 	zynq-zed.dtb \
diff --git a/arch/arm/dts/uniphier-ph1-ld6b-ref.dts b/arch/arm/dts/uniphier-ph1-ld6b-ref.dts
index ca68930527..bd86f09326 100644
--- a/arch/arm/dts/uniphier-ph1-ld6b-ref.dts
+++ b/arch/arm/dts/uniphier-ph1-ld6b-ref.dts
@@ -3,6 +3,7 @@
  *
  * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
  *
+ * SPDX-License-Identifier:	GPL-2.0+
  */
 
 /dts-v1/;
diff --git a/arch/arm/dts/uniphier-proxstream2-gentil.dts b/arch/arm/dts/uniphier-proxstream2-gentil.dts
new file mode 100644
index 0000000000..81d2385bf9
--- /dev/null
+++ b/arch/arm/dts/uniphier-proxstream2-gentil.dts
@@ -0,0 +1,62 @@
+/*
+ * Device Tree Source for UniPhier ProXstream2 Gentil Board
+ *
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/dts-v1/;
+/include/ "uniphier-proxstream2.dtsi"
+
+/ {
+	model = "UniPhier ProXstream2 Gentil Board";
+	compatible = "socionext,proxstream2-gentil", "socionext,proxstream2";
+
+	memory {
+		device_type = "memory";
+		reg = <0x80000000 0x80000000>;
+	};
+
+	chosen {
+		bootargs = "console=ttyS2,115200";
+		stdout-path = &serial2;
+	};
+
+	aliases {
+		serial0 = &serial0;
+		serial1 = &serial1;
+		serial2 = &serial2;
+		i2c0 = &i2c0;
+		i2c4 = &i2c4;
+		i2c5 = &i2c5;
+		i2c6 = &i2c6;
+	};
+};
+
+&serial2 {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+};
+
+/* for U-boot only */
+/ {
+	soc {
+		u-boot,dm-pre-reloc;
+	};
+};
+
+&serial2 {
+	u-boot,dm-pre-reloc;
+};
+
+&pinctrl {
+	u-boot,dm-pre-reloc;
+};
+
+&pinctrl_uart2 {
+	u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/uniphier-proxstream2-vodka.dts b/arch/arm/dts/uniphier-proxstream2-vodka.dts
new file mode 100644
index 0000000000..fba7b742ca
--- /dev/null
+++ b/arch/arm/dts/uniphier-proxstream2-vodka.dts
@@ -0,0 +1,62 @@
+/*
+ * Device Tree Source for UniPhier ProXstream2 Vodka Board
+ *
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/dts-v1/;
+/include/ "uniphier-proxstream2.dtsi"
+
+/ {
+	model = "UniPhier ProXstream2 Vodka Board";
+	compatible = "socionext,proxstream2-vodka", "socionext,proxstream2";
+
+	memory {
+		device_type = "memory";
+		reg = <0x80000000 0x80000000>;
+	};
+
+	chosen {
+		bootargs = "console=ttyS2,115200";
+		stdout-path = &serial2;
+	};
+
+	aliases {
+		serial0 = &serial0;
+		serial1 = &serial1;
+		serial2 = &serial2;
+		i2c0 = &i2c0;
+		i2c4 = &i2c4;
+		i2c5 = &i2c5;
+		i2c6 = &i2c6;
+	};
+};
+
+&serial2 {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+};
+
+/* for U-boot only */
+/ {
+	soc {
+		u-boot,dm-pre-reloc;
+	};
+};
+
+&serial2 {
+	u-boot,dm-pre-reloc;
+};
+
+&pinctrl {
+	u-boot,dm-pre-reloc;
+};
+
+&pinctrl_uart2 {
+	u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/mach-uniphier/Kconfig b/arch/arm/mach-uniphier/Kconfig
index 7a62957de3..22ab798b96 100644
--- a/arch/arm/mach-uniphier/Kconfig
+++ b/arch/arm/mach-uniphier/Kconfig
@@ -42,6 +42,24 @@ config ARCH_UNIPHIER_PH1_PRO5
 	help
 	  This enables support for UniPhier PH1-Pro5 SoC.
 
+config ARCH_UNIPHIER_PROXSTREAM2
+	bool "UniPhier ProXstream2 SoC"
+	select UNIPHIER_SMP
+	depends on !ARCH_UNIPHIER_PH1_SLD3 && \
+		   !ARCH_UNIPHIER_PH1_LD4 && \
+		   !ARCH_UNIPHIER_PH1_SLD8
+	help
+	  This enables support for UniPhier ProXstream2 SoC.
+
+config ARCH_UNIPHIER_PH1_LD6B
+	bool "UniPhier PH1-LD6b SoC"
+	select UNIPHIER_SMP
+	depends on !ARCH_UNIPHIER_PH1_SLD3 && \
+		   !ARCH_UNIPHIER_PH1_LD4 && \
+		   !ARCH_UNIPHIER_PH1_SLD8
+	help
+	  This enables support for UniPhier PH1-LD6b SoC.
+
 config MICRO_SUPPORT_CARD
 	bool "Use Micro Support Card"
 	help
diff --git a/arch/arm/mach-uniphier/board_early_init_f.c b/arch/arm/mach-uniphier/board_early_init_f.c
index fb4927222c..5e0d246ce4 100644
--- a/arch/arm/mach-uniphier/board_early_init_f.c
+++ b/arch/arm/mach-uniphier/board_early_init_f.c
@@ -48,6 +48,20 @@ int board_early_init_f(void)
 		ph1_pro5_clk_init();
 		break;
 #endif
+#if defined(CONFIG_ARCH_UNIPHIER_PROXSTREAM2)
+	case SOC_UNIPHIER_PROXSTREAM2:
+		proxstream2_pin_init();
+		led_puts("U1");
+		proxstream2_clk_init();
+		break;
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD6B)
+	case SOC_UNIPHIER_PH1_LD6B:
+		ph1_ld6b_pin_init();
+		led_puts("U1");
+		proxstream2_clk_init();
+		break;
+#endif
 	default:
 		break;
 	}
diff --git a/arch/arm/mach-uniphier/boards.c b/arch/arm/mach-uniphier/boards.c
index fba8859712..812c58ff96 100644
--- a/arch/arm/mach-uniphier/boards.c
+++ b/arch/arm/mach-uniphier/boards.c
@@ -71,6 +71,22 @@ static const struct uniphier_board_data ph1_pro5_data = {
 };
 #endif
 
+#if defined(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) || \
+	defined(CONFIG_ARCH_UNIPHIER_PH1_LD6B)
+static const struct uniphier_board_data proxstream2_data = {
+	.dram_ch0_base  = 0x80000000,
+	.dram_ch0_size  = 0x40000000,
+	.dram_ch0_width = 32,
+	.dram_ch1_base  = 0xc0000000,
+	.dram_ch1_size  = 0x20000000,
+	.dram_ch1_width = 32,
+	.dram_ch2_base  = 0xe0000000,
+	.dram_ch2_size  = 0x20000000,
+	.dram_ch2_width = 16,
+	.dram_freq      = 1866,
+};
+#endif
+
 struct uniphier_board_id {
 	const char *compatible;
 	const struct uniphier_board_data *param;
@@ -92,6 +108,12 @@ static const struct uniphier_board_id uniphier_boards[] = {
 #if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO5)
 	{ "socionext,ph1-pro5", &ph1_pro5_data, },
 #endif
+#if defined(CONFIG_ARCH_UNIPHIER_PROXSTREAM2)
+	{ "socionext,proxstream2", &proxstream2_data, },
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD6B)
+	{ "socionext,ph1-ld6b", &proxstream2_data, },
+#endif
 };
 
 const struct uniphier_board_data *uniphier_get_board_param(const void *fdt)
diff --git a/arch/arm/mach-uniphier/boot-mode/Makefile b/arch/arm/mach-uniphier/boot-mode/Makefile
index 1d2f8b3946..30c8874905 100644
--- a/arch/arm/mach-uniphier/boot-mode/Makefile
+++ b/arch/arm/mach-uniphier/boot-mode/Makefile
@@ -5,3 +5,5 @@ obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4)	+= boot-mode-ph1-ld4.o
 obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4)	+= boot-mode-ph1-ld4.o
 obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8)	+= boot-mode-ph1-ld4.o
 obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO5)	+= boot-mode-ph1-pro5.o
+obj-$(CONFIG_ARCH_UNIPHIER_PROXSTREAM2)	+= boot-mode-proxstream2.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD6B)	+= boot-mode-proxstream2.o
diff --git a/arch/arm/mach-uniphier/boot-mode/boot-mode-proxstream2.c b/arch/arm/mach-uniphier/boot-mode/boot-mode-proxstream2.c
new file mode 100644
index 0000000000..10a47c6fcc
--- /dev/null
+++ b/arch/arm/mach-uniphier/boot-mode/boot-mode-proxstream2.c
@@ -0,0 +1,75 @@
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <linux/io.h>
+#include <mach/boot-device.h>
+#include <mach/init.h>
+#include <mach/sbc-regs.h>
+#include <mach/sg-regs.h>
+
+static struct boot_device_info boot_device_table[] = {
+	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC  8, EraseSize 128KB, Addr 4)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC  8, EraseSize 128KB, Addr 5)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 5)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC  8, EraseSize 256KB, Addr 5)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 256KB, Addr 5)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC  8, EraseSize 512KB, Addr 5)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 512KB, Addr 5)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 4)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC  8, EraseSize 128KB, Addr 5)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 5)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC  8, EraseSize 256KB, Addr 5)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 256KB, Addr 5)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC  8, EraseSize 512KB, Addr 5)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 512KB, Addr 5)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC  8, EraseSize 128KB, Addr 4)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 4)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC  8, ONFI,            Addr 4)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC  8, ONFI,            Addr 5)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI,            Addr 5)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI,            Addr 4)"},
+	{BOOT_DEVICE_MMC1, "eMMC Boot (1.8V)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC  8, ONFI,            Addr 5)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI,            Addr 5)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC  8, ONFI,            Addr 4)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI,            Addr 4)"},
+	{BOOT_DEVICE_SPI,  "SPI 3Byte CS0"},
+	{BOOT_DEVICE_SPI,  "SPI 4Byte CS0"},
+	{BOOT_DEVICE_SPI,  "SPI 3Byte CS1"},
+	{BOOT_DEVICE_SPI,  "SPI 4Byte CS1"},
+	{BOOT_DEVICE_SPI,  "SPI 4Byte CS0"},
+	{BOOT_DEVICE_SPI,  "SPI 3Byte CS0"},
+	{BOOT_DEVICE_NONE, "Reserved"},
+};
+
+int get_boot_mode_sel(void)
+{
+	return (readl(SG_PINMON0) >> 1) & 0x1f;
+}
+
+u32 proxstream2_boot_device(void)
+{
+	int boot_mode;
+
+	boot_mode = get_boot_mode_sel();
+
+	return boot_device_table[boot_mode].type;
+}
+
+void proxstream2_boot_mode_show(void)
+{
+	int mode_sel, i;
+
+	mode_sel = get_boot_mode_sel();
+
+	puts("Boot Mode Pin:\n");
+
+	for (i = 0; i < ARRAY_SIZE(boot_device_table); i++)
+		printf(" %c %02x %s\n", i == mode_sel ? '*' : ' ', i,
+		       boot_device_table[i].info);
+}
diff --git a/arch/arm/mach-uniphier/boot-mode/boot-mode.c b/arch/arm/mach-uniphier/boot-mode/boot-mode.c
index 60329eb10a..c6cafa7919 100644
--- a/arch/arm/mach-uniphier/boot-mode/boot-mode.c
+++ b/arch/arm/mach-uniphier/boot-mode/boot-mode.c
@@ -33,6 +33,12 @@ u32 spl_boot_device(void)
 	case SOC_UNIPHIER_PH1_PRO5:
 		return ph1_pro5_boot_device();
 #endif
+#if defined(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) || \
+	defined(CONFIG_ARCH_UNIPHIER_PH1_LD6B)
+	case SOC_UNIPHIER_PROXSTREAM2:
+	case SOC_UNIPHIER_PH1_LD6B:
+		return proxstream2_boot_device();
+#endif
 	default:
 		return BOOT_DEVICE_NONE;
 	}
diff --git a/arch/arm/mach-uniphier/clk/Makefile b/arch/arm/mach-uniphier/clk/Makefile
index 873c4f7207..4f397b986b 100644
--- a/arch/arm/mach-uniphier/clk/Makefile
+++ b/arch/arm/mach-uniphier/clk/Makefile
@@ -3,3 +3,5 @@ obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4)	+= clk-ph1-ld4.o
 obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4)	+= clk-ph1-pro4.o
 obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8)	+= clk-ph1-ld4.o
 obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO5)	+= clk-ph1-pro5.o
+obj-$(CONFIG_ARCH_UNIPHIER_PROXSTREAM2)	+= clk-proxstream2.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD6B)	+= clk-proxstream2.o
diff --git a/arch/arm/mach-uniphier/clk/clk-proxstream2.c b/arch/arm/mach-uniphier/clk/clk-proxstream2.c
new file mode 100644
index 0000000000..b494021ecf
--- /dev/null
+++ b/arch/arm/mach-uniphier/clk/clk-proxstream2.c
@@ -0,0 +1,50 @@
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <linux/io.h>
+#include <mach/init.h>
+#include <mach/sc-regs.h>
+
+void proxstream2_clk_init(void)
+{
+	u32 tmp;
+
+	/* deassert reset */
+	tmp = readl(SC_RSTCTRL);
+#ifdef CONFIG_USB_XHCI_UNIPHIER
+	tmp |= SC_RSTCTRL_NRST_USB3B0 | SC_RSTCTRL_NRST_GIO;
+#endif
+#ifdef CONFIG_UNIPHIER_ETH
+	tmp |= SC_RSTCTRL_NRST_ETHER;
+#endif
+#ifdef CONFIG_NAND_DENALI
+	tmp |= SC_RSTCTRL_NRST_NAND;
+#endif
+	writel(tmp, SC_RSTCTRL);
+	readl(SC_RSTCTRL); /* dummy read */
+
+#ifdef CONFIG_USB_XHCI_UNIPHIER
+	tmp = readl(SC_RSTCTRL2);
+	tmp |= SC_RSTCTRL2_NRST_USB3B1;
+	writel(tmp, SC_RSTCTRL2);
+	readl(SC_RSTCTRL2); /* dummy read */
+#endif
+
+	/* privide clocks */
+	tmp = readl(SC_CLKCTRL);
+#ifdef CONFIG_USB_XHCI_UNIPHIER
+	tmp |= SC_CLKCTRL_CEN_USB31 | SC_CLKCTRL_CEN_USB30 |
+		SC_CLKCTRL_CEN_GIO;
+#endif
+#ifdef CONFIG_UNIPHIER_ETH
+	tmp |= SC_CLKCTRL_CEN_ETHER;
+#endif
+#ifdef CONFIG_NAND_DENALI
+	tmp |= SC_CLKCTRL_CEN_NAND;
+#endif
+	writel(tmp, SC_CLKCTRL);
+	readl(SC_CLKCTRL); /* dummy read */
+}
diff --git a/arch/arm/mach-uniphier/cmd_pinmon.c b/arch/arm/mach-uniphier/cmd_pinmon.c
index 58c53bf193..b15ee9dd60 100644
--- a/arch/arm/mach-uniphier/cmd_pinmon.c
+++ b/arch/arm/mach-uniphier/cmd_pinmon.c
@@ -33,6 +33,13 @@ static int do_pinmon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 		ph1_pro5_boot_mode_show();
 		break;
 #endif
+#if defined(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) || \
+	defined(CONFIG_ARCH_UNIPHIER_PH1_LD6B)
+	case SOC_UNIPHIER_PROXSTREAM2:
+	case SOC_UNIPHIER_PH1_LD6B:
+		proxstream2_boot_mode_show();
+		break;
+#endif
 	default:
 		break;
 	}
diff --git a/arch/arm/mach-uniphier/debug_ll.S b/arch/arm/mach-uniphier/debug_ll.S
index 056f77ed55..d8c9fe43e3 100644
--- a/arch/arm/mach-uniphier/debug_ll.S
+++ b/arch/arm/mach-uniphier/debug_ll.S
@@ -125,6 +125,55 @@ ph1_sld8_end:
 	b		init_uart
 ph1_pro5_end:
 #endif
+#if defined(CONFIG_ARCH_UNIPHIER_PROXSTREAM2)
+#define PROXSTREAM2_UART_CLK		88900000
+	cmp		r1, #0x2E
+	bne		proxstream2_end
+
+	ldr		r0, =SG_IECTRL
+	ldr		r1, [r0]
+	orr		r1, r1, #1
+	str		r1, [r0]
+
+	sg_set_pinsel	217, 8, 8, 4, r0, r1	@ TXD0 -> TXD0
+	sg_set_pinsel	115, 8, 8, 4, r0, r1	@ TXD1 -> TXD1
+	sg_set_pinsel	113, 8, 8, 4, r0, r1	@ TXD2 -> TXD2
+	sg_set_pinsel	219, 8, 8, 4, r0, r1	@ TXD3 -> TXD3
+
+	ldr		r0, =SC_CLKCTRL
+	ldr		r1, [r0]
+	orr		r1, r1, #SC_CLKCTRL_CEN_PERI
+	str		r1, [r0]
+
+	ldr		r3, =DIV_ROUND(PROXSTREAM2_UART_CLK, 16 * BAUDRATE)
+
+	b		init_uart
+proxstream2_end:
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD6B)
+#define PH1_LD6B_UART_CLK		88900000
+	cmp		r1, #0x2F
+	bne		ph1_ld6b_end
+
+	ldr		r0, =SG_IECTRL
+	ldr		r1, [r0]
+	orr		r1, r1, #1
+	str		r1, [r0]
+
+	sg_set_pinsel	135, 3, 8, 4, r0, r1	@ PORT10 -> TXD0
+	sg_set_pinsel	115, 0, 8, 4, r0, r1	@ TXD1 -> TXD1
+	sg_set_pinsel	113, 2, 8, 4, r0, r1	@ SBO0 -> TXD2
+
+	ldr		r0, =SC_CLKCTRL
+	ldr		r1, [r0]
+	orr		r1, r1, #SC_CLKCTRL_CEN_PERI
+	str		r1, [r0]
+
+	ldr		r3, =DIV_ROUND(PH1_LD6B_UART_CLK, 16 * BAUDRATE)
+
+	b		init_uart
+ph1_ld6b_end:
+#endif
 
 init_uart:
 	addruart	r0, r1, r2
diff --git a/arch/arm/mach-uniphier/early-clk/Makefile b/arch/arm/mach-uniphier/early-clk/Makefile
index 939795c26d..393ea96f90 100644
--- a/arch/arm/mach-uniphier/early-clk/Makefile
+++ b/arch/arm/mach-uniphier/early-clk/Makefile
@@ -3,3 +3,5 @@ obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4)	+= early-clk-ph1-ld4.o
 obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4)	+= early-clk-ph1-ld4.o
 obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8)	+= early-clk-ph1-ld4.o
 obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO5)	+= early-clk-ph1-pro5.o
+obj-$(CONFIG_ARCH_UNIPHIER_PROXSTREAM2)	+= early-clk-proxstream2.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD6B)	+= early-clk-proxstream2.o
diff --git a/arch/arm/mach-uniphier/early-clk/early-clk-proxstream2.c b/arch/arm/mach-uniphier/early-clk/early-clk-proxstream2.c
new file mode 100644
index 0000000000..c303f16a57
--- /dev/null
+++ b/arch/arm/mach-uniphier/early-clk/early-clk-proxstream2.c
@@ -0,0 +1,44 @@
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <linux/io.h>
+#include <mach/init.h>
+#include <mach/sc-regs.h>
+
+int proxstream2_early_clk_init(const struct uniphier_board_data *bd)
+{
+	u32 tmp;
+
+	/* deassert reset */
+	if (spl_boot_device() != BOOT_DEVICE_NAND) {
+		tmp = readl(SC_RSTCTRL);
+		tmp &= ~SC_RSTCTRL_NRST_NAND;
+		writel(tmp, SC_RSTCTRL);
+	};
+
+	tmp = readl(SC_RSTCTRL4);
+	tmp |= SC_RSTCTRL4_NRST_UMCSB | SC_RSTCTRL4_NRST_UMCA2 |
+	       SC_RSTCTRL4_NRST_UMCA1 | SC_RSTCTRL4_NRST_UMCA0 |
+	       SC_RSTCTRL4_NRST_UMC32 | SC_RSTCTRL4_NRST_UMC31 |
+	       SC_RSTCTRL4_NRST_UMC30;
+	writel(tmp, SC_RSTCTRL4);
+	readl(SC_RSTCTRL4); /* dummy read */
+
+	/* privide clocks */
+	tmp = readl(SC_CLKCTRL);
+	tmp |= SC_CLKCTRL_CEN_SBC | SC_CLKCTRL_CEN_PERI;
+	writel(tmp, SC_CLKCTRL);
+
+	tmp = readl(SC_CLKCTRL4);
+	tmp |= SC_CLKCTRL4_CEN_UMCSB | SC_CLKCTRL4_CEN_UMC2 |
+	       SC_CLKCTRL4_CEN_UMC1 | SC_CLKCTRL4_CEN_UMC0;
+	writel(tmp, SC_CLKCTRL4);
+	readl(SC_CLKCTRL4); /* dummy read */
+
+	return 0;
+}
diff --git a/arch/arm/mach-uniphier/include/mach/boot-device.h b/arch/arm/mach-uniphier/include/mach/boot-device.h
index 3cbe7737a2..2ab5a535fa 100644
--- a/arch/arm/mach-uniphier/include/mach/boot-device.h
+++ b/arch/arm/mach-uniphier/include/mach/boot-device.h
@@ -15,9 +15,11 @@ struct boot_device_info {
 u32 ph1_sld3_boot_device(void);
 u32 ph1_ld4_boot_device(void);
 u32 ph1_pro5_boot_device(void);
+u32 proxstream2_boot_device(void);
 
 void ph1_sld3_boot_mode_show(void);
 void ph1_ld4_boot_mode_show(void);
 void ph1_pro5_boot_mode_show(void);
+void proxstream2_boot_mode_show(void);
 
 #endif /* _ASM_BOOT_DEVICE_H_ */
diff --git a/arch/arm/mach-uniphier/include/mach/init.h b/arch/arm/mach-uniphier/include/mach/init.h
index 914182d1e8..5108eddfc4 100644
--- a/arch/arm/mach-uniphier/include/mach/init.h
+++ b/arch/arm/mach-uniphier/include/mach/init.h
@@ -27,11 +27,13 @@ int ph1_ld4_init(const struct uniphier_board_data *bd);
 int ph1_pro4_init(const struct uniphier_board_data *bd);
 int ph1_sld8_init(const struct uniphier_board_data *bd);
 int ph1_pro5_init(const struct uniphier_board_data *bd);
+int proxstream2_init(const struct uniphier_board_data *bd);
 
 #if defined(CONFIG_MICRO_SUPPORT_CARD)
 int ph1_sld3_sbc_init(const struct uniphier_board_data *bd);
 int ph1_ld4_sbc_init(const struct uniphier_board_data *bd);
 int ph1_pro4_sbc_init(const struct uniphier_board_data *bd);
+int proxstream2_sbc_init(const struct uniphier_board_data *bd);
 #else
 static inline int ph1_sld3_sbc_init(const struct uniphier_board_data *bd)
 {
@@ -47,6 +49,11 @@ static inline int ph1_pro4_sbc_init(const struct uniphier_board_data *bd)
 {
 	return 0;
 }
+
+static inline int proxstream2_sbc_init(const struct uniphier_board_data *bd)
+{
+	return 0;
+}
 #endif
 
 int ph1_sld3_bcu_init(const struct uniphier_board_data *bd);
@@ -54,6 +61,7 @@ int ph1_ld4_bcu_init(const struct uniphier_board_data *bd);
 
 int memconf_init(const struct uniphier_board_data *bd);
 int ph1_sld3_memconf_init(const struct uniphier_board_data *bd);
+int proxstream2_memconf_init(const struct uniphier_board_data *bd);
 
 int ph1_sld3_pll_init(const struct uniphier_board_data *bd);
 int ph1_ld4_pll_init(const struct uniphier_board_data *bd);
@@ -65,6 +73,7 @@ int ph1_ld4_enable_dpll_ssc(const struct uniphier_board_data *bd);
 
 int ph1_ld4_early_clk_init(const struct uniphier_board_data *bd);
 int ph1_pro5_early_clk_init(const struct uniphier_board_data *bd);
+int proxstream2_early_clk_init(const struct uniphier_board_data *bd);
 
 int ph1_sld3_early_pin_init(const struct uniphier_board_data *bd);
 
@@ -77,10 +86,13 @@ void ph1_ld4_pin_init(void);
 void ph1_pro4_pin_init(void);
 void ph1_sld8_pin_init(void);
 void ph1_pro5_pin_init(void);
+void proxstream2_pin_init(void);
+void ph1_ld6b_pin_init(void);
 
 void ph1_ld4_clk_init(void);
 void ph1_pro4_clk_init(void);
 void ph1_pro5_clk_init(void);
+void proxstream2_clk_init(void);
 
 #define pr_err(fmt, args...)	printf(fmt, ##args)
 
diff --git a/arch/arm/mach-uniphier/include/mach/sc-regs.h b/arch/arm/mach-uniphier/include/mach/sc-regs.h
index 903e405091..474b82d243 100644
--- a/arch/arm/mach-uniphier/include/mach/sc-regs.h
+++ b/arch/arm/mach-uniphier/include/mach/sc-regs.h
@@ -64,6 +64,7 @@
 #define SC_RSTCTRL4_NRST_UMCA2		(0x1 << 10)	/* UMC ch2 standby */
 #define SC_RSTCTRL4_NRST_UMCA1		(0x1 <<  9)	/* UMC ch1 standby */
 #define SC_RSTCTRL4_NRST_UMCA0		(0x1 <<  8)	/* UMC ch0 standby */
+#define SC_RSTCTRL4_NRST_UMC32		(0x1 <<  6)	/* UMC ch2 */
 #define SC_RSTCTRL4_NRST_UMC31		(0x1 <<  5)	/* UMC ch1 */
 #define SC_RSTCTRL4_NRST_UMC30		(0x1 <<  4)	/* UMC ch0 */
 
@@ -83,6 +84,7 @@
 /* Pro5 or newer */
 #define SC_CLKCTRL4			(SC_BASE_ADDR | 0x210c)
 #define SC_CLKCTRL4_CEN_UMCSB		(0x1 << 12)	/* UMC system bus */
+#define SC_CLKCTRL4_CEN_UMC2		(0x1 <<  2)	/* UMC ch2 */
 #define SC_CLKCTRL4_CEN_UMC1		(0x1 <<  1)	/* UMC ch1 */
 #define SC_CLKCTRL4_CEN_UMC0		(0x1 <<  0)	/* UMC ch0 */
 
diff --git a/arch/arm/mach-uniphier/include/mach/sg-regs.h b/arch/arm/mach-uniphier/include/mach/sg-regs.h
index 168b35e723..678d437fc9 100644
--- a/arch/arm/mach-uniphier/include/mach/sg-regs.h
+++ b/arch/arm/mach-uniphier/include/mach/sg-regs.h
@@ -53,6 +53,8 @@
 #define SG_MEMCONF_CH2_NUM_MASK		(0x1 << 24)
 #define SG_MEMCONF_CH2_NUM_1		(0x1 << 24)
 #define SG_MEMCONF_CH2_NUM_2		(0x0 << 24)
+/* PH1-LD6b, ProXstream2 only */
+#define SG_MEMCONF_CH2_DISABLE		(0x1 << 21)
 
 #define SG_MEMCONF_SPARSEMEM		(0x1 << 4)
 
diff --git a/arch/arm/mach-uniphier/init/Makefile b/arch/arm/mach-uniphier/init/Makefile
index 1524a8d053..98833b55de 100644
--- a/arch/arm/mach-uniphier/init/Makefile
+++ b/arch/arm/mach-uniphier/init/Makefile
@@ -5,3 +5,5 @@ obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4)	+= init-ph1-ld4.o
 obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4)	+= init-ph1-pro4.o
 obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8)	+= init-ph1-sld8.o
 obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO5)	+= init-ph1-pro5.o
+obj-$(CONFIG_ARCH_UNIPHIER_PROXSTREAM2)	+= init-proxstream2.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD6B)	+= init-proxstream2.o
diff --git a/arch/arm/mach-uniphier/init/init-proxstream2.c b/arch/arm/mach-uniphier/init/init-proxstream2.c
new file mode 100644
index 0000000000..8d03b8f86a
--- /dev/null
+++ b/arch/arm/mach-uniphier/init/init-proxstream2.c
@@ -0,0 +1,41 @@
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <linux/compiler.h>
+#include <mach/init.h>
+#include <mach/micro-support-card.h>
+
+int proxstream2_init(const struct uniphier_board_data *bd)
+{
+	proxstream2_sbc_init(bd);
+
+	support_card_reset();
+
+	support_card_init();
+
+	led_puts("L0");
+
+	memconf_init(bd);
+	proxstream2_memconf_init(bd);
+
+	led_puts("L1");
+
+	proxstream2_early_clk_init(bd);
+
+	led_puts("L2");
+
+	led_puts("L3");
+
+#ifdef CONFIG_SPL_SERIAL_SUPPORT
+	preloader_console_init();
+#endif
+
+	led_puts("L4");
+
+	return 0;
+}
diff --git a/arch/arm/mach-uniphier/init/init.c b/arch/arm/mach-uniphier/init/init.c
index 2649e6c417..bbfc8e5e08 100644
--- a/arch/arm/mach-uniphier/init/init.c
+++ b/arch/arm/mach-uniphier/init/init.c
@@ -45,6 +45,13 @@ void spl_board_init(void)
 		ph1_pro5_init(param);
 		break;
 #endif
+#if defined(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) || \
+	defined(CONFIG_ARCH_UNIPHIER_PH1_LD6B)
+	case SOC_UNIPHIER_PROXSTREAM2:
+	case SOC_UNIPHIER_PH1_LD6B:
+		proxstream2_init(param);
+		break;
+#endif
 	default:
 		break;
 	}
diff --git a/arch/arm/mach-uniphier/memconf/Makefile b/arch/arm/mach-uniphier/memconf/Makefile
index 1a718f31fa..42057a2077 100644
--- a/arch/arm/mach-uniphier/memconf/Makefile
+++ b/arch/arm/mach-uniphier/memconf/Makefile
@@ -1,2 +1,4 @@
 obj-y					+= memconf.o
 obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3)	+= memconf-ph1-sld3.o
+obj-$(CONFIG_ARCH_UNIPHIER_PROXSTREAM2)	+= memconf-proxstream2.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD6B)	+= memconf-proxstream2.o
diff --git a/arch/arm/mach-uniphier/memconf/memconf-proxstream2.c b/arch/arm/mach-uniphier/memconf/memconf-proxstream2.c
new file mode 100644
index 0000000000..d7bf0d4e5f
--- /dev/null
+++ b/arch/arm/mach-uniphier/memconf/memconf-proxstream2.c
@@ -0,0 +1,64 @@
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/sizes.h>
+#include <mach/init.h>
+#include <mach/sg-regs.h>
+
+int proxstream2_memconf_init(const struct uniphier_board_data *bd)
+{
+	u32 tmp;
+	unsigned long size_per_word;
+
+	tmp = readl(SG_MEMCONF);
+
+	tmp &= ~(SG_MEMCONF_CH2_SZ_MASK | SG_MEMCONF_CH2_NUM_MASK);
+
+	switch (bd->dram_ch2_width) {
+	case 16:
+		tmp |= SG_MEMCONF_CH2_NUM_1;
+		size_per_word = bd->dram_ch2_size;
+		break;
+	case 32:
+		tmp |= SG_MEMCONF_CH2_NUM_2;
+		size_per_word = bd->dram_ch2_size >> 1;
+		break;
+	default:
+		pr_err("error: unsupported DRAM Ch2 width\n");
+		return -EINVAL;
+	}
+
+	/* Set DDR size */
+	switch (size_per_word) {
+	case SZ_64M:
+		tmp |= SG_MEMCONF_CH2_SZ_64M;
+		break;
+	case SZ_128M:
+		tmp |= SG_MEMCONF_CH2_SZ_128M;
+		break;
+	case SZ_256M:
+		tmp |= SG_MEMCONF_CH2_SZ_256M;
+		break;
+	case SZ_512M:
+		tmp |= SG_MEMCONF_CH2_SZ_512M;
+		break;
+	default:
+		pr_err("error: unsupported DRAM Ch2 size\n");
+		return -EINVAL;
+	}
+
+	if (size_per_word)
+		tmp &= ~SG_MEMCONF_CH2_DISABLE;
+	else
+		tmp |= SG_MEMCONF_CH2_DISABLE;
+
+	writel(tmp, SG_MEMCONF);
+
+	return 0;
+}
diff --git a/arch/arm/mach-uniphier/pinctrl/Makefile b/arch/arm/mach-uniphier/pinctrl/Makefile
index a7852457f1..85175955d3 100644
--- a/arch/arm/mach-uniphier/pinctrl/Makefile
+++ b/arch/arm/mach-uniphier/pinctrl/Makefile
@@ -3,3 +3,5 @@ obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4)	+= pinctrl-ph1-ld4.o
 obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4)	+= pinctrl-ph1-pro4.o
 obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8)	+= pinctrl-ph1-sld8.o
 obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO5)	+= pinctrl-ph1-pro5.o
+obj-$(CONFIG_ARCH_UNIPHIER_PROXSTREAM2)	+= pinctrl-proxstream2.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD6B)	+= pinctrl-ph1-ld6b.o
diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-ld6b.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-ld6b.c
new file mode 100644
index 0000000000..4f950d3fc6
--- /dev/null
+++ b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-ld6b.c
@@ -0,0 +1,45 @@
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <linux/io.h>
+#include <mach/init.h>
+#include <mach/sg-regs.h>
+
+void ph1_ld6b_pin_init(void)
+{
+	/* Comment format:    PAD Name -> Function Name */
+
+#ifdef CONFIG_NAND_DENALI
+	sg_set_pinsel(30, 0, 8, 4);	/* XNFRE  -> XNFRE */
+	sg_set_pinsel(31, 0, 8, 4);	/* XNFWE  -> XNFWE */
+	sg_set_pinsel(32, 0, 8, 4);	/* NFALE  -> NFALE */
+	sg_set_pinsel(33, 0, 8, 4);	/* NFCLE  -> NFCLE */
+	sg_set_pinsel(34, 0, 8, 4);	/* XNFWP  -> XNFWP */
+	sg_set_pinsel(35, 0, 8, 4);	/* XNFCE0 -> XNFCE0 */
+	sg_set_pinsel(36, 0, 8, 4);	/* NRYBY0 -> NRYBY0 */
+	sg_set_pinsel(37, 0, 8, 4);	/* XNFCE1 -> NRYBY1 */
+	sg_set_pinsel(38, 0, 8, 4);	/* NRYBY1 -> XNFCE1 */
+	sg_set_pinsel(39, 0, 8, 4);	/* NFD0   -> NFD0 */
+	sg_set_pinsel(40, 0, 8, 4);	/* NFD1   -> NFD1 */
+	sg_set_pinsel(41, 0, 8, 4);	/* NFD2   -> NFD2 */
+	sg_set_pinsel(42, 0, 8, 4);	/* NFD3   -> NFD3 */
+	sg_set_pinsel(43, 0, 8, 4);	/* NFD4   -> NFD4 */
+	sg_set_pinsel(44, 0, 8, 4);	/* NFD5   -> NFD5 */
+	sg_set_pinsel(45, 0, 8, 4);	/* NFD6   -> NFD6 */
+	sg_set_pinsel(46, 0, 8, 4);	/* NFD7   -> NFD7 */
+#endif
+
+#ifdef CONFIG_USB_XHCI_UNIPHIER
+	sg_set_pinsel(56, 0, 8, 4);	/* USB0VBUS -> USB0VBUS */
+	sg_set_pinsel(57, 0, 8, 4);	/* USB0OD   -> USB0OD */
+	sg_set_pinsel(58, 0, 8, 4);	/* USB1VBUS -> USB1VBUS */
+	sg_set_pinsel(59, 0, 8, 4);	/* USB1OD   -> USB1OD */
+	sg_set_pinsel(60, 0, 8, 4);	/* USB2VBUS -> USB2VBUS */
+	sg_set_pinsel(61, 0, 8, 4);	/* USB2OD   -> USB2OD */
+	sg_set_pinsel(62, 0, 8, 4);	/* USB3VBUS -> USB3VBUS */
+	sg_set_pinsel(63, 0, 8, 4);	/* USB3OD   -> USB3OD */
+#endif
+}
diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-proxstream2.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-proxstream2.c
new file mode 100644
index 0000000000..96abd0235c
--- /dev/null
+++ b/arch/arm/mach-uniphier/pinctrl/pinctrl-proxstream2.c
@@ -0,0 +1,45 @@
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <linux/io.h>
+#include <mach/init.h>
+#include <mach/sg-regs.h>
+
+void proxstream2_pin_init(void)
+{
+	/* Comment format:    PAD Name -> Function Name */
+
+#ifdef CONFIG_NAND_DENALI
+	sg_set_pinsel(30, 8, 8, 4);	/* XNFRE  -> XNFRE */
+	sg_set_pinsel(31, 8, 8, 4);	/* XNFWE  -> XNFWE */
+	sg_set_pinsel(32, 8, 8, 4);	/* NFALE  -> NFALE */
+	sg_set_pinsel(33, 8, 8, 4);	/* NFCLE  -> NFCLE */
+	sg_set_pinsel(34, 8, 8, 4);	/* XNFWP  -> XNFWP */
+	sg_set_pinsel(35, 8, 8, 4);	/* XNFCE0 -> XNFCE0 */
+	sg_set_pinsel(36, 8, 8, 4);	/* NRYBY0 -> NRYBY0 */
+	sg_set_pinsel(37, 8, 8, 4);	/* XNFCE1 -> NRYBY1 */
+	sg_set_pinsel(38, 8, 8, 4);	/* NRYBY1 -> XNFCE1 */
+	sg_set_pinsel(39, 8, 8, 4);	/* NFD0   -> NFD0 */
+	sg_set_pinsel(40, 8, 8, 4);	/* NFD1   -> NFD1 */
+	sg_set_pinsel(41, 8, 8, 4);	/* NFD2   -> NFD2 */
+	sg_set_pinsel(42, 8, 8, 4);	/* NFD3   -> NFD3 */
+	sg_set_pinsel(43, 8, 8, 4);	/* NFD4   -> NFD4 */
+	sg_set_pinsel(44, 8, 8, 4);	/* NFD5   -> NFD5 */
+	sg_set_pinsel(45, 8, 8, 4);	/* NFD6   -> NFD6 */
+	sg_set_pinsel(46, 8, 8, 4);	/* NFD7   -> NFD7 */
+#endif
+
+#ifdef CONFIG_USB_XHCI_UNIPHIER
+	sg_set_pinsel(56, 8, 8, 4);	/* USB0VBUS -> USB0VBUS */
+	sg_set_pinsel(57, 8, 8, 4);	/* USB0OD   -> USB0OD */
+	sg_set_pinsel(58, 8, 8, 4);	/* USB1VBUS -> USB1VBUS */
+	sg_set_pinsel(59, 8, 8, 4);	/* USB1OD   -> USB1OD */
+	sg_set_pinsel(60, 8, 8, 4);	/* USB2VBUS -> USB2VBUS */
+	sg_set_pinsel(61, 8, 8, 4);	/* USB2OD   -> USB2OD */
+	sg_set_pinsel(62, 8, 8, 4);	/* USB3VBUS -> USB3VBUS */
+	sg_set_pinsel(63, 8, 8, 4);	/* USB3OD   -> USB3OD */
+#endif
+}
diff --git a/arch/arm/mach-uniphier/sbc/Makefile b/arch/arm/mach-uniphier/sbc/Makefile
index 2c5fd1a1fc..db622d2034 100644
--- a/arch/arm/mach-uniphier/sbc/Makefile
+++ b/arch/arm/mach-uniphier/sbc/Makefile
@@ -3,3 +3,5 @@ obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4)	+= sbc-ph1-ld4.o
 obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4)	+= sbc-ph1-pro4.o
 obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8)	+= sbc-ph1-ld4.o
 obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO5)	+= sbc-ph1-pro4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PROXSTREAM2)	+= sbc-proxstream2.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD6B)	+= sbc-proxstream2.o
diff --git a/arch/arm/mach-uniphier/sbc/sbc-proxstream2.c b/arch/arm/mach-uniphier/sbc/sbc-proxstream2.c
new file mode 100644
index 0000000000..9c3aeb7cd0
--- /dev/null
+++ b/arch/arm/mach-uniphier/sbc/sbc-proxstream2.c
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <linux/io.h>
+#include <mach/init.h>
+#include <mach/sbc-regs.h>
+#include <mach/sg-regs.h>
+
+int proxstream2_sbc_init(const struct uniphier_board_data *bd)
+{
+	/* necessary for ROM boot ?? */
+	/* system bus output enable */
+	writel(0x17, PC0CTRL);
+
+	/*
+	 * Only CS1 is connected to support card.
+	 * BKSZ[1:0] should be set to "01".
+	 */
+	writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL10);
+	writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL11);
+	writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL12);
+	writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL14);
+
+	if (boot_is_swapped()) {
+		/*
+		 * Boot Swap On: boot from external NOR/SRAM
+		 * 0x42000000-0x43ffffff is a mirror of 0x40000000-0x41ffffff.
+		 *
+		 * 0x40000000-0x41efffff, 0x42000000-0x43efffff: memory bank
+		 * 0x41f00000-0x41ffffff, 0x43f00000-0x43ffffff: peripherals
+		 */
+		writel(0x0000bc01, SBBASE0);
+	} else {
+		/*
+		 * Boot Swap Off: boot from mask ROM
+		 * 0x40000000-0x41ffffff: mask ROM
+		 * 0x42000000-0x43efffff: memory bank (31MB)
+		 * 0x43f00000-0x43ffffff: peripherals (1MB)
+		 */
+		writel(0x0000be01, SBBASE0); /* dummy */
+		writel(0x0200be01, SBBASE1);
+	}
+
+	return 0;
+}
diff --git a/configs/ph1_ld6b_defconfig b/configs/ph1_ld6b_defconfig
new file mode 100644
index 0000000000..68f6ba847b
--- /dev/null
+++ b/configs/ph1_ld6b_defconfig
@@ -0,0 +1,30 @@
+CONFIG_ARM=y
+CONFIG_ARCH_UNIPHIER=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ARCH_UNIPHIER_PH1_LD6B=y
+CONFIG_MICRO_SUPPORT_CARD=y
+CONFIG_SYS_TEXT_BASE=0x84000000
+CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-ld6b-ref"
+CONFIG_HUSH_PARSER=y
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+CONFIG_CMD_NAND=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
+# CONFIG_CMD_MISC is not set
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_SIMPLE_BUS=y
+CONFIG_NAND_DENALI=y
+CONFIG_SYS_NAND_DENALI_64BIT=y
+CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
+CONFIG_SPL_NAND_DENALI=y
+CONFIG_UNIPHIER_SERIAL=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_STORAGE=y
diff --git a/doc/README.uniphier b/doc/README.uniphier
index 6792327992..6ba0320f4f 100644
--- a/doc/README.uniphier
+++ b/doc/README.uniphier
@@ -48,6 +48,14 @@ PH1-Pro5:
     $ make ph1_pro5_defconfig
     $ make CROSS_COMPILE=arm-linux-gnueabi-
 
+ProXstream2:
+    $ make pxs2_defconfig
+    $ make CROSS_COMPILE=arm-linux-gnueabi-
+
+PH1-LD6b:
+    $ make ph1_ld6b_defconfig
+    $ make CROSS_COMPILE=arm-linux-gnueabi-
+
 You may wish to change the "CROSS_COMPILE=arm-linux-gnueabi-"
 to use your favorite compiler.