ARM: imx: Support larger SPL size on IMX6DQ

Previously the SPL size on all iMX6 platforms was restricted to 68KB
because the OCRAM size on iMX6SL/DL parts is only 128KB. However, the
other iMX6 variants have 256KB of OCRAM. Add an option
CONFIG_MX6_OCRAM_256KB which allows using the full size on boards which
don't need to support the SL/DL variants. This allows for an SPL size of
196KB, which makes it much easier to use configurations such as SPL with
driver model and FDT control.

Signed-off-by: Robert Hancock <hancock@sedsystems.ca>
Tested-by: Adam Ford <aford173@gmail.com> #imx6q_logic

3 files changed, 37 insertions, 3 deletions

diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
index 43d681113d..36e1c98fb5 100644
--- a/arch/arm/mach-imx/mx6/Kconfig
+++ b/arch/arm/mach-imx/mx6/Kconfig
@@ -87,6 +87,15 @@ config MX6ULL
 	select SYSCOUNTER_TIMER
 	select SYS_L2CACHE_OFF
 
+config MX6_OCRAM_256KB
+	bool "Support 256KB OCRAM"
+	depends on MX6D || MX6Q
+	help
+	 Allows using the full 256KB size of the OCRAM on the MX6Q/MX6D series
+	 of chips, such as for SPL. The OCRAM of the Lite series of chips is
+	 only 128KB, so using this option will prevent the resulting code from
+	 working on those chips.
+
 config MX6_DDRCAL
 	bool "Include dynamic DDR calibration routines"
 	depends on SPL
diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index f467eca2be..2ca219995d 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -28,7 +28,8 @@ config SPL_FRAMEWORK
 config SPL_SIZE_LIMIT
 	int "Maximum size of SPL image"
 	depends on SPL
-	default 69632 if ARCH_MX6
+	default 69632 if ARCH_MX6 && !MX6_OCRAM_256KB
+	default 200704 if ARCH_MX6 && MX6_OCRAM_256KB
 	default 0
 	help
 	  Specifies the maximum length of the U-Boot SPL image.
diff --git a/include/configs/imx6_spl.h b/include/configs/imx6_spl.h
index 212dee7f28..a223930240 100644
--- a/include/configs/imx6_spl.h
+++ b/include/configs/imx6_spl.h
@@ -7,10 +7,32 @@
 #define __IMX6_SPL_CONFIG_H
 
 #ifdef CONFIG_SPL
+
+#ifdef CONFIG_MX6_OCRAM_256KB
 /*
- * see Figure 8-3 in IMX6DQ/IMX6SDL Reference manuals:
+ * see Figure 8.4.1 in IMX6DQ Reference manuals:
+ *  - IMX6DQ OCRAM (IRAM) is from 0x00907000 to 0x0093FFFF
+ *  - BOOT ROM stack is at 0x0093FFB8
+ *  - if icache/dcache is enabled (eFuse/strapping controlled) then the
+ *    IMX BOOT ROM will setup MMU table at 0x00938000, therefore we need to
+ *    fit between 0x00907000 and 0x00938000.
+ *  - Additionally the BOOT ROM loads what they consider the firmware image
+ *    which consists of a 4K header in front of us that contains the IVT, DCD
+ *    and some padding thus 'our' max size is really 0x00908000 - 0x00938000
+ *    or 192KB
+ */
+#define CONFIG_SPL_MAX_SIZE		0x30000
+#define CONFIG_SPL_STACK		0x0093FFB8
+/*
+ * Pad SPL to 196KB (4KB header + 192KB max size). This allows to write the
+ * SPL/U-Boot combination generated with u-boot-with-spl.imx directly to a
+ * boot media (given that boot media specific offset is configured properly).
+ */
+#define CONFIG_SPL_PAD_TO		0x31000
+#else
+/*
+ * see Figure 8-3 in IMX6SDL Reference manuals:
  *  - IMX6SDL OCRAM (IRAM) is from 0x00907000 to 0x0091FFFF
- *  - IMX6DQ has 2x IRAM of IMX6SDL but we intend to support IMX6SDL as well
  *  - BOOT ROM stack is at 0x0091FFB8
  *  - if icache/dcache is enabled (eFuse/strapping controlled) then the
  *    IMX BOOT ROM will setup MMU table at 0x00918000, therefore we need to
@@ -29,6 +51,8 @@
  */
 #define CONFIG_SPL_PAD_TO		0x11000
 
+#endif
+
 /* MMC support */
 #if defined(CONFIG_SPL_MMC_SUPPORT)
 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1