diff options
| author | Dinh Nguyen <dinguyen@opensource.altera.com> | 2015-03-30 17:01:05 -0500 |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2015-04-21 12:23:16 +0200 |
| commit | 0812a1d3e5d056b012d6a9b4b2e83469440f7018 (patch) | |
| tree | 45d4979a52bb5f62d9e95d0d178df967090b78ab | |
| parent | c218f85ea18d57beecc36a3460f08e929d81fcd6 (diff) | |
arm: socfpga: spl: enable sdram, timer and uart
Add the calls in the spl_board_init to enable SDRAM, timer, and UART.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: Marek Vasut <marex@denx.de>
| -rw-r--r-- | arch/arm/cpu/armv7/socfpga/spl.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/socfpga/spl.c b/arch/arm/cpu/armv7/socfpga/spl.c index 6a8c15d91f..a4dbe4ffe6 100644 --- a/arch/arm/cpu/armv7/socfpga/spl.c +++ b/arch/arm/cpu/armv7/socfpga/spl.c @@ -144,6 +144,10 @@ void spl_board_init(void) /* freeze all IO banks */ sys_mgr_frzctrl_freeze_req(); + socfpga_sdram_enable(); + socfpga_uart0_enable(); + socfpga_osc1timer_enable(); + debug("Reconfigure Clock Manager\n"); /* reconfigure the PLLs */ cm_basic_init(&cm_default_cfg); |