diff options
| author | wdenk <wdenk> | 2003-09-02 23:08:13 +0000 |
|---|---|---|
| committer | wdenk <wdenk> | 2003-09-02 23:08:13 +0000 |
| commit | 093ae273da8db4d2fc1a0471f7f4fd4d712e2884 (patch) | |
| tree | 24069688a9aa2eca053abd0261cc2028ceea6de4 | |
| parent | 12f34241cb9679c27a1ab3561766562f5a515eff (diff) | |
Fix compile problem
| -rw-r--r-- | cpu/ppc4xx/miiphy.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/cpu/ppc4xx/miiphy.c b/cpu/ppc4xx/miiphy.c index e719a330f6..9f0a47f1b2 100644 --- a/cpu/ppc4xx/miiphy.c +++ b/cpu/ppc4xx/miiphy.c @@ -101,7 +101,9 @@ int miiphy_read (unsigned char addr, unsigned char reg, sta_reg = reg; /* reg address */ /* set clock (50Mhz) and read flags */ sta_reg = (sta_reg | EMAC_STACR_READ) & ~EMAC_STACR_CLK_100MHZ; +#ifdef CONFIG_PHY_CLK_FREQ sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ; +#endif sta_reg = sta_reg | (addr << 5); /* Phy address */ out32 (EMAC_STACR, sta_reg); @@ -157,7 +159,9 @@ int miiphy_write (unsigned char addr, unsigned char reg, sta_reg = reg; /* reg address */ /* set clock (50Mhz) and read flags */ sta_reg = (sta_reg | EMAC_STACR_WRITE) & ~EMAC_STACR_CLK_100MHZ; +#ifdef CONFIG_PHY_CLK_FREQ sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ; /* Set clock frequency (PLB freq. dependend) */ +#endif sta_reg = sta_reg | ((unsigned long) addr << 5); /* Phy address */ memcpy (&sta_reg, &value, 2); /* put in data */ |