* Patch by Christian Hohnstaedt, 23 Apr 2004:

  JFFS2 speed enhancements:
  - repair header CRC calculation in jffs2_1pass.c
  - add eraseblock size to the partition information to skip empty
    eraseblocks if we find more then 4k of free space.
  - The JFFS2 scanner is now fast enough to remove the spinning wheel
    so #ifdef-ed out.
  - add watchdog calls in long running loops

* Patch by Philippe Robin, 22 Apr 2004:
  Fix ethernet configuration for "versatile" board

* Patch by Kshitij Gupta, 21 Apr 2004:
  Remove busy loop and use MPU timer fr usleep() on OMAP1510/1610 boards

* Patch by Steven Scholz, 24 Feb 2004:
  Fix a bug in AT91RM9200 ethernet driver:
  The MII interface is now initialized before accessing the PHY.

* Cleanup PCI ID's

9 files changed, 239 insertions, 153 deletions

diff --git a/CHANGELOG b/CHANGELOG
index fdfb21291e..e1f8e834cd 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,6 +2,25 @@
 Changes for U-Boot 1.1.1:
 ======================================================================
 
+* Patch by Christian Hohnstaedt, 23 Apr 2004:
+  JFFS2 speed enhancements:
+  - repair header CRC calculation in jffs2_1pass.c
+  - add eraseblock size to the partition information to skip empty
+    eraseblocks if we find more then 4k of free space.
+  - The JFFS2 scanner is now fast enough to remove the spinning wheel
+    so #ifdef-ed out.
+  - add watchdog calls in long running loops
+
+* Patch by Philippe Robin, 22 Apr 2004:
+  Fix ethernet configuration for "versatile" board 
+
+* Patch by Kshitij Gupta, 21 Apr 2004:
+  Remove busy loop and use MPU timer fr usleep() on OMAP1510/1610 boards
+
+* Patch by Steven Scholz, 24 Feb 2004:
+  Fix a bug in AT91RM9200 ethernet driver:
+  The MII interface is now initialized before accessing the PHY.
+
 * Patch by John Kerl, 19 Apr 2004:
   Use U-boot's miiphy.h for PHY register names, rather than
   introducing a new header file.
diff --git a/common/cmd_jffs2.c b/common/cmd_jffs2.c
index 3cf00b8e29..11e3cc663e 100644
--- a/common/cmd_jffs2.c
+++ b/common/cmd_jffs2.c
@@ -80,8 +80,14 @@ jffs2_part_info(int part_num)
 			flash_info[CFG_JFFS2_FIRST_BANK].start[0];
 #endif
 
-		/* unused in current jffs2 loader */
-		part.erasesize = 0;
+		/* FIXME: Fast hack to get erase size set */
+
+		/* We assume that our JFFS2 partition has
+		 * all erase blocks with the same size
+		 * If we have a clue about the erasesize
+		 * we can skip empty blocks
+		 */
+		part.erasesize = PHYS_FLASH_SECT_SIZE;
 
 		/* Mark the struct as ready */
 		part.usr_priv=(void*)1;
diff --git a/cpu/arm925t/interrupts.c b/cpu/arm925t/interrupts.c
index d77c4e6f67..d3c94768c0 100644
--- a/cpu/arm925t/interrupts.c
+++ b/cpu/arm925t/interrupts.c
@@ -215,16 +215,9 @@ void set_timer (ulong t)
 	timestamp = t;
 }
 
-/* delay x useconds AND perserve advance timstamp value */
+/* delay x useconds AND preserve advance timestamp value */
 void udelay (unsigned long usec)
 {
-#ifdef CONFIG_INNOVATOROMAP1510
-#define LOOPS_PER_MSEC 60		/* tuned on omap1510 */
-	volatile int i, time_remaining = LOOPS_PER_MSEC * usec;
-
-	for (i = time_remaining; i > 0; i--) {
-	}
-#else
 	ulong tmo, tmp;
 
 	if(usec >= 1000){		/* if "big" number, spread normalization to seconds */
@@ -242,9 +235,8 @@ void udelay (unsigned long usec)
 	else
 		tmo += tmp;		/* else, set advancing stamp wake up time */
 
-	while (get_timer_masked () < tmo)/* loop till event */
+	while (get_timer_masked () < tmo) /* loop till event */
 		/*NOP*/;
-#endif
 }
 
 void reset_timer_masked (void)
diff --git a/cpu/at91rm9200/at91rm9200_ether.c b/cpu/at91rm9200/at91rm9200_ether.c
index 3428a9e10f..544b3175b8 100644
--- a/cpu/at91rm9200/at91rm9200_ether.c
+++ b/cpu/at91rm9200/at91rm9200_ether.c
@@ -378,14 +378,21 @@ int eth_init (bd_t * bd)
 
 	p_mac = AT91C_BASE_EMAC;
 
-	*AT91C_PIOA_PDR = AT91C_PA16_EMDIO | AT91C_PA15_EMDC | AT91C_PA14_ERXER | AT91C_PA13_ERX1 | AT91C_PA12_ERX0 | AT91C_PA11_ECRS_ECRSDV | AT91C_PA10_ETX1 | AT91C_PA9_ETX0 | AT91C_PA8_ETXEN | AT91C_PA7_ETXCK_EREFCK;	/* PIO Disable Register */
+	/* PIO Disable Register */
+	*AT91C_PIOA_PDR = AT91C_PA16_EMDIO | AT91C_PA15_EMDC | AT91C_PA14_ERXER |
+			  AT91C_PA13_ERX1 | AT91C_PA12_ERX0 | AT91C_PA11_ECRS_ECRSDV |
+			  AT91C_PA10_ETX1 | AT91C_PA9_ETX0 | AT91C_PA8_ETXEN |
+			  AT91C_PA7_ETXCK_EREFCK;
 
 	*AT91C_PIOB_PDR = AT91C_PB25_EF100 |
-			AT91C_PB19_ERXCK | AT91C_PB18_ECOL | AT91C_PB17_ERXDV |
-			AT91C_PB16_ERX3 | AT91C_PB15_ERX2 | AT91C_PB14_ETXER |
-			AT91C_PB13_ETX3 | AT91C_PB12_ETX2;
+			  AT91C_PB19_ERXCK | AT91C_PB18_ECOL | AT91C_PB17_ERXDV |
+			  AT91C_PB16_ERX3 | AT91C_PB15_ERX2 | AT91C_PB14_ETXER |
+			  AT91C_PB13_ETX3 | AT91C_PB12_ETX2;
 
-	*AT91C_PIOB_BSR = AT91C_PB25_EF100 | AT91C_PB19_ERXCK | AT91C_PB18_ECOL | AT91C_PB17_ERXDV | AT91C_PB16_ERX3 | AT91C_PB15_ERX2 | AT91C_PB14_ETXER | AT91C_PB13_ETX3 | AT91C_PB12_ETX2;	/* Select B Register */
+	/* Select B Register */
+	*AT91C_PIOB_BSR = AT91C_PB25_EF100 | AT91C_PB19_ERXCK | AT91C_PB18_ECOL |
+			  AT91C_PB17_ERXDV | AT91C_PB16_ERX3 | AT91C_PB15_ERX2 |
+			  AT91C_PB14_ETXER | AT91C_PB13_ETX3 | AT91C_PB12_ETX2;
 
 	*AT91C_PMC_PCER = 1 << AT91C_ID_EMAC;	/* Peripheral Clock Enable Register */
 
@@ -400,6 +407,22 @@ int eth_init (bd_t * bd)
 	rbfdt[RBF_FRAMEMAX - 1].addr |= RBF_WRAP;
 	rbfp = &rbfdt[0];
 
+	p_mac->EMAC_SA2L = (bd->bi_enetaddr[3] << 24) | (bd->bi_enetaddr[2] << 16)
+			 | (bd->bi_enetaddr[1] <<  8) | (bd->bi_enetaddr[0]);
+	p_mac->EMAC_SA2H = (bd->bi_enetaddr[5] <<  8) | (bd->bi_enetaddr[4]);
+
+	p_mac->EMAC_RBQP = (long) (&rbfdt[0]);
+	p_mac->EMAC_RSR &= ~(AT91C_EMAC_RSR_OVR | AT91C_EMAC_REC | AT91C_EMAC_BNA);
+
+	p_mac->EMAC_CFG = (p_mac->EMAC_CFG | AT91C_EMAC_CAF | AT91C_EMAC_NBC)
+			& ~AT91C_EMAC_CLK;
+
+#ifdef CONFIG_AT91C_USE_RMII
+	p_mac->EMAC_CFG |= AT91C_EMAC_RMII;
+#endif
+
+	p_mac->EMAC_CTL |= AT91C_EMAC_TE | AT91C_EMAC_RE;
+
 	at91rm92000_GetPhyInterface ();
 
 	if (!pPhyOps->IsPhyConnected (p_mac))
@@ -416,22 +439,6 @@ int eth_init (bd_t * bd)
 		return 0;
 	}
 
-	p_mac->EMAC_SA2L = (bd->bi_enetaddr[3] << 24) | (bd->bi_enetaddr[2] << 16)
-			 | (bd->bi_enetaddr[1] << 8) | (bd->bi_enetaddr[0]);
-	p_mac->EMAC_SA2H = (bd->bi_enetaddr[5] << 8) | (bd->bi_enetaddr[4]);
-
-	p_mac->EMAC_RBQP = (long) (&rbfdt[0]);
-	p_mac->EMAC_RSR &= ~(AT91C_EMAC_RSR_OVR | AT91C_EMAC_REC | AT91C_EMAC_BNA);
-
-	p_mac->EMAC_CFG = (p_mac->EMAC_CFG | AT91C_EMAC_CAF | AT91C_EMAC_NBC)
-			& ~AT91C_EMAC_CLK;
-
-#ifdef CONFIG_AT91C_USE_RMII
-	p_mac->EMAC_CFG |= AT91C_EMAC_RMII;
-#endif
-
-	p_mac->EMAC_CTL |= AT91C_EMAC_TE | AT91C_EMAC_RE;
-
 	return 0;
 }
 
diff --git a/drivers/ns8382x.c b/drivers/ns8382x.c
index 154d6cacef..281940b222 100644
--- a/drivers/ns8382x.c
+++ b/drivers/ns8382x.c
@@ -266,7 +266,7 @@ static int ns8382x_poll(struct eth_device *dev);
 static void ns8382x_disable(struct eth_device *dev);
 
 static struct pci_device_id supported[] = {
-	{PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_8382x},
+	{PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_83820},
 	{}
 };
 
diff --git a/drivers/sk98lin/skge.c b/drivers/sk98lin/skge.c
index ff7e2af779..61a6094230 100644
--- a/drivers/sk98lin/skge.c
+++ b/drivers/sk98lin/skge.c
@@ -494,7 +494,7 @@ static struct proc_dir_entry	*pSkRootDir;
 static struct pci_device_id supported[] = {
 	{PCI_VENDOR_ID_3COM, 0x1700},
 	{PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_GE},
-	{PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_GE_SA},
+	{PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_YU},
 	{}
 };
 
diff --git a/fs/jffs2/jffs2_1pass.c b/fs/jffs2/jffs2_1pass.c
index 10e6df8e18..5d0192cb80 100644
--- a/fs/jffs2/jffs2_1pass.c
+++ b/fs/jffs2/jffs2_1pass.c
@@ -114,6 +114,7 @@
 #include <common.h>
 #include <config.h>
 #include <malloc.h>
+#include <watchdog.h>
 #include <linux/stat.h>
 #include <linux/time.h>
 
@@ -126,7 +127,7 @@
 
 
 #define	NODE_CHUNK  	1024	/* size of memory allocation chunk in b_nodes */
-#define	SPIN_BLKSIZE	18  	/* spin after having scanned 1<<BLKSIZE bytes */
+#define	SPIN_BLKSIZE	20  	/* spin after having scanned 1<<BLKSIZE bytes */
 
 /* Debugging switches */
 #undef	DEBUG_DIRENTS		/* print directory entry list after scan */
@@ -276,8 +277,10 @@ static char *compr_names[] = {
 	"ZLIB"
 };
 
+#if 0  /* Use spinning wheel */
 /* Spinning wheel */
 static char spinner[] = { '|', '/', '-', '\\' };
+#endif
 
 /* Memory management */
 struct mem_block {
@@ -454,15 +457,24 @@ jffs2_scan_empty(u32 start_offset, struct part_info *part)
 {
 	char *max = part->offset + part->size - sizeof(struct jffs2_raw_inode);
 	char *offset = part->offset + start_offset;
+	int cntr = 0;
 	u32 off;
 
 	while (offset < max &&
 	       *(u32*)get_fl_mem((u32)offset, sizeof(u32), &off) == 0xFFFFFFFF) {
 		offset += sizeof(u32);
+		cntr++;
+#if 0  /* Use spinning wheel */
 		/* return if spinning is due */
 		if (((u32)offset & ((1 << SPIN_BLKSIZE)-1)) == 0) break;
+#endif
+		if (cntr > 1024 && part->erasesize > 0) { /* 4k */
+			/* round up to next erase block border */
+			(u32)offset |= part->erasesize-1;
+			offset++;
+			cntr = 0;
+		}
 	}
-
 	return offset - part->offset;
 }
 
@@ -921,6 +933,9 @@ jffs2_1pass_search_list_inodes(struct b_lists * pL, const char *fname, u32 pino)
 		for (i = 0; i < strlen(c) - 1; i++)
 			tmp[i] = c[i + 1];
 		tmp[i] = '\0';
+
+		WATCHDOG_RESET();
+
 		/* only a failure if we arent looking at top level */
 		if (!(pino = jffs2_1pass_find_inode(pL, working_tmp, pino)) &&
 		    (working_tmp[0])) {
@@ -1061,12 +1076,15 @@ jffs2_1pass_build_lists(struct part_info * part)
 {
 	struct b_lists *pL;
 	struct jffs2_unknown_node *node;
+	struct jffs2_unknown_node crcnode;
 	u32 offset, oldoffset = 0;
 	u32 max = part->size - sizeof(struct jffs2_raw_inode);
 	u32 counter = 0;
 	u32 counter4 = 0;
 	u32 counterF = 0;
 	u32 counterN = 0;
+	u32 counterCRC = 0;
+	u32 counterUNK = 0;
 
 #if defined(CONFIG_JFFS2_NAND) && (CONFIG_COMMANDS & CFG_CMD_NAND)
 	nanddev = (int)part->usr_priv - 1;
@@ -1087,14 +1105,26 @@ jffs2_1pass_build_lists(struct part_info * part)
 	/* start at the beginning of the partition */
 	while (offset < max) {
 	    	if ((oldoffset >> SPIN_BLKSIZE) != (offset >> SPIN_BLKSIZE)) {
+			WATCHDOG_RESET();
+#if 0  /* Use spinning wheel */
 			printf("\b\b%c ", spinner[counter++ % sizeof(spinner)]);
+#endif
 			oldoffset = offset;
 		}
-
 		node = (struct jffs2_unknown_node *) get_node_mem((u32)part->offset + offset);
-		if (node->magic == JFFS2_MAGIC_BITMASK && hdr_crc(node)) {
+		if (node->magic == JFFS2_MAGIC_BITMASK) {
 			/* if its a fragment add it */
-			if (node->nodetype == JFFS2_NODETYPE_INODE &&
+			/* check crc by readding a JFFS2_NODE_ACCURATE */
+			crcnode.magic = node->magic;
+			crcnode.nodetype = node->nodetype | JFFS2_NODE_ACCURATE;
+			crcnode.totlen = node->totlen;
+			crcnode.hdr_crc = node->hdr_crc;
+
+			if (!hdr_crc(&crcnode)) {
+				offset += 4;
+				counterCRC++;
+				continue;
+			} else if (node->nodetype == JFFS2_NODETYPE_INODE &&
 				    inode_crc((struct jffs2_raw_inode *) node)) {
 				if (insert_node(&pL->frag, (u32) part->offset +
 						offset) == NULL) {
@@ -1104,8 +1134,12 @@ jffs2_1pass_build_lists(struct part_info * part)
 			} else if (node->nodetype == JFFS2_NODETYPE_DIRENT &&
 				   dirent_crc((struct jffs2_raw_dirent *) node)  &&
 				   dirent_name_crc((struct jffs2_raw_dirent *) node)) {
-				if (! (counterN%100))
+				if (! (counterN%128))
+#if 0  /* Use spinning wheel */
 					puts ("\b\b.  ");
+#else
+					puts (".");
+#endif
 				if (insert_node(&pL->dir, (u32) part->offset +
 						offset) == NULL) {
 					put_fl_mem(node);
@@ -1123,16 +1157,14 @@ jffs2_1pass_build_lists(struct part_info * part)
 						"%d < %d\n", node->totlen,
 						sizeof(struct jffs2_unknown_node));
 			} else {
-				printf("Unknown node type: %x len %d "
-					"offset 0x%x\n", node->nodetype,
-					node->totlen, offset);
+				counterUNK++;
 			}
 			offset += ((node->totlen + 3) & ~3);
 			counterF++;
 		} else if (node->magic == JFFS2_EMPTY_BITMASK &&
 			   node->nodetype == JFFS2_EMPTY_BITMASK) {
 			offset = jffs2_scan_empty(offset, part);
-		} else {	/* if we know nothing, we just step and look. */
+		} else { /* if we know nothing, we just step and look. */
 			offset += 4;
 			counter4++;
 		}
@@ -1149,6 +1181,8 @@ jffs2_1pass_build_lists(struct part_info * part)
 	putLabeledWord("frag entries = ", pL->frag.listCount);
 	putLabeledWord("+4 increments = ", counter4);
 	putLabeledWord("+file_offset increments = ", counterF);
+	putLabeledWord("Unknown node types = ", counterUNK);
+	putLabeledWord("Bad hdr_crc = ", counterCRC);
 
 #endif
 
@@ -1204,6 +1238,7 @@ jffs2_get_list(struct part_info * part, const char *who)
 			return NULL;
 		}
 	}
+	WATCHDOG_RESET();
 	return (struct b_lists *)part->jffs2_priv;
 }
 
@@ -1213,24 +1248,21 @@ u32
 jffs2_1pass_ls(struct part_info * part, const char *fname)
 {
 	struct b_lists *pl;
-	long ret = 0;
 	u32 inode;
 
 	if (! (pl = jffs2_get_list(part, "ls")))
 		return 0;
 
+
 	if (! (inode = jffs2_1pass_search_list_inodes(pl, fname, 1))) {
 		putstr("ls: Failed to scan jffs2 file structure\r\n");
 		return 0;
 	}
-
-
 #if 0
 	putLabeledWord("found file at inode = ", inode);
 	putLabeledWord("read_inode returns = ", ret);
 #endif
-
-	return ret;
+	return inode;
 }
 
 
diff --git a/include/configs/versatile.h b/include/configs/versatile.h
index 5391439537..8df0e46a90 100644
--- a/include/configs/versatile.h
+++ b/include/configs/versatile.h
@@ -103,7 +103,7 @@
 #include <cmd_confdefs.h>
 
 #define CONFIG_BOOTDELAY	2
-#define CONFIG_BOOTARGS	"root=/dev/nfs mem=128M ip=dhcp netdev=27,0,0xfc800000,0xfc800010,eth0"
+#define CONFIG_BOOTARGS "root=/dev/nfs mem=128M ip=dhcp netdev=25,0,0xf1010000,0xf1010010,eth0"
 /*#define CONFIG_BOOTCOMMAND "bootp ; bootm" */
 
 /*
diff --git a/include/pci_ids.h b/include/pci_ids.h
index 6134421490..7dec378ad4 100644
--- a/include/pci_ids.h
+++ b/include/pci_ids.h
@@ -117,7 +117,7 @@
 
 #define PCI_CLASS_OTHERS		0xff
 
-/* Vendors and devices.  Sort key: vendor first, device next. */
+/* Vendors and devices.	 Sort key: vendor first, device next. */
 
 #define PCI_VENDOR_ID_DYNALINK		0x0675
 #define PCI_DEVICE_ID_DYNALINK_IS64PH	0x1702
@@ -140,11 +140,11 @@
 #define PCI_DEVICE_ID_COMPAQ_NETEL10	0xae34
 #define PCI_DEVICE_ID_COMPAQ_NETFLEX3I	0xae35
 #define PCI_DEVICE_ID_COMPAQ_NETEL100D	0xae40
-#define PCI_DEVICE_ID_COMPAQ_NETEL100PI	0xae43
+#define PCI_DEVICE_ID_COMPAQ_NETEL100PI 0xae43
 #define PCI_DEVICE_ID_COMPAQ_NETEL100I	0xb011
 #define PCI_DEVICE_ID_COMPAQ_CISS	0xb060
 #define PCI_DEVICE_ID_COMPAQ_CISSB	0xb178
-#define PCI_DEVICE_ID_COMPAQ_CISSC 	0x0046
+#define PCI_DEVICE_ID_COMPAQ_CISSC	0x0046
 #define PCI_DEVICE_ID_COMPAQ_THUNDER	0xf130
 #define PCI_DEVICE_ID_COMPAQ_NETFLEX3B	0xf150
 
@@ -407,10 +407,11 @@
 #define PCI_DEVICE_ID_IBM_MPIC		0x0046
 #define PCI_DEVICE_ID_IBM_3780IDSP	0x007d
 #define PCI_DEVICE_ID_IBM_CHUKAR	0x0096
+#define PCI_DEVICE_ID_IBM_CPC700	0x00f9
 #define PCI_DEVICE_ID_IBM_CPC710_PCI64	0x00fc
 #define PCI_DEVICE_ID_IBM_CPC710_PCI32	0x0105
-#define	PCI_DEVICE_ID_IBM_405GP		0x0156
-#define PCI_DEVICE_ID_IBM_SERVERAIDI960	0x01bd
+#define PCI_DEVICE_ID_IBM_405GP		0x0156
+#define PCI_DEVICE_ID_IBM_SERVERAIDI960 0x01bd
 #define PCI_DEVICE_ID_IBM_MPIC_2	0xffff
 
 #define PCI_VENDOR_ID_COMPEX2		0x101a /* pci.ids says "AT&T GIS (NCR)" */
@@ -459,13 +460,13 @@
 #define PCI_DEVICE_ID_AMD_OPUS_7449	0x7449
 #	define PCI_DEVICE_ID_AMD_VIPER_7449	PCI_DEVICE_ID_AMD_OPUS_7449
 #define PCI_DEVICE_ID_AMD_8111_LAN	0x7462
-#define PCI_DEVICE_ID_AMD_8111_IDE     0x7469
-#define PCI_DEVICE_ID_AMD_8111_AC97    0x746d
-#define PCI_DEVICE_ID_AMD_8131_APIC     0x7450
+#define PCI_DEVICE_ID_AMD_8111_IDE	0x7469
+#define PCI_DEVICE_ID_AMD_8111_AC97	0x746d
+#define PCI_DEVICE_ID_AMD_8131_APIC	0x7450
 
 #define PCI_VENDOR_ID_TRIDENT		0x1023
-#define PCI_DEVICE_ID_TRIDENT_4DWAVE_DX	0x2000
-#define PCI_DEVICE_ID_TRIDENT_4DWAVE_NX	0x2001
+#define PCI_DEVICE_ID_TRIDENT_4DWAVE_DX 0x2000
+#define PCI_DEVICE_ID_TRIDENT_4DWAVE_NX 0x2001
 #define PCI_DEVICE_ID_TRIDENT_9320	0x9320
 #define PCI_DEVICE_ID_TRIDENT_9388	0x9388
 #define PCI_DEVICE_ID_TRIDENT_9397	0x9397
@@ -485,7 +486,7 @@
 #define PCI_VENDOR_ID_AI		0x1025
 #define PCI_DEVICE_ID_AI_M1435		0x1435
 
-#define PCI_VENDOR_ID_DELL              0x1028
+#define PCI_VENDOR_ID_DELL		0x1028
 
 #define PCI_VENDOR_ID_MATROX		0x102B
 #define PCI_DEVICE_ID_MATROX_MGA_2	0x0518
@@ -498,7 +499,7 @@
 #define PCI_DEVICE_ID_MATROX_G100_AGP	0x1001
 #define PCI_DEVICE_ID_MATROX_G200_PCI	0x0520
 #define PCI_DEVICE_ID_MATROX_G200_AGP	0x0521
-#define	PCI_DEVICE_ID_MATROX_G400	0x0525
+#define PCI_DEVICE_ID_MATROX_G400	0x0525
 #define PCI_DEVICE_ID_MATROX_G550	0x2527
 #define PCI_DEVICE_ID_MATROX_VIA	0x4536
 
@@ -508,6 +509,7 @@
 #define PCI_DEVICE_ID_CT_65550		0x00e0
 #define PCI_DEVICE_ID_CT_65554		0x00e4
 #define PCI_DEVICE_ID_CT_65555		0x00e5
+#define PCI_DEVICE_ID_CT_69000		0x00c0
 
 #define PCI_VENDOR_ID_MIRO		0x1031
 #define PCI_DEVICE_ID_MIRO_36050	0x5601
@@ -516,9 +518,9 @@
 #define PCI_DEVICE_ID_NEC_NAPCCARD	0x003e
 #define PCI_DEVICE_ID_NEC_PCX2		0x0046
 #define PCI_DEVICE_ID_NEC_NILE4		0x005a
-#define PCI_DEVICE_ID_NEC_VRC5476       0x009b
+#define PCI_DEVICE_ID_NEC_VRC5476	0x009b
 #define PCI_DEVICE_ID_NEC_VRC4173	0x00a5
-#define PCI_DEVICE_ID_NEC_VRC5477_AC97  0x00a6
+#define PCI_DEVICE_ID_NEC_VRC5477_AC97	0x00a6
 
 #define PCI_VENDOR_ID_FD		0x1036
 #define PCI_DEVICE_ID_FD_36C70		0x0000
@@ -567,7 +569,7 @@
 #define PCI_DEVICE_ID_SI_750		0x0750
 #define PCI_DEVICE_ID_SI_751		0x0751
 #define PCI_DEVICE_ID_SI_752		0x0752
-#define PCI_DEVICE_ID_SI_755            0x0755
+#define PCI_DEVICE_ID_SI_755		0x0755
 #define PCI_DEVICE_ID_SI_900		0x0900
 #define PCI_DEVICE_ID_SI_5107		0x5107
 #define PCI_DEVICE_ID_SI_5300		0x5300
@@ -639,10 +641,10 @@
 #define PCI_DEVICE_ID_SGS_2000		0x0008
 #define PCI_DEVICE_ID_SGS_1764		0x0009
 
-#define PCI_VENDOR_ID_BUSLOGIC		      0x104B
-#define PCI_DEVICE_ID_BUSLOGIC_MULTIMASTER_NC 0x0140
-#define PCI_DEVICE_ID_BUSLOGIC_MULTIMASTER    0x1040
-#define PCI_DEVICE_ID_BUSLOGIC_FLASHPOINT     0x8130
+#define PCI_VENDOR_ID_BUSLOGIC			0x104B
+#define PCI_DEVICE_ID_BUSLOGIC_MULTIMASTER_NC	0x0140
+#define PCI_DEVICE_ID_BUSLOGIC_MULTIMASTER	0x1040
+#define PCI_DEVICE_ID_BUSLOGIC_FLASHPOINT	0x8130
 
 #define PCI_VENDOR_ID_TI		0x104c
 #define PCI_DEVICE_ID_TI_TVP4010	0x3d04
@@ -692,10 +694,14 @@
 #define PCI_DEVICE_ID_MOTOROLA_MPC105	0x0001
 #define PCI_DEVICE_ID_MOTOROLA_MPC106	0x0002
 #define PCI_DEVICE_ID_MOTOROLA_MPC107	0x0004
+#define PCI_DEVICE_ID_MOTOROLA_MPC8540	0x0008
+#define PCI_DEVICE_ID_MOTOROLA_MPC8560	0x0009
+#define PCI_DEVICE_ID_MOTOROLA_MPC8265A 0x18c0
 #define PCI_DEVICE_ID_MOTOROLA_RAVEN	0x4801
 #define PCI_DEVICE_ID_MOTOROLA_FALCON	0x4802
 #define PCI_DEVICE_ID_MOTOROLA_HAWK	0x4803
 #define PCI_DEVICE_ID_MOTOROLA_CPX8216	0x4806
+#define PCI_DEVICE_ID_MOTOROLA_MPC190	0x6400
 
 #define PCI_VENDOR_ID_PROMISE		0x105a
 #define PCI_DEVICE_ID_PROMISE_20265	0x0d30
@@ -752,11 +758,11 @@
 #define PCI_DEVICE_ID_APPLE_UNI_N_AGP	0x0020
 #define PCI_DEVICE_ID_APPLE_UNI_N_GMAC	0x0021
 #define PCI_DEVICE_ID_APPLE_KEYLARGO	0x0022
-#define PCI_DEVICE_ID_APPLE_UNI_N_GMACP	0x0024
+#define PCI_DEVICE_ID_APPLE_UNI_N_GMACP 0x0024
 #define PCI_DEVICE_ID_APPLE_KEYLARGO_P	0x0025
 #define PCI_DEVICE_ID_APPLE_KL_USB_P	0x0026
-#define PCI_DEVICE_ID_APPLE_UNI_N_AGP_P	0x0027
-#define PCI_DEVICE_ID_APPLE_UNI_N_AGP15	0x002d
+#define PCI_DEVICE_ID_APPLE_UNI_N_AGP_P 0x0027
+#define PCI_DEVICE_ID_APPLE_UNI_N_AGP15 0x002d
 #define PCI_DEVICE_ID_APPLE_UNI_N_FW2	0x0030
 #define PCI_DEVICE_ID_APPLE_TIGON3	0x1645
 
@@ -781,7 +787,7 @@
 #define PCI_DEVICE_ID_CYRIX_5510	0x0000
 #define PCI_DEVICE_ID_CYRIX_PCI_MASTER	0x0001
 #define PCI_DEVICE_ID_CYRIX_5520	0x0002
-#define PCI_DEVICE_ID_CYRIX_5530_LEGACY	0x0100
+#define PCI_DEVICE_ID_CYRIX_5530_LEGACY 0x0100
 #define PCI_DEVICE_ID_CYRIX_5530_SMI	0x0101
 #define PCI_DEVICE_ID_CYRIX_5530_IDE	0x0102
 #define PCI_DEVICE_ID_CYRIX_5530_AUDIO	0x0103
@@ -899,8 +905,8 @@
 #define PCI_DEVICE_ID_3COM_3C905T4	0x9051
 #define PCI_DEVICE_ID_3COM_3C905B_TX	0x9055
 #define PCI_DEVICE_ID_3COM_3CR990	0x9900
-#define PCI_DEVICE_ID_3COM_3CR990_TX_95	0x9902
-#define PCI_DEVICE_ID_3COM_3CR990_TX_97	0x9903
+#define PCI_DEVICE_ID_3COM_3CR990_TX_95 0x9902
+#define PCI_DEVICE_ID_3COM_3CR990_TX_97 0x9903
 #define PCI_DEVICE_ID_3COM_3CR990B	0x9904
 #define PCI_DEVICE_ID_3COM_3CR990_FX	0x9905
 #define PCI_DEVICE_ID_3COM_3CR990SVR95	0x9908
@@ -922,14 +928,14 @@
 #define PCI_DEVICE_ID_AL_M1523		0x1523
 #define PCI_DEVICE_ID_AL_M1531		0x1531
 #define PCI_DEVICE_ID_AL_M1533		0x1533
-#define PCI_DEVICE_ID_AL_M1535 		0x1535
+#define PCI_DEVICE_ID_AL_M1535		0x1535
 #define PCI_DEVICE_ID_AL_M1541		0x1541
-#define PCI_DEVICE_ID_AL_M1621          0x1621
-#define PCI_DEVICE_ID_AL_M1631          0x1631
-#define PCI_DEVICE_ID_AL_M1641          0x1641
-#define PCI_DEVICE_ID_AL_M1644          0x1644
-#define PCI_DEVICE_ID_AL_M1647          0x1647
-#define PCI_DEVICE_ID_AL_M1651          0x1651
+#define PCI_DEVICE_ID_AL_M1621		0x1621
+#define PCI_DEVICE_ID_AL_M1631		0x1631
+#define PCI_DEVICE_ID_AL_M1641		0x1641
+#define PCI_DEVICE_ID_AL_M1644		0x1644
+#define PCI_DEVICE_ID_AL_M1647		0x1647
+#define PCI_DEVICE_ID_AL_M1651		0x1651
 #define PCI_DEVICE_ID_AL_M1543		0x1543
 #define PCI_DEVICE_ID_AL_M3307		0x3307
 #define PCI_DEVICE_ID_AL_M4803		0x5215
@@ -946,12 +952,12 @@
 #define PCI_DEVICE_ID_SURECOM_NE34	0x0e34
 
 #define PCI_VENDOR_ID_NEOMAGIC		0x10c8
-#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_NM2070 0x0001
-#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_128V 0x0002
-#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_128ZV 0x0003
-#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_NM2160 0x0004
-#define PCI_DEVICE_ID_NEOMAGIC_MAGICMEDIA_256AV       0x0005
-#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_128ZVPLUS   0x0083
+#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_NM2070	0x0001
+#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_128V		0x0002
+#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_128ZV		0x0003
+#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_NM2160	0x0004
+#define PCI_DEVICE_ID_NEOMAGIC_MAGICMEDIA_256AV		0x0005
+#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_128ZVPLUS	0x0083
 
 #define PCI_VENDOR_ID_ASP		0x10cd
 #define PCI_DEVICE_ID_ASP_ABP940	0x1200
@@ -963,7 +969,7 @@
 #define PCI_DEVICE_ID_MACRONIX_MX987x5	0x0531
 
 #define PCI_VENDOR_ID_TCONRAD		0x10da
-#define PCI_DEVICE_ID_TCONRAD_TOKENRING	0x0508
+#define PCI_DEVICE_ID_TCONRAD_TOKENRING 0x0508
 
 #define PCI_VENDOR_ID_CERN		0x10dc
 #define PCI_DEVICE_ID_CERN_SPSB_PMC	0x0001
@@ -1126,8 +1132,8 @@
 #define PCI_DEVICE_ID_VIA_8633_1	0xB091
 #define PCI_DEVICE_ID_VIA_8367_1	0xB099
 
-#define PCI_VENDOR_ID_SIEMENS           0x110A
-#define PCI_DEVICE_ID_SIEMENS_DSCC4     0x2102
+#define PCI_VENDOR_ID_SIEMENS		0x110A
+#define PCI_DEVICE_ID_SIEMENS_DSCC4	0x2102
 
 #define PCI_VENDOR_ID_SMC2		0x1113
 #define PCI_DEVICE_ID_SMC2_1211TX	0x1211
@@ -1153,18 +1159,18 @@
 #define PCI_DEVICE_ID_VORTEX_GDT6557RP	0x0103
 #define PCI_DEVICE_ID_VORTEX_GDT6x11RP	0x0104
 #define PCI_DEVICE_ID_VORTEX_GDT6x21RP	0x0105
-#define PCI_DEVICE_ID_VORTEX_GDT6x17RP1	0x0110
-#define PCI_DEVICE_ID_VORTEX_GDT6x27RP1	0x0111
-#define PCI_DEVICE_ID_VORTEX_GDT6537RP1	0x0112
-#define PCI_DEVICE_ID_VORTEX_GDT6557RP1	0x0113
-#define PCI_DEVICE_ID_VORTEX_GDT6x11RP1	0x0114
-#define PCI_DEVICE_ID_VORTEX_GDT6x21RP1	0x0115
-#define PCI_DEVICE_ID_VORTEX_GDT6x17RP2	0x0120
-#define PCI_DEVICE_ID_VORTEX_GDT6x27RP2	0x0121
-#define PCI_DEVICE_ID_VORTEX_GDT6537RP2	0x0122
-#define PCI_DEVICE_ID_VORTEX_GDT6557RP2	0x0123
-#define PCI_DEVICE_ID_VORTEX_GDT6x11RP2	0x0124
-#define PCI_DEVICE_ID_VORTEX_GDT6x21RP2	0x0125
+#define PCI_DEVICE_ID_VORTEX_GDT6x17RP1 0x0110
+#define PCI_DEVICE_ID_VORTEX_GDT6x27RP1 0x0111
+#define PCI_DEVICE_ID_VORTEX_GDT6537RP1 0x0112
+#define PCI_DEVICE_ID_VORTEX_GDT6557RP1 0x0113
+#define PCI_DEVICE_ID_VORTEX_GDT6x11RP1 0x0114
+#define PCI_DEVICE_ID_VORTEX_GDT6x21RP1 0x0115
+#define PCI_DEVICE_ID_VORTEX_GDT6x17RP2 0x0120
+#define PCI_DEVICE_ID_VORTEX_GDT6x27RP2 0x0121
+#define PCI_DEVICE_ID_VORTEX_GDT6537RP2 0x0122
+#define PCI_DEVICE_ID_VORTEX_GDT6557RP2 0x0123
+#define PCI_DEVICE_ID_VORTEX_GDT6x11RP2 0x0124
+#define PCI_DEVICE_ID_VORTEX_GDT6x21RP2 0x0125
 
 #define PCI_VENDOR_ID_EF		0x111a
 #define PCI_DEVICE_ID_EF_ATM_FPGA	0x0000
@@ -1178,7 +1184,7 @@
 #define PCI_DEVICE_ID_FORE_PCA200E	0x0300
 
 #define PCI_VENDOR_ID_IMAGINGTECH	0x112f
-#define PCI_DEVICE_ID_IMAGINGTECH_ICPCI	0x0000
+#define PCI_DEVICE_ID_IMAGINGTECH_ICPCI 0x0000
 
 #define PCI_VENDOR_ID_PHILIPS		0x1131
 #define PCI_DEVICE_ID_PHILIPS_SAA7145	0x7145
@@ -1188,7 +1194,7 @@
 #define PCI_VENDOR_ID_EICON		0x1133
 #define PCI_DEVICE_ID_EICON_DIVA20PRO	0xe001
 #define PCI_DEVICE_ID_EICON_DIVA20	0xe002
-#define PCI_DEVICE_ID_EICON_DIVA20PRO_U	0xe003
+#define PCI_DEVICE_ID_EICON_DIVA20PRO_U 0xe003
 #define PCI_DEVICE_ID_EICON_DIVA20_U	0xe004
 #define PCI_DEVICE_ID_EICON_DIVA201	0xe005
 #define PCI_DEVICE_ID_EICON_DIVA202	0xe00b
@@ -1201,8 +1207,8 @@
 #define PCI_DEVICE_ID_CYCLONE_SDK	0x0001
 
 #define PCI_VENDOR_ID_ALLIANCE		0x1142
-#define PCI_DEVICE_ID_ALLIANCE_PROMOTIO	0x3210
-#define PCI_DEVICE_ID_ALLIANCE_PROVIDEO	0x6422
+#define PCI_DEVICE_ID_ALLIANCE_PROMOTIO 0x3210
+#define PCI_DEVICE_ID_ALLIANCE_PROVIDEO 0x6422
 #define PCI_DEVICE_ID_ALLIANCE_AT24	0x6424
 #define PCI_DEVICE_ID_ALLIANCE_AT3D	0x643d
 
@@ -1242,25 +1248,25 @@
 #define PCI_DEVICE_ID_RENDITION_VERITE	0x0001
 #define PCI_DEVICE_ID_RENDITION_VERITE2100 0x2000
 
-#define PCI_VENDOR_ID_SERVERWORKS	  0x1166
-#define PCI_DEVICE_ID_SERVERWORKS_HE	  0x0008
-#define PCI_DEVICE_ID_SERVERWORKS_LE	  0x0009
-#define PCI_DEVICE_ID_SERVERWORKS_CIOB30  0x0010
-#define PCI_DEVICE_ID_SERVERWORKS_CMIC_HE 0x0011
-#define PCI_DEVICE_ID_SERVERWORKS_GCNB_LE 0x0017
-#define PCI_DEVICE_ID_SERVERWORKS_OSB4	  0x0200
-#define PCI_DEVICE_ID_SERVERWORKS_CSB5	  0x0201
-#define PCI_DEVICE_ID_SERVERWORKS_CSB6    0x0203
-#define PCI_DEVICE_ID_SERVERWORKS_OSB4IDE 0x0211
-#define PCI_DEVICE_ID_SERVERWORKS_CSB5IDE 0x0212
-#define PCI_DEVICE_ID_SERVERWORKS_CSB6IDE 0x0213
-#define PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2 0x0217
-#define PCI_DEVICE_ID_SERVERWORKS_OSB4USB 0x0220
-#define PCI_DEVICE_ID_SERVERWORKS_CSB5USB PCI_DEVICE_ID_SERVERWORKS_OSB4USB
-#define PCI_DEVICE_ID_SERVERWORKS_CSB6USB 0x0221
-#define PCI_DEVICE_ID_SERVERWORKS_GCLE    0x0225
-#define PCI_DEVICE_ID_SERVERWORKS_GCLE2   0x0227
-#define PCI_DEVICE_ID_SERVERWORKS_CSB5ISA 0x0230
+#define PCI_VENDOR_ID_SERVERWORKS		0x1166
+#define PCI_DEVICE_ID_SERVERWORKS_HE		0x0008
+#define PCI_DEVICE_ID_SERVERWORKS_LE		0x0009
+#define PCI_DEVICE_ID_SERVERWORKS_CIOB30	0x0010
+#define PCI_DEVICE_ID_SERVERWORKS_CMIC_HE	0x0011
+#define PCI_DEVICE_ID_SERVERWORKS_GCNB_LE	0x0017
+#define PCI_DEVICE_ID_SERVERWORKS_OSB4		0x0200
+#define PCI_DEVICE_ID_SERVERWORKS_CSB5		0x0201
+#define PCI_DEVICE_ID_SERVERWORKS_CSB6		0x0203
+#define PCI_DEVICE_ID_SERVERWORKS_OSB4IDE	0x0211
+#define PCI_DEVICE_ID_SERVERWORKS_CSB5IDE	0x0212
+#define PCI_DEVICE_ID_SERVERWORKS_CSB6IDE	0x0213
+#define PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2	0x0217
+#define PCI_DEVICE_ID_SERVERWORKS_OSB4USB	0x0220
+#define PCI_DEVICE_ID_SERVERWORKS_CSB5USB	PCI_DEVICE_ID_SERVERWORKS_OSB4USB
+#define PCI_DEVICE_ID_SERVERWORKS_CSB6USB	0x0221
+#define PCI_DEVICE_ID_SERVERWORKS_GCLE		0x0225
+#define PCI_DEVICE_ID_SERVERWORKS_GCLE2		0x0227
+#define PCI_DEVICE_ID_SERVERWORKS_CSB5ISA	0x0230
 
 #define PCI_VENDOR_ID_SBE		0x1176
 #define PCI_DEVICE_ID_SBE_WANXL100	0x0301
@@ -1275,7 +1281,7 @@
 
 #define PCI_VENDOR_ID_TOSHIBA_2		0x102f
 #define PCI_DEVICE_ID_TOSHIBA_TX3927	0x000a
-#define PCI_DEVICE_ID_TOSHIBA_TC35815CF	0x0030
+#define PCI_DEVICE_ID_TOSHIBA_TC35815CF 0x0030
 #define PCI_DEVICE_ID_TOSHIBA_TX4927	0x0180
 
 #define PCI_VENDOR_ID_RICOH		0x1180
@@ -1343,7 +1349,7 @@
 #define PCI_SUBDEVICE_ID_SPECIALIX_SPEED4 0xa004
 
 #define PCI_VENDOR_ID_AURAVISION	0x11d1
-#define PCI_DEVICE_ID_AURAVISION_VXP524	0x01f7
+#define PCI_DEVICE_ID_AURAVISION_VXP524 0x01f7
 
 #define PCI_VENDOR_ID_ANALOG_DEVICES	0x11d4
 #define PCI_DEVICE_ID_AD1889JS		0x1889
@@ -1360,7 +1366,7 @@
 #define PCI_DEVICE_ID_KINETIC_2915	0x2915
 
 #define PCI_VENDOR_ID_COMPEX		0x11f6
-#define PCI_DEVICE_ID_COMPEX_ENET100VG4	0x0112
+#define PCI_DEVICE_ID_COMPEX_ENET100VG4 0x0112
 #define PCI_DEVICE_ID_COMPEX_RL2000	0x1401
 
 #define PCI_VENDOR_ID_RP		0x11fe
@@ -1440,6 +1446,11 @@
 #define PCI_DEVICE_ID_SATSAGEM_PCR2101	0x5352
 #define PCI_DEVICE_ID_SATSAGEM_TELSATTURBO 0x5a4b
 
+#define PCI_VENDOR_ID_SMI		0x126f
+#define PCI_DEVICE_ID_SMI_710		0x0710
+#define PCI_DEVICE_ID_SMI_712		0x0712
+#define PCI_DEVICE_ID_SMI_810		0x0810
+
 #define PCI_VENDOR_ID_HUGHES		0x1273
 #define PCI_DEVICE_ID_HUGHES_DIRECPC	0x0002
 
@@ -1450,13 +1461,16 @@
 
 #define PCI_VENDOR_ID_ROCKWELL		0x127A
 
+#define PCI_VENDOR_ID_DAVICOM		0x1282
+#define PCI_DEVICE_ID_DAVICOM_DM9102A	0x9102
+
 #define PCI_VENDOR_ID_ITE		0x1283
 #define PCI_DEVICE_ID_ITE_IT8172G	0x8172
 #define PCI_DEVICE_ID_ITE_IT8172G_AUDIO 0x0801
 #define PCI_DEVICE_ID_ITE_IT8181	0x8181
 #define PCI_DEVICE_ID_ITE_8872		0x8872
 
-#define PCI_DEVICE_ID_ITE_IT8330G_0    0xe886
+#define PCI_DEVICE_ID_ITE_IT8330G_0	0xe886
 
 /* formerly Platform Tech */
 #define PCI_VENDOR_ID_ESS_OLD		0x1285
@@ -1506,17 +1520,17 @@
 #define PCI_DEVICE_ID_SIIG_1S_10x_550	0x1000
 #define PCI_DEVICE_ID_SIIG_1S_10x_650	0x1001
 #define PCI_DEVICE_ID_SIIG_1S_10x_850	0x1002
-#define PCI_DEVICE_ID_SIIG_1S1P_10x_550	0x1010
-#define PCI_DEVICE_ID_SIIG_1S1P_10x_650	0x1011
-#define PCI_DEVICE_ID_SIIG_1S1P_10x_850	0x1012
+#define PCI_DEVICE_ID_SIIG_1S1P_10x_550 0x1010
+#define PCI_DEVICE_ID_SIIG_1S1P_10x_650 0x1011
+#define PCI_DEVICE_ID_SIIG_1S1P_10x_850 0x1012
 #define PCI_DEVICE_ID_SIIG_1P_10x	0x1020
 #define PCI_DEVICE_ID_SIIG_2P_10x	0x1021
 #define PCI_DEVICE_ID_SIIG_2S_10x_550	0x1030
 #define PCI_DEVICE_ID_SIIG_2S_10x_650	0x1031
 #define PCI_DEVICE_ID_SIIG_2S_10x_850	0x1032
-#define PCI_DEVICE_ID_SIIG_2S1P_10x_550	0x1034
-#define PCI_DEVICE_ID_SIIG_2S1P_10x_650	0x1035
-#define PCI_DEVICE_ID_SIIG_2S1P_10x_850	0x1036
+#define PCI_DEVICE_ID_SIIG_2S1P_10x_550 0x1034
+#define PCI_DEVICE_ID_SIIG_2S1P_10x_650 0x1035
+#define PCI_DEVICE_ID_SIIG_2S1P_10x_850 0x1036
 #define PCI_DEVICE_ID_SIIG_4S_10x_550	0x1050
 #define PCI_DEVICE_ID_SIIG_4S_10x_650	0x1051
 #define PCI_DEVICE_ID_SIIG_4S_10x_850	0x1052
@@ -1528,18 +1542,18 @@
 #define PCI_DEVICE_ID_SIIG_2S_20x_550	0x2030
 #define PCI_DEVICE_ID_SIIG_2S_20x_650	0x2031
 #define PCI_DEVICE_ID_SIIG_2S_20x_850	0x2032
-#define PCI_DEVICE_ID_SIIG_2P1S_20x_550	0x2040
-#define PCI_DEVICE_ID_SIIG_2P1S_20x_650	0x2041
-#define PCI_DEVICE_ID_SIIG_2P1S_20x_850	0x2042
-#define PCI_DEVICE_ID_SIIG_1S1P_20x_550	0x2010
-#define PCI_DEVICE_ID_SIIG_1S1P_20x_650	0x2011
-#define PCI_DEVICE_ID_SIIG_1S1P_20x_850	0x2012
+#define PCI_DEVICE_ID_SIIG_2P1S_20x_550 0x2040
+#define PCI_DEVICE_ID_SIIG_2P1S_20x_650 0x2041
+#define PCI_DEVICE_ID_SIIG_2P1S_20x_850 0x2042
+#define PCI_DEVICE_ID_SIIG_1S1P_20x_550 0x2010
+#define PCI_DEVICE_ID_SIIG_1S1P_20x_650 0x2011
+#define PCI_DEVICE_ID_SIIG_1S1P_20x_850 0x2012
 #define PCI_DEVICE_ID_SIIG_4S_20x_550	0x2050
 #define PCI_DEVICE_ID_SIIG_4S_20x_650	0x2051
 #define PCI_DEVICE_ID_SIIG_4S_20x_850	0x2052
-#define PCI_DEVICE_ID_SIIG_2S1P_20x_550	0x2060
-#define PCI_DEVICE_ID_SIIG_2S1P_20x_650	0x2061
-#define PCI_DEVICE_ID_SIIG_2S1P_20x_850	0x2062
+#define PCI_DEVICE_ID_SIIG_2S1P_20x_550 0x2060
+#define PCI_DEVICE_ID_SIIG_2S1P_20x_650 0x2061
+#define PCI_DEVICE_ID_SIIG_2S1P_20x_850 0x2062
 
 #define PCI_VENDOR_ID_DOMEX		0x134a
 #define PCI_DEVICE_ID_DOMEX_DMX3191D	0x0001
@@ -1555,8 +1569,8 @@
 #define PCI_VENDOR_ID_SEALEVEL		0x135e
 #define PCI_DEVICE_ID_SEALEVEL_U530	0x7101
 #define PCI_DEVICE_ID_SEALEVEL_UCOMM2	0x7201
-#define PCI_DEVICE_ID_SEALEVEL_UCOMM422	0x7402
-#define PCI_DEVICE_ID_SEALEVEL_UCOMM232	0x7202
+#define PCI_DEVICE_ID_SEALEVEL_UCOMM422 0x7402
+#define PCI_DEVICE_ID_SEALEVEL_UCOMM232 0x7202
 #define PCI_DEVICE_ID_SEALEVEL_COMM4	0x7401
 #define PCI_DEVICE_ID_SEALEVEL_COMM8	0x7801
 
@@ -1609,7 +1623,7 @@
 #define PCI_DEVICE_ID_3WARE_1000	0x1000
 
 #define PCI_VENDOR_ID_ABOCOM		0x13D1
-#define PCI_DEVICE_ID_ABOCOM_2BD1       0x2BD1
+#define PCI_DEVICE_ID_ABOCOM_2BD1	0x2BD1
 
 #define PCI_VENDOR_ID_CMEDIA		0x13f6
 #define PCI_DEVICE_ID_CMEDIA_CM8338A	0x0100
@@ -1640,7 +1654,7 @@
 #define PCI_DEVICE_ID_OXSEMI_12PCI840	0x8403
 #define PCI_DEVICE_ID_OXSEMI_16PCI954	0x9501
 #define PCI_DEVICE_ID_OXSEMI_16PCI95N	0x9511
-#define PCI_DEVICE_ID_OXSEMI_16PCI954PP	0x9513
+#define PCI_DEVICE_ID_OXSEMI_16PCI954PP 0x9513
 #define PCI_DEVICE_ID_OXSEMI_16PCI952	0x9521
 
 #define PCI_VENDOR_ID_AIRONET		0x14b9
@@ -1662,8 +1676,8 @@
 #define PCI_DEVICE_ID_TITAN_800B	0xA004
 
 #define PCI_VENDOR_ID_PANACOM		0x14d4
-#define PCI_DEVICE_ID_PANACOM_QUADMODEM	0x0400
-#define PCI_DEVICE_ID_PANACOM_DUALMODEM	0x0402
+#define PCI_DEVICE_ID_PANACOM_QUADMODEM 0x0400
+#define PCI_DEVICE_ID_PANACOM_DUALMODEM 0x0402
 
 #define PCI_VENDOR_ID_AFAVLAB		0x14db
 #define PCI_DEVICE_ID_AFAVLAB_P028	0x2180
@@ -1734,7 +1748,7 @@
 #define PCI_DEVICE_ID_3DLABS_MX		0x0006
 #define PCI_DEVICE_ID_3DLABS_PERMEDIA2	0x0007
 #define PCI_DEVICE_ID_3DLABS_GAMMA	0x0008
-#define PCI_DEVICE_ID_3DLABS_PERMEDIA2V	0x0009
+#define PCI_DEVICE_ID_3DLABS_PERMEDIA2V 0x0009
 
 #define PCI_VENDOR_ID_AVANCE		0x4005
 #define PCI_DEVICE_ID_AVANCE_ALG2064	0x2064
@@ -1784,6 +1798,7 @@
 
 #define PCI_VENDOR_ID_INTEL		0x8086
 #define PCI_DEVICE_ID_INTEL_21145	0x0039
+#define PCI_DEVICE_ID_INTEL_21152BB	0xb152
 #define PCI_DEVICE_ID_INTEL_82375	0x0482
 #define PCI_DEVICE_ID_INTEL_82424	0x0483
 #define PCI_DEVICE_ID_INTEL_82378	0x0484
@@ -1791,6 +1806,21 @@
 #define PCI_DEVICE_ID_INTEL_82434	0x04a3
 #define PCI_DEVICE_ID_INTEL_I960	0x0960
 #define PCI_DEVICE_ID_INTEL_I960RM	0x0962
+#define PCI_DEVICE_ID_INTEL_82542	0x1000
+#define PCI_DEVICE_ID_INTEL_82543GC_FIBER	0x1001
+#define PCI_DEVICE_ID_INTEL_82543GC_COPPER	0x1004
+#define PCI_DEVICE_ID_INTEL_82544EI_COPPER	0x1008
+#define PCI_DEVICE_ID_INTEL_82544EI_FIBER	0x1009
+#define PCI_DEVICE_ID_INTEL_82544GC_COPPER	0x100C
+#define PCI_DEVICE_ID_INTEL_82544GC_LOM		0x100D
+#define PCI_DEVICE_ID_INTEL_82540EM		0x100E
+#define PCI_DEVICE_ID_INTEL_82545EM_COPPER	0x100F
+#define PCI_DEVICE_ID_INTEL_82546EB_COPPER	0x1010
+#define PCI_DEVICE_ID_INTEL_82545EM_FIBER	0x1011
+#define PCI_DEVICE_ID_INTEL_82546EB_FIBER	0x1012
+#define PCI_DEVICE_ID_INTEL_82540EM_LOM		0x1015
+#define PCI_DEVICE_ID_INTEL_82559		0x1030
+
 #define PCI_DEVICE_ID_INTEL_82562ET	0x1031
 
 #define PCI_DEVICE_ID_INTEL_82815_MC	0x1130