Merge branch 'master' of /home/stefan/git/u-boot/u-boot

1048 files changed, 15233 insertions, 13672 deletions

diff --git a/MAKEALL b/MAKEALL
index cdc0011b9b..4bf6d4dcd5 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -355,6 +355,7 @@ LIST_85xx="		\
 	sbc8540		\
 	sbc8548		\
 	sbc8560		\
+	socrates	\
 	stxgp3		\
 	stxssa		\
 	TQM8540		\
diff --git a/Makefile b/Makefile
index c2f3361e72..04cebacbb9 100644
--- a/Makefile
+++ b/Makefile
@@ -2211,6 +2211,9 @@ sbc8560_66_config:	unconfig
 	fi
 	@$(MKCONFIG) -a sbc8560 ppc mpc85xx sbc8560
 
+socrates_config:	unconfig
+	@$(MKCONFIG) $(@:_config=) ppc mpc85xx socrates
+
 stxgp3_config:		unconfig
 	@$(MKCONFIG) $(@:_config=) ppc mpc85xx stxgp3
 
diff --git a/board/MAI/AmigaOneG3SE/AmigaOneG3SE.c b/board/MAI/AmigaOneG3SE/AmigaOneG3SE.c
index b472176635..3bbc09dd9c 100644
--- a/board/MAI/AmigaOneG3SE/AmigaOneG3SE.c
+++ b/board/MAI/AmigaOneG3SE/AmigaOneG3SE.c
@@ -14,7 +14,7 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
@@ -30,48 +30,48 @@
 #include "memio.h"
 #include "via686.h"
 
-__asm__(" .globl send_kb                   		    \n "
-	"send_kb:                                           \n "
-	"	lis     r9, 0xfe00                          \n "
-	"						    \n "
-	"	li      r4, 0x10        # retries           \n "
-	"	mtctr   r4                                  \n "
-	"						    \n "
-	"idle:                                              \n "
-	"	lbz     r4, 0x64(r9)                        \n "
-	"	andi.   r4, r4, 0x02                        \n "
-	"	bne     idle                                \n "
-
-	"ready:                                             \n "
-	"	stb     r3, 0x60(r9)                        \n "
-	"						    \n "
-	"check:                                             \n "
-	"	lbz     r4, 0x64(r9)                        \n "
-	"	andi.   r4, r4, 0x01                        \n "
-	"	beq     check                               \n "
-	"						    \n "
-	"	lbz     r4, 0x60(r9)                        \n "
-	"	cmpwi   r4, 0xfa                            \n "
-	"	beq     done                                \n "
-
-	"	bdnz    idle                                \n "
-
-	"	li      r3, 0                               \n "
-	"	blr                                         \n "
-
-	"done:                                              \n "
-	"	li      r3, 1                               \n "
-	"	blr                                         \n "
-
-	".globl test_kb                                     \n "
-	"test_kb:                                           \n "
-	"	mflr    r10                                 \n "
-	"	li      r3, 0xed                            \n "
-	"	bl      send_kb                             \n "
-	"	li      r3, 0x01                            \n "
-	"	bl      send_kb                             \n "
-	"	mtlr    r10                                 \n "
-	"	blr                                         "
+__asm__(" .globl send_kb				\n "
+	"send_kb:					\n "
+	"	lis	r9, 0xfe00			\n "
+	"						\n "
+	"	li	r4, 0x10	# retries	\n "
+	"	mtctr	r4				\n "
+	"						\n "
+	"idle:						\n "
+	"	lbz	r4, 0x64(r9)			\n "
+	"	andi.	r4, r4, 0x02			\n "
+	"	bne	idle				\n "
+
+	"ready:						\n "
+	"	stb	r3, 0x60(r9)			\n "
+	"						\n "
+	"check:						\n "
+	"	lbz	r4, 0x64(r9)			\n "
+	"	andi.	r4, r4, 0x01			\n "
+	"	beq	check				\n "
+	"						\n "
+	"	lbz	r4, 0x60(r9)			\n "
+	"	cmpwi	r4, 0xfa			\n "
+	"	beq	done				\n "
+
+	"	bdnz	idle				\n "
+
+	"	li	r3, 0				\n "
+	"	blr					\n "
+
+	"done:						\n "
+	"	li	r3, 1				\n "
+	"	blr					\n "
+
+	".globl test_kb					\n "
+	"test_kb:					\n "
+	"	mflr	r10				\n "
+	"	li	r3, 0xed			\n "
+	"	bl	send_kb				\n "
+	"	li	r3, 0x01			\n "
+	"	bl	send_kb				\n "
+	"	mtlr	r10				\n "
+	"	blr					\n "
 );
 
 
diff --git a/board/MAI/AmigaOneG3SE/enet.c b/board/MAI/AmigaOneG3SE/enet.c
index ad2bcdeffe..5a90cc57dd 100644
--- a/board/MAI/AmigaOneG3SE/enet.c
+++ b/board/MAI/AmigaOneG3SE/enet.c
@@ -90,8 +90,8 @@
 #define DMADone			(1<<8)
 #define DownComplete		(1<<9)
 #define UpComplete		(1<<10)
-#define DMAInProgress		(1<<11)			/* DMA controller is still busy.*/
-#define CmdInProgress		(1<<12)          	/* EL3_CMD is still busy.*/
+#define DMAInProgress		(1<<11)		/* DMA controller is still busy.*/
+#define CmdInProgress		(1<<12)		/* EL3_CMD is still busy.*/
 
 /* Polling Registers */
 
@@ -100,17 +100,17 @@
 
 /* Register window 0 offets */
 
-#define Wn0EepromCmd		10	         	/* Window 0: EEPROM command register. */
-#define Wn0EepromData		12            		/* Window 0: EEPROM results register. */
-#define IntrStatus		0x0E	                /* Valid in all windows. */
+#define Wn0EepromCmd		10		/* Window 0: EEPROM command register. */
+#define Wn0EepromData		12		/* Window 0: EEPROM results register. */
+#define IntrStatus		0x0E		/* Valid in all windows. */
 
 /* Register window 0 EEPROM bits */
 
 #define EEPROM_Read		0x80
 #define EEPROM_WRITE		0x40
 #define EEPROM_ERASE		0xC0
-#define EEPROM_EWENB		0x30          		/* Enable erasing/writing for 10 msec. */
-#define EEPROM_EWDIS		0x00           		/* Disable EWENB before 10 msec timeout. */
+#define EEPROM_EWENB		0x30		/* Enable erasing/writing for 10 msec. */
+#define EEPROM_EWDIS		0x00		/* Disable EWENB before 10 msec timeout. */
 
 /* EEPROM locations. */
 
@@ -135,7 +135,7 @@
 #define RxStatus		0x18
 #define Timer			0x1A
 #define TxStatus		0x1B
-#define TxFree			0x1C			/* Remaining free bytes in Tx buffer. */
+#define TxFree			0x1C		/* Remaining free bytes in Tx buffer. */
 
 /* Register Window 2 */
 
@@ -143,23 +143,23 @@
 
 /* Register Window 3: MAC/config bits */
 
-#define Wn3_Config		0			/* Internal Configuration */
+#define Wn3_Config		0		/* Internal Configuration */
 #define Wn3_MAC_Ctrl		6
 #define Wn3_Options		8
 
 #define BFEXT(value, offset, bitcount)					\
 	((((unsigned long)(value)) >> (offset)) & ((1 << (bitcount)) - 1))
 
-#define BFINS(lhs, rhs, offset, bitcount)                                       \
+#define BFINS(lhs, rhs, offset, bitcount)					\
 	(((lhs) & ~((((1 << (bitcount)) - 1)) << (offset))) |			\
 	(((rhs) & ((1 << (bitcount)) - 1)) << (offset)))
 
-#define RAM_SIZE(v)             BFEXT(v, 0, 3)
+#define RAM_SIZE(v)		BFEXT(v, 0, 3)
 #define RAM_WIDTH(v)		BFEXT(v, 3, 1)
-#define RAM_SPEED(v) 	   	BFEXT(v, 4, 2)
-#define ROM_SIZE(v)             BFEXT(v, 6, 2)
+#define RAM_SPEED(v)		BFEXT(v, 4, 2)
+#define ROM_SIZE(v)		BFEXT(v, 6, 2)
 #define RAM_SPLIT(v)		BFEXT(v, 16, 2)
-#define XCVR(v)                 BFEXT(v, 20, 4)
+#define XCVR(v)			BFEXT(v, 20, 4)
 #define AUTOSELECT(v)		BFEXT(v, 24, 1)
 
 /* Register Window 4: Xcvr/media bits */
@@ -186,20 +186,20 @@
 #define DownListPtr		0x24
 #define FragAddr		0x28
 #define FragLen			0x2c
-#define TxFreeThreshold 	0x2f
+#define TxFreeThreshold	0x2f
 #define UpPktStatus		0x30
-#define UpListPtr 		0x38
+#define UpListPtr		0x38
 
 /* The Rx and Tx descriptor lists. */
 
-#define LAST_FRAG       0x80000000                      /* Last Addr/Len pair in descriptor. */
-#define DN_COMPLETE     0x00010000                      /* This packet has been downloaded */
+#define LAST_FRAG	0x80000000		/* Last Addr/Len pair in descriptor. */
+#define DN_COMPLETE	0x00010000		/* This packet has been downloaded */
 
 struct rx_desc_3com {
-	u32 next;                                       /* Last entry points to 0	   	*/
-	u32 status;					/* FSH -> Frame Start Header 		*/
-	u32 addr;                                       /* Up to 63 addr/len pairs possible 	*/
-	u32 length;                                     /* Set LAST_FRAG to indicate last pair	*/
+	u32 next;				/* Last entry points to 0		*/
+	u32 status;				/* FSH -> Frame Start Header		*/
+	u32 addr;				/* Up to 63 addr/len pairs possible	*/
+	u32 length;				/* Set LAST_FRAG to indicate last pair	*/
 };
 
 /* Values for the Rx status entry. */
@@ -214,8 +214,8 @@ struct rx_desc_3com {
 #define UDPChksumValid		(1<<31)
 
 struct tx_desc_3com {
-	u32 next;                                       /* Last entry points to 0		*/
-	u32 status;                                     /* bits 0:12 length, others see below	*/
+	u32 next;				/* Last entry points to 0		*/
+	u32 status;				/* bits 0:12 length, others see below	*/
 	u32 addr;
 	u32 length;
 };
@@ -227,7 +227,7 @@ struct tx_desc_3com {
 #define AddIPChksum		0x02000000
 #define AddTCPChksum		0x04000000
 #define AddUDPChksum		0x08000000
-#define TxIntrUploaded		0x80000000              /* IRQ when in FIFO, but maybe not sent. */
+#define TxIntrUploaded		0x80000000	/* IRQ when in FIFO, but maybe not sent. */
 
 /* XCVR Types */
 
@@ -240,19 +240,19 @@ struct tx_desc_3com {
 #define XCVR_MII		6
 #define XCVR_NWAY		8
 #define XCVR_ExtMII		9
-#define XCVR_Default		10			/* I don't think this is correct -> should have been 0x10 if Auto Negotiate */
+#define XCVR_Default		10		/* I don't think this is correct -> should have been 0x10 if Auto Negotiate */
 
-struct descriptor {			    		/* A generic descriptor. */
-	u32 next;                                       /* Last entry points to 0	   	*/
-	u32 status;					/* FSH -> Frame Start Header 		*/
-	u32 addr;                                       /* Up to 63 addr/len pairs possible 	*/
-	u32 length;                                     /* Set LAST_FRAG to indicate last pair	*/
+struct descriptor {				/* A generic descriptor. */
+	u32 next;				/* Last entry points to 0		*/
+	u32 status;				/* FSH -> Frame Start Header		*/
+	u32 addr;				/* Up to 63 addr/len pairs possible	*/
+	u32 length;				/* Set LAST_FRAG to indicate last pair	*/
 };
 
 /* Misc. definitions */
 
-#define NUM_RX_DESC 		PKTBUFSRX * 10
-#define NUM_TX_DESC 		1            /* Number of TX descriptors   */
+#define NUM_RX_DESC		PKTBUFSRX * 10
+#define NUM_TX_DESC		1		/* Number of TX descriptors   */
 
 #define TOUT_LOOP		1000000
 
@@ -266,17 +266,17 @@ struct descriptor {			    		/* A generic descriptor. */
 #undef ETH_DEBUG
 
 #ifdef ETH_DEBUG
-#define PRINTF(fmt,args...)     printf (fmt ,##args)
+#define PRINTF(fmt,args...)	printf (fmt ,##args)
 #else
 #define PRINTF(fmt,args...)
 #endif
 
 
-static struct rx_desc_3com *rx_ring;		 	/* RX descriptor ring         		*/
-static struct tx_desc_3com *tx_ring;		 	/* TX descriptor ring         		*/
-static u8 rx_buffer[NUM_RX_DESC][PKTSIZE_ALIGN];	/* storage for the incoming messages 	*/
-static int rx_next = 0;                      		/* RX descriptor ring pointer 		*/
-static int tx_next = 0;                      		/* TX descriptor ring pointer 		*/
+static struct rx_desc_3com *rx_ring;		/* RX descriptor ring		*/
+static struct tx_desc_3com *tx_ring;		/* TX descriptor ring		*/
+static u8 rx_buffer[NUM_RX_DESC][PKTSIZE_ALIGN];/* storage for the incoming messages	*/
+static int rx_next = 0;				/* RX descriptor ring pointer		*/
+static int tx_next = 0;				/* TX descriptor ring pointer		*/
 static int tx_threshold;
 
 static void  init_rx_ring(struct eth_device* dev);
@@ -369,171 +369,163 @@ static int issue_and_wait(struct eth_device* dev, int command)
 	return 0;
 }
 
-/* Determine network media type and set up 3com accordingly           */
+/* Determine network media type and set up 3com accordingly	      */
 /* I think I'm going to start with something known first like 10baseT */
 
-static int auto_negotiate(struct eth_device* dev)
+static int auto_negotiate (struct eth_device *dev)
 {
-    int i;
+	int i;
 
-    EL3WINDOW(dev, 1);
+	EL3WINDOW (dev, 1);
 
-    /* Wait for Auto negotiation to complete */
-    for (i = 0; i <= 1000; i++)
-    {
-	if (ETH_INW(dev, 2) & 0x04)
-	    break;
-	udelay(100);
+	/* Wait for Auto negotiation to complete */
+	for (i = 0; i <= 1000; i++) {
+		if (ETH_INW (dev, 2) & 0x04)
+			break;
+		udelay (100);
 
-	if (i == 1000)
-	{
-	    PRINTF("Error: Auto negotiation failed\n");
-	    return 0;
+		if (i == 1000) {
+			PRINTF ("Error: Auto negotiation failed\n");
+			return 0;
+		}
 	}
-    }
 
 
-    return 1;
+	return 1;
 }
 
-void eth_interrupt(struct eth_device *dev)
+void eth_interrupt (struct eth_device *dev)
 {
-    u16 status = ETH_STATUS(dev);
+	u16 status = ETH_STATUS (dev);
 
-    printf("eth0: status = 0x%04x\n", status);
+	printf ("eth0: status = 0x%04x\n", status);
 
-    if (!(status & IntLatch))
-	return;
+	if (!(status & IntLatch))
+		return;
+
+	if (status & (1 << 6)) {
+		ETH_CMD (dev, AckIntr | (1 << 6));
+		printf ("Acknowledged Interrupt command\n");
+	}
+
+	if (status & DownComplete) {
+		ETH_CMD (dev, AckIntr | DownComplete);
+		printf ("Acknowledged DownComplete\n");
+	}
+
+	if (status & UpComplete) {
+		ETH_CMD (dev, AckIntr | UpComplete);
+		printf ("Acknowledged UpComplete\n");
+	}
 
-    if (status & (1<<6))
-    {
-	ETH_CMD(dev, AckIntr | (1<<6));
-	printf("Acknowledged Interrupt command\n");
-    }
-
-    if (status & DownComplete)
-    {
-	ETH_CMD(dev, AckIntr | DownComplete);
-	printf("Acknowledged DownComplete\n");
-    }
-
-    if (status & UpComplete)
-    {
-	ETH_CMD(dev, AckIntr | UpComplete);
-	printf("Acknowledged UpComplete\n");
-    }
-
-    ETH_CMD(dev, AckIntr | IntLatch);
-    printf("Acknowledged IntLatch\n");
+	ETH_CMD (dev, AckIntr | IntLatch);
+	printf ("Acknowledged IntLatch\n");
 }
 
-int eth_3com_initialize(bd_t *bis)
+int eth_3com_initialize (bd_t * bis)
 {
 	u32 eth_iobase = 0, status;
 	int card_number = 0, ret;
-	struct eth_device* dev;
+	struct eth_device *dev;
 	pci_dev_t devno;
 	char *s;
 
-	s = getenv("3com_base");
+	s = getenv ("3com_base");
 
 	/* Find ethernet controller on the PCI bus */
 
-	if ((devno = pci_find_device(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C905C, 0)) < 0)
-	{
-		PRINTF("Error: Cannot find the ethernet device on the PCI bus\n");
+	if ((devno =
+	     pci_find_device (PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C905C,
+			      0)) < 0) {
+		PRINTF ("Error: Cannot find the ethernet device on the PCI bus\n");
 		goto Done;
 	}
 
-	if (s)
-	{
-	    unsigned long base = atoi(s);
-	    pci_write_config_dword(devno, PCI_BASE_ADDRESS_0, base | 0x01);
+	if (s) {
+		unsigned long base = atoi (s);
+
+		pci_write_config_dword (devno, PCI_BASE_ADDRESS_0,
+					base | 0x01);
 	}
 
-	ret = pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &eth_iobase);
+	ret = pci_read_config_dword (devno, PCI_BASE_ADDRESS_0, &eth_iobase);
 	eth_iobase &= ~0xf;
 
-	PRINTF("eth: 3Com Found at Address: 0x%x\n", eth_iobase);
+	PRINTF ("eth: 3Com Found at Address: 0x%x\n", eth_iobase);
 
-	pci_write_config_dword(devno, PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
+	pci_write_config_dword (devno, PCI_COMMAND,
+				PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
+				PCI_COMMAND_MASTER);
 
-	 /* Check if I/O accesses and Bus Mastering are enabled */
+	/* Check if I/O accesses and Bus Mastering are enabled */
 
-	ret = pci_read_config_dword(devno, PCI_COMMAND, &status);
+	ret = pci_read_config_dword (devno, PCI_COMMAND, &status);
 
-	if (!(status & PCI_COMMAND_IO))
-	{
-		printf("Error: Cannot enable IO access.\n");
+	if (!(status & PCI_COMMAND_IO)) {
+		printf ("Error: Cannot enable IO access.\n");
 		goto Done;
 	}
 
-	if (!(status & PCI_COMMAND_MEMORY))
-	{
-		printf("Error: Cannot enable MEMORY access.\n");
+	if (!(status & PCI_COMMAND_MEMORY)) {
+		printf ("Error: Cannot enable MEMORY access.\n");
 		goto Done;
 	}
 
-	if (!(status & PCI_COMMAND_MASTER))
-	{
-		printf("Error: Cannot enable Bus Mastering.\n");
+	if (!(status & PCI_COMMAND_MASTER)) {
+		printf ("Error: Cannot enable Bus Mastering.\n");
 		goto Done;
 	}
 
-	dev = (struct eth_device*) malloc(sizeof(*dev)); /*struct eth_device)); */
+	dev = (struct eth_device *) malloc (sizeof (*dev));	/*struct eth_device)); */
 
-	sprintf(dev->name, "3Com 3c920c#%d", card_number);
+	sprintf (dev->name, "3Com 3c920c#%d", card_number);
 	dev->iobase = eth_iobase;
-	dev->priv   = (void*) devno;
-	dev->init   = eth_3com_init;
-	dev->halt   = eth_3com_halt;
-	dev->send   = eth_3com_send;
-	dev->recv   = eth_3com_recv;
+	dev->priv = (void *) devno;
+	dev->init = eth_3com_init;
+	dev->halt = eth_3com_halt;
+	dev->send = eth_3com_send;
+	dev->recv = eth_3com_recv;
 
-	eth_register(dev);
+	eth_register (dev);
 
-/* 	{ */
-/* 	    char interrupt; */
-/* 	    devno = pci_find_device(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C905C, 0); */
-/* 	    pci_read_config_byte(devno, PCI_INTERRUPT_LINE, &interrupt); */
+/*	{ */
+/*	    char interrupt; */
+/*	    devno = pci_find_device(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C905C, 0); */
+/*	    pci_read_config_byte(devno, PCI_INTERRUPT_LINE, &interrupt); */
 
-/* 	    printf("Installing eth0 interrupt handler to %d\n", interrupt); */
-/* 	    irq_install_handler(interrupt, eth_interrupt, dev); */
-/* 	} */
+/*	    printf("Installing eth0 interrupt handler to %d\n", interrupt); */
+/*	    irq_install_handler(interrupt, eth_interrupt, dev); */
+/*	} */
 
 	card_number++;
 
 	/* Set the latency timer for value */
-	s = getenv("3com_latency");
-	if (s)
-	{
-	    ret = pci_write_config_byte(devno, PCI_LATENCY_TIMER, (unsigned char)atoi(s));
-	}
-	else ret = pci_write_config_byte(devno, PCI_LATENCY_TIMER, 0x0a);
+	s = getenv ("3com_latency");
+	if (s) {
+		ret = pci_write_config_byte (devno, PCI_LATENCY_TIMER,
+					     (unsigned char) atoi (s));
+	} else
+		ret = pci_write_config_byte (devno, PCI_LATENCY_TIMER, 0x0a);
 
-	read_hw_addr(dev, bis); 				/* get the MAC address from Window 2*/
+	read_hw_addr (dev, bis);	/* get the MAC address from Window 2 */
 
 	/* Reset the ethernet controller */
 
 	PRINTF ("Issuing reset command....\n");
-	if (!issue_and_wait(dev, TotalReset))
-	{
-		printf("Error: Cannot reset ethernet controller.\n");
+	if (!issue_and_wait (dev, TotalReset)) {
+		printf ("Error: Cannot reset ethernet controller.\n");
 		goto Done;
-	}
-	else
+	} else
 		PRINTF ("Ethernet controller reset.\n");
 
 	/* allocate memory for rx and tx rings */
 
-	if(!(rx_ring = memalign(sizeof(struct rx_desc_3com) * NUM_RX_DESC, 16)))
-	{
+	if (!(rx_ring = memalign (sizeof (struct rx_desc_3com) * NUM_RX_DESC, 16))) {
 		PRINTF ("Cannot allocate memory for RX_RING.....\n");
 		goto Done;
 	}
 
-	if (!(tx_ring = memalign(sizeof(struct tx_desc_3com) * NUM_TX_DESC, 16)))
-	{
+	if (!(tx_ring = memalign (sizeof (struct tx_desc_3com) * NUM_TX_DESC, 16))) {
 		PRINTF ("Cannot allocate memory for TX_RING.....\n");
 		goto Done;
 	}
@@ -543,219 +535,208 @@ Done:
 }
 
 
-static int eth_3com_init(struct eth_device* dev, bd_t *bis)
+static int eth_3com_init (struct eth_device *dev, bd_t * bis)
 {
 	int i, status = 0;
 	int tx_cur, loop;
 	u16 status_enable, intr_enable;
 	struct descriptor *ias_cmd;
 
-	/* Determine what type of network the machine is connected to	*/
-	/* presently drops the connect to 10Mbps			*/
+	/* Determine what type of network the machine is connected to   */
+	/* presently drops the connect to 10Mbps                        */
 
-	if (!auto_negotiate(dev))
-	{
-		printf("Error: Cannot determine network media.\n");
+	if (!auto_negotiate (dev)) {
+		printf ("Error: Cannot determine network media.\n");
 		goto Done;
 	}
 
-	issue_and_wait(dev, TxReset);
-	issue_and_wait(dev, RxReset|0x04);
+	issue_and_wait (dev, TxReset);
+	issue_and_wait (dev, RxReset | 0x04);
 
 	/* Switch to register set 7 for normal use. */
-	EL3WINDOW(dev, 7);
+	EL3WINDOW (dev, 7);
 
 	/* Initialize Rx and Tx rings */
 
-	init_rx_ring(dev);
-	purge_tx_ring(dev);
+	init_rx_ring (dev);
+	purge_tx_ring (dev);
 
-	ETH_CMD(dev, SetRxFilter | RxStation | RxBroadcast | RxProm);
+	ETH_CMD (dev, SetRxFilter | RxStation | RxBroadcast | RxProm);
 
-	issue_and_wait(dev,SetTxStart|0x07ff);
+	issue_and_wait (dev, SetTxStart | 0x07ff);
 
 	/* Below sets which indication bits to be seen. */
 
-	status_enable = SetStatusEnb | HostError | DownComplete | UpComplete | (1<<6);
-	ETH_CMD(dev, status_enable);
+	status_enable =
+		SetStatusEnb | HostError | DownComplete | UpComplete | (1 <<
+									6);
+	ETH_CMD (dev, status_enable);
 
 	/* Below sets no bits are to cause an interrupt since this is just polling */
 
-	intr_enable   = SetIntrEnb;
+	intr_enable = SetIntrEnb;
 /*	intr_enable = SetIntrEnb | (1<<9) | (1<<10) | (1<<6); */
-	ETH_CMD(dev, intr_enable);
-	ETH_OUTB(dev, 127, UpPoll);
+	ETH_CMD (dev, intr_enable);
+	ETH_OUTB (dev, 127, UpPoll);
 
 	/* Ack all pending events, and set active indicator mask */
 
-	ETH_CMD(dev, AckIntr | IntLatch | TxAvailable | RxEarly | IntReq);
-	ETH_CMD(dev, intr_enable);
+	ETH_CMD (dev, AckIntr | IntLatch | TxAvailable | RxEarly | IntReq);
+	ETH_CMD (dev, intr_enable);
 
 	/* Tell the adapter where the RX ring is located */
 
-	issue_and_wait(dev,UpStall);				/* Stall and set the UplistPtr 		*/
-	ETH_OUTL(dev, (u32)&rx_ring[rx_next], UpListPtr);
-	ETH_CMD(dev, RxEnable); 				/* Enable the receiver. 		*/
-	issue_and_wait(dev,UpUnstall);
+	issue_and_wait (dev, UpStall);	/* Stall and set the UplistPtr          */
+	ETH_OUTL (dev, (u32) & rx_ring[rx_next], UpListPtr);
+	ETH_CMD (dev, RxEnable);	/* Enable the receiver.         */
+	issue_and_wait (dev, UpUnstall);
 
 	/* Send the Individual Address Setup frame */
 
-	tx_cur       = tx_next;
-	tx_next      = ((tx_next+1) % NUM_TX_DESC);
+	tx_cur = tx_next;
+	tx_next = ((tx_next + 1) % NUM_TX_DESC);
 
-	ias_cmd             = (struct descriptor *)&tx_ring[tx_cur];
-	ias_cmd->status     = cpu_to_le32(1<<31);		/* set DnIndicate bit. 			*/
-	ias_cmd->next       = 0;
-	ias_cmd->addr       = cpu_to_le32((u32)&bis->bi_enetaddr[0]);
-	ias_cmd->length     = cpu_to_le32(6 | LAST_FRAG);
+	ias_cmd = (struct descriptor *) &tx_ring[tx_cur];
+	ias_cmd->status = cpu_to_le32 (1 << 31);	/* set DnIndicate bit.                  */
+	ias_cmd->next = 0;
+	ias_cmd->addr = cpu_to_le32 ((u32) & bis->bi_enetaddr[0]);
+	ias_cmd->length = cpu_to_le32 (6 | LAST_FRAG);
 
 	/* Tell the adapter where the TX ring is located */
 
-	ETH_CMD(dev, TxEnable); 				/* Enable transmitter. 			*/
-	issue_and_wait(dev, DownStall);				/* Stall and set the DownListPtr. 	*/
-	ETH_OUTL(dev, (u32)&tx_ring[tx_cur], DownListPtr);
-	issue_and_wait(dev, DownUnstall);
-	for (i=0; !(ETH_STATUS(dev) & DownComplete); i++)
-	{
-		if (i >= TOUT_LOOP)
-		{
-			PRINTF("TX Ring status (Init):  0x%4x\n", le32_to_cpu(tx_ring[tx_cur].status));
-			PRINTF("ETH_STATUS: 0x%x\n", ETH_STATUS(dev));
+	ETH_CMD (dev, TxEnable);	/* Enable transmitter.                  */
+	issue_and_wait (dev, DownStall);	/* Stall and set the DownListPtr.       */
+	ETH_OUTL (dev, (u32) & tx_ring[tx_cur], DownListPtr);
+	issue_and_wait (dev, DownUnstall);
+	for (i = 0; !(ETH_STATUS (dev) & DownComplete); i++) {
+		if (i >= TOUT_LOOP) {
+			PRINTF ("TX Ring status (Init):	0x%4x\n",
+				le32_to_cpu (tx_ring[tx_cur].status));
+			PRINTF ("ETH_STATUS: 0x%x\n", ETH_STATUS (dev));
 			goto Done;
 		}
 	}
-	if (ETH_STATUS(dev) & DownComplete)			/* If DownLoad Complete ACK the bit 	*/
-	{
-		ETH_CMD(dev, AckIntr | DownComplete);		/* acknowledge the indication bit	*/
-		issue_and_wait(dev, DownStall);			/* stall and clear DownListPtr 		*/
-		ETH_OUTL(dev, 0, DownListPtr);
-		issue_and_wait(dev, DownUnstall);
+	if (ETH_STATUS (dev) & DownComplete) {	/* If DownLoad Complete ACK the bit       */
+		ETH_CMD (dev, AckIntr | DownComplete);	/* acknowledge the indication bit       */
+		issue_and_wait (dev, DownStall);	/* stall and clear DownListPtr          */
+		ETH_OUTL (dev, 0, DownListPtr);
+		issue_and_wait (dev, DownUnstall);
 	}
 	status = 1;
-
 Done:
 	return status;
 }
 
-int eth_3com_send(struct eth_device* dev, volatile void *packet, int length)
+int eth_3com_send (struct eth_device *dev, volatile void *packet, int length)
 {
 	int i, status = 0;
 	int tx_cur;
 
-	if (length <= 0)
-	{
-		PRINTF("eth: bad packet size: %d\n", length);
+	if (length <= 0) {
+		PRINTF ("eth: bad packet size: %d\n", length);
 		goto Done;
 	}
 
-	tx_cur  = tx_next;
-	tx_next = (tx_next+1) % NUM_TX_DESC;
+	tx_cur = tx_next;
+	tx_next = (tx_next + 1) % NUM_TX_DESC;
 
-	tx_ring[tx_cur].status  = cpu_to_le32(1<<31);		/* set DnIndicate bit 			*/
-	tx_ring[tx_cur].next    = 0;
-	tx_ring[tx_cur].addr    = cpu_to_le32(((u32) packet));
-	tx_ring[tx_cur].length  = cpu_to_le32(length | LAST_FRAG);
+	tx_ring[tx_cur].status = cpu_to_le32 (1 << 31);	/* set DnIndicate bit                   */
+	tx_ring[tx_cur].next = 0;
+	tx_ring[tx_cur].addr = cpu_to_le32 (((u32) packet));
+	tx_ring[tx_cur].length = cpu_to_le32 (length | LAST_FRAG);
 
 	/* Send the packet */
 
-	issue_and_wait(dev, DownStall);				/* stall and set the DownListPtr 	*/
-	ETH_OUTL(dev, (u32) &tx_ring[tx_cur], DownListPtr);
-	issue_and_wait(dev, DownUnstall);
+	issue_and_wait (dev, DownStall);	/* stall and set the DownListPtr        */
+	ETH_OUTL (dev, (u32) & tx_ring[tx_cur], DownListPtr);
+	issue_and_wait (dev, DownUnstall);
 
-	for (i=0; !(ETH_STATUS(dev) & DownComplete); i++)
-	{
-		if (i >= TOUT_LOOP)
-		{
-			PRINTF("TX Ring status (send): 0x%4x\n", le32_to_cpu(tx_ring[tx_cur].status));
+	for (i = 0; !(ETH_STATUS (dev) & DownComplete); i++) {
+		if (i >= TOUT_LOOP) {
+			PRINTF ("TX Ring status (send): 0x%4x\n",
+				le32_to_cpu (tx_ring[tx_cur].status));
 			goto Done;
 		}
 	}
-	if (ETH_STATUS(dev) & DownComplete)			/* If DownLoad Complete ACK the bit 	*/
-	{
-		ETH_CMD(dev, AckIntr | DownComplete);		/* acknowledge the indication bit	*/
-		issue_and_wait(dev, DownStall);			/* stall and clear DownListPtr 		*/
-		ETH_OUTL(dev, 0, DownListPtr);
-		issue_and_wait(dev, DownUnstall);
+	if (ETH_STATUS (dev) & DownComplete) {	/* If DownLoad Complete ACK the bit       */
+		ETH_CMD (dev, AckIntr | DownComplete);	/* acknowledge the indication bit       */
+		issue_and_wait (dev, DownStall);	/* stall and clear DownListPtr          */
+		ETH_OUTL (dev, 0, DownListPtr);
+		issue_and_wait (dev, DownUnstall);
 	}
-	status=1;
- Done:
+	status = 1;
+Done:
 	return status;
 }
 
-void PrintPacket (uchar *packet, int length)
+void PrintPacket (uchar * packet, int length)
 {
-int loop;
-uchar *ptr;
+	int loop;
+	uchar *ptr;
 
 	printf ("Printing packet of length %x.\n\n", length);
 	ptr = packet;
-	for (loop = 1; loop <= length; loop++)
-	{
+	for (loop = 1; loop <= length; loop++) {
 		printf ("%2x ", *ptr++);
-		if ((loop % 40)== 0)
+		if ((loop % 40) == 0)
 			printf ("\n");
 	}
 }
 
-int eth_3com_recv(struct eth_device* dev)
+int eth_3com_recv (struct eth_device *dev)
 {
 	u16 stat = 0;
 	u32 status;
 	int rx_prev, length = 0;
 
-	while (!(ETH_STATUS(dev) & UpComplete))			/* wait on receipt of packet 	*/
+	while (!(ETH_STATUS (dev) & UpComplete))	/* wait on receipt of packet        */
 		;
 
-	status = le32_to_cpu(rx_ring[rx_next].status);		/* packet status		*/
+	status = le32_to_cpu (rx_ring[rx_next].status);	/* packet status                */
 
-	while (status & (1<<15))
-	{
+	while (status & (1 << 15)) {
 		/* A packet has been received */
 
-		if (status & (1<<15))
-		{
+		if (status & (1 << 15)) {
 			/* A valid frame received  */
 
-			length = le32_to_cpu(rx_ring[rx_next].status) & 0x1fff;		/* length is in bits 0 - 12 	*/
+			length = le32_to_cpu (rx_ring[rx_next].status) & 0x1fff;	/* length is in bits 0 - 12     */
 
 			/* Pass the packet up to the protocol layers */
 
-			NetReceive((uchar *)le32_to_cpu(rx_ring[rx_next].addr), length);
-			rx_ring[rx_next].status = 0;					/* clear the status word 	*/
-			ETH_CMD(dev, AckIntr | UpComplete);
-			issue_and_wait(dev, UpUnstall);
-		}
-		else
-		if (stat & HostError)
-		{
+			NetReceive ((uchar *)
+				    le32_to_cpu (rx_ring[rx_next].addr),
+				    length);
+			rx_ring[rx_next].status = 0;	/* clear the status word        */
+			ETH_CMD (dev, AckIntr | UpComplete);
+			issue_and_wait (dev, UpUnstall);
+		} else if (stat & HostError) {
 			/* There was an error */
 
-			printf("Rx error status:  0x%4x\n", stat);
-			init_rx_ring(dev);
+			printf ("Rx error status:  0x%4x\n", stat);
+			init_rx_ring (dev);
 			goto Done;
 		}
 
 		rx_prev = rx_next;
 		rx_next = (rx_next + 1) % NUM_RX_DESC;
-		stat = ETH_STATUS(dev);					/* register status 	*/
-		status = le32_to_cpu(rx_ring[rx_next].status);		/* packet status 	*/
+		stat = ETH_STATUS (dev);	/* register status      */
+		status = le32_to_cpu (rx_ring[rx_next].status);	/* packet status        */
 	}
-
 Done:
 	return length;
 }
 
-void eth_3com_halt(struct eth_device* dev)
+void eth_3com_halt (struct eth_device *dev)
 {
-	if (!(dev->iobase))
-	{
+	if (!(dev->iobase)) {
 		goto Done;
 	}
 
-	issue_and_wait(dev, DownStall);		/* shut down transmit and receive */
-	issue_and_wait(dev, UpStall);
-	issue_and_wait(dev, RxDisable);
-	issue_and_wait(dev, TxDisable);
+	issue_and_wait (dev, DownStall);	/* shut down transmit and receive */
+	issue_and_wait (dev, UpStall);
+	issue_and_wait (dev, RxDisable);
+	issue_and_wait (dev, TxDisable);
 
 /*	free(tx_ring);				/###* release memory allocated to the DPD and UPD rings */
 /*	free(rx_ring); */
@@ -764,41 +745,41 @@ Done:
 	return;
 }
 
-static void init_rx_ring(struct eth_device* dev)
+static void init_rx_ring (struct eth_device *dev)
 {
 	int i;
 
-	PRINTF("Initializing rx_ring. rx_buffer = %p\n", rx_buffer);
-	issue_and_wait(dev, UpStall);
+	PRINTF ("Initializing rx_ring. rx_buffer = %p\n", rx_buffer);
+	issue_and_wait (dev, UpStall);
 
-	for (i = 0; i < NUM_RX_DESC; i++)
-	{
-		rx_ring[i].next    = cpu_to_le32(((u32) &rx_ring[(i+1) % NUM_RX_DESC]));
-		rx_ring[i].status  = 0;
-		rx_ring[i].addr    = cpu_to_le32(((u32) &rx_buffer[i][0]));
-		rx_ring[i].length  = cpu_to_le32(PKTSIZE_ALIGN | LAST_FRAG);
+	for (i = 0; i < NUM_RX_DESC; i++) {
+		rx_ring[i].next =
+			cpu_to_le32 (((u32) &
+				      rx_ring[(i + 1) % NUM_RX_DESC]));
+		rx_ring[i].status = 0;
+		rx_ring[i].addr = cpu_to_le32 (((u32) & rx_buffer[i][0]));
+		rx_ring[i].length = cpu_to_le32 (PKTSIZE_ALIGN | LAST_FRAG);
 	}
 	rx_next = 0;
 }
 
-static void purge_tx_ring(struct eth_device* dev)
+static void purge_tx_ring (struct eth_device *dev)
 {
 	int i;
 
-	PRINTF("Purging tx_ring.\n");
+	PRINTF ("Purging tx_ring.\n");
 
-	tx_next      = 0;
+	tx_next = 0;
 
-	for (i = 0; i < NUM_TX_DESC; i++)
-	{
-		tx_ring[i].next    = 0;
-		tx_ring[i].status  = 0;
-		tx_ring[i].addr    = 0;
-		tx_ring[i].length  = 0;
+	for (i = 0; i < NUM_TX_DESC; i++) {
+		tx_ring[i].next = 0;
+		tx_ring[i].status = 0;
+		tx_ring[i].addr = 0;
+		tx_ring[i].length = 0;
 	}
 }
 
-static void read_hw_addr(struct eth_device* dev, bd_t *bis)
+static void read_hw_addr (struct eth_device *dev, bd_t * bis)
 {
 	u8 hw_addr[ETH_ALEN];
 	unsigned int eeprom[0x40];
@@ -807,77 +788,77 @@ static void read_hw_addr(struct eth_device* dev, bd_t *bis)
 
 	/* Read the station address from the EEPROM. */
 
-	EL3WINDOW(dev, 0);
-	for (i = 0; i < 0x40; i++)
-	{
-		ETH_OUTW(dev, EEPROM_Read + i, Wn0EepromCmd);
+	EL3WINDOW (dev, 0);
+	for (i = 0; i < 0x40; i++) {
+		ETH_OUTW (dev, EEPROM_Read + i, Wn0EepromCmd);
 		/* Pause for at least 162 us. for the read to take place. */
-		for (timer = 10; timer >= 0; timer--)
-		{
-			udelay(162);
-			if ((ETH_INW(dev, Wn0EepromCmd) & 0x8000) == 0)
+		for (timer = 10; timer >= 0; timer--) {
+			udelay (162);
+			if ((ETH_INW (dev, Wn0EepromCmd) & 0x8000) == 0)
 				break;
 		}
-		eeprom[i] = ETH_INW(dev, Wn0EepromData);
+		eeprom[i] = ETH_INW (dev, Wn0EepromData);
 	}
 
 	/* Checksum calculation.  I'm not sure about this part and there seems to be a bug on the 3com side of things */
 
 	for (i = 0; i < 0x21; i++)
-		checksum  ^= eeprom[i];
+		checksum ^= eeprom[i];
 	checksum = (checksum ^ (checksum >> 8)) & 0xff;
 
 	if (checksum != 0xbb)
-		printf(" *** INVALID EEPROM CHECKSUM %4.4x *** \n", checksum);
+		printf (" *** INVALID EEPROM CHECKSUM %4.4x *** \n",
+			checksum);
 
-	for (i = 0, j = 0; i < 3; i++)
-	{
-		hw_addr[j++] = (u8)((eeprom[i+10] >> 8) & 0xff);
-		hw_addr[j++] = (u8)(eeprom[i+10] & 0xff);
+	for (i = 0, j = 0; i < 3; i++) {
+		hw_addr[j++] = (u8) ((eeprom[i + 10] >> 8) & 0xff);
+		hw_addr[j++] = (u8) (eeprom[i + 10] & 0xff);
 	}
 
 	/*  MAC Address is in window 2, write value from EEPROM to window 2 */
 
-	EL3WINDOW(dev, 2);
+	EL3WINDOW (dev, 2);
 	for (i = 0; i < 6; i++)
-		ETH_OUTB(dev, hw_addr[i], i);
+		ETH_OUTB (dev, hw_addr[i], i);
 
-	for (j = 0; j < ETH_ALEN; j+=2)
-	{
-		hw_addr[j]   = (u8)(ETH_INW(dev, j) & 0xff);
-		hw_addr[j+1] = (u8)((ETH_INW(dev, j) >> 8) & 0xff);
+	for (j = 0; j < ETH_ALEN; j += 2) {
+		hw_addr[j] = (u8) (ETH_INW (dev, j) & 0xff);
+		hw_addr[j + 1] = (u8) ((ETH_INW (dev, j) >> 8) & 0xff);
 	}
 
-	for (i=0;i<ETH_ALEN;i++)
-	{
-		if (hw_addr[i] != bis->bi_enetaddr[i])
-		{
-/* 			printf("Warning: HW address don't match:\n"); */
-/* 			printf("Address in 3Com Window 2 is         " */
-/* 			       "%02X:%02X:%02X:%02X:%02X:%02X\n", */
-/* 			       hw_addr[0], hw_addr[1], hw_addr[2], */
-/* 			       hw_addr[3], hw_addr[4], hw_addr[5]); */
-/* 			printf("Address used by U-Boot is " */
-/* 			       "%02X:%02X:%02X:%02X:%02X:%02X\n", */
-/* 			       bis->bi_enetaddr[0], bis->bi_enetaddr[1],  */
-/* 			       bis->bi_enetaddr[2], bis->bi_enetaddr[3],  */
-/* 			       bis->bi_enetaddr[4], bis->bi_enetaddr[5]); */
-/* 			goto Done; */
-		    char buffer[256];
-		    if (bis->bi_enetaddr[0] == 0 && bis->bi_enetaddr[1] == 0 &&
-			bis->bi_enetaddr[2] == 0 && bis->bi_enetaddr[3] == 0 &&
-			bis->bi_enetaddr[4] == 0 && bis->bi_enetaddr[5] == 0)
-		    {
-
-			sprintf(buffer, "%02X:%02X:%02X:%02X:%02X:%02X",
-				hw_addr[0], hw_addr[1], hw_addr[2],
-				hw_addr[3], hw_addr[4], hw_addr[5]);
-			setenv("ethaddr", buffer);
-		    }
+	for (i = 0; i < ETH_ALEN; i++) {
+		if (hw_addr[i] != bis->bi_enetaddr[i]) {
+/*			printf("Warning: HW address don't match:\n"); */
+/*			printf("Address in 3Com Window 2 is	    " */
+/*			       "%02X:%02X:%02X:%02X:%02X:%02X\n", */
+/*			       hw_addr[0], hw_addr[1], hw_addr[2], */
+/*			       hw_addr[3], hw_addr[4], hw_addr[5]); */
+/*			printf("Address used by U-Boot is " */
+/*			       "%02X:%02X:%02X:%02X:%02X:%02X\n", */
+/*			       bis->bi_enetaddr[0], bis->bi_enetaddr[1],  */
+/*			       bis->bi_enetaddr[2], bis->bi_enetaddr[3],  */
+/*			       bis->bi_enetaddr[4], bis->bi_enetaddr[5]); */
+/*			goto Done; */
+			char buffer[256];
+
+			if (bis->bi_enetaddr[0] == 0
+			    && bis->bi_enetaddr[1] == 0
+			    && bis->bi_enetaddr[2] == 0
+			    && bis->bi_enetaddr[3] == 0
+			    && bis->bi_enetaddr[4] == 0
+			    && bis->bi_enetaddr[5] == 0) {
+
+				sprintf (buffer,
+					 "%02X:%02X:%02X:%02X:%02X:%02X",
+					 hw_addr[0], hw_addr[1], hw_addr[2],
+					 hw_addr[3], hw_addr[4], hw_addr[5]);
+				setenv ("ethaddr", buffer);
+			}
 		}
 	}
 
-	for(i=0; i<ETH_ALEN; i++) dev->enetaddr[i] = hw_addr[i];
+	for (i = 0; i < ETH_ALEN; i++)
+		dev->enetaddr[i] = hw_addr[i];
 
 Done:
 	return;
diff --git a/board/MAI/AmigaOneG3SE/interrupts.c b/board/MAI/AmigaOneG3SE/interrupts.c
index 5b314a8b71..86b44150d5 100644
--- a/board/MAI/AmigaOneG3SE/interrupts.c
+++ b/board/MAI/AmigaOneG3SE/interrupts.c
@@ -176,9 +176,9 @@ external_interrupt(struct pt_regs *regs)
 	else {
 		PRINTF ("\nBogus External Interrupt IRQ %d\n", irq);
 		/*
-	 	* turn off the bogus interrupt, otherwise it
-	 	* might repeat forever
-	 	*/
+		* turn off the bogus interrupt, otherwise it
+		* might repeat forever
+		*/
 		unmask = 0;
 	}
 
diff --git a/board/MAI/AmigaOneG3SE/ps2kbd.c b/board/MAI/AmigaOneG3SE/ps2kbd.c
index cf4f4d0e3d..39d8149632 100644
--- a/board/MAI/AmigaOneG3SE/ps2kbd.c
+++ b/board/MAI/AmigaOneG3SE/ps2kbd.c
@@ -58,7 +58,7 @@ void i8259_unmask_irq(unsigned int irq);
 #define KBD_STAT_KOBF		0x01
 #define KBD_STAT_IBF		0x02
 #define KBD_STAT_SYS		0x04
-#define KBD_STAT_CD			0x08
+#define KBD_STAT_CD		0x08
 #define KBD_STAT_LOCK		0x10
 #define KBD_STAT_MOBF		0x20
 #define KBD_STAT_TI_OUT	0x40
@@ -71,50 +71,50 @@ void i8259_unmask_irq(unsigned int irq);
  *	Keyboard Controller Commands
  */
 
-#define KBD_CCMD_READ_MODE			0x20	/* Read mode bits */
-#define KBD_CCMD_WRITE_MODE			0x60	/* Write mode bits */
-#define KBD_CCMD_GET_VERSION		0xA1	/* Get controller version */
+#define KBD_CCMD_READ_MODE	0x20	/* Read mode bits */
+#define KBD_CCMD_WRITE_MODE	0x60	/* Write mode bits */
+#define KBD_CCMD_GET_VERSION	0xA1	/* Get controller version */
 #define KBD_CCMD_MOUSE_DISABLE	0xA7	/* Disable mouse interface */
-#define KBD_CCMD_MOUSE_ENABLE		0xA8	/* Enable mouse interface */
-#define KBD_CCMD_TEST_MOUSE			0xA9	/* Mouse interface test */
-#define KBD_CCMD_SELF_TEST			0xAA	/* Controller self test */
-#define KBD_CCMD_KBD_TEST				0xAB	/* Keyboard interface test */
-#define KBD_CCMD_KBD_DISABLE		0xAD	/* Keyboard interface disable */
-#define KBD_CCMD_KBD_ENABLE			0xAE	/* Keyboard interface enable */
+#define KBD_CCMD_MOUSE_ENABLE	0xA8	/* Enable mouse interface */
+#define KBD_CCMD_TEST_MOUSE	0xA9	/* Mouse interface test */
+#define KBD_CCMD_SELF_TEST	0xAA	/* Controller self test */
+#define KBD_CCMD_KBD_TEST	0xAB	/* Keyboard interface test */
+#define KBD_CCMD_KBD_DISABLE	0xAD	/* Keyboard interface disable */
+#define KBD_CCMD_KBD_ENABLE	0xAE	/* Keyboard interface enable */
 #define KBD_CCMD_WRITE_AUX_OBUF	0xD3    /* Write to output buffer as if
 					   initiated by the auxiliary device */
-#define KBD_CCMD_WRITE_MOUSE		0xD4	/* Write the following byte to the mouse */
+#define KBD_CCMD_WRITE_MOUSE	0xD4	/* Write the following byte to the mouse */
 
 /*
  *	Keyboard Commands
  */
 
-#define KBD_CMD_SET_LEDS				0xED	/* Set keyboard leds */
-#define KBD_CMD_SET_RATE				0xF3	/* Set typematic rate */
-#define KBD_CMD_ENABLE					0xF4	/* Enable scanning */
-#define KBD_CMD_DISABLE					0xF5	/* Disable scanning */
-#define KBD_CMD_RESET						0xFF	/* Reset */
+#define KBD_CMD_SET_LEDS	0xED	/* Set keyboard leds */
+#define KBD_CMD_SET_RATE	0xF3	/* Set typematic rate */
+#define KBD_CMD_ENABLE		0xF4	/* Enable scanning */
+#define KBD_CMD_DISABLE		0xF5	/* Disable scanning */
+#define KBD_CMD_RESET		0xFF	/* Reset */
 
 /*
  *	Keyboard Replies
  */
 
-#define KBD_REPLY_POR						0xAA	/* Power on reset */
-#define KBD_REPLY_ACK						0xFA	/* Command ACK */
-#define KBD_REPLY_RESEND				0xFE	/* Command NACK, send the cmd again */
+#define KBD_REPLY_POR		0xAA	/* Power on reset */
+#define KBD_REPLY_ACK		0xFA	/* Command ACK */
+#define KBD_REPLY_RESEND	0xFE	/* Command NACK, send the cmd again */
 
 /*
  *	Status Register Bits
  */
 
-#define KBD_STAT_OBF 						0x01	/* Keyboard output buffer full */
-#define KBD_STAT_IBF 						0x02	/* Keyboard input buffer full */
-#define KBD_STAT_SELFTEST				0x04	/* Self test successful */
-#define KBD_STAT_CMD						0x08	/* Last write was a command write (0=data) */
-#define KBD_STAT_UNLOCKED				0x10	/* Zero if keyboard locked */
-#define KBD_STAT_MOUSE_OBF			0x20	/* Mouse output buffer full */
-#define KBD_STAT_GTO 						0x40	/* General receive/xmit timeout */
-#define KBD_STAT_PERR 					0x80	/* Parity error */
+#define KBD_STAT_OBF		0x01	/* Keyboard output buffer full */
+#define KBD_STAT_IBF		0x02	/* Keyboard input buffer full */
+#define KBD_STAT_SELFTEST	0x04	/* Self test successful */
+#define KBD_STAT_CMD		0x08	/* Last write was a command write (0=data) */
+#define KBD_STAT_UNLOCKED	0x10	/* Zero if keyboard locked */
+#define KBD_STAT_MOUSE_OBF	0x20	/* Mouse output buffer full */
+#define KBD_STAT_GTO		0x40	/* General receive/xmit timeout */
+#define KBD_STAT_PERR		0x80	/* Parity error */
 
 #define AUX_STAT_OBF (KBD_STAT_OBF | KBD_STAT_MOUSE_OBF)
 
@@ -122,24 +122,24 @@ void i8259_unmask_irq(unsigned int irq);
  *	Controller Mode Register Bits
  */
 
-#define KBD_MODE_KBD_INT				0x01	/* Keyboard data generate IRQ1 */
-#define KBD_MODE_MOUSE_INT			0x02	/* Mouse data generate IRQ12 */
-#define KBD_MODE_SYS 						0x04	/* The system flag (?) */
-#define KBD_MODE_NO_KEYLOCK			0x08	/* The keylock doesn't affect the keyboard if set */
-#define KBD_MODE_DISABLE_KBD		0x10	/* Disable keyboard interface */
+#define KBD_MODE_KBD_INT	0x01	/* Keyboard data generate IRQ1 */
+#define KBD_MODE_MOUSE_INT	0x02	/* Mouse data generate IRQ12 */
+#define KBD_MODE_SYS		0x04	/* The system flag (?) */
+#define KBD_MODE_NO_KEYLOCK	0x08	/* The keylock doesn't affect the keyboard if set */
+#define KBD_MODE_DISABLE_KBD	0x10	/* Disable keyboard interface */
 #define KBD_MODE_DISABLE_MOUSE	0x20	/* Disable mouse interface */
-#define KBD_MODE_KCC 						0x40	/* Scan code conversion to PC format */
-#define KBD_MODE_RFU						0x80
+#define KBD_MODE_KCC		0x40	/* Scan code conversion to PC format */
+#define KBD_MODE_RFU		0x80
 
 
-#define KDB_DATA_PORT			0x60
+#define KDB_DATA_PORT		0x60
 #define KDB_COMMAND_PORT	0x64
 
-#define 	LED_SCR		0x01	/* scroll lock led */
-#define 	LED_CAP		0x04	/* caps lock led */
-#define 	LED_NUM		0x02	/* num lock led */
+#define	LED_SCR			0x01	/* scroll lock led */
+#define	LED_CAP			0x04	/* caps lock led */
+#define	LED_NUM			0x02	/* num lock led */
 
-#define 	KBD_BUFFER_LEN 0x20  /* size of the keyboardbuffer */
+#define	KBD_BUFFER_LEN		0x20	/* size of the keyboardbuffer */
 
 
 static volatile char kbd_buffer[KBD_BUFFER_LEN];
@@ -194,21 +194,22 @@ static unsigned char kbd_ctrl_xlate[] = {
  * Init
  ******************************************************************/
 
-int isa_kbd_init(void)
+int isa_kbd_init (void)
 {
-	char* result;
-	result=kbd_initialize();
-	if (result != NULL)
-	{
-	    result = kbd_initialize();
+	char *result;
+
+	result = kbd_initialize ();
+	if (result != NULL) {
+		result = kbd_initialize ();
 	}
-	if(result==NULL) {
-		printf("AT Keyboard initialized\n");
-		irq_install_handler(KBD_INTERRUPT, (interrupt_handler_t *)kbd_interrupt, NULL);
+	if (result == NULL) {
+		printf ("AT Keyboard initialized\n");
+		irq_install_handler (KBD_INTERRUPT,
+				     (interrupt_handler_t *) kbd_interrupt,
+				     NULL);
 		return (1);
-	}
-	else {
-		printf("%s\n",result);
+	} else {
+		printf ("%s\n", result);
 		return (-1);
 	}
 }
@@ -225,20 +226,20 @@ int overwrite_console (void)
 int drv_isa_kbd_init (void)
 {
 	int error;
-  	device_t kbddev ;
+	device_t kbddev ;
 	char *stdinname  = getenv ("stdin");
 
 	if(isa_kbd_init()==-1)
 		return -1;
-  	memset (&kbddev, 0, sizeof(kbddev));
-  	strcpy(kbddev.name, DEVNAME);
-  	kbddev.flags =  DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM;
-  	kbddev.putc = NULL ;
+	memset (&kbddev, 0, sizeof(kbddev));
+	strcpy(kbddev.name, DEVNAME);
+	kbddev.flags =  DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM;
+	kbddev.putc = NULL ;
 	kbddev.puts = NULL ;
 	kbddev.getc = kbd_getc ;
 	kbddev.tstc = kbd_testc ;
 
- 	error = device_register (&kbddev);
+	error = device_register (&kbddev);
 	if(error==0) {
 		/* check if this is the standard input device */
 		if(strcmp(stdinname,DEVNAME)==0) {
@@ -301,7 +302,6 @@ int kbd_getc(void)
 
 }
 
-
 /* set LEDs */
 
 void kbd_set_leds(void)
@@ -322,140 +322,139 @@ void kbd_set_leds(void)
 	kbd_send_data(leds);
 }
 
-
-void handle_keyboard_event(unsigned char scancode)
+void handle_keyboard_event (unsigned char scancode)
 {
 	unsigned char keycode;
 
 	/*  Convert scancode to keycode */
-	PRINTF("scancode %x\n",scancode);
-	if(scancode==0xe0) {
-		e0=1; /* special charakters */
+	PRINTF ("scancode %x\n", scancode);
+	if (scancode == 0xe0) {
+		e0 = 1;		/* special charakters */
 		return;
 	}
-	if(e0==1) {
-		e0=0; /* delete flag */
-		if(!(	((scancode&0x7F)==0x38)|| /* the right ctrl key */
-			((scancode&0x7F)==0x1D)|| /* the right alt key */
-			((scancode&0x7F)==0x35)||	/* the right '/' key */
-			((scancode&0x7F)==0x1C)||  /* the right enter key */
-			((scancode)==0x48)|| /* arrow up */
-			((scancode)==0x50)|| /* arrow down */
-			((scancode)==0x4b)|| /* arrow left */
-			((scancode)==0x4d)))  /* arrow right */
+	if (e0 == 1) {
+		e0 = 0;		/* delete flag */
+		if (!(((scancode & 0x7F) == 0x38) ||	/* the right ctrl key */
+		      ((scancode & 0x7F) == 0x1D) ||	/* the right alt key */
+		      ((scancode & 0x7F) == 0x35) ||	/* the right '/' key */
+		      ((scancode & 0x7F) == 0x1C) ||	/* the right enter key */
+		      ((scancode) == 0x48) ||	/* arrow up */
+		      ((scancode) == 0x50) ||	/* arrow down */
+		      ((scancode) == 0x4b) ||	/* arrow left */
+		      ((scancode) == 0x4d)))
+			/* arrow right */
 			/* we swallow unknown e0 codes */
 			return;
 	}
 	/* special cntrl keys */
-	switch(scancode)
-	{
+	switch (scancode) {
 	case 0x48:
-	    kbd_put_queue(27);
-	    kbd_put_queue(91);
-	    kbd_put_queue('A');
-	    return;
+		kbd_put_queue (27);
+		kbd_put_queue (91);
+		kbd_put_queue ('A');
+		return;
 	case 0x50:
-	    kbd_put_queue(27);
-	    kbd_put_queue(91);
-	    kbd_put_queue('B');
-	    return;
+		kbd_put_queue (27);
+		kbd_put_queue (91);
+		kbd_put_queue ('B');
+		return;
 	case 0x4b:
-	    kbd_put_queue(27);
-	    kbd_put_queue(91);
-	    kbd_put_queue('D');
-	    return;
+		kbd_put_queue (27);
+		kbd_put_queue (91);
+		kbd_put_queue ('D');
+		return;
 	case 0x4D:
-	    kbd_put_queue(27);
-	    kbd_put_queue(91);
-	    kbd_put_queue('C');
-	    return;
-	case 0x58: /* F12 key */
-	    if (ctrl == 1)
-	    {
-		extern int console_changed;
-		setenv("stdin", DEVNAME);
-		setenv("stdout", "vga");
-		console_changed = 1;
-	    }
-	    return;
+		kbd_put_queue (27);
+		kbd_put_queue (91);
+		kbd_put_queue ('C');
+		return;
+	case 0x58:		/* F12 key */
+		if (ctrl == 1) {
+			extern int console_changed;
+
+			setenv ("stdin", DEVNAME);
+			setenv ("stdout", "vga");
+			console_changed = 1;
+		}
+		return;
 	case 0x2A:
-		case 0x36: /* shift pressed */
-			shift=1;
-			return; /* do nothing else */
-		case 0xAA:
-		case 0xB6: /* shift released */
-			shift=0;
-			return; /* do nothing else */
-		case 0x38: /* alt pressed */
-			alt=1;
-			return; /* do nothing else */
-		case 0xB8: /* alt released */
-			alt=0;
-			return; /* do nothing else */
-		case 0x1d: /* ctrl pressed */
-			ctrl=1;
-			return; /* do nothing else */
-		case 0x9d: /* ctrl released */
-			ctrl=0;
-			return; /* do nothing else */
-		case 0x46: /* scrollock pressed */
-			scroll_lock=~scroll_lock;
-			kbd_set_leds();
-			return; /* do nothing else */
-		case 0x3A: /* capslock pressed */
-			caps_lock=~caps_lock;
-			kbd_set_leds();
-			return;
-		case 0x45: /* numlock pressed */
-			num_lock=~num_lock;
-			kbd_set_leds();
-			return;
-		case 0xC6: /* scroll lock released */
-		case 0xC5: /* num lock released */
-		case 0xBA: /* caps lock released */
-			return; /* just swallow */
+	case 0x36:		/* shift pressed */
+		shift = 1;
+		return;		/* do nothing else */
+	case 0xAA:
+	case 0xB6:		/* shift released */
+		shift = 0;
+		return;		/* do nothing else */
+	case 0x38:		/* alt pressed */
+		alt = 1;
+		return;		/* do nothing else */
+	case 0xB8:		/* alt released */
+		alt = 0;
+		return;		/* do nothing else */
+	case 0x1d:		/* ctrl pressed */
+		ctrl = 1;
+		return;		/* do nothing else */
+	case 0x9d:		/* ctrl released */
+		ctrl = 0;
+		return;		/* do nothing else */
+	case 0x46:		/* scrollock pressed */
+		scroll_lock = ~scroll_lock;
+		kbd_set_leds ();
+		return;		/* do nothing else */
+	case 0x3A:		/* capslock pressed */
+		caps_lock = ~caps_lock;
+		kbd_set_leds ();
+		return;
+	case 0x45:		/* numlock pressed */
+		num_lock = ~num_lock;
+		kbd_set_leds ();
+		return;
+	case 0xC6:		/* scroll lock released */
+	case 0xC5:		/* num lock released */
+	case 0xBA:		/* caps lock released */
+		return;		/* just swallow */
 	}
-	if((scancode&0x80)==0x80) /* key released */
+	if ((scancode & 0x80) == 0x80)	/* key released */
 		return;
 	/* now, decide which table we need */
-	if(scancode > (sizeof(kbd_plain_xlate)/sizeof(kbd_plain_xlate[0]))) { /* scancode not in list */
-		PRINTF("unkown scancode %X\n",scancode);
-		return; /* swallow it */
+	if (scancode > (sizeof (kbd_plain_xlate) / sizeof (kbd_plain_xlate[0]))) {	/* scancode not in list */
+		PRINTF ("unkown scancode %X\n", scancode);
+		return;		/* swallow it */
 	}
 	/* setup plain code first */
-	keycode=kbd_plain_xlate[scancode];
-	if(caps_lock==1) { /* caps_lock is pressed, overwrite plain code */
-		if(scancode > (sizeof(kbd_shift_xlate)/sizeof(kbd_shift_xlate[0]))) { /* scancode not in list */
-			PRINTF("unkown caps-locked scancode %X\n",scancode);
-			return; /* swallow it */
+	keycode = kbd_plain_xlate[scancode];
+	if (caps_lock == 1) {	/* caps_lock is pressed, overwrite plain code */
+		if (scancode > (sizeof (kbd_shift_xlate) / sizeof (kbd_shift_xlate[0]))) {	/* scancode not in list */
+			PRINTF ("unkown caps-locked scancode %X\n", scancode);
+			return;	/* swallow it */
 		}
-		keycode=kbd_shift_xlate[scancode];
-		if(keycode<'A') { /* we only want the alphas capital */
-			keycode=kbd_plain_xlate[scancode];
+		keycode = kbd_shift_xlate[scancode];
+		if (keycode < 'A') {	/* we only want the alphas capital */
+			keycode = kbd_plain_xlate[scancode];
 		}
 	}
-	if(shift==1) { /* shift overwrites caps_lock */
-		if(scancode > (sizeof(kbd_shift_xlate)/sizeof(kbd_shift_xlate[0]))) { /* scancode not in list */
-			PRINTF("unkown shifted scancode %X\n",scancode);
-			return; /* swallow it */
+	if (shift == 1) {	/* shift overwrites caps_lock */
+		if (scancode > (sizeof (kbd_shift_xlate) / sizeof (kbd_shift_xlate[0]))) {	/* scancode not in list */
+			PRINTF ("unkown shifted scancode %X\n", scancode);
+			return;	/* swallow it */
 		}
-		keycode=kbd_shift_xlate[scancode];
+		keycode = kbd_shift_xlate[scancode];
 	}
-	if(ctrl==1) { /* ctrl overwrites caps_lock and shift */
-		if(scancode > (sizeof(kbd_ctrl_xlate)/sizeof(kbd_ctrl_xlate[0]))) { /* scancode not in list */
-			PRINTF("unkown ctrl scancode %X\n",scancode);
-			return; /* swallow it */
+	if (ctrl == 1) {	/* ctrl overwrites caps_lock and shift */
+		if (scancode > (sizeof (kbd_ctrl_xlate) / sizeof (kbd_ctrl_xlate[0]))) {	/* scancode not in list */
+			PRINTF ("unkown ctrl scancode %X\n", scancode);
+			return;	/* swallow it */
 		}
-		keycode=kbd_ctrl_xlate[scancode];
+		keycode = kbd_ctrl_xlate[scancode];
 	}
 	/* check if valid keycode */
-	if(keycode==0xff) {
-		PRINTF("unkown scancode %X\n",scancode);
-		return; /* swallow unknown codes */
+	if (keycode == 0xff) {
+		PRINTF ("unkown scancode %X\n", scancode);
+		return;		/* swallow unknown codes */
 	}
 
-	kbd_put_queue(keycode);
-	PRINTF("%x\n",keycode);
+	kbd_put_queue (keycode);
+	PRINTF ("%x\n", keycode);
 }
 
 /*
@@ -463,34 +462,31 @@ void handle_keyboard_event(unsigned char scancode)
  * appropriate action.
  *
  */
-unsigned char handle_kbd_event(void)
+unsigned char handle_kbd_event (void)
 {
-	unsigned char status = kbd_read_status();
+	unsigned char status = kbd_read_status ();
 	unsigned int work = 10000;
 
 	while ((--work > 0) && (status & KBD_STAT_OBF)) {
 		unsigned char scancode;
 
-		scancode = kbd_read_input();
+		scancode = kbd_read_input ();
 
 		/* Error bytes must be ignored to make the
 		   Synaptics touchpads compaq use work */
 		/* Ignore error bytes */
-		if (!(status & (KBD_STAT_GTO | KBD_STAT_PERR)))
-		{
-			if (status & KBD_STAT_MOUSE_OBF)
-				; /* not supported: handle_mouse_event(scancode); */
+		if (!(status & (KBD_STAT_GTO | KBD_STAT_PERR))) {
+			if (status & KBD_STAT_MOUSE_OBF);	/* not supported: handle_mouse_event(scancode); */
 			else
-				handle_keyboard_event(scancode);
+				handle_keyboard_event (scancode);
 		}
-		status = kbd_read_status();
+		status = kbd_read_status ();
 	}
 	if (!work)
-		PRINTF("pc_keyb: controller jammed (0x%02X).\n", status);
+		PRINTF ("pc_keyb: controller jammed (0x%02X).\n", status);
 	return status;
 }
 
-
 /******************************************************************************
  * Lowlevel Part of keyboard section
  */
@@ -529,90 +525,91 @@ int kbd_read_data(void)
 	return val;
 }
 
-int kbd_wait_for_input(void)
+int kbd_wait_for_input (void)
 {
 	unsigned long timeout;
 	int val;
 
 	timeout = KBD_TIMEOUT;
-	val=kbd_read_data();
-	while(val < 0)
-	{
-		if(timeout--==0)
+	val = kbd_read_data ();
+	while (val < 0) {
+		if (timeout-- == 0)
 			return -1;
-		udelay(1000);
-		val=kbd_read_data();
+		udelay (1000);
+		val = kbd_read_data ();
 	}
 	return val;
 }
 
 
-int kb_wait(void)
+int kb_wait (void)
 {
 	unsigned long timeout = KBC_TIMEOUT * 10;
 
 	do {
-		unsigned char status = handle_kbd_event();
+		unsigned char status = handle_kbd_event ();
+
 		if (!(status & KBD_STAT_IBF))
-			return 0; /* ok */
-		udelay(1000);
+			return 0;	/* ok */
+		udelay (1000);
 		timeout--;
 	} while (timeout);
 	return 1;
 }
 
-void kbd_write_command_w(int data)
+void kbd_write_command_w (int data)
 {
-	if(kb_wait())
-		PRINTF("timeout in kbd_write_command_w\n");
-	kbd_write_command(data);
+	if (kb_wait ())
+		PRINTF ("timeout in kbd_write_command_w\n");
+	kbd_write_command (data);
 }
 
-void kbd_write_output_w(int data)
+void kbd_write_output_w (int data)
 {
-	if(kb_wait())
-		PRINTF("timeout in kbd_write_output_w\n");
-	kbd_write_output(data);
+	if (kb_wait ())
+		PRINTF ("timeout in kbd_write_output_w\n");
+	kbd_write_output (data);
 }
 
-void kbd_send_data(unsigned char data)
+void kbd_send_data (unsigned char data)
 {
 	unsigned char status;
-	i8259_mask_irq(KBD_INTERRUPT); /* disable interrupt */
-	kbd_write_output_w(data);
-	status = kbd_wait_for_input();
+
+	i8259_mask_irq (KBD_INTERRUPT);	/* disable interrupt */
+	kbd_write_output_w (data);
+	status = kbd_wait_for_input ();
 	if (status == KBD_REPLY_ACK)
-		i8259_unmask_irq(KBD_INTERRUPT); /* enable interrupt */
+		i8259_unmask_irq (KBD_INTERRUPT);	/* enable interrupt */
 }
 
 
-char * kbd_initialize(void)
+char *kbd_initialize (void)
 {
 	int status;
 
-	in_pointer = 0; /* delete in Buffer */
+	in_pointer = 0;		/* delete in Buffer */
 	out_pointer = 0;
 	/*
 	 * Test the keyboard interface.
 	 * This seems to be the only way to get it going.
 	 * If the test is successful a x55 is placed in the input buffer.
 	 */
-	kbd_write_command_w(KBD_CCMD_SELF_TEST);
-	if (kbd_wait_for_input() != 0x55)
+	kbd_write_command_w (KBD_CCMD_SELF_TEST);
+	if (kbd_wait_for_input () != 0x55)
 		return "Kbd:   failed self test";
 	/*
 	 * Perform a keyboard interface test.  This causes the controller
 	 * to test the keyboard clock and data lines.  The results of the
 	 * test are placed in the input buffer.
 	 */
-	kbd_write_command_w(KBD_CCMD_KBD_TEST);
-	if (kbd_wait_for_input() != 0x00)
+	kbd_write_command_w (KBD_CCMD_KBD_TEST);
+	if (kbd_wait_for_input () != 0x00)
 		return "Kbd:   interface failed self test";
 	/*
 	 * Enable the keyboard by allowing the keyboard clock to run.
 	 */
-	kbd_write_command_w(KBD_CCMD_KBD_ENABLE);
-	status = kbd_wait_for_input();
+	kbd_write_command_w (KBD_CCMD_KBD_ENABLE);
+	status = kbd_wait_for_input ();
 	/*
 	 * Reset keyboard. If the read times out
 	 * then the assumption is that no keyboard is
@@ -622,17 +619,16 @@ char * kbd_initialize(void)
 	 * Set up to try again if the keyboard asks for RESEND.
 	 */
 	do {
-		kbd_write_output_w(KBD_CMD_RESET);
-		status = kbd_wait_for_input();
+		kbd_write_output_w (KBD_CMD_RESET);
+		status = kbd_wait_for_input ();
 		if (status == KBD_REPLY_ACK)
 			break;
-		if (status != KBD_REPLY_RESEND)
-		{
-			PRINTF("status: %X\n",status);
+		if (status != KBD_REPLY_RESEND) {
+			PRINTF ("status: %X\n", status);
 			return "Kbd:   reset failed, no ACK";
 		}
 	} while (1);
-	if (kbd_wait_for_input() != KBD_REPLY_POR)
+	if (kbd_wait_for_input () != KBD_REPLY_POR)
 		return "Kbd:   reset failed, no POR";
 
 	/*
@@ -642,44 +638,43 @@ char * kbd_initialize(void)
 	 * Set up to try again if the keyboard asks for RESEND.
 	 */
 	do {
-		kbd_write_output_w(KBD_CMD_DISABLE);
-		status = kbd_wait_for_input();
+		kbd_write_output_w (KBD_CMD_DISABLE);
+		status = kbd_wait_for_input ();
 		if (status == KBD_REPLY_ACK)
 			break;
 		if (status != KBD_REPLY_RESEND)
 			return "Kbd:   disable keyboard: no ACK";
 	} while (1);
 
-	kbd_write_command_w(KBD_CCMD_WRITE_MODE);
-	kbd_write_output_w(KBD_MODE_KBD_INT
-			      | KBD_MODE_SYS
-			      | KBD_MODE_DISABLE_MOUSE
-			      | KBD_MODE_KCC);
+	kbd_write_command_w (KBD_CCMD_WRITE_MODE);
+	kbd_write_output_w (KBD_MODE_KBD_INT
+			    | KBD_MODE_SYS
+			    | KBD_MODE_DISABLE_MOUSE | KBD_MODE_KCC);
 
 	/* AMCC powerpc portables need this to use scan-code set 1 -- Cort */
-	kbd_write_command_w(KBD_CCMD_READ_MODE);
-	if (!(kbd_wait_for_input() & KBD_MODE_KCC)) {
+	kbd_write_command_w (KBD_CCMD_READ_MODE);
+	if (!(kbd_wait_for_input () & KBD_MODE_KCC)) {
 		/*
 		 * If the controller does not support conversion,
 		 * Set the keyboard to scan-code set 1.
 		 */
-		kbd_write_output_w(0xF0);
-		kbd_wait_for_input();
-		kbd_write_output_w(0x01);
-		kbd_wait_for_input();
+		kbd_write_output_w (0xF0);
+		kbd_wait_for_input ();
+		kbd_write_output_w (0x01);
+		kbd_wait_for_input ();
 	}
-	kbd_write_output_w(KBD_CMD_ENABLE);
-	if (kbd_wait_for_input() != KBD_REPLY_ACK)
+	kbd_write_output_w (KBD_CMD_ENABLE);
+	if (kbd_wait_for_input () != KBD_REPLY_ACK)
 		return "Kbd:   enable keyboard: no ACK";
 
 	/*
 	 * Finally, set the typematic rate to maximum.
 	 */
-	kbd_write_output_w(KBD_CMD_SET_RATE);
-	if (kbd_wait_for_input() != KBD_REPLY_ACK)
+	kbd_write_output_w (KBD_CMD_SET_RATE);
+	if (kbd_wait_for_input () != KBD_REPLY_ACK)
 		return "Kbd:   Set rate: no ACK";
-	kbd_write_output_w(0x00);
-	if (kbd_wait_for_input() != KBD_REPLY_ACK)
+	kbd_write_output_w (0x00);
+	if (kbd_wait_for_input () != KBD_REPLY_ACK)
 		return "Kbd:   Set rate: no ACK";
 	return NULL;
 }
diff --git a/board/MAI/AmigaOneG3SE/start.txt b/board/MAI/AmigaOneG3SE/start.txt
index e4214622ce..2526ed24ae 100644
--- a/board/MAI/AmigaOneG3SE/start.txt
+++ b/board/MAI/AmigaOneG3SE/start.txt
@@ -39,11 +39,11 @@
 
 	DIM0_TIM_CTL_0 = 0x737d737d             (0xc9)
 		      /* DRAM timing control for dimm0 & dimm1; set wait one clock	*/
-		      /* cycle for next data access 					*/
+		      /* cycle for next data access					*/
 
 	DIM2_TIM_CTL_0 = 0x737d737d             (0xca)
 		      /* DRAM timing control for dimm2 & dimm3; set wait one clock	*/
-		      /* cycle for next data access 					*/
+		      /* cycle for next data access					*/
 
 	DIM0_BNK0_CTL_0 = BNK0_RAM_SIZ_128MB    (0x90)
 		      /* set dimm0 bank0 for 128 MB	*/
diff --git a/board/MAI/AmigaOneG3SE/u-boot.lds b/board/MAI/AmigaOneG3SE/u-boot.lds
index 11b28d777d..7386ea7a25 100644
--- a/board/MAI/AmigaOneG3SE/u-boot.lds
+++ b/board/MAI/AmigaOneG3SE/u-boot.lds
@@ -40,11 +40,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/MAI/AmigaOneG3SE/usb_uhci.c b/board/MAI/AmigaOneG3SE/usb_uhci.c
index 14e804308a..479beedc4d 100644
--- a/board/MAI/AmigaOneG3SE/usb_uhci.c
+++ b/board/MAI/AmigaOneG3SE/usb_uhci.c
@@ -522,7 +522,7 @@ void usb_check_int_chain(void)
 		link=swap_32(td_int[i].link) & 0xfffffff0; /* next in chain */
 		td=(uhci_td_t *)link; /* assign it */
 		/* all interrupt TDs are finally linked to the td_int[0].
- 		 * so we process all until we find the td_int[0].
+		 * so we process all until we find the td_int[0].
 		 * if int0 chain points to a QH, we're also done
 	   */
 		while(((i>0) && (link != (unsigned long)&td_int[0])) ||
diff --git a/board/MAI/AmigaOneG3SE/via686.c b/board/MAI/AmigaOneG3SE/via686.c
index 3606db82e0..2427ce5713 100644
--- a/board/MAI/AmigaOneG3SE/via686.c
+++ b/board/MAI/AmigaOneG3SE/via686.c
@@ -97,7 +97,7 @@ void via_isa_init(pci_dev_t dev, struct pci_config_table *table)
 	pci_write_config_byte(dev, 0x80, 0);
 	pci_write_config_byte(dev, 0x85, 0x01);
 
-/* 	pci_write_config_byte(dev, 0x77, 0x00); */
+/*	pci_write_config_byte(dev, 0x77, 0x00); */
     }
 }
 
@@ -212,7 +212,7 @@ void via_cfgfunc_via686(struct pci_controller *host, pci_dev_t dev, struct pci_c
 }
 
 __asm         ("    .globl via_calibrate_time_base \n"
-	       "via_calibrate_time_base: 	   \n"
+	       "via_calibrate_time_base:	   \n"
 	       "   lis     9, 0xfe00		   \n"
 	       "   li      0, 0x00		   \n"
 	       "   mttbu   0			   \n"
@@ -262,9 +262,9 @@ void ide_led(uchar led, uchar status)
 /*     unsigned char c = in_byte(0x92); */
 
 /*     if (!status) */
-/* 	out_byte(0x92, c | 0xC0); */
+/*	out_byte(0x92, c | 0xC0); */
 /*     else */
-/* 	out_byte(0x92, c & ~0xC0); */
+/*	out_byte(0x92, c & ~0xC0); */
 }
 
 
diff --git a/board/MAI/menu/menu.h b/board/MAI/menu/menu.h
index 8aebb7de53..23d89a7068 100644
--- a/board/MAI/menu/menu.h
+++ b/board/MAI/menu/menu.h
@@ -4,15 +4,14 @@
 /* A single menu */
 typedef void (*menu_finish_callback)(struct menu_s *menu);
 
-typedef struct menu_s
-{
-    char *name;                     /* Menu name */
-    int  num_options;               /* Number of options in this menu */
-    int  flags;                     /* Various flags - see below */
-    int  option_align;              /* Aligns options to a field width of this much characters if != 0 */
-
-    struct menu_option_s **options; /* Pointer to this menu's options */
-    menu_finish_callback callback;  /* Called when the menu closes */
+typedef struct menu_s {
+	char *name;		/* Menu name */
+	int num_options;	/* Number of options in this menu */
+	int flags;		/* Various flags - see below */
+	int option_align;	/* Aligns options to a field width of this much characters if != 0 */
+
+	struct menu_option_s **options;	/* Pointer to this menu's options */
+	menu_finish_callback callback;	/* Called when the menu closes */
 } menu_t;
 
 /*
@@ -23,13 +22,12 @@ typedef struct menu_s
  * sys : pointer for system-specific data, init to NULL and don't touch
  */
 
-#define OPTION_PREAMBLE				\
-    int type;                     		\
-    char *name;   				\
-    char *help;   				\
-    int id;                                     \
-    void *sys;                                  \
-
+#define OPTION_PREAMBLE		\
+	int type;		\
+	char *name;		\
+	char *help;		\
+	int id;			\
+	void *sys;
 
 /*
  * Menu option types.
@@ -110,59 +108,49 @@ typedef struct menu_text_s
 
 
 #define MENU_SELECTION_TYPE 3
-typedef struct menu_select_option_s
-{
-    char *map_from;               /* Map this variable contents ... */
-    char *map_to;                 /* ... to this menu text and vice versa */
+typedef struct menu_select_option_s {
+	char *map_from;		/* Map this variable contents ... */
+	char *map_to;		/* ... to this menu text and vice versa */
 } menu_select_option_t;
 
-typedef struct menu_select_s
-{
-    OPTION_PREAMBLE
-
-    int num_options;             /* Number of mappings */
-    menu_select_option_t **options;
-				 /* Option list array */
+typedef struct menu_select_s {
+	OPTION_PREAMBLE int num_options;	/* Number of mappings */
+	menu_select_option_t **options;
+	/* Option list array */
 } menu_select_t;
 
 
 #define MENU_ROUTINE_TYPE 4
-typedef void (*menu_routine_callback)(struct menu_routine_s *);
+typedef void (*menu_routine_callback) (struct menu_routine_s *);
 
-typedef struct menu_routine_s
-{
-    OPTION_PREAMBLE
-    menu_routine_callback callback;
-				 /* routine to be called */
-    void *user_data;             /* User data, don't care for system */
+typedef struct menu_routine_s {
+	OPTION_PREAMBLE menu_routine_callback callback;
+	/* routine to be called */
+	void *user_data;	/* User data, don't care for system */
 } menu_routine_t;
 
 
 #define MENU_CUSTOM_TYPE 5
-typedef void (*menu_custom_draw)(struct menu_custom_s *);
-typedef void (*menu_custom_key)(struct menu_custom_s *, int);
+typedef void (*menu_custom_draw) (struct menu_custom_s *);
+typedef void (*menu_custom_key) (struct menu_custom_s *, int);
 
-typedef struct menu_custom_s
-{
-    OPTION_PREAMBLE
-    menu_custom_draw drawfunc;
-    menu_custom_key  keyfunc;
-    void *user_data;
+typedef struct menu_custom_s {
+	OPTION_PREAMBLE menu_custom_draw drawfunc;
+	menu_custom_key keyfunc;
+	void *user_data;
 } menu_custom_t;
 
 /*
  * The menu option superstructure
  */
-typedef struct menu_option_s
-{
-    union
-    {
-	menu_submenu_t m_sub_menu;
-	menu_boolean_t m_boolean;
-	menu_text_t    m_text;
-	menu_select_t  m_select;
-	menu_routine_t m_routine;
-    };
+typedef struct menu_option_s {
+	union {
+		menu_submenu_t m_sub_menu;
+		menu_boolean_t m_boolean;
+		menu_text_t m_text;
+		menu_select_t m_select;
+		menu_routine_t m_routine;
+	};
 } menu_option_t;
 
 /* Init the menu system. Returns <0 on error */
diff --git a/board/Marvell/common/bootseq.txt b/board/Marvell/common/bootseq.txt
index 391d49a119..290aed90a5 100644
--- a/board/Marvell/common/bootseq.txt
+++ b/board/Marvell/common/bootseq.txt
@@ -56,7 +56,7 @@ in_flash:
     setup stack pointer (r1)
     setup GOT
     call cpu_init_f
-    	debug leds
+	debug leds
     board_init_f: (common/board.c)
 	board_early_init_f:
 	    remap gt regs?
@@ -74,7 +74,7 @@ in_flash:
 		dram_size()
 		setup PCI slave memory mappings
 		setup SCS
-   	setup monitor
+	setup monitor
 	alloc board info struct
 	init bd struct
 	relocate_code: (cpu/mpc7xxx/start.S)
diff --git a/board/Marvell/common/flash.c b/board/Marvell/common/flash.c
index a8add85672..3603372d07 100644
--- a/board/Marvell/common/flash.c
+++ b/board/Marvell/common/flash.c
@@ -23,7 +23,7 @@
 
 /*
  * flash.c - flash support for the 512k, 8bit boot flash
- 	and the 8MB 32bit extra flash on the DB64360
+	and the 8MB 32bit extra flash on the DB64360
  *           most of this file was based on the existing U-Boot
  *           flash drivers.
  *
diff --git a/board/Marvell/db64360/mpsc.c b/board/Marvell/db64360/mpsc.c
index d8acd31953..923d95555b 100644
--- a/board/Marvell/db64360/mpsc.c
+++ b/board/Marvell/db64360/mpsc.c
@@ -425,7 +425,7 @@ void mpsc_sdma_init (void)
 			 (MV64360_SDMA_WIN_ACCESS_FULL <<
 			  (MV64360_CUNIT_BASE_ADDR_WIN_0_BIT * 2)));
 
-/* Setup MPSC internal address space base address 	*/
+/* Setup MPSC internal address space base address	*/
 	GT_REG_WRITE (CUNIT_INTERNAL_SPACE_BASE_ADDR_REG, CFG_GT_REGS);
 
 /* no high address remap*/
diff --git a/board/Marvell/db64360/mpsc.h b/board/Marvell/db64360/mpsc.h
index f95f8c0f47..4b537eadc4 100644
--- a/board/Marvell/db64360/mpsc.h
+++ b/board/Marvell/db64360/mpsc.h
@@ -67,9 +67,9 @@ extern int (*mpsc_test_char)(void);
 #define TX_STOP     0x00010000
 #define RX_ENABLE   0x00000080
 
-#define SDMA_RX_ABORT 		  (1 << 15)
-#define SDMA_TX_ABORT 		  (1 << 31)
-#define MPSC_TX_ABORT 		  (1 << 7)
+#define SDMA_RX_ABORT		  (1 << 15)
+#define SDMA_TX_ABORT		  (1 << 31)
+#define MPSC_TX_ABORT		  (1 << 7)
 #define MPSC_RX_ABORT             (1 << 23)
 #define MPSC_ENTER_HUNT           (1 << 31)
 
diff --git a/board/Marvell/db64360/mv_eth.c b/board/Marvell/db64360/mv_eth.c
index e5a87ad295..dfc0bf7d30 100644
--- a/board/Marvell/db64360/mv_eth.c
+++ b/board/Marvell/db64360/mv_eth.c
@@ -1391,7 +1391,7 @@ u32 mv_get_internal_sram_base (void)
 *       port_phy_addr).
 *
 * INPUT:
-*       ETH_PORT_INFO 	*p_eth_port_ctrl       Ethernet port control struct
+*       ETH_PORT_INFO	*p_eth_port_ctrl       Ethernet port control struct
 *
 * OUTPUT:
 *       See description.
@@ -1551,7 +1551,7 @@ static void eth_port_init (ETH_PORT_INFO * p_eth_port_ctrl)
 *       ether_init_rx_desc_ring for Rx queues).
 *
 * INPUT:
-*       ETH_PORT_INFO 	*p_eth_port_ctrl       Ethernet port control struct
+*       ETH_PORT_INFO	*p_eth_port_ctrl       Ethernet port control struct
 *
 * OUTPUT:
 *       Ethernet port is ready to receive and transmit.
@@ -1641,7 +1641,7 @@ static bool eth_port_start (ETH_PORT_INFO * p_eth_port_ctrl)
 * INPUT:
 *	ETH_PORT eth_port_num     Port number.
 *	char *        p_addr		Address to be set
-*	ETH_QUEUE 	  queue		Rx queue number for this MAC address.
+*	ETH_QUEUE	  queue		Rx queue number for this MAC address.
 *
 * OUTPUT:
 *	Set MAC address low and high registers. also calls eth_port_uc_addr()
@@ -1679,10 +1679,10 @@ static void eth_port_uc_addr_set (ETH_PORT eth_port_num,
 *	parameters.
 *
 * INPUT:
-*	ETH_PORT 	eth_port_num      Port number.
+*	ETH_PORT	eth_port_num      Port number.
 *	unsigned char uc_nibble		Unicast MAC Address last nibble.
-*	ETH_QUEUE 		 queue		Rx queue number for this MAC address.
-*	int 			option      0 = Add, 1 = remove address.
+*	ETH_QUEUE		 queue		Rx queue number for this MAC address.
+*	int			option      0 = Add, 1 = remove address.
 *
 * OUTPUT:
 *	This function add/removes MAC addresses from the port unicast address
@@ -1761,10 +1761,10 @@ static bool eth_port_uc_addr (ETH_PORT eth_port_num,
 *	   In this case, the function calculates the CRC-8bit value and calls
 *	   eth_port_omc_addr() routine to set the Other Multicast Table.
 * INPUT:
-*	ETH_PORT 	eth_port_num      Port number.
-*	unsigned char 	*p_addr		Unicast MAC Address.
-*	ETH_QUEUE 		 queue		Rx queue number for this MAC address.
-*	int 			option      0 = Add, 1 = remove address.
+*	ETH_PORT	eth_port_num      Port number.
+*	unsigned char	*p_addr		Unicast MAC Address.
+*	ETH_QUEUE		 queue		Rx queue number for this MAC address.
+*	int			option      0 = Add, 1 = remove address.
 *
 * OUTPUT:
 *	See description.
@@ -1895,10 +1895,10 @@ static void eth_port_mc_addr (ETH_PORT eth_port_num,
 *	according to the argument given.
 *
 * INPUT:
-*	ETH_PORT 	eth_port_num      Port number.
-*	unsigned char 	mc_byte		Multicast addr last byte (MAC DA[7:0] bits).
-*	ETH_QUEUE 		 queue		Rx queue number for this MAC address.
-*	int 			option      0 = Add, 1 = remove address.
+*	ETH_PORT	eth_port_num      Port number.
+*	unsigned char	mc_byte		Multicast addr last byte (MAC DA[7:0] bits).
+*	ETH_QUEUE		 queue		Rx queue number for this MAC address.
+*	int			option      0 = Add, 1 = remove address.
 *
 * OUTPUT:
 *	See description.
@@ -1959,10 +1959,10 @@ static bool eth_port_smc_addr (ETH_PORT eth_port_num,
 *	CRC-8 argument given.
 *
 * INPUT:
-*	ETH_PORT 	eth_port_num      Port number.
-*	unsigned char 	  crc8		A CRC-8bit (Polynomial: x^8+x^2+x^1+1).
-*	ETH_QUEUE 		 queue		Rx queue number for this MAC address.
-*	int 			option      0 = Add, 1 = remove address.
+*	ETH_PORT	eth_port_num      Port number.
+*	unsigned char	  crc8		A CRC-8bit (Polynomial: x^8+x^2+x^1+1).
+*	ETH_QUEUE		 queue		Rx queue number for this MAC address.
+*	int			option      0 = Add, 1 = remove address.
 *
 * OUTPUT:
 *	See description.
@@ -2203,7 +2203,7 @@ static bool ethernet_phy_reset (ETH_PORT eth_port_num)
  * eth_port_reset - Reset Ethernet port
  *
  * DESCRIPTION:
- * 	This routine resets the chip by aborting any SDMA engine activity and
+ *	This routine resets the chip by aborting any SDMA engine activity and
  *      clearing the MIB counters. The Receiver and the Transmit unit are in
  *      idle state after this command is performed and the port is disabled.
  *
@@ -2556,9 +2556,9 @@ static void eth_set_access_control (ETH_PORT eth_port_num,
  *
  * INPUT:
  *	ETH_PORT_INFO   *p_eth_port_ctrl   Ethernet Port Control srtuct.
- *	ETH_QUEUE   	rx_queue         Number of Rx queue.
- *      int 			rx_desc_num       Number of Rx descriptors
- *      int 			rx_buff_size      Size of Rx buffer
+ *	ETH_QUEUE	rx_queue         Number of Rx queue.
+ *      int			rx_desc_num       Number of Rx descriptors
+ *      int			rx_buff_size      Size of Rx buffer
  *      unsigned int    rx_desc_base_addr  Rx descriptors memory area base addr.
  *      unsigned int    rx_buff_base_addr  Rx buffer memory area base addr.
  *
@@ -2650,9 +2650,9 @@ static bool ether_init_rx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl,
  *
  * INPUT:
  *	ETH_PORT_INFO   *p_eth_port_ctrl   Ethernet Port Control srtuct.
- *	ETH_QUEUE   	tx_queue         Number of Tx queue.
- *      int 			tx_desc_num       Number of Tx descriptors
- *      int 			tx_buff_size      Size of Tx buffer
+ *	ETH_QUEUE	tx_queue         Number of Tx queue.
+ *      int			tx_desc_num       Number of Tx descriptors
+ *      int			tx_buff_size      Size of Tx buffer
  *      unsigned int    tx_desc_base_addr  Tx descriptors memory area base addr.
  *      unsigned int    tx_buff_base_addr  Tx buffer memory area base addr.
  *
@@ -2745,7 +2745,7 @@ static bool ether_init_tx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl,
  *
  * INPUT:
  *	ETH_PORT_INFO   *p_eth_port_ctrl   Ethernet Port Control srtuct.
- *	ETH_QUEUE   	tx_queue         Number of Tx queue.
+ *	ETH_QUEUE	tx_queue         Number of Tx queue.
  *	PKT_INFO        *p_pkt_info       User packet buffer.
  *
  * OUTPUT:
@@ -2861,7 +2861,7 @@ static ETH_FUNC_RET_STATUS eth_port_send (ETH_PORT_INFO * p_eth_port_ctrl,
  *
  * INPUT:
  *	ETH_PORT_INFO   *p_eth_port_ctrl   Ethernet Port Control srtuct.
- *	ETH_QUEUE   	tx_queue         Number of Tx queue.
+ *	ETH_QUEUE	tx_queue         Number of Tx queue.
  *	PKT_INFO        *p_pkt_info       User packet buffer.
  *
  * OUTPUT:
@@ -2930,7 +2930,7 @@ static ETH_FUNC_RET_STATUS eth_tx_return_desc (ETH_PORT_INFO *
  * eth_port_receive - Get received information from Rx ring.
  *
  * DESCRIPTION:
- * 	This routine returns the received data to the caller. There is no
+ *	This routine returns the received data to the caller. There is no
  *	data copying during routine operation. All information is returned
  *	using pointer to packet information struct passed from the caller.
  *      If the routine exhausts	Rx ring resources then the resource error flag
@@ -2938,7 +2938,7 @@ static ETH_FUNC_RET_STATUS eth_tx_return_desc (ETH_PORT_INFO *
  *
  * INPUT:
  *	ETH_PORT_INFO   *p_eth_port_ctrl   Ethernet Port Control srtuct.
- *	ETH_QUEUE   	rx_queue         Number of Rx queue.
+ *	ETH_QUEUE	rx_queue         Number of Rx queue.
  *	PKT_INFO        *p_pkt_info       User packet buffer.
  *
  * OUTPUT:
@@ -2980,7 +2980,7 @@ static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO * p_eth_port_ctrl,
 
 	/* Nothing to receive... */
 	if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) {
-/* 	DP(printf("Rx: command_status: %08x\n", command_status)); */
+/*	DP(printf("Rx: command_status: %08x\n", command_status)); */
 		D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0);
 /*	DP(printf("\nETH_END_OF_JOB ...\n"));*/
 		return ETH_END_OF_JOB;
@@ -3019,7 +3019,7 @@ static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO * p_eth_port_ctrl,
  *
  * INPUT:
  *	ETH_PORT_INFO   *p_eth_port_ctrl   Ethernet Port Control srtuct.
- *	ETH_QUEUE   	rx_queue         Number of Rx queue.
+ *	ETH_QUEUE	rx_queue         Number of Rx queue.
  *      PKT_INFO        *p_pkt_info       Information on the returned buffer.
  *
  * OUTPUT:
diff --git a/board/Marvell/db64360/u-boot.lds b/board/Marvell/db64360/u-boot.lds
index 25e16de3b6..1a95755ab4 100644
--- a/board/Marvell/db64360/u-boot.lds
+++ b/board/Marvell/db64360/u-boot.lds
@@ -37,11 +37,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/Marvell/db64460/mpsc.c b/board/Marvell/db64460/mpsc.c
index b783aff8d1..359b831406 100644
--- a/board/Marvell/db64460/mpsc.c
+++ b/board/Marvell/db64460/mpsc.c
@@ -425,7 +425,7 @@ void mpsc_sdma_init (void)
 			 (MV64460_SDMA_WIN_ACCESS_FULL <<
 			  (MV64460_CUNIT_BASE_ADDR_WIN_0_BIT * 2)));
 
-/* Setup MPSC internal address space base address 	*/
+/* Setup MPSC internal address space base address	*/
 	GT_REG_WRITE (CUNIT_INTERNAL_SPACE_BASE_ADDR_REG, CFG_GT_REGS);
 
 /* no high address remap*/
diff --git a/board/Marvell/db64460/mpsc.h b/board/Marvell/db64460/mpsc.h
index 3cc0c0f7a5..b8462cb68e 100644
--- a/board/Marvell/db64460/mpsc.h
+++ b/board/Marvell/db64460/mpsc.h
@@ -67,9 +67,9 @@ extern int (*mpsc_test_char)(void);
 #define TX_STOP     0x00010000
 #define RX_ENABLE   0x00000080
 
-#define SDMA_RX_ABORT 		  (1 << 15)
-#define SDMA_TX_ABORT 		  (1 << 31)
-#define MPSC_TX_ABORT 		  (1 << 7)
+#define SDMA_RX_ABORT		  (1 << 15)
+#define SDMA_TX_ABORT		  (1 << 31)
+#define MPSC_TX_ABORT		  (1 << 7)
 #define MPSC_RX_ABORT             (1 << 23)
 #define MPSC_ENTER_HUNT           (1 << 31)
 
diff --git a/board/Marvell/db64460/mv_eth.c b/board/Marvell/db64460/mv_eth.c
index b2c7835a57..0458164ef1 100644
--- a/board/Marvell/db64460/mv_eth.c
+++ b/board/Marvell/db64460/mv_eth.c
@@ -1390,7 +1390,7 @@ u32 mv_get_internal_sram_base (void)
 *       port_phy_addr).
 *
 * INPUT:
-*       ETH_PORT_INFO 	*p_eth_port_ctrl       Ethernet port control struct
+*       ETH_PORT_INFO	*p_eth_port_ctrl       Ethernet port control struct
 *
 * OUTPUT:
 *       See description.
@@ -1550,7 +1550,7 @@ static void eth_port_init (ETH_PORT_INFO * p_eth_port_ctrl)
 *       ether_init_rx_desc_ring for Rx queues).
 *
 * INPUT:
-*       ETH_PORT_INFO 	*p_eth_port_ctrl       Ethernet port control struct
+*       ETH_PORT_INFO	*p_eth_port_ctrl       Ethernet port control struct
 *
 * OUTPUT:
 *       Ethernet port is ready to receive and transmit.
@@ -1640,7 +1640,7 @@ static bool eth_port_start (ETH_PORT_INFO * p_eth_port_ctrl)
 * INPUT:
 *	ETH_PORT eth_port_num     Port number.
 *	char *        p_addr		Address to be set
-*	ETH_QUEUE 	  queue		Rx queue number for this MAC address.
+*	ETH_QUEUE	  queue		Rx queue number for this MAC address.
 *
 * OUTPUT:
 *	Set MAC address low and high registers. also calls eth_port_uc_addr()
@@ -1678,10 +1678,10 @@ static void eth_port_uc_addr_set (ETH_PORT eth_port_num,
 *	parameters.
 *
 * INPUT:
-*	ETH_PORT 	eth_port_num      Port number.
+*	ETH_PORT	eth_port_num      Port number.
 *	unsigned char uc_nibble		Unicast MAC Address last nibble.
-*	ETH_QUEUE 		 queue		Rx queue number for this MAC address.
-*	int 			option      0 = Add, 1 = remove address.
+*	ETH_QUEUE		 queue		Rx queue number for this MAC address.
+*	int			option      0 = Add, 1 = remove address.
 *
 * OUTPUT:
 *	This function add/removes MAC addresses from the port unicast address
@@ -1760,10 +1760,10 @@ static bool eth_port_uc_addr (ETH_PORT eth_port_num,
 *	   In this case, the function calculates the CRC-8bit value and calls
 *	   eth_port_omc_addr() routine to set the Other Multicast Table.
 * INPUT:
-*	ETH_PORT 	eth_port_num      Port number.
-*	unsigned char 	*p_addr		Unicast MAC Address.
-*	ETH_QUEUE 		 queue		Rx queue number for this MAC address.
-*	int 			option      0 = Add, 1 = remove address.
+*	ETH_PORT	eth_port_num      Port number.
+*	unsigned char	*p_addr		Unicast MAC Address.
+*	ETH_QUEUE		 queue		Rx queue number for this MAC address.
+*	int			option      0 = Add, 1 = remove address.
 *
 * OUTPUT:
 *	See description.
@@ -1894,10 +1894,10 @@ static void eth_port_mc_addr (ETH_PORT eth_port_num,
 *	according to the argument given.
 *
 * INPUT:
-*	ETH_PORT 	eth_port_num      Port number.
-*	unsigned char 	mc_byte		Multicast addr last byte (MAC DA[7:0] bits).
-*	ETH_QUEUE 		 queue		Rx queue number for this MAC address.
-*	int 			option      0 = Add, 1 = remove address.
+*	ETH_PORT	eth_port_num      Port number.
+*	unsigned char	mc_byte		Multicast addr last byte (MAC DA[7:0] bits).
+*	ETH_QUEUE		 queue		Rx queue number for this MAC address.
+*	int			option      0 = Add, 1 = remove address.
 *
 * OUTPUT:
 *	See description.
@@ -1958,10 +1958,10 @@ static bool eth_port_smc_addr (ETH_PORT eth_port_num,
 *	CRC-8 argument given.
 *
 * INPUT:
-*	ETH_PORT 	eth_port_num      Port number.
-*	unsigned char 	  crc8		A CRC-8bit (Polynomial: x^8+x^2+x^1+1).
-*	ETH_QUEUE 		 queue		Rx queue number for this MAC address.
-*	int 			option      0 = Add, 1 = remove address.
+*	ETH_PORT	eth_port_num      Port number.
+*	unsigned char	  crc8		A CRC-8bit (Polynomial: x^8+x^2+x^1+1).
+*	ETH_QUEUE		 queue		Rx queue number for this MAC address.
+*	int			option      0 = Add, 1 = remove address.
 *
 * OUTPUT:
 *	See description.
@@ -2202,7 +2202,7 @@ static bool ethernet_phy_reset (ETH_PORT eth_port_num)
  * eth_port_reset - Reset Ethernet port
  *
  * DESCRIPTION:
- * 	This routine resets the chip by aborting any SDMA engine activity and
+ *	This routine resets the chip by aborting any SDMA engine activity and
  *      clearing the MIB counters. The Receiver and the Transmit unit are in
  *      idle state after this command is performed and the port is disabled.
  *
@@ -2555,9 +2555,9 @@ static void eth_set_access_control (ETH_PORT eth_port_num,
  *
  * INPUT:
  *	ETH_PORT_INFO   *p_eth_port_ctrl   Ethernet Port Control srtuct.
- *	ETH_QUEUE   	rx_queue         Number of Rx queue.
- *      int 			rx_desc_num       Number of Rx descriptors
- *      int 			rx_buff_size      Size of Rx buffer
+ *	ETH_QUEUE	rx_queue         Number of Rx queue.
+ *      int			rx_desc_num       Number of Rx descriptors
+ *      int			rx_buff_size      Size of Rx buffer
  *      unsigned int    rx_desc_base_addr  Rx descriptors memory area base addr.
  *      unsigned int    rx_buff_base_addr  Rx buffer memory area base addr.
  *
@@ -2649,9 +2649,9 @@ static bool ether_init_rx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl,
  *
  * INPUT:
  *	ETH_PORT_INFO   *p_eth_port_ctrl   Ethernet Port Control srtuct.
- *	ETH_QUEUE   	tx_queue         Number of Tx queue.
- *      int 			tx_desc_num       Number of Tx descriptors
- *      int 			tx_buff_size      Size of Tx buffer
+ *	ETH_QUEUE	tx_queue         Number of Tx queue.
+ *      int			tx_desc_num       Number of Tx descriptors
+ *      int			tx_buff_size      Size of Tx buffer
  *      unsigned int    tx_desc_base_addr  Tx descriptors memory area base addr.
  *      unsigned int    tx_buff_base_addr  Tx buffer memory area base addr.
  *
@@ -2744,7 +2744,7 @@ static bool ether_init_tx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl,
  *
  * INPUT:
  *	ETH_PORT_INFO   *p_eth_port_ctrl   Ethernet Port Control srtuct.
- *	ETH_QUEUE   	tx_queue         Number of Tx queue.
+ *	ETH_QUEUE	tx_queue         Number of Tx queue.
  *	PKT_INFO        *p_pkt_info       User packet buffer.
  *
  * OUTPUT:
@@ -2860,7 +2860,7 @@ static ETH_FUNC_RET_STATUS eth_port_send (ETH_PORT_INFO * p_eth_port_ctrl,
  *
  * INPUT:
  *	ETH_PORT_INFO   *p_eth_port_ctrl   Ethernet Port Control srtuct.
- *	ETH_QUEUE   	tx_queue         Number of Tx queue.
+ *	ETH_QUEUE	tx_queue         Number of Tx queue.
  *	PKT_INFO        *p_pkt_info       User packet buffer.
  *
  * OUTPUT:
@@ -2929,7 +2929,7 @@ static ETH_FUNC_RET_STATUS eth_tx_return_desc (ETH_PORT_INFO *
  * eth_port_receive - Get received information from Rx ring.
  *
  * DESCRIPTION:
- * 	This routine returns the received data to the caller. There is no
+ *	This routine returns the received data to the caller. There is no
  *	data copying during routine operation. All information is returned
  *	using pointer to packet information struct passed from the caller.
  *      If the routine exhausts	Rx ring resources then the resource error flag
@@ -2937,7 +2937,7 @@ static ETH_FUNC_RET_STATUS eth_tx_return_desc (ETH_PORT_INFO *
  *
  * INPUT:
  *	ETH_PORT_INFO   *p_eth_port_ctrl   Ethernet Port Control srtuct.
- *	ETH_QUEUE   	rx_queue         Number of Rx queue.
+ *	ETH_QUEUE	rx_queue         Number of Rx queue.
  *	PKT_INFO        *p_pkt_info       User packet buffer.
  *
  * OUTPUT:
@@ -2979,7 +2979,7 @@ static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO * p_eth_port_ctrl,
 
 	/* Nothing to receive... */
 	if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) {
-/* 	DP(printf("Rx: command_status: %08x\n", command_status)); */
+/*	DP(printf("Rx: command_status: %08x\n", command_status)); */
 		D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0);
 /*	DP(printf("\nETH_END_OF_JOB ...\n"));*/
 		return ETH_END_OF_JOB;
@@ -3018,7 +3018,7 @@ static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO * p_eth_port_ctrl,
  *
  * INPUT:
  *	ETH_PORT_INFO   *p_eth_port_ctrl   Ethernet Port Control srtuct.
- *	ETH_QUEUE   	rx_queue         Number of Rx queue.
+ *	ETH_QUEUE	rx_queue         Number of Rx queue.
  *      PKT_INFO        *p_pkt_info       Information on the returned buffer.
  *
  * OUTPUT:
diff --git a/board/Marvell/db64460/u-boot.lds b/board/Marvell/db64460/u-boot.lds
index 25e16de3b6..1a95755ab4 100644
--- a/board/Marvell/db64460/u-boot.lds
+++ b/board/Marvell/db64460/u-boot.lds
@@ -37,11 +37,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/MigoR/lowlevel_init.S b/board/MigoR/lowlevel_init.S
index 2ec8e04b18..e48f7b3b10 100644
--- a/board/MigoR/lowlevel_init.S
+++ b/board/MigoR/lowlevel_init.S
@@ -87,7 +87,7 @@ lowlevel_init:
 	mov.w	r0, @r1
 
 	mov.l	DLLFRQ_A, r1	! 20080115
-	mov.l	DLLFRQ_D, r0 	! 20080115
+	mov.l	DLLFRQ_D, r0	! 20080115
 	mov.l	r0, @r1
 
 	mov.l	FRQCR_A, r1		! 0xA4150000 Frequency control register
@@ -100,11 +100,11 @@ lowlevel_init:
 
 bsc_init:
 	mov.l	CMNCR_A, r1	! CMNCR address -> R1
-	mov.l 	CMNCR_D, r0	! CMNCR data    -> R0
+	mov.l	CMNCR_D, r0	! CMNCR data    -> R0
 	mov.l	r0, @r1		! CMNCR set
 
 	mov.l	CS0BCR_A, r1	! CS0BCR address -> R1
-	mov.l 	CS0BCR_D, r0	! CS0BCR data    -> R0
+	mov.l	CS0BCR_D, r0	! CS0BCR data    -> R0
 	mov.l	r0, @r1		! CS0BCR set
 
 	mov.l	CS4BCR_A, r1	! CS4BCR address -> R1
@@ -112,35 +112,35 @@ bsc_init:
 	mov.l	r0, @r1		! CS4BCR set
 
 	mov.l	CS5ABCR_A, r1	! CS5ABCR address -> R1
-	mov.l 	CS5ABCR_D, r0	! CS5ABCR data    -> R0
+	mov.l	CS5ABCR_D, r0	! CS5ABCR data    -> R0
 	mov.l	r0, @r1		! CS5ABCR set
 
 	mov.l	CS5BBCR_A, r1	! CS5BBCR address -> R1
-	mov.l 	CS5BBCR_D, r0	! CS5BBCR data    -> R0
+	mov.l	CS5BBCR_D, r0	! CS5BBCR data    -> R0
 	mov.l	r0, @r1		! CS5BBCR set
 
 	mov.l	CS6ABCR_A, r1	! CS6ABCR address -> R1
-	mov.l 	CS6ABCR_D, r0	! CS6ABCR data    -> R0
+	mov.l	CS6ABCR_D, r0	! CS6ABCR data    -> R0
 	mov.l	r0, @r1		! CS6ABCR set
 
 	mov.l	CS0WCR_A, r1	! CS0WCR address -> R1
-	mov.l 	CS0WCR_D, r0	! CS0WCR data    -> R0
+	mov.l	CS0WCR_D, r0	! CS0WCR data    -> R0
 	mov.l	r0, @r1		! CS0WCR set
 
 	mov.l	CS4WCR_A, r1	! CS4WCR address -> R1
-	mov.l 	CS4WCR_D, r0	! CS4WCR data    -> R0
+	mov.l	CS4WCR_D, r0	! CS4WCR data    -> R0
 	mov.l	r0, @r1		! CS4WCR set
 
 	mov.l	CS5AWCR_A, r1	! CS5AWCR address -> R1
-	mov.l 	CS5AWCR_D, r0	! CS5AWCR data    -> R0
+	mov.l	CS5AWCR_D, r0	! CS5AWCR data    -> R0
 	mov.l	r0, @r1		! CS5AWCR set
 
 	mov.l	CS5BWCR_A, r1	! CS5BWCR address -> R1
-	mov.l 	CS5BWCR_D, r0	! CS5BWCR data    -> R0
+	mov.l	CS5BWCR_D, r0	! CS5BWCR data    -> R0
 	mov.l	r0, @r1		! CS5BWCR set
 
 	mov.l	CS6AWCR_A, r1	! CS6AWCR address -> R1
-	mov.l 	CS6AWCR_D, r0	! CS6AWCR data    -> R0
+	mov.l	CS6AWCR_D, r0	! CS6AWCR data    -> R0
 	mov.l	r0, @r1		! CS6AWCR set
 
 	! SDRAM initialization
@@ -173,7 +173,7 @@ bsc_init:
 	mov.l	r0, @r1
 
 	mov.l	SDMR3_A, r1	! SDMR3 address -> R1
-	mov 	#0x00, r0	! SDMR3 data    -> R0
+	mov	#0x00, r0	! SDMR3 data    -> R0
 	mov.b	r0, @r1		! SDMR3 set
 
 	! BL bit off (init = ON)  (?!?)
diff --git a/board/RPXClassic/u-boot.lds b/board/RPXClassic/u-boot.lds
index dbea90cd2a..1f9a191d47 100644
--- a/board/RPXClassic/u-boot.lds
+++ b/board/RPXClassic/u-boot.lds
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/RPXClassic/u-boot.lds.debug b/board/RPXClassic/u-boot.lds.debug
index 753411fcbf..c33581d250 100644
--- a/board/RPXClassic/u-boot.lds.debug
+++ b/board/RPXClassic/u-boot.lds.debug
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/RPXlite/flash.c b/board/RPXlite/flash.c
index 846794df3f..659d60a2dc 100644
--- a/board/RPXlite/flash.c
+++ b/board/RPXlite/flash.c
@@ -31,7 +31,7 @@
  * are not tested.
  *
  * (?) Does an RPXLite board which
- * 	does not use AM29LV800 flash memory exist ?
+ *	does not use AM29LV800 flash memory exist ?
  *	I don't know...
  */
 
diff --git a/board/RPXlite/u-boot.lds b/board/RPXlite/u-boot.lds
index dbea90cd2a..1f9a191d47 100644
--- a/board/RPXlite/u-boot.lds
+++ b/board/RPXlite/u-boot.lds
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/RPXlite/u-boot.lds.debug b/board/RPXlite/u-boot.lds.debug
index 753411fcbf..c33581d250 100644
--- a/board/RPXlite/u-boot.lds.debug
+++ b/board/RPXlite/u-boot.lds.debug
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/RPXlite_dw/RPXlite_dw.c b/board/RPXlite_dw/RPXlite_dw.c
index 237c58af36..d3dc081219 100644
--- a/board/RPXlite_dw/RPXlite_dw.c
+++ b/board/RPXlite_dw/RPXlite_dw.c
@@ -124,7 +124,7 @@ long int initdram (int board_type)
 	memctl->memc_mamr = CFG_MAMR_9COL & (~(MAMR_PTAE)); /* no refresh yet */
 	/*Disable Periodic timer A. */
 
- 	udelay(200);
+	udelay(200);
 
 	/* perform SDRAM initializsation sequence */
 
diff --git a/board/RPXlite_dw/flash.c b/board/RPXlite_dw/flash.c
index 1cbd53719f..41cb036bb8 100644
--- a/board/RPXlite_dw/flash.c
+++ b/board/RPXlite_dw/flash.c
@@ -31,7 +31,7 @@
  * are not tested.
  *
  * (?) Does an RPXLite board which
- * 	does not use AM29LV800 flash memory exist ?
+ *	does not use AM29LV800 flash memory exist ?
  *	I don't know...
  */
 
@@ -178,8 +178,8 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
 
 	value = addr[0] ;
 	switch (value & 0x00FF00FF) {
-	case AMD_MANUFACT:             		/* AMD_MANUFACT=0x00010001 in flash.h. */
-		info->flash_id = FLASH_MAN_AMD; /* FLASH_MAN_AMD=0x00000000 in flash.h.*/
+	case AMD_MANUFACT:			/* AMD_MANUFACT =0x00010001 in flash.h */
+		info->flash_id = FLASH_MAN_AMD; /* FLASH_MAN_AMD=0x00000000 in flash.h */
 		break;
 	case FUJ_MANUFACT:
 		info->flash_id = FLASH_MAN_FUJ;
diff --git a/board/RPXlite_dw/u-boot.lds b/board/RPXlite_dw/u-boot.lds
index 4d0d8a761d..2ee12069d7 100644
--- a/board/RPXlite_dw/u-boot.lds
+++ b/board/RPXlite_dw/u-boot.lds
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/RPXlite_dw/u-boot.lds.debug b/board/RPXlite_dw/u-boot.lds.debug
index 4942c42941..f6d1537639 100644
--- a/board/RPXlite_dw/u-boot.lds.debug
+++ b/board/RPXlite_dw/u-boot.lds.debug
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/RRvision/u-boot.lds b/board/RRvision/u-boot.lds
index 854912e0f6..9e767ee409 100644
--- a/board/RRvision/u-boot.lds
+++ b/board/RRvision/u-boot.lds
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)	}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)	}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)	}
   .rela.got      : { *(.rela.got)	}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/a3000/Makefile b/board/a3000/Makefile
index d3db1a90e2..dcb1907032 100644
--- a/board/a3000/Makefile
+++ b/board/a3000/Makefile
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS 	= $(BOARD).o flash.o
+COBJS	= $(BOARD).o flash.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
diff --git a/board/a3000/a3000.c b/board/a3000/a3000.c
index ab707ae970..737d35d76c 100644
--- a/board/a3000/a3000.c
+++ b/board/a3000/a3000.c
@@ -82,7 +82,7 @@ static struct pci_config_table pci_a3000_config_table[] = {
 				       PCI_COMMAND_MEMORY |
 				       PCI_COMMAND_MASTER }},
 	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
-	  PCI_ANY_ID, 0x15, PCI_ANY_ID, 	/* PCI slot2 */
+	  PCI_ANY_ID, 0x15, PCI_ANY_ID,		/* PCI slot2 */
 	  pci_cfgfunc_config_device, { PCI_ENET2_IOADDR,
 				       PCI_ENET2_MEMADDR,
 				       PCI_COMMAND_IO |
diff --git a/board/adder/u-boot.lds b/board/adder/u-boot.lds
index f0d7567642..25aaa7d8ff 100644
--- a/board/adder/u-boot.lds
+++ b/board/adder/u-boot.lds
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)	}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)	}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)	}
   .rela.got      : { *(.rela.got)	}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/ads5121/Makefile b/board/ads5121/Makefile
index b93bee13be..f4dacce285 100644
--- a/board/ads5121/Makefile
+++ b/board/ads5121/Makefile
@@ -23,9 +23,14 @@
 
 include $(TOPDIR)/config.mk
 
+$(shell mkdir -p $(OBJTREE)/board/freescale/common)
+
 LIB	= $(obj)lib$(BOARD).a
 
 COBJS-y	:= $(BOARD).o
+COBJS-${CONFIG_FSL_DIU_FB} += ads5121_diu.o
+COBJS-${CONFIG_FSL_DIU_FB} += ../freescale/common/fsl_diu_fb.o
+COBJS-${CONFIG_FSL_DIU_FB} += ../freescale/common/fsl_logo_bmp.o
 COBJS-$(CONFIG_PCI) += pci.o
 
 COBJS	:= $(COBJS-y)
diff --git a/board/ads5121/ads5121.c b/board/ads5121/ads5121.c
index 8629b031c4..2892665295 100644
--- a/board/ads5121/ads5121.c
+++ b/board/ads5121/ads5121.c
@@ -39,17 +39,35 @@
 
 #define SCCR2_CLOCKS_EN	(CLOCK_SCCR2_MEM_EN |		\
 			 CLOCK_SCCR2_SPDIF_EN |		\
+			 CLOCK_SCCR2_DIU_EN |		\
 			 CLOCK_SCCR2_I2C_EN)
 
 #define CSAW_START(start)	((start) & 0xFFFF0000)
 #define CSAW_STOP(start, size)	(((start) + (size) - 1) >> 16)
 
+#define MPC5121_IOCTL_PSC6_0	(0x284/4)
+#define MPC5121_IO_DIU_START	(0x288/4)
+#define MPC5121_IO_DIU_END	(0x2fc/4)
+
+/* Functional pin muxing */
+#define MPC5121_IO_FUNC1	(0 << 7)
+#define MPC5121_IO_FUNC2	(1 << 7)
+#define MPC5121_IO_FUNC3	(2 << 7)
+#define MPC5121_IO_FUNC4	(3 << 7)
+#define MPC5121_IO_ST		(1 << 2)
+#define MPC5121_IO_DS_1		(0)
+#define MPC5121_IO_DS_2		(1)
+#define MPC5121_IO_DS_3		(2)
+#define MPC5121_IO_DS_4		(3)
+
 long int fixed_sdram(void);
 
 int board_early_init_f (void)
 {
 	volatile immap_t *im = (immap_t *) CFG_IMMR;
-	u32 lpcaw;
+	u32 lpcaw, tmp32;
+	volatile ioctrl512x_t *ioctl = &(im->io_ctrl);
+	int i;
 
 	/*
 	 * Initialize Local Window for the CPLD registers access (CS2 selects
@@ -81,6 +99,16 @@ int board_early_init_f (void)
 	im->clk.sccr[0] = SCCR1_CLOCKS_EN;
 	im->clk.sccr[1] = SCCR2_CLOCKS_EN;
 
+	/* Configure DIU clock pin */
+	tmp32 = ioctl->regs[MPC5121_IOCTL_PSC6_0];
+	tmp32 &= ~0x1ff;
+	tmp32 |= MPC5121_IO_FUNC3 | MPC5121_IO_DS_4;
+	ioctl->regs[MPC5121_IOCTL_PSC6_0] = tmp32;
+
+	/* Initialize IO pins (pin mux) for DIU function */
+	for (i = MPC5121_IO_DIU_START; i < MPC5121_IO_DIU_END; i++)
+		ioctl->regs[i] |= (MPC5121_IO_FUNC3 | MPC5121_IO_DS_4);
+
 	return 0;
 }
 
@@ -186,6 +214,38 @@ long int fixed_sdram (void)
 	return msize;
 }
 
+int misc_init_r(void)
+{
+	u8 tmp_val;
+
+	/* Using this for DIU init before the driver in linux takes over
+	 *  Enable the TFP410 Encoder (I2C address 0x38)
+	 */
+
+	i2c_set_bus_num(2);
+	tmp_val = 0xBF;
+	i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
+	/* Verify if enabled */
+	tmp_val = 0;
+	i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
+	debug("DVI Encoder Read: 0x%02lx\n", tmp_val);
+
+	tmp_val = 0x10;
+	i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
+	/* Verify if enabled */
+	tmp_val = 0;
+	i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
+	debug("DVI Encoder Read: 0x%02lx\n", tmp_val);
+
+#ifdef CONFIG_FSL_DIU_FB
+#if	!(defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE))
+	ads5121_diu_init();
+#endif
+#endif
+
+	return 0;
+}
+
 int checkboard (void)
 {
 	ushort brd_rev = *(vu_short *) (CFG_CPLD_BASE + 0x00);
diff --git a/board/ads5121/ads5121_diu.c b/board/ads5121/ads5121_diu.c
new file mode 100644
index 0000000000..87cf0cbbe9
--- /dev/null
+++ b/board/ads5121/ads5121_diu.c
@@ -0,0 +1,165 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ * York Sun <yorksun@freescale.com>
+ *
+ * FSL DIU Framebuffer driver
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/io.h>
+
+#ifdef CONFIG_FSL_DIU_FB
+
+#include "../freescale/common/pixis.h"
+#include "../freescale/common/fsl_diu_fb.h"
+
+#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE)
+#include <devices.h>
+#include <video_fb.h>
+#endif
+
+extern unsigned int FSL_Logo_BMP[];
+
+static int xres, yres;
+
+void diu_set_pixel_clock(unsigned int pixclock)
+{
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	volatile clk512x_t *clk = &immap->clk;
+	volatile unsigned int *clkdvdr = &clk->scfr[0];
+	unsigned long speed_ccb, temp, pixval;
+
+	speed_ccb = get_bus_freq(0) * 4;
+	temp = 1000000000/pixclock;
+	temp *= 1000;
+	pixval = speed_ccb / temp;
+	debug("DIU pixval = %lu\n", pixval);
+
+	/* Modify PXCLK in GUTS CLKDVDR */
+	debug("DIU: Current value of CLKDVDR = 0x%08x\n", *clkdvdr);
+	temp = *clkdvdr & 0xFFFFFF00;
+	*clkdvdr = temp | (pixval & 0x1F);
+	debug("DIU: Modified value of CLKDVDR = 0x%08x\n", *clkdvdr);
+}
+
+int ads5121_diu_init(void)
+{
+	unsigned int pixel_format;
+
+	xres = 1024;
+	yres = 768;
+	pixel_format = 0x88883316;
+
+	return fsl_diu_init(xres, pixel_format, 0,
+		     (unsigned char *)FSL_Logo_BMP);
+}
+
+int ads5121diu_init_show_bmp(cmd_tbl_t *cmdtp,
+			     int flag, int argc, char *argv[])
+{
+	unsigned int addr;
+
+	if (argc < 2) {
+		printf("Usage:\n%s\n", cmdtp->usage);
+		return 1;
+	}
+
+	if (!strncmp(argv[1], "init", 4)) {
+#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE)
+		fsl_diu_clear_screen();
+		drv_video_init();
+#else
+		return ads5121_diu_init();
+#endif
+	} else {
+		addr = simple_strtoul(argv[1], NULL, 16);
+		fsl_diu_clear_screen();
+		fsl_diu_display_bmp((unsigned char *)addr, 0, 0, 0);
+	}
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	diufb, CFG_MAXARGS, 1, ads5121diu_init_show_bmp,
+	"diufb init | addr - Init or Display BMP file\n",
+	"init\n    - initialize DIU\n"
+	"addr\n    - display bmp at address 'addr'\n"
+	);
+
+
+#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE)
+
+/*
+ * The Graphic Device
+ */
+GraphicDevice ctfb;
+void *video_hw_init(void)
+{
+	GraphicDevice *pGD = (GraphicDevice *) &ctfb;
+	struct fb_info *info;
+
+	if (ads5121_diu_init() < 0)
+		return;
+
+	/* fill in Graphic device struct */
+	sprintf(pGD->modeIdent, "%dx%dx%d %ldkHz %ldHz",
+		xres, yres, 32, 64, 60);
+
+	pGD->frameAdrs = (unsigned int)fsl_fb_open(&info);
+	pGD->winSizeX = xres;
+	pGD->winSizeY = yres - info->logo_height;
+	pGD->plnSizeX = pGD->winSizeX;
+	pGD->plnSizeY = pGD->winSizeY;
+
+	pGD->gdfBytesPP = 4;
+	pGD->gdfIndex = GDF_32BIT_X888RGB;
+
+	pGD->isaBase = 0;
+	pGD->pciBase = 0;
+	pGD->memSize = info->screen_size - info->logo_size;
+
+	/* Cursor Start Address */
+	pGD->dprBase = 0;
+	pGD->vprBase = 0;
+	pGD->cprBase = 0;
+
+	return (void *)pGD;
+}
+
+/**
+  * Set the LUT
+  *
+  * @index: color number
+  * @r: red
+  * @b: blue
+  * @g: green
+  */
+void video_set_lut
+	(unsigned int index, unsigned char r, unsigned char g, unsigned char b)
+{
+	return;
+}
+
+#endif /* defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE) */
+
+#endif /* CONFIG_FSL_DIU_FB */
diff --git a/board/ads5121/u-boot.lds b/board/ads5121/u-boot.lds
index 141895278e..f2f6e149c3 100644
--- a/board/ads5121/u-boot.lds
+++ b/board/ads5121/u-boot.lds
@@ -30,11 +30,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/amcc/acadia/u-boot-nand.lds b/board/amcc/acadia/u-boot-nand.lds
index e5de203ca8..cbdc0b0500 100644
--- a/board/amcc/acadia/u-boot-nand.lds
+++ b/board/amcc/acadia/u-boot-nand.lds
@@ -31,11 +31,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/amcc/acadia/u-boot.lds b/board/amcc/acadia/u-boot.lds
index f1b7ec70b9..d52b51ae1b 100644
--- a/board/amcc/acadia/u-boot.lds
+++ b/board/amcc/acadia/u-boot.lds
@@ -38,11 +38,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/amcc/bamboo/bamboo.c b/board/amcc/bamboo/bamboo.c
index c4eace5804..50771879e1 100644
--- a/board/amcc/bamboo/bamboo.c
+++ b/board/amcc/bamboo/bamboo.c
@@ -280,86 +280,86 @@ const unsigned char cfg_simulate_spd_eeprom[128] = {
 #define EBC0_BNAP_SMALL_FLASH				\
 	EBC0_BNAP_BME_DISABLED			|	\
 	EBC0_BNAP_TWT_ENCODE(6)			|	\
-	EBC0_BNAP_CSN_ENCODE(0)	    		|	\
-	EBC0_BNAP_OEN_ENCODE(1)	    		|	\
-	EBC0_BNAP_WBN_ENCODE(1)	    		|	\
-	EBC0_BNAP_WBF_ENCODE(3)	    		|	\
-	EBC0_BNAP_TH_ENCODE(1)	    		|	\
-	EBC0_BNAP_RE_ENABLED	    		|	\
-	EBC0_BNAP_SOR_DELAYED	    		|	\
-	EBC0_BNAP_BEM_WRITEONLY	    		|	\
+	EBC0_BNAP_CSN_ENCODE(0)			|	\
+	EBC0_BNAP_OEN_ENCODE(1)			|	\
+	EBC0_BNAP_WBN_ENCODE(1)			|	\
+	EBC0_BNAP_WBF_ENCODE(3)			|	\
+	EBC0_BNAP_TH_ENCODE(1)			|	\
+	EBC0_BNAP_RE_ENABLED			|	\
+	EBC0_BNAP_SOR_DELAYED			|	\
+	EBC0_BNAP_BEM_WRITEONLY			|	\
 	EBC0_BNAP_PEN_DISABLED
 
 #define EBC0_BNCR_SMALL_FLASH_CS0			\
-	EBC0_BNCR_BAS_ENCODE(0xFFF00000)    	| 	\
-	EBC0_BNCR_BS_1MB		    	|	\
-	EBC0_BNCR_BU_RW			    	|	\
+	EBC0_BNCR_BAS_ENCODE(0xFFF00000)	|	\
+	EBC0_BNCR_BS_1MB			|	\
+	EBC0_BNCR_BU_RW				|	\
 	EBC0_BNCR_BW_8BIT
 
 #define EBC0_BNCR_SMALL_FLASH_CS4			\
-	EBC0_BNCR_BAS_ENCODE(0x87F00000)    	| 	\
-	EBC0_BNCR_BS_1MB		    	|	\
-	EBC0_BNCR_BU_RW			    	|	\
+	EBC0_BNCR_BAS_ENCODE(0x87F00000)	|	\
+	EBC0_BNCR_BS_1MB			|	\
+	EBC0_BNCR_BU_RW				|	\
 	EBC0_BNCR_BW_8BIT
 
 /* Large Flash or SRAM */
 #define EBC0_BNAP_LARGE_FLASH_OR_SRAM			\
-	EBC0_BNAP_BME_DISABLED	    		|	\
-	EBC0_BNAP_TWT_ENCODE(8)	    		|	\
-	EBC0_BNAP_CSN_ENCODE(0)	    		|	\
-	EBC0_BNAP_OEN_ENCODE(1)	    		|	\
-	EBC0_BNAP_WBN_ENCODE(1)	    		|	\
-	EBC0_BNAP_WBF_ENCODE(1)	    		|	\
-	EBC0_BNAP_TH_ENCODE(2)	    		|	\
-	EBC0_BNAP_SOR_DELAYED	    		|	\
-	EBC0_BNAP_BEM_RW	    		|	\
+	EBC0_BNAP_BME_DISABLED			|	\
+	EBC0_BNAP_TWT_ENCODE(8)			|	\
+	EBC0_BNAP_CSN_ENCODE(0)			|	\
+	EBC0_BNAP_OEN_ENCODE(1)			|	\
+	EBC0_BNAP_WBN_ENCODE(1)			|	\
+	EBC0_BNAP_WBF_ENCODE(1)			|	\
+	EBC0_BNAP_TH_ENCODE(2)			|	\
+	EBC0_BNAP_SOR_DELAYED			|	\
+	EBC0_BNAP_BEM_RW			|	\
 	EBC0_BNAP_PEN_DISABLED
 
-#define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS0   		\
-	EBC0_BNCR_BAS_ENCODE(0xFF800000)	| 	\
-	EBC0_BNCR_BS_8MB		    	|	\
-	EBC0_BNCR_BU_RW			    	|	\
+#define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS0		\
+	EBC0_BNCR_BAS_ENCODE(0xFF800000)	|	\
+	EBC0_BNCR_BS_8MB			|	\
+	EBC0_BNCR_BU_RW				|	\
 	EBC0_BNCR_BW_16BIT
 
 
-#define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4   		\
-	EBC0_BNCR_BAS_ENCODE(0x87800000)	| 	\
-	EBC0_BNCR_BS_8MB		    	|	\
-	EBC0_BNCR_BU_RW			    	|	\
+#define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4		\
+	EBC0_BNCR_BAS_ENCODE(0x87800000)	|	\
+	EBC0_BNCR_BS_8MB			|	\
+	EBC0_BNCR_BU_RW				|	\
 	EBC0_BNCR_BW_16BIT
 
 /* NVRAM - FPGA */
 #define EBC0_BNAP_NVRAM_FPGA				\
-	EBC0_BNAP_BME_DISABLED	    		|	\
-	EBC0_BNAP_TWT_ENCODE(9)	    		|	\
-	EBC0_BNAP_CSN_ENCODE(0)	    		|	\
-	EBC0_BNAP_OEN_ENCODE(1)	    		|	\
-	EBC0_BNAP_WBN_ENCODE(1)	    		|	\
-	EBC0_BNAP_WBF_ENCODE(0)	    		|	\
-	EBC0_BNAP_TH_ENCODE(2)	    		|	\
-	EBC0_BNAP_RE_ENABLED	    		|	\
-	EBC0_BNAP_SOR_DELAYED	    		|	\
-	EBC0_BNAP_BEM_WRITEONLY	    		|	\
+	EBC0_BNAP_BME_DISABLED			|	\
+	EBC0_BNAP_TWT_ENCODE(9)			|	\
+	EBC0_BNAP_CSN_ENCODE(0)			|	\
+	EBC0_BNAP_OEN_ENCODE(1)			|	\
+	EBC0_BNAP_WBN_ENCODE(1)			|	\
+	EBC0_BNAP_WBF_ENCODE(0)			|	\
+	EBC0_BNAP_TH_ENCODE(2)			|	\
+	EBC0_BNAP_RE_ENABLED			|	\
+	EBC0_BNAP_SOR_DELAYED			|	\
+	EBC0_BNAP_BEM_WRITEONLY			|	\
 	EBC0_BNAP_PEN_DISABLED
 
 #define EBC0_BNCR_NVRAM_FPGA_CS5			\
-	EBC0_BNCR_BAS_ENCODE(0x80000000)    	| 	\
-	EBC0_BNCR_BS_1MB		    	|	\
-	EBC0_BNCR_BU_RW			    	|	\
+	EBC0_BNCR_BAS_ENCODE(0x80000000)	|	\
+	EBC0_BNCR_BS_1MB			|	\
+	EBC0_BNCR_BU_RW				|	\
 	EBC0_BNCR_BW_8BIT
 
 /* Nand Flash */
 #define EBC0_BNAP_NAND_FLASH				\
-	EBC0_BNAP_BME_DISABLED	    		|	\
-	EBC0_BNAP_TWT_ENCODE(3)	    		|	\
-	EBC0_BNAP_CSN_ENCODE(0)	    		|	\
-	EBC0_BNAP_OEN_ENCODE(0)	    		|	\
-	EBC0_BNAP_WBN_ENCODE(0)	    		|	\
-	EBC0_BNAP_WBF_ENCODE(0)	    		|	\
-	EBC0_BNAP_TH_ENCODE(1)	    		|	\
-	EBC0_BNAP_RE_ENABLED	    		|	\
-	EBC0_BNAP_SOR_NOT_DELAYED   		|	\
-	EBC0_BNAP_BEM_RW	    		|	\
+	EBC0_BNAP_BME_DISABLED			|	\
+	EBC0_BNAP_TWT_ENCODE(3)			|	\
+	EBC0_BNAP_CSN_ENCODE(0)			|	\
+	EBC0_BNAP_OEN_ENCODE(0)			|	\
+	EBC0_BNAP_WBN_ENCODE(0)			|	\
+	EBC0_BNAP_WBF_ENCODE(0)			|	\
+	EBC0_BNAP_TH_ENCODE(1)			|	\
+	EBC0_BNAP_RE_ENABLED			|	\
+	EBC0_BNAP_SOR_NOT_DELAYED		|	\
+	EBC0_BNAP_BEM_RW			|	\
 	EBC0_BNAP_PEN_DISABLED
 
 
@@ -367,22 +367,22 @@ const unsigned char cfg_simulate_spd_eeprom[128] = {
 
 /* NAND0 */
 #define EBC0_BNCR_NAND_FLASH_CS1			\
-	EBC0_BNCR_BAS_ENCODE(0x90000000)    	| 	\
-	EBC0_BNCR_BS_1MB		    	|	\
-	EBC0_BNCR_BU_RW			    	|	\
+	EBC0_BNCR_BAS_ENCODE(0x90000000)	|	\
+	EBC0_BNCR_BS_1MB			|	\
+	EBC0_BNCR_BU_RW				|	\
 	EBC0_BNCR_BW_32BIT
 /* NAND1 - Bank2 */
 #define EBC0_BNCR_NAND_FLASH_CS2			\
-	EBC0_BNCR_BAS_ENCODE(0x94000000)    	| 	\
-	EBC0_BNCR_BS_1MB		    	|	\
-	EBC0_BNCR_BU_RW			    	|	\
+	EBC0_BNCR_BAS_ENCODE(0x94000000)	|	\
+	EBC0_BNCR_BS_1MB			|	\
+	EBC0_BNCR_BU_RW				|	\
 	EBC0_BNCR_BW_32BIT
 
 /* NAND1 - Bank3 */
 #define EBC0_BNCR_NAND_FLASH_CS3			\
-	EBC0_BNCR_BAS_ENCODE(0x94000000)    	| 	\
-	EBC0_BNCR_BS_1MB		    	|	\
-	EBC0_BNCR_BU_RW			    	|	\
+	EBC0_BNCR_BAS_ENCODE(0x94000000)	|	\
+	EBC0_BNCR_BS_1MB			|	\
+	EBC0_BNCR_BU_RW				|	\
 	EBC0_BNCR_BW_32BIT
 
 int board_early_init_f(void)
diff --git a/board/amcc/bamboo/u-boot-nand.lds b/board/amcc/bamboo/u-boot-nand.lds
index e5de203ca8..cbdc0b0500 100644
--- a/board/amcc/bamboo/u-boot-nand.lds
+++ b/board/amcc/bamboo/u-boot-nand.lds
@@ -31,11 +31,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/amcc/bamboo/u-boot.lds b/board/amcc/bamboo/u-boot.lds
index 53617b2e25..25d917a4f2 100644
--- a/board/amcc/bamboo/u-boot.lds
+++ b/board/amcc/bamboo/u-boot.lds
@@ -43,11 +43,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/amcc/bubinga/u-boot.lds b/board/amcc/bubinga/u-boot.lds
index f1b7ec70b9..d52b51ae1b 100644
--- a/board/amcc/bubinga/u-boot.lds
+++ b/board/amcc/bubinga/u-boot.lds
@@ -38,11 +38,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/amcc/canyonlands/u-boot-nand.lds b/board/amcc/canyonlands/u-boot-nand.lds
index 332e3aaf2a..8a4b7f5d0d 100644
--- a/board/amcc/canyonlands/u-boot-nand.lds
+++ b/board/amcc/canyonlands/u-boot-nand.lds
@@ -31,11 +31,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/amcc/canyonlands/u-boot.lds b/board/amcc/canyonlands/u-boot.lds
index f4c13f4529..1783bc73f9 100644
--- a/board/amcc/canyonlands/u-boot.lds
+++ b/board/amcc/canyonlands/u-boot.lds
@@ -43,11 +43,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/amcc/ebony/u-boot.lds b/board/amcc/ebony/u-boot.lds
index 557cae73ac..6be4bd1020 100644
--- a/board/amcc/ebony/u-boot.lds
+++ b/board/amcc/ebony/u-boot.lds
@@ -43,11 +43,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/amcc/katmai/katmai.c b/board/amcc/katmai/katmai.c
index e41caaf344..193083fd46 100644
--- a/board/amcc/katmai/katmai.c
+++ b/board/amcc/katmai/katmai.c
@@ -441,27 +441,27 @@ void pcie_setup_hoses(int busno)
 		pci_register_hose(hose);
 
 		if (is_end_point(i)) {
-		    	ppc4xx_setup_pcie_endpoint(hose, i);
+			ppc4xx_setup_pcie_endpoint(hose, i);
 			/*
 			 * Reson for no scanning is endpoint can not generate
 			 * upstream configuration accesses.
-		    	 */
+			 */
 		} else {
-		    	ppc4xx_setup_pcie_rootpoint(hose, i);
+			ppc4xx_setup_pcie_rootpoint(hose, i);
 			env = getenv ("pciscandelay");
-		    	if (env != NULL) {
-			    	delay = simple_strtoul(env, NULL, 10);
+			if (env != NULL) {
+				delay = simple_strtoul(env, NULL, 10);
 				if (delay > 5)
-				    	printf("Warning, expect noticable delay before "
+					printf("Warning, expect noticable delay before "
 					       "PCIe scan due to 'pciscandelay' value!\n");
 				mdelay(delay * 1000);
 			}
 
-		    	/*
-		     	 * Config access can only go down stream
-		     	 */
-		    	hose->last_busno = pci_hose_scan(hose);
-		    	bus = hose->last_busno + 1;
+			/*
+			 * Config access can only go down stream
+			 */
+			hose->last_busno = pci_hose_scan(hose);
+			bus = hose->last_busno + 1;
 		}
 	}
 }
diff --git a/board/amcc/kilauea/Makefile b/board/amcc/kilauea/Makefile
index b8da25ff42..39328c2bda 100644
--- a/board/amcc/kilauea/Makefile
+++ b/board/amcc/kilauea/Makefile
@@ -28,7 +28,7 @@ LIB	= $(obj)lib$(BOARD).a
 COBJS	= $(BOARD).o cmd_pll.o memory.o
 SOBJS	= init.o
 
-SRCS 	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
 
 $(LIB):	$(obj).depend $(OBJS)
diff --git a/board/amcc/kilauea/init.S b/board/amcc/kilauea/init.S
index 053fe19c07..8cd534cd6b 100644
--- a/board/amcc/kilauea/init.S
+++ b/board/amcc/kilauea/init.S
@@ -29,10 +29,10 @@
 #include <ppc_asm.tmpl>
 #include <ppc_defs.h>
 
-#define mtsdram_as(reg, value)	 	\
-	addi    r4,0,reg	;     	\
+#define mtsdram_as(reg, value)		\
+	addi    r4,0,reg	;	\
 	mtdcr   memcfga,r4	;	\
-	addis   r4,0,value@h 	;	\
+	addis   r4,0,value@h	;	\
 	ori     r4,r4,value@l	;	\
 	mtdcr   memcfgd,r4	;
 
diff --git a/board/amcc/kilauea/kilauea.c b/board/amcc/kilauea/kilauea.c
index d806a412eb..f30dc8f924 100644
--- a/board/amcc/kilauea/kilauea.c
+++ b/board/amcc/kilauea/kilauea.c
@@ -338,27 +338,27 @@ void pcie_setup_hoses(int busno)
 		pci_register_hose(hose);
 
 		if (is_end_point(i)) {
-		    	ppc4xx_setup_pcie_endpoint(hose, i);
+			ppc4xx_setup_pcie_endpoint(hose, i);
 			/*
 			 * Reson for no scanning is endpoint can not generate
 			 * upstream configuration accesses.
-		    	 */
+			 */
 		} else {
-		    	ppc4xx_setup_pcie_rootpoint(hose, i);
+			ppc4xx_setup_pcie_rootpoint(hose, i);
 			env = getenv ("pciscandelay");
-		    	if (env != NULL) {
-			    	delay = simple_strtoul(env, NULL, 10);
+			if (env != NULL) {
+				delay = simple_strtoul(env, NULL, 10);
 				if (delay > 5)
-				    	printf("Warning, expect noticable delay before "
+					printf("Warning, expect noticable delay before "
 					       "PCIe scan due to 'pciscandelay' value!\n");
 				mdelay(delay * 1000);
 			}
 
-		    	/*
-		     	 * Config access can only go down stream
-		     	 */
-		    	hose->last_busno = pci_hose_scan(hose);
-		    	bus = hose->last_busno + 1;
+			/*
+			 * Config access can only go down stream
+			 */
+			hose->last_busno = pci_hose_scan(hose);
+			bus = hose->last_busno + 1;
 		}
 	}
 }
diff --git a/board/amcc/kilauea/u-boot-nand.lds b/board/amcc/kilauea/u-boot-nand.lds
index e5de203ca8..cbdc0b0500 100644
--- a/board/amcc/kilauea/u-boot-nand.lds
+++ b/board/amcc/kilauea/u-boot-nand.lds
@@ -31,11 +31,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/amcc/kilauea/u-boot.lds b/board/amcc/kilauea/u-boot.lds
index b6ca3bc6a3..fe51ca1bff 100644
--- a/board/amcc/kilauea/u-boot.lds
+++ b/board/amcc/kilauea/u-boot.lds
@@ -42,11 +42,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/amcc/luan/u-boot.lds b/board/amcc/luan/u-boot.lds
index 0a476cf0ce..791178517d 100644
--- a/board/amcc/luan/u-boot.lds
+++ b/board/amcc/luan/u-boot.lds
@@ -43,11 +43,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/amcc/makalu/Makefile b/board/amcc/makalu/Makefile
index b8da25ff42..39328c2bda 100644
--- a/board/amcc/makalu/Makefile
+++ b/board/amcc/makalu/Makefile
@@ -28,7 +28,7 @@ LIB	= $(obj)lib$(BOARD).a
 COBJS	= $(BOARD).o cmd_pll.o memory.o
 SOBJS	= init.o
 
-SRCS 	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
 
 $(LIB):	$(obj).depend $(OBJS)
diff --git a/board/amcc/makalu/init.S b/board/amcc/makalu/init.S
index 5e9a5e08d3..11c5b1971e 100644
--- a/board/amcc/makalu/init.S
+++ b/board/amcc/makalu/init.S
@@ -29,10 +29,10 @@
 #include <ppc_asm.tmpl>
 #include <ppc_defs.h>
 
-#define mtsdram_as(reg, value)	 	\
-	addi    r4,0,reg	;     	\
+#define mtsdram_as(reg, value)		\
+	addi    r4,0,reg	;	\
 	mtdcr   memcfga,r4	;	\
-	addis   r4,0,value@h 	;	\
+	addis   r4,0,value@h	;	\
 	ori     r4,r4,value@l	;	\
 	mtdcr   memcfgd,r4	;
 
diff --git a/board/amcc/makalu/makalu.c b/board/amcc/makalu/makalu.c
index 25dd715a6f..9baec9af67 100644
--- a/board/amcc/makalu/makalu.c
+++ b/board/amcc/makalu/makalu.c
@@ -294,27 +294,27 @@ void pcie_setup_hoses(int busno)
 		pci_register_hose(hose);
 
 		if (is_end_point(i)) {
-		    	ppc4xx_setup_pcie_endpoint(hose, i);
+			ppc4xx_setup_pcie_endpoint(hose, i);
 			/*
 			 * Reson for no scanning is endpoint can not generate
 			 * upstream configuration accesses.
-		    	 */
+			 */
 		} else {
-		    	ppc4xx_setup_pcie_rootpoint(hose, i);
+			ppc4xx_setup_pcie_rootpoint(hose, i);
 			env = getenv ("pciscandelay");
-		    	if (env != NULL) {
-			    	delay = simple_strtoul(env, NULL, 10);
+			if (env != NULL) {
+				delay = simple_strtoul(env, NULL, 10);
 				if (delay > 5)
-				    	printf("Warning, expect noticable delay before "
+					printf("Warning, expect noticable delay before "
 					       "PCIe scan due to 'pciscandelay' value!\n");
 				mdelay(delay * 1000);
 			}
 
-		    	/*
-		     	 * Config access can only go down stream
-		     	 */
-		    	hose->last_busno = pci_hose_scan(hose);
-		    	bus = hose->last_busno + 1;
+			/*
+			 * Config access can only go down stream
+			 */
+			hose->last_busno = pci_hose_scan(hose);
+			bus = hose->last_busno + 1;
 		}
 	}
 }
diff --git a/board/amcc/makalu/u-boot.lds b/board/amcc/makalu/u-boot.lds
index b6ca3bc6a3..fe51ca1bff 100644
--- a/board/amcc/makalu/u-boot.lds
+++ b/board/amcc/makalu/u-boot.lds
@@ -42,11 +42,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/amcc/ocotea/u-boot.lds b/board/amcc/ocotea/u-boot.lds
index 76d1aefa22..298aba82d1 100644
--- a/board/amcc/ocotea/u-boot.lds
+++ b/board/amcc/ocotea/u-boot.lds
@@ -43,11 +43,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/amcc/sequoia/u-boot-nand.lds b/board/amcc/sequoia/u-boot-nand.lds
index 94dd7543cc..ae2e18de4e 100644
--- a/board/amcc/sequoia/u-boot-nand.lds
+++ b/board/amcc/sequoia/u-boot-nand.lds
@@ -31,11 +31,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/amcc/sequoia/u-boot.lds b/board/amcc/sequoia/u-boot.lds
index da2a400b77..b20fb1c0a2 100644
--- a/board/amcc/sequoia/u-boot.lds
+++ b/board/amcc/sequoia/u-boot.lds
@@ -43,11 +43,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/amcc/taihu/u-boot.lds b/board/amcc/taihu/u-boot.lds
index f1b7ec70b9..d52b51ae1b 100644
--- a/board/amcc/taihu/u-boot.lds
+++ b/board/amcc/taihu/u-boot.lds
@@ -38,11 +38,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/amcc/taishan/u-boot.lds b/board/amcc/taishan/u-boot.lds
index a0e9e96565..85d3759382 100644
--- a/board/amcc/taishan/u-boot.lds
+++ b/board/amcc/taishan/u-boot.lds
@@ -43,11 +43,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/amcc/walnut/u-boot.lds b/board/amcc/walnut/u-boot.lds
index c36346aa85..5d07e44389 100644
--- a/board/amcc/walnut/u-boot.lds
+++ b/board/amcc/walnut/u-boot.lds
@@ -38,11 +38,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/amcc/yosemite/u-boot.lds b/board/amcc/yosemite/u-boot.lds
index 92cf177f11..c12aad7e32 100644
--- a/board/amcc/yosemite/u-boot.lds
+++ b/board/amcc/yosemite/u-boot.lds
@@ -43,11 +43,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/amcc/yucca/yucca.c b/board/amcc/yucca/yucca.c
index 52486cc4c9..11d1743355 100644
--- a/board/amcc/yucca/yucca.c
+++ b/board/amcc/yucca/yucca.c
@@ -737,27 +737,27 @@ void yucca_setup_pcie_fpga_rootpoint(int port)
 	case 0:
 		rootpoint   = FPGA_REG1C_PE0_ROOTPOINT;
 		endpoint    = 0;
-		power 	    = FPGA_REG1A_PE0_PWRON;
+		power	    = FPGA_REG1A_PE0_PWRON;
 		green_led   = FPGA_REG1A_PE0_GLED;
-		clock 	    = FPGA_REG1A_PE0_REFCLK_ENABLE;
+		clock	    = FPGA_REG1A_PE0_REFCLK_ENABLE;
 		yellow_led  = FPGA_REG1A_PE0_YLED;
 		reset_off   = FPGA_REG1C_PE0_PERST;
 		break;
 	case 1:
 		rootpoint   = 0;
 		endpoint    = FPGA_REG1C_PE1_ENDPOINT;
-		power 	    = FPGA_REG1A_PE1_PWRON;
+		power	    = FPGA_REG1A_PE1_PWRON;
 		green_led   = FPGA_REG1A_PE1_GLED;
-		clock 	    = FPGA_REG1A_PE1_REFCLK_ENABLE;
+		clock	    = FPGA_REG1A_PE1_REFCLK_ENABLE;
 		yellow_led  = FPGA_REG1A_PE1_YLED;
 		reset_off   = FPGA_REG1C_PE1_PERST;
 		break;
 	case 2:
 		rootpoint   = 0;
 		endpoint    = FPGA_REG1C_PE2_ENDPOINT;
-		power 	    = FPGA_REG1A_PE2_PWRON;
+		power	    = FPGA_REG1A_PE2_PWRON;
 		green_led   = FPGA_REG1A_PE2_GLED;
-		clock 	    = FPGA_REG1A_PE2_REFCLK_ENABLE;
+		clock	    = FPGA_REG1A_PE2_REFCLK_ENABLE;
 		yellow_led  = FPGA_REG1A_PE2_YLED;
 		reset_off   = FPGA_REG1C_PE2_PERST;
 		break;
@@ -794,27 +794,27 @@ void yucca_setup_pcie_fpga_endpoint(int port)
 	case 0:
 		rootpoint   = FPGA_REG1C_PE0_ROOTPOINT;
 		endpoint    = 0;
-		power 	    = FPGA_REG1A_PE0_PWRON;
+		power	    = FPGA_REG1A_PE0_PWRON;
 		green_led   = FPGA_REG1A_PE0_GLED;
-		clock 	    = FPGA_REG1A_PE0_REFCLK_ENABLE;
+		clock	    = FPGA_REG1A_PE0_REFCLK_ENABLE;
 		yellow_led  = FPGA_REG1A_PE0_YLED;
 		reset_off   = FPGA_REG1C_PE0_PERST;
 		break;
 	case 1:
 		rootpoint   = 0;
 		endpoint    = FPGA_REG1C_PE1_ENDPOINT;
-		power 	    = FPGA_REG1A_PE1_PWRON;
+		power	    = FPGA_REG1A_PE1_PWRON;
 		green_led   = FPGA_REG1A_PE1_GLED;
-		clock 	    = FPGA_REG1A_PE1_REFCLK_ENABLE;
+		clock	    = FPGA_REG1A_PE1_REFCLK_ENABLE;
 		yellow_led  = FPGA_REG1A_PE1_YLED;
 		reset_off   = FPGA_REG1C_PE1_PERST;
 		break;
 	case 2:
 		rootpoint   = 0;
 		endpoint    = FPGA_REG1C_PE2_ENDPOINT;
-		power 	    = FPGA_REG1A_PE2_PWRON;
+		power	    = FPGA_REG1A_PE2_PWRON;
 		green_led   = FPGA_REG1A_PE2_GLED;
-		clock 	    = FPGA_REG1A_PE2_REFCLK_ENABLE;
+		clock	    = FPGA_REG1A_PE2_REFCLK_ENABLE;
 		yellow_led  = FPGA_REG1A_PE2_YLED;
 		reset_off   = FPGA_REG1C_PE2_PERST;
 		break;
@@ -884,21 +884,21 @@ void pcie_setup_hoses(int busno)
 			/*
 			 * Reson for no scanning is endpoint can not generate
 			 * upstream configuration accesses.
-		 	 */
+			 */
 		} else {
 			ppc4xx_setup_pcie_rootpoint(hose, i);
 			env = getenv("pciscandelay");
 			if (env != NULL) {
 				delay = simple_strtoul(env, NULL, 10);
 				if (delay > 5)
-				    	printf("Warning, expect noticable delay before "
+					printf("Warning, expect noticable delay before "
 					       "PCIe scan due to 'pciscandelay' value!\n");
 				mdelay(delay * 1000);
 			}
 
 			/*
 			 * Config access can only go down stream
-		 	 */
+			 */
 			hose->last_busno = pci_hose_scan(hose);
 			bus = hose->last_busno + 1;
 		}
diff --git a/board/amirix/ap1000/u-boot.lds b/board/amirix/ap1000/u-boot.lds
index 766e2bbcea..a939e03311 100644
--- a/board/amirix/ap1000/u-boot.lds
+++ b/board/amirix/ap1000/u-boot.lds
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/apollon/apollon.c b/board/apollon/apollon.c
index 383b0643f8..7e39817a0f 100644
--- a/board/apollon/apollon.c
+++ b/board/apollon/apollon.c
@@ -140,7 +140,7 @@ void wait_for_command_complete(unsigned int wd_base)
 /*******************************************************************
  * Routine:ether_init
  * Description: take the Ethernet controller out of reset and wait
- *  		   for the EEPROM load to complete.
+ *		   for the EEPROM load to complete.
  ******************************************************************/
 void ether_init(void)
 {
diff --git a/board/armadillo/lowlevel_init.S b/board/armadillo/lowlevel_init.S
index 6cf642611c..e7d373d274 100644
--- a/board/armadillo/lowlevel_init.S
+++ b/board/armadillo/lowlevel_init.S
@@ -29,8 +29,8 @@
 
 /* some parameters for the board */
 /* setting up the memory */
-#define 	SRAM_START 	0x60000000
-#define 	SRAM_SIZE	0x0000c000
+#define	SRAM_START	0x60000000
+#define	SRAM_SIZE	0x0000c000
 
 .globl lowlevel_init
 lowlevel_init:
diff --git a/board/assabet/assabet.c b/board/assabet/assabet.c
index 4f84a58117..6f02db29b8 100644
--- a/board/assabet/assabet.c
+++ b/board/assabet/assabet.c
@@ -46,7 +46,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define ECSR_PWRDWN		0x04
 #define ECSR_INT		0x02
 #define SMC_IO_SHIFT		2
-#define NCR_0           	(*((volatile u_char *)(0x100000a0)))
+#define NCR_0			(*((volatile u_char *)(0x100000a0)))
 #define NCR_ENET_OSC_EN		(1<<3)
 
 static inline u8
diff --git a/board/atmel/at91sam9260ek/at91sam9260ek.c b/board/atmel/at91sam9260ek/at91sam9260ek.c
index 21479acab4..b30aad8373 100644
--- a/board/atmel/at91sam9260ek/at91sam9260ek.c
+++ b/board/atmel/at91sam9260ek/at91sam9260ek.c
@@ -126,7 +126,7 @@ static void at91sam9260ek_macb_hw_init(void)
 	/*
 	 * Disable pull-up on:
 	 *	RXDV (PA17) => PHY normal mode (not Test mode)
-	 * 	ERX0 (PA14) => PHY ADDR0
+	 *	ERX0 (PA14) => PHY ADDR0
 	 *	ERX1 (PA15) => PHY ADDR1
 	 *	ERX2 (PA25) => PHY ADDR2
 	 *	ERX3 (PA26) => PHY ADDR3
diff --git a/board/atum8548/u-boot.lds b/board/atum8548/u-boot.lds
index dd5375b19e..46c45d7711 100644
--- a/board/atum8548/u-boot.lds
+++ b/board/atum8548/u-boot.lds
@@ -42,11 +42,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/barco/speed.h b/board/barco/speed.h
index 46860e840e..e883dfb2ed 100644
--- a/board/barco/speed.h
+++ b/board/barco/speed.h
@@ -52,10 +52,10 @@
  * SPEED_TMR3_PS = (GCLK / (16 * SPEED_FCOUNT3)) - 1
  *
  * SPEED_FCOUNT2	timer 2 counting frequency
- * GCLK	      		CPU clock
+ * GCLK			CPU clock
  * SPEED_TMR2_PS	prescaler
  */
-#define SPEED_TMR2_PS  	(250 - 1)	/* divide by 250	*/
+#define SPEED_TMR2_PS	(250 - 1)	/* divide by 250	*/
 
 /*-----------------------------------------------------------------------
  * Timer value for PIT
diff --git a/board/bc3450/cmd_bc3450.c b/board/bc3450/cmd_bc3450.c
index 1455953078..f7f0013c7d 100644
--- a/board/bc3450/cmd_bc3450.c
+++ b/board/bc3450/cmd_bc3450.c
@@ -69,7 +69,7 @@ struct therm {
 #define SM501_POWER_MODE0_GATE		0x00000040UL
 #define SM501_POWER_MODE1_GATE		0x00000048UL
 #define POWER_MODE_GATE_GPIO_PWM_I2C	0x00000040UL
-#define SM501_GPIO_DATA_LOW 		0x00010000UL
+#define SM501_GPIO_DATA_LOW		0x00010000UL
 #define SM501_GPIO_DATA_HIGH		0x00010004UL
 #define SM501_GPIO_DATA_DIR_LOW		0x00010008UL
 #define SM501_GPIO_DATA_DIR_HIGH	0x0001000CUL
diff --git a/board/bf533-ezkit/flash-defines.h b/board/bf533-ezkit/flash-defines.h
index bd9e859e70..4e043e072b 100644
--- a/board/bf533-ezkit/flash-defines.h
+++ b/board/bf533-ezkit/flash-defines.h
@@ -44,11 +44,11 @@
 #define ERASE_SECT		6
 #define READ			7
 #define GET_SECTNUM		8
-#define FLASH_START_L 		0x0000
-#define FLASH_START_H 		0x2000
+#define FLASH_START_L		0x0000
+#define FLASH_START_H		0x2000
 #define FLASH_TOT_SECT		40
-#define FLASH_SIZE 		0x220000
-#define FLASH_MAN_ST 		2
+#define FLASH_SIZE		0x220000
+#define FLASH_MAN_ST		2
 #define CFG_FLASH0_BASE		0x20000000
 #define RESET_VAL		0xF0
 
diff --git a/board/bf533-stamp/bf533-stamp.h b/board/bf533-stamp/bf533-stamp.h
index 1e58e47546..3b0d620b3c 100644
--- a/board/bf533-stamp/bf533-stamp.h
+++ b/board/bf533-stamp/bf533-stamp.h
@@ -38,13 +38,13 @@ extern unsigned long pll_div_fact;
 extern void serial_setbrg(void);
 
 /* Definitions used in  Compact Flash Boot support */
-#define FIO_EDGE_CF_BITS 	0x0000
-#define FIO_POLAR_CF_BITS 	0x0000
-#define	FIO_EDGE_BITS  		0x1E0
-#define	FIO_POLAR_BITS  	0x160
+#define FIO_EDGE_CF_BITS	0x0000
+#define FIO_POLAR_CF_BITS	0x0000
+#define	FIO_EDGE_BITS		0x1E0
+#define	FIO_POLAR_BITS		0x160
 
 /* Compact flash status bits in status register */
-#define CF_STAT_BITS 		0x00000060
+#define CF_STAT_BITS		0x00000060
 
 /* CF Flags used to switch between expansion and external
  * memory banks
diff --git a/board/bmw/README b/board/bmw/README
index 70bc81362f..1f04b1b8a1 100644
--- a/board/bmw/README
+++ b/board/bmw/README
@@ -89,7 +89,7 @@ Interrupt Mappings
 BMW uses MPC8245 discrete mode interrupts. With the following
 hardwired mappings:
 
-BCM5701 10/100/1000 Ethernet 		IRQ1
+BCM5701 10/100/1000 Ethernet		IRQ1
 CompactPCI Interrupt A			IRQ2
 RTC/Watchdog Interrupt			IRQ3
 Internal NS16552 UART			IRQ4
diff --git a/board/bmw/early_init.S b/board/bmw/early_init.S
index e6400c3088..57a06a91f6 100644
--- a/board/bmw/early_init.S
+++ b/board/bmw/early_init.S
@@ -246,7 +246,7 @@ early_init_f:
 #if 1	/* Turn off floating point (remove to keep FP on) */
 	andi.	r3, r3, 0
 	sync
-	mtmsr 	r3
+	mtmsr	r3
 	isync
 #endif
 
@@ -1137,7 +1137,7 @@ early_init_f:
 	/* delay */
 	lis     r7, 1
 	mtctr   r7
-label1: 	bdnz    label1
+label1:	bdnz    label1
 
 	/* Set memgo bit */
 	/* MCCR1 */
@@ -1151,7 +1151,7 @@ label1: 	bdnz    label1
 	/* delay again */
 	lis     r7, 1
 	mtctr   r7
-label2: 	bdnz    label2
+label2:	bdnz    label2
 #if 0
 /* DEBUG: Infinite loop, write then read */
 loop:
diff --git a/board/c2mon/pcmcia.c b/board/c2mon/pcmcia.c
index c389c6778b..57846b10cf 100644
--- a/board/c2mon/pcmcia.c
+++ b/board/c2mon/pcmcia.c
@@ -235,14 +235,14 @@ int pcmcia_voltage_set(int slot, int vcc, int vpp)
 	sreg |= TPS2211_VPPD0 | TPS2211_VPPD1;		/* VAVPP always Hi-Z */
 
 	switch(vcc) {
-		case  0: 			break;	/* Switch off		*/
+		case  0:			break;	/* Switch off		*/
 		case 33: sreg |=  TPS2211_VCCD0;	/* Switch on 3.3V	*/
 		sreg &= ~TPS2211_VCCD1;
 		break;
 		case 50: sreg &= ~TPS2211_VCCD0;	/* Switch on 5.0V	*/
 		sreg |=  TPS2211_VCCD1;
 		break;
-		default: 			goto done;
+		default:			goto done;
 	}
 
 	/* Checking supported voltages */
diff --git a/board/c2mon/u-boot.lds b/board/c2mon/u-boot.lds
index ee598c2cfc..10b38ec356 100644
--- a/board/c2mon/u-boot.lds
+++ b/board/c2mon/u-boot.lds
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/c2mon/u-boot.lds.debug b/board/c2mon/u-boot.lds.debug
index 1a25a98f17..85072feda4 100644
--- a/board/c2mon/u-boot.lds.debug
+++ b/board/c2mon/u-boot.lds.debug
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/cerf250/lowlevel_init.S b/board/cerf250/lowlevel_init.S
index c9b68d7ff3..ad3c59f9fb 100644
--- a/board/cerf250/lowlevel_init.S
+++ b/board/cerf250/lowlevel_init.S
@@ -40,7 +40,7 @@ DRAM_SIZE:  .long   CFG_DRAM_SIZE
 
 
 /*
- * 	Memory setup
+ *	Memory setup
  */
 
 .globl lowlevel_init
@@ -48,69 +48,69 @@ lowlevel_init:
 
 	/* Set up GPIO pins first ----------------------------------------- */
 
-	ldr		r0,	=GPSR0
-	ldr		r1,	=CFG_GPSR0_VAL
-	str		r1,	[r0]
+	ldr	r0, =GPSR0
+	ldr	r1, =CFG_GPSR0_VAL
+	str	r1, [r0]
 
-	ldr		r0,	=GPSR1
-	ldr		r1,	=CFG_GPSR1_VAL
-	str		r1,  [r0]
+	ldr	r0, =GPSR1
+	ldr	r1, =CFG_GPSR1_VAL
+	str	r1, [r0]
 
-	ldr		r0,	=GPSR2
-	ldr		r1,	=CFG_GPSR2_VAL
-	str		r1,	[r0]
+	ldr	r0, =GPSR2
+	ldr	r1, =CFG_GPSR2_VAL
+	str	r1, [r0]
 
-	ldr		r0,	=GPCR0
-	ldr		r1,	=CFG_GPCR0_VAL
-	str		r1,	[r0]
+	ldr	r0, =GPCR0
+	ldr	r1, =CFG_GPCR0_VAL
+	str	r1, [r0]
 
-	ldr		r0,	=GPCR1
-	ldr		r1,	=CFG_GPCR1_VAL
-	str		r1,	[r0]
+	ldr	r0, =GPCR1
+	ldr	r1, =CFG_GPCR1_VAL
+	str	r1, [r0]
 
-	ldr		r0,	=GPCR2
-	ldr		r1,	=CFG_GPCR2_VAL
-	str		r1,	[r0]
+	ldr	r0, =GPCR2
+	ldr	r1, =CFG_GPCR2_VAL
+	str	r1, [r0]
 
-	ldr		r0,	=GPDR0
-	ldr		r1,	=CFG_GPDR0_VAL
-	str		r1,	[r0]
+	ldr	r0, =GPDR0
+	ldr	r1, =CFG_GPDR0_VAL
+	str	r1, [r0]
 
-	ldr		r0,	=GPDR1
-	ldr		r1,	=CFG_GPDR1_VAL
-	str		r1,	[r0]
+	ldr	r0, =GPDR1
+	ldr	r1, =CFG_GPDR1_VAL
+	str	r1, [r0]
 
-	ldr		r0,	=GPDR2
-	ldr		r1,	=CFG_GPDR2_VAL
-	str		r1,	[r0]
+	ldr	r0, =GPDR2
+	ldr	r1, =CFG_GPDR2_VAL
+	str	r1, [r0]
 
-	ldr		r0,	=GAFR0_L
-	ldr		r1,	=CFG_GAFR0_L_VAL
-	str		r1,	[r0]
+	ldr	r0, =GAFR0_L
+	ldr	r1, =CFG_GAFR0_L_VAL
+	str	r1, [r0]
 
-	ldr		r0,	=GAFR0_U
-	ldr		r1,	=CFG_GAFR0_U_VAL
-	str		r1,	[r0]
+	ldr	r0, =GAFR0_U
+	ldr	r1, =CFG_GAFR0_U_VAL
+	str	r1, [r0]
 
-	ldr		r0,	=GAFR1_L
-	ldr		r1,	=CFG_GAFR1_L_VAL
-	str		r1,	[r0]
+	ldr	r0, =GAFR1_L
+	ldr	r1, =CFG_GAFR1_L_VAL
+	str	r1, [r0]
 
-	ldr		r0,	=GAFR1_U
-	ldr		r1,	=CFG_GAFR1_U_VAL
-	str		r1,	[r0]
+	ldr	r0, =GAFR1_U
+	ldr	r1, =CFG_GAFR1_U_VAL
+	str	r1, [r0]
 
-	ldr		r0,	=GAFR2_L
-	ldr		r1,	=CFG_GAFR2_L_VAL
-	str		r1,	[r0]
+	ldr	r0, =GAFR2_L
+	ldr	r1, =CFG_GAFR2_L_VAL
+	str	r1, [r0]
 
-	ldr		r0,	=GAFR2_U
-	ldr		r1,	=CFG_GAFR2_U_VAL
-	str		r1,	[r0]
+	ldr	r0, =GAFR2_U
+	ldr	r1, =CFG_GAFR2_U_VAL
+	str	r1, [r0]
 
-	ldr		r0,	=PSSR				/* enable GPIO pins */
-	ldr		r1,	=CFG_PSSR_VAL
-	str		r1,	[r0]
+	ldr	r0, =PSSR			/* enable GPIO pins */
+	ldr	r1, =CFG_PSSR_VAL
+	str	r1, [r0]
 
 	/* ---------------------------------------------------------------- */
 	/* Enable memory interface                                          */
@@ -126,19 +126,19 @@ lowlevel_init:
 	/*         FIXME: can be optimized later                            */
 	/* ---------------------------------------------------------------- */
 
-	ldr		r3,	=OSCR			/* reset the OS Timer Count to zero */
-	mov 	r2,	#0
-	str 	r2,	[r3]
-	ldr 	r4,	=0x300				/* really 0x2E1 is about 200usec,   */
-							/* so 0x300 should be plenty        */
+	ldr	r3, =OSCR			/* reset the OS Timer Count to zero */
+	mov	r2, #0
+	str	r2, [r3]
+	ldr	r4, =0x300			/* really 0x2E1 is about 200usec,   */
+						/* so 0x300 should be plenty        */
 1:
-	ldr 	r2,	[r3]
-	cmp 	r4,	r2
-	bgt 	1b
+	ldr	r2, [r3]
+	cmp	r4, r2
+	bgt	1b
 
 mem_init:
 
-	ldr  	r1,	=MEMC_BASE		/* get memory controller base addr. */
+	ldr	r1, =MEMC_BASE			/* get memory controller base addr. */
 
 	/* ---------------------------------------------------------------- */
 	/* Step 2a: Initialize Asynchronous static memory controller        */
@@ -147,58 +147,58 @@ mem_init:
 	/* MSC registers: timing, bus width, mem type                       */
 
 	/* MSC0: nCS(0,1)                                                   */
-	ldr  	r2,	=CFG_MSC0_VAL
-	str  	r2,	[r1, #MSC0_OFFSET]
-	ldr  	r2,	[r1, #MSC0_OFFSET]	/* read back to ensure      */
+	ldr	r2, =CFG_MSC0_VAL
+	str	r2, [r1, #MSC0_OFFSET]
+	ldr	r2, [r1, #MSC0_OFFSET]		/* read back to ensure      */
 						/* that data latches        */
 	/* MSC1: nCS(2,3)                                                   */
-	ldr  	r2,	=CFG_MSC1_VAL
-	str  	r2,	[r1, #MSC1_OFFSET]
-	ldr  	r2,	[r1, #MSC1_OFFSET]
+	ldr	r2, =CFG_MSC1_VAL
+	str	r2, [r1, #MSC1_OFFSET]
+	ldr	r2, [r1, #MSC1_OFFSET]
 
 	/* MSC2: nCS(4,5)                                                   */
-	ldr  	r2,	=CFG_MSC2_VAL
-	str  	r2,	[r1, #MSC2_OFFSET]
-	ldr  	r2,	[r1, #MSC2_OFFSET]
+	ldr	r2, =CFG_MSC2_VAL
+	str	r2, [r1, #MSC2_OFFSET]
+	ldr	r2, [r1, #MSC2_OFFSET]
 
 	/* ---------------------------------------------------------------- */
 	/* Step 2b: Initialize Card Interface                               */
 	/* ---------------------------------------------------------------- */
 
 	/* MECR: Memory Expansion Card Register                             */
-	ldr  	r2,	=CFG_MECR_VAL
-	str  	r2,	[r1, #MECR_OFFSET]
-	ldr	 	r2,	[r1, #MECR_OFFSET]
+	ldr	r2, =CFG_MECR_VAL
+	str	r2, [r1, #MECR_OFFSET]
+	ldr	r2, [r1, #MECR_OFFSET]
 
 	/* MCMEM0: Card Interface slot 0 timing                             */
-	ldr  	r2,	=CFG_MCMEM0_VAL
-	str  	r2,	[r1, #MCMEM0_OFFSET]
-	ldr	 	r2,	[r1, #MCMEM0_OFFSET]
+	ldr	r2, =CFG_MCMEM0_VAL
+	str	r2, [r1, #MCMEM0_OFFSET]
+	ldr	r2, [r1, #MCMEM0_OFFSET]
 
 	/* MCMEM1: Card Interface slot 1 timing                             */
-	ldr  	r2,	=CFG_MCMEM1_VAL
-	str  	r2,	[r1, #MCMEM1_OFFSET]
-	ldr	 	r2,	[r1, #MCMEM1_OFFSET]
+	ldr	r2, =CFG_MCMEM1_VAL
+	str	r2, [r1, #MCMEM1_OFFSET]
+	ldr	r2, [r1, #MCMEM1_OFFSET]
 
 	/* MCATT0: Card Interface Attribute Space Timing, slot 0            */
-	ldr  	r2,	=CFG_MCATT0_VAL
-	str  	r2,	[r1, #MCATT0_OFFSET]
-	ldr	 	r2,	[r1, #MCATT0_OFFSET]
+	ldr	r2, =CFG_MCATT0_VAL
+	str	r2, [r1, #MCATT0_OFFSET]
+	ldr	r2, [r1, #MCATT0_OFFSET]
 
 	/* MCATT1: Card Interface Attribute Space Timing, slot 1            */
-	ldr  	r2, =CFG_MCATT1_VAL
-	str  	r2, [r1, #MCATT1_OFFSET]
-	ldr	 	r2,	[r1, #MCATT1_OFFSET]
+	ldr	r2, =CFG_MCATT1_VAL
+	str	r2, [r1, #MCATT1_OFFSET]
+	ldr	r2, [r1, #MCATT1_OFFSET]
 
 	/* MCIO0: Card Interface I/O Space Timing, slot 0                   */
-	ldr  	r2, =CFG_MCIO0_VAL
-	str  	r2, [r1, #MCIO0_OFFSET]
-	ldr	 	r2,	[r1, #MCIO0_OFFSET]
+	ldr	r2, =CFG_MCIO0_VAL
+	str	r2, [r1, #MCIO0_OFFSET]
+	ldr	r2, [r1, #MCIO0_OFFSET]
 
 	/* MCIO1: Card Interface I/O Space Timing, slot 1                   */
-	ldr  	r2, =CFG_MCIO1_VAL
-	str  	r2, [r1, #MCIO1_OFFSET]
-	ldr	 	r2,	[r1, #MCIO1_OFFSET]
+	ldr	r2, =CFG_MCIO1_VAL
+	str	r2, [r1, #MCIO1_OFFSET]
+	ldr	r2, [r1, #MCIO1_OFFSET]
 
 	/* ---------------------------------------------------------------- */
 	/* Step 2c: Write FLYCNFG  FIXME: what's that???                    */
@@ -212,16 +212,16 @@ mem_init:
 	/* Before accessing MDREFR we need a valid DRI field, so we set     */
 	/* this to power on defaults + DRI field, set SDRAM clocks free running */
 
-	ldr  	r3, =CFG_MDREFR_VAL
-	ldr  	r2, =0xFFF
-	and  	r3, r3,  r2
+	ldr	r3, =CFG_MDREFR_VAL
+	ldr	r2, =0xFFF
+	and	r3, r3,  r2
 
-	ldr	 	r0,	[r1, #MDREFR_OFFSET]
-	bic	 	r0, r0, r2
-	bic	 	r0, r0, #(MDREFR_K0FREE|MDREFR_K1FREE|MDREFR_K2FREE)
-	orr	 	r0, r0, r3
+	ldr	r0, [r1, #MDREFR_OFFSET]
+	bic	r0, r0, r2
+	bic	r0, r0, #(MDREFR_K0FREE|MDREFR_K1FREE|MDREFR_K2FREE)
+	orr	r0, r0, r3
 
-	str		r0,	[r1, #MDREFR_OFFSET]	/* write back MDREFR        */
+	str	r0, [r1, #MDREFR_OFFSET]	/* write back MDREFR        */
 
 
 	/* ---------------------------------------------------------------- */
@@ -244,18 +244,18 @@ mem_init:
 	/* set MDREFR according to user define with exception of a few bits */
 
 	ldr     r4, =CFG_MDREFR_VAL
-	ldr		r2, =(MDREFR_K0RUN|MDREFR_K0DB2|MDREFR_K1RUN|MDREFR_K1DB2|\
+	ldr	r2, =(MDREFR_K0RUN|MDREFR_K0DB2|MDREFR_K1RUN|MDREFR_K1DB2|\
 					MDREFR_K2RUN |MDREFR_K2DB2)
-	and		r4, r4, r2
-	bic		r0,	r0,	r2
-	orr		r0, r0, r4
+	and	r4, r4, r2
+	bic	r0, r0, r2
+	orr	r0, r0, r4
 
 	str     r0, [r1, #MDREFR_OFFSET]    /* write back MDREFR        */
 	ldr     r0, [r1, #MDREFR_OFFSET]
 
 	/* Step 4b: de-assert MDREFR:SLFRSH.                                */
 
-	bic		r0, r0,	#(MDREFR_SLFRSH)
+	bic	r0, r0, #(MDREFR_SLFRSH)
 	str     r0, [r1, #MDREFR_OFFSET]    /* write back MDREFR        */
 	ldr     r0, [r1, #MDREFR_OFFSET]
 
@@ -263,10 +263,10 @@ mem_init:
 	/* Step 4c: assert MDREFR:E1PIN and E0PIO as desired, set KXFREE  */
 
 	ldr     r4, =CFG_MDREFR_VAL
-	ldr		r2, =(MDREFR_E0PIN|MDREFR_E1PIN|MDREFR_K0FREE| \
-					MDREFR_K1FREE | MDREFR_K2FREE)
-	and		r4, r4, r2
-	orr		r0, r0, r4
+	ldr	r2, =(MDREFR_E0PIN|MDREFR_E1PIN|MDREFR_K0FREE| \
+			MDREFR_K1FREE | MDREFR_K2FREE)
+	and	r4, r4, r2
+	orr	r0, r0, r4
 	str     r0, [r1, #MDREFR_OFFSET]    /* write back MDREFR        */
 	ldr     r0, [r1, #MDREFR_OFFSET]
 
@@ -274,9 +274,9 @@ mem_init:
 	/* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to  */
 	/*          configure but not enable each SDRAM partition pair.     */
 
-	ldr		r4,	=CFG_MDCNFG_VAL
-	bic		r4,	r4,	#(MDCNFG_DE0|MDCNFG_DE1)
-	bic		r4, r4,	#(MDCNFG_DE2|MDCNFG_DE3)
+	ldr	r4, =CFG_MDCNFG_VAL
+	bic	r4, r4, #(MDCNFG_DE0|MDCNFG_DE1)
+	bic	r4, r4, #(MDCNFG_DE2|MDCNFG_DE3)
 	str     r4, [r1, #MDCNFG_OFFSET]	/* write back MDCNFG        */
 	ldr     r4, [r1, #MDCNFG_OFFSET]
 
@@ -284,15 +284,15 @@ mem_init:
 	/* Step 4e: Wait for the clock to the SDRAMs to stabilize,          */
 	/*          100..200 µsec.                                          */
 
-	ldr 	r3, =OSCR			/* reset the OS Timer Count to zero */
-	mov 	r2, #0
-	str 	r2, [r3]
-	ldr 	r4, =0x300			/* really 0x2E1 is about 200usec,   */
+	ldr	r3, =OSCR			/* reset the OS Timer Count to zero */
+	mov	r2, #0
+	str	r2, [r3]
+	ldr	r4, =0x300			/* really 0x2E1 is about 200usec,   */
 						/* so 0x300 should be plenty        */
 1:
-	ldr 	r2, [r3]
-	cmp 	r4, r2
-	bgt 	1b
+	ldr	r2, [r3]
+	cmp	r4, r2
+	bgt	1b
 
 
 	/* Step 4f: Trigger a number (usually 8) refresh cycles by          */
@@ -301,16 +301,16 @@ mem_init:
 	/*          documented in SDRAM data sheets. The address(es) used   */
 	/*          for this purpose must not be cacheable.                 */
 
-	ldr		r3,	=CFG_DRAM_BASE
+	ldr	r3, =CFG_DRAM_BASE
 .rept 8
-	str		r2,	[r3]
+	str	r2, [r3]
 .endr
 
 	/* Step 4g: Write MDCNFG with enable bits asserted                  */
 	/*          (MDCNFG:DEx set to 1).                                  */
 
 	ldr     r3, [r1, #MDCNFG_OFFSET]
-	orr	r3,	r3,	#(MDCNFG_DE0|MDCNFG_DE1)
+	orr	r3, r3, #(MDCNFG_DE0|MDCNFG_DE1)
 	str     r3, [r1, #MDCNFG_OFFSET]
 
 	/* Step 4h: Write MDMRS.                                            */
@@ -378,27 +378,27 @@ initclks:
 	/* ---------------------------------------------------------------- */
 
 	/* Save SDRAM size */
-    ldr     r1, =DRAM_SIZE
-	str   	r8, [r1]
+	ldr     r1, =DRAM_SIZE
+	str	r8, [r1]
 
 	/* Interrupt init: Mask all interrupts                              */
-    ldr		r0,	=ICMR /* enable no sources */
-	mov 	r1,	#0
-    str 	r1,	[r0]
+	ldr	r0, =ICMR /* enable no sources */
+	mov	r1, #0
+	str	r1, [r0]
 
 	/* FIXME */
 
 #define NODEBUG
 #ifdef NODEBUG
 	/*Disable software and data breakpoints */
-	mov		r0,#0
-	mcr		p15,0,r0,c14,c8,0  /* ibcr0 */
-	mcr		p15,0,r0,c14,c9,0  /* ibcr1 */
-	mcr		p15,0,r0,c14,c4,0  /* dbcon */
+	mov	r0,#0
+	mcr	p15,0,r0,c14,c8,0  /* ibcr0 */
+	mcr	p15,0,r0,c14,c9,0  /* ibcr1 */
+	mcr	p15,0,r0,c14,c4,0  /* dbcon */
 
 	/*Enable all debug functionality */
-	mov		r0,#0x80000000
-	mcr		p14,0,r0,c10,c0,0  /* dcsr */
+	mov	r0,#0x80000000
+	mcr	p14,0,r0,c10,c0,0  /* dcsr */
 
 #endif
 
@@ -408,4 +408,4 @@ initclks:
 
 endlowlevel_init:
 
-    mov     pc,	lr
+	mov     pc, lr
diff --git a/board/cm5200/u-boot.lds b/board/cm5200/u-boot.lds
index 5d2efadd2a..87f37de164 100644
--- a/board/cm5200/u-boot.lds
+++ b/board/cm5200/u-boot.lds
@@ -31,11 +31,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/cmc_pu2/cmc_pu2.c b/board/cmc_pu2/cmc_pu2.c
index 374cd07013..3ad756de1c 100644
--- a/board/cmc_pu2/cmc_pu2.c
+++ b/board/cmc_pu2/cmc_pu2.c
@@ -73,7 +73,7 @@ int board_init (void)
 	pioc->PIO_PPUDR = AT91C_PIO_PC0 | AT91C_PIO_PC1 |
 			AT91C_PIO_PC2 | AT91C_PIO_PC3;
 	pioc->PIO_PER = AT91C_PIO_PC0 | AT91C_PIO_PC1 |
-	        	AT91C_PIO_PC2 | AT91C_PIO_PC3;
+			AT91C_PIO_PC2 | AT91C_PIO_PC3;
 
 	/*
 	 * On CMC-PU2 board configure PB3-PB6 to input without pull ups to
diff --git a/board/cmi/flash.c b/board/cmi/flash.c
index f7c25f4284..f57d8ecfe9 100644
--- a/board/cmi/flash.c
+++ b/board/cmi/flash.c
@@ -25,7 +25,7 @@
  * File:		flash.c
  *
  * Discription:		This Driver is for 28F320J3A, 28F640J3A and
- * 			28F128J3A Intel flashs working in 16 Bit mode.
+ *			28F128J3A Intel flashs working in 16 Bit mode.
  *			They are single bank flashs.
  *
  *			Most of this code is taken from existing u-boot
@@ -67,9 +67,9 @@ flash_info_t	flash_info[CFG_MAX_FLASH_BANKS];
 /*
  * Local function prototypes
  */
-static ulong 	flash_get_size 		(vu_short *addr, flash_info_t *info);
-static int 	write_short 		(flash_info_t *info, ulong dest, ushort data);
-static void 	flash_get_offsets 	(ulong base, flash_info_t *info);
+static ulong	flash_get_size		(vu_short *addr, flash_info_t *info);
+static int	write_short		(flash_info_t *info, ulong dest, ushort data);
+static void	flash_get_offsets	(ulong base, flash_info_t *info);
 
 /*
  * Initialize flash
diff --git a/board/cobra5272/u-boot.lds b/board/cobra5272/u-boot.lds
index 8f719ea28d..f99a236a31 100644
--- a/board/cobra5272/u-boot.lds
+++ b/board/cobra5272/u-boot.lds
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/cogent/lcd.h b/board/cogent/lcd.h
index 1056eea473..9e6157ee66 100644
--- a/board/cogent/lcd.h
+++ b/board/cogent/lcd.h
@@ -70,7 +70,7 @@
 
 /* LCD status values */
 #define LCD_OK		0x00
-#define LCD_ERR 	0x01
+#define LCD_ERR		0x01
 
 #define LCD_LINE0	0x00
 #define LCD_LINE1	0x40
diff --git a/board/cogent/u-boot.lds b/board/cogent/u-boot.lds
index 8d9c08ef2b..59d62e1011 100644
--- a/board/cogent/u-boot.lds
+++ b/board/cogent/u-boot.lds
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/cogent/u-boot.lds.debug b/board/cogent/u-boot.lds.debug
index 753411fcbf..c33581d250 100644
--- a/board/cogent/u-boot.lds.debug
+++ b/board/cogent/u-boot.lds.debug
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/cpc45/plx9030.c b/board/cpc45/plx9030.c
index 99ec39af7a..3711ccbd3c 100644
--- a/board/cpc45/plx9030.c
+++ b/board/cpc45/plx9030.c
@@ -54,7 +54,7 @@ registers (CS3) on CPC45.
 
 /* PLX9030 register offsets  */
 #define	P9030_LAS0RR	0x00
-#define	P9030_LAS1RR 	0x04
+#define	P9030_LAS1RR	0x04
 #define	P9030_LAS2RR	0x08
 #define	P9030_LAS3RR	0x0c
 #define	P9030_EROMRR	0x10
@@ -72,8 +72,8 @@ registers (CS3) on CPC45.
 #define	P9030_CS1BASE	0x40
 #define	P9030_CS2BASE	0x44
 #define	P9030_CS3BASE	0x48
-#define	P9030_INTCSR 	0x4c
-#define	P9030_CNTRL  	0x50
+#define	P9030_INTCSR	0x4c
+#define	P9030_CNTRL	0x50
 #define	P9030_GPIOC	0x54
 
 /* typedefs */
diff --git a/board/cray/L1/L1.h b/board/cray/L1/L1.h
index 1b41824483..c3a0b8f5eb 100644
--- a/board/cray/L1/L1.h
+++ b/board/cray/L1/L1.h
@@ -26,7 +26,7 @@
  *
  *                          Start Address    Length
  * +++++++++++++++++++++++++ 0xFFC0_0000     Start of Flash -----------------
- * | Failsafe Linux Image  | 	(1M)
+ * | Failsafe Linux Image  |	(1M)
  * +=======================+ 0xFFD0_0000
  * | (Reserved FlashFiles) |	(1M)
  * +=======================+ 0xFFE0_0000
@@ -36,7 +36,7 @@
  * | U N U S E D           |
  * |                       |
  * +-----------------------+ 0xFFFD_0000	U-Boot image header (64 bytes)
- * | environment settings  | 	(64k)
+ * | environment settings  |	(64k)
  * +-----------------------+ 0xFFFE_0000	U-Boot image header (64 bytes)
  * | U-Boot                | 0xFFFE_0040    _start of U-Boot
  * |                       | 0xFFFE_FFFC    reset vector - branch to _start
diff --git a/board/cray/L1/u-boot.lds b/board/cray/L1/u-boot.lds
index 56c6cdb705..a6bbef3dcc 100644
--- a/board/cray/L1/u-boot.lds
+++ b/board/cray/L1/u-boot.lds
@@ -39,11 +39,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/cray/L1/u-boot.lds.debug b/board/cray/L1/u-boot.lds.debug
index 88dcaf91bf..0552994f40 100644
--- a/board/cray/L1/u-boot.lds.debug
+++ b/board/cray/L1/u-boot.lds.debug
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/csb226/lowlevel_init.S b/board/csb226/lowlevel_init.S
index aa9dcba6fc..4c9f10ffbd 100644
--- a/board/csb226/lowlevel_init.S
+++ b/board/csb226/lowlevel_init.S
@@ -43,7 +43,7 @@ _TEXT_BASE:
 
 
 /*
- * 	Memory setup
+ *	Memory setup
  */
 
 .globl lowlevel_init
@@ -129,8 +129,8 @@ lowlevel_init:
 /*loop: */
 /* */
 /*   ldr	r0, =0xB0070001 */
-/*   ldr    	r1, =_LED */
-/*   str    	r0, [r1]		/  hex display */
+/*   ldr	r1, =_LED */
+/*   str	r0, [r1]		/  hex display */
 
 
 	/* ---------------------------------------------------------------- */
@@ -239,7 +239,7 @@ mem_init:
 	/* Before accessing MDREFR we need a valid DRI field, so we set     */
 	/* this to power on defaults + DRI field.                           */
 
-	ldr 	r3, 	=CFG_MDREFR_VAL
+	ldr	r3,	=CFG_MDREFR_VAL
 	ldr	r2,	=0xFFF
 	and	r3,	r3, r2
 	ldr	r4,	=0x03ca4000
diff --git a/board/csb272/u-boot.lds b/board/csb272/u-boot.lds
index 44af70e86a..947fbd6382 100644
--- a/board/csb272/u-boot.lds
+++ b/board/csb272/u-boot.lds
@@ -38,11 +38,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/csb472/u-boot.lds b/board/csb472/u-boot.lds
index 00219180fd..de3643eed9 100644
--- a/board/csb472/u-boot.lds
+++ b/board/csb472/u-boot.lds
@@ -38,11 +38,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/dave/B2/B2.c b/board/dave/B2/B2.c
index 64fe948fcc..ec742adc7f 100644
--- a/board/dave/B2/B2.c
+++ b/board/dave/B2/B2.c
@@ -78,16 +78,16 @@ int board_init (void)
 	INTCON = 0x05;
 
     /*
-    	Configure chip ethernet interrupt as High level
-    	Port G EINT 0-7 EINT0 -> CHIP ETHERNET
+	Configure chip ethernet interrupt as High level
+	Port G EINT 0-7 EINT0 -> CHIP ETHERNET
     */
 	temp = EXTINT;
-   	temp &= ~0x7;
+	temp &= ~0x7;
     temp |= 0x1; /*LEVEL_HIGH*/
 	EXTINT = temp;
 
     /*
-    	Reset SMSC LAN91C96 chip
+	Reset SMSC LAN91C96 chip
     */
     temp= PCONF;
     temp |= 0x00000040;
diff --git a/board/dave/PPChameleonEVB/u-boot.lds b/board/dave/PPChameleonEVB/u-boot.lds
index 289bff2732..3037a049c3 100644
--- a/board/dave/PPChameleonEVB/u-boot.lds
+++ b/board/dave/PPChameleonEVB/u-boot.lds
@@ -38,11 +38,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/davinci/dv-evm/dv_board.c b/board/davinci/dv-evm/dv_board.c
index dce821ba6a..88b1e57593 100644
--- a/board/davinci/dv-evm/dv_board.c
+++ b/board/davinci/dv-evm/dv_board.c
@@ -73,7 +73,7 @@ void lpsc_on(unsigned int id)
 		(id == DAVINCI_LPSC_McBSP) ||
 		(id == DAVINCI_LPSC_GPIO)
 	   )
-	   	*mdctl |= 0x200;
+		*mdctl |= 0x200;
 
 	REG(PSC_PTCMD) = 0x01;
 
diff --git a/board/davinci/schmoogie/dv_board.c b/board/davinci/schmoogie/dv_board.c
index 0a07523b12..13d2195819 100644
--- a/board/davinci/schmoogie/dv_board.c
+++ b/board/davinci/schmoogie/dv_board.c
@@ -73,7 +73,7 @@ void lpsc_on(unsigned int id)
 		(id == DAVINCI_LPSC_McBSP) ||
 		(id == DAVINCI_LPSC_GPIO)
 	   )
-	   	*mdctl |= 0x200;
+		*mdctl |= 0x200;
 
 	REG(PSC_PTCMD) = 0x01;
 
diff --git a/board/davinci/sonata/dv_board.c b/board/davinci/sonata/dv_board.c
index cd2dac610d..e8665e5d3a 100644
--- a/board/davinci/sonata/dv_board.c
+++ b/board/davinci/sonata/dv_board.c
@@ -73,7 +73,7 @@ void lpsc_on(unsigned int id)
 		(id == DAVINCI_LPSC_McBSP) ||
 		(id == DAVINCI_LPSC_GPIO)
 	   )
-	   	*mdctl |= 0x200;
+		*mdctl |= 0x200;
 
 	REG(PSC_PTCMD) = 0x01;
 
diff --git a/board/eltec/bab7xx/u-boot.lds b/board/eltec/bab7xx/u-boot.lds
index 25e16de3b6..1a95755ab4 100644
--- a/board/eltec/bab7xx/u-boot.lds
+++ b/board/eltec/bab7xx/u-boot.lds
@@ -37,11 +37,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/eltec/elppc/u-boot.lds b/board/eltec/elppc/u-boot.lds
index 25e16de3b6..1a95755ab4 100644
--- a/board/eltec/elppc/u-boot.lds
+++ b/board/eltec/elppc/u-boot.lds
@@ -37,11 +37,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/eltec/mhpc/u-boot.lds b/board/eltec/mhpc/u-boot.lds
index 94ab7457f9..85117aa56e 100644
--- a/board/eltec/mhpc/u-boot.lds
+++ b/board/eltec/mhpc/u-boot.lds
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/eltec/mhpc/u-boot.lds.debug b/board/eltec/mhpc/u-boot.lds.debug
index 1a25a98f17..85072feda4 100644
--- a/board/eltec/mhpc/u-boot.lds.debug
+++ b/board/eltec/mhpc/u-boot.lds.debug
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/emk/top860/u-boot.lds b/board/emk/top860/u-boot.lds
index 2168087eb0..97ef89a400 100644
--- a/board/emk/top860/u-boot.lds
+++ b/board/emk/top860/u-boot.lds
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/emk/top860/u-boot.lds.debug b/board/emk/top860/u-boot.lds.debug
index 25bbd264a0..5d97095c12 100644
--- a/board/emk/top860/u-boot.lds.debug
+++ b/board/emk/top860/u-boot.lds.debug
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/ep8260/flash.c b/board/ep8260/flash.c
index 278d606b32..966a345260 100644
--- a/board/ep8260/flash.c
+++ b/board/ep8260/flash.c
@@ -72,7 +72,7 @@ ulong flash_get_size( ulong baseaddr, flash_info_t *info )
 		info->flash_id = FLASH_UNKNOWN;
 		info->sector_count = 0;
 		info->size = 0;
-		return (0);  				/* no or unknown flash	   */
+		return (0);				/* no or unknown flash	   */
 	}
 
 	flashtest_h = V_ULONG(baseaddr + 8);	        /* device ID		   */
@@ -91,11 +91,11 @@ ulong flash_get_size( ulong baseaddr, flash_info_t *info )
 	case AMD_ID_LV640U:	/* AMDLV640 and AMDLV641 have same ID */
 		info->flash_id += FLASH_AMLV640U;
 		info->sector_count = 128;
-		info->size = 0x02000000; 	/* 4 * 8 MB = 32 MB	*/
+		info->size = 0x02000000;	/* 4 * 8 MB = 32 MB	*/
 		break;
 	default:
 		info->flash_id = FLASH_UNKNOWN;
-		return(0);  			 	/* no or unknown flash	   */
+		return(0);				/* no or unknown flash	   */
 	}
 
 	if(flashtest_h == AMD_ID_LV640U) {
diff --git a/board/ep82xxm/ep82xxm.c b/board/ep82xxm/ep82xxm.c
index fe3f78e738..27443d3dfb 100644
--- a/board/ep82xxm/ep82xxm.c
+++ b/board/ep82xxm/ep82xxm.c
@@ -46,146 +46,146 @@ const iop_conf_t iop_conf_tab[4][32] = {
 
     /* Port A */
     {	/*	     conf      ppar psor pdir podr pdat */
-	/* PA31 */ { 0,          0,   0,   0,   0,   1 }, /* PA31	     */
-	/* PA30 */ { 0,          0,   0,   0,   0,   1 }, /* PA30	     */
-	/* PA29 */ { 0,          0,   0,   0,   0,   1 }, /* PA29	     */
-	/* PA28 */ { 0,          0,   0,   0,   0,   1 }, /* PA28	     */
-	/* PA27 */ { 0,          0,   0,   0,   0,   1 }, /* PA27	     */
-	/* PA26 */ { 0,          0,   0,   0,   0,   1 }, /* PA26	     */
-	/* PA25 */ { 0,          0,   0,   0,   0,   1 }, /* PA25            */
-	/* PA24 */ { 0,          0,   0,   0,   0,   1 }, /* PA24            */
-	/* PA23 */ { 0,          0,   0,   0,   0,   1 }, /* PA23            */
-	/* PA22 */ { 0,          0,   0,   0,   0,   0 }, /* PA22            */
-	/* PA21 */ { 0,          0,   0,   0,   0,   1 }, /* PA21	     */
-	/* PA20 */ { 0,          0,   0,   0,   0,   1 }, /* PA20 	     */
-	/* PA19 */ { 0,          0,   0,   0,   0,   1 }, /* PA19	     */
-	/* PA18 */ { 0,          0,   0,   0,   0,   1 }, /* PA18	     */
-	/* PA17 */ { 0,          0,   0,   0,   0,   1 }, /* PA17  	     */
-	/* PA16 */ { 0,          0,   0,   0,   0,   1 }, /* PA16	     */
-	/* PA15 */ { 0,          0,   0,   0,   0,   1 }, /* PA15	     */
-	/* PA14 */ { 0,          0,   0,   0,   0,   1 }, /* PA14	     */
-	/* PA13 */ { 0,          0,   0,   0,   0,   1 }, /* PA13            */
-	/* PA12 */ { 0,          0,   0,   0,   0,   1 }, /* PA12            */
-	/* PA11 */ { 0,          0,   0,   0,   0,   1 }, /* PA11            */
-	/* PA10 */ { 0,          0,   0,   0,   0,   1 }, /* PA10            */
-	/* PA9  */ { 1,          1,   0,   1,   0,   1 }, /* SMC2 TxD        */
-	/* PA8  */ { 1,          1,   0,   0,   0,   1 }, /* SMC2 RxD        */
-	/* PA7  */ { 0,          0,   0,   0,   0,   1 }, /* PA7             */
-	/* PA6  */ { 0,          0,   0,   0,   0,   1 }, /* PA6             */
-	/* PA5  */ { 0,          0,   0,   0,   0,   1 }, /* PA5             */
-	/* PA4  */ { 0,          0,   0,   0,   0,   1 }, /* PA4             */
-	/* PA3  */ { 0,          0,   0,   0,   0,   1 }, /* PA3             */
-	/* PA2  */ { 0,          0,   0,   0,   0,   1 }, /* PA2             */
-	/* PA1  */ { 0,          0,   0,   0,   0,   1 }, /* PA1             */
-	/* PA0  */ { 0,          0,   0,   0,   0,   1 }  /* PA0             */
+	/* PA31 */ { 0,		 0,   0,   0,	0,   1 }, /* PA31	     */
+	/* PA30 */ { 0,		 0,   0,   0,	0,   1 }, /* PA30	     */
+	/* PA29 */ { 0,		 0,   0,   0,	0,   1 }, /* PA29	     */
+	/* PA28 */ { 0,		 0,   0,   0,	0,   1 }, /* PA28	     */
+	/* PA27 */ { 0,		 0,   0,   0,	0,   1 }, /* PA27	     */
+	/* PA26 */ { 0,		 0,   0,   0,	0,   1 }, /* PA26	     */
+	/* PA25 */ { 0,		 0,   0,   0,	0,   1 }, /* PA25	     */
+	/* PA24 */ { 0,		 0,   0,   0,	0,   1 }, /* PA24	     */
+	/* PA23 */ { 0,		 0,   0,   0,	0,   1 }, /* PA23	     */
+	/* PA22 */ { 0,		 0,   0,   0,	0,   0 }, /* PA22	     */
+	/* PA21 */ { 0,		 0,   0,   0,	0,   1 }, /* PA21	     */
+	/* PA20 */ { 0,		 0,   0,   0,	0,   1 }, /* PA20	     */
+	/* PA19 */ { 0,		 0,   0,   0,	0,   1 }, /* PA19	     */
+	/* PA18 */ { 0,		 0,   0,   0,	0,   1 }, /* PA18	     */
+	/* PA17 */ { 0,		 0,   0,   0,	0,   1 }, /* PA17	     */
+	/* PA16 */ { 0,		 0,   0,   0,	0,   1 }, /* PA16	     */
+	/* PA15 */ { 0,		 0,   0,   0,	0,   1 }, /* PA15	     */
+	/* PA14 */ { 0,		 0,   0,   0,	0,   1 }, /* PA14	     */
+	/* PA13 */ { 0,		 0,   0,   0,	0,   1 }, /* PA13	     */
+	/* PA12 */ { 0,		 0,   0,   0,	0,   1 }, /* PA12	     */
+	/* PA11 */ { 0,		 0,   0,   0,	0,   1 }, /* PA11	     */
+	/* PA10 */ { 0,		 0,   0,   0,	0,   1 }, /* PA10	     */
+	/* PA9	*/ { 1,		 1,   0,   1,	0,   1 }, /* SMC2 TxD	     */
+	/* PA8	*/ { 1,		 1,   0,   0,	0,   1 }, /* SMC2 RxD	     */
+	/* PA7	*/ { 0,		 0,   0,   0,	0,   1 }, /* PA7	     */
+	/* PA6	*/ { 0,		 0,   0,   0,	0,   1 }, /* PA6	     */
+	/* PA5	*/ { 0,		 0,   0,   0,	0,   1 }, /* PA5	     */
+	/* PA4	*/ { 0,		 0,   0,   0,	0,   1 }, /* PA4	     */
+	/* PA3	*/ { 0,		 0,   0,   0,	0,   1 }, /* PA3	     */
+	/* PA2	*/ { 0,		 0,   0,   0,	0,   1 }, /* PA2	     */
+	/* PA1	*/ { 0,		 0,   0,   0,	0,   1 }, /* PA1	     */
+	/* PA0	*/ { 0,		 0,   0,   0,	0,   1 }  /* PA0	     */
     },
 
     /* Port B */
-    {   /*	     conf       ppar psor pdir podr pdat */
-	/* PB31 */ { CFG_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TX_ER  */
-	/* PB30 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RX_DV  */
-	/* PB29 */ { CFG_FCC2,   1,   1,   1,   0,   0 }, /* FCC2 MII TX_EN  */
-	/* PB28 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RX_ER  */
-	/* PB27 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII COL    */
-	/* PB26 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII CRS    */
-	/* PB25 */ { CFG_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[3] */
-	/* PB24 */ { CFG_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[2] */
-	/* PB23 */ { CFG_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[1] */
-	/* PB22 */ { CFG_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[0] */
-	/* PB21 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[0] */
-	/* PB20 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[1] */
-	/* PB19 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[2] */
-	/* PB18 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[3] */
-	/* PB17 */ { CFG_FCC3,   1,   0,   0,   0,   0 }, /* FCC3:RX_DIV     */
-	/* PB16 */ { CFG_FCC3,   1,   0,   0,   0,   0 }, /* FCC3:RX_ERR     */
-	/* PB15 */ { CFG_FCC3,   1,   0,   1,   0,   0 }, /* FCC3:TX_ERR     */
-	/* PB14 */ { CFG_FCC3,   1,   0,   1,   0,   0 }, /* FCC3:TX_EN      */
-	/* PB13 */ { CFG_FCC3,   1,   0,   0,   0,   0 }, /* FCC3:COL	     */
-	/* PB12 */ { CFG_FCC3,   1,   0,   0,   0,   0 }, /* FCC3:CRS        */
-	/* PB11 */ { CFG_FCC3,   1,   0,   0,   0,   0 }, /* FCC3:RXD        */
-	/* PB10 */ { CFG_FCC3,   1,   0,   0,   0,   0 }, /* FCC3:RXD        */
-	/* PB9  */ { CFG_FCC3,   1,   0,   0,   0,   0 }, /* FCC3:RXD        */
-	/* PB8  */ { CFG_FCC3,   1,   0,   0,   0,   0 }, /* FCC3:RXD        */
-	/* PB7  */ { 0,		 0,   0,   0,   0,   0 }, /* PB7             */
-	/* PB6  */ { CFG_FCC3,   1,   0,   1,   0,   0 }, /* FCC3:TXD        */
-	/* PB5  */ { CFG_FCC3,   1,   0,   1,   0,   0 }, /* FCC3:TXD        */
-	/* PB4  */ { CFG_FCC3,   1,   0,   1,   0,   0 }, /* FCC3:TXD        */
-	/* PB3  */ { 0,        	 0,   0,   0,   0,   0 }, /* non-existent    */
-	/* PB2  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
-	/* PB1  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
-	/* PB0  */ { 0,          0,   0,   0,   0,   0 }  /* non-existent    */
+    {	/*	     conf	ppar psor pdir podr pdat */
+	/* PB31 */ { CFG_FCC2,	 1,   0,   1,	0,   0 }, /* FCC2 MII TX_ER  */
+	/* PB30 */ { CFG_FCC2,	 1,   0,   0,	0,   0 }, /* FCC2 MII RX_DV  */
+	/* PB29 */ { CFG_FCC2,	 1,   1,   1,	0,   0 }, /* FCC2 MII TX_EN  */
+	/* PB28 */ { CFG_FCC2,	 1,   0,   0,	0,   0 }, /* FCC2 MII RX_ER  */
+	/* PB27 */ { CFG_FCC2,	 1,   0,   0,	0,   0 }, /* FCC2 MII COL    */
+	/* PB26 */ { CFG_FCC2,	 1,   0,   0,	0,   0 }, /* FCC2 MII CRS    */
+	/* PB25 */ { CFG_FCC2,	 1,   0,   1,	0,   0 }, /* FCC2 MII TxD[3] */
+	/* PB24 */ { CFG_FCC2,	 1,   0,   1,	0,   0 }, /* FCC2 MII TxD[2] */
+	/* PB23 */ { CFG_FCC2,	 1,   0,   1,	0,   0 }, /* FCC2 MII TxD[1] */
+	/* PB22 */ { CFG_FCC2,	 1,   0,   1,	0,   0 }, /* FCC2 MII TxD[0] */
+	/* PB21 */ { CFG_FCC2,	 1,   0,   0,	0,   0 }, /* FCC2 MII RxD[0] */
+	/* PB20 */ { CFG_FCC2,	 1,   0,   0,	0,   0 }, /* FCC2 MII RxD[1] */
+	/* PB19 */ { CFG_FCC2,	 1,   0,   0,	0,   0 }, /* FCC2 MII RxD[2] */
+	/* PB18 */ { CFG_FCC2,	 1,   0,   0,	0,   0 }, /* FCC2 MII RxD[3] */
+	/* PB17 */ { CFG_FCC3,	 1,   0,   0,	0,   0 }, /* FCC3:RX_DIV     */
+	/* PB16 */ { CFG_FCC3,	 1,   0,   0,	0,   0 }, /* FCC3:RX_ERR     */
+	/* PB15 */ { CFG_FCC3,	 1,   0,   1,	0,   0 }, /* FCC3:TX_ERR     */
+	/* PB14 */ { CFG_FCC3,	 1,   0,   1,	0,   0 }, /* FCC3:TX_EN      */
+	/* PB13 */ { CFG_FCC3,	 1,   0,   0,	0,   0 }, /* FCC3:COL	     */
+	/* PB12 */ { CFG_FCC3,	 1,   0,   0,	0,   0 }, /* FCC3:CRS	     */
+	/* PB11 */ { CFG_FCC3,	 1,   0,   0,	0,   0 }, /* FCC3:RXD	     */
+	/* PB10 */ { CFG_FCC3,	 1,   0,   0,	0,   0 }, /* FCC3:RXD	     */
+	/* PB9	*/ { CFG_FCC3,	 1,   0,   0,	0,   0 }, /* FCC3:RXD	     */
+	/* PB8	*/ { CFG_FCC3,	 1,   0,   0,	0,   0 }, /* FCC3:RXD	     */
+	/* PB7	*/ { 0,		 0,   0,   0,	0,   0 }, /* PB7	     */
+	/* PB6	*/ { CFG_FCC3,	 1,   0,   1,	0,   0 }, /* FCC3:TXD	     */
+	/* PB5	*/ { CFG_FCC3,	 1,   0,   1,	0,   0 }, /* FCC3:TXD	     */
+	/* PB4	*/ { CFG_FCC3,	 1,   0,   1,	0,   0 }, /* FCC3:TXD	     */
+	/* PB3	*/ { 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
+	/* PB2	*/ { 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
+	/* PB1	*/ { 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
+	/* PB0	*/ { 0,		 0,   0,   0,	0,   0 }  /* non-existent    */
     },
 
     /* Port C */
-    {   /*	     conf	ppar psor pdir podr pdat */
-	/* PC31 */ { 0,          0,   0,   0,   0,   0 }, /* PC31            */
-	/* PC30 */ { 0,          0,   0,   0,   0,   0 }, /* PC30            */
-	/* PC29 */ { 1,          1,   1,   0,   0,   0 }, /* SCC1 CTS#       */
-	/* PC28 */ { 0,          0,   0,   0,   0,   0 }, /* PC28            */
-	/* PC27 */ { CFG_FCC3,   1,   0,   1,   0,   0 }, /* FCC3: TXD[0]    */
-	/* PC26 */ { 0,          0,   0,   0,   0,   0 }, /* PC26            */
-	/* PC25 */ { 0,          0,   0,   0,   0,   0 }, /* PC25            */
-	/* PC24 */ { 0,          0,   0,   0,   0,   0 }, /* PC24            */
-	/* PC23 */ { 0,          0,   0,   0,   0,   0 }, /* PC23            */
-	/* PC22 */ { 0,  	 0,   0,   0,   0,   0 }, /* PC22	     */
-	/* PC21 */ { 0,   	 0,   0,   0,   0,   0 }, /* PC21	     */
-	/* PC20 */ { 0,          0,   0,   0,   0,   0 }, /* PC20            */
-	/* PC19 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* RxClk (CLK13)   */
-	/* PC18 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* TxClk (CLK14)   */
-	/* PC17 */ { CFG_FCC3,   1,   0,   0,   0,   0 }, /* RxClk (CLK15)   */
-	/* PC16 */ { CFG_FCC3,   1,   0,   0,   0,   0 }, /* TxClk (CLK16)   */
-	/* PC15 */ { 0,          0,   0,   0,   0,   0 }, /* PC15            */
-	/* PC14 */ { 1,          1,   0,   0,   0,   0 }, /* SCC1 CD#        */
-	/* PC13 */ { 1,          1,   0,   0,   0,   0 }, /* SCC2 CTS#       */
-	/* PC12 */ { 1,          1,   0,   0,   0,   0 }, /* SCC2 CD#        */
-	/* PC11 */ { 0,          0,   0,   0,   0,   0 }, /* PC11            */
-	/* PC10 */ { 1,          1,   0,   0,   0,   0 }, /* SCC3 CD#        */
-	/* PC9  */ { 0,          0,   0,   0,   0,   0 }, /* PC9             */
-	/* PC8  */ { 1,          1,   1,   0,   0,   0 }, /* SCC3 CTS#       */
-	/* PC7  */ { 0,          0,   0,   0,   0,   0 }, /* PC7             */
-	/* PC6  */ { 0,          0,   0,   0,   0,   0 }, /* PC6             */
-	/* PC5  */ { 0,          0,   0,   0,   0,   0 }, /* PC5             */
-	/* PC4  */ { 0,          0,   0,   0,   0,   0 }, /* PC4             */
-	/* PC3  */ { 0,          0,   0,   0,   0,   0 }, /* PC3             */
-	/* PC2  */ { 0,          0,   0,   0,   0,   0 }, /* PC2             */
-	/* PC1  */ { 0,          0,   0,   0,   0,   0 }, /* PC1             */
-	/* PC0  */ { 0,          0,   0,   0,   0,   0 }, /* PC0             */
+    {	/*	     conf	ppar psor pdir podr pdat */
+	/* PC31 */ { 0,		 0,   0,   0,	0,   0 }, /* PC31	     */
+	/* PC30 */ { 0,		 0,   0,   0,	0,   0 }, /* PC30	     */
+	/* PC29 */ { 1,		 1,   1,   0,	0,   0 }, /* SCC1 CTS#	     */
+	/* PC28 */ { 0,		 0,   0,   0,	0,   0 }, /* PC28	     */
+	/* PC27 */ { CFG_FCC3,	 1,   0,   1,	0,   0 }, /* FCC3: TXD[0]    */
+	/* PC26 */ { 0,		 0,   0,   0,	0,   0 }, /* PC26	     */
+	/* PC25 */ { 0,		 0,   0,   0,	0,   0 }, /* PC25	     */
+	/* PC24 */ { 0,		 0,   0,   0,	0,   0 }, /* PC24	     */
+	/* PC23 */ { 0,		 0,   0,   0,	0,   0 }, /* PC23	     */
+	/* PC22 */ { 0,		 0,   0,   0,	0,   0 }, /* PC22	     */
+	/* PC21 */ { 0,		 0,   0,   0,	0,   0 }, /* PC21	     */
+	/* PC20 */ { 0,		 0,   0,   0,	0,   0 }, /* PC20	     */
+	/* PC19 */ { CFG_FCC2,	 1,   0,   0,	0,   0 }, /* RxClk (CLK13)   */
+	/* PC18 */ { CFG_FCC2,	 1,   0,   0,	0,   0 }, /* TxClk (CLK14)   */
+	/* PC17 */ { CFG_FCC3,	 1,   0,   0,	0,   0 }, /* RxClk (CLK15)   */
+	/* PC16 */ { CFG_FCC3,	 1,   0,   0,	0,   0 }, /* TxClk (CLK16)   */
+	/* PC15 */ { 0,		 0,   0,   0,	0,   0 }, /* PC15	     */
+	/* PC14 */ { 1,		 1,   0,   0,	0,   0 }, /* SCC1 CD#	     */
+	/* PC13 */ { 1,		 1,   0,   0,	0,   0 }, /* SCC2 CTS#	     */
+	/* PC12 */ { 1,		 1,   0,   0,	0,   0 }, /* SCC2 CD#	     */
+	/* PC11 */ { 0,		 0,   0,   0,	0,   0 }, /* PC11	     */
+	/* PC10 */ { 1,		 1,   0,   0,	0,   0 }, /* SCC3 CD#	     */
+	/* PC9	*/ { 0,		 0,   0,   0,	0,   0 }, /* PC9	     */
+	/* PC8	*/ { 1,		 1,   1,   0,	0,   0 }, /* SCC3 CTS#	     */
+	/* PC7	*/ { 0,		 0,   0,   0,	0,   0 }, /* PC7	     */
+	/* PC6	*/ { 0,		 0,   0,   0,	0,   0 }, /* PC6	     */
+	/* PC5	*/ { 0,		 0,   0,   0,	0,   0 }, /* PC5	     */
+	/* PC4	*/ { 0,		 0,   0,   0,	0,   0 }, /* PC4	     */
+	/* PC3	*/ { 0,		 0,   0,   0,	0,   0 }, /* PC3	     */
+	/* PC2	*/ { 0,		 0,   0,   0,	0,   0 }, /* PC2	     */
+	/* PC1	*/ { 0,		 0,   0,   0,	0,   0 }, /* PC1	     */
+	/* PC0	*/ { 0,		 0,   0,   0,	0,   0 }, /* PC0	     */
     },
 
     /* Port D */
-    {   /*	     conf      ppar psor pdir podr pdat */
-	/* PD31 */ { 1,          1,   0,   0,   0,   0 }, /* SCC1 RXD        */
-	/* PD30 */ { 1,          1,   1,   1,   0,   1 }, /* SCC1 TXD        */
-	/* PD29 */ { 1,          1,   0,   1,   0,   0 }, /* SCC1 RTS#       */
-	/* PD28 */ { 1,          1,   0,   0,   0,   0 }, /* SCC2 RXD        */
-	/* PD27 */ { 1,          1,   0,   1,   0,   0 }, /* SCC2 TXD        */
-	/* PD26 */ { 1,          1,   0,   1,   0,   0 }, /* SCC2 RTS#       */
-	/* PD25 */ { 1,          1,   0,   0,   0,   0 }, /* SCC3 RXD        */
-	/* PD24 */ { 1,          1,   0,   1,   0,   0 }, /* SCC3 TXD        */
-	/* PD23 */ { 1,          1,   0,   1,   0,   0 }, /* SCC3 RTS#       */
-	/* PD22 */ { 0,          0,   0,   0,   0,   1 }, /* PD22            */
-	/* PD21 */ { 0,          0,   0,   0,   0,   1 }, /* PD21            */
-	/* PD20 */ { 0,          0,   0,   0,   0,   1 }, /* PD20            */
-	/* PD19 */ { 0,          0,   0,   0,   0,   1 }, /* PD19            */
-	/* PD18 */ { 0,          0,   0,   0,   0,   1 }, /* PD18            */
-	/* PD17 */ { 0,          0,   0,   0,   0,   1 }, /* PD17            */
-	/* PD16 */ { 0,          0,   0,   0,   0,   1 }, /* PD16            */
-	/* PD15 */ { 1,          1,   1,   0,   1,   1 }, /* I2C SDA         */
-	/* PD14 */ { 1,          1,   1,   0,   1,   1 }, /* I2C SCL         */
-	/* PD13 */ { 0,          0,   0,   0,   0,   1 }, /* PD13            */
-	/* PD12 */ { 0,          0,   0,   0,   0,   1 }, /* PD12            */
-	/* PD11 */ { 0,          0,   0,   0,   0,   1 }, /* PD11            */
-	/* PD10 */ { 0,          0,   0,   0,   0,   1 }, /* PD10            */
-	/* PD9  */ { 1,          1,   0,   1,   0,   1 }, /* SMC1 TxD        */
-	/* PD8  */ { 1,          1,   0,   0,   0,   1 }, /* SMC1 RxD        */
-	/* PD7  */ { 1,          1,   0,   0,   0,   1 }, /* SMC1 SMSYN      */
-	/* PD6  */ { 0,          0,   0,   0,   0,   1 }, /* PD6             */
-	/* PD5  */ { 0,          0,   0,   0,   0,   1 }, /* PD5             */
-	/* PD4  */ { 0,          0,   0,   0,   0,   1 }, /* PD4             */
-	/* PD3  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
-	/* PD2  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
-	/* PD1  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
-	/* PD0  */ { 0,          0,   0,   0,   0,   0 }  /* non-existent    */
+    {	/*	     conf      ppar psor pdir podr pdat */
+	/* PD31 */ { 1,		 1,   0,   0,	0,   0 }, /* SCC1 RXD	     */
+	/* PD30 */ { 1,		 1,   1,   1,	0,   1 }, /* SCC1 TXD	     */
+	/* PD29 */ { 1,		 1,   0,   1,	0,   0 }, /* SCC1 RTS#	     */
+	/* PD28 */ { 1,		 1,   0,   0,	0,   0 }, /* SCC2 RXD	     */
+	/* PD27 */ { 1,		 1,   0,   1,	0,   0 }, /* SCC2 TXD	     */
+	/* PD26 */ { 1,		 1,   0,   1,	0,   0 }, /* SCC2 RTS#	     */
+	/* PD25 */ { 1,		 1,   0,   0,	0,   0 }, /* SCC3 RXD	     */
+	/* PD24 */ { 1,		 1,   0,   1,	0,   0 }, /* SCC3 TXD	     */
+	/* PD23 */ { 1,		 1,   0,   1,	0,   0 }, /* SCC3 RTS#	     */
+	/* PD22 */ { 0,		 0,   0,   0,	0,   1 }, /* PD22	     */
+	/* PD21 */ { 0,		 0,   0,   0,	0,   1 }, /* PD21	     */
+	/* PD20 */ { 0,		 0,   0,   0,	0,   1 }, /* PD20	     */
+	/* PD19 */ { 0,		 0,   0,   0,	0,   1 }, /* PD19	     */
+	/* PD18 */ { 0,		 0,   0,   0,	0,   1 }, /* PD18	     */
+	/* PD17 */ { 0,		 0,   0,   0,	0,   1 }, /* PD17	     */
+	/* PD16 */ { 0,		 0,   0,   0,	0,   1 }, /* PD16	     */
+	/* PD15 */ { 1,		 1,   1,   0,	1,   1 }, /* I2C SDA	     */
+	/* PD14 */ { 1,		 1,   1,   0,	1,   1 }, /* I2C SCL	     */
+	/* PD13 */ { 0,		 0,   0,   0,	0,   1 }, /* PD13	     */
+	/* PD12 */ { 0,		 0,   0,   0,	0,   1 }, /* PD12	     */
+	/* PD11 */ { 0,		 0,   0,   0,	0,   1 }, /* PD11	     */
+	/* PD10 */ { 0,		 0,   0,   0,	0,   1 }, /* PD10	     */
+	/* PD9	*/ { 1,		 1,   0,   1,	0,   1 }, /* SMC1 TxD	     */
+	/* PD8	*/ { 1,		 1,   0,   0,	0,   1 }, /* SMC1 RxD	     */
+	/* PD7	*/ { 1,		 1,   0,   0,	0,   1 }, /* SMC1 SMSYN      */
+	/* PD6	*/ { 0,		 0,   0,   0,	0,   1 }, /* PD6	     */
+	/* PD5	*/ { 0,		 0,   0,   0,	0,   1 }, /* PD5	     */
+	/* PD4	*/ { 0,		 0,   0,   0,	0,   1 }, /* PD4	     */
+	/* PD3	*/ { 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
+	/* PD2	*/ { 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
+	/* PD1	*/ { 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
+	/* PD0	*/ { 0,		 0,   0,   0,	0,   0 }  /* non-existent    */
     }
 };
 
@@ -230,8 +230,8 @@ long int initdram(int board_type)
 	uint psdmr = CFG_PSDMR;
 	int i;
 
-	unsigned char           ramtmp;
-    	unsigned char           *ramptr1 = (unsigned char *)0x00000110;
+	unsigned char	ramtmp;
+	unsigned char	*ramptr1 = (unsigned char *)0x00000110;
 
 	memctl->memc_mptpr = CFG_MPTPR;
 
diff --git a/board/ep88x/u-boot.lds b/board/ep88x/u-boot.lds
index 2a763adf7f..3545142333 100644
--- a/board/ep88x/u-boot.lds
+++ b/board/ep88x/u-boot.lds
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)	}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)	}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)	}
   .rela.got      : { *(.rela.got)	}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/eric/flash.c b/board/eric/flash.c
index c08a760266..2c7d2a08c4 100644
--- a/board/eric/flash.c
+++ b/board/eric/flash.c
@@ -564,17 +564,17 @@ ulong flash_get_size (volatile FLASH_WORD_SIZE *addr, flash_info_t *info)
 		info->flash_id += FLASH_28F320J3A;
 		info->sector_count = 32;
 		info->size = 0x00400000;
-		break;				/* => 32 MBit  	*/
+		break;				/* => 32 MBit	*/
 	case (INTEL_ID_28F640J3A & FLASH_ID_MASK):
 		info->flash_id += FLASH_28F640J3A;
 		info->sector_count = 64;
 		info->size = 0x00800000;
-		break;				/* => 64 MBit  	*/
+		break;				/* => 64 MBit	*/
 	case (INTEL_ID_28F128J3A & FLASH_ID_MASK):
 		info->flash_id += FLASH_28F128J3A;
 		info->sector_count = 128;
 		info->size = 0x01000000;
-		break;				/* => 128 MBit  	*/
+		break;				/* => 128 MBit	*/
 
 	default:
 		/* FIXME*/
@@ -981,148 +981,151 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
  * 2 - Flash not erased
  */
 #ifndef CFG_FLASH_16BIT
-static int write_word (flash_info_t *info, ulong dest, ulong data)
+static int write_word (flash_info_t * info, ulong dest, ulong data)
 {
-	vu_long *addr = (vu_long*)(info->start[0]);
-	ulong start,barf;
+	vu_long *addr = (vu_long *) (info->start[0]);
+	ulong start, barf;
 	int flag;
 
 
 	/* Check if Flash is (sufficiently) erased */
-	if ((*((vu_long *)dest) & data) != data) {
+	if ((*((vu_long *) dest) & data) != data) {
 		return (2);
 	}
 
 	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts();
+	flag = disable_interrupts ();
 
-     if(info->flash_id > FLASH_AMD_COMP) {
-	/* AMD stuff */
-	addr[0x0555] = 0x00AA00AA;
-	addr[0x02AA] = 0x00550055;
-	addr[0x0555] = 0x00A000A0;
-     } else {
-	/* intel stuff */
-	*addr = 0x00400040;
-     }
-	*((vu_long *)dest) = data;
+	if (info->flash_id > FLASH_AMD_COMP) {
+		/* AMD stuff */
+		addr[0x0555] = 0x00AA00AA;
+		addr[0x02AA] = 0x00550055;
+		addr[0x0555] = 0x00A000A0;
+	} else {
+		/* intel stuff */
+		*addr = 0x00400040;
+	}
+	*((vu_long *) dest) = data;
 
 	/* re-enable interrupts if necessary */
 	if (flag)
-		enable_interrupts();
+		enable_interrupts ();
 
 	/* data polling for D7 */
 	start = get_timer (0);
 
-     if(info->flash_id > FLASH_AMD_COMP) {
+	if (info->flash_id > FLASH_AMD_COMP) {
 
-	while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) {
-		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
-			return (1);
+		while ((*((vu_long *) dest) & 0x00800080) !=
+		       (data & 0x00800080)) {
+			if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+				return (1);
+			}
 		}
-	}
 
-     } else {
+	} else {
 
-	while(!(addr[0] & 0x00800080)){  	/* wait for error or finish */
-		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
-			return (1);
-	}
+		while (!(addr[0] & 0x00800080)) {	/* wait for error or finish */
+			if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+				return (1);
+			}
 
-	if( addr[0] & 0x003A003A) {	/* check for error */
-		barf = addr[0] & 0x003A0000;
-		if( barf ) {
-			barf >>=16;
-		} else {
-			barf = addr[0] & 0x0000003A;
-		}
-		printf("\nFlash write error at address %lx\n",(unsigned long)dest);
-		if(barf & 0x0002) printf("Block locked, not erased.\n");
-		if(barf & 0x0010) printf("Programming error.\n");
-		if(barf & 0x0008) printf("Vpp Low error.\n");
-		return(2);
-	}
+			if (addr[0] & 0x003A003A) {	/* check for error */
+				barf = addr[0] & 0x003A0000;
+				if (barf) {
+					barf >>= 16;
+				} else {
+					barf = addr[0] & 0x0000003A;
+				}
+				printf ("\nFlash write error at address %lx\n",
+					(unsigned long) dest);
+				if (barf & 0x0002)
+					printf ("Block locked, not erased.\n");
+				if (barf & 0x0010)
+					printf ("Programming error.\n");
+				if (barf & 0x0008)
+					printf ("Vpp Low error.\n");
+				return (2);
+			}
 
 
-     }
+		}
 
-	return (0);
+		return (0);
 
-}
+	}
 
 #else
 
-static int write_short (flash_info_t *info, ulong dest, ushort data)
+static int write_short (flash_info_t * info, ulong dest, ushort data)
 {
-	vu_short *addr = (vu_short*)(info->start[0]);
-	ulong start,barf;
+	vu_short *addr = (vu_short *) (info->start[0]);
+	ulong start, barf;
 	int flag;
 
 	/* Check if Flash is (sufficiently) erased */
-	if ((*((vu_short *)dest) & data) != data) {
+	if ((*((vu_short *) dest) & data) != data) {
 		return (2);
 	}
 
 	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts();
+	flag = disable_interrupts ();
 
-     if(info->flash_id < FLASH_AMD_COMP) {
-	/* AMD stuff */
-	addr[0x0555] = 0x00AA;
-	addr[0x02AA] = 0x0055;
-	addr[0x0555] = 0x00A0;
-     } else {
-	/* intel stuff */
-	*addr = 0x00D0;
-	*addr = 0x0040;
-     }
-	*((vu_short *)dest) = data;
+	if (info->flash_id < FLASH_AMD_COMP) {
+		/* AMD stuff */
+		addr[0x0555] = 0x00AA;
+		addr[0x02AA] = 0x0055;
+		addr[0x0555] = 0x00A0;
+	} else {
+		/* intel stuff */
+		*addr = 0x00D0;
+		*addr = 0x0040;
+	}
+	*((vu_short *) dest) = data;
 
 	/* re-enable interrupts if necessary */
 	if (flag)
-		enable_interrupts();
+		enable_interrupts ();
 
 	/* data polling for D7 */
 	start = get_timer (0);
 
-     if(info->flash_id < FLASH_AMD_COMP) {
-	  /* AMD stuff */
-	while ((*((vu_short *)dest) & 0x0080) != (data & 0x0080)) {
-		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
-			return (1);
+	if (info->flash_id < FLASH_AMD_COMP) {
+		/* AMD stuff */
+		while ((*((vu_short *) dest) & 0x0080) != (data & 0x0080)) {
+			if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+				return (1);
+			}
 		}
-	}
 
-     } else {
-	/* intel stuff */
-	while(!(addr[0] & 0x0080)){  	/* wait for error or finish */
-		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) return (1);
-	}
+	} else {
+		/* intel stuff */
+		while (!(addr[0] & 0x0080)) {	/* wait for error or finish */
+			if (get_timer (start) > CFG_FLASH_WRITE_TOUT)
+				return (1);
+		}
 
-	if( addr[0] & 0x003A) {	/* check for error */
-		barf = addr[0] & 0x003A;
-		printf("\nFlash write error at address %lx\n",(unsigned long)dest);
-		if(barf & 0x0002) printf("Block locked, not erased.\n");
-		if(barf & 0x0010) printf("Programming error.\n");
-		if(barf & 0x0008) printf("Vpp Low error.\n");
-		return(2);
-	}
-	*addr = 0x00B0;
-	*addr = 0x0070;
-	while(!(addr[0] & 0x0080)){  	/* wait for error or finish */
-		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) return (1);
+		if (addr[0] & 0x003A) {	/* check for error */
+			barf = addr[0] & 0x003A;
+			printf ("\nFlash write error at address %lx\n",
+				(unsigned long) dest);
+			if (barf & 0x0002)
+				printf ("Block locked, not erased.\n");
+			if (barf & 0x0010)
+				printf ("Programming error.\n");
+			if (barf & 0x0008)
+				printf ("Vpp Low error.\n");
+			return (2);
+		}
+		*addr = 0x00B0;
+		*addr = 0x0070;
+		while (!(addr[0] & 0x0080)) {	/* wait for error or finish */
+			if (get_timer (start) > CFG_FLASH_WRITE_TOUT)
+				return (1);
+		}
+		*addr = 0x00FF;
 	}
-
-	*addr = 0x00FF;
-
-     }
-
 	return (0);
-
 }
-
-
 #endif
-
-/*-----------------------------------------------------------------------
- */
+/*-----------------------------------------------------------------------*/
diff --git a/board/eric/u-boot.lds b/board/eric/u-boot.lds
index 799002ff6c..00e35a6b8d 100644
--- a/board/eric/u-boot.lds
+++ b/board/eric/u-boot.lds
@@ -38,11 +38,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/esd/adciop/u-boot.lds b/board/esd/adciop/u-boot.lds
index 50250b14ce..db65fe69b3 100644
--- a/board/esd/adciop/u-boot.lds
+++ b/board/esd/adciop/u-boot.lds
@@ -38,11 +38,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/esd/apc405/u-boot.lds b/board/esd/apc405/u-boot.lds
index f5daaefd24..21547ac275 100644
--- a/board/esd/apc405/u-boot.lds
+++ b/board/esd/apc405/u-boot.lds
@@ -38,11 +38,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/esd/ar405/u-boot.lds b/board/esd/ar405/u-boot.lds
index f4b5e3a7de..b072bbb3ee 100644
--- a/board/esd/ar405/u-boot.lds
+++ b/board/esd/ar405/u-boot.lds
@@ -38,11 +38,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/esd/ash405/u-boot.lds b/board/esd/ash405/u-boot.lds
index 1c5d8916b5..644174a46d 100644
--- a/board/esd/ash405/u-boot.lds
+++ b/board/esd/ash405/u-boot.lds
@@ -38,11 +38,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/esd/canbt/u-boot.lds b/board/esd/canbt/u-boot.lds
index 07e8110531..e66db5d233 100644
--- a/board/esd/canbt/u-boot.lds
+++ b/board/esd/canbt/u-boot.lds
@@ -38,11 +38,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/esd/cms700/cms700.c b/board/esd/cms700/cms700.c
index 2cdd7be360..3d4f2371d9 100644
--- a/board/esd/cms700/cms700.c
+++ b/board/esd/cms700/cms700.c
@@ -92,7 +92,7 @@ int misc_init_r (void)
 	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
 	gd->bd->bi_flashoffset = 0;
 
- 	/*
+	/*
 	 * Setup and enable EEPROM write protection
 	 */
 	out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_EEPROM_WP);
diff --git a/board/esd/cms700/u-boot.lds b/board/esd/cms700/u-boot.lds
index f5daaefd24..21547ac275 100644
--- a/board/esd/cms700/u-boot.lds
+++ b/board/esd/cms700/u-boot.lds
@@ -38,11 +38,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/esd/cpci2dp/u-boot.lds b/board/esd/cpci2dp/u-boot.lds
index f5daaefd24..21547ac275 100644
--- a/board/esd/cpci2dp/u-boot.lds
+++ b/board/esd/cpci2dp/u-boot.lds
@@ -38,11 +38,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/esd/cpci405/u-boot.lds b/board/esd/cpci405/u-boot.lds
index f5daaefd24..21547ac275 100644
--- a/board/esd/cpci405/u-boot.lds
+++ b/board/esd/cpci405/u-boot.lds
@@ -38,11 +38,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/esd/cpci5200/Makefile b/board/esd/cpci5200/Makefile
index 276eabb9f5..673a5b9662 100644
--- a/board/esd/cpci5200/Makefile
+++ b/board/esd/cpci5200/Makefile
@@ -30,8 +30,8 @@ LIB	= $(obj)lib$(BOARD).a
 
 # Objects for Xilinx JTAG programming (CPLD)
 # CPLD  = ../common/xilinx_jtag/lenval.o \
-# 	  ../common/xilinx_jtag/micro.o \
-# 	  ../common/xilinx_jtag/ports.o
+#	  ../common/xilinx_jtag/micro.o \
+#	  ../common/xilinx_jtag/ports.o
 
 # COBJS	= $(BOARD).o flash.o $(CPLD)
 COBJS	= $(BOARD).o strataflash.o
diff --git a/board/esd/cpci750/mpsc.c b/board/esd/cpci750/mpsc.c
index 25c10e062e..fa8d3bda96 100644
--- a/board/esd/cpci750/mpsc.c
+++ b/board/esd/cpci750/mpsc.c
@@ -426,7 +426,7 @@ void mpsc_sdma_init (void)
 			 (MV64360_SDMA_WIN_ACCESS_FULL <<
 			  (MV64360_CUNIT_BASE_ADDR_WIN_0_BIT * 2)));
 
-/* Setup MPSC internal address space base address 	*/
+/* Setup MPSC internal address space base address	*/
 	GT_REG_WRITE (CUNIT_INTERNAL_SPACE_BASE_ADDR_REG, CFG_GT_REGS);
 
 /* no high address remap*/
diff --git a/board/esd/cpci750/mpsc.h b/board/esd/cpci750/mpsc.h
index a03d1cc0f8..aa0f862ee8 100644
--- a/board/esd/cpci750/mpsc.h
+++ b/board/esd/cpci750/mpsc.h
@@ -67,9 +67,9 @@ extern int (*mpsc_test_char)(void);
 #define TX_STOP     0x00010000
 #define RX_ENABLE   0x00000080
 
-#define SDMA_RX_ABORT 		  (1 << 15)
-#define SDMA_TX_ABORT 		  (1 << 31)
-#define MPSC_TX_ABORT 		  (1 << 7)
+#define SDMA_RX_ABORT		  (1 << 15)
+#define SDMA_TX_ABORT		  (1 << 31)
+#define MPSC_TX_ABORT		  (1 << 7)
 #define MPSC_RX_ABORT             (1 << 23)
 #define MPSC_ENTER_HUNT           (1 << 31)
 
diff --git a/board/esd/cpci750/mv_eth.c b/board/esd/cpci750/mv_eth.c
index bc84ef08e6..1c215277cf 100644
--- a/board/esd/cpci750/mv_eth.c
+++ b/board/esd/cpci750/mv_eth.c
@@ -1392,7 +1392,7 @@ u32 mv_get_internal_sram_base (void)
 *       port_phy_addr).
 *
 * INPUT:
-*       ETH_PORT_INFO 	*p_eth_port_ctrl       Ethernet port control struct
+*       ETH_PORT_INFO	*p_eth_port_ctrl       Ethernet port control struct
 *
 * OUTPUT:
 *       See description.
@@ -1552,7 +1552,7 @@ static void eth_port_init (ETH_PORT_INFO * p_eth_port_ctrl)
 *       ether_init_rx_desc_ring for Rx queues).
 *
 * INPUT:
-*       ETH_PORT_INFO 	*p_eth_port_ctrl       Ethernet port control struct
+*       ETH_PORT_INFO	*p_eth_port_ctrl       Ethernet port control struct
 *
 * OUTPUT:
 *       Ethernet port is ready to receive and transmit.
@@ -1642,7 +1642,7 @@ static bool eth_port_start (ETH_PORT_INFO * p_eth_port_ctrl)
 * INPUT:
 *	ETH_PORT eth_port_num     Port number.
 *	char *        p_addr		Address to be set
-*	ETH_QUEUE 	  queue		Rx queue number for this MAC address.
+*	ETH_QUEUE	  queue		Rx queue number for this MAC address.
 *
 * OUTPUT:
 *	Set MAC address low and high registers. also calls eth_port_uc_addr()
@@ -1680,10 +1680,10 @@ static void eth_port_uc_addr_set (ETH_PORT eth_port_num,
 *	parameters.
 *
 * INPUT:
-*	ETH_PORT 	eth_port_num      Port number.
+*	ETH_PORT	eth_port_num      Port number.
 *	unsigned char uc_nibble		Unicast MAC Address last nibble.
-*	ETH_QUEUE 		 queue		Rx queue number for this MAC address.
-*	int 			option      0 = Add, 1 = remove address.
+*	ETH_QUEUE		 queue		Rx queue number for this MAC address.
+*	int			option      0 = Add, 1 = remove address.
 *
 * OUTPUT:
 *	This function add/removes MAC addresses from the port unicast address
@@ -1762,10 +1762,10 @@ static bool eth_port_uc_addr (ETH_PORT eth_port_num,
 *	   In this case, the function calculates the CRC-8bit value and calls
 *	   eth_port_omc_addr() routine to set the Other Multicast Table.
 * INPUT:
-*	ETH_PORT 	eth_port_num      Port number.
-*	unsigned char 	*p_addr		Unicast MAC Address.
-*	ETH_QUEUE 		 queue		Rx queue number for this MAC address.
-*	int 			option      0 = Add, 1 = remove address.
+*	ETH_PORT	eth_port_num      Port number.
+*	unsigned char	*p_addr		Unicast MAC Address.
+*	ETH_QUEUE		 queue		Rx queue number for this MAC address.
+*	int			option      0 = Add, 1 = remove address.
 *
 * OUTPUT:
 *	See description.
@@ -1896,10 +1896,10 @@ static void eth_port_mc_addr (ETH_PORT eth_port_num,
 *	according to the argument given.
 *
 * INPUT:
-*	ETH_PORT 	eth_port_num      Port number.
-*	unsigned char 	mc_byte		Multicast addr last byte (MAC DA[7:0] bits).
-*	ETH_QUEUE 		 queue		Rx queue number for this MAC address.
-*	int 			option      0 = Add, 1 = remove address.
+*	ETH_PORT	eth_port_num      Port number.
+*	unsigned char	mc_byte		Multicast addr last byte (MAC DA[7:0] bits).
+*	ETH_QUEUE		 queue		Rx queue number for this MAC address.
+*	int			option      0 = Add, 1 = remove address.
 *
 * OUTPUT:
 *	See description.
@@ -1960,10 +1960,10 @@ static bool eth_port_smc_addr (ETH_PORT eth_port_num,
 *	CRC-8 argument given.
 *
 * INPUT:
-*	ETH_PORT 	eth_port_num      Port number.
-*	unsigned char 	  crc8		A CRC-8bit (Polynomial: x^8+x^2+x^1+1).
-*	ETH_QUEUE 		 queue		Rx queue number for this MAC address.
-*	int 			option      0 = Add, 1 = remove address.
+*	ETH_PORT	eth_port_num      Port number.
+*	unsigned char	  crc8		A CRC-8bit (Polynomial: x^8+x^2+x^1+1).
+*	ETH_QUEUE		 queue		Rx queue number for this MAC address.
+*	int			option      0 = Add, 1 = remove address.
 *
 * OUTPUT:
 *	See description.
@@ -2204,7 +2204,7 @@ static bool ethernet_phy_reset (ETH_PORT eth_port_num)
  * eth_port_reset - Reset Ethernet port
  *
  * DESCRIPTION:
- * 	This routine resets the chip by aborting any SDMA engine activity and
+ *	This routine resets the chip by aborting any SDMA engine activity and
  *      clearing the MIB counters. The Receiver and the Transmit unit are in
  *      idle state after this command is performed and the port is disabled.
  *
@@ -2557,9 +2557,9 @@ static void eth_set_access_control (ETH_PORT eth_port_num,
  *
  * INPUT:
  *	ETH_PORT_INFO   *p_eth_port_ctrl   Ethernet Port Control srtuct.
- *	ETH_QUEUE   	rx_queue         Number of Rx queue.
- *      int 			rx_desc_num       Number of Rx descriptors
- *      int 			rx_buff_size      Size of Rx buffer
+ *	ETH_QUEUE	rx_queue         Number of Rx queue.
+ *      int			rx_desc_num       Number of Rx descriptors
+ *      int			rx_buff_size      Size of Rx buffer
  *      unsigned int    rx_desc_base_addr  Rx descriptors memory area base addr.
  *      unsigned int    rx_buff_base_addr  Rx buffer memory area base addr.
  *
@@ -2651,9 +2651,9 @@ static bool ether_init_rx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl,
  *
  * INPUT:
  *	ETH_PORT_INFO   *p_eth_port_ctrl   Ethernet Port Control srtuct.
- *	ETH_QUEUE   	tx_queue         Number of Tx queue.
- *      int 			tx_desc_num       Number of Tx descriptors
- *      int 			tx_buff_size      Size of Tx buffer
+ *	ETH_QUEUE	tx_queue         Number of Tx queue.
+ *      int			tx_desc_num       Number of Tx descriptors
+ *      int			tx_buff_size      Size of Tx buffer
  *      unsigned int    tx_desc_base_addr  Tx descriptors memory area base addr.
  *      unsigned int    tx_buff_base_addr  Tx buffer memory area base addr.
  *
@@ -2746,7 +2746,7 @@ static bool ether_init_tx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl,
  *
  * INPUT:
  *	ETH_PORT_INFO   *p_eth_port_ctrl   Ethernet Port Control srtuct.
- *	ETH_QUEUE   	tx_queue         Number of Tx queue.
+ *	ETH_QUEUE	tx_queue         Number of Tx queue.
  *	PKT_INFO        *p_pkt_info       User packet buffer.
  *
  * OUTPUT:
@@ -2862,7 +2862,7 @@ static ETH_FUNC_RET_STATUS eth_port_send (ETH_PORT_INFO * p_eth_port_ctrl,
  *
  * INPUT:
  *	ETH_PORT_INFO   *p_eth_port_ctrl   Ethernet Port Control srtuct.
- *	ETH_QUEUE   	tx_queue         Number of Tx queue.
+ *	ETH_QUEUE	tx_queue         Number of Tx queue.
  *	PKT_INFO        *p_pkt_info       User packet buffer.
  *
  * OUTPUT:
@@ -2931,7 +2931,7 @@ static ETH_FUNC_RET_STATUS eth_tx_return_desc (ETH_PORT_INFO *
  * eth_port_receive - Get received information from Rx ring.
  *
  * DESCRIPTION:
- * 	This routine returns the received data to the caller. There is no
+ *	This routine returns the received data to the caller. There is no
  *	data copying during routine operation. All information is returned
  *	using pointer to packet information struct passed from the caller.
  *      If the routine exhausts	Rx ring resources then the resource error flag
@@ -2939,7 +2939,7 @@ static ETH_FUNC_RET_STATUS eth_tx_return_desc (ETH_PORT_INFO *
  *
  * INPUT:
  *	ETH_PORT_INFO   *p_eth_port_ctrl   Ethernet Port Control srtuct.
- *	ETH_QUEUE   	rx_queue         Number of Rx queue.
+ *	ETH_QUEUE	rx_queue         Number of Rx queue.
  *	PKT_INFO        *p_pkt_info       User packet buffer.
  *
  * OUTPUT:
@@ -2981,7 +2981,7 @@ static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO * p_eth_port_ctrl,
 
 	/* Nothing to receive... */
 	if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) {
-/* 	DP(printf("Rx: command_status: %08x\n", command_status)); */
+/*	DP(printf("Rx: command_status: %08x\n", command_status)); */
 		D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0);
 /*	DP(printf("\nETH_END_OF_JOB ...\n"));*/
 		return ETH_END_OF_JOB;
@@ -3020,7 +3020,7 @@ static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO * p_eth_port_ctrl,
  *
  * INPUT:
  *	ETH_PORT_INFO   *p_eth_port_ctrl   Ethernet Port Control srtuct.
- *	ETH_QUEUE   	rx_queue         Number of Rx queue.
+ *	ETH_QUEUE	rx_queue         Number of Rx queue.
  *      PKT_INFO        *p_pkt_info       Information on the returned buffer.
  *
  * OUTPUT:
diff --git a/board/esd/cpci750/sdram_init.c b/board/esd/cpci750/sdram_init.c
index 78d1880185..f43e83f491 100644
--- a/board/esd/cpci750/sdram_init.c
+++ b/board/esd/cpci750/sdram_init.c
@@ -106,7 +106,7 @@ memory_map_bank(unsigned int bankNo,
 	return 0;
 }
 
-#define GB         (1 << 30)
+#define GB	   (1 << 30)
 
 /* much of this code is based on (or is) the code in the pip405 port */
 /* thanks go to the authors of said port - Josh */
@@ -134,86 +134,85 @@ typedef enum _max_CL_supported_SD {SD_CL_1=1,  SD_CL_2,  SD_CL_3, SD_CL_4, SD_CL
 
 
 /* SDRAM/DDR information struct */
-typedef struct _gtMemoryDimmInfo
-{
-    MEMORY_TYPE          memoryType;
-    unsigned int         numOfRowAddresses;
-    unsigned int         numOfColAddresses;
-    unsigned int         numOfModuleBanks;
-    unsigned int         dataWidth;
-    VOLTAGE_INTERFACE    voltageInterface;
-    unsigned int         errorCheckType;                                /* ECC , PARITY..*/
-    unsigned int         sdramWidth;                                    /* 4,8,16 or 32 */;
-    unsigned int         errorCheckDataWidth;                           /* 0 - no, 1 - Yes */
-    unsigned int         minClkDelay;
-    unsigned int         burstLengthSupported;
-    unsigned int         numOfBanksOnEachDevice;
-    unsigned int         suportedCasLatencies;
-    unsigned int     	 RefreshInterval;
-    unsigned int   	 maxCASlatencySupported_LoP;			/* LoP left of point (measured in ns) */
-    unsigned int   	 maxCASlatencySupported_RoP;			/* RoP right of point (measured in ns)*/
-    MAX_CL_SUPPORTED_DDR maxClSupported_DDR;
-    MAX_CL_SUPPORTED_SD  maxClSupported_SD;
-    unsigned int         moduleBankDensity;
-    /* module attributes (true for yes) */
-    bool                 bufferedAddrAndControlInputs;
-    bool                 registeredAddrAndControlInputs;
-    bool                 onCardPLL;
-    bool                 bufferedDQMBinputs;
-    bool                 registeredDQMBinputs;
-    bool	         differentialClockInput;
-    bool                 redundantRowAddressing;
-
-    /* module general attributes */
-    bool                 suportedAutoPreCharge;
-    bool                 suportedPreChargeAll;
-    bool                 suportedEarlyRasPreCharge;
-    bool                 suportedWrite1ReadBurst;
-    bool                 suported5PercentLowVCC;
-    bool                 suported5PercentUpperVCC;
-    /* module timing parameters */
-    unsigned int         minRasToCasDelay;
-    unsigned int         minRowActiveRowActiveDelay;
-    unsigned int         minRasPulseWidth;
-    unsigned int         minRowPrechargeTime;   			/* measured in ns */
-
-    int   	         addrAndCommandHoldTime;			/* LoP left of point (measured in ns) */
-    int   	         addrAndCommandSetupTime;				/* (measured in ns/100) */
-    int   	         dataInputSetupTime;				/* LoP left of point (measured in ns) */
-    int   	         dataInputHoldTime;				/* LoP left of point (measured in ns) */
+typedef struct _gtMemoryDimmInfo {
+	MEMORY_TYPE memoryType;
+	unsigned int numOfRowAddresses;
+	unsigned int numOfColAddresses;
+	unsigned int numOfModuleBanks;
+	unsigned int dataWidth;
+	VOLTAGE_INTERFACE voltageInterface;
+	unsigned int errorCheckType;			/* ECC , PARITY.. */
+	unsigned int sdramWidth;			/* 4,8,16 or 32 */ ;
+	unsigned int errorCheckDataWidth;		/* 0 - no, 1 - Yes */
+	unsigned int minClkDelay;
+	unsigned int burstLengthSupported;
+	unsigned int numOfBanksOnEachDevice;
+	unsigned int suportedCasLatencies;
+	unsigned int RefreshInterval;
+	unsigned int maxCASlatencySupported_LoP;	/* LoP left of point (measured in ns) */
+	unsigned int maxCASlatencySupported_RoP;	/* RoP right of point (measured in ns) */
+	MAX_CL_SUPPORTED_DDR maxClSupported_DDR;
+	MAX_CL_SUPPORTED_SD maxClSupported_SD;
+	unsigned int moduleBankDensity;
+	/* module attributes (true for yes) */
+	bool bufferedAddrAndControlInputs;
+	bool registeredAddrAndControlInputs;
+	bool onCardPLL;
+	bool bufferedDQMBinputs;
+	bool registeredDQMBinputs;
+	bool differentialClockInput;
+	bool redundantRowAddressing;
+
+	/* module general attributes */
+	bool suportedAutoPreCharge;
+	bool suportedPreChargeAll;
+	bool suportedEarlyRasPreCharge;
+	bool suportedWrite1ReadBurst;
+	bool suported5PercentLowVCC;
+	bool suported5PercentUpperVCC;
+	/* module timing parameters */
+	unsigned int minRasToCasDelay;
+	unsigned int minRowActiveRowActiveDelay;
+	unsigned int minRasPulseWidth;
+	unsigned int minRowPrechargeTime;		/* measured in ns */
+
+	int addrAndCommandHoldTime;			/* LoP left of point (measured in ns) */
+	int addrAndCommandSetupTime;			/* (measured in ns/100) */
+	int dataInputSetupTime;				/* LoP left of point (measured in ns) */
+	int dataInputHoldTime;				/* LoP left of point (measured in ns) */
 /* tAC times for highest 2nd and 3rd highest CAS Latency values */
-    unsigned int   	 clockToDataOut_LoP;				/* LoP left of point (measured in ns) */
-    unsigned int   	 clockToDataOut_RoP;				/* RoP right of point (measured in ns)*/
-    unsigned int   	 clockToDataOutMinus1_LoP;				/* LoP left of point (measured in ns) */
-    unsigned int   	 clockToDataOutMinus1_RoP;			/* RoP right of point (measured in ns)*/
-    unsigned int   	 clockToDataOutMinus2_LoP;				/* LoP left of point (measured in ns) */
-    unsigned int   	 clockToDataOutMinus2_RoP;			/* RoP right of point (measured in ns)*/
-
-    unsigned int   	 minimumCycleTimeAtMaxCasLatancy_LoP;		/* LoP left of point (measured in ns) */
-    unsigned int   	 minimumCycleTimeAtMaxCasLatancy_RoP;		/* RoP right of point (measured in ns)*/
-
-    unsigned int   	 minimumCycleTimeAtMaxCasLatancyMinus1_LoP;	/* LoP left of point (measured in ns) */
-    unsigned int   	 minimumCycleTimeAtMaxCasLatancyMinus1_RoP;	/* RoP right of point (measured in ns)*/
-
-    unsigned int   	 minimumCycleTimeAtMaxCasLatancyMinus2_LoP;	/* LoP left of point (measured in ns) */
-    unsigned int   	 minimumCycleTimeAtMaxCasLatancyMinus2_RoP;	/* RoP right of point (measured in ns)*/
-
-    /* Parameters calculated from
-       the extracted DIMM information */
-    unsigned int         size;
-    unsigned int         deviceDensity;           		       	/* 16,64,128,256 or 512 Mbit */
-    unsigned int         numberOfDevices;
-    uchar 		 drb_size;				       	/* DRAM size in n*64Mbit */
-    uchar 		 slot;						/* Slot Number this module is inserted in */
-    uchar 		 spd_raw_data[128];			       	/* Content of SPD-EEPROM copied 1:1 */
+	unsigned int clockToDataOut_LoP;		/* LoP left of point (measured in ns) */
+	unsigned int clockToDataOut_RoP;		/* RoP right of point (measured in ns) */
+	unsigned int clockToDataOutMinus1_LoP;		/* LoP left of point (measured in ns) */
+	unsigned int clockToDataOutMinus1_RoP;		/* RoP right of point (measured in ns) */
+	unsigned int clockToDataOutMinus2_LoP;		/* LoP left of point (measured in ns) */
+	unsigned int clockToDataOutMinus2_RoP;		/* RoP right of point (measured in ns) */
+
+	unsigned int minimumCycleTimeAtMaxCasLatancy_LoP;	/* LoP left of point (measured in ns) */
+	unsigned int minimumCycleTimeAtMaxCasLatancy_RoP;	/* RoP right of point (measured in ns) */
+
+	unsigned int minimumCycleTimeAtMaxCasLatancyMinus1_LoP;	/* LoP left of point (measured in ns) */
+	unsigned int minimumCycleTimeAtMaxCasLatancyMinus1_RoP;	/* RoP right of point (measured in ns) */
+
+	unsigned int minimumCycleTimeAtMaxCasLatancyMinus2_LoP;	/* LoP left of point (measured in ns) */
+	unsigned int minimumCycleTimeAtMaxCasLatancyMinus2_RoP;	/* RoP right of point (measured in ns) */
+
+	/* Parameters calculated from
+	   the extracted DIMM information */
+	unsigned int size;
+	unsigned int deviceDensity;			/* 16,64,128,256 or 512 Mbit */
+	unsigned int numberOfDevices;
+	uchar drb_size;					/* DRAM size in n*64Mbit */
+	uchar slot;					/* Slot Number this module is inserted in */
+	uchar spd_raw_data[128];			/* Content of SPD-EEPROM copied 1:1 */
 #ifdef DEBUG
-    uchar 		 manufactura[8];				/* Content of SPD-EEPROM Byte 64-71 */
-    uchar 		 modul_id[18];					/* Content of SPD-EEPROM Byte 73-90 */
-    uchar 		 vendor_data[27];			       	/* Content of SPD-EEPROM Byte 99-125 */
-    unsigned long	 modul_serial_no;			       	/* Content of SPD-EEPROM Byte 95-98 */
-    unsigned int         manufac_date;					/* Content of SPD-EEPROM Byte 93-94 */
-    unsigned int         modul_revision;				/* Content of SPD-EEPROM Byte 91-92 */
-    uchar 		 manufac_place;					/* Content of SPD-EEPROM Byte 72 */
+	uchar manufactura[8];				/* Content of SPD-EEPROM Byte 64-71 */
+	uchar modul_id[18];				/* Content of SPD-EEPROM Byte 73-90 */
+	uchar vendor_data[27];				/* Content of SPD-EEPROM Byte 99-125 */
+	unsigned long modul_serial_no;			/* Content of SPD-EEPROM Byte 95-98 */
+	unsigned int manufac_date;			/* Content of SPD-EEPROM Byte 93-94 */
+	unsigned int modul_revision;			/* Content of SPD-EEPROM Byte 91-92 */
+	uchar manufac_place;				/* Content of SPD-EEPROM Byte 72 */
 
 #endif
 } AUX_MEM_DIMM_INFO;
@@ -364,31 +363,31 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo)
 	for (i = 0; i < sizeof (dimmInfo->manufactura); i++) {
 		dimmInfo->manufactura[i] = data[64 + i];
 	}
-	printf ("\nThis RAM-Module is produced by: 		%s\n",
+	printf ("\nThis RAM-Module is produced by:		%s\n",
 		dimmInfo->manufactura);
 
 	/* find Manul-ID of Dimm Module */
 	for (i = 0; i < sizeof (dimmInfo->modul_id); i++) {
 		dimmInfo->modul_id[i] = data[73 + i];
 	}
-	printf ("The Module-ID of this RAM-Module is: 		%s\n",
+	printf ("The Module-ID of this RAM-Module is:		%s\n",
 		dimmInfo->modul_id);
 
 	/* find Vendor-Data of Dimm Module */
 	for (i = 0; i < sizeof (dimmInfo->vendor_data); i++) {
 		dimmInfo->vendor_data[i] = data[99 + i];
 	}
-	printf ("Vendor Data of this RAM-Module is: 		%s\n",
+	printf ("Vendor Data of this RAM-Module is:		%s\n",
 		dimmInfo->vendor_data);
 
 	/* find modul_serial_no of Dimm Module */
 	dimmInfo->modul_serial_no = (*((unsigned long *) (&data[95])));
-	printf ("Serial No. of this RAM-Module is: 		%ld (%lx)\n",
+	printf ("Serial No. of this RAM-Module is:		%ld (%lx)\n",
 		dimmInfo->modul_serial_no, dimmInfo->modul_serial_no);
 
 	/* find Manufac-Data of Dimm Module */
 	dimmInfo->manufac_date = (*((unsigned int *) (&data[93])));
-	printf ("Manufactoring Date of this RAM-Module is: 	%d.%d\n", data[93], data[94]);	/*dimmInfo->manufac_date */
+	printf ("Manufactoring Date of this RAM-Module is:	%d.%d\n", data[93], data[94]);	/*dimmInfo->manufac_date */
 
 	/* find modul_revision of Dimm Module */
 	dimmInfo->modul_revision = (*((unsigned int *) (&data[91])));
@@ -396,7 +395,7 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo)
 
 	/* find manufac_place of Dimm Module */
 	dimmInfo->manufac_place = (*((unsigned char *) (&data[72])));
-	printf ("manufac_place of this RAM-Module is: 		%d\n",
+	printf ("manufac_place of this RAM-Module is:		%d\n",
 		dimmInfo->manufac_place);
 
 #endif
@@ -426,11 +425,11 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo)
 #ifdef DEBUG
 			if (dimmInfo->memoryType == 0)
 				DP (printf
-				    ("Dram_type in slot %d is: 			SDRAM\n",
+				    ("Dram_type in slot %d is:			SDRAM\n",
 				     dimmInfo->slot));
 			if (dimmInfo->memoryType == 1)
 				DP (printf
-				    ("Dram_type in slot %d is: 			DDRAM\n",
+				    ("Dram_type in slot %d is:			DDRAM\n",
 				     dimmInfo->slot));
 #endif
 			break;
@@ -439,7 +438,7 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo)
 		case 3:	/* Number Of Row Addresses */
 			dimmInfo->numOfRowAddresses = data[i];
 			DP (printf
-			    ("Module Number of row addresses: 		%d\n",
+			    ("Module Number of row addresses:		%d\n",
 			     dimmInfo->numOfRowAddresses));
 			break;
 /*------------------------------------------------------------------------------------------------------------------------------*/
@@ -447,7 +446,7 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo)
 		case 4:	/* Number Of Column Addresses */
 			dimmInfo->numOfColAddresses = data[i];
 			DP (printf
-			    ("Module Number of col addresses: 		%d\n",
+			    ("Module Number of col addresses:		%d\n",
 			     dimmInfo->numOfColAddresses));
 			break;
 /*------------------------------------------------------------------------------------------------------------------------------*/
@@ -463,7 +462,7 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo)
 		case 6:	/* Data Width */
 			dimmInfo->dataWidth = data[i];
 			DP (printf
-			    ("Module Data Width: 				%d\n",
+			    ("Module Data Width:				%d\n",
 			     dimmInfo->dataWidth));
 			break;
 /*------------------------------------------------------------------------------------------------------------------------------*/
@@ -518,7 +517,7 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo)
 			dimmInfo->minimumCycleTimeAtMaxCasLatancy_RoP =
 				rightOfPoint;
 			DP (printf
-			    ("Minimum Cycle Time At Max CasLatancy: 		%d.%d [ns]\n",
+			    ("Minimum Cycle Time At Max CasLatancy:		%d.%d [ns]\n",
 			     leftOfPoint, rightOfPoint));
 			break;
 /*------------------------------------------------------------------------------------------------------------------------------*/
@@ -533,7 +532,7 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo)
 			dimmInfo->clockToDataOut_LoP = leftOfPoint;
 			dimmInfo->clockToDataOut_RoP = rightOfPoint;
 			DP (printf
-			    ("Clock To Data Out: 				%d.%2d [ns]\n",
+			    ("Clock To Data Out:				%d.%2d [ns]\n",
 			     leftOfPoint, rightOfPoint));
 			/*dimmInfo->clockToDataOut */
 			break;
@@ -543,7 +542,7 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo)
 		case 11:	/* Error Check Type */
 			dimmInfo->errorCheckType = data[i];
 			DP (printf
-			    ("Error Check Type (0=NONE): 			%d\n",
+			    ("Error Check Type (0=NONE):			%d\n",
 			     dimmInfo->errorCheckType));
 			break;
 #endif
@@ -560,7 +559,7 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo)
 		case 13:	/* Sdram Width */
 			dimmInfo->sdramWidth = data[i];
 			DP (printf
-			    ("Sdram Width: 					%d\n",
+			    ("Sdram Width:					%d\n",
 			     dimmInfo->sdramWidth));
 			break;
 /*------------------------------------------------------------------------------------------------------------------------------*/
@@ -568,7 +567,7 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo)
 		case 14:	/* Error Check Data Width */
 			dimmInfo->errorCheckDataWidth = data[i];
 			DP (printf
-			    ("Error Check Data Width: 			%d\n",
+			    ("Error Check Data Width:			%d\n",
 			     dimmInfo->errorCheckDataWidth));
 			break;
 /*------------------------------------------------------------------------------------------------------------------------------*/
@@ -576,7 +575,7 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo)
 		case 15:	/* Minimum Clock Delay */
 			dimmInfo->minClkDelay = data[i];
 			DP (printf
-			    ("Minimum Clock Delay: 				%d\n",
+			    ("Minimum Clock Delay:				%d\n",
 			     dimmInfo->minClkDelay));
 			break;
 /*------------------------------------------------------------------------------------------------------------------------------*/
@@ -585,7 +584,7 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo)
 			   /******-******-******-*******
 			   * bit3 | bit2 | bit1 | bit0 *
 			   *******-******-******-*******
-	    burst length = *  8   |  4   |   2  |   1  *
+	    burst length = *  8   |  4	 |   2	|   1  *
 			   *****************************
 
 	    If for example bit0 and bit2 are set, the burst
@@ -594,7 +593,7 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo)
 			dimmInfo->burstLengthSupported = data[i];
 #ifdef DEBUG
 			DP (printf
-			    ("Burst Length Supported: 			"));
+			    ("Burst Length Supported:			"));
 			if (dimmInfo->burstLengthSupported & 0x01)
 				DP (printf ("1, "));
 			if (dimmInfo->burstLengthSupported & 0x02)
@@ -611,7 +610,7 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo)
 		case 17:	/* Number Of Banks On Each Device */
 			dimmInfo->numOfBanksOnEachDevice = data[i];
 			DP (printf
-			    ("Number Of Banks On Each Chip: 			%d\n",
+			    ("Number Of Banks On Each Chip:			%d\n",
 			     dimmInfo->numOfBanksOnEachDevice));
 			break;
 /*------------------------------------------------------------------------------------------------------------------------------*/
@@ -622,24 +621,24 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo)
 			 *******-******-******-******-******-******-******-*******
 			 * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 *
 			 *******-******-******-******-******-******-******-*******
-			 CAS =   * TBD  | TBD  | 3.5  |   3  | 2.5  |  2   | 1.5  |   1  *
+			 CAS =	 * TBD	| TBD  | 3.5  |   3  | 2.5  |  2   | 1.5  |   1  *
 			 *********************************************************
 			 SDRAM:
 			 *******-******-******-******-******-******-******-*******
 			 * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 *
 			 *******-******-******-******-******-******-******-*******
-			 CAS =   * TBD  |  7   |  6   |  5   |  4   |  3   |   2  |   1  *
+			 CAS =	 * TBD	|  7   |  6   |  5   |	4   |  3   |   2  |   1  *
 			 ********************************************************/
 			dimmInfo->suportedCasLatencies = data[i];
 #ifdef DEBUG
 			DP (printf
-			    ("Suported Cas Latencies: (CL) 			"));
+			    ("Suported Cas Latencies: (CL)			"));
 			if (dimmInfo->memoryType == 0) {	/* SDRAM */
 				for (k = 0; k <= 7; k++) {
 					if (dimmInfo->
 					    suportedCasLatencies & (1 << k))
 						DP (printf
-						    ("%d, 			",
+						    ("%d,			",
 						     k + 1));
 				}
 
@@ -738,7 +737,7 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo)
 								maxCASlatencySupported_RoP
 								= 0;
 						DP (printf
-						    ("Max. Cas Latencies (DDR LoP.RoP Notation): 	%d.%d \n",
+						    ("Max. Cas Latencies (DDR LoP.RoP Notation):	%d.%d \n",
 						     dimmInfo->
 						     maxCASlatencySupported_LoP,
 						     dimmInfo->
@@ -746,7 +745,7 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo)
 						break;
 					case SDRAM:
 						/* CAS latency 1, 2, 3, 4, 5, 6, 7 */
-						dimmInfo->maxClSupported_SD = j;	/*  Cas Latency DDR-RAM Coded                   */
+						dimmInfo->maxClSupported_SD = j;	/*  Cas Latency DDR-RAM Coded			*/
 						DP (printf
 						    ("Max. Cas Latencies (SD): %d\n",
 						     dimmInfo->
@@ -886,7 +885,7 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo)
 				    (" - lower VCC tolerance:			5 Percent \n"));
 			else
 				DP (printf
-				    ("  - lower VCC tolerance:			10 Percent \n"));
+				    ("	- lower VCC tolerance:			10 Percent \n"));
 
 			if (dimmInfo->suported5PercentUpperVCC == 1)
 				DP (printf
@@ -986,7 +985,7 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo)
 			    ("*** 1 clock cycle = %ld  10ps intervalls = %ld.%ld ns****\n",
 			     tmemclk, tmemclk / 100, tmemclk % 100));
 			DP (printf
-			    ("Minimum Row Precharge Time [ns]: 		%d.%2d = in Clk cycles %d\n",
+			    ("Minimum Row Precharge Time [ns]:		%d.%2d = in Clk cycles %d\n",
 			     leftOfPoint, rightOfPoint, trp_clocks));
 			break;
 /*------------------------------------------------------------------------------------------------------------------------------*/
@@ -1005,7 +1004,7 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo)
 				(dimmInfo->minRowActiveRowActiveDelay +
 				 (tmemclk - 1)) / tmemclk;
 			DP (printf
-			    ("Minimum Row Active -To- Row Active Delay [ns]: 	%d.%2d = in Clk cycles %d\n",
+			    ("Minimum Row Active -To- Row Active Delay [ns]:	%d.%2d = in Clk cycles %d\n",
 			     leftOfPoint, rightOfPoint, trp_clocks));
 			break;
 /*------------------------------------------------------------------------------------------------------------------------------*/
@@ -1024,7 +1023,7 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo)
 				(dimmInfo->minRowActiveRowActiveDelay +
 				 (tmemclk - 1)) / tmemclk;
 			DP (printf
-			    ("Minimum Ras-To-Cas Delay [ns]: 			%d.%2d = in Clk cycles %d\n",
+			    ("Minimum Ras-To-Cas Delay [ns]:			%d.%2d = in Clk cycles %d\n",
 			     leftOfPoint, rightOfPoint, trp_clocks));
 			break;
 /*------------------------------------------------------------------------------------------------------------------------------*/
@@ -1035,7 +1034,7 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo)
 				(NSto10PS (data[i]) +
 				 (tmemclk - 1)) / tmemclk;
 			DP (printf
-			    ("Minimum Ras Pulse Width [ns]: 			%d = in Clk cycles %d\n",
+			    ("Minimum Ras Pulse Width [ns]:			%d = in Clk cycles %d\n",
 			     dimmInfo->minRasPulseWidth, tras_clocks));
 
 			break;
@@ -1044,7 +1043,7 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo)
 		case 31:	/* Module Bank Density */
 			dimmInfo->moduleBankDensity = data[i];
 			DP (printf
-			    ("Module Bank Density: 				%d\n",
+			    ("Module Bank Density:				%d\n",
 			     dimmInfo->moduleBankDensity));
 #ifdef DEBUG
 			DP (printf
@@ -1095,7 +1094,7 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo)
 			dimmInfo->addrAndCommandSetupTime =
 				(leftOfPoint * 100 + rightOfPoint) * sign;
 			DP (printf
-			    ("Address And Command Setup Time [ns]: 		%d.%d\n",
+			    ("Address And Command Setup Time [ns]:		%d.%d\n",
 			     sign * leftOfPoint, rightOfPoint));
 			break;
 /*------------------------------------------------------------------------------------------------------------------------------*/
@@ -1122,7 +1121,7 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo)
 			dimmInfo->addrAndCommandHoldTime =
 				(leftOfPoint * 100 + rightOfPoint) * sign;
 			DP (printf
-			    ("Address And Command Hold Time [ns]: 		%d.%d\n",
+			    ("Address And Command Hold Time [ns]:		%d.%d\n",
 			     sign * leftOfPoint, rightOfPoint));
 			break;
 /*------------------------------------------------------------------------------------------------------------------------------*/
@@ -1149,7 +1148,7 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo)
 			dimmInfo->dataInputSetupTime =
 				(leftOfPoint * 100 + rightOfPoint) * sign;
 			DP (printf
-			    ("Data Input Setup Time [ns]: 			%d.%d\n",
+			    ("Data Input Setup Time [ns]:			%d.%d\n",
 			     sign * leftOfPoint, rightOfPoint));
 			break;
 /*------------------------------------------------------------------------------------------------------------------------------*/
@@ -1176,7 +1175,7 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo)
 			dimmInfo->dataInputHoldTime =
 				(leftOfPoint * 100 + rightOfPoint) * sign;
 			DP (printf
-			    ("Data Input Hold Time [ns]: 			%d.%d\n\n",
+			    ("Data Input Hold Time [ns]:			%d.%d\n\n",
 			     sign * leftOfPoint, rightOfPoint));
 			break;
 /*------------------------------------------------------------------------------------------------------------------------------*/
@@ -1212,7 +1211,7 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo)
 	       (dimmInfo->numOfRowAddresses + dimmInfo->numOfColAddresses));
 	tmp *= dimmInfo->numOfModuleBanks;
 	tmp *= dimmInfo->sdramWidth;
-	tmp = tmp >> 24;	/* div by 0x4000000 (64M)       */
+	tmp = tmp >> 24;	/* div by 0x4000000 (64M)	*/
 	dimmInfo->drb_size = (uchar) tmp;
 	DP (printf ("Module DRB size (n*64Mbit): %d\n", dimmInfo->drb_size));
 
@@ -1328,7 +1327,7 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info)
 				DP (printf
 				    ("Max. CL is 2,5s CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
 				     tmp_sdram_mode, tmp_dunit_control_low));
-			} else {	/* clk sync. bypassed     */
+			} else {	/* clk sync. bypassed	  */
 
 				tmp_dunit_control_low = 0x03000000;	/* Read-Data sampled on rising edge of Clk */
 				tmp_sdram_mode = 0x62;	/* CL=2,5 Burstlength = 4 */
@@ -1345,7 +1344,7 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info)
 				DP (printf
 				    ("Max. CL is 2s CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
 				     tmp_sdram_mode, tmp_dunit_control_low));
-			} else {	/* Not sync.      */
+			} else {	/* Not sync.	  */
 
 				tmp_dunit_control_low = 0x3b000000;	/* Read-Data sampled on rising edge of Clk */
 				tmp_sdram_mode = 0x22;	/* CL=2 Burstlength = 4 */
@@ -1504,7 +1503,7 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info)
 
 /*	for (i = info->slot * 2; i < ((info->slot * 2) + info->banks); i++) */
 	{
-	        int l, l1;
+		int l, l1;
 
 		i = info->slot;
 		DP (printf
@@ -1518,31 +1517,31 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info)
 		GT_REG_WRITE (EXTENDED_DRAM_MODE, 0x0);
 		GT_REG_WRITE (SDRAM_OPERATION, 0x4);
 		while (GTREGREAD (SDRAM_OPERATION) != 0) {
-		        DP (printf
+			DP (printf
 			    ("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n"));
 		}
 
 		GT_REG_WRITE (SDRAM_MODE, tmp | 0x80);
 		GT_REG_WRITE (SDRAM_OPERATION, 0x3);
 		while (GTREGREAD (SDRAM_OPERATION) != 0) {
-		        DP (printf
+			DP (printf
 			    ("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n"));
 		}
 		l1 = 0;
 		for (l=0;l<200;l++)
-		        l1 += GTREGREAD (SDRAM_OPERATION);
+			l1 += GTREGREAD (SDRAM_OPERATION);
 
 		GT_REG_WRITE (SDRAM_MODE, tmp);
 		GT_REG_WRITE (SDRAM_OPERATION, 0x3);
 		while (GTREGREAD (SDRAM_OPERATION) != 0) {
-		        DP (printf
+			DP (printf
 			    ("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n"));
 		}
 
 		/* switch back to normal operation mode */
 		GT_REG_WRITE (SDRAM_OPERATION, 0x5);
 		while (GTREGREAD (SDRAM_OPERATION) != 0) {
-		        DP (printf
+			DP (printf
 			    ("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n"));
 		}
 
@@ -1677,16 +1676,16 @@ initdram(int board_type)
 }
 
 /* ***************************************************************************************
-! *                             SDRAM INIT                                              *
-! *  This procedure detect all Sdram types: 64, 128, 256, 512 Mbit, 1Gbit and 2Gb       *
-! *               This procedure fits only the Atlantis                                *
-! *                                                                                     *
+! *				SDRAM INIT						*
+! *  This procedure detect all Sdram types: 64, 128, 256, 512 Mbit, 1Gbit and 2Gb	*
+! *		  This procedure fits only the Atlantis				       *
+! *											*
 ! *************************************************************************************** */
 
 
 /* ***************************************************************************************
-! *                             DFCDL initialize MV643xx Design Considerations             *
-! *                                                                                     *
+! *				DFCDL initialize MV643xx Design Considerations		   *
+! *											*
 ! *************************************************************************************** */
 int set_dfcdlInit (void)
 {
diff --git a/board/esd/cpci750/u-boot.lds b/board/esd/cpci750/u-boot.lds
index 25e16de3b6..1a95755ab4 100644
--- a/board/esd/cpci750/u-boot.lds
+++ b/board/esd/cpci750/u-boot.lds
@@ -37,11 +37,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/esd/cpciiser4/u-boot.lds b/board/esd/cpciiser4/u-boot.lds
index f5daaefd24..21547ac275 100644
--- a/board/esd/cpciiser4/u-boot.lds
+++ b/board/esd/cpciiser4/u-boot.lds
@@ -38,11 +38,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/esd/dasa_sim/u-boot.lds b/board/esd/dasa_sim/u-boot.lds
index 2b5e33d55b..67d72f77fb 100644
--- a/board/esd/dasa_sim/u-boot.lds
+++ b/board/esd/dasa_sim/u-boot.lds
@@ -38,11 +38,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/esd/dp405/u-boot.lds b/board/esd/dp405/u-boot.lds
index 196f88c4df..d70d37934e 100644
--- a/board/esd/dp405/u-boot.lds
+++ b/board/esd/dp405/u-boot.lds
@@ -38,11 +38,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/esd/du405/u-boot.lds b/board/esd/du405/u-boot.lds
index 71ab63d671..46ef7e72ab 100644
--- a/board/esd/du405/u-boot.lds
+++ b/board/esd/du405/u-boot.lds
@@ -38,11 +38,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/esd/du440/u-boot.lds b/board/esd/du440/u-boot.lds
index da2a400b77..b20fb1c0a2 100644
--- a/board/esd/du440/u-boot.lds
+++ b/board/esd/du440/u-boot.lds
@@ -43,11 +43,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/esd/hh405/hh405.c b/board/esd/hh405/hh405.c
index 67b5d5406d..279d9214e2 100644
--- a/board/esd/hh405/hh405.c
+++ b/board/esd/hh405/hh405.c
@@ -471,7 +471,7 @@ int misc_init_r (void)
 	 */
 	*fpga_ctrl |= gd->board_type & 0x0003;
 
- 	/*
+	/*
 	 * Setup and enable EEPROM write protection
 	 */
 	out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP);
diff --git a/board/esd/hh405/u-boot.lds b/board/esd/hh405/u-boot.lds
index f5daaefd24..21547ac275 100644
--- a/board/esd/hh405/u-boot.lds
+++ b/board/esd/hh405/u-boot.lds
@@ -38,11 +38,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/esd/hub405/u-boot.lds b/board/esd/hub405/u-boot.lds
index 46e8f3e3bc..f21c7aad4b 100644
--- a/board/esd/hub405/u-boot.lds
+++ b/board/esd/hub405/u-boot.lds
@@ -38,11 +38,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/esd/ocrtc/u-boot.lds b/board/esd/ocrtc/u-boot.lds
index eca720ce0d..5fb9699446 100644
--- a/board/esd/ocrtc/u-boot.lds
+++ b/board/esd/ocrtc/u-boot.lds
@@ -38,11 +38,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/esd/pci405/cmd_pci405.c b/board/esd/pci405/cmd_pci405.c
index 9a0bf1e360..5c717e253d 100644
--- a/board/esd/pci405/cmd_pci405.c
+++ b/board/esd/pci405/cmd_pci405.c
@@ -735,7 +735,7 @@ U_BOOT_CMD(
 );
 
 
-#define SECTOR_SIZE 	32		/* 32 byte cache line */
+#define SECTOR_SIZE	32		/* 32 byte cache line */
 #define SECTOR_MASK	0x1F
 
 void my_flush_dcache(ulong lcl_addr, ulong count)
diff --git a/board/esd/pci405/u-boot.lds b/board/esd/pci405/u-boot.lds
index f5daaefd24..21547ac275 100644
--- a/board/esd/pci405/u-boot.lds
+++ b/board/esd/pci405/u-boot.lds
@@ -38,11 +38,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/esd/pf5200/Makefile b/board/esd/pf5200/Makefile
index a47cd3d73a..2e54315704 100644
--- a/board/esd/pf5200/Makefile
+++ b/board/esd/pf5200/Makefile
@@ -31,8 +31,8 @@ LIB	= $(obj)lib$(BOARD).a
 
 # Objects for Xilinx JTAG programming (CPLD)
 # CPLD  = ../common/xilinx_jtag/lenval.o \
-# 	  ../common/xilinx_jtag/micro.o \
-# 	  ../common/xilinx_jtag/ports.o
+#	  ../common/xilinx_jtag/micro.o \
+#	  ../common/xilinx_jtag/ports.o
 
 # COBJS	= $(BOARD).o flash.o $(CPLD)
 COBJS	= $(BOARD).o flash.o
diff --git a/board/esd/plu405/u-boot.lds b/board/esd/plu405/u-boot.lds
index 196f88c4df..d70d37934e 100644
--- a/board/esd/plu405/u-boot.lds
+++ b/board/esd/plu405/u-boot.lds
@@ -38,11 +38,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/esd/pmc405/u-boot.lds b/board/esd/pmc405/u-boot.lds
index 5b9321e9b3..81ee614f65 100644
--- a/board/esd/pmc405/u-boot.lds
+++ b/board/esd/pmc405/u-boot.lds
@@ -38,11 +38,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/esd/pmc440/u-boot-nand.lds b/board/esd/pmc440/u-boot-nand.lds
index 94dd7543cc..ae2e18de4e 100644
--- a/board/esd/pmc440/u-boot-nand.lds
+++ b/board/esd/pmc440/u-boot-nand.lds
@@ -31,11 +31,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/esd/pmc440/u-boot.lds b/board/esd/pmc440/u-boot.lds
index da2a400b77..b20fb1c0a2 100644
--- a/board/esd/pmc440/u-boot.lds
+++ b/board/esd/pmc440/u-boot.lds
@@ -43,11 +43,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/esd/tasreg/u-boot.lds b/board/esd/tasreg/u-boot.lds
index d21ecd497b..afdb7202ca 100644
--- a/board/esd/tasreg/u-boot.lds
+++ b/board/esd/tasreg/u-boot.lds
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/esd/voh405/u-boot.lds b/board/esd/voh405/u-boot.lds
index 196f88c4df..d70d37934e 100644
--- a/board/esd/voh405/u-boot.lds
+++ b/board/esd/voh405/u-boot.lds
@@ -38,11 +38,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/esd/vom405/u-boot.lds b/board/esd/vom405/u-boot.lds
index f5daaefd24..21547ac275 100644
--- a/board/esd/vom405/u-boot.lds
+++ b/board/esd/vom405/u-boot.lds
@@ -38,11 +38,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/esd/wuh405/u-boot.lds b/board/esd/wuh405/u-boot.lds
index 1c5d8916b5..644174a46d 100644
--- a/board/esd/wuh405/u-boot.lds
+++ b/board/esd/wuh405/u-boot.lds
@@ -38,11 +38,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/esteem192e/flash.c b/board/esteem192e/flash.c
index 5465deaf97..d5eb2019b6 100644
--- a/board/esteem192e/flash.c
+++ b/board/esteem192e/flash.c
@@ -24,7 +24,7 @@
 #include <common.h>
 #include <mpc8xx.h>
 
-flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips        */
 
 #ifdef CONFIG_FLASH_16BIT
 #define FLASH_WORD_SIZE	unsigned short
@@ -38,97 +38,101 @@ flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
  * Functions
  */
 
-ulong flash_get_size (volatile FLASH_WORD_SIZE *addr, flash_info_t *info);
+ulong flash_get_size (volatile FLASH_WORD_SIZE * addr, flash_info_t * info);
+
 #ifndef CONFIG_FLASH_16BIT
-static int write_word (flash_info_t *info, ulong dest, ulong data);
+static int write_word (flash_info_t * info, ulong dest, ulong data);
 #else
-static int write_short (flash_info_t *info, ulong dest, ushort data);
+static int write_short (flash_info_t * info, ulong dest, ushort data);
 #endif
 /*int flash_write (uchar *, ulong, ulong); */
 /*flash_info_t *addr2info (ulong);   */
 
-static void flash_get_offsets (ulong base, flash_info_t *info);
+static void flash_get_offsets (ulong base, flash_info_t * info);
 
 /*-----------------------------------------------------------------------
  */
 unsigned long flash_init (void)
 {
-	volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	unsigned long size_b0, size_b1;
 	int i;
 
 	/* Init: no FLASHes known */
-	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}
 
 	/* Static FLASH Bank configuration here - FIXME XXX */
 
-	size_b0 = flash_get_size((volatile FLASH_WORD_SIZE *)FLASH_BASE0_PRELIM,
-				 &flash_info[0]);
+	size_b0 =
+		flash_get_size ((volatile FLASH_WORD_SIZE *)
+				FLASH_BASE0_PRELIM, &flash_info[0]);
 	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
-		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
-			size_b0, size_b0<<20);
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", size_b0, size_b0 << 20);
 	}
 
-	size_b1 = flash_get_size((volatile FLASH_WORD_SIZE *)FLASH_BASE1_PRELIM,
-				 &flash_info[1]);
+	size_b1 =
+		flash_get_size ((volatile FLASH_WORD_SIZE *)
+				FLASH_BASE1_PRELIM, &flash_info[1]);
 
 	if (size_b1 > size_b0) {
 		printf ("## ERROR: "
 			"Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n",
-			size_b1, size_b1<<20,
-			size_b0, size_b0<<20
-		);
-		flash_info[0].flash_id	= FLASH_UNKNOWN;
-		flash_info[1].flash_id	= FLASH_UNKNOWN;
-		flash_info[0].sector_count	= -1;
-		flash_info[1].sector_count	= -1;
-		flash_info[0].size		= 0;
-		flash_info[1].size		= 0;
+			size_b1, size_b1 << 20, size_b0, size_b0 << 20);
+		flash_info[0].flash_id = FLASH_UNKNOWN;
+		flash_info[1].flash_id = FLASH_UNKNOWN;
+		flash_info[0].sector_count = -1;
+		flash_info[1].sector_count = -1;
+		flash_info[0].size = 0;
+		flash_info[1].size = 0;
 		return (0);
 	}
 
 	/* Remap FLASH according to real size */
 	memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000);
-	memctl->memc_br0 = CFG_FLASH_BASE | 0x00000801; /*  (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;*/
+	memctl->memc_br0 = CFG_FLASH_BASE | 0x00000801;	/*  (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; */
 
 	/* Re-do sizing to get full correct info */
 
-	size_b0 = flash_get_size((volatile FLASH_WORD_SIZE *)CFG_FLASH_BASE,
-				 &flash_info[0]);
+	size_b0 = flash_get_size ((volatile FLASH_WORD_SIZE *) CFG_FLASH_BASE,
+				  &flash_info[0]);
 	flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
 
 #if CFG_MONITOR_BASE >= CFG_FLASH_BASE
 	/* monitor protection ON by default */
-	(void)flash_protect(FLAG_PROTECT_SET,
-			    CFG_MONITOR_BASE,
-			    CFG_MONITOR_BASE+monitor_flash_len-1,
-			    &flash_info[0]);
+	(void) flash_protect (FLAG_PROTECT_SET,
+			      CFG_MONITOR_BASE,
+			      CFG_MONITOR_BASE + monitor_flash_len - 1,
+			      &flash_info[0]);
 #endif
 
 	if (size_b1) {
-		memctl->memc_or1 = CFG_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000);
-		memctl->memc_br1 = (CFG_FLASH_BASE | 0x00000801) + (size_b0 & BR_BA_MSK);
-			      /*((CFG_FLASH_BASE + size_b0) & BR_BA_MSK) |
-				    BR_MS_GPCM | BR_V;*/
+		memctl->memc_or1 =
+			CFG_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000);
+		memctl->memc_br1 =
+			(CFG_FLASH_BASE | 0x00000801) + (size_b0 & BR_BA_MSK);
+		/*((CFG_FLASH_BASE + size_b0) & BR_BA_MSK) |
+		   BR_MS_GPCM | BR_V; */
 
 		/* Re-do sizing to get full correct info */
-		size_b1 = flash_get_size((volatile FLASH_WORD_SIZE *)(CFG_FLASH_BASE + size_b0),
-					  &flash_info[1]);
+		size_b1 =
+			flash_get_size ((volatile FLASH_WORD_SIZE
+					 *) (CFG_FLASH_BASE + size_b0),
+					&flash_info[1]);
 
 		flash_get_offsets (CFG_FLASH_BASE + size_b0, &flash_info[1]);
 
 #if CFG_MONITOR_BASE >= CFG_FLASH_BASE
 		/* monitor protection ON by default */
-		(void)flash_protect(FLAG_PROTECT_SET,
-				    CFG_MONITOR_BASE,
-				    CFG_MONITOR_BASE+monitor_flash_len-1,
-				    &flash_info[1]);
+		(void) flash_protect (FLAG_PROTECT_SET,
+				      CFG_MONITOR_BASE,
+				      CFG_MONITOR_BASE + monitor_flash_len -
+				      1, &flash_info[1]);
 #endif
 	} else {
-		memctl->memc_br1 = 0;		/* invalidate bank */
+		memctl->memc_br1 = 0;	/* invalidate bank */
 
 		flash_info[1].flash_id = FLASH_UNKNOWN;
 		flash_info[1].sector_count = -1;
@@ -142,110 +146,112 @@ unsigned long flash_init (void)
 
 /*-----------------------------------------------------------------------
  */
-static void flash_get_offsets (ulong base, flash_info_t *info)
+static void flash_get_offsets (ulong base, flash_info_t * info)
 {
 	int i;
 
 	/* set up sector start adress table */
 	if (info->flash_id & FLASH_BTYPE) {
-	     if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+		if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
 
 #ifndef CONFIG_FLASH_16BIT
-		/* set sector offsets for bottom boot block type	*/
-		info->start[0] = base + 0x00000000;
-		info->start[1] = base + 0x00004000;
-		info->start[2] = base + 0x00008000;
-		info->start[3] = base + 0x0000C000;
-		info->start[4] = base + 0x00010000;
-		info->start[5] = base + 0x00014000;
-		info->start[6] = base + 0x00018000;
-		info->start[7] = base + 0x0001C000;
-		for (i = 8; i < info->sector_count; i++) {
-			info->start[i] = base + (i * 0x00020000) - 0x000E0000;
-		}
-	       }
-	     else {
-		/* set sector offsets for bottom boot block type	*/
-		info->start[0] = base + 0x00000000;
-		info->start[1] = base + 0x00008000;
-		info->start[2] = base + 0x0000C000;
-		info->start[3] = base + 0x00010000;
-		for (i = 4; i < info->sector_count; i++) {
-			info->start[i] = base + (i * 0x00020000) - 0x00060000;
+			/* set sector offsets for bottom boot block type        */
+			info->start[0] = base + 0x00000000;
+			info->start[1] = base + 0x00004000;
+			info->start[2] = base + 0x00008000;
+			info->start[3] = base + 0x0000C000;
+			info->start[4] = base + 0x00010000;
+			info->start[5] = base + 0x00014000;
+			info->start[6] = base + 0x00018000;
+			info->start[7] = base + 0x0001C000;
+			for (i = 8; i < info->sector_count; i++) {
+				info->start[i] =
+					base + (i * 0x00020000) - 0x000E0000;
+			}
+		} else {
+			/* set sector offsets for bottom boot block type        */
+			info->start[0] = base + 0x00000000;
+			info->start[1] = base + 0x00008000;
+			info->start[2] = base + 0x0000C000;
+			info->start[3] = base + 0x00010000;
+			for (i = 4; i < info->sector_count; i++) {
+				info->start[i] =
+					base + (i * 0x00020000) - 0x00060000;
+			}
 		}
-	       }
 #else
-		/* set sector offsets for bottom boot block type	*/
-		info->start[0] = base + 0x00000000;
-		info->start[1] = base + 0x00002000;
-		info->start[2] = base + 0x00004000;
-		info->start[3] = base + 0x00006000;
-		info->start[4] = base + 0x00008000;
-		info->start[5] = base + 0x0000A000;
-		info->start[6] = base + 0x0000C000;
-		info->start[7] = base + 0x0000E000;
-		for (i = 8; i < info->sector_count; i++) {
-			info->start[i] = base + (i * 0x00010000) - 0x00070000;
-		}
-	       }
-	     else {
-		/* set sector offsets for bottom boot block type	*/
-		info->start[0] = base + 0x00000000;
-		info->start[1] = base + 0x00004000;
-		info->start[2] = base + 0x00006000;
-		info->start[3] = base + 0x00008000;
-		for (i = 4; i < info->sector_count; i++) {
-			info->start[i] = base + (i * 0x00010000) - 0x00030000;
+			/* set sector offsets for bottom boot block type        */
+			info->start[0] = base + 0x00000000;
+			info->start[1] = base + 0x00002000;
+			info->start[2] = base + 0x00004000;
+			info->start[3] = base + 0x00006000;
+			info->start[4] = base + 0x00008000;
+			info->start[5] = base + 0x0000A000;
+			info->start[6] = base + 0x0000C000;
+			info->start[7] = base + 0x0000E000;
+			for (i = 8; i < info->sector_count; i++) {
+				info->start[i] =
+					base + (i * 0x00010000) - 0x00070000;
+			}
+		} else {
+			/* set sector offsets for bottom boot block type        */
+			info->start[0] = base + 0x00000000;
+			info->start[1] = base + 0x00004000;
+			info->start[2] = base + 0x00006000;
+			info->start[3] = base + 0x00008000;
+			for (i = 4; i < info->sector_count; i++) {
+				info->start[i] =
+					base + (i * 0x00010000) - 0x00030000;
+			}
 		}
-	       }
 #endif
 	} else {
-		/* set sector offsets for top boot block type		*/
+		/* set sector offsets for top boot block type           */
 		i = info->sector_count - 1;
-	     if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+		if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
 
 #ifndef CONFIG_FLASH_16BIT
-		info->start[i--] = base + info->size - 0x00004000;
-		info->start[i--] = base + info->size - 0x00008000;
-		info->start[i--] = base + info->size - 0x0000C000;
-		info->start[i--] = base + info->size - 0x00010000;
-		info->start[i--] = base + info->size - 0x00014000;
-		info->start[i--] = base + info->size - 0x00018000;
-		info->start[i--] = base + info->size - 0x0001C000;
-		for (; i >= 0; i--) {
-			info->start[i] = base + i * 0x00020000;
-		}
+			info->start[i--] = base + info->size - 0x00004000;
+			info->start[i--] = base + info->size - 0x00008000;
+			info->start[i--] = base + info->size - 0x0000C000;
+			info->start[i--] = base + info->size - 0x00010000;
+			info->start[i--] = base + info->size - 0x00014000;
+			info->start[i--] = base + info->size - 0x00018000;
+			info->start[i--] = base + info->size - 0x0001C000;
+			for (; i >= 0; i--) {
+				info->start[i] = base + i * 0x00020000;
+			}
 
-	       } else {
+		} else {
 
-		info->start[i--] = base + info->size - 0x00008000;
-		info->start[i--] = base + info->size - 0x0000C000;
-		info->start[i--] = base + info->size - 0x00010000;
-		for (; i >= 0; i--) {
-			info->start[i] = base + i * 0x00020000;
+			info->start[i--] = base + info->size - 0x00008000;
+			info->start[i--] = base + info->size - 0x0000C000;
+			info->start[i--] = base + info->size - 0x00010000;
+			for (; i >= 0; i--) {
+				info->start[i] = base + i * 0x00020000;
+			}
 		}
-	       }
 #else
-		info->start[i--] = base + info->size - 0x00002000;
-		info->start[i--] = base + info->size - 0x00004000;
-		info->start[i--] = base + info->size - 0x00006000;
-		info->start[i--] = base + info->size - 0x00008000;
-		info->start[i--] = base + info->size - 0x0000A000;
-		info->start[i--] = base + info->size - 0x0000C000;
-		info->start[i--] = base + info->size - 0x0000E000;
-		for (; i >= 0; i--) {
-			info->start[i] = base + i * 0x00010000;
-		}
+			info->start[i--] = base + info->size - 0x00002000;
+			info->start[i--] = base + info->size - 0x00004000;
+			info->start[i--] = base + info->size - 0x00006000;
+			info->start[i--] = base + info->size - 0x00008000;
+			info->start[i--] = base + info->size - 0x0000A000;
+			info->start[i--] = base + info->size - 0x0000C000;
+			info->start[i--] = base + info->size - 0x0000E000;
+			for (; i >= 0; i--) {
+				info->start[i] = base + i * 0x00010000;
+			}
 
-	       } else {
+		} else {
 
-		info->start[i--] = base + info->size - 0x00004000;
-		info->start[i--] = base + info->size - 0x00006000;
-		info->start[i--] = base + info->size - 0x00008000;
-		for (; i >= 0; i--) {
-			info->start[i] = base + i * 0x00010000;
+			info->start[i--] = base + info->size - 0x00004000;
+			info->start[i--] = base + info->size - 0x00006000;
+			info->start[i--] = base + info->size - 0x00008000;
+			for (; i >= 0; i--) {
+				info->start[i] = base + i * 0x00010000;
+			}
 		}
-	       }
 #endif
 	}
 
@@ -254,12 +260,12 @@ static void flash_get_offsets (ulong base, flash_info_t *info)
 
 /*-----------------------------------------------------------------------
  */
-void flash_print_info  (flash_info_t *info)
+void flash_print_info (flash_info_t * info)
 {
 	int i;
 	uchar *boottype;
-	uchar botboot[]=", bottom boot sect)\n";
-	uchar topboot[]=", top boot sector)\n";
+	uchar botboot[] = ", bottom boot sect)\n";
+	uchar topboot[] = ", top boot sector)\n";
 
 	if (info->flash_id == FLASH_UNKNOWN) {
 		printf ("missing or unknown FLASH type\n");
@@ -267,73 +273,100 @@ void flash_print_info  (flash_info_t *info)
 	}
 
 	switch (info->flash_id & FLASH_VENDMASK) {
-	case FLASH_MAN_AMD:	printf ("AMD ");		break;
-	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
-	case FLASH_MAN_SST:	printf ("SST ");		break;
-	case FLASH_MAN_STM:	printf ("STM ");		break;
-	case FLASH_MAN_INTEL:	printf ("INTEL ");		break;
-	default:		printf ("Unknown Vendor ");	break;
+	case FLASH_MAN_AMD:
+		printf ("AMD ");
+		break;
+	case FLASH_MAN_FUJ:
+		printf ("FUJITSU ");
+		break;
+	case FLASH_MAN_SST:
+		printf ("SST ");
+		break;
+	case FLASH_MAN_STM:
+		printf ("STM ");
+		break;
+	case FLASH_MAN_INTEL:
+		printf ("INTEL ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
 	}
 
-	if (info->flash_id & 0x0001 ) {
-	boottype = botboot;
+	if (info->flash_id & 0x0001) {
+		boottype = botboot;
 	} else {
-	boottype = topboot;
+		boottype = topboot;
 	}
 
 	switch (info->flash_id & FLASH_TYPEMASK) {
-	case FLASH_AM400B:	printf ("AM29LV400B (4 Mbit%s",boottype);
-				break;
-	case FLASH_AM400T:	printf ("AM29LV400T (4 Mbit%s",boottype);
-				break;
-	case FLASH_AM800B:	printf ("AM29LV800B (8 Mbit%s",boottype);
-				break;
-	case FLASH_AM800T:	printf ("AM29LV800T (8 Mbit%s",boottype);
-				break;
-	case FLASH_AM160B:	printf ("AM29LV160B (16 Mbit%s",boottype);
-				break;
-	case FLASH_AM160T:	printf ("AM29LV160T (16 Mbit%s",boottype);
-				break;
-	case FLASH_AM320B:	printf ("AM29LV320B (32 Mbit%s",boottype);
-				break;
-	case FLASH_AM320T:	printf ("AM29LV320T (32 Mbit%s",boottype);
-				break;
-	case FLASH_INTEL800B:	printf ("INTEL28F800B (8 Mbit%s",boottype);
-				break;
-	case FLASH_INTEL800T:	printf ("INTEL28F800T (8 Mbit%s",boottype);
-				break;
-	case FLASH_INTEL160B:	printf ("INTEL28F160B (16 Mbit%s",boottype);
-				break;
-	case FLASH_INTEL160T:	printf ("INTEL28F160T (16 Mbit%s",boottype);
-				break;
-	case FLASH_INTEL320B:	printf ("INTEL28F320B (32 Mbit%s",boottype);
-				break;
-	case FLASH_INTEL320T:	printf ("INTEL28F320T (32 Mbit%s",boottype);
-				break;
-
-#if 0 /* enable when devices are available */
-
-	case FLASH_INTEL640B:	printf ("INTEL28F640B (64 Mbit%s",boottype);
-				break;
-	case FLASH_INTEL640T:	printf ("INTEL28F640T (64 Mbit%s",boottype);
-				break;
+	case FLASH_AM400B:
+		printf ("AM29LV400B (4 Mbit%s", boottype);
+		break;
+	case FLASH_AM400T:
+		printf ("AM29LV400T (4 Mbit%s", boottype);
+		break;
+	case FLASH_AM800B:
+		printf ("AM29LV800B (8 Mbit%s", boottype);
+		break;
+	case FLASH_AM800T:
+		printf ("AM29LV800T (8 Mbit%s", boottype);
+		break;
+	case FLASH_AM160B:
+		printf ("AM29LV160B (16 Mbit%s", boottype);
+		break;
+	case FLASH_AM160T:
+		printf ("AM29LV160T (16 Mbit%s", boottype);
+		break;
+	case FLASH_AM320B:
+		printf ("AM29LV320B (32 Mbit%s", boottype);
+		break;
+	case FLASH_AM320T:
+		printf ("AM29LV320T (32 Mbit%s", boottype);
+		break;
+	case FLASH_INTEL800B:
+		printf ("INTEL28F800B (8 Mbit%s", boottype);
+		break;
+	case FLASH_INTEL800T:
+		printf ("INTEL28F800T (8 Mbit%s", boottype);
+		break;
+	case FLASH_INTEL160B:
+		printf ("INTEL28F160B (16 Mbit%s", boottype);
+		break;
+	case FLASH_INTEL160T:
+		printf ("INTEL28F160T (16 Mbit%s", boottype);
+		break;
+	case FLASH_INTEL320B:
+		printf ("INTEL28F320B (32 Mbit%s", boottype);
+		break;
+	case FLASH_INTEL320T:
+		printf ("INTEL28F320T (32 Mbit%s", boottype);
+		break;
+
+#if 0				/* enable when devices are available */
+
+	case FLASH_INTEL640B:
+		printf ("INTEL28F640B (64 Mbit%s", boottype);
+		break;
+	case FLASH_INTEL640T:
+		printf ("INTEL28F640T (64 Mbit%s", boottype);
+		break;
 #endif
 
-	default:		printf ("Unknown Chip Type\n");
-				break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
 	}
 
 	printf ("  Size: %ld MB in %d Sectors\n",
 		info->size >> 20, info->sector_count);
 
 	printf ("  Sector Start Addresses:");
-	for (i=0; i<info->sector_count; ++i) {
+	for (i = 0; i < info->sector_count; ++i) {
 		if ((i % 5) == 0)
 			printf ("\n   ");
 		printf (" %08lX%s",
-			info->start[i],
-			info->protect[i] ? " (RO)" : "     "
-		);
+			info->start[i], info->protect[i] ? " (RO)" : "     ");
 	}
 	printf ("\n");
 	return;
@@ -349,10 +382,10 @@ void flash_print_info  (flash_info_t *info)
 /*
  * The following code cannot be run from FLASH!
  */
-ulong flash_get_size (volatile FLASH_WORD_SIZE *addr, flash_info_t *info)
+ulong flash_get_size (volatile FLASH_WORD_SIZE * addr, flash_info_t * info)
 {
 	short i;
-	ulong base = (ulong)addr;
+	ulong base = (ulong) addr;
 	FLASH_WORD_SIZE value;
 
 	/* Write auto select command: read Manufacturer ID */
@@ -367,7 +400,7 @@ ulong flash_get_size (volatile FLASH_WORD_SIZE *addr, flash_info_t *info)
 	 */
 
 	addr[0x0000] = 0x00900090;
-	if(addr[0x0000] != 0x00890089){
+	if (addr[0x0000] != 0x00890089) {
 		addr[0x0555] = 0x00AA00AA;
 		addr[0x02AA] = 0x00550055;
 		addr[0x0555] = 0x00900090;
@@ -381,7 +414,7 @@ ulong flash_get_size (volatile FLASH_WORD_SIZE *addr, flash_info_t *info)
 
 	addr[0x0000] = 0x0090;
 
-	if(addr[0x0000] != 0x0089){
+	if (addr[0x0000] != 0x0089) {
 		addr[0x0555] = 0x00AA;
 		addr[0x02AA] = 0x0055;
 		addr[0x0555] = 0x0090;
@@ -409,11 +442,11 @@ ulong flash_get_size (volatile FLASH_WORD_SIZE *addr, flash_info_t *info)
 		info->flash_id = FLASH_UNKNOWN;
 		info->sector_count = 0;
 		info->size = 0;
-		return (0);			/* no or unknown flash	*/
+		return (0);	/* no or unknown flash  */
 
 	}
 
-	value = addr[1];			/* device ID		*/
+	value = addr[1];	/* device ID            */
 
 	switch (value) {
 
@@ -421,206 +454,208 @@ ulong flash_get_size (volatile FLASH_WORD_SIZE *addr, flash_info_t *info)
 		info->flash_id += FLASH_AM400T;
 		info->sector_count = 11;
 		info->size = 0x00100000;
-		break;				/* => 1 MB		*/
+		break;		/* => 1 MB              */
 
 	case (AMD_ID_LV400B & FLASH_ID_MASK):
 		info->flash_id += FLASH_AM400B;
 		info->sector_count = 11;
 		info->size = 0x00100000;
-		break;				/* => 1 MB		*/
+		break;		/* => 1 MB              */
 
 	case (AMD_ID_LV800T & FLASH_ID_MASK):
 		info->flash_id += FLASH_AM800T;
 		info->sector_count = 19;
 		info->size = 0x00200000;
-		break;				/* => 2 MB		*/
+		break;		/* => 2 MB              */
 
 	case (AMD_ID_LV800B & FLASH_ID_MASK):
 		info->flash_id += FLASH_AM800B;
 		info->sector_count = 19;
 		info->size = 0x00200000;
-		break;				/* => 2 MB		*/
+		break;		/* => 2 MB              */
 
 	case (AMD_ID_LV160T & FLASH_ID_MASK):
 		info->flash_id += FLASH_AM160T;
 		info->sector_count = 35;
 		info->size = 0x00400000;
-		break;				/* => 4 MB		*/
+		break;		/* => 4 MB              */
 
 	case (AMD_ID_LV160B & FLASH_ID_MASK):
 		info->flash_id += FLASH_AM160B;
 		info->sector_count = 35;
 		info->size = 0x00400000;
-		break;				/* => 4 MB		*/
-#if 0	/* enable when device IDs are available */
+		break;		/* => 4 MB              */
+#if 0				/* enable when device IDs are available */
 	case (AMD_ID_LV320T & FLASH_ID_MASK):
 		info->flash_id += FLASH_AM320T;
 		info->sector_count = 67;
 		info->size = 0x00800000;
-		break;				/* => 8 MB		*/
+		break;		/* => 8 MB              */
 
 	case (AMD_ID_LV320B & FLASH_ID_MASK):
 		info->flash_id += FLASH_AM320B;
 		info->sector_count = 67;
 		info->size = 0x00800000;
-		break;				/* => 8 MB		*/
+		break;		/* => 8 MB              */
 #endif
 
 	case (INTEL_ID_28F800B3T & FLASH_ID_MASK):
 		info->flash_id += FLASH_INTEL800T;
 		info->sector_count = 23;
 		info->size = 0x00200000;
-		break;				/* => 2 MB		*/
+		break;		/* => 2 MB              */
 
 	case (INTEL_ID_28F800B3B & FLASH_ID_MASK):
 		info->flash_id += FLASH_INTEL800B;
 		info->sector_count = 23;
 		info->size = 0x00200000;
-		break;				/* => 2 MB		*/
+		break;		/* => 2 MB              */
 
 	case (INTEL_ID_28F160B3T & FLASH_ID_MASK):
 		info->flash_id += FLASH_INTEL160T;
 		info->sector_count = 39;
 		info->size = 0x00400000;
-		break;				/* => 4 MB		*/
+		break;		/* => 4 MB              */
 
 	case (INTEL_ID_28F160B3B & FLASH_ID_MASK):
 		info->flash_id += FLASH_INTEL160B;
 		info->sector_count = 39;
 		info->size = 0x00400000;
-		break;				/* => 4 MB		*/
+		break;		/* => 4 MB              */
 
 	case (INTEL_ID_28F320B3T & FLASH_ID_MASK):
 		info->flash_id += FLASH_INTEL320T;
 		info->sector_count = 71;
 		info->size = 0x00800000;
-		break;				/* => 8 MB		*/
+		break;		/* => 8 MB              */
 
 	case (INTEL_ID_28F320B3B & FLASH_ID_MASK):
 		info->flash_id += FLASH_AM320B;
 		info->sector_count = 71;
 		info->size = 0x00800000;
-		break;				/* => 8 MB		*/
+		break;		/* => 8 MB              */
 
-#if 0 /* enable when devices are available */
+#if 0				/* enable when devices are available */
 	case (INTEL_ID_28F320B3T & FLASH_ID_MASK):
 		info->flash_id += FLASH_INTEL320T;
 		info->sector_count = 135;
 		info->size = 0x01000000;
-		break;				/* => 16 MB		*/
+		break;		/* => 16 MB             */
 
 	case (INTEL_ID_28F320B3B & FLASH_ID_MASK):
 		info->flash_id += FLASH_AM320B;
 		info->sector_count = 135;
 		info->size = 0x01000000;
-		break;				/* => 16 MB		*/
+		break;		/* => 16 MB             */
 #endif
 	default:
 		info->flash_id = FLASH_UNKNOWN;
-		return (0);			/* => no or unknown flash */
+		return (0);	/* => no or unknown flash */
 
 	}
 
 	/* set up sector start adress table */
 	if (info->flash_id & FLASH_BTYPE) {
-	     if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+		if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
 
 #ifndef CONFIG_FLASH_16BIT
-		/* set sector offsets for bottom boot block type	*/
-		info->start[0] = base + 0x00000000;
-		info->start[1] = base + 0x00004000;
-		info->start[2] = base + 0x00008000;
-		info->start[3] = base + 0x0000C000;
-		info->start[4] = base + 0x00010000;
-		info->start[5] = base + 0x00014000;
-		info->start[6] = base + 0x00018000;
-		info->start[7] = base + 0x0001C000;
-		for (i = 8; i < info->sector_count; i++) {
-			info->start[i] = base + (i * 0x00020000) - 0x000E0000;
-		}
-	       }
-	     else {
-		/* set sector offsets for bottom boot block type	*/
-		info->start[0] = base + 0x00000000;
-		info->start[1] = base + 0x00008000;
-		info->start[2] = base + 0x0000C000;
-		info->start[3] = base + 0x00010000;
-		for (i = 4; i < info->sector_count; i++) {
-			info->start[i] = base + (i * 0x00020000) - 0x00060000;
+			/* set sector offsets for bottom boot block type        */
+			info->start[0] = base + 0x00000000;
+			info->start[1] = base + 0x00004000;
+			info->start[2] = base + 0x00008000;
+			info->start[3] = base + 0x0000C000;
+			info->start[4] = base + 0x00010000;
+			info->start[5] = base + 0x00014000;
+			info->start[6] = base + 0x00018000;
+			info->start[7] = base + 0x0001C000;
+			for (i = 8; i < info->sector_count; i++) {
+				info->start[i] =
+					base + (i * 0x00020000) - 0x000E0000;
+			}
+		} else {
+			/* set sector offsets for bottom boot block type        */
+			info->start[0] = base + 0x00000000;
+			info->start[1] = base + 0x00008000;
+			info->start[2] = base + 0x0000C000;
+			info->start[3] = base + 0x00010000;
+			for (i = 4; i < info->sector_count; i++) {
+				info->start[i] =
+					base + (i * 0x00020000) - 0x00060000;
+			}
 		}
-	       }
 #else
-		/* set sector offsets for bottom boot block type	*/
-		info->start[0] = base + 0x00000000;
-		info->start[1] = base + 0x00002000;
-		info->start[2] = base + 0x00004000;
-		info->start[3] = base + 0x00006000;
-		info->start[4] = base + 0x00008000;
-		info->start[5] = base + 0x0000A000;
-		info->start[6] = base + 0x0000C000;
-		info->start[7] = base + 0x0000E000;
-		for (i = 8; i < info->sector_count; i++) {
-			info->start[i] = base + (i * 0x00010000) - 0x00070000;
-		}
-	       }
-	     else {
-		/* set sector offsets for bottom boot block type	*/
-		info->start[0] = base + 0x00000000;
-		info->start[1] = base + 0x00004000;
-		info->start[2] = base + 0x00006000;
-		info->start[3] = base + 0x00008000;
-		for (i = 4; i < info->sector_count; i++) {
-			info->start[i] = base + (i * 0x00010000) - 0x00030000;
+			/* set sector offsets for bottom boot block type        */
+			info->start[0] = base + 0x00000000;
+			info->start[1] = base + 0x00002000;
+			info->start[2] = base + 0x00004000;
+			info->start[3] = base + 0x00006000;
+			info->start[4] = base + 0x00008000;
+			info->start[5] = base + 0x0000A000;
+			info->start[6] = base + 0x0000C000;
+			info->start[7] = base + 0x0000E000;
+			for (i = 8; i < info->sector_count; i++) {
+				info->start[i] =
+					base + (i * 0x00010000) - 0x00070000;
+			}
+		} else {
+			/* set sector offsets for bottom boot block type        */
+			info->start[0] = base + 0x00000000;
+			info->start[1] = base + 0x00004000;
+			info->start[2] = base + 0x00006000;
+			info->start[3] = base + 0x00008000;
+			for (i = 4; i < info->sector_count; i++) {
+				info->start[i] =
+					base + (i * 0x00010000) - 0x00030000;
+			}
 		}
-	       }
 #endif
 	} else {
-		/* set sector offsets for top boot block type		*/
+		/* set sector offsets for top boot block type           */
 		i = info->sector_count - 1;
-	     if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+		if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
 
 #ifndef CONFIG_FLASH_16BIT
-		info->start[i--] = base + info->size - 0x00004000;
-		info->start[i--] = base + info->size - 0x00008000;
-		info->start[i--] = base + info->size - 0x0000C000;
-		info->start[i--] = base + info->size - 0x00010000;
-		info->start[i--] = base + info->size - 0x00014000;
-		info->start[i--] = base + info->size - 0x00018000;
-		info->start[i--] = base + info->size - 0x0001C000;
-		for (; i >= 0; i--) {
-			info->start[i] = base + i * 0x00020000;
-		}
+			info->start[i--] = base + info->size - 0x00004000;
+			info->start[i--] = base + info->size - 0x00008000;
+			info->start[i--] = base + info->size - 0x0000C000;
+			info->start[i--] = base + info->size - 0x00010000;
+			info->start[i--] = base + info->size - 0x00014000;
+			info->start[i--] = base + info->size - 0x00018000;
+			info->start[i--] = base + info->size - 0x0001C000;
+			for (; i >= 0; i--) {
+				info->start[i] = base + i * 0x00020000;
+			}
 
-	       } else {
+		} else {
 
-		info->start[i--] = base + info->size - 0x00008000;
-		info->start[i--] = base + info->size - 0x0000C000;
-		info->start[i--] = base + info->size - 0x00010000;
-		for (; i >= 0; i--) {
-			info->start[i] = base + i * 0x00020000;
+			info->start[i--] = base + info->size - 0x00008000;
+			info->start[i--] = base + info->size - 0x0000C000;
+			info->start[i--] = base + info->size - 0x00010000;
+			for (; i >= 0; i--) {
+				info->start[i] = base + i * 0x00020000;
+			}
 		}
-	       }
 #else
-		info->start[i--] = base + info->size - 0x00002000;
-		info->start[i--] = base + info->size - 0x00004000;
-		info->start[i--] = base + info->size - 0x00006000;
-		info->start[i--] = base + info->size - 0x00008000;
-		info->start[i--] = base + info->size - 0x0000A000;
-		info->start[i--] = base + info->size - 0x0000C000;
-		info->start[i--] = base + info->size - 0x0000E000;
-		for (; i >= 0; i--) {
-			info->start[i] = base + i * 0x00010000;
-		}
+			info->start[i--] = base + info->size - 0x00002000;
+			info->start[i--] = base + info->size - 0x00004000;
+			info->start[i--] = base + info->size - 0x00006000;
+			info->start[i--] = base + info->size - 0x00008000;
+			info->start[i--] = base + info->size - 0x0000A000;
+			info->start[i--] = base + info->size - 0x0000C000;
+			info->start[i--] = base + info->size - 0x0000E000;
+			for (; i >= 0; i--) {
+				info->start[i] = base + i * 0x00010000;
+			}
 
-	       } else {
+		} else {
 
-		info->start[i--] = base + info->size - 0x00004000;
-		info->start[i--] = base + info->size - 0x00006000;
-		info->start[i--] = base + info->size - 0x00008000;
-		for (; i >= 0; i--) {
-			info->start[i] = base + i * 0x00010000;
+			info->start[i--] = base + info->size - 0x00004000;
+			info->start[i--] = base + info->size - 0x00006000;
+			info->start[i--] = base + info->size - 0x00008000;
+			for (; i >= 0; i--) {
+				info->start[i] = base + i * 0x00010000;
+			}
 		}
-	       }
 #endif
 	}
 
@@ -628,7 +663,7 @@ ulong flash_get_size (volatile FLASH_WORD_SIZE *addr, flash_info_t *info)
 	for (i = 0; i < info->sector_count; i++) {
 		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
 		/* D0 = 1 if protected */
-		addr = (volatile FLASH_WORD_SIZE *)(info->start[i]);
+		addr = (volatile FLASH_WORD_SIZE *) (info->start[i]);
 		info->protect[i] = addr[2] & 1;
 	}
 
@@ -636,11 +671,11 @@ ulong flash_get_size (volatile FLASH_WORD_SIZE *addr, flash_info_t *info)
 	 * Prevent writes to uninitialized FLASH.
 	 */
 	if (info->flash_id != FLASH_UNKNOWN) {
-		addr = (volatile FLASH_WORD_SIZE *)info->start[0];
-		if( (info->flash_id & 0xFF00) == FLASH_MAN_INTEL){
-		   *addr = (0x00F000F0 & FLASH_ID_MASK);	/* reset bank */
+		addr = (volatile FLASH_WORD_SIZE *) info->start[0];
+		if ((info->flash_id & 0xFF00) == FLASH_MAN_INTEL) {
+			*addr = (0x00F000F0 & FLASH_ID_MASK);	/* reset bank */
 		} else {
-		   *addr = (0x00FF00FF & FLASH_ID_MASK);	/* reset bank */
+			*addr = (0x00FF00FF & FLASH_ID_MASK);	/* reset bank */
 		}
 	}
 
@@ -651,10 +686,11 @@ ulong flash_get_size (volatile FLASH_WORD_SIZE *addr, flash_info_t *info)
 /*-----------------------------------------------------------------------
  */
 
-int	flash_erase (flash_info_t *info, int s_first, int s_last)
+int flash_erase (flash_info_t * info, int s_first, int s_last)
 {
 
-	volatile FLASH_WORD_SIZE *addr=(volatile FLASH_WORD_SIZE*)(info->start[0]);
+	volatile FLASH_WORD_SIZE *addr =
+		(volatile FLASH_WORD_SIZE *) (info->start[0]);
 	int flag, prot, sect, l_sect, barf;
 	ulong start, now, last;
 	int rcode = 0;
@@ -670,21 +706,20 @@ int	flash_erase (flash_info_t *info, int s_first, int s_last)
 
 	if ((info->flash_id == FLASH_UNKNOWN) ||
 	    ((info->flash_id > FLASH_AMD_COMP) &&
-	     ( (info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL ) ) ){
+	     ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL))) {
 		printf ("Can't erase unknown flash type - aborted\n");
 		return 1;
 	}
 
 	prot = 0;
-	for (sect=s_first; sect<=s_last; ++sect) {
+	for (sect = s_first; sect <= s_last; ++sect) {
 		if (info->protect[sect]) {
 			prot++;
 		}
 	}
 
 	if (prot) {
-		printf ("- Warning: %d protected sectors will not be erased!\n",
-			prot);
+		printf ("- Warning: %d protected sectors will not be erased!\n", prot);
 	} else {
 		printf ("\n");
 	}
@@ -692,109 +727,111 @@ int	flash_erase (flash_info_t *info, int s_first, int s_last)
 	l_sect = -1;
 
 	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts();
-    if(info->flash_id < FLASH_AMD_COMP) {
+	flag = disable_interrupts ();
+	if (info->flash_id < FLASH_AMD_COMP) {
 #ifndef CONFIG_FLASH_16BIT
-	addr[0x0555] = 0x00AA00AA;
-	addr[0x02AA] = 0x00550055;
-	addr[0x0555] = 0x00800080;
-	addr[0x0555] = 0x00AA00AA;
-	addr[0x02AA] = 0x00550055;
+		addr[0x0555] = 0x00AA00AA;
+		addr[0x02AA] = 0x00550055;
+		addr[0x0555] = 0x00800080;
+		addr[0x0555] = 0x00AA00AA;
+		addr[0x02AA] = 0x00550055;
 #else
-	addr[0x0555] = 0x00AA;
-	addr[0x02AA] = 0x0055;
-	addr[0x0555] = 0x0080;
-	addr[0x0555] = 0x00AA;
-	addr[0x02AA] = 0x0055;
+		addr[0x0555] = 0x00AA;
+		addr[0x02AA] = 0x0055;
+		addr[0x0555] = 0x0080;
+		addr[0x0555] = 0x00AA;
+		addr[0x02AA] = 0x0055;
 #endif
-	/* Start erase on unprotected sectors */
-	for (sect = s_first; sect<=s_last; sect++) {
-		if (info->protect[sect] == 0) {	/* not protected */
-			addr = (volatile FLASH_WORD_SIZE *)(info->start[sect]);
-			addr[0] = (0x00300030 & FLASH_ID_MASK);
-			l_sect = sect;
+		/* Start erase on unprotected sectors */
+		for (sect = s_first; sect <= s_last; sect++) {
+			if (info->protect[sect] == 0) {	/* not protected */
+				addr = (volatile FLASH_WORD_SIZE *) (info->start[sect]);
+				addr[0] = (0x00300030 & FLASH_ID_MASK);
+				l_sect = sect;
+			}
 		}
-	}
-
-	/* re-enable interrupts if necessary */
-	if (flag)
-		enable_interrupts();
-
-	/* wait at least 80us - let's wait 1 ms */
-	udelay (1000);
-
-	/*
-	 * We wait for the last triggered sector
-	 */
-	if (l_sect < 0)
-		goto DONE;
 
-	start = get_timer (0);
-	last  = start;
-	addr = (volatile FLASH_WORD_SIZE*)(info->start[l_sect]);
-	while ((addr[0] & (0x00800080&FLASH_ID_MASK)) !=
-			  (0x00800080&FLASH_ID_MASK)  )
-	{
-		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
-			printf ("Timeout\n");
-			return 1;
-		}
-		/* show that we're waiting */
-		if ((now - last) > 1000) {	/* every second */
-			serial_putc ('.');
-			last = now;
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts ();
+
+		/* wait at least 80us - let's wait 1 ms */
+		udelay (1000);
+
+		/*
+		 * We wait for the last triggered sector
+		 */
+		if (l_sect < 0)
+			goto DONE;
+
+		start = get_timer (0);
+		last = start;
+		addr = (volatile FLASH_WORD_SIZE *) (info->start[l_sect]);
+		while ((addr[0] & (0x00800080 & FLASH_ID_MASK)) !=
+		       (0x00800080 & FLASH_ID_MASK)) {
+			if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) {
+				printf ("Timeout\n");
+				return 1;
+			}
+			/* show that we're waiting */
+			if ((now - last) > 1000) {	/* every second */
+				serial_putc ('.');
+				last = now;
+			}
 		}
-	}
 
-DONE:
-	/* reset to read mode */
-	addr = (volatile FLASH_WORD_SIZE *)info->start[0];
-	addr[0] = (0x00F000F0 & FLASH_ID_MASK);	/* reset bank */
-    } else {
+	      DONE:
+		/* reset to read mode */
+		addr = (volatile FLASH_WORD_SIZE *) info->start[0];
+		addr[0] = (0x00F000F0 & FLASH_ID_MASK);	/* reset bank */
+	} else {
 
 
-	for (sect = s_first; sect<=s_last; sect++) {
-		if (info->protect[sect] == 0) {	/* not protected */
-			barf = 0;
+		for (sect = s_first; sect <= s_last; sect++) {
+			if (info->protect[sect] == 0) {	/* not protected */
+				barf = 0;
 #ifndef CONFIG_FLASH_16BIT
-			addr = (vu_long*)(info->start[sect]);
-			addr[0] = 0x00200020;
-			addr[0] = 0x00D000D0;
-			while(!(addr[0] & 0x00800080));	/* wait for error or finish */
-			if( addr[0] & 0x003A003A) {	/* check for error */
-				barf = addr[0] & 0x003A0000;
-				if( barf ) {
-					barf >>=16;
-				} else {
-					barf = addr[0] & 0x0000003A;
+				addr = (vu_long *) (info->start[sect]);
+				addr[0] = 0x00200020;
+				addr[0] = 0x00D000D0;
+				while (!(addr[0] & 0x00800080));	/* wait for error or finish */
+				if (addr[0] & 0x003A003A) {	/* check for error */
+					barf = addr[0] & 0x003A0000;
+					if (barf) {
+						barf >>= 16;
+					} else {
+						barf = addr[0] & 0x0000003A;
+					}
 				}
-			}
 #else
-			addr = (vu_short*)(info->start[sect]);
-			addr[0] = 0x0020;
-			addr[0] = 0x00D0;
-			while(!(addr[0] & 0x0080));	/* wait for error or finish */
-			if( addr[0] & 0x003A)	/* check for error */
-				barf = addr[0] & 0x003A;
+				addr = (vu_short *) (info->start[sect]);
+				addr[0] = 0x0020;
+				addr[0] = 0x00D0;
+				while (!(addr[0] & 0x0080));	/* wait for error or finish */
+				if (addr[0] & 0x003A)	/* check for error */
+					barf = addr[0] & 0x003A;
 #endif
-			if(barf) {
-				printf("\nFlash error in sector at %lx\n",(unsigned long)addr);
-				if(barf & 0x0002) printf("Block locked, not erased.\n");
-				if((barf & 0x0030) == 0x0030)
-					printf("Command Sequence error.\n");
-				if((barf & 0x0030) == 0x0020)
-					printf("Block Erase error.\n");
-				if(barf & 0x0008) printf("Vpp Low error.\n");
-				rcode = 1;
-			} else printf(".");
-			l_sect = sect;
+				if (barf) {
+					printf ("\nFlash error in sector at %lx\n", (unsigned long) addr);
+					if (barf & 0x0002)
+						printf ("Block locked, not erased.\n");
+					if ((barf & 0x0030) == 0x0030)
+						printf ("Command Sequence error.\n");
+					if ((barf & 0x0030) == 0x0020)
+						printf ("Block Erase error.\n");
+					if (barf & 0x0008)
+						printf ("Vpp Low error.\n");
+					rcode = 1;
+				} else
+					printf (".");
+				l_sect = sect;
+			}
+			addr = (volatile FLASH_WORD_SIZE *) info->start[0];
+			addr[0] = (0x00FF00FF & FLASH_ID_MASK);	/* reset bank */
+
 		}
-	addr = (volatile FLASH_WORD_SIZE *)info->start[0];
-	addr[0] = (0x00FF00FF & FLASH_ID_MASK);	/* reset bank */
 
 	}
-
-    }
 	printf (" done\n");
 	return rcode;
 }
@@ -809,7 +846,7 @@ DONE:
  * 2 - Flash not erased
  */
 
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
 {
 #ifndef CONFIG_FLASH_16BIT
 	ulong cp, wp, data;
@@ -830,19 +867,19 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
 	 */
 	if ((l = addr - wp) != 0) {
 		data = 0;
-		for (i=0, cp=wp; i<l; ++i, ++cp) {
-			data = (data << 8) | (*(uchar *)cp);
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
 		}
-		for (; i<4 && cnt>0; ++i) {
+		for (; i < 4 && cnt > 0; ++i) {
 			data = (data << 8) | *src++;
 			--cnt;
 			++cp;
 		}
-		for (; cnt==0 && i<4; ++i, ++cp) {
-			data = (data << 8) | (*(uchar *)cp);
+		for (; cnt == 0 && i < 4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
 		}
 
-		if ((rc = write_word(info, wp, data)) != 0) {
+		if ((rc = write_word (info, wp, data)) != 0) {
 			return (rc);
 		}
 		wp += 4;
@@ -853,13 +890,13 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
 	 */
 	while (cnt >= 4) {
 		data = 0;
-		for (i=0; i<4; ++i) {
+		for (i = 0; i < 4; ++i) {
 			data = (data << 8) | *src++;
 		}
-		if ((rc = write_word(info, wp, data)) != 0) {
+		if ((rc = write_word (info, wp, data)) != 0) {
 			return (rc);
 		}
-		wp  += 4;
+		wp += 4;
 		cnt -= 4;
 	}
 
@@ -871,15 +908,15 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
 	 * handle unaligned tail bytes
 	 */
 	data = 0;
-	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+	for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
 		data = (data << 8) | *src++;
 		--cnt;
 	}
-	for (; i<4; ++i, ++cp) {
-		data = (data << 8) | (*(uchar *)cp);
+	for (; i < 4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
 	}
 
-	return (write_word(info, wp, data));
+	return (write_word (info, wp, data));
 
 #else
 	wp = (addr & ~1);	/* get lower word aligned address */
@@ -891,7 +928,7 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
 		data = 0;
 		data = (data << 8) | *src++;
 		--cnt;
-		if ((rc = write_short(info, wp, data)) != 0) {
+		if ((rc = write_short (info, wp, data)) != 0) {
 			return (rc);
 		}
 		wp += 2;
@@ -903,7 +940,7 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
 /*	l = 0; used for debuging  */
 	while (cnt >= 2) {
 		data = 0;
-		for (i=0; i<2; ++i) {
+		for (i = 0; i < 2; ++i) {
 			data = (data << 8) | *src++;
 		}
 
@@ -912,10 +949,10 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
 			l = 1;
 		}  used for debuging */
 
-		if ((rc = write_short(info, wp, data)) != 0) {
+		if ((rc = write_short (info, wp, data)) != 0) {
 			return (rc);
 		}
-		wp  += 2;
+		wp += 2;
 		cnt -= 2;
 	}
 
@@ -927,15 +964,15 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
 	 * handle unaligned tail bytes
 	 */
 	data = 0;
-	for (i=0, cp=wp; i<2 && cnt>0; ++i, ++cp) {
+	for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) {
 		data = (data << 8) | *src++;
 		--cnt;
 	}
-	for (; i<2; ++i, ++cp) {
-		data = (data << 8) | (*(uchar *)cp);
+	for (; i < 2; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
 	}
 
-	return (write_short(info, wp, data));
+	return (write_short (info, wp, data));
 
 
 #endif
@@ -948,148 +985,151 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
  * 2 - Flash not erased
  */
 #ifndef CONFIG_FLASH_16BIT
-static int write_word (flash_info_t *info, ulong dest, ulong data)
+static int write_word (flash_info_t * info, ulong dest, ulong data)
 {
-	vu_long *addr = (vu_long*)(info->start[0]);
-	ulong start,barf;
+	vu_long *addr = (vu_long *) (info->start[0]);
+	ulong start, barf;
 	int flag;
 
 
 	/* Check if Flash is (sufficiently) erased */
-	if ((*((vu_long *)dest) & data) != data) {
+	if ((*((vu_long *) dest) & data) != data) {
 		return (2);
 	}
 
 	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts();
-
-     if(info->flash_id > FLASH_AMD_COMP) {
-	/* AMD stuff */
-	addr[0x0555] = 0x00AA00AA;
-	addr[0x02AA] = 0x00550055;
-	addr[0x0555] = 0x00A000A0;
-     } else {
-	/* intel stuff */
-	*addr = 0x00400040;
-     }
-	*((vu_long *)dest) = data;
+	flag = disable_interrupts ();
+
+	if (info->flash_id > FLASH_AMD_COMP) {
+		/* AMD stuff */
+		addr[0x0555] = 0x00AA00AA;
+		addr[0x02AA] = 0x00550055;
+		addr[0x0555] = 0x00A000A0;
+	} else {
+		/* intel stuff */
+		*addr = 0x00400040;
+	}
+	*((vu_long *) dest) = data;
 
 	/* re-enable interrupts if necessary */
 	if (flag)
-		enable_interrupts();
+		enable_interrupts ();
 
 	/* data polling for D7 */
 	start = get_timer (0);
 
-     if(info->flash_id > FLASH_AMD_COMP) {
+	if (info->flash_id > FLASH_AMD_COMP) {
 
-	while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) {
-		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
-			return (1);
+		while ((*((vu_long *) dest) & 0x00800080) !=
+		       (data & 0x00800080)) {
+			if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+				return (1);
+			}
 		}
-	}
 
-     } else {
+	} else {
 
-	while(!(addr[0] & 0x00800080)){  	/* wait for error or finish */
-		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
-			return (1);
-	}
+		while (!(addr[0] & 0x00800080)) {	/* wait for error or finish */
+			if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+				return (1);
+			}
 
-	if( addr[0] & 0x003A003A) {	/* check for error */
-		barf = addr[0] & 0x003A0000;
-		if( barf ) {
-			barf >>=16;
-		} else {
-			barf = addr[0] & 0x0000003A;
-		}
-		printf("\nFlash write error at address %lx\n",(unsigned long)dest);
-		if(barf & 0x0002) printf("Block locked, not erased.\n");
-		if(barf & 0x0010) printf("Programming error.\n");
-		if(barf & 0x0008) printf("Vpp Low error.\n");
-		return(2);
-	}
+			if (addr[0] & 0x003A003A) {	/* check for error */
+				barf = addr[0] & 0x003A0000;
+				if (barf) {
+					barf >>= 16;
+				} else {
+					barf = addr[0] & 0x0000003A;
+				}
+				printf ("\nFlash write error at address %lx\n", (unsigned long) dest);
+				if (barf & 0x0002)
+					printf ("Block locked, not erased.\n");
+				if (barf & 0x0010)
+					printf ("Programming error.\n");
+				if (barf & 0x0008)
+					printf ("Vpp Low error.\n");
+				return (2);
+			}
 
 
-     }
+		}
 
-	return (0);
+		return (0);
 
-}
+	}
 
 #else
 
-static int write_short (flash_info_t *info, ulong dest, ushort data)
+static int write_short (flash_info_t * info, ulong dest, ushort data)
 {
-	vu_short *addr = (vu_short*)(info->start[0]);
-	ulong start,barf;
+	vu_short *addr = (vu_short *) (info->start[0]);
+	ulong start, barf;
 	int flag;
 
 	/* Check if Flash is (sufficiently) erased */
-	if ((*((vu_short *)dest) & data) != data) {
+	if ((*((vu_short *) dest) & data) != data) {
 		return (2);
 	}
 
 	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts();
-
-     if(info->flash_id < FLASH_AMD_COMP) {
-	/* AMD stuff */
-	addr[0x0555] = 0x00AA;
-	addr[0x02AA] = 0x0055;
-	addr[0x0555] = 0x00A0;
-     } else {
-	/* intel stuff */
-	*addr = 0x00D0;
-	*addr = 0x0040;
-     }
-	*((vu_short *)dest) = data;
+	flag = disable_interrupts ();
+
+	if (info->flash_id < FLASH_AMD_COMP) {
+		/* AMD stuff */
+		addr[0x0555] = 0x00AA;
+		addr[0x02AA] = 0x0055;
+		addr[0x0555] = 0x00A0;
+	} else {
+		/* intel stuff */
+		*addr = 0x00D0;
+		*addr = 0x0040;
+	}
+	*((vu_short *) dest) = data;
 
 	/* re-enable interrupts if necessary */
 	if (flag)
-		enable_interrupts();
+		enable_interrupts ();
 
 	/* data polling for D7 */
 	start = get_timer (0);
 
-     if(info->flash_id < FLASH_AMD_COMP) {
-	  /* AMD stuff */
-	while ((*((vu_short *)dest) & 0x0080) != (data & 0x0080)) {
-		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
-			return (1);
+	if (info->flash_id < FLASH_AMD_COMP) {
+		/* AMD stuff */
+		while ((*((vu_short *) dest) & 0x0080) != (data & 0x0080)) {
+			if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+				return (1);
+			}
 		}
-	}
 
-     } else {
-	/* intel stuff */
-	while(!(addr[0] & 0x0080)){  	/* wait for error or finish */
-		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) return (1);
-	}
+	} else {
+		/* intel stuff */
+		while (!(addr[0] & 0x0080)) {	/* wait for error or finish */
+			if (get_timer (start) > CFG_FLASH_WRITE_TOUT)
+				return (1);
+		}
 
-	if( addr[0] & 0x003A) {	/* check for error */
-		barf = addr[0] & 0x003A;
-		printf("\nFlash write error at address %lx\n",(unsigned long)dest);
-		if(barf & 0x0002) printf("Block locked, not erased.\n");
-		if(barf & 0x0010) printf("Programming error.\n");
-		if(barf & 0x0008) printf("Vpp Low error.\n");
-		return(2);
-	}
-	*addr = 0x00B0;
-	*addr = 0x0070;
-	while(!(addr[0] & 0x0080)){  	/* wait for error or finish */
-		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) return (1);
+		if (addr[0] & 0x003A) {	/* check for error */
+			barf = addr[0] & 0x003A;
+			printf ("\nFlash write error at address %lx\n",
+				(unsigned long) dest);
+			if (barf & 0x0002)
+				printf ("Block locked, not erased.\n");
+			if (barf & 0x0010)
+				printf ("Programming error.\n");
+			if (barf & 0x0008)
+				printf ("Vpp Low error.\n");
+			return (2);
+		}
+		*addr = 0x00B0;
+		*addr = 0x0070;
+		while (!(addr[0] & 0x0080)) {	/* wait for error or finish */
+			if (get_timer (start) > CFG_FLASH_WRITE_TOUT)
+				return (1);
+		}
+		*addr = 0x00FF;
 	}
-
-	*addr = 0x00FF;
-
-     }
-
 	return (0);
-
 }
 
-
 #endif
-
-/*-----------------------------------------------------------------------
- */
+/*-----------------------------------------------------------------------*/
diff --git a/board/esteem192e/u-boot.lds b/board/esteem192e/u-boot.lds
index 2a8d9e2f6c..acaf4e34fc 100644
--- a/board/esteem192e/u-boot.lds
+++ b/board/esteem192e/u-boot.lds
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/etin/debris/debris.c b/board/etin/debris/debris.c
index 08ed635f34..67375e9fea 100644
--- a/board/etin/debris/debris.c
+++ b/board/etin/debris/debris.c
@@ -43,7 +43,7 @@ int checkboard (void)
 	return 0;
 }
 
-#if 0 	/* NOT USED */
+#if 0	/* NOT USED */
 int checkflash (void)
 {
 	/* TODO: XXX XXX XXX */
diff --git a/board/etin/debris/speed.h b/board/etin/debris/speed.h
index b66393bec5..3f32a143cc 100644
--- a/board/etin/debris/speed.h
+++ b/board/etin/debris/speed.h
@@ -28,10 +28,10 @@
  * SPEED_TMR3_PS = (GCLK / (16 * SPEED_FCOUNT3)) - 1
  *
  * SPEED_FCOUNT2	timer 2 counting frequency
- * GCLK	      		CPU clock
+ * GCLK			CPU clock
  * SPEED_TMR2_PS	prescaler
  */
-#define SPEED_TMR2_PS  	(250 - 1)	/* divide by 250	*/
+#define SPEED_TMR2_PS	(250 - 1)	/* divide by 250	*/
 
 /*-----------------------------------------------------------------------
  * Timer value for PIT
diff --git a/board/etx094/u-boot.lds b/board/etx094/u-boot.lds
index 0e7bd37b42..5313bd40a5 100644
--- a/board/etx094/u-boot.lds
+++ b/board/etx094/u-boot.lds
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/etx094/u-boot.lds.debug b/board/etx094/u-boot.lds.debug
index a0121cedb5..06115ead82 100644
--- a/board/etx094/u-boot.lds.debug
+++ b/board/etx094/u-boot.lds.debug
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/evb64260/bootseq.txt b/board/evb64260/bootseq.txt
index 391d49a119..290aed90a5 100644
--- a/board/evb64260/bootseq.txt
+++ b/board/evb64260/bootseq.txt
@@ -56,7 +56,7 @@ in_flash:
     setup stack pointer (r1)
     setup GOT
     call cpu_init_f
-    	debug leds
+	debug leds
     board_init_f: (common/board.c)
 	board_early_init_f:
 	    remap gt regs?
@@ -74,7 +74,7 @@ in_flash:
 		dram_size()
 		setup PCI slave memory mappings
 		setup SCS
-   	setup monitor
+	setup monitor
 	alloc board info struct
 	init bd struct
 	relocate_code: (cpu/mpc7xxx/start.S)
diff --git a/board/evb64260/eth.c b/board/evb64260/eth.c
index add2b3df53..618af6f90c 100644
--- a/board/evb64260/eth.c
+++ b/board/evb64260/eth.c
@@ -529,7 +529,7 @@ gt6426x_eth_probe(void *v, bd_t *bis)
 #endif
 
 	/* 31  28 27  24 23  20 19  16
-	 *  0000   0000   0000   0000 	[0004]
+	 *  0000   0000   0000   0000	[0004]
 	 * 15  12 11  8   7  4   3  0
 	 *  1000   1101   0000   0000	[4d00]
 	 *    20 - 0=MII 1=RMII
diff --git a/board/evb64260/mpsc.c b/board/evb64260/mpsc.c
index 98ac7f63df..9e8bfe01c4 100644
--- a/board/evb64260/mpsc.c
+++ b/board/evb64260/mpsc.c
@@ -309,9 +309,9 @@ mpsc_init(int baud)
 
 	/* COMM_MPSC CONFIG */
 #ifdef SOFTWARE_CACHE_MANAGEMENT
-	galmpsc_set_snoop(CHANNEL, 0);     				/* disable snoop */
+	galmpsc_set_snoop(CHANNEL, 0);				/* disable snoop */
 #else
-	galmpsc_set_snoop(CHANNEL, 1);     				/* enable snoop */
+	galmpsc_set_snoop(CHANNEL, 1);				/* enable snoop */
 #endif
 
 	return 0;
diff --git a/board/evb64260/mpsc.h b/board/evb64260/mpsc.h
index 54b642a83d..c71258ca49 100644
--- a/board/evb64260/mpsc.h
+++ b/board/evb64260/mpsc.h
@@ -55,9 +55,9 @@ extern int (*mpsc_putchar)(char ch);
 #define TX_STOP     0x00010000
 #define RX_ENABLE   0x00000080
 
-#define SDMA_RX_ABORT 		  (1 << 15)
-#define SDMA_TX_ABORT 		  (1 << 31)
-#define MPSC_TX_ABORT 		  (1 << 7)
+#define SDMA_RX_ABORT		  (1 << 15)
+#define SDMA_TX_ABORT		  (1 << 31)
+#define MPSC_TX_ABORT		  (1 << 7)
 #define MPSC_RX_ABORT             (1 << 23)
 #define MPSC_ENTER_HUNT           (1 << 31)
 
diff --git a/board/evb64260/u-boot.lds b/board/evb64260/u-boot.lds
index 25e16de3b6..1a95755ab4 100644
--- a/board/evb64260/u-boot.lds
+++ b/board/evb64260/u-boot.lds
@@ -37,11 +37,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/evb64260/zuma_pbb_mbox.c b/board/evb64260/zuma_pbb_mbox.c
index 2b9a469f8d..6f5df6e806 100644
--- a/board/evb64260/zuma_pbb_mbox.c
+++ b/board/evb64260/zuma_pbb_mbox.c
@@ -148,7 +148,7 @@ zuma_mbox_setenv(void)
 }
 
 /**
- * 	zuma_mbox_init:
+ *	zuma_mbox_init:
  */
 
 int zuma_mbox_init(void)
diff --git a/board/exbitgen/exbitgen.h b/board/exbitgen/exbitgen.h
index 058ad48ea2..dceaf6dbc0 100644
--- a/board/exbitgen/exbitgen.h
+++ b/board/exbitgen/exbitgen.h
@@ -25,15 +25,15 @@
 
 
 #define CPLD_BASE		0x10000000		/* t.b.m. */
-#define DEBUG_LEDS_ADDR 	CPLD_BASE + 0x01
-#define HW_ID_ADDR      	CPLD_BASE + 0x02
-#define DIP_SWITCH_ADDR 	CPLD_BASE + 0x04
-#define PHY_CTRL_ADDR   	CPLD_BASE + 0x05
-#define SPI_OUT_ADDR    	CPLD_BASE + 0x07
-#define SPI_IN_ADDR     	CPLD_BASE + 0x08
-#define MDIO_OUT_ADDR   	CPLD_BASE + 0x09
-#define MDIO_IN_ADDR    	CPLD_BASE + 0x0A
-#define MISC_OUT_ADDR   	CPLD_BASE + 0x0B
+#define DEBUG_LEDS_ADDR		CPLD_BASE + 0x01
+#define HW_ID_ADDR		CPLD_BASE + 0x02
+#define DIP_SWITCH_ADDR		CPLD_BASE + 0x04
+#define PHY_CTRL_ADDR		CPLD_BASE + 0x05
+#define SPI_OUT_ADDR		CPLD_BASE + 0x07
+#define SPI_IN_ADDR		CPLD_BASE + 0x08
+#define MDIO_OUT_ADDR		CPLD_BASE + 0x09
+#define MDIO_IN_ADDR		CPLD_BASE + 0x0A
+#define MISC_OUT_ADDR		CPLD_BASE + 0x0B
 
 /* Addresses used on I2C bus */
 #define LM75_CHIP_ADDR		0x9C
diff --git a/board/exbitgen/init.S b/board/exbitgen/init.S
index 0e6cd04ba8..71aefb97cf 100644
--- a/board/exbitgen/init.S
+++ b/board/exbitgen/init.S
@@ -184,11 +184,11 @@ ext_bus_cntlr_init:
 	ori	r3, r3, HW_ID_ADDR@l
 	lbz     r3,0x0000(r3)
 	cmpi	0, r3, 1          /* if (HW_ID==1) */
-	beq 	setup_h2evalboard /* then jump */
+	beq	setup_h2evalboard /* then jump */
 	cmpi	0, r3, 2          /* if (HW_ID==2) */
-	beq 	setup_genieboard  /* then jump */
+	beq	setup_genieboard  /* then jump */
 	cmpi	0, r3, 3          /* if (HW_ID==3) */
-	beq 	setup_genieboard  /* then jump */
+	beq	setup_genieboard  /* then jump */
 
 setup_genieboard:
 	/*--------------------------------------------------------------- */
diff --git a/board/exbitgen/u-boot.lds b/board/exbitgen/u-boot.lds
index 99068e773d..e4faa446ee 100644
--- a/board/exbitgen/u-boot.lds
+++ b/board/exbitgen/u-boot.lds
@@ -38,11 +38,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/fads/fads.h b/board/fads/fads.h
index ffa72cbb41..0a8b98352a 100644
--- a/board/fads/fads.h
+++ b/board/fads/fads.h
@@ -143,7 +143,7 @@
 #define	CFG_MAXARGS		16		/* max number of command args	*/
 #define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_LOAD_ADDR	 	0x00100000
+#define CFG_LOAD_ADDR		0x00100000
 
 #define	CFG_HZ		        1000	/* decrementer freq: 1 ms ticks */
 
@@ -176,7 +176,7 @@
  */
 #define	CFG_SDRAM_BASE		0x00000000
 #if defined(CONFIG_MPC86xADS) || defined(CONFIG_MPC885ADS) /* New ADS or Duet */
-#define	CFG_SDRAM_SIZE		0x00800000      	/* 8 Mbyte */
+#define	CFG_SDRAM_SIZE		0x00800000	/* 8 Mbyte */
 /*
  * 2048	SDRAM rows
  * 1000	factor s -> ms
@@ -195,7 +195,7 @@
 #if (CFG_SDRAM_SIZE)
 #define CFG_MEMTEST_END		CFG_SDRAM_SIZE	/* 1 ... SDRAM_SIZE	*/
 #else
-#define CFG_MEMTEST_END		0x0400000     	/* 1 ... 4 MB in DRAM	*/
+#define CFG_MEMTEST_END		0x0400000	/* 1 ... 4 MB in DRAM	*/
 #endif /* CFG_SDRAM_SIZE */
 
 /*
diff --git a/board/fads/pcmcia.c b/board/fads/pcmcia.c
index 57a24543a8..99fe0b4fb9 100644
--- a/board/fads/pcmcia.c
+++ b/board/fads/pcmcia.c
@@ -62,7 +62,7 @@ int pcmcia_voltage_set(int slot, int vcc, int vpp)
 	*((uint *)BCSR1) |= reg;
 #endif
 
- 	*((uint *)BCSR1) |= reg << 20;
+	*((uint *)BCSR1) |= reg << 20;
 
 	return 0;
 }
diff --git a/board/fads/u-boot.lds b/board/fads/u-boot.lds
index 51db49094d..c7571e4996 100644
--- a/board/fads/u-boot.lds
+++ b/board/fads/u-boot.lds
@@ -31,11 +31,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)	}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)	}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)	}
   .rela.got      : { *(.rela.got)	}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/fads/u-boot.lds.debug b/board/fads/u-boot.lds.debug
index 96c4e22c24..fd2245f57b 100644
--- a/board/fads/u-boot.lds.debug
+++ b/board/fads/u-boot.lds.debug
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/flagadm/u-boot.lds b/board/flagadm/u-boot.lds
index ca8ffb07c0..f0984126b1 100644
--- a/board/flagadm/u-boot.lds
+++ b/board/flagadm/u-boot.lds
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/flagadm/u-boot.lds.debug b/board/flagadm/u-boot.lds.debug
index 1a25a98f17..85072feda4 100644
--- a/board/flagadm/u-boot.lds.debug
+++ b/board/flagadm/u-boot.lds.debug
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/freescale/common/fsl_diu_fb.c b/board/freescale/common/fsl_diu_fb.c
index 2336f6bc5c..75f782e9da 100644
--- a/board/freescale/common/fsl_diu_fb.c
+++ b/board/freescale/common/fsl_diu_fb.c
@@ -29,12 +29,6 @@
 
 #include "fsl_diu_fb.h"
 
-#ifdef DEBUG
-#define DPRINTF(fmt, args...) printf("%s: " fmt,__FUNCTION__,## args)
-#else
-#define DPRINTF(fmt, args...)
-#endif
-
 struct fb_videomode {
 	const char *name;	/* optional */
 	unsigned int refresh;		/* optional */
@@ -160,11 +154,9 @@ struct diu_hw {
 
 struct diu_addr {
 	unsigned char  *  paddr;	/* Virtual address */
-	unsigned int 	   offset;
+	unsigned int	   offset;
 };
 
-#define FSL_DIU_BASE_OFFSET	0x2C000	/* Offset of Display Interface Unit */
-
 /*
  * Modes of operation of DIU
  */
@@ -197,7 +189,7 @@ static void disable_lcdc(void);
 static int fsl_diu_enable_panel(struct fb_info *info);
 static int fsl_diu_disable_panel(struct fb_info *info);
 static int allocate_buf(struct diu_addr *buf, u32 size, u32 bytes_align);
-static u32 get_busfreq(void);
+void diu_set_pixel_clock(unsigned int pixclock);
 
 int fsl_diu_init(int xres,
 		 unsigned int pixel_format,
@@ -209,15 +201,11 @@ int fsl_diu_init(int xres,
 	struct diu *hw;
 	struct fb_info *info = &fsl_fb_info;
 	struct fb_var_screeninfo *var = &info->var;
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
-	volatile ccsr_gur_t *gur = &immap->im_gur;
-	volatile unsigned int *guts_clkdvdr = &gur->clkdvdr;
 	unsigned char *gamma_table_base;
 	unsigned int i, j;
-	unsigned long speed_ccb, temp, pixval;
 
-	DPRINTF("Enter fsl_diu_init\n");
-	dr.diu_reg = (struct diu *) (CFG_IMMR + FSL_DIU_BASE_OFFSET);
+	debug("Enter fsl_diu_init\n");
+	dr.diu_reg = (struct diu *) (CFG_DIU_ADDR);
 	hw = (struct diu *) dr.diu_reg;
 
 	disable_lcdc();
@@ -230,10 +218,10 @@ int fsl_diu_init(int xres,
 
 	if (0 == fb_initialized) {
 		allocate_buf(&gamma, 768, 32);
-		DPRINTF("gamma is allocated @ 0x%x\n",
+		debug("gamma is allocated @ 0x%x\n",
 			(unsigned int)gamma.paddr);
 		allocate_buf(&cursor, MAX_CURS * MAX_CURS * 2, 32);
-		DPRINTF("curosr is allocated @ 0x%x\n",
+		debug("curosr is allocated @ 0x%x\n",
 			(unsigned int)cursor.paddr);
 
 		/* create a dummy fb and dummy ad */
@@ -261,8 +249,8 @@ int fsl_diu_init(int xres,
 	dr.diu_reg->desc[0] = (unsigned int) &dummy_ad;
 	dr.diu_reg->desc[1] = (unsigned int) &dummy_ad;
 	dr.diu_reg->desc[2] = (unsigned int) &dummy_ad;
-	DPRINTF("dummy dr.diu_reg->desc[0] = 0x%x\n", dr.diu_reg->desc[0]);
-	DPRINTF("dummy desc[0] = 0x%x\n", hw->desc[0]);
+	debug("dummy dr.diu_reg->desc[0] = 0x%x\n", dr.diu_reg->desc[0]);
+	debug("dummy desc[0] = 0x%x\n", hw->desc[0]);
 
 	/* read mode info */
 	var->xres = fsl_diu_mode_db->xres;
@@ -286,7 +274,7 @@ int fsl_diu_init(int xres,
 	ad->src_size_g_alpha
 			= cpu_to_le32((var->yres << 12) | var->xres);
 	/* fix me. AOI should not be greater than display size */
-	ad->aoi_size 	= cpu_to_le32(( var->yres << 16) |  var->xres);
+	ad->aoi_size	= cpu_to_le32(( var->yres << 16) |  var->xres);
 	ad->offset_xyi = 0;
 	ad->offset_xyd = 0;
 
@@ -300,7 +288,7 @@ int fsl_diu_init(int xres,
 	ad->ckmin_b = 255;
 
 	gamma_table_base = gamma.paddr;
-	DPRINTF("gamma_table_base is allocated @ 0x%x\n",
+	debug("gamma_table_base is allocated @ 0x%x\n",
 		(unsigned int)gamma_table_base);
 
 	/* Prep for DIU init  - gamma table */
@@ -310,7 +298,7 @@ int fsl_diu_init(int xres,
 			*gamma_table_base++ = j;
 
 	if (gamma_fix == 1) {	/* fix the gamma */
-		DPRINTF("Fix gamma table\n");
+		debug("Fix gamma table\n");
 		gamma_table_base = gamma.paddr;
 		for (i = 0; i < 256*3; i++) {
 			gamma_table_base[i] = (gamma_table_base[i] << 2)
@@ -318,14 +306,14 @@ int fsl_diu_init(int xres,
 		}
 	}
 
-	DPRINTF("update-lcdc: HW - %p\n Disabling DIU\n", hw);
+	debug("update-lcdc: HW - %p\n Disabling DIU\n", hw);
 
 	/* Program DIU registers */
 
 	hw->gamma = (unsigned int) gamma.paddr;
 	hw->cursor= (unsigned int) cursor.paddr;
 	hw->bgnd = 0x007F7F7F;				/* BGND */
-	hw->bgnd_wb = 0; 				/* BGND_WB */
+	hw->bgnd_wb = 0;				/* BGND_WB */
 	hw->disp_size = var->yres << 16 | var->xres;	/* DISP SIZE */
 	hw->wb_size = 0;				/* WB SIZE */
 	hw->wb_mem_addr = 0;				/* WB MEM ADDR */
@@ -336,37 +324,22 @@ int fsl_diu_init(int xres,
 			var->vsync_len << 11    |	/* PW_V  */
 			var->lower_margin;		/* FP_V  */
 
-	/* Pixel Clock configuration */
-	DPRINTF("DIU: Bus Frequency = %d\n", get_busfreq());
-	speed_ccb = get_busfreq();
-
-	DPRINTF("DIU pixclock in ps - %d\n", var->pixclock);
-	temp = 1;
-	temp *= 1000000000;
-	temp /= var->pixclock;
-	temp *= 1000;
-	pixval = speed_ccb / temp;
-	DPRINTF("DIU pixval = %lu\n", pixval);
-
 	hw->syn_pol = 0;			/* SYNC SIGNALS POLARITY */
 	hw->thresholds = 0x00037800;		/* The Thresholds */
 	hw->int_status = 0;			/* INTERRUPT STATUS */
 	hw->int_mask = 0;			/* INT MASK */
 	hw->plut = 0x01F5F666;
 
-	/* Modify PXCLK in GUTS CLKDVDR */
-	DPRINTF("DIU: Current value of CLKDVDR = 0x%08x\n", *guts_clkdvdr);
-	temp = *guts_clkdvdr & 0x2000FFFF;
-	*guts_clkdvdr = temp;				/* turn off clock */
-	*guts_clkdvdr = temp | 0x80000000 | ((pixval & 0x1F) << 16);
-	DPRINTF("DIU: Modified value of CLKDVDR = 0x%08x\n", *guts_clkdvdr);
+	/* Pixel Clock configuration */
+	debug("DIU pixclock in ps - %d\n", var->pixclock);
+	diu_set_pixel_clock(var->pixclock);
 
 	fb_initialized = 1;
 
 	if (splash_bmp) {
 		info->logo_height = fsl_diu_display_bmp(splash_bmp, 0, 0, 0);
 		info->logo_size = info->logo_height * info->line_length;
-		DPRINTF("logo height %d, logo_size 0x%x\n",
+		debug("logo height %d, logo_size 0x%x\n",
 			info->logo_height,info->logo_size);
 	}
 
@@ -395,10 +368,10 @@ static int fsl_diu_enable_panel(struct fb_info *info)
 	struct diu *hw = dr.diu_reg;
 	struct diu_ad *ad = &fsl_diu_fb_ad;
 
-	DPRINTF("Entered: enable_panel\n");
+	debug("Entered: enable_panel\n");
 	if (hw->desc[0] != (unsigned int)ad)
 		hw->desc[0] = (unsigned int)ad;
-	DPRINTF("desc[0] = 0x%x\n", hw->desc[0]);
+	debug("desc[0] = 0x%x\n", hw->desc[0]);
 	return 0;
 }
 
@@ -406,7 +379,7 @@ static int fsl_diu_disable_panel(struct fb_info *info)
 {
 	struct diu *hw = dr.diu_reg;
 
-	DPRINTF("Entered: disable_panel\n");
+	debug("Entered: disable_panel\n");
 	if (hw->desc[0] != (unsigned int)&dummy_ad)
 		hw->desc[0] = (unsigned int)&dummy_ad;
 	return 0;
@@ -417,10 +390,10 @@ static int map_video_memory(struct fb_info *info, unsigned long bytes_align)
 	unsigned long offset;
 	unsigned long mask;
 
-	DPRINTF("Entered: map_video_memory\n");
+	debug("Entered: map_video_memory\n");
 	/* allocate maximum 1280*1024 with 32bpp */
 	info->smem_len = 1280 * 4 *1024 + bytes_align;
-	DPRINTF("MAP_VIDEO_MEMORY: smem_len = %d\n", info->smem_len);
+	debug("MAP_VIDEO_MEMORY: smem_len = %d\n", info->smem_len);
 	info->screen_base = malloc(info->smem_len);
 	if (info->screen_base == NULL) {
 		printf("Unable to allocate fb memory\n");
@@ -437,7 +410,7 @@ static int map_video_memory(struct fb_info *info, unsigned long bytes_align)
 
 	info->screen_size = info->smem_len;
 
-	DPRINTF("Allocated fb @ 0x%08lx, size=%d.\n",
+	debug("Allocated fb @ 0x%08lx, size=%d.\n",
 		info->smem_start, info->smem_len);
 
 	return 0;
@@ -447,33 +420,25 @@ static void enable_lcdc(void)
 {
 	struct diu *hw = dr.diu_reg;
 
-	DPRINTF("Entered: enable_lcdc, fb_enabled = %d\n", fb_enabled);
+	debug("Entered: enable_lcdc, fb_enabled = %d\n", fb_enabled);
 	if (!fb_enabled) {
 		hw->diu_mode = dr.mode;
 		fb_enabled++;
 	}
-	DPRINTF("diu_mode = %d\n", hw->diu_mode);
+	debug("diu_mode = %d\n", hw->diu_mode);
 }
 
 static void disable_lcdc(void)
 {
 	struct diu *hw = dr.diu_reg;
 
-	DPRINTF("Entered: disable_lcdc, fb_enabled = %d\n", fb_enabled);
+	debug("Entered: disable_lcdc, fb_enabled = %d\n", fb_enabled);
 	if (fb_enabled) {
 		hw->diu_mode = 0;
 		fb_enabled = 0;
 	}
 }
 
-static u32 get_busfreq(void)
-{
-	u32 fs_busfreq = 0;
-
-	fs_busfreq = get_bus_freq(0);
-	return fs_busfreq;
-}
-
 /*
  * Align to 64-bit(8-byte), 32-byte, etc.
  */
@@ -482,7 +447,7 @@ static int allocate_buf(struct diu_addr *buf, u32 size, u32 bytes_align)
 	u32 offset, ssize;
 	u32 mask;
 
-	DPRINTF("Entered: allocate_buf\n");
+	debug("Entered: allocate_buf\n");
 	ssize = size + bytes_align;
 	buf->paddr = malloc(ssize);
 	if (!buf->paddr)
@@ -524,16 +489,16 @@ int fsl_diu_display_bmp(unsigned char *bmp,
 	bitmap   = bmp + raster;
 	cpp = info->var.bits_per_pixel / 8;
 
-	DPRINTF("bmp = 0x%08x\n", (unsigned int)bmp);
-	DPRINTF("bitmap = 0x%08x\n", (unsigned int)bitmap);
-	DPRINTF("width = %d\n", width);
-	DPRINTF("height = %d\n", height);
-	DPRINTF("bpp = %d\n", bpp);
-	DPRINTF("ncolors = %d\n", ncolors);
+	debug("bmp = 0x%08x\n", (unsigned int)bmp);
+	debug("bitmap = 0x%08x\n", (unsigned int)bitmap);
+	debug("width = %d\n", width);
+	debug("height = %d\n", height);
+	debug("bpp = %d\n", bpp);
+	debug("ncolors = %d\n", ncolors);
 
-	DPRINTF("xres = %d\n", info->var.xres);
-	DPRINTF("yres = %d\n", info->var.yres);
-	DPRINTF("Screen_base = 0x%x\n", (unsigned int)info->screen_base);
+	debug("xres = %d\n", info->var.xres);
+	debug("yres = %d\n", info->var.yres);
+	debug("Screen_base = 0x%x\n", (unsigned int)info->screen_base);
 
 	if (((width+xoffset) > info->var.xres) ||
 	    ((height+yoffset) > info->var.yres)) {
diff --git a/board/freescale/common/pixis.c b/board/freescale/common/pixis.c
index bff6a82e28..64e2e08c54 100644
--- a/board/freescale/common/pixis.c
+++ b/board/freescale/common/pixis.c
@@ -397,7 +397,7 @@ pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	 * Check that cf has all required parms
 	 */
 	if ((p_cf && !(p_cf_sysclk && p_cf_corepll && p_cf_mpxpll))
-	    || 	unknown_param) {
+	    ||	unknown_param) {
 		puts(cmdtp->help);
 		return 1;
 	}
diff --git a/board/freescale/common/sys_eeprom.c b/board/freescale/common/sys_eeprom.c
index c8e17d0dd0..8b13d06c3d 100644
--- a/board/freescale/common/sys_eeprom.c
+++ b/board/freescale/common/sys_eeprom.c
@@ -32,15 +32,15 @@ typedef struct {
 	u8 sn[12];		/* 0x0004 - 0x000F Serial Number */
 	u8 errata[5];		/* 0x0010 - 0x0014 Errata Level */
 	u8 date[6];		/* 0x0015 - 0x001a Build Date */
-	u8 res_0;		/* 0x001b 	   Reserved */
+	u8 res_0;		/* 0x001b	   Reserved */
 	u8 version[4];		/* 0x001c - 0x001f Version */
 	u8 tempcal[8];		/* 0x0020 - 0x0027 Temperature Calibration Factors*/
-	u8 tempcalsys[2]; 	/* 0x0028 - 0x0029 System Temperature Calibration Factors*/
+	u8 tempcalsys[2];	/* 0x0028 - 0x0029 System Temperature Calibration Factors*/
 	u8 res_1[22];		/* 0x0020 - 0x003f Reserved */
-	u8 mac_size;		/* 0x0040 	   Mac table size */
-	u8 mac_flag;		/* 0x0041 	   Mac table flags */
+	u8 mac_size;		/* 0x0040	   Mac table size */
+	u8 mac_flag;		/* 0x0041	   Mac table flags */
 	u8 mac[8][6];		/* 0x0042 - 0x0071 Mac addresses */
-	u32 crc;		/* 0x0072 	   crc32 checksum */
+	u32 crc;		/* 0x0072	   crc32 checksum */
 } EEPROM_data;
 
 static EEPROM_data mac_data;
diff --git a/board/freescale/m52277evb/u-boot.lds b/board/freescale/m52277evb/u-boot.lds
index 9fda0cab54..098e9d3464 100644
--- a/board/freescale/m52277evb/u-boot.lds
+++ b/board/freescale/m52277evb/u-boot.lds
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/freescale/m5235evb/u-boot.16 b/board/freescale/m5235evb/u-boot.16
index c8c215ca17..4ca026fc53 100644
--- a/board/freescale/m5235evb/u-boot.16
+++ b/board/freescale/m5235evb/u-boot.16
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/freescale/m5235evb/u-boot.32 b/board/freescale/m5235evb/u-boot.32
index 95b10c7bbc..eeffdfb4e7 100644
--- a/board/freescale/m5235evb/u-boot.32
+++ b/board/freescale/m5235evb/u-boot.32
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/freescale/m5235evb/u-boot.lds b/board/freescale/m5235evb/u-boot.lds
index ba07426fe5..33133a0fcd 100644
--- a/board/freescale/m5235evb/u-boot.lds
+++ b/board/freescale/m5235evb/u-boot.lds
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/freescale/m5249evb/u-boot.lds b/board/freescale/m5249evb/u-boot.lds
index d21ecd497b..afdb7202ca 100644
--- a/board/freescale/m5249evb/u-boot.lds
+++ b/board/freescale/m5249evb/u-boot.lds
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/freescale/m5253evbe/u-boot.lds b/board/freescale/m5253evbe/u-boot.lds
index 089dc10f52..6d225f5281 100644
--- a/board/freescale/m5253evbe/u-boot.lds
+++ b/board/freescale/m5253evbe/u-boot.lds
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)	}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)	}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)	}
   .rela.got      : { *(.rela.got)	}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/freescale/m5275evb/u-boot.lds b/board/freescale/m5275evb/u-boot.lds
index 51c008f4fe..d810ebc144 100644
--- a/board/freescale/m5275evb/u-boot.lds
+++ b/board/freescale/m5275evb/u-boot.lds
@@ -49,7 +49,7 @@ SECTIONS
   .rel.plt       : { *(.rel.plt)	}
   .rela.plt      : { *(.rela.plt)	}
   .init          : { *(.init)		}
-  .plt           : { *(.plt) 		}
+  .plt           : { *(.plt)		}
   .text      :
   {
     /* WARNING - the following is hand-optimized to fit within	*/
diff --git a/board/freescale/m5329evb/u-boot.lds b/board/freescale/m5329evb/u-boot.lds
index cf9730d13d..1ddfbc4706 100644
--- a/board/freescale/m5329evb/u-boot.lds
+++ b/board/freescale/m5329evb/u-boot.lds
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/freescale/m5373evb/u-boot.lds b/board/freescale/m5373evb/u-boot.lds
index 47e1f67a0e..d30a401be9 100644
--- a/board/freescale/m5373evb/u-boot.lds
+++ b/board/freescale/m5373evb/u-boot.lds
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/freescale/m54455evb/u-boot.atm b/board/freescale/m54455evb/u-boot.atm
index 6562fd1c5b..22c6048653 100644
--- a/board/freescale/m54455evb/u-boot.atm
+++ b/board/freescale/m54455evb/u-boot.atm
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/freescale/m54455evb/u-boot.int b/board/freescale/m54455evb/u-boot.int
index 70cb7e2862..4d504a22f1 100644
--- a/board/freescale/m54455evb/u-boot.int
+++ b/board/freescale/m54455evb/u-boot.int
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/freescale/m54455evb/u-boot.lds b/board/freescale/m54455evb/u-boot.lds
index c0ca4516ac..1aa53c23f6 100644
--- a/board/freescale/m54455evb/u-boot.lds
+++ b/board/freescale/m54455evb/u-boot.lds
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/freescale/m547xevb/u-boot.lds b/board/freescale/m547xevb/u-boot.lds
index f87e4bed3b..cc7f3eba87 100644
--- a/board/freescale/m547xevb/u-boot.lds
+++ b/board/freescale/m547xevb/u-boot.lds
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/freescale/m548xevb/u-boot.lds b/board/freescale/m548xevb/u-boot.lds
index f87e4bed3b..cc7f3eba87 100644
--- a/board/freescale/m548xevb/u-boot.lds
+++ b/board/freescale/m548xevb/u-boot.lds
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/freescale/mpc7448hpc2/asm_init.S b/board/freescale/mpc7448hpc2/asm_init.S
index a7a40a134c..521301fcec 100644
--- a/board/freescale/mpc7448hpc2/asm_init.S
+++ b/board/freescale/mpc7448hpc2/asm_init.S
@@ -415,7 +415,7 @@ set_default_values:
 #ifdef SDC_AUTOPRECH_EN
 	oris	r5,r5,0x0001		/* set auto precharge EN bit */
 #endif
-	stw 	r5,SD_D0_CTRL(r4)
+	stw	r5,SD_D0_CTRL(r4)
 	LOAD_U32(r5,VAL_SD_D0_BAR)
 	stw	r5,SD_D0_BAR(r4)
 	sync
diff --git a/board/freescale/mpc7448hpc2/tsi108_init.c b/board/freescale/mpc7448hpc2/tsi108_init.c
index 30ae17d872..efa952c2e7 100644
--- a/board/freescale/mpc7448hpc2/tsi108_init.c
+++ b/board/freescale/mpc7448hpc2/tsi108_init.c
@@ -616,7 +616,7 @@ int misc_init_r (void)
 		0x802e0044);	/* D=0.25% */
 	out32 (CFG_TSI108_CSR_BASE +
 		TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0,
-	 	0x80000000 | pll0_config[i].ctrl0);
+		0x80000000 | pll0_config[i].ctrl0);
 #endif	/* CFG_CLK_SPREAD */
 
 #ifdef CFG_L2
diff --git a/board/freescale/mpc7448hpc2/u-boot.lds b/board/freescale/mpc7448hpc2/u-boot.lds
index 77dfad6f69..6b228f7a91 100644
--- a/board/freescale/mpc7448hpc2/u-boot.lds
+++ b/board/freescale/mpc7448hpc2/u-boot.lds
@@ -37,11 +37,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/freescale/mpc8260ads/mpc8260ads.c b/board/freescale/mpc8260ads/mpc8260ads.c
index 93550e2ad0..548d813af5 100644
--- a/board/freescale/mpc8260ads/mpc8260ads.c
+++ b/board/freescale/mpc8260ads/mpc8260ads.c
@@ -340,7 +340,7 @@ long int initdram (int board_type)
 #if CONFIG_ADSTYPE == CFG_PQ2FADS /* CS3 */
 		memctl->memc_or3   = 0xFF803280;
 		memctl->memc_br3   = CFG_LSDRAM_BASE | 0x00001861;
-#else  				  /* CS4 */
+#else				  /* CS4 */
 		memctl->memc_or4   = 0xFFC01480;
 		memctl->memc_br4   = CFG_LSDRAM_BASE | 0x00001861;
 #endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */
diff --git a/board/freescale/mpc8349emds/pci.c b/board/freescale/mpc8349emds/pci.c
index 564e436f8d..ecc67b66e5 100644
--- a/board/freescale/mpc8349emds/pci.c
+++ b/board/freescale/mpc8349emds/pci.c
@@ -43,7 +43,7 @@ DECLARE_GLOBAL_DATA_PTR;
 static struct pci_config_table pci_mpc8349emds_config_table[] = {
 	{PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
 	 PCI_IDSEL_NUMBER, PCI_ANY_ID,
- 	 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
+	 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
 				     PCI_ENET0_MEMADDR,
 				     PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
 		}
diff --git a/board/freescale/mpc8349itx/mpc8349itx.c b/board/freescale/mpc8349itx/mpc8349itx.c
index 704f9636bc..0317bfe6d4 100644
--- a/board/freescale/mpc8349itx/mpc8349itx.c
+++ b/board/freescale/mpc8349itx/mpc8349itx.c
@@ -273,13 +273,13 @@ int misc_init_r(void)
 	static u8 eeprom_data[] =	/* HRCW data */
 	{
 		0xAA, 0x55, 0xAA,       /* Preamble */
-		0x7C, 		        /* ACS=0, BYTE_EN=1111, CONT=1 */
-		0x02, 0x40, 	        /* RCWL ADDR=0x0_0900 */
+		0x7C,		        /* ACS=0, BYTE_EN=1111, CONT=1 */
+		0x02, 0x40,	        /* RCWL ADDR=0x0_0900 */
 		(CFG_HRCW_LOW >> 24) & 0xFF,
 		(CFG_HRCW_LOW >> 16) & 0xFF,
 		(CFG_HRCW_LOW >> 8) & 0xFF,
 		CFG_HRCW_LOW & 0xFF,
-		0x7C, 		        /* ACS=0, BYTE_EN=1111, CONT=1 */
+		0x7C,		        /* ACS=0, BYTE_EN=1111, CONT=1 */
 		0x02, 0x41,	        /* RCWH ADDR=0x0_0904 */
 		(CFG_HRCW_HIGH >> 24) & 0xFF,
 		(CFG_HRCW_HIGH >> 16) & 0xFF,
diff --git a/board/freescale/mpc8540ads/u-boot.lds b/board/freescale/mpc8540ads/u-boot.lds
index 075d8f3852..f200810f06 100644
--- a/board/freescale/mpc8540ads/u-boot.lds
+++ b/board/freescale/mpc8540ads/u-boot.lds
@@ -43,11 +43,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/freescale/mpc8541cds/u-boot.lds b/board/freescale/mpc8541cds/u-boot.lds
index d0ba43c21b..5f4dcf021d 100644
--- a/board/freescale/mpc8541cds/u-boot.lds
+++ b/board/freescale/mpc8541cds/u-boot.lds
@@ -42,11 +42,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/freescale/mpc8544ds/u-boot.lds b/board/freescale/mpc8544ds/u-boot.lds
index b551339cfc..785a00616b 100644
--- a/board/freescale/mpc8544ds/u-boot.lds
+++ b/board/freescale/mpc8544ds/u-boot.lds
@@ -42,11 +42,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/freescale/mpc8548cds/u-boot.lds b/board/freescale/mpc8548cds/u-boot.lds
index 03f62b8259..eba7e8a9d3 100644
--- a/board/freescale/mpc8548cds/u-boot.lds
+++ b/board/freescale/mpc8548cds/u-boot.lds
@@ -42,11 +42,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/freescale/mpc8555cds/u-boot.lds b/board/freescale/mpc8555cds/u-boot.lds
index d0ba43c21b..5f4dcf021d 100644
--- a/board/freescale/mpc8555cds/u-boot.lds
+++ b/board/freescale/mpc8555cds/u-boot.lds
@@ -42,11 +42,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/freescale/mpc8560ads/u-boot.lds b/board/freescale/mpc8560ads/u-boot.lds
index 31412e3f91..cb30ea9a29 100644
--- a/board/freescale/mpc8560ads/u-boot.lds
+++ b/board/freescale/mpc8560ads/u-boot.lds
@@ -43,11 +43,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/freescale/mpc8568mds/bcsr.h b/board/freescale/mpc8568mds/bcsr.h
index f7f70bcfa1..046025bbb2 100644
--- a/board/freescale/mpc8568mds/bcsr.h
+++ b/board/freescale/mpc8568mds/bcsr.h
@@ -32,8 +32,8 @@
 	7	cfg boot seq
 
 	* BCSR 1 *
-	0:2 	cfg rom lock
-	3:5 	cfg host agent
+	0:2	cfg rom lock
+	3:5	cfg host agent
 	6	PCI IO
 	7	cfg RIO size
 
@@ -46,7 +46,7 @@
 	0	TSEC1 reduce
 	1	TSEC2 reduce
 	2:3	TSEC1 protocol
-	4:5 	TSEC2 protocol
+	4:5	TSEC2 protocol
 	6	PHY1 slave
 	7	PHY2 slave
 
@@ -70,9 +70,9 @@
 	7	Power on reset
 
 	* BCSR 7 *
-	2 	board host mode indication
-	5 	enable TSEC1 PHY
-	6 	enable TSEC2 PHY
+	2	board host mode indication
+	5	enable TSEC1 PHY
+	6	enable TSEC2 PHY
 
 	* BCSR 8 *
 	0	UCC GETH1 enable
diff --git a/board/freescale/mpc8568mds/tlb.c b/board/freescale/mpc8568mds/tlb.c
index a866c526c8..75651765fc 100644
--- a/board/freescale/mpc8568mds/tlb.c
+++ b/board/freescale/mpc8568mds/tlb.c
@@ -62,7 +62,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 	/*
 	 * TLBe 2:	1G	Non-cacheable, guarded
 	 * 0x80000000	512M	PCI1 MEM
-	 * 0xa0000000 	512M	PCIe MEM
+	 * 0xa0000000	512M	PCIe MEM
 	 */
 	SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
diff --git a/board/freescale/mpc8568mds/u-boot.lds b/board/freescale/mpc8568mds/u-boot.lds
index 40f6d3b3ca..1b83834c86 100644
--- a/board/freescale/mpc8568mds/u-boot.lds
+++ b/board/freescale/mpc8568mds/u-boot.lds
@@ -45,11 +45,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c b/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c
index b70637f940..4db941ced0 100644
--- a/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c
+++ b/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c
@@ -41,6 +41,26 @@ extern unsigned int FSL_Logo_BMP[];
 
 static int xres, yres;
 
+void diu_set_pixel_clock(unsigned int pixclock)
+{
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	volatile ccsr_gur_t *gur = &immap->im_gur;
+	volatile unsigned int *guts_clkdvdr = &gur->clkdvdr;
+	unsigned long speed_ccb, temp, pixval;
+
+	speed_ccb = get_bus_freq(0);
+	temp = 1000000000/pixclock;
+	temp *= 1000;
+	pixval = speed_ccb / temp;
+	debug("DIU pixval = %lu\n", pixval);
+
+	/* Modify PXCLK in GUTS CLKDVDR */
+	debug("DIU: Current value of CLKDVDR = 0x%08x\n", *guts_clkdvdr);
+	temp = *guts_clkdvdr & 0x2000FFFF;
+	*guts_clkdvdr = temp;				/* turn off clock */
+	*guts_clkdvdr = temp | 0x80000000 | ((pixval & 0x1F) << 16);
+	debug("DIU: Modified value of CLKDVDR = 0x%08x\n", *guts_clkdvdr);
+}
 
 void mpc8610hpcd_diu_init(void)
 {
diff --git a/board/freescale/mpc8641hpcn/u-boot.lds b/board/freescale/mpc8641hpcn/u-boot.lds
index 06d491bec9..4f884f987e 100644
--- a/board/freescale/mpc8641hpcn/u-boot.lds
+++ b/board/freescale/mpc8641hpcn/u-boot.lds
@@ -31,11 +31,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/g2000/u-boot.lds b/board/g2000/u-boot.lds
index 196f88c4df..d70d37934e 100644
--- a/board/g2000/u-boot.lds
+++ b/board/g2000/u-boot.lds
@@ -38,11 +38,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/gen860t/README b/board/gen860t/README
index 7205afb4de..e20680db02 100644
--- a/board/gen860t/README
+++ b/board/gen860t/README
@@ -142,5 +142,3 @@ Sr. Staff Engineer
 Microvision, Inc.
 <keith_outwater@mvis.com>
 <outwater@eskimo.com>
-
-vim: set ts=4 sw=4 tw=78:
diff --git a/board/gen860t/beeper.c b/board/gen860t/beeper.c
index 46fe66ba61..b4c2c89885 100644
--- a/board/gen860t/beeper.c
+++ b/board/gen860t/beeper.c
@@ -34,7 +34,6 @@
  * drives the amplifier input.
  */
 
-
 /*
  * Initialize beeper-related hardware. Initialize timer 1 for use with
  * the beeper. Use 66 Mhz internal clock with prescale of 33 to get
@@ -42,66 +41,59 @@
  * FIXME: we should really compute the prescale based on the reported
  * core clock frequency.
  */
-void
-init_beeper(void)
+void init_beeper (void)
 {
-    volatile immap_t *immap  = (immap_t *)CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
 
 	immap->im_cpmtimer.cpmt_tgcr &= ~TGCR_RST1 | TGCR_STP1;
 	immap->im_cpmtimer.cpmt_tmr1 = ((33 << TMR_PS_SHIFT) & TMR_PS_MSK)
-								 | TMR_OM | TMR_FRR | TMR_ICLK_IN_GEN;
+		| TMR_OM | TMR_FRR | TMR_ICLK_IN_GEN;
 	immap->im_cpmtimer.cpmt_tcn1 = 0;
 	immap->im_cpmtimer.cpmt_ter1 = 0xffff;
 	immap->im_cpmtimer.cpmt_tgcr |= TGCR_RST1;
 }
 
-
 /*
  * Set beeper frequency.  Max allowed frequency is 2.5 KHz.  This limit
  * is mostly arbitrary, but the beeper isn't really much good beyond this
  * frequency.
  */
-void
-set_beeper_frequency(uint frequency)
+void set_beeper_frequency (uint frequency)
 {
 #define FREQ_LIMIT	2500
 
-    volatile immap_t *immap  = (immap_t *)CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
 
 	/*
 	 * Compute timer ticks given desired frequency.  The timer is set up
 	 * to count 0.5 uS per tick and it takes two ticks per cycle (Hz).
 	 */
-	if (frequency > FREQ_LIMIT) frequency = FREQ_LIMIT;
-	frequency = 1000000/frequency;
-	immap->im_cpmtimer.cpmt_trr1 = (ushort)frequency;
+	if (frequency > FREQ_LIMIT)
+		frequency = FREQ_LIMIT;
+	frequency = 1000000 / frequency;
+	immap->im_cpmtimer.cpmt_trr1 = (ushort) frequency;
 }
 
-
 /*
  * Turn the beeper on
  */
-void
-beeper_on(void)
+void beeper_on (void)
 {
-    volatile immap_t *immap  = (immap_t *)CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
 
 	immap->im_cpmtimer.cpmt_tgcr &= ~TGCR_STP1;
 }
 
-
 /*
  * Turn the beeper off
  */
-void
-beeper_off(void)
+void beeper_off (void)
 {
-    volatile immap_t *immap  = (immap_t *)CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
 
 	immap->im_cpmtimer.cpmt_tgcr |= TGCR_STP1;
 }
 
-
 /*
  * Increase or decrease the beeper volume.  Volume can be set
  * from off to full in 64 steps.  To increase volume, the output
@@ -110,75 +102,71 @@ beeper_off(void)
  * change pin mode to tristate) then output a high to go back to
  * tristate.
  */
-void
-set_beeper_volume(int steps)
+void set_beeper_volume (int steps)
 {
-    volatile immap_t *immap  = (immap_t *)CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
 	int i;
 
 	if (steps >= 0) {
 		for (i = 0; i < (steps >= 64 ? 64 : steps); i++) {
 			immap->im_cpm.cp_pbodr &= ~(0x80000000 >> 19);
-			udelay(1);
+			udelay (1);
 			immap->im_cpm.cp_pbodr |= (0x80000000 >> 19);
-			udelay(1);
+			udelay (1);
 		}
-	}
-	else {
+	} else {
 		for (i = 0; i > (steps <= -64 ? -64 : steps); i--) {
 			immap->im_cpm.cp_pbdat &= ~(0x80000000 >> 19);
-			udelay(1);
+			udelay (1);
 			immap->im_cpm.cp_pbdat |= (0x80000000 >> 19);
-			udelay(1);
+			udelay (1);
 		}
 	}
 }
 
-
 /*
  * Check the environment to see if the beeper needs beeping.
  * Controlled by a sequence of the form:
  * freq/delta volume/on time/off time;... where:
- * freq 		= frequency in Hz (0 - 2500)
+ * freq			= frequency in Hz (0 - 2500)
  * delta volume = volume steps up or down (-64 <= vol <= 64)
  * on time		= time in mS
  * off time		= time in mS
  *
  * Return 1 on success, 0 on failure
  */
-int
-do_beeper(char *sequence)
+int do_beeper (char *sequence)
 {
 #define DELIMITER	';'
 
-int args[4];
-int i;
-int val;
-char *p = sequence;
-char *tp;
+	int args[4];
+	int i;
+	int val;
+	char *p = sequence;
+	char *tp;
 
 	/*
 	 * Parse the control sequence.  This is a really simple parser
 	 * without any real error checking.  You can probably blow it
 	 * up really easily.
 	 */
-	if (*p == '\0' || !isdigit(*p)) {
-		printf("%s:%d: null or invalid string (%s)\n",
-				__FILE__, __LINE__, p);
+	if (*p == '\0' || !isdigit (*p)) {
+		printf ("%s:%d: null or invalid string (%s)\n",
+			__FILE__, __LINE__, p);
 		return 0;
 	}
 
 	i = 0;
 	while (*p != '\0') {
 		while (*p != DELIMITER) {
-			if (i > 3) i = 0;
-			val = (int) simple_strtol(p, &tp, 0);
+			if (i > 3)
+				i = 0;
+			val = (int) simple_strtol (p, &tp, 0);
 			if (tp == p) {
-				printf("%s:%d: no digits or bad format\n",
-								__FILE__,__LINE__);
+				printf ("%s:%d: no digits or bad format\n",
+					__FILE__, __LINE__);
 				return 0;
-			}
-			else {
+			} else {
 				args[i] = val;
 			}
 
@@ -195,19 +183,17 @@ char *tp;
 		 */
 #if 0
 		for (i = 0; i < 4; i++) {
-			printf("%s:%d:arg %d = %d\n", __FILE__, __LINE__, i, args[i]);
+			printf ("%s:%d:arg %d = %d\n", __FILE__, __LINE__, i,
+				args[i]);
 		}
-		printf("\n");
+		printf ("\n");
 #endif
-
-		set_beeper_frequency(args[0]);
-		set_beeper_volume(args[1]);
-		beeper_on();
-		udelay(1000 * args[2]);
-		beeper_off();
-		udelay(1000 * args[3]);
+		set_beeper_frequency (args[0]);
+		set_beeper_volume (args[1]);
+		beeper_on ();
+		udelay (1000 * args[2]);
+		beeper_off ();
+		udelay (1000 * args[3]);
 	}
 	return 1;
 }
-
-/* vim: set ts=4 sw=4 tw=78: */
diff --git a/board/gen860t/beeper.h b/board/gen860t/beeper.h
index 535ee6c4d6..125b90f4b3 100644
--- a/board/gen860t/beeper.h
+++ b/board/gen860t/beeper.h
@@ -27,5 +27,3 @@ void beeper_on(void);
 void beeper_off(void);
 void set_beeper_volume(int steps);
 int do_beeper(char *sequence);
-
-/* vim: set ts=4 tw=78 sw=4: */
diff --git a/board/gen860t/flash.c b/board/gen860t/flash.c
index ec32d07dbf..13faaf39f3 100644
--- a/board/gen860t/flash.c
+++ b/board/gen860t/flash.c
@@ -156,9 +156,9 @@ flash_init (void)
 	 * Monitor protection is ON by default
 	 */
 	flash_protect(FLAG_PROTECT_SET,
-		      	  CFG_MONITOR_BASE,
-		      	  CFG_MONITOR_BASE + monitor_flash_len - 1,
-		      	  &flash_info[0]);
+			  CFG_MONITOR_BASE,
+			  CFG_MONITOR_BASE + monitor_flash_len - 1,
+			  &flash_info[0]);
 #endif
 
 #ifdef	CFG_ENV_IS_IN_FLASH
@@ -166,9 +166,9 @@ flash_init (void)
 	 * Environment protection ON by default
 	 */
 	flash_protect(FLAG_PROTECT_SET,
-		      	  CFG_ENV_ADDR,
-		      	  CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
-		      	  &flash_info[0]);
+			  CFG_ENV_ADDR,
+			  CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
+			  &flash_info[0]);
 #endif
 
 	PRINTF("## Final Flash bank size: 0x%08lx\n",size_b0);
@@ -190,14 +190,14 @@ flash_get_offsets (ulong base, flash_info_t *info)
 
 	switch (info->flash_id & FLASH_VENDMASK) {
 		case FLASH_MAN_INTEL:
-	    	for (i = 0; i < info->sector_count; i++) {
+		for (i = 0; i < info->sector_count; i++) {
 				info->start[i] = base;
 				base += 1024 * 128;
-	    	}
-	    	return;
+		}
+		return;
 
 		default:
-	   		printf ("Don't know sector offsets for FLASH"
+			printf ("Don't know sector offsets for FLASH"
 			        " type 0x%lx\n", info->flash_id);
 	    return;
 	}
@@ -436,7 +436,7 @@ write_flash_buffer8(flash_info_t *info_p, vu_char *src_p, vu_char *dest_p,
 	 * We assume that the block does not cross a boundary (we'll check before
 	 * calling this function).
 	 */
- 	for (i = 0; i < info_p->sector_count; ++i) {
+	for (i = 0; i < info_p->sector_count; ++i) {
 		if ( ((ulong)dest_p >= info_p->start[i]) &&
 		    ((ulong)dest_p < (info_p->start[i] + blocksize)) ) {
 			PRINTF("%s:%d: Dest addr 0x%p is in block %d @ 0x%.8lx\n",
diff --git a/board/gen860t/fpga.c b/board/gen860t/fpga.c
index 3816e52eed..1e6bdf1ccf 100644
--- a/board/gen860t/fpga.c
+++ b/board/gen860t/fpga.c
@@ -376,5 +376,3 @@ int fpga_busy_fn (int cookie)
 	return 0;
 }
 #endif
-
-/* vim: set ts=4 tw=78 sw=4: */
diff --git a/board/gen860t/fpga.h b/board/gen860t/fpga.h
index 01967a42fd..18deb739bc 100644
--- a/board/gen860t/fpga.h
+++ b/board/gen860t/fpga.h
@@ -41,5 +41,3 @@ extern int fpga_busy_fn(int cookie);
 extern int fpga_abort_fn(int cookie );
 extern int fpga_pre_config_fn(int cookie );
 extern int fpga_post_config_fn(int cookie );
-
-/* vim: set ts=4 sw=4 tw=78: */
diff --git a/board/gen860t/ioport.c b/board/gen860t/ioport.c
index 1fc95455ae..d8c3006a6b 100644
--- a/board/gen860t/ioport.c
+++ b/board/gen860t/ioport.c
@@ -43,10 +43,10 @@ const mpc8xx_iop_conf_t iop_conf_tab[NUM_PORTS][PORT_BITS] = {
     /*
 	 * Port A configuration
 	 * Pin	Signal					Type	Active	Initial state
-	 * PA7 	fpgaProgramLowOut		Out		Low			High
-	 * PA1 	fpgaCoreVoltageFailLow	In		Low			N/A
+	 * PA7	fpgaProgramLowOut		Out		Low			High
+	 * PA1	fpgaCoreVoltageFailLow	In		Low			N/A
 	 */
-    {	/*	    conf ppar psor pdir podr pdat pint	   function 		*/
+    {	/*	    conf ppar psor pdir podr pdat pint	   function		*/
 	/* N/A  */ { 0,   0,   0,   0,   0,   0,   0 }, /* No pin			*/
 	/* N/A  */ { 0,   0,   0,   0,   0,   0,   0 }, /* No pin			*/
 	/* PA15 */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
@@ -83,7 +83,7 @@ const mpc8xx_iop_conf_t iop_conf_tab[NUM_PORTS][PORT_BITS] = {
 	 * PB23		batteryOkSig	In			High		X
 	 * PB31		pulseCatcherClr	Out			High		0
 	 */
-	{	/*	    conf ppar psor pdir podr pdat pint 	  function			*/
+	{	/*	    conf ppar psor pdir podr pdat pint	  function			*/
 #if !defined(CONFIG_SC)
 	/* PB31 */ { 0,	  0,   0,   0,   0,   0,   0 }, /*	*/
 #else
@@ -116,7 +116,7 @@ const mpc8xx_iop_conf_t iop_conf_tab[NUM_PORTS][PORT_BITS] = {
 #if !defined(CONFIG_SC)
 	/* PB14 */ { 1,   0,   0,   0,   0,   0,   0 }  /* docBusyLow		*/
 #else
-	/* PB14 */ { 0,   0,   0,   0,   0,   0,   0 }  /* 	*/
+	/* PB14 */ { 0,   0,   0,   0,   0,   0,   0 }  /*	*/
 #endif
 	},
 
@@ -132,7 +132,7 @@ const mpc8xx_iop_conf_t iop_conf_tab[NUM_PORTS][PORT_BITS] = {
 	 * PC12		systemBitOkIn		In		High		X
 	 * PC15		selfDreqLow			In		Low			X
 	 */
-	{	/*	    conf ppar psor pdir podr pdat pint 	  function			*/
+	{	/*	    conf ppar psor pdir podr pdat pint	  function			*/
 	/* N/A	*/ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
 	/* N/A	*/ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
 	/* PC15 */ { 1,   0,   0,   0,   0,   0,   0 }, /* selfDreqLowIn	*/
@@ -141,7 +141,7 @@ const mpc8xx_iop_conf_t iop_conf_tab[NUM_PORTS][PORT_BITS] = {
 #if !defined(CONFIG_SC)
 	/* PC12 */ { 1,   0,   0,   0,   0,   0,   0 }, /* systemBitOkIn	*/
 #else
-	/* PC12 */ { 0,   0,   0,   0,   0,   0,   0 }, /* 	*/
+	/* PC12 */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
 #endif
 	/* PC11 */ { 1,   0,   0,   1,   0,   1,   0 }, /* fpgaResetLowOut	*/
 #if !defined(CONFIG_SC)
@@ -173,7 +173,7 @@ const mpc8xx_iop_conf_t iop_conf_tab[NUM_PORTS][PORT_BITS] = {
 	/*
 	 * Port D configuration
 	 */
-	{	/*	    conf ppar psor pdir podr pdat pint 	   function			*/
+	{	/*	    conf ppar psor pdir podr pdat pint	   function			*/
 	/* N/A  */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
 	/* N/A  */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
 	/* PD15 */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
diff --git a/board/gen860t/ioport.h b/board/gen860t/ioport.h
index 34a2d7b1d9..3af0bc998d 100644
--- a/board/gen860t/ioport.h
+++ b/board/gen860t/ioport.h
@@ -40,5 +40,3 @@ typedef struct {
 } mpc8xx_iop_conf_t;
 
 extern void config_mpc8xx_ioports(volatile immap_t *immr);
-
-/* vim: set ts=4 tw=78 sw=4: */
diff --git a/board/gen860t/u-boot-flashenv.lds b/board/gen860t/u-boot-flashenv.lds
index aa124f976d..bb03d3aacd 100644
--- a/board/gen860t/u-boot-flashenv.lds
+++ b/board/gen860t/u-boot-flashenv.lds
@@ -36,11 +36,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)	}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)	}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)	}
   .rela.got      : { *(.rela.got)	}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/gen860t/u-boot.lds b/board/gen860t/u-boot.lds
index ce1ffe0ca9..d33aa2ea19 100644
--- a/board/gen860t/u-boot.lds
+++ b/board/gen860t/u-boot.lds
@@ -35,11 +35,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)	}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)	}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)	}
   .rela.got      : { *(.rela.got)	}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/genietv/flash.c b/board/genietv/flash.c
index 1c1728bb49..7292c9c12f 100644
--- a/board/genietv/flash.c
+++ b/board/genietv/flash.c
@@ -131,11 +131,11 @@ void flash_print_info  (flash_info_t *info)
 
 	if (info->size >> 20) {
 	    printf ("  Size: %ld MB in %d Sectors\n",
-	    	info->size >> 20,
+		info->size >> 20,
 		info->sector_count);
 	} else {
 	    printf ("  Size: %ld KB in %d Sectors\n",
-	    	info->size >> 10,
+		info->size >> 10,
 		info->sector_count);
 	}
 
@@ -213,7 +213,7 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
 			info->flash_id += FLASH_AM040;
 			info->sector_count = 8;
 			info->size = 0x00080000;
-			break;				/* => 512Kb 		*/
+			break;				/* => 512Kb		*/
 
 		default:
 			info->flash_id = FLASH_UNKNOWN;
@@ -448,7 +448,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data)
 
 	    /* re-enable interrupts if necessary */
 	    if (flag)
-	    	enable_interrupts();
+		enable_interrupts();
 
 	    /* data polling for D7 */
 	    start = get_timer (0);
diff --git a/board/genietv/u-boot.lds b/board/genietv/u-boot.lds
index 0c6417f563..3573608d2b 100644
--- a/board/genietv/u-boot.lds
+++ b/board/genietv/u-boot.lds
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/genietv/u-boot.lds.debug b/board/genietv/u-boot.lds.debug
index 3251ec3751..8dedba8147 100644
--- a/board/genietv/u-boot.lds.debug
+++ b/board/genietv/u-boot.lds.debug
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/gth/flash.c b/board/gth/flash.c
index 41a5c50b0f..11e105e58e 100644
--- a/board/gth/flash.c
+++ b/board/gth/flash.c
@@ -75,7 +75,7 @@ unsigned long flash_init (void)
 
 	  if (size_b1 > size_b0) {
 	    printf ("## ERROR: Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n",
-	    	size_b1, size_b1<<20,size_b0, size_b0<<20);
+		size_b1, size_b1<<20,size_b0, size_b0<<20);
 
 	    flash_info[0].flash_id	= FLASH_UNKNOWN;
 	    flash_info[1].flash_id	= FLASH_UNKNOWN;
diff --git a/board/gth/u-boot.lds b/board/gth/u-boot.lds
index facb88a9fa..95f94454d0 100644
--- a/board/gth/u-boot.lds
+++ b/board/gth/u-boot.lds
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/hermes/u-boot.lds b/board/hermes/u-boot.lds
index 45e812c09d..5f5fb0d58e 100644
--- a/board/hermes/u-boot.lds
+++ b/board/hermes/u-boot.lds
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/hermes/u-boot.lds.debug b/board/hermes/u-boot.lds.debug
index f87bd0723f..41d603f7ea 100644
--- a/board/hermes/u-boot.lds.debug
+++ b/board/hermes/u-boot.lds.debug
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/hidden_dragon/speed.h b/board/hidden_dragon/speed.h
index b66393bec5..3f32a143cc 100644
--- a/board/hidden_dragon/speed.h
+++ b/board/hidden_dragon/speed.h
@@ -28,10 +28,10 @@
  * SPEED_TMR3_PS = (GCLK / (16 * SPEED_FCOUNT3)) - 1
  *
  * SPEED_FCOUNT2	timer 2 counting frequency
- * GCLK	      		CPU clock
+ * GCLK			CPU clock
  * SPEED_TMR2_PS	prescaler
  */
-#define SPEED_TMR2_PS  	(250 - 1)	/* divide by 250	*/
+#define SPEED_TMR2_PS	(250 - 1)	/* divide by 250	*/
 
 /*-----------------------------------------------------------------------
  * Timer value for PIT
diff --git a/board/hymod/hymod.c b/board/hymod/hymod.c
index 5e98e9edb7..13e60e2226 100644
--- a/board/hymod/hymod.c
+++ b/board/hymod/hymod.c
@@ -86,7 +86,7 @@ const iop_conf_t iop_conf_tab[4][32] = {
 		{   1,  0,  0,  1,  0,  0   },	/* PA03: VM ENABLE */
 		{   1,  0,  0,  0,  1,  0   },	/* PA02: VM DONE */
 		{   1,  0,  0,  1,  1,  0   },	/* PA01: VM INIT */
-		{   1,  0,  0,  1,  0,  0   } 	/* PA00: VM ~PROG */
+		{   1,  0,  0,  1,  0,  0   }	/* PA00: VM ~PROG */
 	},
 
 	/* Port B configuration */
@@ -414,10 +414,10 @@ initdram (int board_type)
 
 /* ------------------------------------------------------------------------- */
 /* miscellaneous initialisations after relocation into ram (misc_init_r)     */
-/* 									     */
+/*									     */
 /* loads the data in the main board and mezzanine board eeproms into	     */
 /* the hymod configuration struct stored in the board information area.	     */
-/* 									     */
+/*									     */
 /* if the contents of either eeprom is invalid, prompts for a serial	     */
 /* number (and an ethernet address if required) then fetches a file	     */
 /* containing information to be stored in the eeprom from the tftp server    */
diff --git a/board/hymod/u-boot.lds b/board/hymod/u-boot.lds
index 61891494d7..cb7b4ea067 100644
--- a/board/hymod/u-boot.lds
+++ b/board/hymod/u-boot.lds
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/hymod/u-boot.lds.debug b/board/hymod/u-boot.lds.debug
index 753411fcbf..c33581d250 100644
--- a/board/hymod/u-boot.lds.debug
+++ b/board/hymod/u-boot.lds.debug
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/icu862/pcmcia.c b/board/icu862/pcmcia.c
index 11de18317d..20922d8a40 100644
--- a/board/icu862/pcmcia.c
+++ b/board/icu862/pcmcia.c
@@ -223,10 +223,10 @@ int pcmcia_voltage_set(int slot, int vcc, int vpp)
 	reg  = cp->cp_pbdat;
 
 	switch(vcc) {
-		case  0: 			break;	/* Switch off		*/
+		case  0:			break;	/* Switch off		*/
 		case 33: reg &= ~TPS2205_VCC3;	break;	/* Switch on 3.3V	*/
 		case 50: reg &= ~TPS2205_VCC5;	break;	/* Switch on 5.0V	*/
-		default: 			goto done;
+		default:			goto done;
 	}
 
 	/* Checking supported voltages */
diff --git a/board/icu862/u-boot.lds b/board/icu862/u-boot.lds
index cd388d0575..be4bf7278c 100644
--- a/board/icu862/u-boot.lds
+++ b/board/icu862/u-boot.lds
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/icu862/u-boot.lds.debug b/board/icu862/u-boot.lds.debug
index 452c6c0a37..7a7a40c23e 100644
--- a/board/icu862/u-boot.lds.debug
+++ b/board/icu862/u-boot.lds.debug
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/idmr/u-boot.lds b/board/idmr/u-boot.lds
index bc83534a23..c07d023834 100644
--- a/board/idmr/u-boot.lds
+++ b/board/idmr/u-boot.lds
@@ -34,11 +34,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/imx31_litekit/lowlevel_init.S b/board/imx31_litekit/lowlevel_init.S
index 88b5261d2e..9d96db8b48 100644
--- a/board/imx31_litekit/lowlevel_init.S
+++ b/board/imx31_litekit/lowlevel_init.S
@@ -62,9 +62,9 @@ lowlevel_init:
 	REG	0x43FAC26C, 0 /* SDCLK */
 	REG	0x43FAC270, 0 /* CAS */
 	REG	0x43FAC274, 0 /* RAS */
-	REG	0x43FAC27C, 0x1000 /* CS2 	CSD0) */
+	REG	0x43FAC27C, 0x1000 /* CS2	CSD0) */
 	REG	0x43FAC284, 0 /* DQM3 */
-	REG	0x43FAC288, 0 /* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 	0x288..0x2DC) */
+	REG	0x43FAC288, 0 /* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10	0x288..0x2DC) */
 	REG	0x43FAC28C, 0
 	REG	0x43FAC290, 0
 	REG	0x43FAC294, 0
diff --git a/board/imx31_phycore/lowlevel_init.S b/board/imx31_phycore/lowlevel_init.S
index 4895b6ab3f..70f30c0cd9 100644
--- a/board/imx31_phycore/lowlevel_init.S
+++ b/board/imx31_phycore/lowlevel_init.S
@@ -63,9 +63,9 @@ lowlevel_init:
 	REG	0x43FAC26C, 0 /* SDCLK */
 	REG	0x43FAC270, 0 /* CAS */
 	REG	0x43FAC274, 0 /* RAS */
-	REG	0x43FAC27C, 0x1000 /* CS2 	CSD0) */
+	REG	0x43FAC27C, 0x1000 /* CS2	CSD0) */
 	REG	0x43FAC284, 0 /* DQM3 */
-	REG	0x43FAC288, 0 /* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 	0x288..0x2DC) */
+	REG	0x43FAC288, 0 /* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10	0x288..0x2DC) */
 	REG	0x43FAC28C, 0
 	REG	0x43FAC290, 0
 	REG	0x43FAC294, 0
diff --git a/board/innokom/flash.c b/board/innokom/flash.c
index 298acc86a3..8fc6e5bd91 100644
--- a/board/innokom/flash.c
+++ b/board/innokom/flash.c
@@ -88,8 +88,8 @@ ulong flash_init(void)
 	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
 		ulong flashbase = 0;
 		flash_info[i].flash_id =
-	  		(INTEL_MANUFACT & FLASH_VENDMASK) |
-	  		(INTEL_ID_28F128J3 & FLASH_TYPEMASK);
+			(INTEL_MANUFACT & FLASH_VENDMASK) |
+			(INTEL_ID_28F128J3 & FLASH_TYPEMASK);
 		flash_info[i].size = FLASH_BANK_SIZE;
 		flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
 		memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
@@ -350,7 +350,7 @@ static int write_word (flash_info_t *info, ulong dest, ushort data)
  * @param info:
  * @param src:	source of copy transaction
  * @param addr:	where to copy to
- * @param cnt: 	number of bytes to copy
+ * @param cnt:	number of bytes to copy
  *
  * @return	error code
  */
diff --git a/board/innokom/lowlevel_init.S b/board/innokom/lowlevel_init.S
index aa9dcba6fc..4c9f10ffbd 100644
--- a/board/innokom/lowlevel_init.S
+++ b/board/innokom/lowlevel_init.S
@@ -43,7 +43,7 @@ _TEXT_BASE:
 
 
 /*
- * 	Memory setup
+ *	Memory setup
  */
 
 .globl lowlevel_init
@@ -129,8 +129,8 @@ lowlevel_init:
 /*loop: */
 /* */
 /*   ldr	r0, =0xB0070001 */
-/*   ldr    	r1, =_LED */
-/*   str    	r0, [r1]		/  hex display */
+/*   ldr	r1, =_LED */
+/*   str	r0, [r1]		/  hex display */
 
 
 	/* ---------------------------------------------------------------- */
@@ -239,7 +239,7 @@ mem_init:
 	/* Before accessing MDREFR we need a valid DRI field, so we set     */
 	/* this to power on defaults + DRI field.                           */
 
-	ldr 	r3, 	=CFG_MDREFR_VAL
+	ldr	r3,	=CFG_MDREFR_VAL
 	ldr	r2,	=0xFFF
 	and	r3,	r3, r2
 	ldr	r4,	=0x03ca4000
diff --git a/board/integratorap/memsetup.S b/board/integratorap/memsetup.S
index dfdc7848fd..da43cb6a71 100644
--- a/board/integratorap/memsetup.S
+++ b/board/integratorap/memsetup.S
@@ -20,7 +20,7 @@
  * MA 02111-1307 USA
  */
 /*
- * 	Memory setup
+ *	Memory setup
  *      - the reset defaults are assumed sufficient
  */
 
diff --git a/board/integratorap/split_by_variant.sh b/board/integratorap/split_by_variant.sh
index 4b94d8ff8c..8c54250ec4 100755
--- a/board/integratorap/split_by_variant.sh
+++ b/board/integratorap/split_by_variant.sh
@@ -3,7 +3,7 @@
 # Set the platform defines
 # ---------------------------------------------------------
 echo -n	"/* Integrator configuration implied "	 > tmp.fil
-echo	" by Makefile target */"	 	>> tmp.fil
+echo	" by Makefile target */"		>> tmp.fil
 echo -n	"#define CONFIG_INTEGRATOR"		>> tmp.fil
 echo	" /* Integrator board */"		>> tmp.fil
 echo -n	"#define CONFIG_ARCH_INTEGRATOR"	>> tmp.fil
@@ -42,22 +42,22 @@ else
 
 	ap720t_config)
 	cpu="arm720t"
-	echo -n	"#define CONFIG_CM720T"		>> tmp.fil
-	echo	" 1 /* CPU core is ARM720T */ "	>> tmp.fil
+	echo -n	"#define CONFIG_CM720T"			>> tmp.fil
+	echo	" 1 /* CPU core is ARM720T */ "		>> tmp.fil
 	variant="Core module CM720T"
 	;;
 
 	ap922_XA10_config)
 	cpu="arm_intcm"
 	variant="unported core module CM922T_XA10"
-	echo -n	"#define CONFIG_CM922T_XA10" 		>> tmp.fil
-	echo	" 1 /* CPU core is ARM922T_XA10 */" 	>> tmp.fil
+	echo -n	"#define CONFIG_CM922T_XA10"		>> tmp.fil
+	echo	" 1 /* CPU core is ARM922T_XA10 */"	>> tmp.fil
 	;;
 
 	ap920t_config)
 	cpu="arm920t"
 	variant="Core module CM920T"
-	echo -n	"#define CONFIG_CM920T" 		>> tmp.fil
+	echo -n	"#define CONFIG_CM920T"			>> tmp.fil
 	echo	" 1 /* CPU core is ARM920T */"		>> tmp.fil
 	;;
 
@@ -89,19 +89,19 @@ then
 	echo "/* Core module undefined/not ported */"	>> tmp.fil
 	echo "#define CONFIG_ARM_INTCM 1"		>> tmp.fil
 	echo -n	"#undef CONFIG_CM_MULTIPLE_SSRAM"	>> tmp.fil
-	echo -n	"	/* CM may not have " 		>> tmp.fil
+	echo -n	"	/* CM may not have "		>> tmp.fil
 	echo	"multiple SSRAM mapping */"		>> tmp.fil
-	echo -n	"#undef CONFIG_CM_SPD_DETECT " 		>> tmp.fil
-	echo -n	" /* CM may not support SPD " 		>> tmp.fil
+	echo -n	"#undef CONFIG_CM_SPD_DETECT "		>> tmp.fil
+	echo -n	" /* CM may not support SPD "		>> tmp.fil
 	echo	"query */"				>> tmp.fil
-	echo -n	"#undef CONFIG_CM_REMAP	" 		>> tmp.fil
+	echo -n	"#undef CONFIG_CM_REMAP	"		>> tmp.fil
 	echo -n	" /* CM may not support "		>> tmp.fil
-	echo	"remapping */"	 			>> tmp.fil
-	echo -n	"#undef CONFIG_CM_INIT	" 		>> tmp.fil
+	echo	"remapping */"				>> tmp.fil
+	echo -n	"#undef CONFIG_CM_INIT	"		>> tmp.fil
 	echo -n	" /* CM may not have	"		>> tmp.fil
 	echo	"initialization reg */"			>> tmp.fil
-	echo -n	"#undef CONFIG_CM_TCRAM	" 		>> tmp.fil
-	echo	" /* CM may not have TCRAM */" 		>> tmp.fil
+	echo -n	"#undef CONFIG_CM_TCRAM	"		>> tmp.fil
+	echo	" /* CM may not have TCRAM */"		>> tmp.fil
 fi
 
 mkdir -p ${obj}include
diff --git a/board/integratorcp/flash.c b/board/integratorcp/flash.c
index 4d6eff0bf1..b653c058e1 100644
--- a/board/integratorcp/flash.c
+++ b/board/integratorcp/flash.c
@@ -73,7 +73,7 @@ OrgDef OrgIntel_28F256L18T[] = {
 };
 
 /* CP control register base address */
-#define CPCR_BASE      		0xCB000000
+#define CPCR_BASE		0xCB000000
 #define CPCR_EXTRABANK		0x8
 #define CPCR_FLASHSIZE		0x4
 #define CPCR_FLWREN		0x2
diff --git a/board/integratorcp/memsetup.S b/board/integratorcp/memsetup.S
index dfdc7848fd..da43cb6a71 100644
--- a/board/integratorcp/memsetup.S
+++ b/board/integratorcp/memsetup.S
@@ -20,7 +20,7 @@
  * MA 02111-1307 USA
  */
 /*
- * 	Memory setup
+ *	Memory setup
  *      - the reset defaults are assumed sufficient
  */
 
diff --git a/board/integratorcp/split_by_variant.sh b/board/integratorcp/split_by_variant.sh
index 79a6a9d55d..3f0a447e44 100755
--- a/board/integratorcp/split_by_variant.sh
+++ b/board/integratorcp/split_by_variant.sh
@@ -3,11 +3,11 @@
 # Set the platform defines
 # ---------------------------------------------------------
 echo -n "/* Integrator configuration implied "   > tmp.fil
-echo    " by Makefile target */"   		>> tmp.fil
-echo -n "#define CONFIG_INTEGRATOR"  		>> tmp.fil
-echo	 " /* Integrator board */"  		>> tmp.fil
+echo    " by Makefile target */"		>> tmp.fil
+echo -n "#define CONFIG_INTEGRATOR"		>> tmp.fil
+echo	 " /* Integrator board */"		>> tmp.fil
 echo -n "#define CONFIG_ARCH_CINTEGRATOR"	>> tmp.fil
-echo     " 1 /* Integrator/CP   */"  		>> tmp.fil
+echo     " 1 /* Integrator/CP   */"		>> tmp.fil
 
 cpu="arm_intcm"
 variant="unknown core module"
@@ -36,14 +36,14 @@ else
 	cp922_XA10_config)
 	cpu="arm_intcm"
 	variant="unported core module CM922T_XA10"
-	echo -n "#define CONFIG_CM922T_XA10" 		>> tmp.fil
-	echo    " 1 /* CPU core is ARM922T_XA10 */" 	>> tmp.fil
+	echo -n "#define CONFIG_CM922T_XA10"		>> tmp.fil
+	echo    " 1 /* CPU core is ARM922T_XA10 */"	>> tmp.fil
 	;;
 
 	cp920t_config)
 	cpu="arm920t"
 	variant="Core module CM920T"
-	echo -n "#define CONFIG_CM920T" 		>> tmp.fil
+	echo -n "#define CONFIG_CM920T"			>> tmp.fil
 	echo    " 1 /* CPU core is ARM920T */"		>> tmp.fil
 	;;
 
@@ -82,21 +82,21 @@ fi
 if [ "$cpu" = "arm_intcm" ]
 then
 	echo "/* Core module undefined/not ported */"	>> tmp.fil
-	echo "#define CONFIG_ARM_INTCM 1"  		>> tmp.fil
+	echo "#define CONFIG_ARM_INTCM 1"		>> tmp.fil
 	echo -n "#undef CONFIG_CM_MULTIPLE_SSRAM"	>> tmp.fil
-	echo -n "  /* CM may not have " 		>> tmp.fil
-	echo    "multiple SSRAM mapping */"  		>> tmp.fil
-	echo -n "#undef CONFIG_CM_SPD_DETECT " 		>> tmp.fil
-	echo -n " /* CM may not support SPD " 		>> tmp.fil
-	echo    "query */"    				>> tmp.fil
-	echo -n "#undef CONFIG_CM_REMAP  " 		>> tmp.fil
-	echo -n " /* CM may not support "  		>> tmp.fil
-	echo    "remapping */"   			>> tmp.fil
-	echo -n "#undef CONFIG_CM_INIT  " 		>> tmp.fil
-	echo -n " /* CM may not have  "  		>> tmp.fil
-	echo    "initialization reg */"  		>> tmp.fil
-	echo -n "#undef CONFIG_CM_TCRAM  " 		>> tmp.fil
-	echo    " /* CM may not have TCRAM */" 		>> tmp.fil
+	echo -n "  /* CM may not have "			>> tmp.fil
+	echo    "multiple SSRAM mapping */"		>> tmp.fil
+	echo -n "#undef CONFIG_CM_SPD_DETECT "		>> tmp.fil
+	echo -n " /* CM may not support SPD "		>> tmp.fil
+	echo    "query */"				>> tmp.fil
+	echo -n "#undef CONFIG_CM_REMAP  "		>> tmp.fil
+	echo -n " /* CM may not support "		>> tmp.fil
+	echo    "remapping */"				>> tmp.fil
+	echo -n "#undef CONFIG_CM_INIT  "		>> tmp.fil
+	echo -n " /* CM may not have  "			>> tmp.fil
+	echo    "initialization reg */"			>> tmp.fil
+	echo -n "#undef CONFIG_CM_TCRAM  "		>> tmp.fil
+	echo    " /* CM may not have TCRAM */"		>> tmp.fil
 fi
 
 mkdir -p ${obj}include
diff --git a/board/ip860/u-boot.lds b/board/ip860/u-boot.lds
index 6556ed5a69..ef88297930 100644
--- a/board/ip860/u-boot.lds
+++ b/board/ip860/u-boot.lds
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/ip860/u-boot.lds.debug b/board/ip860/u-boot.lds.debug
index f571350922..ad685e6f8d 100644
--- a/board/ip860/u-boot.lds.debug
+++ b/board/ip860/u-boot.lds.debug
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/ivm/u-boot.lds b/board/ivm/u-boot.lds
index bbd93ee42e..d7f360f3bb 100644
--- a/board/ivm/u-boot.lds
+++ b/board/ivm/u-boot.lds
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)	}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)	}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)	}
   .rela.got      : { *(.rela.got)	}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/ivm/u-boot.lds.debug b/board/ivm/u-boot.lds.debug
index c6f2ad533f..995fc83270 100644
--- a/board/ivm/u-boot.lds.debug
+++ b/board/ivm/u-boot.lds.debug
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)	}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)	}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)	}
   .rela.got      : { *(.rela.got)	}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/ixdp425/flash.c b/board/ixdp425/flash.c
index 1d958c8c19..704dea8637 100644
--- a/board/ixdp425/flash.c
+++ b/board/ixdp425/flash.c
@@ -35,19 +35,19 @@ flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips        */
 #define FLASH_PORT_WIDTH16
 
 #ifdef FLASH_PORT_WIDTH16
-#define FLASH_PORT_WIDTH		ushort
-#define FLASH_PORT_WIDTHV		vu_short
-#define SWAP(x)               		x
+#define FLASH_PORT_WIDTH	ushort
+#define FLASH_PORT_WIDTHV	vu_short
+#define SWAP(x)			x
 #else
-#define FLASH_PORT_WIDTH		ulong
-#define FLASH_PORT_WIDTHV		vu_long
-#define SWAP(x)               		__swab32(x)
+#define FLASH_PORT_WIDTH	ulong
+#define FLASH_PORT_WIDTHV	vu_long
+#define SWAP(x)			__swab32(x)
 #endif
 
-#define FPW	   FLASH_PORT_WIDTH
-#define FPWV   FLASH_PORT_WIDTHV
+#define FPW	FLASH_PORT_WIDTH
+#define FPWV	FLASH_PORT_WIDTHV
 
-#define mb() __asm__ __volatile__ ("" : : : "memory")
+#define mb()	__asm__ __volatile__ ("" : : : "memory")
 
 /*-----------------------------------------------------------------------
  * Functions
diff --git a/board/jse/u-boot.lds b/board/jse/u-boot.lds
index 96101ecccb..7e060cbfd0 100644
--- a/board/jse/u-boot.lds
+++ b/board/jse/u-boot.lds
@@ -38,11 +38,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/korat/u-boot-F7FC.lds b/board/korat/u-boot-F7FC.lds
index 174060e11b..6dccf958ff 100644
--- a/board/korat/u-boot-F7FC.lds
+++ b/board/korat/u-boot-F7FC.lds
@@ -43,11 +43,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/korat/u-boot.lds b/board/korat/u-boot.lds
index da2a400b77..b20fb1c0a2 100644
--- a/board/korat/u-boot.lds
+++ b/board/korat/u-boot.lds
@@ -43,11 +43,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/kup/common/pcmcia.c b/board/kup/common/pcmcia.c
index def38f1c68..8f0cf17b98 100644
--- a/board/kup/common/pcmcia.c
+++ b/board/kup/common/pcmcia.c
@@ -188,7 +188,7 @@ int pcmcia_voltage_set(int slot, int vcc, int vpp)
 	cp->cp_pbdat |=  KUP4K_PCMCIA_B_3V3; /* active low */
 
 	switch(vcc) {
-		case  0: 		break;
+		case  0:		break;
 		case 33:
 			cp->cp_pbdat &= ~KUP4K_PCMCIA_B_3V3;
 			debug ("PCMCIA powered at 3.3V\n");
diff --git a/board/kup/kup4k/u-boot.lds b/board/kup/kup4k/u-boot.lds
index e0ae224238..2e9169c163 100644
--- a/board/kup/kup4k/u-boot.lds
+++ b/board/kup/kup4k/u-boot.lds
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)	}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)	}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)	}
   .rela.got      : { *(.rela.got)	}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/kup/kup4k/u-boot.lds.debug b/board/kup/kup4k/u-boot.lds.debug
index 4942c42941..f6d1537639 100644
--- a/board/kup/kup4k/u-boot.lds.debug
+++ b/board/kup/kup4k/u-boot.lds.debug
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/kup/kup4x/u-boot.lds b/board/kup/kup4x/u-boot.lds
index e0ae224238..2e9169c163 100644
--- a/board/kup/kup4x/u-boot.lds
+++ b/board/kup/kup4x/u-boot.lds
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)	}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)	}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)	}
   .rela.got      : { *(.rela.got)	}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/kup/kup4x/u-boot.lds.debug b/board/kup/kup4x/u-boot.lds.debug
index 4942c42941..f6d1537639 100644
--- a/board/kup/kup4x/u-boot.lds.debug
+++ b/board/kup/kup4x/u-boot.lds.debug
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/lantec/u-boot.lds b/board/lantec/u-boot.lds
index 688846b130..2d266434f4 100644
--- a/board/lantec/u-boot.lds
+++ b/board/lantec/u-boot.lds
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/lantec/u-boot.lds.debug b/board/lantec/u-boot.lds.debug
index a39ee9d069..7dc4408c67 100644
--- a/board/lantec/u-boot.lds.debug
+++ b/board/lantec/u-boot.lds.debug
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/linkstation/avr.c b/board/linkstation/avr.c
index 68bc5450a6..a689c6330f 100644
--- a/board/linkstation/avr.c
+++ b/board/linkstation/avr.c
@@ -35,7 +35,7 @@
 /* LED commands */
 #define PWRBLINKSTRT		'['		/* Blink power LED	*/
 #define PWRBLINKSTOP		'Z'		/* Solid power LED	*/
-#define HDDLEDON		'W'		/* HDD LED on 		*/
+#define HDDLEDON		'W'		/* HDD LED on		*/
 #define HDDLEDOFF		'V'		/* HDD LED off		*/
 #define HDDBLINKSTRT		'Y'		/* HDD LED start blink	*/
 #define HDDBLINKSTOP		'X'		/* HDD LED stop blink	*/
@@ -57,7 +57,7 @@ static char *consoles[] = {
 	"nc",
 #endif
 };
-#define MAX_CONS_CHOICE 	(sizeof(consoles)/sizeof(char *))
+#define MAX_CONS_CHOICE		(sizeof(consoles)/sizeof(char *))
 
 #if !defined(CONFIG_NETCONSOLE)
 #define DEF_CONS_CHOICE		0
diff --git a/board/logodl/flash.c b/board/logodl/flash.c
index a9477314dc..0807b80913 100644
--- a/board/logodl/flash.c
+++ b/board/logodl/flash.c
@@ -593,7 +593,7 @@ int bad_write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
  * @param info:
  * @param src:	source of copy transaction
  * @param addr:	where to copy to
- * @param cnt: 	number of bytes to copy
+ * @param cnt:	number of bytes to copy
  *
  * @return	error code
  */
diff --git a/board/logodl/lowlevel_init.S b/board/logodl/lowlevel_init.S
index aa9dcba6fc..4c9f10ffbd 100644
--- a/board/logodl/lowlevel_init.S
+++ b/board/logodl/lowlevel_init.S
@@ -43,7 +43,7 @@ _TEXT_BASE:
 
 
 /*
- * 	Memory setup
+ *	Memory setup
  */
 
 .globl lowlevel_init
@@ -129,8 +129,8 @@ lowlevel_init:
 /*loop: */
 /* */
 /*   ldr	r0, =0xB0070001 */
-/*   ldr    	r1, =_LED */
-/*   str    	r0, [r1]		/  hex display */
+/*   ldr	r1, =_LED */
+/*   str	r0, [r1]		/  hex display */
 
 
 	/* ---------------------------------------------------------------- */
@@ -239,7 +239,7 @@ mem_init:
 	/* Before accessing MDREFR we need a valid DRI field, so we set     */
 	/* this to power on defaults + DRI field.                           */
 
-	ldr 	r3, 	=CFG_MDREFR_VAL
+	ldr	r3,	=CFG_MDREFR_VAL
 	ldr	r2,	=0xFFF
 	and	r3,	r3, r2
 	ldr	r4,	=0x03ca4000
diff --git a/board/lpc2292sodimm/lowlevel_init.S b/board/lpc2292sodimm/lowlevel_init.S
index a0e9747a9b..4e8eb893e2 100644
--- a/board/lpc2292sodimm/lowlevel_init.S
+++ b/board/lpc2292sodimm/lowlevel_init.S
@@ -23,19 +23,19 @@
 
 /* some parameters for the board */
 /* setting up the memory */
-#define 	SRAM_START 	0x40000000
-#define 	SRAM_SIZE	0x00004000
-#define   BCFG0_VALUE 0x1000ffef
-#define   BCFG1_VALUE 0x10001C61
+#define	SRAM_START	0x40000000
+#define	SRAM_SIZE	0x00004000
+#define BCFG0_VALUE	0x1000ffef
+#define BCFG1_VALUE	0x10001C61
 
 _TEXT_BASE:
 	.word	TEXT_BASE
 MEMMAP_ADR:
 	.word	MEMMAP
 BCFG0_ADR:
-  .word BCFG0
+	.word	BCFG0
 _BCFG0_VALUE:
-  .word BCFG0_VALUE
+	.word	BCFG0_VALUE
 BCFG1_ADR:
 	.word	BCFG1
 _BCFG1_VALUE:
diff --git a/board/lpd7a40x/lowlevel_init.S b/board/lpd7a40x/lowlevel_init.S
index b3ed55ce35..780b931bed 100644
--- a/board/lpd7a40x/lowlevel_init.S
+++ b/board/lpd7a40x/lowlevel_init.S
@@ -38,7 +38,7 @@
 #define BCRX_IDCY_SHIFT	(0)
 
 /* Bank0 Async Flash */
-#define BCR0	   	(0x80002000)
+#define BCR0		(0x80002000)
 #define BCR0_FLASH	(BCRX_MW_32 | (0x08<<BCRX_WST2_SHIFT) | (0x0E<<BCRX_WST1_SHIFT))
 
 /* Bank1 Open */
@@ -55,7 +55,7 @@
 /* Bank5 PC Card2 */
 
 /* Bank6 CPLD IO Controller Peripherals (slow) */
-#define BCR6	 	(0x80002018)
+#define BCR6		(0x80002018)
 #define BCR6_CPLD_SLOW	(BCRX_DEFAULT | BCRX_MW_16)
 
 /* Bank7 CPLD IO Controller Peripherals (fast) */
diff --git a/board/lubbock/lowlevel_init.S b/board/lubbock/lowlevel_init.S
index 15276e89d0..2a9bcbf494 100644
--- a/board/lubbock/lowlevel_init.S
+++ b/board/lubbock/lowlevel_init.S
@@ -40,7 +40,7 @@ DRAM_SIZE:  .long   CFG_DRAM_SIZE
 
 
 /*
- * 	Memory setup
+ *	Memory setup
  */
 
 .globl lowlevel_init
diff --git a/board/lwmon/pcmcia.c b/board/lwmon/pcmcia.c
index ebca7a2ca1..8825bd9714 100644
--- a/board/lwmon/pcmcia.c
+++ b/board/lwmon/pcmcia.c
@@ -204,10 +204,10 @@ int pcmcia_voltage_set(int slot, int vcc, int vpp)
 
 	val = 0;
 	switch(vcc) {
-	case  0: 			break;
+	case  0:			break;
 	case 33: val = MAX1604_VCC_35;	break;
-	case 50: 			break;
-	default: 			goto done;
+	case 50:			break;
+	default:			goto done;
 	}
 
 	/* Checking supported voltages */
diff --git a/board/lwmon/u-boot.lds b/board/lwmon/u-boot.lds
index 93015712e5..bc1ea73723 100644
--- a/board/lwmon/u-boot.lds
+++ b/board/lwmon/u-boot.lds
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)	}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)	}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)	}
   .rela.got      : { *(.rela.got)	}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/lwmon/u-boot.lds.debug b/board/lwmon/u-boot.lds.debug
index 44bae70884..2ee8237451 100644
--- a/board/lwmon/u-boot.lds.debug
+++ b/board/lwmon/u-boot.lds.debug
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)	}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)	}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)	}
   .rela.got      : { *(.rela.got)	}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/lwmon5/u-boot.lds b/board/lwmon5/u-boot.lds
index da2a400b77..b20fb1c0a2 100644
--- a/board/lwmon5/u-boot.lds
+++ b/board/lwmon5/u-boot.lds
@@ -43,11 +43,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/m5271evb/u-boot.lds b/board/m5271evb/u-boot.lds
index bc83534a23..c07d023834 100644
--- a/board/m5271evb/u-boot.lds
+++ b/board/m5271evb/u-boot.lds
@@ -34,11 +34,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/m5272c3/u-boot.lds b/board/m5272c3/u-boot.lds
index 884ff2de83..8420c91a7c 100644
--- a/board/m5272c3/u-boot.lds
+++ b/board/m5272c3/u-boot.lds
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/m5282evb/u-boot.lds b/board/m5282evb/u-boot.lds
index eea3230f9a..dd2666b764 100644
--- a/board/m5282evb/u-boot.lds
+++ b/board/m5282evb/u-boot.lds
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/mbx8xx/u-boot.lds b/board/mbx8xx/u-boot.lds
index 3ccdd3390a..2998e835ea 100644
--- a/board/mbx8xx/u-boot.lds
+++ b/board/mbx8xx/u-boot.lds
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/mbx8xx/u-boot.lds.debug b/board/mbx8xx/u-boot.lds.debug
index 96c4e22c24..fd2245f57b 100644
--- a/board/mbx8xx/u-boot.lds.debug
+++ b/board/mbx8xx/u-boot.lds.debug
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/mgsuvd/u-boot.lds b/board/mgsuvd/u-boot.lds
index 7ab29ef0f8..8c46e4677f 100644
--- a/board/mgsuvd/u-boot.lds
+++ b/board/mgsuvd/u-boot.lds
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)	}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)	}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)	}
   .rela.got      : { *(.rela.got)	}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/ml2/u-boot.lds b/board/ml2/u-boot.lds
index 9a05a61651..c9406ad7f0 100644
--- a/board/ml2/u-boot.lds
+++ b/board/ml2/u-boot.lds
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/ml2/u-boot.lds.debug b/board/ml2/u-boot.lds.debug
index 88dcaf91bf..0552994f40 100644
--- a/board/ml2/u-boot.lds.debug
+++ b/board/ml2/u-boot.lds.debug
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/mousse/u-boot.lds b/board/mousse/u-boot.lds
index 4e3b89d184..86a1d85ed5 100644
--- a/board/mousse/u-boot.lds
+++ b/board/mousse/u-boot.lds
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/mousse/u-boot.lds.ram b/board/mousse/u-boot.lds.ram
index 68c4ccaacf..46b98a04a8 100644
--- a/board/mousse/u-boot.lds.ram
+++ b/board/mousse/u-boot.lds.ram
@@ -24,9 +24,9 @@
 OUTPUT_ARCH(powerpc)
 
 MEMORY {
- 	ram  (!rx) : org = 0x00000000 , LENGTH = 8M
- 	code (!rx) : org = 0x00002000 , LENGTH = (4M - 0x2000)
- 	rom   (rx) : org = 0xfff00000 , LENGTH = 512K
+	ram  (!rx) : org = 0x00000000 , LENGTH = 8M
+	code (!rx) : org = 0x00002000 , LENGTH = (4M - 0x2000)
+	rom   (rx) : org = 0xfff00000 , LENGTH = 512K
 }
 
 SECTIONS
diff --git a/board/mousse/u-boot.lds.rom b/board/mousse/u-boot.lds.rom
index 952bf01813..3ba7c3c9a4 100644
--- a/board/mousse/u-boot.lds.rom
+++ b/board/mousse/u-boot.lds.rom
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/mpc8540eval/u-boot.lds b/board/mpc8540eval/u-boot.lds
index ef4ea97168..dadfc7dee5 100644
--- a/board/mpc8540eval/u-boot.lds
+++ b/board/mpc8540eval/u-boot.lds
@@ -35,11 +35,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/mpl/common/common_util.c b/board/mpl/common/common_util.c
index 785d204696..11d4345125 100644
--- a/board/mpl/common/common_util.c
+++ b/board/mpl/common/common_util.c
@@ -219,7 +219,7 @@ mpl_prg_image(uchar *ld_addr)
 		uchar *buf;
 		/* reserve space for uncompressed image */
 		if ((buf = malloc(IMAGE_SIZE)) == NULL) {
-		    	puts("Insufficient space for decompression\n");
+			puts("Insufficient space for decompression\n");
 			return 1;
 		}
 
@@ -461,7 +461,7 @@ void show_stdio_dev(void)
 
 int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
- 	ulong size,src,ld_addr;
+	ulong size,src,ld_addr;
 	int result;
 #if !defined(CONFIG_PATI)
 	backup_t back;
@@ -473,11 +473,11 @@ int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	{
 #if defined(CONFIG_CMD_FDC)
 		if (strcmp(argv[2], "floppy") == 0) {
- 			char *local_args[3];
+			char *local_args[3];
 			extern int do_fdcboot (cmd_tbl_t *, int, int, char *[]);
 			puts("\nupdating bootloader image from floppy\n");
 			local_args[0] = argv[0];
-	    		if(argc==4) {
+			if(argc==4) {
 				local_args[1] = argv[3];
 				local_args[2] = NULL;
 				ld_addr=simple_strtoul(argv[3], NULL, 16);
@@ -493,7 +493,7 @@ int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 		}
 #endif
 		if (strcmp(argv[2], "mem") == 0) {
-	    		if(argc==4) {
+			if(argc==4) {
 				ld_addr=simple_strtoul(argv[3], NULL, 16);
 			}
 			else {
@@ -524,7 +524,7 @@ int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	    src&=0xfff00000;
 	    size=0;
 	    do {
-	    	size++;
+		size++;
 			printf("\n\nPass %ld\n",size);
 			mem_test(CFG_MEMTEST_START,src,1);
 			if(ctrlc())
@@ -538,7 +538,7 @@ int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 #if !defined(CONFIG_PATI)
 	if (strcmp(argv[1], "clearenvvalues") == 0)
 	{
- 		if (strcmp(argv[2], "yes") == 0)
+		if (strcmp(argv[2], "yes") == 0)
 		{
 			clear_env_values();
 			return 0;
diff --git a/board/mpl/common/common_util.h b/board/mpl/common/common_util.h
index d4b1f68dfa..46573da1f5 100644
--- a/board/mpl/common/common_util.h
+++ b/board/mpl/common/common_util.h
@@ -26,7 +26,7 @@
 
 typedef struct {
 	char signature[4];
-	char serial_name[17]; 	/* "MIP405_1000xxxxx" */
+	char serial_name[17];	/* "MIP405_1000xxxxx" */
 	char eth_addr[21];	/* "00:60:C2:0a:00:00" */
 } backup_t;
 
diff --git a/board/mpl/common/flash.c b/board/mpl/common/flash.c
index 6f53192ac7..a437dab1c6 100644
--- a/board/mpl/common/flash.c
+++ b/board/mpl/common/flash.c
@@ -398,7 +398,7 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
 		return (0);			/* no or unknown flash	*/
 	}
 	value = addr2[1];			/* device ID		*/
-	/*	printf("Device value %x\n",value); 		    */
+	/*	printf("Device value %x\n",value);		    */
 	switch (value) {
 	case (FLASH_WORD_SIZE)AMD_ID_F040B:
 		info->flash_id += FLASH_AM040;
diff --git a/board/mpl/common/kbd.c b/board/mpl/common/kbd.c
index 7724e241d1..931ed43083 100644
--- a/board/mpl/common/kbd.c
+++ b/board/mpl/common/kbd.c
@@ -53,63 +53,63 @@ void enable_8259A_irq(unsigned int irq);
 #define KBD_STAT_KOBF		0x01
 #define KBD_STAT_IBF		0x02
 #define KBD_STAT_SYS		0x04
-#define KBD_STAT_CD			0x08
+#define KBD_STAT_CD		0x08
 #define KBD_STAT_LOCK		0x10
 #define KBD_STAT_MOBF		0x20
-#define KBD_STAT_TI_OUT	0x40
-#define KBD_STAT_PARERR	0x80
+#define KBD_STAT_TI_OUT		0x40
+#define KBD_STAT_PARERR		0x80
 
-#define KBD_INIT_TIMEOUT 1000		/* Timeout in ms for initializing the keyboard */
-#define KBC_TIMEOUT 250			/* Timeout in ms for sending to keyboard controller */
-#define KBD_TIMEOUT 2000		/* Timeout in ms for keyboard command acknowledge */
+#define KBD_INIT_TIMEOUT	1000	/* Timeout in ms for initializing the keyboard */
+#define KBC_TIMEOUT		250	/* Timeout in ms for sending to keyboard controller */
+#define KBD_TIMEOUT		2000	/* Timeout in ms for keyboard command acknowledge */
 /*
  *	Keyboard Controller Commands
  */
 
-#define KBD_CCMD_READ_MODE			0x20	/* Read mode bits */
-#define KBD_CCMD_WRITE_MODE			0x60	/* Write mode bits */
-#define KBD_CCMD_GET_VERSION		0xA1	/* Get controller version */
+#define KBD_CCMD_READ_MODE	0x20	/* Read mode bits */
+#define KBD_CCMD_WRITE_MODE	0x60	/* Write mode bits */
+#define KBD_CCMD_GET_VERSION	0xA1	/* Get controller version */
 #define KBD_CCMD_MOUSE_DISABLE	0xA7	/* Disable mouse interface */
-#define KBD_CCMD_MOUSE_ENABLE		0xA8	/* Enable mouse interface */
-#define KBD_CCMD_TEST_MOUSE			0xA9	/* Mouse interface test */
-#define KBD_CCMD_SELF_TEST			0xAA	/* Controller self test */
-#define KBD_CCMD_KBD_TEST				0xAB	/* Keyboard interface test */
-#define KBD_CCMD_KBD_DISABLE		0xAD	/* Keyboard interface disable */
-#define KBD_CCMD_KBD_ENABLE			0xAE	/* Keyboard interface enable */
+#define KBD_CCMD_MOUSE_ENABLE	0xA8	/* Enable mouse interface */
+#define KBD_CCMD_TEST_MOUSE	0xA9	/* Mouse interface test */
+#define KBD_CCMD_SELF_TEST	0xAA	/* Controller self test */
+#define KBD_CCMD_KBD_TEST	0xAB	/* Keyboard interface test */
+#define KBD_CCMD_KBD_DISABLE	0xAD	/* Keyboard interface disable */
+#define KBD_CCMD_KBD_ENABLE	0xAE	/* Keyboard interface enable */
 #define KBD_CCMD_WRITE_AUX_OBUF	0xD3    /* Write to output buffer as if
 					   initiated by the auxiliary device */
-#define KBD_CCMD_WRITE_MOUSE		0xD4	/* Write the following byte to the mouse */
+#define KBD_CCMD_WRITE_MOUSE	0xD4	/* Write the following byte to the mouse */
 
 /*
  *	Keyboard Commands
  */
 
-#define KBD_CMD_SET_LEDS				0xED	/* Set keyboard leds */
-#define KBD_CMD_SET_RATE				0xF3	/* Set typematic rate */
-#define KBD_CMD_ENABLE					0xF4	/* Enable scanning */
-#define KBD_CMD_DISABLE					0xF5	/* Disable scanning */
-#define KBD_CMD_RESET						0xFF	/* Reset */
+#define KBD_CMD_SET_LEDS	0xED	/* Set keyboard leds */
+#define KBD_CMD_SET_RATE	0xF3	/* Set typematic rate */
+#define KBD_CMD_ENABLE		0xF4	/* Enable scanning */
+#define KBD_CMD_DISABLE		0xF5	/* Disable scanning */
+#define KBD_CMD_RESET		0xFF	/* Reset */
 
 /*
  *	Keyboard Replies
  */
 
-#define KBD_REPLY_POR						0xAA	/* Power on reset */
-#define KBD_REPLY_ACK						0xFA	/* Command ACK */
-#define KBD_REPLY_RESEND				0xFE	/* Command NACK, send the cmd again */
+#define KBD_REPLY_POR		0xAA	/* Power on reset */
+#define KBD_REPLY_ACK		0xFA	/* Command ACK */
+#define KBD_REPLY_RESEND	0xFE	/* Command NACK, send the cmd again */
 
 /*
  *	Status Register Bits
  */
 
-#define KBD_STAT_OBF 						0x01	/* Keyboard output buffer full */
-#define KBD_STAT_IBF 						0x02	/* Keyboard input buffer full */
-#define KBD_STAT_SELFTEST				0x04	/* Self test successful */
-#define KBD_STAT_CMD						0x08	/* Last write was a command write (0=data) */
-#define KBD_STAT_UNLOCKED				0x10	/* Zero if keyboard locked */
-#define KBD_STAT_MOUSE_OBF			0x20	/* Mouse output buffer full */
-#define KBD_STAT_GTO 						0x40	/* General receive/xmit timeout */
-#define KBD_STAT_PERR 					0x80	/* Parity error */
+#define KBD_STAT_OBF		0x01	/* Keyboard output buffer full */
+#define KBD_STAT_IBF		0x02	/* Keyboard input buffer full */
+#define KBD_STAT_SELFTEST	0x04	/* Self test successful */
+#define KBD_STAT_CMD		0x08	/* Last write was a command write (0=data) */
+#define KBD_STAT_UNLOCKED	0x10	/* Zero if keyboard locked */
+#define KBD_STAT_MOUSE_OBF	0x20	/* Mouse output buffer full */
+#define KBD_STAT_GTO		0x40	/* General receive/xmit timeout */
+#define KBD_STAT_PERR		0x80	/* Parity error */
 
 #define AUX_STAT_OBF (KBD_STAT_OBF | KBD_STAT_MOUSE_OBF)
 
@@ -117,24 +117,24 @@ void enable_8259A_irq(unsigned int irq);
  *	Controller Mode Register Bits
  */
 
-#define KBD_MODE_KBD_INT				0x01	/* Keyboard data generate IRQ1 */
-#define KBD_MODE_MOUSE_INT			0x02	/* Mouse data generate IRQ12 */
-#define KBD_MODE_SYS 						0x04	/* The system flag (?) */
-#define KBD_MODE_NO_KEYLOCK			0x08	/* The keylock doesn't affect the keyboard if set */
-#define KBD_MODE_DISABLE_KBD		0x10	/* Disable keyboard interface */
+#define KBD_MODE_KBD_INT	0x01	/* Keyboard data generate IRQ1 */
+#define KBD_MODE_MOUSE_INT	0x02	/* Mouse data generate IRQ12 */
+#define KBD_MODE_SYS		0x04	/* The system flag (?) */
+#define KBD_MODE_NO_KEYLOCK	0x08	/* The keylock doesn't affect the keyboard if set */
+#define KBD_MODE_DISABLE_KBD	0x10	/* Disable keyboard interface */
 #define KBD_MODE_DISABLE_MOUSE	0x20	/* Disable mouse interface */
-#define KBD_MODE_KCC 						0x40	/* Scan code conversion to PC format */
-#define KBD_MODE_RFU						0x80
+#define KBD_MODE_KCC		0x40	/* Scan code conversion to PC format */
+#define KBD_MODE_RFU		0x80
 
 
-#define KDB_DATA_PORT			0x60
+#define KDB_DATA_PORT		0x60
 #define KDB_COMMAND_PORT	0x64
 
-#define 	LED_SCR		0x01	/* scroll lock led */
-#define 	LED_CAP		0x04	/* caps lock led */
-#define 	LED_NUM		0x02	/* num lock led */
+#define	LED_SCR			0x01	/* scroll lock led */
+#define	LED_CAP			0x04	/* caps lock led */
+#define	LED_NUM			0x02	/* num lock led */
 
-#define 	KBD_BUFFER_LEN 0x20  /* size of the keyboardbuffer */
+#define	KBD_BUFFER_LEN		0x20	/* size of the keyboardbuffer */
 
 
 static volatile char kbd_buffer[KBD_BUFFER_LEN];
@@ -197,8 +197,7 @@ int isa_kbd_init(void)
 		irq_install_handler(25, (interrupt_handler_t *)handle_isa_int, NULL);
 		isa_irq_install_handler(KBD_INTERRUPT, (interrupt_handler_t *)kbd_interrupt, NULL);
 		return (1);
-	}
-	else {
+	} else {
 		printf("%s\n",result);
 		return (-1);
 	}
@@ -216,20 +215,20 @@ int overwrite_console (void)
 int drv_isa_kbd_init (void)
 {
 	int error;
-  	device_t kbddev ;
+	device_t kbddev ;
 	char *stdinname  = getenv ("stdin");
 
 	if(isa_kbd_init()==-1)
 		return -1;
-  	memset (&kbddev, 0, sizeof(kbddev));
-  	strcpy(kbddev.name, DEVNAME);
-  	kbddev.flags =  DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM;
-  	kbddev.putc = NULL ;
+	memset (&kbddev, 0, sizeof(kbddev));
+	strcpy(kbddev.name, DEVNAME);
+	kbddev.flags =  DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM;
+	kbddev.putc = NULL ;
 	kbddev.puts = NULL ;
 	kbddev.getc = kbd_getc ;
 	kbddev.tstc = kbd_testc ;
 
- 	error = device_register (&kbddev);
+	error = device_register (&kbddev);
 	if(error==0) {
 		/* check if this is the standard input device */
 		if(strcmp(stdinname,DEVNAME)==0) {
@@ -313,106 +312,106 @@ void kbd_set_leds(void)
 }
 
 
-void handle_keyboard_event(unsigned char scancode)
+void handle_keyboard_event (unsigned char scancode)
 {
 	unsigned char keycode;
 
 	/*  Convert scancode to keycode */
-	PRINTF("scancode %x\n",scancode);
-	if(scancode==0xe0) {
-		e0=1; /* special charakters */
+	PRINTF ("scancode %x\n", scancode);
+	if (scancode == 0xe0) {
+		e0 = 1;		/* special charakters */
 		return;
 	}
-	if(e0==1) {
-		e0=0; /* delete flag */
-		if(!(	((scancode&0x7F)==0x38)|| /* the right ctrl key */
-					((scancode&0x7F)==0x1D)|| /* the right alt key */
-					((scancode&0x7F)==0x35)||	/* the right '/' key */
-					((scancode&0x7F)==0x1C) ))  /* the right enter key */
+	if (e0 == 1) {
+		e0 = 0;		/* delete flag */
+		if (!(((scancode & 0x7F) == 0x38) ||	/* the right ctrl key */
+		      ((scancode & 0x7F) == 0x1D) ||	/* the right alt key */
+		      ((scancode & 0x7F) == 0x35) ||	/* the right '/' key */
+		      ((scancode & 0x7F) == 0x1C)))
+			/* the right enter key */
 			/* we swallow unknown e0 codes */
 			return;
 	}
 	/* special cntrl keys */
-	switch(scancode)
-	{
-		case 0x2A:
-		case 0x36: /* shift pressed */
-			shift=1;
-			return; /* do nothing else */
-		case 0xAA:
-		case 0xB6: /* shift released */
-			shift=0;
-			return; /* do nothing else */
-		case 0x38: /* alt pressed */
-			alt=1;
-			return; /* do nothing else */
-		case 0xB8: /* alt released */
-			alt=0;
-			return; /* do nothing else */
-		case 0x1d: /* ctrl pressed */
-			ctrl=1;
-			return; /* do nothing else */
-		case 0x9d: /* ctrl released */
-			ctrl=0;
-			return; /* do nothing else */
-		case 0x46: /* scrollock pressed */
-			scroll_lock=~scroll_lock;
-			kbd_set_leds();
-			return; /* do nothing else */
-		case 0x3A: /* capslock pressed */
-			caps_lock=~caps_lock;
-			kbd_set_leds();
-			return;
-		case 0x45: /* numlock pressed */
-			num_lock=~num_lock;
-			kbd_set_leds();
-			return;
-		case 0xC6: /* scroll lock released */
-		case 0xC5: /* num lock released */
-		case 0xBA: /* caps lock released */
-			return; /* just swallow */
+	switch (scancode) {
+	case 0x2A:
+	case 0x36:		/* shift pressed */
+		shift = 1;
+		return;		/* do nothing else */
+	case 0xAA:
+	case 0xB6:		/* shift released */
+		shift = 0;
+		return;		/* do nothing else */
+	case 0x38:		/* alt pressed */
+		alt = 1;
+		return;		/* do nothing else */
+	case 0xB8:		/* alt released */
+		alt = 0;
+		return;		/* do nothing else */
+	case 0x1d:		/* ctrl pressed */
+		ctrl = 1;
+		return;		/* do nothing else */
+	case 0x9d:		/* ctrl released */
+		ctrl = 0;
+		return;		/* do nothing else */
+	case 0x46:		/* scrollock pressed */
+		scroll_lock = ~scroll_lock;
+		kbd_set_leds ();
+		return;		/* do nothing else */
+	case 0x3A:		/* capslock pressed */
+		caps_lock = ~caps_lock;
+		kbd_set_leds ();
+		return;
+	case 0x45:		/* numlock pressed */
+		num_lock = ~num_lock;
+		kbd_set_leds ();
+		return;
+	case 0xC6:		/* scroll lock released */
+	case 0xC5:		/* num lock released */
+	case 0xBA:		/* caps lock released */
+		return;		/* just swallow */
 	}
-	if((scancode&0x80)==0x80) /* key released */
+	if ((scancode & 0x80) == 0x80)	/* key released */
 		return;
 	/* now, decide which table we need */
-	if(scancode > (sizeof(kbd_plain_xlate)/sizeof(kbd_plain_xlate[0]))) { /* scancode not in list */
-		PRINTF("unkown scancode %X\n",scancode);
-		return; /* swallow it */
+	if (scancode > (sizeof (kbd_plain_xlate) / sizeof (kbd_plain_xlate[0]))) {	/* scancode not in list */
+		PRINTF ("unkown scancode %X\n", scancode);
+		return;		/* swallow it */
 	}
 	/* setup plain code first */
-	keycode=kbd_plain_xlate[scancode];
-	if(caps_lock==1) { /* caps_lock is pressed, overwrite plain code */
-		if(scancode > (sizeof(kbd_shift_xlate)/sizeof(kbd_shift_xlate[0]))) { /* scancode not in list */
-			PRINTF("unkown caps-locked scancode %X\n",scancode);
-			return; /* swallow it */
+	keycode = kbd_plain_xlate[scancode];
+	if (caps_lock == 1) {	/* caps_lock is pressed, overwrite plain code */
+		if (scancode > (sizeof (kbd_shift_xlate) / sizeof (kbd_shift_xlate[0]))) {	/* scancode not in list */
+			PRINTF ("unkown caps-locked scancode %X\n", scancode);
+			return;	/* swallow it */
 		}
-		keycode=kbd_shift_xlate[scancode];
-		if(keycode<'A') { /* we only want the alphas capital */
-			keycode=kbd_plain_xlate[scancode];
+		keycode = kbd_shift_xlate[scancode];
+		if (keycode < 'A') {	/* we only want the alphas capital */
+			keycode = kbd_plain_xlate[scancode];
 		}
 	}
-	if(shift==1) { /* shift overwrites caps_lock */
-		if(scancode > (sizeof(kbd_shift_xlate)/sizeof(kbd_shift_xlate[0]))) { /* scancode not in list */
-			PRINTF("unkown shifted scancode %X\n",scancode);
-			return; /* swallow it */
+	if (shift == 1) {	/* shift overwrites caps_lock */
+		if (scancode > (sizeof (kbd_shift_xlate) / sizeof (kbd_shift_xlate[0]))) {	/* scancode not in list */
+			PRINTF ("unkown shifted scancode %X\n", scancode);
+			return;	/* swallow it */
 		}
-		keycode=kbd_shift_xlate[scancode];
+		keycode = kbd_shift_xlate[scancode];
 	}
-	if(ctrl==1) { /* ctrl overwrites caps_lock and shift */
-		if(scancode > (sizeof(kbd_ctrl_xlate)/sizeof(kbd_ctrl_xlate[0]))) { /* scancode not in list */
-			PRINTF("unkown ctrl scancode %X\n",scancode);
-			return; /* swallow it */
+	if (ctrl == 1) {	/* ctrl overwrites caps_lock and shift */
+		if (scancode > (sizeof (kbd_ctrl_xlate) / sizeof (kbd_ctrl_xlate[0]))) {	/* scancode not in list */
+			PRINTF ("unkown ctrl scancode %X\n", scancode);
+			return;	/* swallow it */
 		}
-		keycode=kbd_ctrl_xlate[scancode];
+		keycode = kbd_ctrl_xlate[scancode];
 	}
 	/* check if valid keycode */
-	if(keycode==0xff) {
-		PRINTF("unkown scancode %X\n",scancode);
-		return; /* swallow unknown codes */
+	if (keycode == 0xff) {
+		PRINTF ("unkown scancode %X\n", scancode);
+		return;		/* swallow unknown codes */
 	}
 
-	kbd_put_queue(keycode);
-	PRINTF("%x\n",keycode);
+	kbd_put_queue (keycode);
+	PRINTF ("%x\n", keycode);
 }
 
 /*
@@ -583,8 +582,7 @@ char * kbd_initialize(void)
 		status = kbd_wait_for_input();
 		if (status == KBD_REPLY_ACK)
 			break;
-		if (status != KBD_REPLY_RESEND)
-		{
+		if (status != KBD_REPLY_RESEND) {
 			PRINTF("status: %X\n",status);
 			return "Kbd:   reset failed, no ACK";
 		}
diff --git a/board/mpl/common/memtst.c b/board/mpl/common/memtst.c
index 1d28513d87..1393ea15af 100644
--- a/board/mpl/common/memtst.c
+++ b/board/mpl/common/memtst.c
@@ -55,9 +55,9 @@ DECLARE_GLOBAL_DATA_PTR;
 #define FALSE           0
 #define TRUE            1
 
-#define TEST_QUIET 	8
-#define TEST_SHOW_PROG 	4
-#define TEST_SHOW_ERR 	2
+#define TEST_QUIET	8
+#define TEST_SHOW_PROG	4
+#define TEST_SHOW_ERR	2
 #define TEST_SHOW_ALL	1
 
 #define TESTPAT1 0xAA55AA55
@@ -473,19 +473,19 @@ void mem_test_reloc(void)
 	unsigned long addr;
 	int i;
 	for (i=0; i< TEST_STAGES; i++) {
- 		addr = (ulong) (test_stage[i].test_write) + gd->reloc_off;
+		addr = (ulong) (test_stage[i].test_write) + gd->reloc_off;
 		test_stage[i].test_write=
 			(void (*) (unsigned long startaddr, unsigned long size,
 						unsigned long *pat))addr;
- 		addr = (ulong) (test_stage[i].test_write_desc) + gd->reloc_off;
+		addr = (ulong) (test_stage[i].test_write_desc) + gd->reloc_off;
 		test_stage[i].test_write_desc=(char *)addr;
- 		if(test_stage[i].test_check1) {
+		if(test_stage[i].test_check1) {
 			addr = (ulong) (test_stage[i].test_check1) + gd->reloc_off;
 			test_stage[i].test_check1=
 				(void *(*) (int mode, unsigned long startaddr,
 				 unsigned long size, unsigned long *pat))addr;
 		}
- 		if(test_stage[i].test_check2) {
+		if(test_stage[i].test_check2) {
 			addr = (ulong) (test_stage[i].test_check2) + gd->reloc_off;
 			test_stage[i].test_check2=
 				(void *(*) (int mode, unsigned long startaddr,
diff --git a/board/mpl/common/pci.c b/board/mpl/common/pci.c
index bde14beeb1..bfd642892b 100644
--- a/board/mpl/common/pci.c
+++ b/board/mpl/common/pci.c
@@ -97,7 +97,7 @@ static void reloc_pci_cfg_table(struct pci_config_table *table)
 	unsigned long addr;
 
 	for (; table && table->vendor; table++) {
- 		addr = (ulong) (table->config_device) + gd->reloc_off;
+		addr = (ulong) (table->config_device) + gd->reloc_off;
 #ifdef DEBUG
 		printf ("device \"%d\": 0x%08lx => 0x%08lx\n",
 				table->device, (ulong) (table->config_device), addr);
diff --git a/board/mpl/common/pci_parts.h b/board/mpl/common/pci_parts.h
index 60008e2b24..7bca961c5c 100644
--- a/board/mpl/common/pci_parts.h
+++ b/board/mpl/common/pci_parts.h
@@ -80,9 +80,9 @@
  */
 
 struct pci_pip405_config_entry {
-	int 		index; 	/* address */
-	unsigned long 	val;	/* value */
-	int 		width;	/* data size */
+	int		index;	/* address */
+	unsigned long	val;	/* value */
+	int		width;	/* data size */
 };
 
 extern void pci_pip405_write_regs(struct pci_controller *,
@@ -95,37 +95,37 @@ static struct pci_pip405_config_entry piix4_isa_bridge_f0[] = {
 	{PCI_CFG_PIIX4_GENCFG,	0x00018041,	4}, /* enable SERIRQs, ISA, PNP, GPI11 */
 	{PCI_CFG_PIIX4_TOM,	0xFE,		1}, /* Top of Memory		*/
 	{PCI_CFG_PIIX4_XBCS,	0x02C4,		2}, /* disable all peri CS	*/
-	{PCI_CFG_PIIX4_RTCCFG,	0x21,		1}, /* enable RTC	   	*/
+	{PCI_CFG_PIIX4_RTCCFG,	0x21,		1}, /* enable RTC		*/
 #if defined(CONFIG_PIP405)
-	{PCI_CFG_PIIX4_MBDMA,	0x82,		1}, /* set MBDMA0 to DMA 2   	*/
-	{PCI_CFG_PIIX4_MBDMA+1,	0x83,		1}, /* set MBDMA1 to DMA 3   	*/
+	{PCI_CFG_PIIX4_MBDMA,	0x82,		1}, /* set MBDMA0 to DMA 2	*/
+	{PCI_CFG_PIIX4_MBDMA+1,	0x83,		1}, /* set MBDMA1 to DMA 3	*/
 #endif
 	{PCI_CFG_PIIX4_DLC,	0x0,		1}, /* disable passive release feature */
-	{ }				    	    /* end of device table	*/
+	{ }					    /* end of device table	*/
 };
 
 /* PIIX4 IDE Controller Function 1 */
 static struct pci_pip405_config_entry piix4_ide_cntrl_f1[] = {
 	{PCI_CFG_PIIX4_BMIBA,	0x0001000,	4}, /* set BMI to a valid address */
-	{PCI_COMMAND,		0x0001,		2}, /* enable IO access 	*/
+	{PCI_COMMAND,		0x0001,		2}, /* enable IO access	*/
 #if !defined(CONFIG_MIP405T)
 	{PCI_CFG_PIIX4_IDETIM,	0x80008000,	4}, /* enable Both IDE channels	*/
 #else
 	{PCI_CFG_PIIX4_IDETIM,	0x00008000,	4}, /* enable IDE channel0	*/
 #endif
-	{ }					    /* end of device table 	*/
+	{ }					    /* end of device table	*/
 };
 
 /* PIIX4 USB Controller Function 2 */
 static struct pci_pip405_config_entry piix4_usb_cntrl_f2[] = {
 #if !defined(CONFIG_MIP405T)
-	{PCI_INTERRUPT_LINE,	31,		1}, /* Int vector = 31 		*/
+	{PCI_INTERRUPT_LINE,	31,		1}, /* Int vector = 31		*/
 	{PCI_BASE_ADDRESS_4,	0x0000E001,	4}, /* Set IO Address to 0xe000 to 0xe01F */
-	{PCI_LATENCY_TIMER,	0x80,		1}, /* Latency Timer 0x80 	*/
-	{0xC0,			0x2000,		2}, /* Legacy support 		*/
+	{PCI_LATENCY_TIMER,	0x80,		1}, /* Latency Timer 0x80	*/
+	{0xC0,			0x2000,		2}, /* Legacy support		*/
 	{PCI_COMMAND,		0x0005,		2}, /* enable IO access and Master */
 #endif
-	{ }					    /* end of device table 	*/
+	{ }					    /* end of device table	*/
 };
 
 /* PIIX4 Power Management Function 3 */
@@ -133,12 +133,12 @@ static struct pci_pip405_config_entry piix4_pmm_cntrl_f3[] = {
 	{PCI_CFG_PIIX4_PMBA,	0x00004000,	4}, /* set PMBA to "valid" value */
 	{PCI_CFG_PIIX4_SMBBA,	0x00005000,	4}, /* set SMBBA to "valid" value */
 	{PCI_CFG_PIIX4_PMMISC,	0x01,		1}, /* enable PMBA IO access	*/
-	{PCI_COMMAND,		0x0001,		2}, /* enable IO access 	*/
-	{ }					    /* end of device table 	*/
+	{PCI_COMMAND,		0x0001,		2}, /* enable IO access	*/
+	{ }					    /* end of device table	*/
 };
 /* PPC405 Dummy only used to prevent autosetup on this host bridge */
 static struct pci_pip405_config_entry ppc405_dummy[] = {
-	{ }				    	    /* end of device table 	*/
+	{ }					    /* end of device table	*/
 };
 
 void pci_405gp_setup_vga(struct pci_controller *hose, pci_dev_t dev,
@@ -146,13 +146,13 @@ void pci_405gp_setup_vga(struct pci_controller *hose, pci_dev_t dev,
 
 
 static struct pci_config_table pci_pip405_config_table[]={
-	{PCI_VENDOR_ID_IBM, 			/* 405 dummy */
+	{PCI_VENDOR_ID_IBM,			/* 405 dummy */
 	 PCI_DEVICE_ID_IBM_405GP,
 	 PCI_ANY_ID,
 	 PCI_ANY_ID, PCI_ANY_ID, 0,
 	 pci_pip405_write_regs, {(unsigned long) ppc405_dummy}},
 
-	{PCI_VENDOR_ID_INTEL, 			/* PIIX4 ISA Bridge Function 0 */
+	{PCI_VENDOR_ID_INTEL,			/* PIIX4 ISA Bridge Function 0 */
 	 PCI_DEVICE_ID_INTEL_82371AB_0,
 	 PCI_ANY_ID,
 	 PCI_ANY_ID, PCI_ANY_ID, 0,
diff --git a/board/mpl/common/usb_uhci.c b/board/mpl/common/usb_uhci.c
index 84c91c44b6..6778e4098c 100644
--- a/board/mpl/common/usb_uhci.c
+++ b/board/mpl/common/usb_uhci.c
@@ -540,7 +540,7 @@ void usb_check_int_chain(void)
 		link=swap_32(td_int[i].link) & 0xfffffff0; /* next in chain */
 		td=(uhci_td_t *)link; /* assign it */
 		/* all interrupt TDs are finally linked to the td_int[0].
- 		 * so we process all until we find the td_int[0].
+		 * so we process all until we find the td_int[0].
 		 * if int0 chain points to a QH, we're also done
 	   */
 		while(((i>0) && (link != (unsigned long)&td_int[0])) ||
diff --git a/board/mpl/mip405/cmd_mip405.c b/board/mpl/mip405/cmd_mip405.c
index 6fbc5859c0..6ad95b5dda 100644
--- a/board/mpl/mip405/cmd_mip405.c
+++ b/board/mpl/mip405/cmd_mip405.c
@@ -38,19 +38,19 @@ extern int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
 int do_mip405(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
 
- 	ulong led_on;
+	ulong led_on;
 
 	if (strcmp(argv[1], "info") == 0)
 	{
 		print_mip405_info();
-	 	return 0;
-   	}
- 	if (strcmp(argv[1], "led") == 0)
+		return 0;
+	}
+	if (strcmp(argv[1], "led") == 0)
 	{
 		led_on = (ulong)simple_strtoul(argv[2], NULL, 10);
 		user_led0(led_on);
 		return 0;
-   	}
+	}
 	return (do_mplcommon(cmdtp, flag, argc, argv));
 }
 U_BOOT_CMD(
diff --git a/board/mpl/mip405/mip405.c b/board/mpl/mip405/mip405.c
index 4b1c1c0669..9e8f9bbdd4 100644
--- a/board/mpl/mip405/mip405.c
+++ b/board/mpl/mip405/mip405.c
@@ -89,12 +89,12 @@ extern ldiv_t ldiv (long int __numer, long int __denom);
 #endif
 
 
-#define PLD_PART_REG 		PER_PLD_ADDR + 0
-#define PLD_VERS_REG 		PER_PLD_ADDR + 1
-#define PLD_BOARD_CFG_REG 	PER_PLD_ADDR + 2
-#define PLD_IRQ_REG 		PER_PLD_ADDR + 3
-#define PLD_COM_MODE_REG 	PER_PLD_ADDR + 4
-#define PLD_EXT_CONF_REG 	PER_PLD_ADDR + 5
+#define PLD_PART_REG		PER_PLD_ADDR + 0
+#define PLD_VERS_REG		PER_PLD_ADDR + 1
+#define PLD_BOARD_CFG_REG	PER_PLD_ADDR + 2
+#define PLD_IRQ_REG		PER_PLD_ADDR + 3
+#define PLD_COM_MODE_REG	PER_PLD_ADDR + 4
+#define PLD_EXT_CONF_REG	PER_PLD_ADDR + 5
 
 #define MEGA_BYTE (1024*1024)
 
diff --git a/board/mpl/mip405/mip405.h b/board/mpl/mip405/mip405.h
index b1d91deece..fd7e78a45d 100644
--- a/board/mpl/mip405/mip405.h
+++ b/board/mpl/mip405/mip405.h
@@ -35,7 +35,7 @@ void user_led0(unsigned char on);
 #endif
 /* timings */
 /* PLD (CS7) */
-#define PLD_BME	0 	/* Burst disable */
+#define PLD_BME	0	/* Burst disable */
 #define PLD_TWE	5	/* 5 * 30ns 120ns Waitstates (access=TWT+1+TH) */
 #define PLD_CSN	1	/* Chipselect is driven inactive for 1 Cycle BTW transfers */
 #define PLD_OEN	1	/* Cycles from CS low to OE low   */
@@ -46,7 +46,7 @@ void user_led0(unsigned char on);
 #define PLD_SOR	1	/* Sample on Ready disabled */
 #define PLD_BEM	0	/* Byte Write only active on Write cycles */
 #define PLD_PEN	0	/* Parity disable */
-#define PLD_AP 	((PLD_BME << 31) + (PLD_TWE << 23) + (PLD_CSN << 18) + (PLD_OEN << 16) + (PLD_WBN << 14) + \
+#define PLD_AP	((PLD_BME << 31) + (PLD_TWE << 23) + (PLD_CSN << 18) + (PLD_OEN << 16) + (PLD_WBN << 14) + \
 					(PLD_WBF << 12) + (PLD_TH << 9) + (PLD_RE << 8) + (PLD_SOR << 7) + (PLD_BEM << 6) + (PLD_PEN << 5))
 
 /* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
@@ -62,7 +62,7 @@ void user_led0(unsigned char on);
 
 #define PER_BOARD_ADDR (PER_UART1_ADDR+(1024*1024))
 /* Dummy CS to get the board revision */
-#define BOARD_BME	0 	/* Burst disable */
+#define BOARD_BME	0	/* Burst disable */
 #define BOARD_TWE	255	/* 255 * 30ns 120ns Waitstates (access=TWT+1+TH) */
 #define BOARD_CSN	1	/* Chipselect is driven inactive for 1 Cycle BTW transfers */
 #define BOARD_OEN	1	/* Cycles from CS low to OE low   */
@@ -73,7 +73,7 @@ void user_led0(unsigned char on);
 #define BOARD_SOR	1	/* Sample on Ready disabled */
 #define BOARD_BEM	0	/* Byte Write only active on Write cycles */
 #define BOARD_PEN	0	/* Parity disable */
-#define BOARD_AP 	((BOARD_BME << 31) + (BOARD_TWE << 23) + (BOARD_CSN << 18) + (BOARD_OEN << 16) + (BOARD_WBN << 14) + \
+#define BOARD_AP	((BOARD_BME << 31) + (BOARD_TWE << 23) + (BOARD_CSN << 18) + (BOARD_OEN << 16) + (BOARD_WBN << 14) + \
 					(BOARD_WBF << 12) + (BOARD_TH << 9) + (BOARD_RE << 8) + (BOARD_SOR << 7) + (BOARD_BEM << 6) + (BOARD_PEN << 5))
 
 /* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
@@ -86,7 +86,7 @@ void user_led0(unsigned char on);
 
 
 /* UART0 CS2 */
-#define UART0_BME	0 	/* Burst disable */
+#define UART0_BME	0	/* Burst disable */
 #define UART0_TWE	7	/* 7 * 30ns 210ns Waitstates (access=TWT+1+TH) */
 #define UART0_CSN	1	/* Chipselect is driven inactive for 1 Cycle BTW transfers */
 #define UART0_OEN	1	/* Cycles from CS low to OE low   */
@@ -97,7 +97,7 @@ void user_led0(unsigned char on);
 #define UART0_SOR	1	/* Sample on Ready disabled */
 #define UART0_BEM	0	/* Byte Write only active on Write cycles */
 #define UART0_PEN	0	/* Parity disable */
-#define UART0_AP 	((UART0_BME << 31) + (UART0_TWE << 23) + (UART0_CSN << 18) + (UART0_OEN << 16) + (UART0_WBN << 14) + \
+#define UART0_AP	((UART0_BME << 31) + (UART0_TWE << 23) + (UART0_CSN << 18) + (UART0_OEN << 16) + (UART0_WBN << 14) + \
 					(UART0_WBF << 12) + (UART0_TH << 9) + (UART0_RE << 8) + (UART0_SOR << 7) + (UART0_BEM << 6) + (UART0_PEN << 5))
 
 /* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
@@ -115,10 +115,10 @@ void user_led0(unsigned char on);
 
 /* Flash CS0 or CS 1 */
 /* 0x7F8FFE80 slowest timing at all... */
-#define FLASH_BME_B	1 	/* Burst enable */
+#define FLASH_BME_B	1	/* Burst enable */
 #define FLASH_FWT_B	0x6	/* 6 * 30ns 210ns First Wait Access */
 #define FLASH_BWT_B	0x6	/* 6 * 30ns 210ns Burst Wait Access */
-#define FLASH_BME	0 	/* Burst disable */
+#define FLASH_BME	0	/* Burst disable */
 #define FLASH_TWE	0xb/* 11 * 30ns 330ns Waitstates (access=TWT+1+TH) */
 #define FLASH_CSN	0	/* Chipselect is driven inactive for 1 Cycle BTW transfers */
 #define FLASH_OEN	1	/* Cycles from CS low to OE low   */
@@ -130,10 +130,10 @@ void user_led0(unsigned char on);
 #define FLASH_BEM	0	/* Byte Write only active on Write cycles */
 #define FLASH_PEN	0	/* Parity disable */
 /* Access Parameter Register for non Boot */
-#define FLASH_AP 	((FLASH_BME << 31) + (FLASH_TWE << 23) + (FLASH_CSN << 18) + (FLASH_OEN << 16) + (FLASH_WBN << 14) + \
+#define FLASH_AP	((FLASH_BME << 31) + (FLASH_TWE << 23) + (FLASH_CSN << 18) + (FLASH_OEN << 16) + (FLASH_WBN << 14) + \
 					(FLASH_WBF << 12) + (FLASH_TH << 9) + (FLASH_RE << 8) + (FLASH_SOR << 7) + (FLASH_BEM << 6) + (FLASH_PEN << 5))
 /* Access Parameter Register for Boot */
-#define FLASH_AP_B 	((FLASH_BME_B << 31) + (FLASH_FWT_B << 26) + (FLASH_BWT_B << 23) + (FLASH_CSN << 18) + (FLASH_OEN << 16) + (FLASH_WBN << 14) + \
+#define FLASH_AP_B	((FLASH_BME_B << 31) + (FLASH_FWT_B << 26) + (FLASH_BWT_B << 23) + (FLASH_CSN << 18) + (FLASH_OEN << 16) + (FLASH_WBN << 14) + \
 					(FLASH_WBF << 12) + (FLASH_TH << 9) + (FLASH_RE << 8) + (FLASH_SOR << 7) + (FLASH_BEM << 6) + (FLASH_PEN << 5))
 
 /* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
@@ -149,10 +149,10 @@ void user_led0(unsigned char on);
 
 /* MPS CS1 or CS0 */
 /* Boot CS: */
-#define MPS_BME_B	1 	/* Burst enable */
+#define MPS_BME_B	1	/* Burst enable */
 #define MPS_FWT_B	0x6/* 6 * 30ns 210ns First Wait Access */
 #define MPS_BWT_B	0x6	/* 6 * 30ns 210ns Burst Wait Access */
-#define MPS_BME		0 	/* Burst disable */
+#define MPS_BME		0	/* Burst disable */
 #define MPS_TWE		0xb/* 11 * 30ns 330ns Waitstates (access=TWT+1+TH) */
 #define MPS_CSN		0	/* Chipselect is driven inactive for 1 Cycle BTW transfers */
 #define MPS_OEN		1	/* Cycles from CS low to OE low   */
@@ -164,10 +164,10 @@ void user_led0(unsigned char on);
 #define MPS_BEM		0	/* Byte Write only active on Write cycles */
 #define MPS_PEN		0	/* Parity disable */
 /* Access Parameter Register for non Boot */
-#define MPS_AP 		((MPS_BME << 31) + (MPS_TWE << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \
+#define MPS_AP		((MPS_BME << 31) + (MPS_TWE << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \
 					(MPS_WBF << 12) + (MPS_TH << 9) + (MPS_RE << 8) + (MPS_SOR << 7) + (MPS_BEM << 6) + (MPS_PEN << 5))
 /* Access Parameter Register for Boot */
-#define MPS_AP_B 		((MPS_BME_B << 31) + (MPS_FWT_B << 26) + (MPS_BWT_B << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \
+#define MPS_AP_B		((MPS_BME_B << 31) + (MPS_FWT_B << 26) + (MPS_BWT_B << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \
 					(MPS_WBF << 12) + (MPS_TH << 9) + (MPS_RE << 8) + (MPS_SOR << 7) + (MPS_BEM << 6) + (MPS_PEN << 5))
 
 /* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
diff --git a/board/mpl/mip405/u-boot.lds b/board/mpl/mip405/u-boot.lds
index ffdf467305..7932b9fc0f 100644
--- a/board/mpl/mip405/u-boot.lds
+++ b/board/mpl/mip405/u-boot.lds
@@ -42,11 +42,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/mpl/pati/cmd_pati.c b/board/mpl/pati/cmd_pati.c
index 98429c033d..91683a38d1 100644
--- a/board/mpl/pati/cmd_pati.c
+++ b/board/mpl/pati/cmd_pati.c
@@ -360,12 +360,12 @@ int do_pati(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	if (strcmp(argv[1], "info") == 0)
 	{
 		show_pld_regs();
-	 	return 0;
+		return 0;
 	}
 	if (strcmp(argv[1], "pci") == 0)
 	{
 		display_pci_regs();
-	 	return 0;
+		return 0;
 	}
 	if (strcmp(argv[1], "led") == 0)
 	{
@@ -377,7 +377,7 @@ int do_pati(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 		else
 			user_led1(led_on);
 		return 0;
-   	}
+	}
 #if defined(CFG_PCI_CON_DEVICE)
 	if (strcmp(argv[1], "con") == 0) {
 		pci_con_connect();
diff --git a/board/mpl/pati/pati.c b/board/mpl/pati/pati.c
index 0355b65b84..7893d61f16 100644
--- a/board/mpl/pati/pati.c
+++ b/board/mpl/pati/pati.c
@@ -484,7 +484,7 @@ int pci_con_getc(void)
 	else
 		diff=r_ptr-w_ptr;
 	if((diff<(REC_BUFFER_SIZE-4)) && buff_full) {
-   		/* clear Mail box */
+		/* clear Mail box */
 			buff_full=0;
 			PCICON_SET_REG(PCICON_RECEIVE_REG,0L);
 	}
diff --git a/board/mpl/pati/pati.h b/board/mpl/pati/pati.h
index d5217724da..86c7a41cc8 100644
--- a/board/mpl/pati/pati.h
+++ b/board/mpl/pati/pati.h
@@ -89,7 +89,7 @@
 #define SDRAM_CAL	9
 #define SDRAM_RCD	10
 #define SDRAM_WREQ	11
-#define SDRAM_PR 	12
+#define SDRAM_PR	12
 #define SDRAM_RC	13
 #define SDRAM_LMR	14
 #define SDRAM_IIP	19
@@ -128,7 +128,7 @@
 #define SDRAM_MUX0	9
 #define SDRAM_MUX1	10
 #define SDRAM_PDIS	11
-#define SDRAM_RES1 	12
+#define SDRAM_RES1	12
 #define SDRAM_RES2	13
 #define SDRAM_RES3	14
 #define SDRAM_RES4	19
@@ -177,7 +177,7 @@
 #define SDRAM_RES5	9
 #define SDRAM_CFG1	10
 #define SDRAM_CFG2	11
-#define SDRAM_CFG3 	12
+#define SDRAM_CFG3	12
 #define SDRAM_RES6	13
 #define SDRAM_CFG5	14
 #define SDRAM_CFG6	19
@@ -214,7 +214,7 @@
  * MISC Defines
  ***************************************************************/
 
-#define PCI_VENDOR_ID_MPL 	0x18E6
+#define PCI_VENDOR_ID_MPL	0x18E6
 #define PCI_DEVICE_ID_PATI	0x00DA
 
 #if defined(CONFIG_MIP405)
@@ -269,12 +269,12 @@
 
 /* Config Area */
 #define PATI_LOC_CFG_ADDR		0x07000000		/* Local Address */
-#define PATI_LOC_CFG_MASK		0xFFFFFF00  		/* 256 Bytes */
+#define PATI_LOC_CFG_MASK		0xFFFFFF00		/* 256 Bytes */
 /* Attributes */
-#define PATI_LOC_CFG_BUS_SIZE		PATI_BUS_SIZE_32  	/* 32 Bit */
-#define PATI_LOC_CFG_BURST		0  			/* No Burst */
-#define PATI_LOC_CFG_NO_PREFETCH	1  			/* No Prefetch */
-#define PATI_LOC_CFG_TA_ENABLE		1 			/* Enable TA */
+#define PATI_LOC_CFG_BUS_SIZE		PATI_BUS_SIZE_32	/* 32 Bit */
+#define PATI_LOC_CFG_BURST		0			/* No Burst */
+#define PATI_LOC_CFG_NO_PREFETCH	1			/* No Prefetch */
+#define PATI_LOC_CFG_TA_ENABLE		1			/* Enable TA */
 
 #define PATI_LOC_CFG_SPACE0_ATTR  ( \
 		PATI_LOC_CFG_BUS_SIZE | \
@@ -295,10 +295,10 @@
 #define PATI_LOC_SDRAM_ADDR		0x06000000		/* Local Address */
 #define PATI_LOC_SDRAM_MASK		0xFFF00000		/* 1MByte */
 /* Attributes */
-#define PATI_LOC_SDRAM_BUS_SIZE		PATI_BUS_SIZE_32  	/* 32 Bit */
-#define PATI_LOC_SDRAM_BURST		0  			/* No Burst */
-#define PATI_LOC_SDRAM_NO_PREFETCH	0  			/* Prefetch */
-#define PATI_LOC_SDRAM_TA_ENABLE	1  			/* Enable TA */
+#define PATI_LOC_SDRAM_BUS_SIZE		PATI_BUS_SIZE_32	/* 32 Bit */
+#define PATI_LOC_SDRAM_BURST		0			/* No Burst */
+#define PATI_LOC_SDRAM_NO_PREFETCH	0			/* Prefetch */
+#define PATI_LOC_SDRAM_TA_ENABLE	1			/* Enable TA */
 
 /* should never be used */
 #define PATI_LOC_SDRAM_SPACE0_ATTR  ( \
@@ -319,10 +319,10 @@
 #define PATI_LOC_FLASH_ADDR		0x03000000		/* Local Address */
 #define PATI_LOC_FLASH_MASK		0xFFF00000		/* 1MByte */
 /* Attributes */
-#define PATI_LOC_FLASH_BUS_SIZE		PATI_BUS_SIZE_16  	/* 16 Bit */
-#define PATI_LOC_FLASH_BURST		0  			/* No Burst */
-#define PATI_LOC_FLASH_NO_PREFETCH	1  			/* No Prefetch */
-#define PATI_LOC_FLASH_TA_ENABLE	1  			/* Enable TA */
+#define PATI_LOC_FLASH_BUS_SIZE		PATI_BUS_SIZE_16	/* 16 Bit */
+#define PATI_LOC_FLASH_BURST		0			/* No Burst */
+#define PATI_LOC_FLASH_NO_PREFETCH	1			/* No Prefetch */
+#define PATI_LOC_FLASH_TA_ENABLE	1			/* Enable TA */
 
 /* should never be used */
 #define PATI_LOC_FLASH_SPACE0_ATTR  ( \
@@ -343,7 +343,7 @@
 #define PATI_LOC_CPU_ADDR		0x01000000		/* Local Address */
 #define PATI_LOC_CPU_MASK		0xFFF00000		/* 1Mbyte */
 /* Attributes */
-#define PATI_LOC_CPU_BUS_SIZE		PATI_BUS_SIZE_32  	/* 32 Bit */
+#define PATI_LOC_CPU_BUS_SIZE		PATI_BUS_SIZE_32	/* 32 Bit */
 #define PATI_LOC_CPU_BURST		0			/* No Burst */
 #define PATI_LOC_CPU_NO_PREFETCH	1			/* No Prefetch */
 #define PATI_LOC_CPU_TA_ENABLE		1			/* Enable TA */
@@ -393,9 +393,9 @@
 
 
 #define PATI_HW_START		((BOOT_EXT_FLASH | INITIAL_MEM_28M | INITIAL_IRQ_PREF))
-#define PATI_HW_PCI_ONLY 	((BOOT_EXT_FLASH | INITIAL_MEM_28M | INITIAL_IRQ_PREF | PCI_MASTER_ONLY))
+#define PATI_HW_PCI_ONLY	((BOOT_EXT_FLASH | INITIAL_MEM_28M | INITIAL_IRQ_PREF | PCI_MASTER_ONLY))
 #define PATI_HW_CPU_ACC		((BOOT_EXT_FLASH | INITIAL_MEM_12M | INITIAL_IRQ_PREF | PCI_MASTER_ONLY))
-#define PATI_HW_CPU_SLAVE 	((BOOT_EXT_FLASH | INITIAL_MEM_12M | INITIAL_IRQ_PREF | PCI_MASTER_ONLY | LOCAL_CPU_SLAVE))
+#define PATI_HW_CPU_SLAVE	((BOOT_EXT_FLASH | INITIAL_MEM_12M | INITIAL_IRQ_PREF | PCI_MASTER_ONLY | LOCAL_CPU_SLAVE))
 
 /***************************************************
  * Direct Master Config
@@ -404,12 +404,12 @@
 #define PATI_BUS_MASTER 1
 
 
-#define PATI_DMASTER_MASK 		0xFFF00000  /* 1MByte */
-#define PATI_DMASTER_ADDR 		0x01000000  /* Local Address */
+#define PATI_DMASTER_MASK		0xFFF00000  /* 1MByte */
+#define PATI_DMASTER_ADDR		0x01000000  /* Local Address */
 
-#define PATI_DMASTER_MEMORY_EN 		0x00000001 /* 0x00000001 */
-#define PATI_DMASTER_READ_AHEAD 	0x00000004 /* 0x00000004 */
-#define PATI_DMASTER_READ_NOT_AHEAD 	0x00000000 /* 0x00000004 */
+#define PATI_DMASTER_MEMORY_EN		0x00000001 /* 0x00000001 */
+#define PATI_DMASTER_READ_AHEAD		0x00000004 /* 0x00000004 */
+#define PATI_DMASTER_READ_NOT_AHEAD	0x00000000 /* 0x00000004 */
 #define PATI_DMASTER_PRE_SIZE_CNTRL_0	0x00000000
 #define PATI_DMASTER_PRE_SIZE_CNTRL_4	0x00000008
 #define PATI_DMASTER_PRE_SIZE_CNTRL_8	0x00001000
diff --git a/board/mpl/pati/pci_eeprom.h b/board/mpl/pati/pci_eeprom.h
index 96588089ea..af34b86c31 100644
--- a/board/mpl/pati/pci_eeprom.h
+++ b/board/mpl/pati/pci_eeprom.h
@@ -35,57 +35,57 @@ typedef struct pci_eeprom_t {
 } pci_eeprom;
 
 static pci_eeprom pati_eeprom[] = {
-	{ 0x00,PCI_DEVICE_ID_PATI }, 	/* PCI Device ID PCIIDR[31:16] */
-	{ 0x02,PCI_VENDOR_ID_MPL }, 	/* PCI Vendor ID PCIIDR[15:0] */
-	{ 0x04,PCI_CLASS_PROCESSOR_POWERPC }, 	/* PCI Class Code PCICCR[23:8] */
-	{ 0x06,0x00BA }, 	/* PCI Class Code / PCI Revision ID PCICCR[7:0] / PCIREV[7:0] */
-	{ 0x08,0x0007 }, 	/* PCI Maximum Latency / PCI Minimum Grant PCIMLR[7:0] / PCIMGR[7:0] */
-	{ 0x0A,0x0100 }, 	/* PCI Interrupt Pin / PCI Interrupt Line PCIIPR[7:0] / PCIILR[7:0] */
-	{ 0x0C,0x0000 }, 	/* MSW of Mailbox 0 (User Defined) PCI9056_MAILBOX0[31:16] */
-	{ 0x0E,0x0000 }, 	/* LSW of Mailbox 0 (User Defined) PCI9056_MAILBOX0[15:0] */
-	{ 0x10,0x0000 }, 	/* MSW of Mailbox 1 (User Defined) PCI9056_MAILBOX1[31:16] */
-	{ 0x12,0x0000 }, 	/* LSW of Mailbox 1 (User Defined) PCI9056_MAILBOX1[15:0] */
-	{ 0x14,HIGH_WORD(PATI_LOC_CFG_MASK) }, 	/* MSW of Direct Slave Local Address Space 0 Range LAS0RR[31:16] */
-	{ 0x16,LOW_WORD(PATI_LOC_CFG_MASK) }, 	/* LSW of Direct Slave Local Address Space 0 Range LAS0RR[15:0] */
-	{ 0x18,HIGH_WORD(PATI_LOC_CFG_ADDR) }, 	/* MSW of Direct Slave Local Address Space 0 Local Base Address (Remap) LAS0BA[31:16] (CFG) */
-	{ 0x1A,LOW_WORD(PATI_LOC_CFG_ADDR)|1 }, 	/* LSW of Direct Slave Local Address Space 0 Local Base Address (Remap) LAS0BA[15:2, 0], Reserved [1] */
-	{ 0x1C,0x0000 }, 	/* MSW of Mode/DMA Arbitration MARBR[31, 29:16] or DMAARB[31, 29:16], Reserved [30] */
-	{ 0x1E,0x0000 }, 	/* LSW of Mode/DMA Arbitration MARBR[15:0] or DMAARB[15:0] */
-	{ 0x20,0x0030 }, 	/* Local Miscellaneous Control 2 / Serial EEPROM WP Addr Boundary LMISC2[5:0], Res[7:6] / PROT_AREA[6:0], Res[7] */
-	{ 0x22,0x0510 }, 	/* Local Miscellaneous Control 1 / Local Bus Big/Little Endian Descriptor LMISC1[7:0] / BIGEND[7:0] */
-	{ 0x24,0x0000 }, 	/* MSW of Direct Slave Expansion ROM Range EROMRR[31:16] */
-	{ 0x26,0x0000 }, 	/* LSW of Direct Slave Expansion ROM Range EROMRR[15:11, 0], Reserved [10:1]  */
-	{ 0x28,0x0000 }, 	/* MSW of Direct Slave Expansion ROM Local Base Address (Remap) and BREQo Control EROMBA[31:16] */
-	{ 0x2A,0x0000 }, 	/* LSW of Direct Slave Expansion ROM Local Base Address (Remap) and BREQo Control EROMBA[15:11, 5:0], Reserved [10:6] */
-	{ 0x2C,(0x4243 | HIGH_WORD((PATI_LOC_CFG_SPACE0_ATTR))) }, 	/* MSW of Local Address Space 0/Expansion ROM Bus Region Descriptor LBRD0[31:16] */
-	{ 0x2E,LOW_WORD(PATI_LOC_CFG_SPACE0_ATTR) }, 	/* LSW of Local Address Space 0/Expansion ROM Bus Region Descriptor LBRD0[15:0] */
-	{ 0x30,HIGH_WORD(PATI_DMASTER_MASK) }, 	/* MSW of Local Range for Direct Master-to-PCI DMRR[31:16] */
-	{ 0x32,LOW_WORD(PATI_DMASTER_MASK) }, 	/* LSW of Local Range for Direct Master-to-PCI (Reserved) DMRR[15:0] */
-	{ 0x34,HIGH_WORD(PATI_DMASTER_ADDR) }, 	/* MSW of Local Base Address for Direct Master-to-PCI Memory DMLBAM[31:16] */
-	{ 0x36,LOW_WORD(PATI_DMASTER_ADDR) }, 	/* LSW of Local Base Address for Direct Master-to-PCI Memory (Reserved) DMLBAM[15:0] */
-	{ 0x38,0x0000 }, 	/* MSW of Local Bus Address for Direct Master-to-PCI I/O Configuration DMLBAI[31:16] */
-	{ 0x3A,0x0000 }, 	/* LSW of Local Bus Address for Direct Master-to-PCI I/O Configuration (Reserved) DMLBAI[15:0] */
-	{ 0x3C,0x0000 }, 	/* MSW of PCI Base Address (Remap) for Direct Master-to-PCI Memory DMPBAM[31:16] */
-	{ 0x3E,0x0000 }, 	/* LSW of PCI Base Address (Remap) for Direct Master-to-PCI Memory DMPBAM[15:0] */
-	{ 0x40,0x0000 }, 	/* MSW of PCI Configuration Address for Direct Master-to-PCI I/O Configuration DMCFGA[31, 23:16] Reserved [30:24]*/
-	{ 0x42,0x0000 }, 	/* LSW of PCI Configuration Address for Direct Master-to-PCI I/O Configuration DMCFGA[15:0] */
-	{ 0x44,0x0000 }, 	/* PCI Subsystem ID PCISID[15:0] */
-	{ 0x46,0x0000 }, 	/* PCI Subsystem Vendor ID PCISVID[15:0] */
-	{ 0x48,HIGH_WORD(PATI_LOC_SDRAM_MASK) }, 	/* MSW of Direct Slave Local Address Space 1 Range (1 MB) LAS1RR[31:16] */
-	{ 0x4A,LOW_WORD(PATI_LOC_SDRAM_MASK) }, 	/* LSW of Direct Slave Local Address Space 1 Range (1 MB) LAS1RR[15:0] */
-	{ 0x4C,HIGH_WORD(PATI_LOC_SDRAM_ADDR) }, 	/* MSW of Direct Slave Local Address Space 1 Local Base Address (Remap) LAS1BA[31:16] (SDRAM) */
-	{ 0x4E,LOW_WORD(PATI_LOC_SDRAM_ADDR) | 0x1 }, 	/* LSW of Direct Slave Local Address Space 1 Local Base Address (Remap) LAS1BA[15:2, 0], Reserved [1] */
-	{ 0x50,HIGH_WORD(PATI_LOC_SDRAM_SPACE1_ATTR) }, 	/* MSW of Local Address Space 1 Bus Region Descriptor LBRD1[31:16] */
-	{ 0x52,LOW_WORD(PATI_LOC_SDRAM_SPACE1_ATTR) }, 	/* LSW of Local Address Space 1 Bus Region Descriptor (Reserved) LBRD1[15:0] */
-	{ 0x54,0x0000 }, 	/* Hot Swap Control/Status (Reserved) Reserved */
-	{ 0x56,0x0000 }, 	/* Hot Swap Next Capability Pointer / Hot Swap Control HS_NEXT[7:0] / HS_CNTL[7:0] */
-	{ 0x58,0x0000 }, 	/* Reserved Reserved */
-	{ 0x5A,0x0000 }, 	/* PCI Arbiter Control PCIARB[3:0], Reserved [15:4] */
-	{ 0x5C,0x0000 }, 	/* Power Management Capabilities PMC[15:9, 2:0] */
-	{ 0x5E,0x0000 }, 	/* Power Management Next Capability Pointer (Reserved) / Power Management Capability ID (Reserved) Reserved*/
-	{ 0x60,0x0000 }, 	/* Power Management Data / PMCSR Bridge Support Extension (Reserved) PMDATA[7:0] / Reserved */
-	{ 0x62,0x0000 }, 	/* Power Management Control/Status PMCSR[14:8] */
-	{ 0xFFFF,0xFFFF} 	/* terminaror */
+	{ 0x00,PCI_DEVICE_ID_PATI },	/* PCI Device ID PCIIDR[31:16] */
+	{ 0x02,PCI_VENDOR_ID_MPL },	/* PCI Vendor ID PCIIDR[15:0] */
+	{ 0x04,PCI_CLASS_PROCESSOR_POWERPC },	/* PCI Class Code PCICCR[23:8] */
+	{ 0x06,0x00BA },	/* PCI Class Code / PCI Revision ID PCICCR[7:0] / PCIREV[7:0] */
+	{ 0x08,0x0007 },	/* PCI Maximum Latency / PCI Minimum Grant PCIMLR[7:0] / PCIMGR[7:0] */
+	{ 0x0A,0x0100 },	/* PCI Interrupt Pin / PCI Interrupt Line PCIIPR[7:0] / PCIILR[7:0] */
+	{ 0x0C,0x0000 },	/* MSW of Mailbox 0 (User Defined) PCI9056_MAILBOX0[31:16] */
+	{ 0x0E,0x0000 },	/* LSW of Mailbox 0 (User Defined) PCI9056_MAILBOX0[15:0] */
+	{ 0x10,0x0000 },	/* MSW of Mailbox 1 (User Defined) PCI9056_MAILBOX1[31:16] */
+	{ 0x12,0x0000 },	/* LSW of Mailbox 1 (User Defined) PCI9056_MAILBOX1[15:0] */
+	{ 0x14,HIGH_WORD(PATI_LOC_CFG_MASK) },	/* MSW of Direct Slave Local Address Space 0 Range LAS0RR[31:16] */
+	{ 0x16,LOW_WORD(PATI_LOC_CFG_MASK) },	/* LSW of Direct Slave Local Address Space 0 Range LAS0RR[15:0] */
+	{ 0x18,HIGH_WORD(PATI_LOC_CFG_ADDR) },	/* MSW of Direct Slave Local Address Space 0 Local Base Address (Remap) LAS0BA[31:16] (CFG) */
+	{ 0x1A,LOW_WORD(PATI_LOC_CFG_ADDR)|1 },	/* LSW of Direct Slave Local Address Space 0 Local Base Address (Remap) LAS0BA[15:2, 0], Reserved [1] */
+	{ 0x1C,0x0000 },	/* MSW of Mode/DMA Arbitration MARBR[31, 29:16] or DMAARB[31, 29:16], Reserved [30] */
+	{ 0x1E,0x0000 },	/* LSW of Mode/DMA Arbitration MARBR[15:0] or DMAARB[15:0] */
+	{ 0x20,0x0030 },	/* Local Miscellaneous Control 2 / Serial EEPROM WP Addr Boundary LMISC2[5:0], Res[7:6] / PROT_AREA[6:0], Res[7] */
+	{ 0x22,0x0510 },	/* Local Miscellaneous Control 1 / Local Bus Big/Little Endian Descriptor LMISC1[7:0] / BIGEND[7:0] */
+	{ 0x24,0x0000 },	/* MSW of Direct Slave Expansion ROM Range EROMRR[31:16] */
+	{ 0x26,0x0000 },	/* LSW of Direct Slave Expansion ROM Range EROMRR[15:11, 0], Reserved [10:1]  */
+	{ 0x28,0x0000 },	/* MSW of Direct Slave Expansion ROM Local Base Address (Remap) and BREQo Control EROMBA[31:16] */
+	{ 0x2A,0x0000 },	/* LSW of Direct Slave Expansion ROM Local Base Address (Remap) and BREQo Control EROMBA[15:11, 5:0], Reserved [10:6] */
+	{ 0x2C,(0x4243 | HIGH_WORD((PATI_LOC_CFG_SPACE0_ATTR))) },	/* MSW of Local Address Space 0/Expansion ROM Bus Region Descriptor LBRD0[31:16] */
+	{ 0x2E,LOW_WORD(PATI_LOC_CFG_SPACE0_ATTR) },	/* LSW of Local Address Space 0/Expansion ROM Bus Region Descriptor LBRD0[15:0] */
+	{ 0x30,HIGH_WORD(PATI_DMASTER_MASK) },	/* MSW of Local Range for Direct Master-to-PCI DMRR[31:16] */
+	{ 0x32,LOW_WORD(PATI_DMASTER_MASK) },	/* LSW of Local Range for Direct Master-to-PCI (Reserved) DMRR[15:0] */
+	{ 0x34,HIGH_WORD(PATI_DMASTER_ADDR) },	/* MSW of Local Base Address for Direct Master-to-PCI Memory DMLBAM[31:16] */
+	{ 0x36,LOW_WORD(PATI_DMASTER_ADDR) },	/* LSW of Local Base Address for Direct Master-to-PCI Memory (Reserved) DMLBAM[15:0] */
+	{ 0x38,0x0000 },	/* MSW of Local Bus Address for Direct Master-to-PCI I/O Configuration DMLBAI[31:16] */
+	{ 0x3A,0x0000 },	/* LSW of Local Bus Address for Direct Master-to-PCI I/O Configuration (Reserved) DMLBAI[15:0] */
+	{ 0x3C,0x0000 },	/* MSW of PCI Base Address (Remap) for Direct Master-to-PCI Memory DMPBAM[31:16] */
+	{ 0x3E,0x0000 },	/* LSW of PCI Base Address (Remap) for Direct Master-to-PCI Memory DMPBAM[15:0] */
+	{ 0x40,0x0000 },	/* MSW of PCI Configuration Address for Direct Master-to-PCI I/O Configuration DMCFGA[31, 23:16] Reserved [30:24]*/
+	{ 0x42,0x0000 },	/* LSW of PCI Configuration Address for Direct Master-to-PCI I/O Configuration DMCFGA[15:0] */
+	{ 0x44,0x0000 },	/* PCI Subsystem ID PCISID[15:0] */
+	{ 0x46,0x0000 },	/* PCI Subsystem Vendor ID PCISVID[15:0] */
+	{ 0x48,HIGH_WORD(PATI_LOC_SDRAM_MASK) },	/* MSW of Direct Slave Local Address Space 1 Range (1 MB) LAS1RR[31:16] */
+	{ 0x4A,LOW_WORD(PATI_LOC_SDRAM_MASK) },	/* LSW of Direct Slave Local Address Space 1 Range (1 MB) LAS1RR[15:0] */
+	{ 0x4C,HIGH_WORD(PATI_LOC_SDRAM_ADDR) },	/* MSW of Direct Slave Local Address Space 1 Local Base Address (Remap) LAS1BA[31:16] (SDRAM) */
+	{ 0x4E,LOW_WORD(PATI_LOC_SDRAM_ADDR) | 0x1 },	/* LSW of Direct Slave Local Address Space 1 Local Base Address (Remap) LAS1BA[15:2, 0], Reserved [1] */
+	{ 0x50,HIGH_WORD(PATI_LOC_SDRAM_SPACE1_ATTR) },	/* MSW of Local Address Space 1 Bus Region Descriptor LBRD1[31:16] */
+	{ 0x52,LOW_WORD(PATI_LOC_SDRAM_SPACE1_ATTR) },	/* LSW of Local Address Space 1 Bus Region Descriptor (Reserved) LBRD1[15:0] */
+	{ 0x54,0x0000 },	/* Hot Swap Control/Status (Reserved) Reserved */
+	{ 0x56,0x0000 },	/* Hot Swap Next Capability Pointer / Hot Swap Control HS_NEXT[7:0] / HS_CNTL[7:0] */
+	{ 0x58,0x0000 },	/* Reserved Reserved */
+	{ 0x5A,0x0000 },	/* PCI Arbiter Control PCIARB[3:0], Reserved [15:4] */
+	{ 0x5C,0x0000 },	/* Power Management Capabilities PMC[15:9, 2:0] */
+	{ 0x5E,0x0000 },	/* Power Management Next Capability Pointer (Reserved) / Power Management Capability ID (Reserved) Reserved*/
+	{ 0x60,0x0000 },	/* Power Management Data / PMCSR Bridge Support Extension (Reserved) PMDATA[7:0] / Reserved */
+	{ 0x62,0x0000 },	/* Power Management Control/Status PMCSR[14:8] */
+	{ 0xFFFF,0xFFFF}	/* terminaror */
 };
 #define PATI_EEPROM_LAST_OFFSET	0x64
 #endif /* #ifndef __PCI_EEPROM_H_ */
diff --git a/board/mpl/pip405/cmd_pip405.c b/board/mpl/pip405/cmd_pip405.c
index 1bf4d7bd87..945e5c9584 100644
--- a/board/mpl/pip405/cmd_pip405.c
+++ b/board/mpl/pip405/cmd_pip405.c
@@ -38,14 +38,14 @@ extern int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
 int do_pip405(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
 
- 	ulong led_on,led_nr;
+	ulong led_on,led_nr;
 
 	if (strcmp(argv[1], "info") == 0)
 	{
 		print_pip405_info();
-	 	return 0;
-   	}
- 	if (strcmp(argv[1], "led") == 0)
+		return 0;
+	}
+	if (strcmp(argv[1], "led") == 0)
 	{
 		led_nr = (ulong)simple_strtoul(argv[2], NULL, 10);
 		led_on = (ulong)simple_strtoul(argv[3], NULL, 10);
@@ -54,7 +54,7 @@ int do_pip405(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 		else
 			user_led1(led_on);
 		return 0;
-   	}
+	}
 
 	return (do_mplcommon(cmdtp, flag, argc, argv));
 }
diff --git a/board/mpl/pip405/pip405.h b/board/mpl/pip405/pip405.h
index b41c5bb282..5815786ebf 100644
--- a/board/mpl/pip405/pip405.h
+++ b/board/mpl/pip405/pip405.h
@@ -56,7 +56,7 @@ void user_led1(unsigned char on);
 /* timings */
 
 /* CS Config register (CS7) */
-#define CONFIG_PORT_BME	0 	/* Burst disable */
+#define CONFIG_PORT_BME	0	/* Burst disable */
 #define CONFIG_PORT_TWE	255	/* 255 * 30ns 120ns Waitstates (access=TWT+1+TH) */
 #define CONFIG_PORT_CSN	1	/* Chipselect is driven inactive for 1 Cycle BTW transfers */
 #define CONFIG_PORT_OEN	1	/* Cycles from CS low to OE low   */
@@ -67,7 +67,7 @@ void user_led1(unsigned char on);
 #define CONFIG_PORT_SOR	1	/* Sample on Ready disabled */
 #define CONFIG_PORT_BEM	0	/* Byte Write only active on Write cycles */
 #define CONFIG_PORT_PEN	0	/* Parity disable */
-#define CONFIG_PORT_AP 	((CONFIG_PORT_BME << 31) + (CONFIG_PORT_TWE << 23) + (CONFIG_PORT_CSN << 18) + (CONFIG_PORT_OEN << 16) + (CONFIG_PORT_WBN << 14) + \
+#define CONFIG_PORT_AP	((CONFIG_PORT_BME << 31) + (CONFIG_PORT_TWE << 23) + (CONFIG_PORT_CSN << 18) + (CONFIG_PORT_OEN << 16) + (CONFIG_PORT_WBN << 14) + \
 				(CONFIG_PORT_WBF << 12) + (CONFIG_PORT_TH << 9) + (CONFIG_PORT_RE << 8) + (CONFIG_PORT_SOR << 7) + (CONFIG_PORT_BEM << 6) + (CONFIG_PORT_PEN << 5))
 
 /* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
@@ -80,10 +80,10 @@ void user_led1(unsigned char on);
 
 /* Flash CS0 or CS 1 */
 /* 0x7F8FFE80 slowest timing at all... */
-#define FLASH_BME_B	1 	/* Burst enable */
+#define FLASH_BME_B	1	/* Burst enable */
 #define FLASH_FWT_B	0x6	/* 6 * 30ns 210ns First Wait Access */
 #define FLASH_BWT_B	0x6	/* 6 * 30ns 210ns Burst Wait Access */
-#define FLASH_BME	0 	/* Burst disable */
+#define FLASH_BME	0	/* Burst disable */
 #define FLASH_TWE	0xb/* 11 * 30ns 330ns Waitstates (access=TWT+1+TH) */
 #define FLASH_CSN	0	/* Chipselect is driven inactive for 1 Cycle BTW transfers */
 #define FLASH_OEN	1	/* Cycles from CS low to OE low   */
@@ -95,10 +95,10 @@ void user_led1(unsigned char on);
 #define FLASH_BEM	0	/* Byte Write only active on Write cycles */
 #define FLASH_PEN	0	/* Parity disable */
 /* Access Parameter Register for non Boot */
-#define FLASH_AP 	((FLASH_BME << 31) + (FLASH_TWE << 23) + (FLASH_CSN << 18) + (FLASH_OEN << 16) + (FLASH_WBN << 14) + \
+#define FLASH_AP	((FLASH_BME << 31) + (FLASH_TWE << 23) + (FLASH_CSN << 18) + (FLASH_OEN << 16) + (FLASH_WBN << 14) + \
 				(FLASH_WBF << 12) + (FLASH_TH << 9) + (FLASH_RE << 8) + (FLASH_SOR << 7) + (FLASH_BEM << 6) + (FLASH_PEN << 5))
 /* Access Parameter Register for Boot */
-#define FLASH_AP_B 	((FLASH_BME_B << 31) + (FLASH_FWT_B << 26) + (FLASH_BWT_B << 23) + (FLASH_CSN << 18) + (FLASH_OEN << 16) + (FLASH_WBN << 14) + \
+#define FLASH_AP_B	((FLASH_BME_B << 31) + (FLASH_FWT_B << 26) + (FLASH_BWT_B << 23) + (FLASH_CSN << 18) + (FLASH_OEN << 16) + (FLASH_WBN << 14) + \
 				(FLASH_WBF << 12) + (FLASH_TH << 9) + (FLASH_RE << 8) + (FLASH_SOR << 7) + (FLASH_BEM << 6) + (FLASH_PEN << 5))
 
 /* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
@@ -114,10 +114,10 @@ void user_led1(unsigned char on);
 
 /* MPS CS1 or CS0 */
 /* Boot CS: */
-#define MPS_BME_B	1 	/* Burst enable */
+#define MPS_BME_B	1	/* Burst enable */
 #define MPS_FWT_B	0x6/* 6 * 30ns 210ns First Wait Access */
 #define MPS_BWT_B	0x6	/* 6 * 30ns 210ns Burst Wait Access */
-#define MPS_BME		0 	/* Burst disable */
+#define MPS_BME		0	/* Burst disable */
 #define MPS_TWE		0xb/* 11 * 30ns 330ns Waitstates (access=TWT+1+TH) */
 #define MPS_CSN		0	/* Chipselect is driven inactive for 1 Cycle BTW transfers */
 #define MPS_OEN		1	/* Cycles from CS low to OE low   */
@@ -129,10 +129,10 @@ void user_led1(unsigned char on);
 #define MPS_BEM		0	/* Byte Write only active on Write cycles */
 #define MPS_PEN		0	/* Parity disable */
 /* Access Parameter Register for non Boot */
-#define MPS_AP 		((MPS_BME << 31) + (MPS_TWE << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \
+#define MPS_AP		((MPS_BME << 31) + (MPS_TWE << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \
 				(MPS_WBF << 12) + (MPS_TH << 9) + (MPS_RE << 8) + (MPS_SOR << 7) + (MPS_BEM << 6) + (MPS_PEN << 5))
 /* Access Parameter Register for Boot */
-#define MPS_AP_B 	((MPS_BME_B << 31) + (MPS_FWT_B << 26) + (MPS_BWT_B << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \
+#define MPS_AP_B	((MPS_BME_B << 31) + (MPS_FWT_B << 26) + (MPS_BWT_B << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \
 				(MPS_WBF << 12) + (MPS_TH << 9) + (MPS_RE << 8) + (MPS_SOR << 7) + (MPS_BEM << 6) + (MPS_PEN << 5))
 
 /* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
diff --git a/board/mpl/pip405/u-boot.lds b/board/mpl/pip405/u-boot.lds
index c7ae4d07bc..fb710649a5 100644
--- a/board/mpl/pip405/u-boot.lds
+++ b/board/mpl/pip405/u-boot.lds
@@ -38,11 +38,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/mpl/pip405/u-boot.lds.debug b/board/mpl/pip405/u-boot.lds.debug
index 88dcaf91bf..0552994f40 100644
--- a/board/mpl/pip405/u-boot.lds.debug
+++ b/board/mpl/pip405/u-boot.lds.debug
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/mpl/vcma9/cmd_vcma9.c b/board/mpl/vcma9/cmd_vcma9.c
index 90a1b08e24..d3629c5899 100644
--- a/board/mpl/vcma9/cmd_vcma9.c
+++ b/board/mpl/vcma9/cmd_vcma9.c
@@ -58,8 +58,8 @@ int do_vcma9(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	if (strcmp(argv[1], "info") == 0)
 	{
 		print_vcma9_info();
-	 	return 0;
-   	}
+		return 0;
+	}
 #if defined(CONFIG_DRIVER_CS8900)
 	if (strcmp(argv[1], "cs8900") == 0) {
 		if (strcmp(argv[2], "read") == 0) {
diff --git a/board/mpl/vcma9/lowlevel_init.S b/board/mpl/vcma9/lowlevel_init.S
index a02335314b..e3af073094 100644
--- a/board/mpl/vcma9/lowlevel_init.S
+++ b/board/mpl/vcma9/lowlevel_init.S
@@ -39,92 +39,92 @@
 #define SDRAM_REG	0x2C000106
 
 /* BWSCON */
-#define DW8		 	(0x0)
-#define DW16		 	(0x1)
-#define DW32		 	(0x2)
-#define WAIT		 	(0x1<<2)
-#define UBLB		 	(0x1<<3)
+#define DW8			(0x0)
+#define DW16			(0x1)
+#define DW32			(0x2)
+#define WAIT			(0x1<<2)
+#define UBLB			(0x1<<3)
 
 /* BANKSIZE */
 #define BURST_EN		(0x1<<7)
 
-#define B1_BWSCON	  	(DW16)
-#define B2_BWSCON	  	(DW32)
-#define B3_BWSCON	  	(DW32)
-#define B4_BWSCON	  	(DW16 + WAIT + UBLB)
-#define B5_BWSCON	  	(DW8 + UBLB)
-#define B6_BWSCON	  	(DW32)
-#define B7_BWSCON	  	(DW32)
+#define B1_BWSCON		(DW16)
+#define B2_BWSCON		(DW32)
+#define B3_BWSCON		(DW32)
+#define B4_BWSCON		(DW16 + WAIT + UBLB)
+#define B5_BWSCON		(DW8 + UBLB)
+#define B6_BWSCON		(DW32)
+#define B7_BWSCON		(DW32)
 
 /* BANK0CON */
-#define B0_Tacs		 	0x0	/*  0clk */
-#define B0_Tcos		 	0x1	/*  1clk */
+#define B0_Tacs			0x0	/*  0clk */
+#define B0_Tcos			0x1	/*  1clk */
 /*#define B0_Tcos		0x0	  0clk */
-#define B0_Tacc		 	0x7	/*  14clk */
+#define B0_Tacc			0x7	/*  14clk */
 /*#define B0_Tacc		0x5	  8clk */
-#define B0_Tcoh		 	0x0	/*  0clk */
-#define B0_Tah		 	0x0	/*  0clk */
-#define B0_Tacp		 	0x0     /* page mode is not used */
-#define B0_PMC		 	0x0	/* page mode disabled */
+#define B0_Tcoh			0x0	/*  0clk */
+#define B0_Tah			0x0	/*  0clk */
+#define B0_Tacp			0x0     /* page mode is not used */
+#define B0_PMC			0x0	/* page mode disabled */
 
 /* BANK1CON */
-#define B1_Tacs		 	0x0	/*  0clk */
-#define B1_Tcos		 	0x1	/*  1clk */
+#define B1_Tacs			0x0	/*  0clk */
+#define B1_Tcos			0x1	/*  1clk */
 /*#define B1_Tcos		0x0	  0clk */
 #define B1_Tacc			0x7	/*  14clk */
 /*#define B1_Tacc		0x5	  8clk */
-#define B1_Tcoh		 	0x0	/*  0clk */
-#define B1_Tah		 	0x0	/*  0clk */
-#define B1_Tacp		 	0x0     /* page mode is not used */
-#define B1_PMC		 	0x0	/* page mode disabled */
-
-#define B2_Tacs		 	0x3	/*  4clk */
-#define B2_Tcos		 	0x3	/*  4clk */
-#define B2_Tacc		 	0x7     /* 14clk */
-#define B2_Tcoh		 	0x3	/*  4clk */
-#define B2_Tah		 	0x3	/*  4clk */
-#define B2_Tacp		 	0x0	/* page mode is not used */
-#define B2_PMC		 	0x0     /* page mode disabled */
-
-#define B3_Tacs		 	0x3	/*  4clk */
-#define B3_Tcos		 	0x3	/*  4clk */
-#define B3_Tacc		 	0x7     /* 14clk */
-#define B3_Tcoh		 	0x3	/*  4clk */
-#define B3_Tah		 	0x3	/*  4clk */
-#define B3_Tacp		 	0x0	/* page mode is not used */
-#define B3_PMC		 	0x0     /* page mode disabled */
-
-#define B4_Tacs		 	0x3	/*  4clk */
-#define B4_Tcos		 	0x1	/*  1clk */
-#define B4_Tacc		 	0x7	/* 14clk */
-#define B4_Tcoh		 	0x1	/*  1clk */
-#define B4_Tah		 	0x0	/*  0clk */
-#define B4_Tacp		 	0x0     /* page mode is not used */
-#define B4_PMC		 	0x0	/* page mode disabled */
-
-#define B5_Tacs		 	0x0	/*  0clk */
-#define B5_Tcos		 	0x3	/*  4clk */
-#define B5_Tacc		 	0x5	/*  8clk */
-#define B5_Tcoh		 	0x2	/*  2clk */
-#define B5_Tah		 	0x1	/*  1clk */
-#define B5_Tacp		 	0x0     /* page mode is not used */
-#define B5_PMC		 	0x0	/* page mode disabled */
-
-#define B6_MT		 	0x3	/* SDRAM */
-#define B6_Trcd	 	 	0x1	/* 3clk */
-#define B6_SCAN		 	0x2	/* 10bit */
-
-#define B7_MT		 	0x3	/* SDRAM */
-#define B7_Trcd		 	0x1	/* 3clk */
-#define B7_SCAN		 	0x2	/* 10bit */
+#define B1_Tcoh			0x0	/*  0clk */
+#define B1_Tah			0x0	/*  0clk */
+#define B1_Tacp			0x0     /* page mode is not used */
+#define B1_PMC			0x0	/* page mode disabled */
+
+#define B2_Tacs			0x3	/*  4clk */
+#define B2_Tcos			0x3	/*  4clk */
+#define B2_Tacc			0x7     /* 14clk */
+#define B2_Tcoh			0x3	/*  4clk */
+#define B2_Tah			0x3	/*  4clk */
+#define B2_Tacp			0x0	/* page mode is not used */
+#define B2_PMC			0x0     /* page mode disabled */
+
+#define B3_Tacs			0x3	/*  4clk */
+#define B3_Tcos			0x3	/*  4clk */
+#define B3_Tacc			0x7     /* 14clk */
+#define B3_Tcoh			0x3	/*  4clk */
+#define B3_Tah			0x3	/*  4clk */
+#define B3_Tacp			0x0	/* page mode is not used */
+#define B3_PMC			0x0     /* page mode disabled */
+
+#define B4_Tacs			0x3	/*  4clk */
+#define B4_Tcos			0x1	/*  1clk */
+#define B4_Tacc			0x7	/* 14clk */
+#define B4_Tcoh			0x1	/*  1clk */
+#define B4_Tah			0x0	/*  0clk */
+#define B4_Tacp			0x0     /* page mode is not used */
+#define B4_PMC			0x0	/* page mode disabled */
+
+#define B5_Tacs			0x0	/*  0clk */
+#define B5_Tcos			0x3	/*  4clk */
+#define B5_Tacc			0x5	/*  8clk */
+#define B5_Tcoh			0x2	/*  2clk */
+#define B5_Tah			0x1	/*  1clk */
+#define B5_Tacp			0x0     /* page mode is not used */
+#define B5_PMC			0x0	/* page mode disabled */
+
+#define B6_MT			0x3	/* SDRAM */
+#define B6_Trcd			0x1	/* 3clk */
+#define B6_SCAN			0x2	/* 10bit */
+
+#define B7_MT			0x3	/* SDRAM */
+#define B7_Trcd			0x1	/* 3clk */
+#define B7_SCAN			0x2	/* 10bit */
 
 /* REFRESH parameter */
-#define REFEN		 	0x1	/* Refresh enable */
-#define TREFMD		 	0x0	/* CBR(CAS before RAS)/Auto refresh */
-#define Trp		 	0x0	/* 2clk */
-#define Trc		 	0x3	/* 7clk */
-#define Tchr		 	0x2	/* 3clk */
-#define REFCNT		 	1113	/* period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) */
+#define REFEN			0x1	/* Refresh enable */
+#define TREFMD			0x0	/* CBR(CAS before RAS)/Auto refresh */
+#define Trp			0x0	/* 2clk */
+#define Trc			0x3	/* 7clk */
+#define Tchr			0x2	/* 3clk */
+#define REFCNT			1113	/* period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) */
 /**************************************/
 
 _TEXT_BASE:
diff --git a/board/ms7722se/lowlevel_init.S b/board/ms7722se/lowlevel_init.S
index 2024e27ffe..332f65a4ce 100644
--- a/board/ms7722se/lowlevel_init.S
+++ b/board/ms7722se/lowlevel_init.S
@@ -114,11 +114,11 @@ bsc_init:
 	mov.w	r0, @r1
 
 	mov.l	CMNCR_A, r1	! CMNCR address -> R1
-	mov.l 	CMNCR_D, r0	! CMNCR data    -> R0
+	mov.l	CMNCR_D, r0	! CMNCR data    -> R0
 	mov.l	r0, @r1		! CMNCR set
 
 	mov.l	CS0BCR_A, r1	! CS0BCR address -> R1
-	mov.l 	CS0BCR_D, r0	! CS0BCR data    -> R0
+	mov.l	CS0BCR_D, r0	! CS0BCR data    -> R0
 	mov.l	r0, @r1		! CS0BCR set
 
 	mov.l	CS2BCR_A, r1	! CS2BCR address -> R1
@@ -130,39 +130,39 @@ bsc_init:
 	mov.l	r0, @r1		! CS4BCR set
 
 	mov.l	CS5ABCR_A, r1	! CS5ABCR address -> R1
-	mov.l 	CS5ABCR_D, r0	! CS5ABCR data    -> R0
+	mov.l	CS5ABCR_D, r0	! CS5ABCR data    -> R0
 	mov.l	r0, @r1		! CS5ABCR set
 
 	mov.l	CS5BBCR_A, r1	! CS5BBCR address -> R1
-	mov.l 	CS5BBCR_D, r0	! CS5BBCR data    -> R0
+	mov.l	CS5BBCR_D, r0	! CS5BBCR data    -> R0
 	mov.l	r0, @r1		! CS5BBCR set
 
 	mov.l	CS6ABCR_A, r1	! CS6ABCR address -> R1
-	mov.l 	CS6ABCR_D, r0	! CS6ABCR data    -> R0
+	mov.l	CS6ABCR_D, r0	! CS6ABCR data    -> R0
 	mov.l	r0, @r1		! CS6ABCR set
 
 	mov.l	CS0WCR_A, r1	! CS0WCR address -> R1
-	mov.l 	CS0WCR_D, r0	! CS0WCR data    -> R0
+	mov.l	CS0WCR_D, r0	! CS0WCR data    -> R0
 	mov.l	r0, @r1		! CS0WCR set
 
 	mov.l	CS2WCR_A, r1	! CS2WCR address -> R1
-	mov.l 	CS2WCR_D, r0	! CS2WCR data    -> R0
+	mov.l	CS2WCR_D, r0	! CS2WCR data    -> R0
 	mov.l	r0, @r1		! CS2WCR set
 
 	mov.l	CS4WCR_A, r1	! CS4WCR address -> R1
-	mov.l 	CS4WCR_D, r0	! CS4WCR data    -> R0
+	mov.l	CS4WCR_D, r0	! CS4WCR data    -> R0
 	mov.l	r0, @r1		! CS4WCR set
 
 	mov.l	CS5AWCR_A, r1	! CS5AWCR address -> R1
-	mov.l 	CS5AWCR_D, r0	! CS5AWCR data    -> R0
+	mov.l	CS5AWCR_D, r0	! CS5AWCR data    -> R0
 	mov.l	r0, @r1		! CS5AWCR set
 
 	mov.l	CS5BWCR_A, r1	! CS5BWCR address -> R1
-	mov.l 	CS5BWCR_D, r0	! CS5BWCR data    -> R0
+	mov.l	CS5BWCR_D, r0	! CS5BWCR data    -> R0
 	mov.l	r0, @r1		! CS5BWCR set
 
 	mov.l	CS6AWCR_A, r1	! CS6AWCR address -> R1
-	mov.l 	CS6AWCR_D, r0	! CS6AWCR data    -> R0
+	mov.l	CS6AWCR_D, r0	! CS6AWCR data    -> R0
 	mov.l	r0, @r1		! CS6AWCR set
 
 	! SDRAM initialization
@@ -187,7 +187,7 @@ bsc_init:
 	mov.l	r0, @r1		! SB_RTCSR set
 
 	mov.l	SDMR3_A, r1	! SDMR3 address -> R1
-	mov 	#0x00, r0	! SDMR3 data    -> R0
+	mov	#0x00, r0	! SDMR3 data    -> R0
 	mov.b	r0, @r1		! SDMR3 set
 
 	! BL bit off (init = ON)  (?!?)
diff --git a/board/munices/u-boot.lds b/board/munices/u-boot.lds
index 6fe615bedf..e9b3be8ea3 100644
--- a/board/munices/u-boot.lds
+++ b/board/munices/u-boot.lds
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/musenki/musenki.c b/board/musenki/musenki.c
index 88ef83ac12..4408b07c55 100644
--- a/board/musenki/musenki.c
+++ b/board/musenki/musenki.c
@@ -35,7 +35,7 @@ int checkboard (void)
 
 }
 
-#if 0 	/* NOT USED */
+#if 0	/* NOT USED */
 int checkflash (void)
 {
 	/* TODO: XXX XXX XXX */
diff --git a/board/mvblue/flash.c b/board/mvblue/flash.c
index 8df573aa0b..0c0738cf27 100644
--- a/board/mvblue/flash.c
+++ b/board/mvblue/flash.c
@@ -337,9 +337,9 @@ static ulong flash_get_size (vu_long *address, flash_info_t *info)
 #define ERASE_DATA4 ERASE_DATA1
 #define ERASE_DATA5 ERASE_DATA2
 
-#define ERASE_SECTOR_DATA 	(0x00300030 & FLASH_DATA_MASK)
-#define ERASE_CHIP_DATA 	(0x00100010 & FLASH_DATA_MASK)
-#define ERASE_CONFIRM_DATA 	(0x00800080 & FLASH_DATA_MASK)
+#define ERASE_SECTOR_DATA	(0x00300030 & FLASH_DATA_MASK)
+#define ERASE_CHIP_DATA		(0x00100010 & FLASH_DATA_MASK)
+#define ERASE_CONFIRM_DATA	(0x00800080 & FLASH_DATA_MASK)
 
 int	flash_erase (flash_info_t *info, int s_first, int s_last)
 {
@@ -559,7 +559,7 @@ static int write_char (flash_info_t *info, ulong dest, uchar data)
 			return (1);
 		}
 	}
- 	mvdebug (("-write_byte\n"));
+	mvdebug (("-write_byte\n"));
 	return (0);
 }
 
@@ -577,7 +577,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data)
 	mvdebug (("+write_word : 0x%08lx @ 0x%08lx\n", data, dest));
 	for ( i=0; (i < 4) && (result == 0); i++, dest+=1 )
 		result = write_char (info, dest, (data >> (8*(3-i))) & 0xff );
- 	mvdebug (("-write_word\n"));
+	mvdebug (("-write_word\n"));
 	return result;
 }
 /*---------------------------------------------------------------- */
diff --git a/board/mvs1/flash.c b/board/mvs1/flash.c
index 0845943587..a52fe55b09 100644
--- a/board/mvs1/flash.c
+++ b/board/mvs1/flash.c
@@ -649,7 +649,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data)
 		}
 	}
 
- 	mvdebug (("-write_word\n"));
+	mvdebug (("-write_word\n"));
 	return (0);
 }
 #else /* CONFIG_MVS_16BIT_FLASH */
@@ -691,7 +691,7 @@ static int write_halfword (flash_info_t *info, ulong dest, ushort data)
 			return (1);
 		}
 	}
- 	mvdebug (("-write_halfword\n"));
+	mvdebug (("-write_halfword\n"));
 	return (0);
 }
 
diff --git a/board/mvs1/u-boot.lds b/board/mvs1/u-boot.lds
index 76dfebae3a..55a9c3ae85 100644
--- a/board/mvs1/u-boot.lds
+++ b/board/mvs1/u-boot.lds
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)	}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)	}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)	}
   .rela.got      : { *(.rela.got)	}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/mvs1/u-boot.lds.debug b/board/mvs1/u-boot.lds.debug
index 753411fcbf..c33581d250 100644
--- a/board/mvs1/u-boot.lds.debug
+++ b/board/mvs1/u-boot.lds.debug
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/mx1ads/lowlevel_init.S b/board/mx1ads/lowlevel_init.S
index 09c260d64d..6967fb2b41 100644
--- a/board/mx1ads/lowlevel_init.S
+++ b/board/mx1ads/lowlevel_init.S
@@ -35,7 +35,7 @@ _TEXT_BASE:
 
 .globl lowlevel_init
 lowlevel_init:
-/* memory controller init	 	*/
+/* memory controller init		*/
 
 	ldr  r1, =SDCTL0
 
@@ -50,7 +50,7 @@ lowlevel_init:
 	ldr  r3, =0x8200000
 	ldr  r2, [r3]
 
-/* Set AutoRefresh Command 		*/
+/* Set AutoRefresh Command		*/
 	ldr  r3, =0xA2120200
 	str  r3, [r1]
 
@@ -65,17 +65,17 @@ lowlevel_init:
 	ldr  r2, [r3]
 	ldr  r2, [r3]
 
-/* Set Mode Register 			*/
+/* Set Mode Register			*/
 	ldr  r3, =0xB2120200
 	str  r3, [r1]
 
 /* Issue Mode Register Command		*/
-	ldr  r3, =0x08111800 	/* Mode Register Value 		*/
+	ldr  r3, =0x08111800	/* Mode Register Value		*/
 	ldr  r2, [r3]
 
 /* Set Normal Mode			*/
 	ldr  r3, =0x82124200
 	str  r3, [r1]
 
-/* everything is fine now 		*/
+/* everything is fine now		*/
 	mov	pc, lr
diff --git a/board/mx1ads/mx1ads.c b/board/mx1ads/mx1ads.c
index abf2fd51e9..ba152e2e88 100644
--- a/board/mx1ads/mx1ads.c
+++ b/board/mx1ads/mx1ads.c
@@ -85,8 +85,8 @@ int board_init (void)
 
 	GPCR = 0x000003AB;	/* I/O pad driving strength     */
 
-	/*	MX1_CS1U 	= 0x00000A00;	*/ /* SRAM initialization          */
-/*	MX1_CS1L 	= 0x11110601; 	*/
+	/*	MX1_CS1U	= 0x00000A00;	*/ /* SRAM initialization          */
+/*	MX1_CS1L	= 0x11110601;	*/
 
 	MPCTL0 = 0x04632410;	/* setting for 150 MHz MCU PLL CLK      */
 
diff --git a/board/mx1ads/syncflash.c b/board/mx1ads/syncflash.c
index eb7fde5071..fae9fbb39d 100644
--- a/board/mx1ads/syncflash.c
+++ b/board/mx1ads/syncflash.c
@@ -40,13 +40,13 @@ flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips    */
 #define SYNCFLASH_A10		(0x00100000)
 
 #define CMD_NORMAL		(0x81020300)			/* Normal Mode			*/
-#define CMD_PREC		(CMD_NORMAL + 0x10000000) 	/* Precharge Command		*/
-#define CMD_AUTO		(CMD_NORMAL + 0x20000000) 	/* Auto Refresh Command		*/
-#define CMD_LMR			(CMD_NORMAL + 0x30000000) 	/* Load Mode Register Command 	*/
-#define CMD_LCR			(CMD_NORMAL + 0x60000000) 	/* LCR Command			*/
+#define CMD_PREC		(CMD_NORMAL + 0x10000000)	/* Precharge Command		*/
+#define CMD_AUTO		(CMD_NORMAL + 0x20000000)	/* Auto Refresh Command		*/
+#define CMD_LMR			(CMD_NORMAL + 0x30000000)	/* Load Mode Register Command	*/
+#define CMD_LCR			(CMD_NORMAL + 0x60000000)	/* LCR Command			*/
 #define CMD_PROGRAM		(CMD_NORMAL + 0x70000000)
 
-#define MODE_REG_VAL		(CFG_FLASH_BASE+0x0008CC00) 	/* Cas Latency 3		*/
+#define MODE_REG_VAL		(CFG_FLASH_BASE+0x0008CC00)	/* Cas Latency 3		*/
 
 /* LCR Command */
 #define LCR_READSTATUS		(0x0001C000)			/* 0x70				*/
@@ -55,22 +55,22 @@ flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips    */
 #define LCR_PROG_NVMODE		(0x00028000)			/* 0xA0				*/
 #define LCR_SR_CLEAR		(0x00014000)			/* 0x50				*/
 
-/* Get Status register 			*/
+/* Get Status register			*/
 u32 SF_SR(void) {
 	u32 tmp,tmp1;
 
 	reg_SFCTL	= CMD_PROGRAM;
-	tmp 		= __REG(CFG_FLASH_BASE);
+	tmp		= __REG(CFG_FLASH_BASE);
 
 	reg_SFCTL	= CMD_NORMAL;
 
-	reg_SFCTL	= CMD_LCR;			/* Activate LCR Mode 		*/
-	tmp1 		= __REG(CFG_FLASH_BASE + LCR_SR_CLEAR);
+	reg_SFCTL	= CMD_LCR;			/* Activate LCR Mode		*/
+	tmp1		= __REG(CFG_FLASH_BASE + LCR_SR_CLEAR);
 
 	return tmp;
 }
 
-/* check if SyncFlash is ready 		*/
+/* check if SyncFlash is ready		*/
 u8 SF_Ready(void) {
 	u32 tmp;
 
@@ -84,19 +84,19 @@ u8 SF_Ready(void) {
 		printf ("SyncFlash Error code %08x\n",tmp);
 	};
 
-	if (tmp == 0x00800080) 		/* Test Bit 7 of SR	*/
+	if (tmp == 0x00800080)		/* Test Bit 7 of SR	*/
 		return 1;
 	else
 		return 0;
 }
 
-/* Issue the precharge all command 		*/
+/* Issue the precharge all command		*/
 void SF_PrechargeAll(void) {
 
 	u32 tmp;
 
-	reg_SFCTL	= CMD_PREC;			/* Set Precharge Command 	*/
-	tmp 		= __REG(CFG_FLASH_BASE + SYNCFLASH_A10); /* Issue Precharge All Command */
+	reg_SFCTL	= CMD_PREC;			/* Set Precharge Command	*/
+	tmp		= __REG(CFG_FLASH_BASE + SYNCFLASH_A10); /* Issue Precharge All Command */
 }
 
 /* set SyncFlash to normal mode			*/
@@ -107,21 +107,21 @@ void SF_Normal(void) {
 	reg_SFCTL	= CMD_NORMAL;
 }
 
-/* Erase SyncFlash 				*/
+/* Erase SyncFlash				*/
 void SF_Erase(u32 RowAddress) {
 	u32 tmp;
 
 	reg_SFCTL	= CMD_NORMAL;
-	tmp 		= __REG(RowAddress);
+	tmp		= __REG(RowAddress);
 
 	reg_SFCTL	= CMD_PREC;
-	tmp 		= __REG(RowAddress);
+	tmp		= __REG(RowAddress);
 
-	reg_SFCTL 	= CMD_LCR;			/* Set LCR mode 		*/
-	__REG(RowAddress + LCR_ERASE_CONFIRM)	= 0;	/* Issue Erase Setup Command 	*/
+	reg_SFCTL	= CMD_LCR;			/* Set LCR mode		*/
+	__REG(RowAddress + LCR_ERASE_CONFIRM)	= 0;	/* Issue Erase Setup Command	*/
 
-	reg_SFCTL	= CMD_NORMAL;			/* return to Normal mode 	*/
-	__REG(RowAddress)	= 0xD0D0D0D0; 		/* Confirm			*/
+	reg_SFCTL	= CMD_NORMAL;			/* return to Normal mode	*/
+	__REG(RowAddress)	= 0xD0D0D0D0;		/* Confirm			*/
 
 	while(!SF_Ready());
 }
@@ -132,8 +132,8 @@ void SF_NvmodeErase(void) {
 	reg_SFCTL	= CMD_LCR;			/* Set to LCR mode		*/
 	__REG(CFG_FLASH_BASE + LCR_ERASE_NVMODE)  = 0;	/* Issue Erase Nvmode Reg Command */
 
-	reg_SFCTL	= CMD_NORMAL;			/* Return to Normal mode 	*/
-	__REG(CFG_FLASH_BASE + LCR_ERASE_NVMODE) = 0xC0C0C0C0;	/* Confirm 		*/
+	reg_SFCTL	= CMD_NORMAL;			/* Return to Normal mode	*/
+	__REG(CFG_FLASH_BASE + LCR_ERASE_NVMODE) = 0xC0C0C0C0;	/* Confirm		*/
 
 	while(!SF_Ready());
 }
@@ -141,11 +141,11 @@ void SF_NvmodeErase(void) {
 void SF_NvmodeWrite(void) {
 	SF_PrechargeAll();
 
-	reg_SFCTL 	= CMD_LCR;			/* Set to LCR mode 		*/
+	reg_SFCTL	= CMD_LCR;			/* Set to LCR mode		*/
 	__REG(CFG_FLASH_BASE+LCR_PROG_NVMODE) = 0;	/* Issue Program Nvmode reg command */
 
-	reg_SFCTL	= CMD_NORMAL;			/* Return to Normal mode 	*/
-	__REG(CFG_FLASH_BASE+LCR_PROG_NVMODE) = 0xC0C0C0C0; 	/* Confirm not needed 	*/
+	reg_SFCTL	= CMD_NORMAL;			/* Return to Normal mode	*/
+	__REG(CFG_FLASH_BASE+LCR_PROG_NVMODE) = 0xC0C0C0C0;	/* Confirm not needed	*/
 }
 
 /****************************************************************************************/
@@ -156,19 +156,19 @@ ulong flash_init(void) {
 
 /* Turn on CSD1 for negating RESETSF of SyncFLash */
 
-	reg_SFCTL 	|= 0x80000000;		/* enable CSD1 for SyncFlash 		*/
+	reg_SFCTL	|= 0x80000000;		/* enable CSD1 for SyncFlash		*/
 	udelay(200);
 
-	reg_SFCTL 	= CMD_LMR;		/* Set Load Mode Register Command 	*/
-	tmp 		= __REG(MODE_REG_VAL);	/* Issue Load Mode Register Command 	*/
+	reg_SFCTL	= CMD_LMR;		/* Set Load Mode Register Command	*/
+	tmp		= __REG(MODE_REG_VAL);	/* Issue Load Mode Register Command	*/
 
 	SF_Normal();
 
 	i = 0;
 
-	flash_info[i].flash_id 	=  FLASH_MAN_MT | FLASH_MT28S4M16LC;
+	flash_info[i].flash_id	=  FLASH_MAN_MT | FLASH_MT28S4M16LC;
 
-	flash_info[i].size 	= FLASH_BANK_SIZE;
+	flash_info[i].size	= FLASH_BANK_SIZE;
 	flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
 
 	memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
diff --git a/board/mx1fs2/flash.c b/board/mx1fs2/flash.c
index 47885bceb2..73ce8957e0 100644
--- a/board/mx1fs2/flash.c
+++ b/board/mx1fs2/flash.c
@@ -612,7 +612,7 @@ bad_write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
  * @param info:
  * @param src:	source of copy transaction
  * @param addr:	where to copy to
- * @param cnt: 	number of bytes to copy
+ * @param cnt:	number of bytes to copy
  *
  * @return	error code
  */
diff --git a/board/mx1fs2/lowlevel_init.S b/board/mx1fs2/lowlevel_init.S
index 8211beb3f8..4b2cb487aa 100644
--- a/board/mx1fs2/lowlevel_init.S
+++ b/board/mx1fs2/lowlevel_init.S
@@ -166,22 +166,22 @@ lowlevel_init:
 	ldr  r1,=0x00221000   /* adr of SDCTRL0			*/
 	ldr  r0,=0x92120200
 	str  r0,[r1,#0]       /* put in precharge command mode    */
-	ldr  r2,=0x08200000   /* adr for precharge cmd 	   */
+	ldr  r2,=0x08200000   /* adr for precharge cmd	   */
 	ldr  r0,[r2,#0]       /* precharge			   */
 	ldr  r0,=0xA2120200
 	ldr  r2,=0x08000000   /* start of SDRAM		   */
 	str  r0,[r1,#0]       /* put in auto-refresh mode	   */
-	ldr  r0,[r2,#0]       /* auto-refresh  		   */
-	ldr  r0,[r2,#0]       /* auto-refresh  		   */
-	ldr  r0,[r2,#0]       /* auto-refresh  		   */
-	ldr  r0,[r2,#0]       /* auto-refresh  		   */
-	ldr  r0,[r2,#0]       /* auto-refresh  		   */
-	ldr  r0,[r2,#0]       /* auto-refresh  		   */
-	ldr  r0,[r2,#0]       /* auto-refresh  		   */
+	ldr  r0,[r2,#0]       /* auto-refresh		   */
+	ldr  r0,[r2,#0]       /* auto-refresh		   */
+	ldr  r0,[r2,#0]       /* auto-refresh		   */
+	ldr  r0,[r2,#0]       /* auto-refresh		   */
+	ldr  r0,[r2,#0]       /* auto-refresh		   */
+	ldr  r0,[r2,#0]       /* auto-refresh		   */
+	ldr  r0,[r2,#0]       /* auto-refresh		   */
 	ldr  r0,=0xB2120200
 	ldr  r2,=0x08111800
 	str  r0,[r1,#0]       /* setup for mode register of SDRAM */
-	ldr  r0,[r2,#0]       /* program mode register 	   */
+	ldr  r0,[r2,#0]       /* program mode register	   */
 	ldr  r0,=0x82124267
 	str  r0,[r1,#0]       /* back to normal operation	   */
 
diff --git a/board/nc650/u-boot.lds b/board/nc650/u-boot.lds
index 159224f246..09a442aeeb 100644
--- a/board/nc650/u-boot.lds
+++ b/board/nc650/u-boot.lds
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/nc650/u-boot.lds.debug b/board/nc650/u-boot.lds.debug
index 40e4bd04ff..079a55abeb 100644
--- a/board/nc650/u-boot.lds.debug
+++ b/board/nc650/u-boot.lds.debug
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/netphone/netphone.c b/board/netphone/netphone.c
index ccc8b3ed85..1072b3f88a 100644
--- a/board/netphone/netphone.c
+++ b/board/netphone/netphone.c
@@ -691,7 +691,7 @@ int last_stage_init(void)
 	i = CFG_HZ * 2;
 	while (i > 0) {
 
-	       	if (tstc()) {
+		if (tstc()) {
 			getc();
 			break;
 		}
diff --git a/board/netphone/u-boot.lds b/board/netphone/u-boot.lds
index ea39cd9121..271102b770 100644
--- a/board/netphone/u-boot.lds
+++ b/board/netphone/u-boot.lds
@@ -33,10 +33,10 @@ SECTIONS
   .dynsym       : { *(.dynsym)		}
   .dynstr       : { *(.dynstr)		}
   .rel.text     : { *(.rel.text)	}
-  .rela.text    : { *(.rela.text) 	}
+  .rela.text    : { *(.rela.text)	}
   .rel.data     : { *(.rel.data)	}
-  .rela.data    : { *(.rela.data) 	}
-  .rel.rodata   : { *(.rel.rodata) 	}
+  .rela.data    : { *(.rela.data)	}
+  .rel.rodata   : { *(.rel.rodata)	}
   .rela.rodata  : { *(.rela.rodata)	}
   .rel.got      : { *(.rel.got)		}
   .rela.got     : { *(.rela.got)	}
@@ -49,8 +49,8 @@ SECTIONS
   .rel.plt      : { *(.rel.plt)		}
   .rela.plt     : { *(.rela.plt)	}
   .init         : { *(.init)		}
-  .plt			: { *(.plt) 		}
-  .text      	:
+  .plt		: { *(.plt)		}
+  .text	:
   {
     cpu/mpc8xx/start.o		(.text)
     cpu/mpc8xx/traps.o		(.text)
diff --git a/board/netphone/u-boot.lds.debug b/board/netphone/u-boot.lds.debug
index 80bcbfcb90..5bf1a66286 100644
--- a/board/netphone/u-boot.lds.debug
+++ b/board/netphone/u-boot.lds.debug
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/netstal/hcu4/u-boot.lds b/board/netstal/hcu4/u-boot.lds
index ab0b18a3d4..3bcfea2a8c 100644
--- a/board/netstal/hcu4/u-boot.lds
+++ b/board/netstal/hcu4/u-boot.lds
@@ -38,11 +38,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/netstal/hcu5/hcu5.c b/board/netstal/hcu5/hcu5.c
index 55e4cc69c6..4ecdb25da8 100644
--- a/board/netstal/hcu5/hcu5.c
+++ b/board/netstal/hcu5/hcu5.c
@@ -310,8 +310,8 @@ int misc_init_r(void)
 	if (mfspr(dbcr0) & 0x80000000) {
 		/* External debugger alive
 		 * enable trace facilty for Lauterbach
-		 * CCR0[DTB]=0 		Enable broadcast of trace information
-		 * SDR0_PFC0[TRE] 	Trace signals are enabled instead of
+		 * CCR0[DTB]=0		Enable broadcast of trace information
+		 * SDR0_PFC0[TRE]	Trace signals are enabled instead of
 		 *			GPIO49-63
 		 */
 	        mtspr(ccr0, mfspr(ccr0)  &~ (CCR0_DTB));
diff --git a/board/netstal/hcu5/init.S b/board/netstal/hcu5/init.S
index 188272e780..d73c861e66 100644
--- a/board/netstal/hcu5/init.S
+++ b/board/netstal/hcu5/init.S
@@ -85,7 +85,7 @@ tlbtab:
 	/* TLB#9: */
 	tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
 
-	/* 		CAN */
+	/*		CAN */
 	/* TLB#10: */
 	tlbentry( CFG_CS_1, SZ_1K, CFG_CS_1, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
 
@@ -96,7 +96,7 @@ tlbtab:
 	tlbentry( CFG_CS_2 + 0x1000000, SZ_16M, CFG_CS_2 + 0x1000000, 1,
 		AC_R|AC_W|AC_X|SA_G|SA_I )
 
-	 /* 		IMC-Fast 32 MB */
+	 /*		IMC-Fast 32 MB */
 	/* TLB#13: */
 	tlbentry( CFG_CS_3, SZ_16M, CFG_CS_3, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
 	/* TLB#14: */
diff --git a/board/netstal/hcu5/u-boot.lds b/board/netstal/hcu5/u-boot.lds
index 6c0ebbb271..c72e5ba699 100644
--- a/board/netstal/hcu5/u-boot.lds
+++ b/board/netstal/hcu5/u-boot.lds
@@ -42,11 +42,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/netstal/mcu25/u-boot.lds b/board/netstal/mcu25/u-boot.lds
index a9532c4b82..740bc9c970 100644
--- a/board/netstal/mcu25/u-boot.lds
+++ b/board/netstal/mcu25/u-boot.lds
@@ -38,11 +38,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/netstar/crcek.S b/board/netstar/crcek.S
index a74abf9a09..af35662187 100644
--- a/board/netstar/crcek.S
+++ b/board/netstar/crcek.S
@@ -33,7 +33,7 @@
 	ldr	r4, [r3, r4, lsl#2]
 	eor	r0, r4, r0, lsr#8
 	subs	r2, r2, #0x1
-	bne 	1b
+	bne	1b
 	eor	r0, r0, r5
 	.endm
 
@@ -58,7 +58,7 @@
 	mov	\reg, #0x100000
 3:
 	subs	\reg, \reg, #0x1
-	bne 	3b
+	bne	3b
 	.endm
 
 .text
diff --git a/board/netstar/eeprom_start.S b/board/netstar/eeprom_start.S
index 75d9f0558f..1306485854 100644
--- a/board/netstar/eeprom_start.S
+++ b/board/netstar/eeprom_start.S
@@ -29,7 +29,7 @@ _start:	b       eeprom
 	ldr	r4, [r3, r4, lsl#2]
 	eor	r0, r4, r0, lsr#8
 	subs	r2, r2, #0x1
-	bne 	1b
+	bne	1b
 	eor	r0, r0, r5
 	.endm
 
@@ -58,7 +58,7 @@ _start:	b       eeprom
 	mov	\reg, #0x1000
 3:
 	subs	\reg, \reg, #0x1
-	bne 	3b
+	bne	3b
 
 	.endm
 .text
diff --git a/board/netstar/setup.S b/board/netstar/setup.S
index 5dacc9cc45..3c2d467979 100644
--- a/board/netstar/setup.S
+++ b/board/netstar/setup.S
@@ -277,7 +277,7 @@ ulocking:
 	mov	r0, #0x4000
 sdelay:
 	subs	r0, r0, #0x1
-	bne 	sdelay
+	bne	sdelay
 
 	/* back to arch calling code */
 	mov	pc, lr
diff --git a/board/netta/dsp.c b/board/netta/dsp.c
index 66e0b85e6c..3739e16d6f 100644
--- a/board/netta/dsp.c
+++ b/board/netta/dsp.c
@@ -1031,7 +1031,7 @@ const struct host_init hi_default = {
 
 	.clk_divider	= {
 		[0]	= 47,		/* must be 2048Hz */
-		[1] 	= 47,
+		[1]	= 47,
 	},
 
 	.initmode	= 1,
diff --git a/board/netta/pcmcia.c b/board/netta/pcmcia.c
index 86b3cfb992..66e6e511e2 100644
--- a/board/netta/pcmcia.c
+++ b/board/netta/pcmcia.c
@@ -231,12 +231,12 @@ int pcmcia_hardware_enable(int slot)
 	       (reg&PCMCIA_VS2(slot))?"n":"ff");
 
 	if ((pipr & mask) == mask) {
-		set_vppd(0, 1); set_vppd(1, 1); 		/* VAVPP => Hi-Z */
-		set_vccd(0, 0); set_vccd(1, 1); 		/* 5V on, 3V off */
+		set_vppd(0, 1); set_vppd(1, 1);		/* VAVPP => Hi-Z */
+		set_vccd(0, 0); set_vccd(1, 1);		/* 5V on, 3V off */
 		puts (" 5.0V card found: ");
 	} else {
-		set_vppd(0, 1); set_vppd(1, 1); 		/* VAVPP => Hi-Z */
-		set_vccd(0, 1); set_vccd(1, 0); 		/* 5V off, 3V on */
+		set_vppd(0, 1); set_vppd(1, 1);		/* VAVPP => Hi-Z */
+		set_vccd(0, 1); set_vccd(1, 0);		/* 5V off, 3V on */
 		puts (" 3.3V card found: ");
 	}
 
@@ -244,7 +244,7 @@ int pcmcia_hardware_enable(int slot)
 	for (i=0; i<5000; ++i) {
 		if (!get_oc()) {
 			printf ("   *** Overcurrent - Safety shutdown ***\n");
-			set_vccd(0, 0); set_vccd(1, 0); 		/* VAVPP => Hi-Z */
+			set_vccd(0, 0); set_vccd(1, 0);		/* VAVPP => Hi-Z */
 			return (1);
 		}
 		udelay (100);
diff --git a/board/netta/u-boot.lds b/board/netta/u-boot.lds
index ea39cd9121..f560189c0b 100644
--- a/board/netta/u-boot.lds
+++ b/board/netta/u-boot.lds
@@ -28,15 +28,15 @@ SECTIONS
 {
   /* Read-only sections, merged into text segment: */
   . = + SIZEOF_HEADERS;
-  .interp		: { *(.interp)		}
+  .interp	: { *(.interp)		}
   .hash         : { *(.hash)		}
   .dynsym       : { *(.dynsym)		}
   .dynstr       : { *(.dynstr)		}
   .rel.text     : { *(.rel.text)	}
-  .rela.text    : { *(.rela.text) 	}
+  .rela.text    : { *(.rela.text)	}
   .rel.data     : { *(.rel.data)	}
-  .rela.data    : { *(.rela.data) 	}
-  .rel.rodata   : { *(.rel.rodata) 	}
+  .rela.data    : { *(.rela.data)	}
+  .rel.rodata   : { *(.rel.rodata)	}
   .rela.rodata  : { *(.rela.rodata)	}
   .rel.got      : { *(.rel.got)		}
   .rela.got     : { *(.rela.got)	}
@@ -49,8 +49,8 @@ SECTIONS
   .rel.plt      : { *(.rel.plt)		}
   .rela.plt     : { *(.rela.plt)	}
   .init         : { *(.init)		}
-  .plt			: { *(.plt) 		}
-  .text      	:
+  .plt		: { *(.plt)		}
+  .text	:
   {
     cpu/mpc8xx/start.o		(.text)
     cpu/mpc8xx/traps.o		(.text)
diff --git a/board/netta/u-boot.lds.debug b/board/netta/u-boot.lds.debug
index 80bcbfcb90..5bf1a66286 100644
--- a/board/netta/u-boot.lds.debug
+++ b/board/netta/u-boot.lds.debug
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/netta2/u-boot.lds b/board/netta2/u-boot.lds
index ea39cd9121..f560189c0b 100644
--- a/board/netta2/u-boot.lds
+++ b/board/netta2/u-boot.lds
@@ -28,15 +28,15 @@ SECTIONS
 {
   /* Read-only sections, merged into text segment: */
   . = + SIZEOF_HEADERS;
-  .interp		: { *(.interp)		}
+  .interp	: { *(.interp)		}
   .hash         : { *(.hash)		}
   .dynsym       : { *(.dynsym)		}
   .dynstr       : { *(.dynstr)		}
   .rel.text     : { *(.rel.text)	}
-  .rela.text    : { *(.rela.text) 	}
+  .rela.text    : { *(.rela.text)	}
   .rel.data     : { *(.rel.data)	}
-  .rela.data    : { *(.rela.data) 	}
-  .rel.rodata   : { *(.rel.rodata) 	}
+  .rela.data    : { *(.rela.data)	}
+  .rel.rodata   : { *(.rel.rodata)	}
   .rela.rodata  : { *(.rela.rodata)	}
   .rel.got      : { *(.rel.got)		}
   .rela.got     : { *(.rela.got)	}
@@ -49,8 +49,8 @@ SECTIONS
   .rel.plt      : { *(.rel.plt)		}
   .rela.plt     : { *(.rela.plt)	}
   .init         : { *(.init)		}
-  .plt			: { *(.plt) 		}
-  .text      	:
+  .plt		: { *(.plt)		}
+  .text	:
   {
     cpu/mpc8xx/start.o		(.text)
     cpu/mpc8xx/traps.o		(.text)
diff --git a/board/netta2/u-boot.lds.debug b/board/netta2/u-boot.lds.debug
index 80bcbfcb90..5bf1a66286 100644
--- a/board/netta2/u-boot.lds.debug
+++ b/board/netta2/u-boot.lds.debug
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/netvia/u-boot.lds b/board/netvia/u-boot.lds
index 79399f8c1c..b4f210e484 100644
--- a/board/netvia/u-boot.lds
+++ b/board/netvia/u-boot.lds
@@ -28,15 +28,15 @@ SECTIONS
 {
   /* Read-only sections, merged into text segment: */
   . = + SIZEOF_HEADERS;
-  .interp		: { *(.interp)		}
+  .interp	: { *(.interp)		}
   .hash         : { *(.hash)		}
   .dynsym       : { *(.dynsym)		}
   .dynstr       : { *(.dynstr)		}
   .rel.text     : { *(.rel.text)	}
-  .rela.text    : { *(.rela.text) 	}
+  .rela.text    : { *(.rela.text)	}
   .rel.data     : { *(.rel.data)	}
-  .rela.data    : { *(.rela.data) 	}
-  .rel.rodata   : { *(.rel.rodata) 	}
+  .rela.data    : { *(.rela.data)	}
+  .rel.rodata   : { *(.rel.rodata)	}
   .rela.rodata  : { *(.rela.rodata)	}
   .rel.got      : { *(.rel.got)		}
   .rela.got     : { *(.rela.got)	}
@@ -49,8 +49,8 @@ SECTIONS
   .rel.plt      : { *(.rel.plt)		}
   .rela.plt     : { *(.rela.plt)	}
   .init         : { *(.init)		}
-  .plt			: { *(.plt) 		}
-  .text      	:
+  .plt		: { *(.plt)		}
+  .text	:
   {
     cpu/mpc8xx/start.o		(.text)
     cpu/mpc8xx/traps.o		(.text)
diff --git a/board/netvia/u-boot.lds.debug b/board/netvia/u-boot.lds.debug
index dda52a99ed..1014ec6e8c 100644
--- a/board/netvia/u-boot.lds.debug
+++ b/board/netvia/u-boot.lds.debug
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/ns9750dev/ns9750dev.c b/board/ns9750dev/ns9750dev.c
index 1dd348a0c3..fc46244c74 100644
--- a/board/ns9750dev/ns9750dev.c
+++ b/board/ns9750dev/ns9750dev.c
@@ -102,7 +102,7 @@ void flash__init (void)
 /*************************************************************
  Routine:ether__init
  Description: take the Ethernet controller out of reset and wait
-	  		   for the EEPROM load to complete.
+			   for the EEPROM load to complete.
 *************************************************************/
 void ether__init (void)
 {
diff --git a/board/nx823/u-boot.lds b/board/nx823/u-boot.lds
index 94ab7457f9..85117aa56e 100644
--- a/board/nx823/u-boot.lds
+++ b/board/nx823/u-boot.lds
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/nx823/u-boot.lds.debug b/board/nx823/u-boot.lds.debug
index 1a25a98f17..85072feda4 100644
--- a/board/nx823/u-boot.lds.debug
+++ b/board/nx823/u-boot.lds.debug
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/omap1610inn/lowlevel_init.S b/board/omap1610inn/lowlevel_init.S
index cc8347fa14..e4ed9f3c69 100644
--- a/board/omap1610inn/lowlevel_init.S
+++ b/board/omap1610inn/lowlevel_init.S
@@ -58,7 +58,7 @@ lowlevel_init:
 	str	r1,	[r0]
 
 	/*------------------------------------------------------*
-	 * Set up ARM CLM registers (IDLECT2)  		        *
+	 * Set up ARM CLM registers (IDLECT2)		        *
 	 *------------------------------------------------------*/
 	ldr	r0,	REG_ARM_IDLECT2
 	ldr	r1,	VAL_ARM_IDLECT2
@@ -123,7 +123,7 @@ lock_end:
 
 	/*------------------------------------------------------*
 	 * Turn off the watchdog during init...			*
- 	 *------------------------------------------------------*/
+	 *------------------------------------------------------*/
 disable_wd:
 	ldr	r0,	REG_WATCHDOG
 	ldr	r1,	WATCHDOG_VAL1
@@ -156,13 +156,13 @@ watch2Wait:
 	 * and branch to appropriate initialization code.
 	 */
 	/* Load physical SDRAM base. */
-	mov 	r0, 	#0x10000000
+	mov	r0,	#0x10000000
 	/* Get current execution location. */
-	mov 	r1, 	pc
+	mov	r1,	pc
 	/* Compare. */
-	cmp 	r1, 	r0
+	cmp	r1,	r0
 	/* Skip over EMIF-fast initialization if running from SDRAM. */
-	bge 	skip_sdram
+	bge	skip_sdram
 
 	/*
 	* Delay for SDRAM initialization.
@@ -170,7 +170,7 @@ watch2Wait:
 	mov	r3,	#0x1800		/* value should be checked */
 3:
 	subs	r3,	r3,	#0x1	/* Decrement count */
-	bne 	3b
+	bne	3b
 
 
 	/*
@@ -270,7 +270,7 @@ common_tc:
 #ifdef CONFIG_H2_OMAP1610
 	/* inserting additional 2 clock cycle hold time for LAN */
 	ldr     r0,     REG_TC_EMIFS_CS1_ADVANCED
-	ldr    	r1,     VAL_TC_EMIFS_CS1_ADVANCED
+	ldr	r1,     VAL_TC_EMIFS_CS1_ADVANCED
 	str     r1,     [r0]
 #endif
 	/* Start MPU Timer 1 */
diff --git a/board/omap1610inn/omap1610innovator.c b/board/omap1610inn/omap1610innovator.c
index 8dbe686a89..2e04ad4bdd 100644
--- a/board/omap1610inn/omap1610innovator.c
+++ b/board/omap1610inn/omap1610innovator.c
@@ -116,7 +116,7 @@ void flash__init (void)
 /*************************************************************
  Routine:ether__init
  Description: take the Ethernet controller out of reset and wait
-	  		   for the EEPROM load to complete.
+			   for the EEPROM load to complete.
 *************************************************************/
 void ether__init (void)
 {
@@ -162,7 +162,7 @@ int dram_init (void)
 /******************************************************
  Routine: set_muxconf_regs
  Description: Setting up the configuration Mux registers
- 			  specific to the hardware
+			  specific to the hardware
 *******************************************************/
 void set_muxconf_regs (void)
 {
diff --git a/board/omap2420h4/mem.c b/board/omap2420h4/mem.c
index 62eb6e38a3..a3295fd4e0 100644
--- a/board/omap2420h4/mem.c
+++ b/board/omap2420h4/mem.c
@@ -253,7 +253,7 @@ next_mem_type:
 		a = H4_242x_SDRC_ACTIM_CTRLA_0_ES1;
 		b = H4_242x_SDRC_ACTIM_CTRLB_0_ES1;
 		r = H4_242x_SDRC_RFR_CTRL_ES1;
- 	}
+	}
 
 	if (cs0) {
 		__raw_writel(a, SDRC_ACTIM_CTRLA_0);
diff --git a/board/omap2420h4/omap2420h4.c b/board/omap2420h4/omap2420h4.c
index 1b917b3147..09b070dc1a 100644
--- a/board/omap2420h4/omap2420h4.c
+++ b/board/omap2420h4/omap2420h4.c
@@ -152,7 +152,7 @@ void wait_for_command_complete(unsigned int wd_base)
 /*******************************************************************
  * Routine:ether_init
  * Description: take the Ethernet controller out of reset and wait
- *  		   for the EEPROM load to complete.
+ *		   for the EEPROM load to complete.
  ******************************************************************/
 void ether_init (void)
 {
diff --git a/board/omap5912osk/lowlevel_init.S b/board/omap5912osk/lowlevel_init.S
index a1fa097d9e..7bfdb26325 100644
--- a/board/omap5912osk/lowlevel_init.S
+++ b/board/omap5912osk/lowlevel_init.S
@@ -125,7 +125,7 @@ lock_end:
 
 	/*------------------------------------------------------*
 	 * Turn off the watchdog during init...                 *
- 	 *------------------------------------------------------*/
+	 *------------------------------------------------------*/
 	ldr	r0,	REG_WATCHDOG
 	ldr	r1,	WATCHDOG_VAL1
 	str	r1,	[r0]
@@ -191,7 +191,7 @@ skip_TMP_Patch:
 	mov	r0,	#0x1800		/* value should be checked */
 3:
 	subs	r0,	r0,	#0x1	/* Decrement count */
-	bne 	3b
+	bne	3b
 
 	/*
 	 * Set SDRAM control values. Disable refresh before MRS command.
@@ -294,7 +294,7 @@ common_tc:
 #ifdef CONFIG_H2_OMAP1610
 	/* inserting additional 2 clock cycle hold time for LAN */
 	ldr     r0,     REG_TC_EMIFS_CS1_ADVANCED
-	ldr    	r1,     VAL_TC_EMIFS_CS1_ADVANCED
+	ldr	r1,     VAL_TC_EMIFS_CS1_ADVANCED
 	str     r1,     [r0]
 #endif
 	/* Start MPU Timer 1 */
diff --git a/board/omap730p2/lowlevel_init.S b/board/omap730p2/lowlevel_init.S
index 9ab71cf551..d4e97a5aa7 100644
--- a/board/omap730p2/lowlevel_init.S
+++ b/board/omap730p2/lowlevel_init.S
@@ -65,7 +65,7 @@ lowlevel_init:
 	str	r1,	[r0]
 
 	/*------------------------------------------------------*
-	 * Set up ARM CLM registers (IDLECT2)  		        *
+	 * Set up ARM CLM registers (IDLECT2)		        *
 	 *------------------------------------------------------*/
 	ldr	r0,	REG_ARM_IDLECT2
 	ldr	r1,	VAL_ARM_IDLECT2
@@ -123,7 +123,7 @@ lock_end:
 
 	/*------------------------------------------------------*
 	 * Turn off the watchdog during init...			*
- 	 *------------------------------------------------------*/
+	 *------------------------------------------------------*/
 	ldr	r0,	REG_WATCHDOG
 	ldr	r1,	WATCHDOG_VAL1
 	str	r1,	[r0]
@@ -158,7 +158,7 @@ watch2Wait:
 	/* Compare. */
 	cmp     r0, #0
 	/* Skip over EMIF-fast initialization if running from SDRAM. */
-	bne 	skip_sdram
+	bne	skip_sdram
 
 	/*
 	* Delay for SDRAM initialization.
@@ -166,7 +166,7 @@ watch2Wait:
 	mov	r3,	#0x1800		/* value should be checked */
 3:
 	subs	r3,	r3,	#0x1	/* Decrement count */
-	bne 	3b
+	bne	3b
 
 	ldr	r0,	REG_SDRAM_CONFIG
 	ldr	r1,	SDRAM_CONFIG_VAL
@@ -239,7 +239,7 @@ common_tc:
 #ifdef CONFIG_P2_OMAP1610
 	/* inserting additional 2 clock cycle hold time for LAN */
 	ldr     r0,     REG_TC_EMIFS_CS1_ADVANCED
-	ldr    	r1,     VAL_TC_EMIFS_CS1_ADVANCED
+	ldr	r1,     VAL_TC_EMIFS_CS1_ADVANCED
 	str     r1,     [r0]
 #endif
 	/* Start MPU Timer 1 */
diff --git a/board/oxc/flash.c b/board/oxc/flash.c
index 795b7ccff9..296c01dc84 100644
--- a/board/oxc/flash.c
+++ b/board/oxc/flash.c
@@ -163,7 +163,7 @@ static ulong flash_get_size (vu_char *addr, flash_info_t *info)
     }
 
     if (devid == FLASH_STM320DB) {
-    	/* MPC8240 can address maximum 2Mb of flash, that is why the MSB
+	/* MPC8240 can address maximum 2Mb of flash, that is why the MSB
 	 * lead is grounded and we can access only 2 first Mb */
 	info->flash_id     = vendor << 16 | devid;
 	info->sector_count = 32;
diff --git a/board/pcippc2/cpc710_init_ram.c b/board/pcippc2/cpc710_init_ram.c
index 57ed8f087f..171f06c58f 100644
--- a/board/pcippc2/cpc710_init_ram.c
+++ b/board/pcippc2/cpc710_init_ram.c
@@ -28,227 +28,205 @@
 #include "pcippc2.h"
 #include "i2c.h"
 
-typedef struct cpc710_mem_org_s
-{
-  u8		rows;
-  u8		cols;
-  u8		banks2;
-  u8		org;
+typedef struct cpc710_mem_org_s {
+	u8 rows;
+	u8 cols;
+	u8 banks2;
+	u8 org;
 } cpc710_mem_org_t;
 
-static int		cpc710_compute_mcer	(u32 *		mcer,
-						 unsigned long *
-								size,
-						 unsigned int	sdram);
-static int		cpc710_eeprom_checksum	(unsigned int	sdram);
-static u8		cpc710_eeprom_read	(unsigned int	sdram,
-						 unsigned int	offset);
-
-static u32		cpc710_mcer_mem [] =
-{
-  0x000003f3,	/* 18 lines,    4 Mb */
-  0x000003e3,	/* 19 lines,    8 Mb */
-  0x000003c3,	/* 20 lines,   16 Mb */
-  0x00000383,	/* 21 lines,   32 Mb */
-  0x00000303,	/* 22 lines,   64 Mb */
-  0x00000203,	/* 23 lines,  128 Mb */
-  0x00000003,	/* 24 lines,  256 Mb */
-  0x00000002,	/* 25 lines,  512 Mb */
-  0x00000001	/* 26 lines, 1024 Mb */
+static int cpc710_compute_mcer (u32 * mcer,
+				unsigned long *size, unsigned int sdram);
+static int cpc710_eeprom_checksum (unsigned int sdram);
+static u8 cpc710_eeprom_read (unsigned int sdram, unsigned int offset);
+
+static u32 cpc710_mcer_mem[] = {
+	0x000003f3,		/* 18 lines,    4 Mb */
+	0x000003e3,		/* 19 lines,    8 Mb */
+	0x000003c3,		/* 20 lines,   16 Mb */
+	0x00000383,		/* 21 lines,   32 Mb */
+	0x00000303,		/* 22 lines,   64 Mb */
+	0x00000203,		/* 23 lines,  128 Mb */
+	0x00000003,		/* 24 lines,  256 Mb */
+	0x00000002,		/* 25 lines,  512 Mb */
+	0x00000001		/* 26 lines, 1024 Mb */
 };
-static cpc710_mem_org_t	cpc710_mem_org [] =
-{
-  { 0x0c, 0x09, 0x02, 0x00 },	/* 0000: 12/ 9/2 */
-  { 0x0d, 0x09, 0x02, 0x00 },	/* 0000: 13/ 9/2 */
-  { 0x0d, 0x0a, 0x02, 0x00 },	/* 0000: 13/10/2 */
-  { 0x0d, 0x0b, 0x02, 0x00 },	/* 0000: 13/11/2 */
-  { 0x0d, 0x0c, 0x02, 0x00 },	/* 0000: 13/12/2 */
-  { 0x0e, 0x0c, 0x02, 0x00 },	/* 0000: 14/12/2 */
-  { 0x0b, 0x08, 0x02, 0x01 },	/* 0001: 11/ 8/2 */
-  { 0x0b, 0x09, 0x01, 0x02 },	/* 0010: 11/ 9/1 */
-  { 0x0b, 0x0a, 0x01, 0x03 },	/* 0011: 11/10/1 */
-  { 0x0c, 0x08, 0x02, 0x04 },	/* 0100: 12/ 8/2 */
-  { 0x0c, 0x0a, 0x02, 0x05 },	/* 0101: 12/10/2 */
-  { 0x0d, 0x08, 0x01, 0x06 },	/* 0110: 13/ 8/1 */
-  { 0x0d, 0x08, 0x02, 0x07 },	/* 0111: 13/ 8/2 */
-  { 0x0d, 0x09, 0x01, 0x08 },	/* 1000: 13/ 9/1 */
-  { 0x0d, 0x0a, 0x01, 0x09 },	/* 1001: 13/10/1 */
-  { 0x0b, 0x08, 0x01, 0x0a },	/* 1010: 11/ 8/1 */
-  { 0x0c, 0x08, 0x01, 0x0b },	/* 1011: 12/ 8/1 */
-  { 0x0c, 0x09, 0x01, 0x0c },	/* 1100: 12/ 9/1 */
-  { 0x0e, 0x09, 0x02, 0x0d },	/* 1101: 14/ 9/2 */
-  { 0x0e, 0x0a, 0x02, 0x0e },	/* 1110: 14/10/2 */
-  { 0x0e, 0x0b, 0x02, 0x0f } 	/* 1111: 14/11/2 */
+static cpc710_mem_org_t cpc710_mem_org[] = {
+	{0x0c, 0x09, 0x02, 0x00},	/* 0000: 12/ 9/2 */
+	{0x0d, 0x09, 0x02, 0x00},	/* 0000: 13/ 9/2 */
+	{0x0d, 0x0a, 0x02, 0x00},	/* 0000: 13/10/2 */
+	{0x0d, 0x0b, 0x02, 0x00},	/* 0000: 13/11/2 */
+	{0x0d, 0x0c, 0x02, 0x00},	/* 0000: 13/12/2 */
+	{0x0e, 0x0c, 0x02, 0x00},	/* 0000: 14/12/2 */
+	{0x0b, 0x08, 0x02, 0x01},	/* 0001: 11/ 8/2 */
+	{0x0b, 0x09, 0x01, 0x02},	/* 0010: 11/ 9/1 */
+	{0x0b, 0x0a, 0x01, 0x03},	/* 0011: 11/10/1 */
+	{0x0c, 0x08, 0x02, 0x04},	/* 0100: 12/ 8/2 */
+	{0x0c, 0x0a, 0x02, 0x05},	/* 0101: 12/10/2 */
+	{0x0d, 0x08, 0x01, 0x06},	/* 0110: 13/ 8/1 */
+	{0x0d, 0x08, 0x02, 0x07},	/* 0111: 13/ 8/2 */
+	{0x0d, 0x09, 0x01, 0x08},	/* 1000: 13/ 9/1 */
+	{0x0d, 0x0a, 0x01, 0x09},	/* 1001: 13/10/1 */
+	{0x0b, 0x08, 0x01, 0x0a},	/* 1010: 11/ 8/1 */
+	{0x0c, 0x08, 0x01, 0x0b},	/* 1011: 12/ 8/1 */
+	{0x0c, 0x09, 0x01, 0x0c},	/* 1100: 12/ 9/1 */
+	{0x0e, 0x09, 0x02, 0x0d},	/* 1101: 14/ 9/2 */
+	{0x0e, 0x0a, 0x02, 0x0e},	/* 1110: 14/10/2 */
+	{0x0e, 0x0b, 0x02, 0x0f}	/* 1111: 14/11/2 */
 };
 
 unsigned long cpc710_ram_init (void)
 {
-  unsigned long 	memsize = 0;
-  unsigned long		bank_size;
-  u32			mcer;
+	unsigned long memsize = 0;
+	unsigned long bank_size;
+	u32 mcer;
 
 #ifndef CFG_RAMBOOT
-    /* Clear memory banks
-     */
-  out32(REG(SDRAM0, MCER0), 0);
-  out32(REG(SDRAM0, MCER1), 0);
-  out32(REG(SDRAM0, MCER2), 0);
-  out32(REG(SDRAM0, MCER3), 0);
-  out32(REG(SDRAM0, MCER4), 0);
-  out32(REG(SDRAM0, MCER5), 0);
-  out32(REG(SDRAM0, MCER6), 0);
-  out32(REG(SDRAM0, MCER7), 0);
-  iobarrier_rw();
-
-    /* Disable memory
-     */
-  out32(REG(SDRAM0,MCCR), 0x13b06000);
-  iobarrier_rw();
+	/* Clear memory banks
+	 */
+	out32 (REG (SDRAM0, MCER0), 0);
+	out32 (REG (SDRAM0, MCER1), 0);
+	out32 (REG (SDRAM0, MCER2), 0);
+	out32 (REG (SDRAM0, MCER3), 0);
+	out32 (REG (SDRAM0, MCER4), 0);
+	out32 (REG (SDRAM0, MCER5), 0);
+	out32 (REG (SDRAM0, MCER6), 0);
+	out32 (REG (SDRAM0, MCER7), 0);
+	iobarrier_rw ();
+
+	/* Disable memory
+	 */
+	out32 (REG (SDRAM0, MCCR), 0x13b06000);
+	iobarrier_rw ();
 #endif
 
-    /* Only the first memory bank is initialised now
-     */
-  if (! cpc710_compute_mcer(& mcer, & bank_size, 0))
-  {
-    puts("Unsupported SDRAM type !\n");
-    hang();
-  }
-  memsize += bank_size;
+	/* Only the first memory bank is initialised now
+	 */
+	if (!cpc710_compute_mcer (&mcer, &bank_size, 0)) {
+		puts ("Unsupported SDRAM type !\n");
+		hang ();
+	}
+	memsize += bank_size;
 #ifndef CFG_RAMBOOT
-    /* Enable bank, zero start
-     */
-  out32(REG(SDRAM0, MCER0), mcer | 0x80000000);
-  iobarrier_rw();
+	/* Enable bank, zero start
+	 */
+	out32 (REG (SDRAM0, MCER0), mcer | 0x80000000);
+	iobarrier_rw ();
 #endif
 
 #ifndef CFG_RAMBOOT
-    /* Enable memory
-     */
-  out32(REG(SDRAM0, MCCR), in32(REG(SDRAM0, MCCR)) | 0x80000000);
-
-    /* Wait until initialisation finished
-     */
-  while (! (in32 (REG(SDRAM0, MCCR)) & 0x20000000))
-  {
-    iobarrier_rw();
-  }
-
-    /* Clear Memory Error Status and Address registers
-     */
-  out32(REG(SDRAM0, MESR), 0);
-  out32(REG(SDRAM0, MEAR), 0);
-  iobarrier_rw();
-
-    /* ECC is not configured now
-     */
+	/* Enable memory
+	 */
+	out32 (REG (SDRAM0, MCCR), in32 (REG (SDRAM0, MCCR)) | 0x80000000);
+
+	/* Wait until initialisation finished
+	 */
+	while (!(in32 (REG (SDRAM0, MCCR)) & 0x20000000)) {
+		iobarrier_rw ();
+	}
+
+	/* Clear Memory Error Status and Address registers
+	 */
+	out32 (REG (SDRAM0, MESR), 0);
+	out32 (REG (SDRAM0, MEAR), 0);
+	iobarrier_rw ();
+
+	/* ECC is not configured now
+	 */
 #endif
 
-    /* Memory size counter
-     */
-  out32(REG(CPC0, RGBAN1), memsize);
+	/* Memory size counter
+	 */
+	out32 (REG (CPC0, RGBAN1), memsize);
 
-  return memsize;
+	return memsize;
 }
 
-static int cpc710_compute_mcer (
-  u32 *			mcer,
-  unsigned long	*	size,
-  unsigned int		sdram)
+static int cpc710_compute_mcer (u32 * mcer, unsigned long *size, unsigned int sdram)
 {
-  u8			rows;
-  u8			cols;
-  u8			banks2;
-  unsigned int		lines;
-  u32			mc = 0;
-  unsigned int		i;
-  cpc710_mem_org_t *	org = 0;
-
-
-  if (! i2c_reset())
-  {
-    puts("Can't reset I2C!\n");
-    hang();
-  }
-
-  if (! cpc710_eeprom_checksum(sdram))
-  {
-    puts("Invalid EEPROM checksum !\n");
-    hang();
-  }
-
-  rows   = cpc710_eeprom_read(sdram, 3);
-  cols   = cpc710_eeprom_read(sdram, 4);
-    /* Can be 2 or 4 banks; divide by 2
-     */
-  banks2 = cpc710_eeprom_read(sdram, 17) / 2;
-
-  lines = rows + cols + banks2;
-
-  if (lines < 18 || lines > 26)
-  {
-      /* Unsupported configuration
-       */
-    return 0;
-  }
-
-
-  mc |= cpc710_mcer_mem [lines - 18] << 6;
-
-  for (i = 0; i < sizeof(cpc710_mem_org) / sizeof(cpc710_mem_org_t); i++)
-  {
-    cpc710_mem_org_t *	corg = cpc710_mem_org + i;
-
-    if (corg->rows == rows && corg->cols == cols && corg->banks2 == banks2)
-    {
-      org = corg;
-
-      break;
-    }
-  }
-
-  if (! org)
-  {
-      /* Unsupported configuration
-       */
-    return 0;
-  }
-
-  mc |= (u32) org->org << 2;
-
-    /* Supported configuration
-     */
-  *mcer = mc;
-  *size = 1l << (lines + 4);
-
-  return 1;
+	u8 rows;
+	u8 cols;
+	u8 banks2;
+	unsigned int lines;
+	u32 mc = 0;
+	unsigned int i;
+	cpc710_mem_org_t *org = 0;
+
+	if (!i2c_reset ()) {
+		puts ("Can't reset I2C!\n");
+		hang ();
+	}
+
+	if (!cpc710_eeprom_checksum (sdram)) {
+		puts ("Invalid EEPROM checksum !\n");
+		hang ();
+	}
+
+	rows = cpc710_eeprom_read (sdram, 3);
+	cols = cpc710_eeprom_read (sdram, 4);
+	/* Can be 2 or 4 banks; divide by 2
+	 */
+	banks2 = cpc710_eeprom_read (sdram, 17) / 2;
+
+	lines = rows + cols + banks2;
+
+	if (lines < 18 || lines > 26) {
+		/* Unsupported configuration
+		 */
+		return 0;
+	}
+
+	mc |= cpc710_mcer_mem[lines - 18] << 6;
+
+	for (i = 0; i < sizeof (cpc710_mem_org) / sizeof (cpc710_mem_org_t);
+	     i++) {
+		cpc710_mem_org_t *corg = cpc710_mem_org + i;
+
+		if (corg->rows == rows && corg->cols == cols
+		    && corg->banks2 == banks2) {
+			org = corg;
+
+			break;
+		}
+	}
+
+	if (!org) {
+		/* Unsupported configuration
+		 */
+		return 0;
+	}
+
+	mc |= (u32) org->org << 2;
+
+	/* Supported configuration
+	 */
+	*mcer = mc;
+	*size = 1l << (lines + 4);
+
+	return 1;
 }
 
-static int cpc710_eeprom_checksum (
-  unsigned int		sdram)
+static int cpc710_eeprom_checksum (unsigned int sdram)
 {
-  u8			sum = 0;
-  unsigned int		i;
+	u8 sum = 0;
+	unsigned int i;
 
-  for (i = 0; i < 63; i++)
-  {
-    sum += cpc710_eeprom_read(sdram, i);
-  }
+	for (i = 0; i < 63; i++) {
+		sum += cpc710_eeprom_read (sdram, i);
+	}
 
-  return sum == cpc710_eeprom_read(sdram, 63);
+	return sum == cpc710_eeprom_read (sdram, 63);
 }
 
-static u8 cpc710_eeprom_read (
-  unsigned int		sdram,
-  unsigned int		offset)
+static u8 cpc710_eeprom_read (unsigned int sdram, unsigned int offset)
 {
-  u8			dev = (sdram << 1) | 0xa0;
-  u8			data;
+	u8 dev = (sdram << 1) | 0xa0;
+	u8 data;
 
-  if (! i2c_read_byte(& data, dev,offset))
-  {
-    puts("I2C error !\n");
-    hang();
-  }
+	if (!i2c_read_byte (&data, dev, offset)) {
+		puts ("I2C error !\n");
+		hang ();
+	}
 
-  return data;
+	return data;
 }
diff --git a/board/pcippc2/fpga_serial.h b/board/pcippc2/fpga_serial.h
index 92c9cdd331..52750143c4 100644
--- a/board/pcippc2/fpga_serial.h
+++ b/board/pcippc2/fpga_serial.h
@@ -25,10 +25,10 @@
 #define _FPGA_SERIAL_H_
 
 extern void	fpga_serial_init	(int);
-extern void	fpga_serial_putc 	(char);
-extern void	fpga_serial_puts 	(const char *);
-extern int	fpga_serial_getc 	(void);
-extern int	fpga_serial_tstc 	(void);
-extern void	fpga_serial_setbrg 	(void);
+extern void	fpga_serial_putc	(char);
+extern void	fpga_serial_puts	(const char *);
+extern int	fpga_serial_getc	(void);
+extern int	fpga_serial_tstc	(void);
+extern void	fpga_serial_setbrg	(void);
 
 #endif
diff --git a/board/pcippc2/pcippc2.h b/board/pcippc2/pcippc2.h
index 3820bbec61..a1366ef69c 100644
--- a/board/pcippc2/pcippc2.h
+++ b/board/pcippc2/pcippc2.h
@@ -38,11 +38,11 @@ extern u32		pcippc2_fpga1_phys;
 
 extern u32	pcippc2_sdram_size		(void);
 
-extern void 	pcippc2_fpga_init		(void);
+extern void	pcippc2_fpga_init		(void);
 
-extern void 	pcippc2_cpci3264_init	(void);
+extern void	pcippc2_cpci3264_init	(void);
 
-extern void 	cpc710_pci_init			(void);
+extern void	cpc710_pci_init			(void);
 extern void	cpc710_pci_enable_timeout	(void);
 
 extern unsigned long
diff --git a/board/pcippc2/sconsole.h b/board/pcippc2/sconsole.h
index 40fd75b81b..5d850a589d 100644
--- a/board/pcippc2/sconsole.h
+++ b/board/pcippc2/sconsole.h
@@ -26,24 +26,23 @@
 
 #include <config.h>
 
-typedef struct sconsole_buffer_s
-{
-  unsigned long		size;
-  unsigned long		max_size;
-  unsigned long 	pos;
-  unsigned long 	baud;
-  char			data [1];
+typedef struct sconsole_buffer_s {
+	unsigned long size;
+	unsigned long max_size;
+	unsigned long pos;
+	unsigned long baud;
+	char data[1];
 } sconsole_buffer_t;
 
 #define SCONSOLE_BUFFER		((sconsole_buffer_t *) CFG_SCONSOLE_ADDR)
 
-extern void	(* sconsole_putc) 	(char);
-extern void	(* sconsole_puts) 	(const char *);
-extern int	(* sconsole_getc) 	(void);
-extern int	(* sconsole_tstc) 	(void);
-extern void	(* sconsole_setbrg) 	(void);
+extern void	(* sconsole_putc)	(char);
+extern void	(* sconsole_puts)	(const char *);
+extern int	(* sconsole_getc)	(void);
+extern int	(* sconsole_tstc)	(void);
+extern void	(* sconsole_setbrg)	(void);
 
 extern void	sconsole_flush		(void);
-extern int 	sconsole_get_baudrate 	(void);
+extern int	sconsole_get_baudrate	(void);
 
 #endif
diff --git a/board/pcippc2/u-boot.lds b/board/pcippc2/u-boot.lds
index 1959807334..ebb1b6d46a 100644
--- a/board/pcippc2/u-boot.lds
+++ b/board/pcippc2/u-boot.lds
@@ -40,11 +40,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/pcs440ep/pcs440ep.c b/board/pcs440ep/pcs440ep.c
index 96adbc915d..620000a229 100644
--- a/board/pcs440ep/pcs440ep.c
+++ b/board/pcs440ep/pcs440ep.c
@@ -798,8 +798,8 @@ int do_led (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 }
 
 U_BOOT_CMD(
- 	led,	2,	1,	do_led,
- 	"led [bitmask]   - set the DIAG-LED\n",
+	led,	2,	1,	do_led,
+	"led [bitmask]   - set the DIAG-LED\n",
 	"[bitmask] 0x01 = DIAG 1 on\n"
 	"              0x02 = DIAG 2 on\n"
 	"              0x04 = DIAG 3 on\n"
@@ -860,8 +860,8 @@ int do_sha1 (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 }
 
 U_BOOT_CMD(
- 	sha1,	4,	1,	do_sha1,
- 	"sha1    - calculate the SHA1 Sum\n",
+	sha1,	4,	1,	do_sha1,
+	"sha1    - calculate the SHA1 Sum\n",
 	"address len [addr]  calculate the SHA1 sum [save at addr]\n"
 	"     -p calculate the SHA1 sum from the U-Boot image in flash and print\n"
 	"     -c check the U-Boot image in flash\n"
diff --git a/board/pcs440ep/u-boot.lds b/board/pcs440ep/u-boot.lds
index 0a8ed67903..ed6135987f 100644
--- a/board/pcs440ep/u-boot.lds
+++ b/board/pcs440ep/u-boot.lds
@@ -43,11 +43,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/pm520/flash.c b/board/pm520/flash.c
index 38f579bc59..4301b8c234 100644
--- a/board/pm520/flash.c
+++ b/board/pm520/flash.c
@@ -35,36 +35,36 @@ flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips    */
 #undef FLASH_PORT_WIDTH16
 
 #ifdef FLASH_PORT_WIDTH16
-#define FLASH_PORT_WIDTH		ushort
-#define FLASH_PORT_WIDTHV		vu_short
-#define SWAP(x)               		(x)
+#define FLASH_PORT_WIDTH	ushort
+#define FLASH_PORT_WIDTHV	vu_short
+#define SWAP(x)			(x)
 #else
-#define FLASH_PORT_WIDTH		ulong
-#define FLASH_PORT_WIDTHV		vu_long
-#define SWAP(x)               		(x)
+#define FLASH_PORT_WIDTH	ulong
+#define FLASH_PORT_WIDTHV	vu_long
+#define SWAP(x)			(x)
 #endif
 
 /* Intel-compatible flash ID */
-#define INTEL_COMPAT  0x00890089
-#define INTEL_ALT     0x00B000B0
+#define INTEL_COMPAT		0x00890089
+#define INTEL_ALT		0x00B000B0
 
 /* Intel-compatible flash commands */
-#define INTEL_PROGRAM 0x00100010
-#define INTEL_ERASE   0x00200020
-#define INTEL_CLEAR   0x00500050
-#define INTEL_LOCKBIT 0x00600060
-#define INTEL_PROTECT 0x00010001
-#define INTEL_STATUS  0x00700070
-#define INTEL_READID  0x00900090
-#define INTEL_CONFIRM 0x00D000D0
-#define INTEL_RESET   0xFFFFFFFF
+#define INTEL_PROGRAM		0x00100010
+#define INTEL_ERASE		0x00200020
+#define INTEL_CLEAR		0x00500050
+#define INTEL_LOCKBIT		0x00600060
+#define INTEL_PROTECT		0x00010001
+#define INTEL_STATUS		0x00700070
+#define INTEL_READID		0x00900090
+#define INTEL_CONFIRM		0x00D000D0
+#define INTEL_RESET		0xFFFFFFFF
 
 /* Intel-compatible flash status bits */
-#define INTEL_FINISHED 0x00800080
-#define INTEL_OK       0x00800080
+#define INTEL_FINISHED		0x00800080
+#define INTEL_OK		0x00800080
 
-#define FPW	   FLASH_PORT_WIDTH
-#define FPWV   FLASH_PORT_WIDTHV
+#define FPW	FLASH_PORT_WIDTH
+#define FPWV	FLASH_PORT_WIDTHV
 
 #define mb() __asm__ __volatile__ ("" : : : "memory")
 
diff --git a/board/pm854/pm854.c b/board/pm854/pm854.c
index 5e7bf346cc..5d3252573e 100644
--- a/board/pm854/pm854.c
+++ b/board/pm854/pm854.c
@@ -93,7 +93,7 @@ initdram(int board_type)
 	    udelay (200);
 	    while (gur->ddrdllcr != 0x81000100)
 	    {
-	    	gur->devdisr = gur->devdisr | 0x00010000;
+		gur->devdisr = gur->devdisr | 0x00010000;
 		asm("sync;isync;msync");
 		for (i=0; i<x; i++)
 		    ;
diff --git a/board/pm854/u-boot.lds b/board/pm854/u-boot.lds
index 075d8f3852..f200810f06 100644
--- a/board/pm854/u-boot.lds
+++ b/board/pm854/u-boot.lds
@@ -43,11 +43,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/pm856/pm856.c b/board/pm856/pm856.c
index 792d1e5890..6386abcd3f 100644
--- a/board/pm856/pm856.c
+++ b/board/pm856/pm856.c
@@ -248,7 +248,7 @@ initdram(int board_type)
 	    udelay (200);
 	    while (gur->ddrdllcr != 0x81000100)
 	    {
-	    	gur->devdisr = gur->devdisr | 0x00010000;
+		gur->devdisr = gur->devdisr | 0x00010000;
 		asm("sync;isync;msync");
 		for (i=0; i<x; i++)
 		    ;
diff --git a/board/pm856/u-boot.lds b/board/pm856/u-boot.lds
index d52a325b89..01727d177b 100644
--- a/board/pm856/u-boot.lds
+++ b/board/pm856/u-boot.lds
@@ -44,11 +44,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/pn62/pn62.h b/board/pn62/pn62.h
index 7bda0ad9d0..f356a40f07 100644
--- a/board/pn62/pn62.h
+++ b/board/pn62/pn62.h
@@ -26,8 +26,8 @@
 /*
  * Definitions for the Intel Bridge 21554 or 21555.
  */
-#define I2155X_VPD_ADDR 	0xe6
-#define I2155X_VPD_DATA 	0xe8
+#define I2155X_VPD_ADDR		0xe6
+#define I2155X_VPD_DATA		0xe8
 
 #define I2155X_VPD_START	0x80
 #define I2155X_VPD_SN_START	0x80
@@ -65,17 +65,17 @@
  * Definitions for boot protocol using Scratchpad registers.
  */
 #define BOOT_DONE		0
-#define BOOT_DONE_CLEAR  	  0x00dead00
-#define BOOT_DONE_ERROR  	  0xbad0dead
-#define BOOT_DONE_U_BOOT 	  0x12345678
-#define BOOT_DONE_LINUX   	  0x87654321
-#define BOOT_CMD 		1
-#define BOOT_CMD_MOVE   	  0x1
-#define BOOT_CMD_BOOT		  0x2
+#define BOOT_DONE_CLEAR		0x00dead00
+#define BOOT_DONE_ERROR		0xbad0dead
+#define BOOT_DONE_U_BOOT	0x12345678
+#define BOOT_DONE_LINUX		0x87654321
+#define BOOT_CMD		1
+#define BOOT_CMD_MOVE		0x1
+#define BOOT_CMD_BOOT		0x2
 #define BOOT_DATA		2
 #define BOOT_PROTO		3
-#define BOOT_PROTO_READY	  0x23456789
-#define BOOT_PROTO_CLEAR	  0x00000000
+#define BOOT_PROTO_READY	0x23456789
+#define BOOT_PROTO_CLEAR	0x00000000
 #define BOOT_STATUS		4
 
 /*
@@ -145,15 +145,15 @@
 /*
  * Forward declarations
  */
-int  i2155x_init         (void);
+int  i2155x_init	 (void);
 void i2155x_write_scrapad(int idx, u32 val);
 u32  i2155x_read_scrapad (int idx);
 void i2155x_set_bar_base (int bar, u32 addr);
-int  i2155x_read_vpd     (int offset, int size, unsigned char *data);
+int  i2155x_read_vpd	 (int offset, int size, unsigned char *data);
 
 int  am79c95x_init	 (void);
 
-void set_led             (unsigned int number, unsigned int function);
+void set_led		 (unsigned int number, unsigned int function);
 void fatal_error	 (unsigned int error_code);
 void show_startup_phase  (int phase);
 
diff --git a/board/ppmc7xx/u-boot.lds b/board/ppmc7xx/u-boot.lds
index 3231325cbf..5239b35af2 100644
--- a/board/ppmc7xx/u-boot.lds
+++ b/board/ppmc7xx/u-boot.lds
@@ -37,11 +37,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/prodrive/alpr/u-boot.lds b/board/prodrive/alpr/u-boot.lds
index 9b1d91c3d0..d114bd61c9 100644
--- a/board/prodrive/alpr/u-boot.lds
+++ b/board/prodrive/alpr/u-boot.lds
@@ -43,11 +43,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/prodrive/p3mx/mpsc.c b/board/prodrive/p3mx/mpsc.c
index da95cfa777..2494ec6dfe 100644
--- a/board/prodrive/p3mx/mpsc.c
+++ b/board/prodrive/p3mx/mpsc.c
@@ -421,7 +421,7 @@ void mpsc_sdma_init (void)
 			 (MV64460_SDMA_WIN_ACCESS_FULL <<
 			  (MV64460_CUNIT_BASE_ADDR_WIN_0_BIT * 2)));
 
-	/* Setup MPSC internal address space base address 	*/
+	/* Setup MPSC internal address space base address	*/
 	GT_REG_WRITE (CUNIT_INTERNAL_SPACE_BASE_ADDR_REG, CFG_GT_REGS);
 
 	/* no high address remap*/
diff --git a/board/prodrive/p3mx/mpsc.h b/board/prodrive/p3mx/mpsc.h
index a03d1cc0f8..aa0f862ee8 100644
--- a/board/prodrive/p3mx/mpsc.h
+++ b/board/prodrive/p3mx/mpsc.h
@@ -67,9 +67,9 @@ extern int (*mpsc_test_char)(void);
 #define TX_STOP     0x00010000
 #define RX_ENABLE   0x00000080
 
-#define SDMA_RX_ABORT 		  (1 << 15)
-#define SDMA_TX_ABORT 		  (1 << 31)
-#define MPSC_TX_ABORT 		  (1 << 7)
+#define SDMA_RX_ABORT		  (1 << 15)
+#define SDMA_TX_ABORT		  (1 << 31)
+#define MPSC_TX_ABORT		  (1 << 7)
 #define MPSC_RX_ABORT             (1 << 23)
 #define MPSC_ENTER_HUNT           (1 << 31)
 
diff --git a/board/prodrive/p3mx/u-boot.lds b/board/prodrive/p3mx/u-boot.lds
index 25e16de3b6..1a95755ab4 100644
--- a/board/prodrive/p3mx/u-boot.lds
+++ b/board/prodrive/p3mx/u-boot.lds
@@ -37,11 +37,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/prodrive/p3p440/u-boot.lds b/board/prodrive/p3p440/u-boot.lds
index 2843642f9a..0e6c878a4d 100644
--- a/board/prodrive/p3p440/u-boot.lds
+++ b/board/prodrive/p3p440/u-boot.lds
@@ -43,11 +43,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/purple/purple.c b/board/purple/purple.c
index 13a14556ba..89cb906972 100644
--- a/board/purple/purple.c
+++ b/board/purple/purple.c
@@ -33,25 +33,25 @@
 
 #include "sconsole.h"
 
-#define cache_unroll(base,op)	        	\
-	__asm__ __volatile__("	         	\
-		.set noreorder;		        \
-		.set mips3;		        \
-		cache %1, (%0);	                \
-		.set mips0;			\
-		.set reorder"			\
-		:				\
-		: "r" (base),			\
+#define cache_unroll(base,op)		\
+	__asm__ __volatile__("		\
+		.set noreorder;		\
+		.set mips3;		\
+		cache %1, (%0);		\
+		.set mips0;		\
+		.set reorder"		\
+		:			\
+		: "r" (base),		\
 		  "i" (op));
 
 typedef void (*FUNCPTR)(ulong *source, ulong *destination, ulong nlongs);
 
 extern void	asc_serial_init		(void);
-extern void	asc_serial_putc 	(char);
-extern void	asc_serial_puts 	(const char *);
-extern int	asc_serial_getc 	(void);
-extern int	asc_serial_tstc 	(void);
-extern void	asc_serial_setbrg 	(void);
+extern void	asc_serial_putc		(char);
+extern void	asc_serial_puts		(const char *);
+extern int	asc_serial_getc		(void);
+extern int	asc_serial_tstc		(void);
+extern void	asc_serial_setbrg	(void);
 
 void _machine_restart(void)
 {
@@ -184,8 +184,7 @@ static void copydwords (ulong *source, ulong *destination, ulong nlongs)
 	ulong temp,temp1;
 	ulong *dstend = destination + nlongs;
 
-	while (destination < dstend)
-	{
+	while (destination < dstend) {
 		temp = *source++;
 		/* dummy read from sdram */
 		temp1 = *(ulong *)0xa0000000;
diff --git a/board/purple/sconsole.h b/board/purple/sconsole.h
index d441f37fcf..e130ad4c1c 100644
--- a/board/purple/sconsole.h
+++ b/board/purple/sconsole.h
@@ -26,21 +26,20 @@
 
 #include <config.h>
 
-typedef struct sconsole_buffer_s
-{
-  unsigned long		size;
-  unsigned long		max_size;
-  unsigned long 	pos;
-  char			data [1];
+typedef struct sconsole_buffer_s {
+	unsigned long size;
+	unsigned long max_size;
+	unsigned long pos;
+	char data[1];
 } sconsole_buffer_t;
 
 #define SCONSOLE_BUFFER		((sconsole_buffer_t *) CFG_SCONSOLE_ADDR)
 
-extern void	(* sconsole_putc) 	(char);
-extern void	(* sconsole_puts) 	(const char *);
-extern int	(* sconsole_getc) 	(void);
-extern int	(* sconsole_tstc) 	(void);
-extern void	(* sconsole_setbrg) 	(void);
+extern void	(* sconsole_putc)	(char);
+extern void	(* sconsole_puts)	(const char *);
+extern int	(* sconsole_getc)	(void);
+extern int	(* sconsole_tstc)	(void);
+extern void	(* sconsole_setbrg)	(void);
 
 extern void	sconsole_flush		(void);
 
diff --git a/board/pxa255_idp/lowlevel_init.S b/board/pxa255_idp/lowlevel_init.S
index aaa4d8eb93..80b5182cf9 100644
--- a/board/pxa255_idp/lowlevel_init.S
+++ b/board/pxa255_idp/lowlevel_init.S
@@ -39,7 +39,7 @@ DRAM_SIZE:  .long   CFG_DRAM_SIZE
 	.endm
 
 /*
- * 	Memory setup
+ *	Memory setup
  */
 .globl lowlevel_init
 lowlevel_init:
@@ -118,7 +118,7 @@ lowlevel_init:
 
 #ifdef DEBUG_BLINK_ENABLE
 	/* 4th debug blink */
-	bl 	blink
+	bl	blink
 #endif
 
 	/* ---------------------------------------------------------------- */
@@ -211,7 +211,7 @@ mem_init:
 
 #ifdef DEBUG_BLINK_ENABLE
 	/* 5th blink */
-	bl 	blink
+	bl	blink
 #endif
 
 	/* ---------------------------------------------------------------- */
@@ -326,14 +326,14 @@ mem_init:
 #if 0
 	/* FIXME turn on serial ports */
 	/* look into moving this to board_init() */
-	ldr 	r2, =(PXA_CS5_PHYS + 0x03C0002c)
+	ldr	r2, =(PXA_CS5_PHYS + 0x03C0002c)
 	mov	r3, #0x13
 	str	r3, [r2]
 #endif
 
 #ifdef DEBUG_BLINK_ENABLE
 	/* 6th blink */
-	bl 	blink
+	bl	blink
 #endif
 
 	/* ---------------------------------------------------------------- */
@@ -423,7 +423,7 @@ initclks:
 
 #ifdef DEBUG_BLINK_ENABLE
 	/* 7th blink */
-	bl 	blink
+	bl	blink
 #endif
 
 endlowlevel_init:
diff --git a/board/quantum/fpga.h b/board/quantum/fpga.h
index 2ef45e59b1..79b73b561e 100644
--- a/board/quantum/fpga.h
+++ b/board/quantum/fpga.h
@@ -31,4 +31,3 @@ int fpga_boot(unsigned char *fpgadata, int size);
 #define ERROR_FPGA_PRG_INIT_LOW  -1        /* Timeout after PRG* asserted   */
 #define ERROR_FPGA_PRG_INIT_HIGH -2        /* Timeout after PRG* deasserted */
 #define ERROR_FPGA_PRG_DONE      -3        /* Timeout after programming     */
-/* vim: set ts=4 sw=4 tw=78: */
diff --git a/board/quantum/u-boot.lds b/board/quantum/u-boot.lds
index dbea90cd2a..1f9a191d47 100644
--- a/board/quantum/u-boot.lds
+++ b/board/quantum/u-boot.lds
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/quantum/u-boot.lds.debug b/board/quantum/u-boot.lds.debug
index 5cedcb13e0..0cd053a8bb 100644
--- a/board/quantum/u-boot.lds.debug
+++ b/board/quantum/u-boot.lds.debug
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/r360mpi/pcmcia.c b/board/r360mpi/pcmcia.c
index a83ca8da47..4fd9d1298b 100644
--- a/board/r360mpi/pcmcia.c
+++ b/board/r360mpi/pcmcia.c
@@ -195,10 +195,10 @@ int pcmcia_voltage_set(int slot, int vcc, int vpp)
 
 	reg = 0;
 	switch(vcc) {
-		case  0: 		break;
+		case  0:		break;
 		case 33: reg |= 0x0200;	break;
 		case 50: reg |= 0x0400;	break;
-		default: 		goto done;
+		default:		goto done;
 	}
 
 	/* Checking supported voltages */
diff --git a/board/r360mpi/u-boot.lds b/board/r360mpi/u-boot.lds
index c3708bf5bc..5fcd5c9f1b 100644
--- a/board/r360mpi/u-boot.lds
+++ b/board/r360mpi/u-boot.lds
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/r7780mp/lowlevel_init.S b/board/r7780mp/lowlevel_init.S
index eb5d8b721d..05c075b6ca 100644
--- a/board/r7780mp/lowlevel_init.S
+++ b/board/r7780mp/lowlevel_init.S
@@ -326,11 +326,11 @@ RWTCSR_D_1:				.word	0xA507
 RWTCSR_D_2:				.word	0xA507
 RWTCNT_D:				.word	0x5A00
 
-BBG_PMMR_A: 			.long	0xFF800010
+BBG_PMMR_A:			.long	0xFF800010
 BBG_PMSR1_A:			.long	0xFF800014
 BBG_PMSR2_A:			.long	0xFF800018
 BBG_PMSR3_A:			.long	0xFF80001C
-BBG_PMSR4_A:			.long 	0xFF800020
+BBG_PMSR4_A:			.long	0xFF800020
 BBG_PMSRG_A:			.long	0xFF800024
 
 BBG_PMMR_D_PMSR1:       .long	0xffffbffd
@@ -339,7 +339,7 @@ BBG_PMMR_D_PMSR2:       .long	0xfc21a7ff
 BBG_PMSR2_D:            .long	0x03de5800
 BBG_PMMR_D_PMSR3:       .long	0xfffffff8
 BBG_PMSR3_D:            .long	0x00000007
-BBG_PMMR_D_PMSR4:       .long 	0xdffdfff9
+BBG_PMMR_D_PMSR4:       .long	0xdffdfff9
 BBG_PMSR4_D:            .long	0x20020006
 BBG_PMMR_D_PMSRG:       .long	0xffffffff
 BBG_PMSRG_D:            .long	0x00000000
diff --git a/board/rbc823/flash.c b/board/rbc823/flash.c
index 84ae5c1b5d..26ebcae860 100644
--- a/board/rbc823/flash.c
+++ b/board/rbc823/flash.c
@@ -131,11 +131,11 @@ void flash_print_info  (flash_info_t *info)
 
 	if (info->size >> 20) {
 	    printf ("  Size: %ld MB in %d Sectors\n",
-	    	info->size >> 20,
+		info->size >> 20,
 		info->sector_count);
 	} else {
 	    printf ("  Size: %ld KB in %d Sectors\n",
-	    	info->size >> 10,
+		info->size >> 10,
 		info->sector_count);
 	}
 
@@ -213,7 +213,7 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
 			info->flash_id += FLASH_AM040;
 			info->sector_count = 8;
 			info->size = 0x00080000;
-			break;				/* => 512Kb 		*/
+			break;				/* => 512Kb		*/
 
 		default:
 			info->flash_id = FLASH_UNKNOWN;
@@ -448,7 +448,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data)
 
 	    /* re-enable interrupts if necessary */
 	    if (flag)
-	    	enable_interrupts();
+		enable_interrupts();
 
 	    /* data polling for D7 */
 	    start = get_timer (0);
diff --git a/board/rbc823/u-boot.lds b/board/rbc823/u-boot.lds
index 8350edadc3..e41782554f 100644
--- a/board/rbc823/u-boot.lds
+++ b/board/rbc823/u-boot.lds
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/rmu/u-boot.lds b/board/rmu/u-boot.lds
index dbea90cd2a..1f9a191d47 100644
--- a/board/rmu/u-boot.lds
+++ b/board/rmu/u-boot.lds
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/rmu/u-boot.lds.debug b/board/rmu/u-boot.lds.debug
index 5cedcb13e0..0cd053a8bb 100644
--- a/board/rmu/u-boot.lds.debug
+++ b/board/rmu/u-boot.lds.debug
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/rsdproto/flash.c b/board/rsdproto/flash.c
index 5ad3218520..4e43b29660 100644
--- a/board/rsdproto/flash.c
+++ b/board/rsdproto/flash.c
@@ -76,17 +76,17 @@ unsigned long flash_init (void)
 		unsigned long long *f_addr = (unsigned long long *)PHYS_FLASH;
 		unsigned long long f_command, vendor, device;
 		/* Perform Autoselect */
-		f_command 	= 0x00AA00AA00AA00AAULL;
+		f_command	= 0x00AA00AA00AA00AAULL;
 		ull_write(&f_addr[0x555], &f_command);
-		f_command 	= 0x0055005500550055ULL;
+		f_command	= 0x0055005500550055ULL;
 		ull_write(&f_addr[0x2AA], &f_command);
-		f_command 	= 0x0090009000900090ULL;
+		f_command	= 0x0090009000900090ULL;
 		ull_write(&f_addr[0x555], &f_command);
 		ull_read(&f_addr[0], &vendor);
 		vendor &= 0xffff;
 		ull_read(&f_addr[1], &device);
 		device &= 0xffff;
-		f_command 	= 0x00F000F000F000F0ULL;
+		f_command	= 0x00F000F000F000F0ULL;
 		ull_write(&f_addr[0x555], &f_command);
 		if (vendor != VENDOR_AMD || device != AMD_29DL323C_B)
 		  return 0;
@@ -225,16 +225,16 @@ int	flash_erase (flash_info_t *info, int s_first, int s_last)
 		printf ("\n");
     }
 
-	f_addr 	= (unsigned long long *)info->start[0];
-	f_command 	= 0x00AA00AA00AA00AAULL;
+	f_addr	= (unsigned long long *)info->start[0];
+	f_command	= 0x00AA00AA00AA00AAULL;
 	ull_write(&f_addr[0x555], &f_command);
-	f_command 	= 0x0055005500550055ULL;
+	f_command	= 0x0055005500550055ULL;
 	ull_write(&f_addr[0x2AA], &f_command);
-	f_command 	= 0x0080008000800080ULL;
+	f_command	= 0x0080008000800080ULL;
 	ull_write(&f_addr[0x555], &f_command);
-	f_command 	= 0x00AA00AA00AA00AAULL;
+	f_command	= 0x00AA00AA00AA00AAULL;
 	ull_write(&f_addr[0x555], &f_command);
-	f_command 	= 0x0055005500550055ULL;
+	f_command	= 0x0055005500550055ULL;
 	ull_write(&f_addr[0x2AA], &f_command);
 
     /* Disable interrupts which might cause a timeout here */
@@ -244,9 +244,9 @@ int	flash_erase (flash_info_t *info, int s_first, int s_last)
     for (l_sect = -1, sect = s_first; sect<=s_last; sect++) {
 		if (info->protect[sect] == 0) {	/* not protected */
 
-			f_addr 	=
+			f_addr	=
 			  (unsigned long long *)(info->start[sect]);
-			f_command 	= 0x0030003000300030ULL;
+			f_command	= 0x0030003000300030ULL;
 			ull_write(f_addr, &f_command);
 			l_sect = sect;
 		}
@@ -264,7 +264,7 @@ int	flash_erase (flash_info_t *info, int s_first, int s_last)
 			/* this command turns the flash back to read mode     */
 			f_addr =
 			  (unsigned long long *)(info->start[l_sect]);
-			f_command 	= 0x00F000F000F000F0ULL;
+			f_command	= 0x00F000F000F000F0ULL;
 			ull_write(f_addr, &f_command);
 			printf (" timeout\n");
 			return 1;
@@ -357,7 +357,7 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
 *
 * PARAMETERS:   32 bit long pointer to address, 64 bit long pointer to data
 *
-* RETURNS: 	0 if OK, 1 if timeout, 4 if parameter error
+* RETURNS:	0 if OK, 1 if timeout, 4 if parameter error
 *--------------------------------------------------------------------------*/
 
 static unsigned char write_ull(flash_info_t *info,
@@ -372,16 +372,16 @@ static unsigned char write_ull(flash_info_t *info,
 	if (address & 0x7)
 	  return ERR_ALIGN;
 
-	f_addr 	= (unsigned long long *)info->start[0];
-	f_command 	= 0x00AA00AA00AA00AAULL;
+	f_addr	= (unsigned long long *)info->start[0];
+	f_command	= 0x00AA00AA00AA00AAULL;
 	ull_write(&f_addr[0x555], &f_command);
-	f_command 	= 0x0055005500550055ULL;
+	f_command	= 0x0055005500550055ULL;
 	ull_write(&f_addr[0x2AA], &f_command);
-	f_command 	= 0x00A000A000A000A0ULL;
+	f_command	= 0x00A000A000A000A0ULL;
 	ull_write(&f_addr[0x555], &f_command);
 
-	f_addr 	= (unsigned long long *)address;
-	f_command 	= data;
+	f_addr	= (unsigned long long *)address;
+	f_command	= data;
 	ull_write(f_addr, &f_command);
 
 	start = get_timer (0);
@@ -391,8 +391,8 @@ static unsigned char write_ull(flash_info_t *info,
 		{
 			/* write reset command, command address is unimportant */
 			/* this command turns the flash back to read mode     */
-			f_addr 	= (unsigned long long *)info->start[0];
-			f_command 	= 0x00F000F000F000F0ULL;
+			f_addr	= (unsigned long long *)info->start[0];
+			f_command	= 0x00F000F000F000F0ULL;
 			ull_write(f_addr, &f_command);
 			return ERR_TIMOUT;
 		}
diff --git a/board/rsdproto/u-boot.lds b/board/rsdproto/u-boot.lds
index 63dda1f2a7..07a7277c83 100644
--- a/board/rsdproto/u-boot.lds
+++ b/board/rsdproto/u-boot.lds
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/sandburst/karef/u-boot.lds b/board/sandburst/karef/u-boot.lds
index bc628d99f6..216f9c64dc 100644
--- a/board/sandburst/karef/u-boot.lds
+++ b/board/sandburst/karef/u-boot.lds
@@ -44,11 +44,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)	}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)	}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)	}
   .rela.got      : { *(.rela.got)	}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/sandburst/karef/u-boot.lds.debug b/board/sandburst/karef/u-boot.lds.debug
index a2352a37df..af7d5c08aa 100644
--- a/board/sandburst/karef/u-boot.lds.debug
+++ b/board/sandburst/karef/u-boot.lds.debug
@@ -34,11 +34,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)	}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)	}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)	}
   .rela.got      : { *(.rela.got)	}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/sandburst/metrobox/u-boot.lds b/board/sandburst/metrobox/u-boot.lds
index ebc44d9125..6abf3f390a 100644
--- a/board/sandburst/metrobox/u-boot.lds
+++ b/board/sandburst/metrobox/u-boot.lds
@@ -44,11 +44,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)	}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)	}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)	}
   .rela.got      : { *(.rela.got)	}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/sandburst/metrobox/u-boot.lds.debug b/board/sandburst/metrobox/u-boot.lds.debug
index 8f4c6d7c1d..527c264326 100644
--- a/board/sandburst/metrobox/u-boot.lds.debug
+++ b/board/sandburst/metrobox/u-boot.lds.debug
@@ -34,11 +34,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)	}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)	}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)	}
   .rela.got      : { *(.rela.got)	}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/sandpoint/sandpoint.c b/board/sandpoint/sandpoint.c
index d3445bd92d..aeb10a7434 100644
--- a/board/sandpoint/sandpoint.c
+++ b/board/sandpoint/sandpoint.c
@@ -40,7 +40,7 @@ int checkboard (void)
 	return 0;
 }
 
-#if 0 	/* NOT USED */
+#if 0	/* NOT USED */
 int checkflash (void)
 {
 	/* TODO: XXX XXX XXX */
diff --git a/board/sandpoint/speed.h b/board/sandpoint/speed.h
index b66393bec5..3f32a143cc 100644
--- a/board/sandpoint/speed.h
+++ b/board/sandpoint/speed.h
@@ -28,10 +28,10 @@
  * SPEED_TMR3_PS = (GCLK / (16 * SPEED_FCOUNT3)) - 1
  *
  * SPEED_FCOUNT2	timer 2 counting frequency
- * GCLK	      		CPU clock
+ * GCLK			CPU clock
  * SPEED_TMR2_PS	prescaler
  */
-#define SPEED_TMR2_PS  	(250 - 1)	/* divide by 250	*/
+#define SPEED_TMR2_PS	(250 - 1)	/* divide by 250	*/
 
 /*-----------------------------------------------------------------------
  * Timer value for PIT
diff --git a/board/sbc405/u-boot.lds b/board/sbc405/u-boot.lds
index a9696739b6..7b1c6b211d 100644
--- a/board/sbc405/u-boot.lds
+++ b/board/sbc405/u-boot.lds
@@ -38,11 +38,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/sbc8548/law.c b/board/sbc8548/law.c
index d903cdc2b3..bcf3468ba6 100644
--- a/board/sbc8548/law.c
+++ b/board/sbc8548/law.c
@@ -40,7 +40,7 @@
  * 0xff80_0000	0xffff_ffff	FLASH (boot bank)	8M
  *
  * Notes:
- * 	CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ *	CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
  *	If flash is 8M at default position (last 8M), no LAW needed.
  */
 
diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c
index 46496da60b..9c8c6733f7 100644
--- a/board/sbc8548/sbc8548.c
+++ b/board/sbc8548/sbc8548.c
@@ -310,7 +310,7 @@ long int fixed_sdram (void)
 	ddr->sdram_interval	= 0x05080100;
 	ddr->sdram_md_cntl	= 0x00000000;
 	ddr->sdram_data_init	= 0x00000000;
-	ddr->sdram_clk_cntl 	= 0x03800000;
+	ddr->sdram_clk_cntl	= 0x03800000;
 	asm("sync;isync;msync");
 	udelay(500);
 
diff --git a/board/sbc8548/u-boot.lds b/board/sbc8548/u-boot.lds
index 03f62b8259..eba7e8a9d3 100644
--- a/board/sbc8548/u-boot.lds
+++ b/board/sbc8548/u-boot.lds
@@ -42,11 +42,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/sbc8560/u-boot.lds b/board/sbc8560/u-boot.lds
index 4b31797d74..ba5ce0bd60 100644
--- a/board/sbc8560/u-boot.lds
+++ b/board/sbc8560/u-boot.lds
@@ -46,11 +46,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/sbc8641d/u-boot.lds b/board/sbc8641d/u-boot.lds
index be362eed03..a9e9d80a10 100644
--- a/board/sbc8641d/u-boot.lds
+++ b/board/sbc8641d/u-boot.lds
@@ -31,11 +31,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/sc3/sc3.c b/board/sc3/sc3.c
index 09407647ab..fbdc1d769c 100644
--- a/board/sc3/sc3.c
+++ b/board/sc3/sc3.c
@@ -446,7 +446,7 @@ static void printCSConfig(int reg,unsigned long ap,unsigned long cr)
 		printf(" at 0x%08lX", cr & 0xFFF00000U);
 		printf(" size: %u MB", banks[(cr & 0x000E0000) >> 17]);
 		printf(" rights: %s", bankaccess[(cr & 0x00018000) >> 15]);
-   	   	if (ap & 0x80000000) {
+		if (ap & 0x80000000) {
 			printf("\n -Burst device (%luns/%luns)",
 				(((ap & 0x7C000000) >> 26) + 1) * CYCLE,
 				(((ap & 0x03800000) >> 23) + 1) * CYCLE);
diff --git a/board/sc3/sc3.h b/board/sc3/sc3.h
index cf920f9f51..060aecedef 100644
--- a/board/sc3/sc3.h
+++ b/board/sc3/sc3.h
@@ -85,7 +85,7 @@ static unsigned long inline hcReadDWord (unsigned long base, unsigned int offset
 
 /* control and status registers isp1161 */
 #define HcRevision		0x00
-#define HcControl 		0x01
+#define HcControl		0x01
 #define HcCommandStatus		0x02
 #define HcInterruptStatus	0x03
 #define HcInterruptEnable	0x04
diff --git a/board/sc3/u-boot.lds b/board/sc3/u-boot.lds
index 24cf46c26e..27cc0b928c 100644
--- a/board/sc3/u-boot.lds
+++ b/board/sc3/u-boot.lds
@@ -38,11 +38,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/sc520_cdp/sc520_cdp.c b/board/sc520_cdp/sc520_cdp.c
index f6f0e72443..8050aa6fee 100644
--- a/board/sc520_cdp/sc520_cdp.c
+++ b/board/sc520_cdp/sc520_cdp.c
@@ -233,9 +233,9 @@ static void bus_init(void)
 {
 
 	/* set up the GP IO pins */
-	write_mmcr_word(SC520_PIOPFS31_16, 0xf7ff); 	/* set the GPIO pin function 31-16 reg */
-	write_mmcr_word(SC520_PIOPFS15_0, 0xffff);  	/* set the GPIO pin function 15-0 reg */
-	write_mmcr_byte(SC520_CSPFS, 0xf8);  		/* set the CS pin function  reg */
+	write_mmcr_word(SC520_PIOPFS31_16, 0xf7ff);	/* set the GPIO pin function 31-16 reg */
+	write_mmcr_word(SC520_PIOPFS15_0, 0xffff);	/* set the GPIO pin function 15-0 reg */
+	write_mmcr_byte(SC520_CSPFS, 0xf8);		/* set the CS pin function  reg */
 	write_mmcr_byte(SC520_CLKSEL, 0x70);
 
 
diff --git a/board/sc520_cdp/sc520_cdp_asm.S b/board/sc520_cdp/sc520_cdp_asm.S
index 7f70d65d5f..6ac5a5de9d 100644
--- a/board/sc520_cdp/sc520_cdp_asm.S
+++ b/board/sc520_cdp/sc520_cdp_asm.S
@@ -73,7 +73,7 @@ done:   movb	$0x88, %al
 	movw	$0x680, %dx
 	out	%al, %dx
 
-	jmp 	*%ebp		     /* return to caller */
+	jmp	*%ebp		     /* return to caller */
 
 
 .globl show_boot_progress
diff --git a/board/sc520_cdp/u-boot.lds b/board/sc520_cdp/u-boot.lds
index 12c850f4e4..96093263e9 100644
--- a/board/sc520_cdp/u-boot.lds
+++ b/board/sc520_cdp/u-boot.lds
@@ -33,7 +33,7 @@ SECTIONS
 	. = ALIGN(4);
 	.rodata : { *(.rodata) *(.rodata.str1.1) *(.rodata.str1.32) }
 
-	. = 0x400000; 	                    /* Ram data segment to use */
+	. = 0x400000;	                    /* Ram data segment to use */
 	_i386boot_romdata_dest = ABSOLUTE(.);
 	.data : AT ( LOADADDR(.rodata) + SIZEOF(.rodata) ) { *(.data) }
 	_i386boot_romdata_start = LOADADDR(.data);
diff --git a/board/sc520_spunk/sc520_spunk.c b/board/sc520_spunk/sc520_spunk.c
index d119a7d997..038d479953 100644
--- a/board/sc520_spunk/sc520_spunk.c
+++ b/board/sc520_spunk/sc520_spunk.c
@@ -256,11 +256,11 @@ static void bus_init(void)
 
 	if (version) {
 		/* set up the GP IO pins (for the Spunk board) */
-		write_mmcr_word(SC520_PIOPFS31_16, 0xfff0); 	/* set the GPIO pin function 31-16 reg */
-		write_mmcr_word(SC520_PIOPFS15_0,  0x000f);  	/* set the GPIO pin function 15-0 reg */
-		write_mmcr_word(SC520_PIODIR31_16, 0x000f); 	/* set the GPIO direction 31-16 reg */
-		write_mmcr_word(SC520_PIODIR15_0,  0x1ff0);  	/* set the GPIO direction 15-0 reg */
-		write_mmcr_byte(SC520_CSPFS, 0xc0);  		/* set the CS pin function reg */
+		write_mmcr_word(SC520_PIOPFS31_16, 0xfff0);	/* set the GPIO pin function 31-16 reg */
+		write_mmcr_word(SC520_PIOPFS15_0,  0x000f);	/* set the GPIO pin function 15-0 reg */
+		write_mmcr_word(SC520_PIODIR31_16, 0x000f);	/* set the GPIO direction 31-16 reg */
+		write_mmcr_word(SC520_PIODIR15_0,  0x1ff0);	/* set the GPIO direction 15-0 reg */
+		write_mmcr_byte(SC520_CSPFS, 0xc0);		/* set the CS pin function reg */
 		write_mmcr_byte(SC520_CLKSEL, 0x70);
 
 		write_mmcr_word(SC520_PIOCLR31_16, 0x0003);     /* reset SSI chip-selects */
@@ -268,11 +268,11 @@ static void bus_init(void)
 
 	} else {
 		/* set up the GP IO pins (for the Hyglo board) */
-		write_mmcr_word(SC520_PIOPFS31_16, 0xffc0); 	/* set the GPIO pin function 31-16 reg */
-		write_mmcr_word(SC520_PIOPFS15_0, 0x1e7f);  	/* set the GPIO pin function 15-0 reg */
-		write_mmcr_word(SC520_PIODIR31_16, 0x003f); 	/* set the GPIO direction 31-16 reg */
-		write_mmcr_word(SC520_PIODIR15_0, 0xe180);  	/* set the GPIO direction 15-0 reg */
-		write_mmcr_byte(SC520_CSPFS, 0x00);  		/* set the CS pin function reg */
+		write_mmcr_word(SC520_PIOPFS31_16, 0xffc0);	/* set the GPIO pin function 31-16 reg */
+		write_mmcr_word(SC520_PIOPFS15_0, 0x1e7f);	/* set the GPIO pin function 15-0 reg */
+		write_mmcr_word(SC520_PIODIR31_16, 0x003f);	/* set the GPIO direction 31-16 reg */
+		write_mmcr_word(SC520_PIODIR15_0, 0xe180);	/* set the GPIO direction 15-0 reg */
+		write_mmcr_byte(SC520_CSPFS, 0x00);		/* set the CS pin function reg */
 		write_mmcr_byte(SC520_CLKSEL, 0x70);
 
 		write_mmcr_word(SC520_PIOCLR15_0, 0x0180);      /* reset SSI chip-selects */
@@ -656,7 +656,7 @@ ssize_t spi_read(uchar *addr, int alen, uchar *buffer, int len)
 		offset |= addr[i];
 	}
 
-	return 	read_mmcr_byte(SC520_SYSINFO) ?
+	return	read_mmcr_byte(SC520_SYSINFO) ?
 		spi_eeprom_read(1, offset, buffer, len) :
 	mw_eeprom_read(1, offset, buffer, len);
 }
@@ -672,7 +672,7 @@ ssize_t spi_write(uchar *addr, int alen, uchar *buffer, int len)
 		offset |= addr[i];
 	}
 
-	return 	read_mmcr_byte(SC520_SYSINFO) ?
+	return	read_mmcr_byte(SC520_SYSINFO) ?
 		spi_eeprom_write(1, offset, buffer, len) :
 	mw_eeprom_write(1, offset, buffer, len);
 }
diff --git a/board/sc520_spunk/sc520_spunk_asm.S b/board/sc520_spunk/sc520_spunk_asm.S
index 0127076db1..3430b6adba 100644
--- a/board/sc520_spunk/sc520_spunk_asm.S
+++ b/board/sc520_spunk/sc520_spunk_asm.S
@@ -70,7 +70,7 @@ next:	addl	$8, %esi             /* advance esi */
 done:   movl    $0xfffefc32,%edx
 	movw    $0000,(%edx)
 
-	jmp 	*%ebp		     /* return to caller */
+	jmp	*%ebp		     /* return to caller */
 
 
 .globl show_boot_progress
diff --git a/board/sc520_spunk/u-boot.lds b/board/sc520_spunk/u-boot.lds
index 887e0a0897..33480d3286 100644
--- a/board/sc520_spunk/u-boot.lds
+++ b/board/sc520_spunk/u-boot.lds
@@ -34,7 +34,7 @@ SECTIONS
 	. = ALIGN(4);
 	.rodata : { *(.rodata) }
 
-	. = 0x400000; 	                    /* Ram data segment to use */
+	. = 0x400000;	                    /* Ram data segment to use */
 	_i386boot_romdata_dest = ABSOLUTE(.);
 	.data : AT ( LOADADDR(.rodata) + SIZEOF(.rodata) ) { *(.data) }
 	_i386boot_romdata_start = LOADADDR(.data);
diff --git a/board/siemens/CCM/u-boot.lds b/board/siemens/CCM/u-boot.lds
index ee598c2cfc..10b38ec356 100644
--- a/board/siemens/CCM/u-boot.lds
+++ b/board/siemens/CCM/u-boot.lds
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/siemens/CCM/u-boot.lds.debug b/board/siemens/CCM/u-boot.lds.debug
index d799f939e9..bf63991976 100644
--- a/board/siemens/CCM/u-boot.lds.debug
+++ b/board/siemens/CCM/u-boot.lds.debug
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/siemens/IAD210/u-boot.lds b/board/siemens/IAD210/u-boot.lds
index 6a1e718a47..291f6b3684 100644
--- a/board/siemens/IAD210/u-boot.lds
+++ b/board/siemens/IAD210/u-boot.lds
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/siemens/SMN42/lowlevel_init.S b/board/siemens/SMN42/lowlevel_init.S
index 11abb63324..f13d9b9823 100644
--- a/board/siemens/SMN42/lowlevel_init.S
+++ b/board/siemens/SMN42/lowlevel_init.S
@@ -26,11 +26,11 @@
 
 /* some parameters for the board */
 /* setting up the CPU-internal memory */
-#define 	SRAM_START 	0x40000000
-#define 	SRAM_SIZE	0x00004000
-#define   BCFG0_VALUE 0x1000ffef
-#define   BCFG1_VALUE 0x10005D2F
-#define   BCFG2_VALUE 0x10005D2F
+#define	SRAM_START	0x40000000
+#define	SRAM_SIZE	0x00004000
+#define BCFG0_VALUE	0x1000ffef
+#define BCFG1_VALUE	0x10005D2F
+#define BCFG2_VALUE	0x10005D2F
 /*
  * For P0.18 to set ZZ to the SRAMs to 1. Also set P0.2 (SCL) and P0.3 (SDA)
  * for the bit-banger I2C driver correctly.
diff --git a/board/siemens/pcu_e/u-boot.lds b/board/siemens/pcu_e/u-boot.lds
index 93015712e5..bc1ea73723 100644
--- a/board/siemens/pcu_e/u-boot.lds
+++ b/board/siemens/pcu_e/u-boot.lds
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)	}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)	}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)	}
   .rela.got      : { *(.rela.got)	}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/siemens/pcu_e/u-boot.lds.debug b/board/siemens/pcu_e/u-boot.lds.debug
index 44bae70884..2ee8237451 100644
--- a/board/siemens/pcu_e/u-boot.lds.debug
+++ b/board/siemens/pcu_e/u-boot.lds.debug
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)	}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)	}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)	}
   .rela.got      : { *(.rela.got)	}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/sixnet/u-boot.lds b/board/sixnet/u-boot.lds
index 343c4d7e2f..b91c44a57d 100644
--- a/board/sixnet/u-boot.lds
+++ b/board/sixnet/u-boot.lds
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/sl8245/Makefile b/board/sl8245/Makefile
index d3db1a90e2..dcb1907032 100644
--- a/board/sl8245/Makefile
+++ b/board/sl8245/Makefile
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS 	= $(BOARD).o flash.o
+COBJS	= $(BOARD).o flash.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
diff --git a/board/smdk2410/lowlevel_init.S b/board/smdk2410/lowlevel_init.S
index 310f2a0a94..ab6afdd488 100644
--- a/board/smdk2410/lowlevel_init.S
+++ b/board/smdk2410/lowlevel_init.S
@@ -45,85 +45,85 @@
 #define BWSCON	0x48000000
 
 /* BWSCON */
-#define DW8		 	(0x0)
-#define DW16		 	(0x1)
-#define DW32		 	(0x2)
-#define WAIT		 	(0x1<<2)
-#define UBLB		 	(0x1<<3)
-
-#define B1_BWSCON	  	(DW32)
-#define B2_BWSCON	  	(DW16)
-#define B3_BWSCON	  	(DW16 + WAIT + UBLB)
-#define B4_BWSCON	  	(DW16)
-#define B5_BWSCON	  	(DW16)
-#define B6_BWSCON	  	(DW32)
-#define B7_BWSCON	  	(DW32)
+#define DW8			(0x0)
+#define DW16			(0x1)
+#define DW32			(0x2)
+#define WAIT			(0x1<<2)
+#define UBLB			(0x1<<3)
+
+#define B1_BWSCON		(DW32)
+#define B2_BWSCON		(DW16)
+#define B3_BWSCON		(DW16 + WAIT + UBLB)
+#define B4_BWSCON		(DW16)
+#define B5_BWSCON		(DW16)
+#define B6_BWSCON		(DW32)
+#define B7_BWSCON		(DW32)
 
 /* BANK0CON */
-#define B0_Tacs		 	0x0	/*  0clk */
-#define B0_Tcos		 	0x0	/*  0clk */
-#define B0_Tacc		 	0x7	/* 14clk */
-#define B0_Tcoh		 	0x0	/*  0clk */
-#define B0_Tah		 	0x0	/*  0clk */
-#define B0_Tacp		 	0x0
-#define B0_PMC		 	0x0	/* normal */
+#define B0_Tacs			0x0	/*  0clk */
+#define B0_Tcos			0x0	/*  0clk */
+#define B0_Tacc			0x7	/* 14clk */
+#define B0_Tcoh			0x0	/*  0clk */
+#define B0_Tah			0x0	/*  0clk */
+#define B0_Tacp			0x0
+#define B0_PMC			0x0	/* normal */
 
 /* BANK1CON */
-#define B1_Tacs		 	0x0	/*  0clk */
-#define B1_Tcos		 	0x0	/*  0clk */
-#define B1_Tacc		 	0x7	/* 14clk */
-#define B1_Tcoh		 	0x0	/*  0clk */
-#define B1_Tah		 	0x0	/*  0clk */
-#define B1_Tacp		 	0x0
-#define B1_PMC		 	0x0
-
-#define B2_Tacs		 	0x0
-#define B2_Tcos		 	0x0
-#define B2_Tacc		 	0x7
-#define B2_Tcoh		 	0x0
-#define B2_Tah		 	0x0
-#define B2_Tacp		 	0x0
-#define B2_PMC		 	0x0
-
-#define B3_Tacs		 	0x0	/*  0clk */
-#define B3_Tcos		 	0x3	/*  4clk */
-#define B3_Tacc		 	0x7	/* 14clk */
-#define B3_Tcoh		 	0x1	/*  1clk */
-#define B3_Tah		 	0x0	/*  0clk */
-#define B3_Tacp		 	0x3     /*  6clk */
-#define B3_PMC		 	0x0	/* normal */
-
-#define B4_Tacs		 	0x0	/*  0clk */
-#define B4_Tcos		 	0x0	/*  0clk */
-#define B4_Tacc		 	0x7	/* 14clk */
-#define B4_Tcoh		 	0x0	/*  0clk */
-#define B4_Tah		 	0x0	/*  0clk */
-#define B4_Tacp		 	0x0
-#define B4_PMC		 	0x0	/* normal */
-
-#define B5_Tacs		 	0x0	/*  0clk */
-#define B5_Tcos		 	0x0	/*  0clk */
-#define B5_Tacc		 	0x7	/* 14clk */
-#define B5_Tcoh		 	0x0	/*  0clk */
-#define B5_Tah		 	0x0	/*  0clk */
-#define B5_Tacp		 	0x0
-#define B5_PMC		 	0x0	/* normal */
-
-#define B6_MT		 	0x3	/* SDRAM */
-#define B6_Trcd	 	 	0x1
-#define B6_SCAN		 	0x1	/* 9bit */
-
-#define B7_MT		 	0x3	/* SDRAM */
-#define B7_Trcd		 	0x1	/* 3clk */
-#define B7_SCAN		 	0x1	/* 9bit */
+#define B1_Tacs			0x0	/*  0clk */
+#define B1_Tcos			0x0	/*  0clk */
+#define B1_Tacc			0x7	/* 14clk */
+#define B1_Tcoh			0x0	/*  0clk */
+#define B1_Tah			0x0	/*  0clk */
+#define B1_Tacp			0x0
+#define B1_PMC			0x0
+
+#define B2_Tacs			0x0
+#define B2_Tcos			0x0
+#define B2_Tacc			0x7
+#define B2_Tcoh			0x0
+#define B2_Tah			0x0
+#define B2_Tacp			0x0
+#define B2_PMC			0x0
+
+#define B3_Tacs			0x0	/*  0clk */
+#define B3_Tcos			0x3	/*  4clk */
+#define B3_Tacc			0x7	/* 14clk */
+#define B3_Tcoh			0x1	/*  1clk */
+#define B3_Tah			0x0	/*  0clk */
+#define B3_Tacp			0x3     /*  6clk */
+#define B3_PMC			0x0	/* normal */
+
+#define B4_Tacs			0x0	/*  0clk */
+#define B4_Tcos			0x0	/*  0clk */
+#define B4_Tacc			0x7	/* 14clk */
+#define B4_Tcoh			0x0	/*  0clk */
+#define B4_Tah			0x0	/*  0clk */
+#define B4_Tacp			0x0
+#define B4_PMC			0x0	/* normal */
+
+#define B5_Tacs			0x0	/*  0clk */
+#define B5_Tcos			0x0	/*  0clk */
+#define B5_Tacc			0x7	/* 14clk */
+#define B5_Tcoh			0x0	/*  0clk */
+#define B5_Tah			0x0	/*  0clk */
+#define B5_Tacp			0x0
+#define B5_PMC			0x0	/* normal */
+
+#define B6_MT			0x3	/* SDRAM */
+#define B6_Trcd			0x1
+#define B6_SCAN			0x1	/* 9bit */
+
+#define B7_MT			0x3	/* SDRAM */
+#define B7_Trcd			0x1	/* 3clk */
+#define B7_SCAN			0x1	/* 9bit */
 
 /* REFRESH parameter */
-#define REFEN		 	0x1	/* Refresh enable */
-#define TREFMD		 	0x0	/* CBR(CAS before RAS)/Auto refresh */
-#define Trp		 	0x0	/* 2clk */
-#define Trc		 	0x3	/* 7clk */
-#define Tchr		 	0x2	/* 3clk */
-#define REFCNT		 	1113	/* period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) */
+#define REFEN			0x1	/* Refresh enable */
+#define TREFMD			0x0	/* CBR(CAS before RAS)/Auto refresh */
+#define Trp			0x0	/* 2clk */
+#define Trc			0x3	/* 7clk */
+#define Tchr			0x2	/* 3clk */
+#define REFCNT			1113	/* period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) */
 /**************************************/
 
 _TEXT_BASE:
diff --git a/board/snmc/qs850/u-boot.lds b/board/snmc/qs850/u-boot.lds
index ba6f38849f..2410d5f2c3 100644
--- a/board/snmc/qs850/u-boot.lds
+++ b/board/snmc/qs850/u-boot.lds
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)	}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)	}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)	}
   .rela.got      : { *(.rela.got)	}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/snmc/qs860t/flash.c b/board/snmc/qs860t/flash.c
index c84d08d628..aa2e85605a 100644
--- a/board/snmc/qs860t/flash.c
+++ b/board/snmc/qs860t/flash.c
@@ -79,8 +79,7 @@ unsigned long flash_init (void)
 	}
 
 	/* Only one bank */
-	if (CFG_MAX_FLASH_BANKS == 1)
-	{
+	if (CFG_MAX_FLASH_BANKS == 1) {
 		/* Setup offsets */
 		flash_get_offsets (FLASH_BASE1_PRELIM, &flash_info[0]);
 
@@ -98,15 +97,11 @@ unsigned long flash_init (void)
 #endif
 		size_b1 = 0 ;
 		flash_info[0].size = size_b0;
-	}
-	/* 2 banks */
-	else
-	{
+	} else {	/* 2 banks */
 		size_b1 = flash_get_size((volatile FLASH_WORD_SIZE *)FLASH_BASE1_PRELIM, &flash_info[1]);
 
 		/* Re-do sizing to get full correct info */
-		if (size_b1)
-		{
+		if (size_b1) {
 			mtdcr(ebccfga, pb0cr);
 			pbcr = mfdcr(ebccfgd);
 			mtdcr(ebccfga, pb0cr);
@@ -115,8 +110,7 @@ unsigned long flash_init (void)
 			mtdcr(ebccfgd, pbcr);
 		}
 
-		if (size_b0)
-		{
+		if (size_b0) {
 			mtdcr(ebccfga, pb1cr);
 			pbcr = mfdcr(ebccfgd);
 			mtdcr(ebccfga, pb1cr);
@@ -566,17 +560,17 @@ ulong flash_get_size (volatile FLASH_WORD_SIZE *addr, flash_info_t *info)
 		info->flash_id += FLASH_28F320J3A;
 		info->sector_count = 32;
 		info->size = 0x00400000;
-		break;				/* => 32 MBit  	*/
+		break;				/* => 32 MBit	*/
 	case (INTEL_ID_28F640J3A & FLASH_ID_MASK):
 		info->flash_id += FLASH_28F640J3A;
 		info->sector_count = 64;
 		info->size = 0x00800000;
-		break;				/* => 64 MBit  	*/
+		break;				/* => 64 MBit	*/
 	case (INTEL_ID_28F128J3A & FLASH_ID_MASK):
 		info->flash_id += FLASH_28F128J3A;
 		info->sector_count = 128;
 		info->size = 0x01000000;
-		break;				/* => 128 MBit  	*/
+		break;				/* => 128 MBit	*/
 
 	default:
 		/* FIXME*/
@@ -613,10 +607,11 @@ ulong flash_get_size (volatile FLASH_WORD_SIZE *addr, flash_info_t *info)
 /*-----------------------------------------------------------------------
  */
 
-int flash_erase (flash_info_t *info, int s_first, int s_last)
+int flash_erase (flash_info_t * info, int s_first, int s_last)
 {
 
-	volatile FLASH_WORD_SIZE *addr=(volatile FLASH_WORD_SIZE*)(info->start[0]);
+	volatile FLASH_WORD_SIZE *addr =
+		(volatile FLASH_WORD_SIZE *) (info->start[0]);
 	int flag, prot, sect, l_sect, barf;
 	ulong start, now, last;
 	int rcode = 0;
@@ -631,22 +626,21 @@ int flash_erase (flash_info_t *info, int s_first, int s_last)
 	}
 
 	if ((info->flash_id == FLASH_UNKNOWN) ||
-		((info->flash_id > FLASH_AMD_COMP) &&
-		( (info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL ) ) ){
+	    ((info->flash_id > FLASH_AMD_COMP) &&
+	     ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL))) {
 		printf ("Can't erase unknown flash type - aborted\n");
 		return 1;
 	}
 
 	prot = 0;
-	for (sect=s_first; sect<=s_last; ++sect) {
+	for (sect = s_first; sect <= s_last; ++sect) {
 		if (info->protect[sect]) {
 			prot++;
 		}
 	}
 
 	if (prot) {
-		printf ("- Warning: %d protected sectors will not be erased!\n",
-			prot);
+		printf ("- Warning: %d protected sectors will not be erased!\n", prot);
 	} else {
 		printf ("\n");
 	}
@@ -654,109 +648,112 @@ int flash_erase (flash_info_t *info, int s_first, int s_last)
 	l_sect = -1;
 
 	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts();
-    if(info->flash_id < FLASH_AMD_COMP) {
+	flag = disable_interrupts ();
+	if (info->flash_id < FLASH_AMD_COMP) {
 #ifndef CFG_FLASH_16BIT
-	addr[0x0555] = 0x00AA00AA;
-	addr[0x02AA] = 0x00550055;
-	addr[0x0555] = 0x00800080;
-	addr[0x0555] = 0x00AA00AA;
-	addr[0x02AA] = 0x00550055;
+		addr[0x0555] = 0x00AA00AA;
+		addr[0x02AA] = 0x00550055;
+		addr[0x0555] = 0x00800080;
+		addr[0x0555] = 0x00AA00AA;
+		addr[0x02AA] = 0x00550055;
 #else
-	addr[0x0555] = 0x00AA;
-	addr[0x02AA] = 0x0055;
-	addr[0x0555] = 0x0080;
-	addr[0x0555] = 0x00AA;
-	addr[0x02AA] = 0x0055;
+		addr[0x0555] = 0x00AA;
+		addr[0x02AA] = 0x0055;
+		addr[0x0555] = 0x0080;
+		addr[0x0555] = 0x00AA;
+		addr[0x02AA] = 0x0055;
 #endif
-	/* Start erase on unprotected sectors */
-	for (sect = s_first; sect<=s_last; sect++) {
-		if (info->protect[sect] == 0) {	/* not protected */
-			addr = (volatile FLASH_WORD_SIZE *)(info->start[sect]);
-			addr[0] = (0x00300030 & FLASH_ID_MASK);
-			l_sect = sect;
+		/* Start erase on unprotected sectors */
+		for (sect = s_first; sect <= s_last; sect++) {
+			if (info->protect[sect] == 0) {	/* not protected */
+				addr = (volatile FLASH_WORD_SIZE *) (info->start[sect]);
+				addr[0] = (0x00300030 & FLASH_ID_MASK);
+				l_sect = sect;
+			}
 		}
-	}
-
-	/* re-enable interrupts if necessary */
-	if (flag)
-		enable_interrupts();
 
-	/* wait at least 80us - let's wait 1 ms */
-	udelay (1000);
-
-	/*
-	 * We wait for the last triggered sector
-	 */
-	if (l_sect < 0)
-		goto DONE;
-
-	start = get_timer (0);
-	last  = start;
-	addr = (volatile FLASH_WORD_SIZE*)(info->start[l_sect]);
-	while ((addr[0] & (0x00800080&FLASH_ID_MASK)) !=
-		(0x00800080&FLASH_ID_MASK)  )
-	{
-		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
-			printf ("Timeout\n");
-			return 1;
-		}
-		/* show that we're waiting */
-		if ((now - last) > 1000) {	/* every second */
-			serial_putc ('.');
-			last = now;
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts ();
+
+		/* wait at least 80us - let's wait 1 ms */
+		udelay (1000);
+
+		/*
+		 * We wait for the last triggered sector
+		 */
+		if (l_sect < 0)
+			goto DONE;
+
+		start = get_timer (0);
+		last = start;
+		addr = (volatile FLASH_WORD_SIZE *) (info->start[l_sect]);
+		while ((addr[0] & (0x00800080 & FLASH_ID_MASK)) !=
+		       (0x00800080 & FLASH_ID_MASK)) {
+			if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) {
+				printf ("Timeout\n");
+				return 1;
+			}
+			/* show that we're waiting */
+			if ((now - last) > 1000) {	/* every second */
+				serial_putc ('.');
+				last = now;
+			}
 		}
-	}
 
-DONE:
-	/* reset to read mode */
-	addr = (volatile FLASH_WORD_SIZE *)info->start[0];
-	addr[0] = (0x00F000F0 & FLASH_ID_MASK);	/* reset bank */
-    } else {
+	      DONE:
+		/* reset to read mode */
+		addr = (volatile FLASH_WORD_SIZE *) info->start[0];
+		addr[0] = (0x00F000F0 & FLASH_ID_MASK);	/* reset bank */
+	} else {
 
 
-	for (sect = s_first; sect<=s_last; sect++) {
-		if (info->protect[sect] == 0) {	/* not protected */
-			barf = 0;
+		for (sect = s_first; sect <= s_last; sect++) {
+			if (info->protect[sect] == 0) {	/* not protected */
+				barf = 0;
 #ifndef CFG_FLASH_16BIT
-			addr = (vu_long*)(info->start[sect]);
-			addr[0] = 0x00200020;
-			addr[0] = 0x00D000D0;
-			while(!(addr[0] & 0x00800080));	/* wait for error or finish */
-			if( addr[0] & 0x003A003A) {	/* check for error */
-				barf = addr[0] & 0x003A0000;
-				if( barf ) {
-					barf >>=16;
-				} else {
-					barf = addr[0] & 0x0000003A;
+				addr = (vu_long *) (info->start[sect]);
+				addr[0] = 0x00200020;
+				addr[0] = 0x00D000D0;
+				while (!(addr[0] & 0x00800080));	/* wait for error or finish */
+				if (addr[0] & 0x003A003A) {	/* check for error */
+					barf = addr[0] & 0x003A0000;
+					if (barf) {
+						barf >>= 16;
+					} else {
+						barf = addr[0] & 0x0000003A;
+					}
 				}
-			}
 #else
-			addr = (vu_short*)(info->start[sect]);
-			addr[0] = 0x0020;
-			addr[0] = 0x00D0;
-			while(!(addr[0] & 0x0080));	/* wait for error or finish */
-			if( addr[0] & 0x003A)	/* check for error */
-				barf = addr[0] & 0x003A;
+				addr = (vu_short *) (info->start[sect]);
+				addr[0] = 0x0020;
+				addr[0] = 0x00D0;
+				while (!(addr[0] & 0x0080));	/* wait for error or finish */
+				if (addr[0] & 0x003A)	/* check for error */
+					barf = addr[0] & 0x003A;
 #endif
-			if(barf) {
-				printf("\nFlash error in sector at %lx\n",(unsigned long)addr);
-				if(barf & 0x0002) printf("Block locked, not erased.\n");
-				if((barf & 0x0030) == 0x0030)
-					printf("Command Sequence error.\n");
-				if((barf & 0x0030) == 0x0020)
-					printf("Block Erase error.\n");
-				if(barf & 0x0008) printf("Vpp Low error.\n");
-				rcode = 1;
-			} else printf(".");
-			l_sect = sect;
+				if (barf) {
+					printf ("\nFlash error in sector at %lx\n",
+						(unsigned long) addr);
+					if (barf & 0x0002)
+						printf ("Block locked, not erased.\n");
+					if ((barf & 0x0030) == 0x0030)
+						printf ("Command Sequence error.\n");
+					if ((barf & 0x0030) == 0x0020)
+						printf ("Block Erase error.\n");
+					if (barf & 0x0008)
+						printf ("Vpp Low error.\n");
+					rcode = 1;
+				} else
+					printf (".");
+				l_sect = sect;
+			}
+			addr = (volatile FLASH_WORD_SIZE *) info->start[0];
+			addr[0] = (0x00FF00FF & FLASH_ID_MASK);	/* reset bank */
+
 		}
-	addr = (volatile FLASH_WORD_SIZE *)info->start[0];
-	addr[0] = (0x00FF00FF & FLASH_ID_MASK);	/* reset bank */
 
 	}
-
-    }
 	printf (" done\n");
 	return rcode;
 }
@@ -1023,7 +1020,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data)
 			}
 		}
 	} else {
-		while(!(addr[0] & 0x00800080)) {  	/* wait for error or finish */
+		while(!(addr[0] & 0x00800080)) {	/* wait for error or finish */
 			if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
 				return (1);
 			}
@@ -1091,7 +1088,7 @@ static int write_short (flash_info_t *info, ulong dest, ushort data)
 
 	} else {
 		/* intel stuff */
-		while(!(addr[0] & 0x0080)){  	/* wait for error or finish */
+		while(!(addr[0] & 0x0080)){	/* wait for error or finish */
 			if (get_timer(start) > CFG_FLASH_WRITE_TOUT) return (1);
 		}
 
@@ -1105,7 +1102,7 @@ static int write_short (flash_info_t *info, ulong dest, ushort data)
 		}
 		*addr = 0x00B0;
 		*addr = 0x0070;
-		while(!(addr[0] & 0x0080)){  	/* wait for error or finish */
+		while(!(addr[0] & 0x0080)){	/* wait for error or finish */
 			if (get_timer(start) > CFG_FLASH_WRITE_TOUT) return (1);
 		}
 		*addr = 0x00FF;
@@ -1113,8 +1110,6 @@ static int write_short (flash_info_t *info, ulong dest, ushort data)
 	return (0);
 }
 
-
 #endif
 
-/*-----------------------------------------------------------------------
- */
+/*-----------------------------------------------------------------------*/
diff --git a/board/snmc/qs860t/u-boot.lds b/board/snmc/qs860t/u-boot.lds
index ba6f38849f..2410d5f2c3 100644
--- a/board/snmc/qs860t/u-boot.lds
+++ b/board/snmc/qs860t/u-boot.lds
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)	}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)	}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)	}
   .rela.got      : { *(.rela.got)	}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/socrates/Makefile b/board/socrates/Makefile
new file mode 100644
index 0000000000..6453f2480f
--- /dev/null
+++ b/board/socrates/Makefile
@@ -0,0 +1,53 @@
+#
+# (C) Copyright 2008
+# Sergei Poselenov,  Emcraft Systems, sposelenov@emcraft.com.
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+#
+
+COBJS	:= $(BOARD).o law.o tlb.o sdram.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+	rm -f $(OBJS) $(SOBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/socrates/config.mk b/board/socrates/config.mk
new file mode 100644
index 0000000000..1cf5d380df
--- /dev/null
+++ b/board/socrates/config.mk
@@ -0,0 +1,30 @@
+# Copyright 2004 Freescale Semiconductor.
+#
+# Modified by Sergei Poselenov
+# (C) Copyright 2008, Emcraft Systems.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# socrates board
+# default CCARBAR is at 0xff700000
+# assume U-Boot is less than 256k
+#
+TEXT_BASE = 0xfffc0000
diff --git a/board/socrates/law.c b/board/socrates/law.c
new file mode 100644
index 0000000000..5f4b8ca4f9
--- /dev/null
+++ b/board/socrates/law.c
@@ -0,0 +1,57 @@
+/*
+ * (C) Copyright 2008
+ * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
+ *
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ * 0x0000_0000	   0x7fff_ffff	   DDR			   2G
+ * 0x8000_0000	   0x9fff_ffff	   PCI1 MEM		   512M
+ * 0xc000_0000	   0xdfff_ffff	   RapidIO		   512M
+ * 0xe000_0000	   0xe000_ffff	   CCSR			   1M
+ * 0xe200_0000	   0xe2ff_ffff	   PCI1 IO		   16M
+ * 0xf800_0000	   0xf80f_ffff	   BCSR			   1M
+ * 0xfe00_0000	   0xffff_ffff	   FLASH (boot bank)	   32M
+ *
+ * Notes:
+ *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ *    If flash is 8M at default position (last 8M), no LAW needed.
+ */
+
+struct law_entry law_table[] = {
+	SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR),
+	SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
+	SET_LAW_ENTRY(3, CFG_LBC_FLASH_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC),
+	SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
+	SET_LAW_ENTRY(5, CFG_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/socrates/sdram.c b/board/socrates/sdram.c
new file mode 100644
index 0000000000..329eaccd5d
--- /dev/null
+++ b/board/socrates/sdram.c
@@ -0,0 +1,122 @@
+/*
+ * (C) Copyright 2008
+ * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <spd_sdram.h>
+
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*
+ * Autodetect onboard DDR SDRAM on 85xx platforms
+ *
+ * NOTE: Some of the hardcoded values are hardware dependant,
+ *       so this should be extended for other future boards
+ *       using this routine!
+ */
+long int sdram_setup(int casl)
+{
+	volatile ccsr_ddr_t *ddr = (void *)(CFG_MPC85xx_DDR_ADDR);
+
+	/*
+	 * Disable memory controller.
+	 */
+	ddr->cs0_config = 0;
+	ddr->sdram_cfg = 0;
+
+	ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
+	ddr->cs0_config = CFG_DDR_CS0_CONFIG;
+	ddr->timing_cfg_0 = CFG_DDR_TIMING_0;
+	ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
+	ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
+	ddr->sdram_mode = CFG_DDR_MODE;
+	ddr->sdram_interval = CFG_DDR_INTERVAL;
+	ddr->sdram_cfg_2 = CFG_DDR_CONFIG_2;
+	ddr->sdram_clk_cntl = CFG_DDR_CLK_CONTROL;
+
+	asm ("sync;isync;msync");
+	udelay(1000);
+
+	ddr->sdram_cfg = CFG_DDR_CONFIG;
+	asm ("sync; isync; msync");
+	udelay(1000);
+
+	if (get_ram_size(0, CFG_SDRAM_SIZE<<20) == CFG_SDRAM_SIZE<<20) {
+		/*
+		 * OK, size detected -> all done
+		 */
+		return CFG_SDRAM_SIZE<<20;
+	}
+
+	return 0;				/* nothing found !		*/
+}
+#endif
+
+long int initdram (int board_type)
+{
+	long dram_size = 0;
+#if defined(CONFIG_SPD_EEPROM)
+	dram_size = spd_sdram ();
+#else
+	dram_size = sdram_setup(CONFIG_DDR_DEFAULT_CL);
+#endif
+	return dram_size;
+}
+
+#if defined(CFG_DRAM_TEST)
+int testdram (void)
+{
+	uint *pstart = (uint *) CFG_MEMTEST_START;
+	uint *pend = (uint *) CFG_MEMTEST_END;
+	uint *p;
+
+	printf ("SDRAM test phase 1:\n");
+	for (p = pstart; p < pend; p++)
+		*p = 0xaaaaaaaa;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0xaaaaaaaa) {
+			printf ("SDRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	printf ("SDRAM test phase 2:\n");
+	for (p = pstart; p < pend; p++)
+		*p = 0x55555555;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0x55555555) {
+			printf ("SDRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	printf ("SDRAM test passed.\n");
+	return 0;
+}
+#endif
diff --git a/board/socrates/socrates.c b/board/socrates/socrates.c
new file mode 100644
index 0000000000..cb5899485a
--- /dev/null
+++ b/board/socrates/socrates.c
@@ -0,0 +1,211 @@
+/*
+ * (C) Copyright 2008
+ * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
+ *
+ * Copyright 2004 Freescale Semiconductor.
+ * (C) Copyright 2002,2003, Motorola Inc.
+ * Xianghua Xiao, (X.Xiao@motorola.com)
+ *
+ * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <ioports.h>
+#include <flash.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern flash_info_t flash_info[];	/* FLASH chips info */
+
+void local_bus_init (void);
+ulong flash_get_size (ulong base, int banknum);
+
+int checkboard (void)
+{
+	char *s = getenv("serial#");
+
+	puts("Board: Socrates");
+	if (s != NULL) {
+		puts(", serial# ");
+		puts(s);
+	}
+	putc('\n');
+
+#ifdef CONFIG_PCI
+	printf ("PCI1:  32 bit, %d MHz (compiled)\n",
+		CONFIG_SYS_CLK_FREQ / 1000000);
+#else
+	printf ("PCI1:  disabled\n");
+#endif
+
+	/*
+	 * Initialize local bus.
+	 */
+	local_bus_init ();
+
+	return 0;
+}
+
+int misc_init_r (void)
+{
+	volatile ccsr_lbc_t *memctl = (void *)(CFG_MPC85xx_LBC_ADDR);
+
+	/*
+	 * Adjust flash start and offset to detected values
+	 */
+	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
+	gd->bd->bi_flashoffset = 0;
+
+	/*
+	 * Check if boot FLASH isn't max size
+	 */
+	if (gd->bd->bi_flashsize < (0 - CFG_FLASH0)) {
+		memctl->or0 = gd->bd->bi_flashstart | (CFG_OR0_PRELIM & 0x00007fff);
+		memctl->br0 = gd->bd->bi_flashstart | (CFG_BR0_PRELIM & 0x00007fff);
+
+		/*
+		 * Re-check to get correct base address
+		 */
+		flash_get_size(gd->bd->bi_flashstart, CFG_MAX_FLASH_BANKS - 1);
+	}
+
+	/*
+	 * Check if only one FLASH bank is available
+	 */
+	if (gd->bd->bi_flashsize != CFG_MAX_FLASH_BANKS * (0 - CFG_FLASH0)) {
+		memctl->or1 = 0;
+		memctl->br1 = 0;
+
+		/*
+		 * Re-do flash protection upon new addresses
+		 */
+		flash_protect (FLAG_PROTECT_CLEAR,
+			       gd->bd->bi_flashstart, 0xffffffff,
+			       &flash_info[CFG_MAX_FLASH_BANKS - 1]);
+
+		/* Monitor protection ON by default */
+		flash_protect (FLAG_PROTECT_SET,
+			       CFG_MONITOR_BASE, CFG_MONITOR_BASE + monitor_flash_len - 1,
+			       &flash_info[CFG_MAX_FLASH_BANKS - 1]);
+
+		/* Environment protection ON by default */
+		flash_protect (FLAG_PROTECT_SET,
+			       CFG_ENV_ADDR,
+			       CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
+			       &flash_info[CFG_MAX_FLASH_BANKS - 1]);
+
+		/* Redundant environment protection ON by default */
+		flash_protect (FLAG_PROTECT_SET,
+			       CFG_ENV_ADDR_REDUND,
+			       CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1,
+			       &flash_info[CFG_MAX_FLASH_BANKS - 1]);
+	}
+
+	return 0;
+}
+
+/*
+ * Initialize Local Bus
+ */
+void local_bus_init (void)
+{
+
+	volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
+	volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR);
+
+	lbc->ltesr = 0xffffffff;	/* Clear LBC error interrupts */
+	lbc->lteir = 0xffffffff;	/* Enable LBC error interrupts */
+	ecm->eedr = 0xffffffff;		/* Clear ecm errors */
+	ecm->eeer = 0xffffffff;		/* Enable ecm errors */
+
+}
+
+#if defined(CONFIG_PCI)
+/*
+ * Initialize PCI Devices, report devices found.
+ */
+
+#ifndef CONFIG_PCI_PNP
+static struct pci_config_table pci_mpc85xxads_config_table[] = {
+	{PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+	 PCI_IDSEL_NUMBER, PCI_ANY_ID,
+	 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
+				     PCI_ENET0_MEMADDR,
+				     PCI_COMMAND_MEMORY |
+				     PCI_COMMAND_MASTER}},
+	{}
+};
+#endif
+
+
+static struct pci_controller hose = {
+#ifndef CONFIG_PCI_PNP
+	config_table:pci_mpc85xxads_config_table,
+#endif
+};
+
+#endif /* CONFIG_PCI */
+
+
+void pci_init_board (void)
+{
+#ifdef CONFIG_PCI
+	pci_mpc85xx_init (&hose);
+#endif /* CONFIG_PCI */
+}
+
+#ifdef CONFIG_BOARD_EARLY_INIT_R
+int board_early_init_r (void)
+{
+#ifdef CONFIG_PS2MULT
+	ps2mult_early_init();
+#endif /* CONFIG_PS2MULT */
+	return (0);
+}
+#endif /* CONFIG_BOARD_EARLY_INIT_R */
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+void
+ft_board_setup(void *blob, bd_t *bd)
+{
+	u32 val[4];
+	int rc;
+
+	ft_cpu_setup(blob, bd);
+
+	/* Fixup NOR mapping */
+	val[0] = 0;				/* chip select number */
+	val[1] = 0;				/* always 0 */
+	val[2] = gd->bd->bi_flashstart;
+	val[3] = gd->bd->bi_flashsize;
+
+	rc = fdt_find_and_setprop(blob, "/localbus", "ranges",
+				  val, sizeof(val), 1);
+	if (rc)
+		printf("Unable to update property NOR mapping, err=%s\n",
+		       fdt_strerror(rc));
+}
+#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
diff --git a/board/socrates/tlb.c b/board/socrates/tlb.c
new file mode 100644
index 0000000000..b80caea5e0
--- /dev/null
+++ b/board/socrates/tlb.c
@@ -0,0 +1,117 @@
+/*
+ * (C) Copyright 2008
+ * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
+ *
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+
+
+	/*
+	 * TLB 0, 1:	128M	Non-cacheable, guarded
+	 * 0xf8000000	128M	FLASH
+	 * Out of reset this entry is only 4K.
+	 */
+	SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 1, BOOKE_PAGESZ_64M, 1),
+	SET_TLB_ENTRY(1, CFG_FLASH_BASE + 0x4000000, CFG_FLASH_BASE + 0x4000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_64M, 1),
+
+	/*
+	 * TLB 2:	256M	Non-cacheable, guarded
+	 * 0x80000000	256M	PCI1 MEM First half
+	 */
+	SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 2, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * TLB 3:	256M	Non-cacheable, guarded
+	 * 0x90000000	256M	PCI1 MEM Second half
+	 */
+	SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS + 0x10000000, CFG_PCI1_MEM_PHYS + 0x10000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 3, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * TLB 4:	256M	Non-cacheable, guarded
+	 * 0xc0000000	256M	Rapid IO MEM First half
+	 */
+	SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE, CFG_RIO_MEM_BASE,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 4, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * TLB 5:	256M	Non-cacheable, guarded
+	 * 0xd0000000	256M	Rapid IO MEM Second half
+	 */
+	SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE + 0x10000000, CFG_RIO_MEM_BASE + 0x10000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 5, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * TLB 6:	64M	Non-cacheable, guarded
+	 * 0xe000_0000	1M	CCSRBAR
+	 * 0xe200_0000	16M	PCI1 IO
+	 */
+	SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 6, BOOKE_PAGESZ_64M, 1),
+
+	/*
+	 * TLB 7+8:	512M	DDR, cache disabled (needed for memory test)
+	 * 0x00000000  512M	DDR System memory
+	 * Without SPD EEPROM configured DDR, this must be setup manually.
+	 * Make sure the TLB count at the top of this table is correct.
+	 * Likely it needs to be increased by two for these entries.
+	 */
+	SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 7, BOOKE_PAGESZ_256M, 1),
+
+	SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE + 0x10000000, CFG_DDR_SDRAM_BASE + 0x10000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 8, BOOKE_PAGESZ_256M, 1),
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/socrates/u-boot.lds b/board/socrates/u-boot.lds
new file mode 100644
index 0000000000..8d2f65cccf
--- /dev/null
+++ b/board/socrates/u-boot.lds
@@ -0,0 +1,150 @@
+/*
+ * (C) Copyright 2008
+ * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
+ *
+ * (C) Copyright 2002,2003, Motorola,Inc.
+ * Xianghua Xiao, X.Xiao@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  .bootpg 0xFFFFF000 :
+  {
+    cpu/mpc85xx/start.o (.bootpg)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash		 : { *(.hash)		}
+  .dynsym	 : { *(.dynsym)		}
+  .dynstr	 : { *(.dynstr)		}
+  .rel.text	 : { *(.rel.text)		}
+  .rela.text	 : { *(.rela.text)	}
+  .rel.data	 : { *(.rel.data)		}
+  .rela.data	 : { *(.rela.data)	}
+  .rel.rodata	 : { *(.rel.rodata)	}
+  .rela.rodata	 : { *(.rela.rodata)	}
+  .rel.got	 : { *(.rel.got)		}
+  .rela.got	 : { *(.rela.got)		}
+  .rel.ctors	 : { *(.rel.ctors)	}
+  .rela.ctors	 : { *(.rela.ctors)	}
+  .rel.dtors	 : { *(.rel.dtors)	}
+  .rela.dtors	 : { *(.rela.dtors)	}
+  .rel.bss	 : { *(.rel.bss)		}
+  .rela.bss	 : { *(.rela.bss)		}
+  .rel.plt	 : { *(.rel.plt)		}
+  .rela.plt	 : { *(.rela.plt)		}
+  .init		 : { *(.init)	}
+  .plt : { *(.plt) }
+  .text	     :
+  {
+    cpu/mpc85xx/start.o (.text)
+    cpu/mpc85xx/traps.o (.text)
+    cpu/mpc85xx/interrupts.o (.text)
+    cpu/mpc85xx/cpu_init.o (.text)
+    cpu/mpc85xx/cpu.o (.text)
+    cpu/mpc85xx/speed.o (.text)
+    cpu/mpc85xx/pci.o (.text)
+    common/dlmalloc.o (.text)
+    lib_generic/crc32.o (.text)
+    lib_ppc/extable.o (.text)
+    lib_generic/zlib.o (.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+   }
+    _etext = .;
+    PROVIDE (etext = .);
+    .rodata    :
+   {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini	     : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data	   :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)	     :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/spc1920/u-boot.lds b/board/spc1920/u-boot.lds
index 7ab29ef0f8..8c46e4677f 100644
--- a/board/spc1920/u-boot.lds
+++ b/board/spc1920/u-boot.lds
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)	}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)	}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)	}
   .rela.got      : { *(.rela.got)	}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/spd8xx/u-boot.lds b/board/spd8xx/u-boot.lds
index 16e2cd02ca..13b29084f1 100644
--- a/board/spd8xx/u-boot.lds
+++ b/board/spd8xx/u-boot.lds
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/spd8xx/u-boot.lds.debug b/board/spd8xx/u-boot.lds.debug
index 96c4e22c24..fd2245f57b 100644
--- a/board/spd8xx/u-boot.lds.debug
+++ b/board/spd8xx/u-boot.lds.debug
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/stxgp3/u-boot.lds b/board/stxgp3/u-boot.lds
index 8c590b9b66..9cc499747f 100644
--- a/board/stxgp3/u-boot.lds
+++ b/board/stxgp3/u-boot.lds
@@ -48,11 +48,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/stxssa/u-boot.lds b/board/stxssa/u-boot.lds
index 9381688268..b0a9d683da 100644
--- a/board/stxssa/u-boot.lds
+++ b/board/stxssa/u-boot.lds
@@ -48,11 +48,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/stxxtc/u-boot.lds b/board/stxxtc/u-boot.lds
index ea39cd9121..f560189c0b 100644
--- a/board/stxxtc/u-boot.lds
+++ b/board/stxxtc/u-boot.lds
@@ -28,15 +28,15 @@ SECTIONS
 {
   /* Read-only sections, merged into text segment: */
   . = + SIZEOF_HEADERS;
-  .interp		: { *(.interp)		}
+  .interp	: { *(.interp)		}
   .hash         : { *(.hash)		}
   .dynsym       : { *(.dynsym)		}
   .dynstr       : { *(.dynstr)		}
   .rel.text     : { *(.rel.text)	}
-  .rela.text    : { *(.rela.text) 	}
+  .rela.text    : { *(.rela.text)	}
   .rel.data     : { *(.rel.data)	}
-  .rela.data    : { *(.rela.data) 	}
-  .rel.rodata   : { *(.rel.rodata) 	}
+  .rela.data    : { *(.rela.data)	}
+  .rel.rodata   : { *(.rel.rodata)	}
   .rela.rodata  : { *(.rela.rodata)	}
   .rel.got      : { *(.rel.got)		}
   .rela.got     : { *(.rela.got)	}
@@ -49,8 +49,8 @@ SECTIONS
   .rel.plt      : { *(.rel.plt)		}
   .rela.plt     : { *(.rela.plt)	}
   .init         : { *(.init)		}
-  .plt			: { *(.plt) 		}
-  .text      	:
+  .plt		: { *(.plt)		}
+  .text	:
   {
     cpu/mpc8xx/start.o		(.text)
     cpu/mpc8xx/traps.o		(.text)
diff --git a/board/stxxtc/u-boot.lds.debug b/board/stxxtc/u-boot.lds.debug
index 80bcbfcb90..5bf1a66286 100644
--- a/board/stxxtc/u-boot.lds.debug
+++ b/board/stxxtc/u-boot.lds.debug
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/svm_sc8xx/u-boot.lds b/board/svm_sc8xx/u-boot.lds
index 35267dcdea..14ff179879 100644
--- a/board/svm_sc8xx/u-boot.lds
+++ b/board/svm_sc8xx/u-boot.lds
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)	}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)	}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)	}
   .rela.got      : { *(.rela.got)	}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/svm_sc8xx/u-boot.lds.debug b/board/svm_sc8xx/u-boot.lds.debug
index 5cedcb13e0..0cd053a8bb 100644
--- a/board/svm_sc8xx/u-boot.lds.debug
+++ b/board/svm_sc8xx/u-boot.lds.debug
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/total5200/total5200.c b/board/total5200/total5200.c
index f32dadf5a2..c8d4c67102 100644
--- a/board/total5200/total5200.c
+++ b/board/total5200/total5200.c
@@ -118,7 +118,7 @@ void init_ide_reset (void)
 {
 	debug ("init_ide_reset\n");
 
-    	/* Configure IRDA_1 (PSC6_3) as GPIO output for ATA reset */
+	/* Configure IRDA_1 (PSC6_3) as GPIO output for ATA reset */
 	*(vu_long *) MPC5XXX_GPIO_ENABLE |= GPIO_IRDA_1;
 	*(vu_long *) MPC5XXX_GPIO_DIR    |= GPIO_IRDA_1;
 }
diff --git a/board/tqm5200/cmd_stk52xx.c b/board/tqm5200/cmd_stk52xx.c
index 27a6c4163d..7472ca9e97 100644
--- a/board/tqm5200/cmd_stk52xx.c
+++ b/board/tqm5200/cmd_stk52xx.c
@@ -46,7 +46,7 @@
 #define SM501_POWER_MODE0_GATE		0x00000040UL
 #define SM501_POWER_MODE1_GATE		0x00000048UL
 #define POWER_MODE_GATE_GPIO_PWM_I2C	0x00000040UL
-#define SM501_GPIO_DATA_LOW 		0x00010000UL
+#define SM501_GPIO_DATA_LOW		0x00010000UL
 #define SM501_GPIO_DATA_HIGH		0x00010004UL
 #define SM501_GPIO_DATA_DIR_LOW		0x00010008UL
 #define SM501_GPIO_DATA_DIR_HIGH	0x0001000CUL
@@ -586,7 +586,7 @@ int do_led(char *argv[])
 	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
 	struct mpc5xxx_gpt_0_7 *gpt = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT;
 
-	switch 	(simple_strtoul(argv[2], NULL, 10)) {
+	switch	(simple_strtoul(argv[2], NULL, 10)) {
 
 	case 0:
 		if (strcmp (argv[3], "on") == 0) {
@@ -1000,7 +1000,7 @@ int do_rs232(char *argv[])
 	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
 	struct mpc5xxx_psc *psc1 = (struct mpc5xxx_psc *)MPC5XXX_PSC1;
 
-	switch 	(simple_strtoul(argv[2], NULL, 10)) {
+	switch	(simple_strtoul(argv[2], NULL, 10)) {
 
 	case 1:
 		/* check RTS <-> CTS loop */
diff --git a/board/tqm8260/tqm8260.c b/board/tqm8260/tqm8260.c
index 029863b7d9..736c410ede 100644
--- a/board/tqm8260/tqm8260.c
+++ b/board/tqm8260/tqm8260.c
@@ -304,7 +304,7 @@ long int initdram (int board_type)
     ulong start =  memctl->memc_ ## brX & 0xFFFF8000;	\
     ulong sizem = ~memctl->memc_ ## orX | 0x00007FFF;	\
     printf ("\n"					\
-    	    #brX " 0x%08x  " #orX " 0x%08x "		\
+	    #brX " 0x%08x  " #orX " 0x%08x "		\
 	    "==> 0x%08lx ... 0x%08lx = %ld MB\n",	\
 	memctl->memc_ ## brX, memctl->memc_ ## orX,	\
 	start, start+sizem, (sizem+1)>>20);		\
diff --git a/board/tqm834x/pci.c b/board/tqm834x/pci.c
index d896f17aad..e3d0309d90 100644
--- a/board/tqm834x/pci.c
+++ b/board/tqm834x/pci.c
@@ -37,7 +37,7 @@
 static struct pci_config_table pci_tqm834x_config_table[] = {
 	{PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
 	 PCI_IDSEL_NUMBER, PCI_ANY_ID,
- 	 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
+	 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
 				     PCI_ENET0_MEMADDR,
 				     PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
 		}
diff --git a/board/tqm8xx/u-boot.lds b/board/tqm8xx/u-boot.lds
index 7ab29ef0f8..8c46e4677f 100644
--- a/board/tqm8xx/u-boot.lds
+++ b/board/tqm8xx/u-boot.lds
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)	}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)	}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)	}
   .rela.got      : { *(.rela.got)	}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/tqm8xx/u-boot.lds.debug b/board/tqm8xx/u-boot.lds.debug
index 753411fcbf..c33581d250 100644
--- a/board/tqm8xx/u-boot.lds.debug
+++ b/board/tqm8xx/u-boot.lds.debug
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/trab/lowlevel_init.S b/board/trab/lowlevel_init.S
index 128ae7e4aa..bc7142abe3 100644
--- a/board/trab/lowlevel_init.S
+++ b/board/trab/lowlevel_init.S
@@ -128,7 +128,7 @@
 #define TREFMD	0x0	/* CBR(CAS before RAS)/auto refresh */
 #define Trp	0x0	/* 2 clk */
 #define Trc	0x3	/* 7 clk */
-#define Tchr	0x2 	/* 3 clk */
+#define Tchr	0x2	/* 3 clk */
 
 #ifdef CONFIG_TRAB_50MHZ
 #define REFCNT	1269	/* period=15.6 us, HCLK=50Mhz, (2048+1-15.6*50) */
diff --git a/board/trab/memory.c b/board/trab/memory.c
index 58bd99500a..8614be7bad 100644
--- a/board/trab/memory.c
+++ b/board/trab/memory.c
@@ -282,7 +282,7 @@ static int memory_post_addrline(ulong *testaddr, ulong *base, ulong size)
 #endif
 			if(readback == *testaddr) {
 				printf ("Memory (address line) error at %08lx<->%08lx, "
-				  	"XOR value %08lx !\n",
+					"XOR value %08lx !\n",
 					(ulong)testaddr, (ulong)target,
 					xor);
 				ret = -1;
diff --git a/board/trab/trab.c b/board/trab/trab.c
index d8a726b226..b869023ea7 100644
--- a/board/trab/trab.c
+++ b/board/trab/trab.c
@@ -89,7 +89,7 @@ int board_init ()
 	gpio->PBCON = 0xaaaaaaaa;
 	gpio->PBUP  = 0xffff;
 	/* INPUT nCTS0 nRTS0 TXD[1] TXD[0] RXD[1] RXD[0]	*/
-	/*  00,    10,      10,      10,      10,      10,      10 	*/
+	/*  00,    10,      10,      10,      10,      10,      10	*/
 	gpio->PFCON = (2<<0) | (2<<2) | (2<<4) | (2<<6) | (2<<8) | (2<<10);
 #ifdef CONFIG_HWFLOW
 	/* do not pull up RXD0, RXD1, TXD0, TXD1, CTS0, RTS0 */
@@ -130,7 +130,7 @@ int board_init ()
 
 #ifdef CONFIG_DRIVER_S3C24X0_I2C
 	/* Configure I/O ports PG5 und PG6 for I2C */
- 	gpio->PGCON = (gpio->PGCON & 0x003c00) | 0x003c00;
+	gpio->PGCON = (gpio->PGCON & 0x003c00) | 0x003c00;
 #endif /* CONFIG_DRIVER_S3C24X0_I2C */
 
 	return 0;
@@ -321,9 +321,9 @@ int do_kbd (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 }
 
 U_BOOT_CMD(
- 	kbd,	1,	1,	do_kbd,
- 	"kbd     - read keyboard status\n",
- 	NULL
+	kbd,	1,	1,	do_kbd,
+	"kbd     - read keyboard status\n",
+	NULL
 );
 
 #ifdef CONFIG_MODEM_SUPPORT
@@ -356,7 +356,7 @@ static void spi_init(void)
 	int i;
 
 	/* Configure I/O ports. */
- 	gpio->PDCON = (gpio->PDCON & 0xF3FFFF) | 0x040000;
+	gpio->PDCON = (gpio->PDCON & 0xF3FFFF) | 0x040000;
 	gpio->PGCON = (gpio->PGCON & 0x0F3FFF) | 0x008000;
 	gpio->PGCON = (gpio->PGCON & 0x0CFFFF) | 0x020000;
 	gpio->PGCON = (gpio->PGCON & 0x03FFFF) | 0x080000;
diff --git a/board/trab/tsc2000.h b/board/trab/tsc2000.h
index aac9c0c77e..af1b644587 100644
--- a/board/trab/tsc2000.h
+++ b/board/trab/tsc2000.h
@@ -29,45 +29,45 @@
 #define _TSC2000_H_
 
 /* temperature channel multiplexer definitions */
-#define CON_MUX0         	(gpio->PCCON = (gpio->PCCON & 0x0FFFFFCFF) | 0x00000100)
-#define CLR_MUX0         	(gpio->PCDAT &= 0x0FFEF)
-#define SET_MUX0         	(gpio->PCDAT |= 0x00010)
+#define CON_MUX0		(gpio->PCCON = (gpio->PCCON & 0x0FFFFFCFF) | 0x00000100)
+#define CLR_MUX0		(gpio->PCDAT &= 0x0FFEF)
+#define SET_MUX0		(gpio->PCDAT |= 0x00010)
 
-#define CON_MUX1         	(gpio->PCCON = (gpio->PCCON & 0x0FFFFF3FF) | 0x00000400)
-#define CLR_MUX1         	(gpio->PCDAT &= 0x0FFDF)
-#define SET_MUX1         	(gpio->PCDAT |= 0x00020)
+#define CON_MUX1		(gpio->PCCON = (gpio->PCCON & 0x0FFFFF3FF) | 0x00000400)
+#define CLR_MUX1		(gpio->PCDAT &= 0x0FFDF)
+#define SET_MUX1		(gpio->PCDAT |= 0x00020)
 
-#define CON_MUX1_ENABLE  	(gpio->PCCON = (gpio->PCCON & 0x0FFFFCFFF) | 0x00001000)
-#define CLR_MUX1_ENABLE  	(gpio->PCDAT |= 0x00040)
-#define SET_MUX1_ENABLE  	(gpio->PCDAT &= 0x0FFBF)
+#define CON_MUX1_ENABLE		(gpio->PCCON = (gpio->PCCON & 0x0FFFFCFFF) | 0x00001000)
+#define CLR_MUX1_ENABLE		(gpio->PCDAT |= 0x00040)
+#define SET_MUX1_ENABLE		(gpio->PCDAT &= 0x0FFBF)
 
-#define CON_MUX2_ENABLE  	(gpio->PCCON = (gpio->PCCON & 0x0FFFF3FFF) | 0x00004000)
-#define CLR_MUX2_ENABLE  	(gpio->PCDAT |= 0x00080)
-#define SET_MUX2_ENABLE  	(gpio->PCDAT &= 0x0FF7F)
+#define CON_MUX2_ENABLE		(gpio->PCCON = (gpio->PCCON & 0x0FFFF3FFF) | 0x00004000)
+#define CLR_MUX2_ENABLE		(gpio->PCDAT |= 0x00080)
+#define SET_MUX2_ENABLE		(gpio->PCDAT &= 0x0FF7F)
 
-#define CON_MUX3_ENABLE  	(gpio->PCCON = (gpio->PCCON & 0x0FFFCFFFF) | 0x00010000)
-#define CLR_MUX3_ENABLE  	(gpio->PCDAT |= 0x00100)
-#define SET_MUX3_ENABLE  	(gpio->PCDAT &= 0x0FEFF)
+#define CON_MUX3_ENABLE		(gpio->PCCON = (gpio->PCCON & 0x0FFFCFFFF) | 0x00010000)
+#define CLR_MUX3_ENABLE		(gpio->PCDAT |= 0x00100)
+#define SET_MUX3_ENABLE		(gpio->PCDAT &= 0x0FEFF)
 
-#define CON_MUX4_ENABLE  	(gpio->PCCON = (gpio->PCCON & 0x0FFF3FFFF) | 0x00040000)
-#define CLR_MUX4_ENABLE  	(gpio->PCDAT |= 0x00200)
-#define SET_MUX4_ENABLE  	(gpio->PCDAT &= 0x0FDFF)
+#define CON_MUX4_ENABLE		(gpio->PCCON = (gpio->PCCON & 0x0FFF3FFFF) | 0x00040000)
+#define CLR_MUX4_ENABLE		(gpio->PCDAT |= 0x00200)
+#define SET_MUX4_ENABLE		(gpio->PCDAT &= 0x0FDFF)
 
-#define CON_SEL_TEMP_V_0 	(gpio->PCCON = (gpio->PCCON & 0x0FFCFFFFF) | 0x00100000)
-#define CLR_SEL_TEMP_V_0 	(gpio->PCDAT &= 0x0FBFF)
-#define SET_SEL_TEMP_V_0 	(gpio->PCDAT |= 0x00400)
+#define CON_SEL_TEMP_V_0	(gpio->PCCON = (gpio->PCCON & 0x0FFCFFFFF) | 0x00100000)
+#define CLR_SEL_TEMP_V_0	(gpio->PCDAT &= 0x0FBFF)
+#define SET_SEL_TEMP_V_0	(gpio->PCDAT |= 0x00400)
 
-#define CON_SEL_TEMP_V_1 	(gpio->PCCON = (gpio->PCCON & 0x0FF3FFFFF) | 0x00400000)
-#define CLR_SEL_TEMP_V_1 	(gpio->PCDAT &= 0x0F7FF)
-#define SET_SEL_TEMP_V_1 	(gpio->PCDAT |= 0x00800)
+#define CON_SEL_TEMP_V_1	(gpio->PCCON = (gpio->PCCON & 0x0FF3FFFFF) | 0x00400000)
+#define CLR_SEL_TEMP_V_1	(gpio->PCDAT &= 0x0F7FF)
+#define SET_SEL_TEMP_V_1	(gpio->PCDAT |= 0x00800)
 
-#define CON_SEL_TEMP_V_2 	(gpio->PCCON = (gpio->PCCON & 0x0FCFFFFFF) | 0x01000000)
-#define CLR_SEL_TEMP_V_2 	(gpio->PCDAT &= 0x0EFFF)
-#define SET_SEL_TEMP_V_2 	(gpio->PCDAT |= 0x01000)
+#define CON_SEL_TEMP_V_2	(gpio->PCCON = (gpio->PCCON & 0x0FCFFFFFF) | 0x01000000)
+#define CLR_SEL_TEMP_V_2	(gpio->PCDAT &= 0x0EFFF)
+#define SET_SEL_TEMP_V_2	(gpio->PCDAT |= 0x01000)
 
-#define CON_SEL_TEMP_V_3 	(gpio->PCCON = (gpio->PCCON & 0x0F3FFFFFF) | 0x04000000)
-#define CLR_SEL_TEMP_V_3 	(gpio->PCDAT &= 0x0DFFF)
-#define SET_SEL_TEMP_V_3 	(gpio->PCDAT |= 0x02000)
+#define CON_SEL_TEMP_V_3	(gpio->PCCON = (gpio->PCCON & 0x0F3FFFFFF) | 0x04000000)
+#define CLR_SEL_TEMP_V_3	(gpio->PCDAT &= 0x0DFFF)
+#define SET_SEL_TEMP_V_3	(gpio->PCDAT |= 0x02000)
 
 /* TSC2000 register definition */
 #define TSC2000_REG_X		((0 << 11) | (0 << 5))
@@ -89,21 +89,21 @@
 #define TSC2000_REG_CONFIG	((1 << 11) | (5 << 5))
 
 /* bit definition of TSC2000 ADC register */
-#define TC_PSM          (1 << 15)
-#define TC_STS          (1 << 14)
-#define TC_AD3          (1 << 13)
-#define TC_AD2          (1 << 12)
-#define TC_AD1          (1 << 11)
-#define TC_AD0          (1 << 10)
-#define TC_RS1          (1 << 9)
-#define TC_RS0          (1 << 8)
-#define TC_AV1          (1 << 7)
-#define TC_AV0          (1 << 6)
-#define TC_CL1          (1 << 5)
-#define TC_CL0          (1 << 4)
-#define TC_PV2          (1 << 3)
-#define TC_PV1          (1 << 2)
-#define TC_PV0          (1 << 1)
+#define TC_PSM			(1 << 15)
+#define TC_STS			(1 << 14)
+#define TC_AD3			(1 << 13)
+#define TC_AD2			(1 << 12)
+#define TC_AD1			(1 << 11)
+#define TC_AD0			(1 << 10)
+#define TC_RS1			(1 << 9)
+#define TC_RS0			(1 << 8)
+#define TC_AV1			(1 << 7)
+#define TC_AV0			(1 << 6)
+#define TC_CL1			(1 << 5)
+#define TC_CL0			(1 << 4)
+#define TC_PV2			(1 << 3)
+#define TC_PV1			(1 << 2)
+#define TC_PV0			(1 << 1)
 
 /* default value for TSC2000 ADC register for use with touch functions */
 #define DEFAULT_ADC		(TC_PV1 | TC_AV0 | TC_AV1 | TC_RS0)
@@ -111,8 +111,7 @@
 #define TSC2000_DELAY_BASE	500
 #define TSC2000_NO_SENSOR	-0x10000
 
-#define ERROR_BATTERY   220     /* must be adjusted, if R68 is changed on
-				 * TRAB */
+#define ERROR_BATTERY		220	/* must be adjusted, if R68 is changed on TRAB */
 
 void tsc2000_write(unsigned short, unsigned short);
 unsigned short tsc2000_read (unsigned short);
diff --git a/board/trab/vfd.c b/board/trab/vfd.c
index b6798fdce7..eb506f39b6 100644
--- a/board/trab/vfd.c
+++ b/board/trab/vfd.c
@@ -104,7 +104,7 @@ void init_grid_ctrl(void)
 			bit = grid_cycle * 256  * 4 +
 			     (grid_cycle + 200) * 4 +
 			     frame_buf_offs + display;
- 			/* wrap arround if offset (see manual S3C2400) */
+			/* wrap arround if offset (see manual S3C2400) */
 			if (bit>=FRAME_BUF_SIZE*8)
 				bit = bit - (FRAME_BUF_SIZE * 8);
 			adr = gd->fb_base + (bit/32) * 4 + (3 - (bit%32) / 8);
@@ -117,7 +117,7 @@ void init_grid_ctrl(void)
 			if(grid_cycle<55)
 				bit = grid_cycle*256*4+(grid_cycle+201)*4+frame_buf_offs+display;
 			else
-				bit = grid_cycle*256*4+200*4+frame_buf_offs+display-4; 	/* grid nr. 0 */
+				bit = grid_cycle*256*4+200*4+frame_buf_offs+display-4;	/* grid nr. 0 */
 			/* wrap arround if offset (see manual S3C2400) */
 			if (bit>=FRAME_BUF_SIZE*8)
 				bit = bit-(FRAME_BUF_SIZE*8);
@@ -190,7 +190,7 @@ void create_vfd_table(void)
 			    /* Display 0 red pixels */
 			    vfd_table[x][y][1][display][0] =
 				(x==0) ? y*16+512+display
-			    	       : (x%4)*4+y*16+((x-1)/2)*1024+512+display;
+				       : (x%4)*4+y*16+((x-1)/2)*1024+512+display;
 		    }
 		}
 	    }
@@ -488,7 +488,7 @@ int drv_vfd_init(void)
 	lcd->LCDCON1 = 0x00000000;
 	/* frame buffer startadr */
 	lcd->LCDSADDR1 = gd->fb_base >> 1;
- 	/* frame buffer endadr */
+	/* frame buffer endadr */
 	lcd->LCDSADDR2 = (gd->fb_base + FRAME_BUF_SIZE) >> 1;
 	lcd->LCDSADDR3 = ((256/4));
 	lcd->LCDCON2 = 0x000DC000;
diff --git a/board/uc100/u-boot.lds b/board/uc100/u-boot.lds
index 2554abc40c..db29342491 100644
--- a/board/uc100/u-boot.lds
+++ b/board/uc100/u-boot.lds
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)	}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)	}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)	}
   .rela.got      : { *(.rela.got)	}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/uc100/u-boot.lds.debug b/board/uc100/u-boot.lds.debug
index 5aede106f2..25702a543c 100644
--- a/board/uc100/u-boot.lds.debug
+++ b/board/uc100/u-boot.lds.debug
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/uc100/uc100.c b/board/uc100/uc100.c
index 4f2cff624f..a5dd95d78e 100644
--- a/board/uc100/uc100.c
+++ b/board/uc100/uc100.c
@@ -188,7 +188,7 @@ long int initdram (int board_type)
 	memctl->memc_mptpr = 0x0200; /* Divide by 32 WV */
 
 	memctl->memc_mamr = CFG_MAMR_VAL & 0xFF7FFFFF; /* Bit 8 := "0" Kein Refresh WV */
-   	memctl->memc_mbmr = CFG_MBMR_VAL;
+	memctl->memc_mbmr = CFG_MBMR_VAL;
 
 	/*---------------------------------------------------------------------*/
 	/* Initialize the Memory Controller registers, MPTPR, Chip Select 1    */
diff --git a/board/utx8245/flash.c b/board/utx8245/flash.c
index 3271827081..199f619a82 100644
--- a/board/utx8245/flash.c
+++ b/board/utx8245/flash.c
@@ -46,7 +46,7 @@
 #endif
 
 #define	FLASH_BANK_SIZE	((uint)(16 * 1024 * 1024))	/* max 16Mbyte */
-#define	MAIN_SECT_SIZE 	0x10000
+#define	MAIN_SECT_SIZE	0x10000
 #define	SECT_SIZE_32KB	0x8000
 #define	SECT_SIZE_8KB	0x2000
 
diff --git a/board/v37/flash.c b/board/v37/flash.c
index 6a319721b2..d845f652f3 100644
--- a/board/v37/flash.c
+++ b/board/v37/flash.c
@@ -31,7 +31,7 @@
  * are not tested.
  *
  * (?) Does an RPXLite board which
- * 	does not use AM29LV800 flash memory exist ?
+ *	does not use AM29LV800 flash memory exist ?
  *	I don't know...
  */
 
diff --git a/board/v37/u-boot.lds b/board/v37/u-boot.lds
index 8253a25806..7bcf061555 100644
--- a/board/v37/u-boot.lds
+++ b/board/v37/u-boot.lds
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)	}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)	}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)	}
   .rela.got      : { *(.rela.got)	}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/v37/v37.c b/board/v37/v37.c
index 1ef879d5f1..2e47573024 100644
--- a/board/v37/v37.c
+++ b/board/v37/v37.c
@@ -38,8 +38,8 @@ static long int dram_size (void);
 
 /* ------------------------------------------------------------------------- */
 
-#define MBYTE 		(1024*1024)
-#define DRAM_DELAY  	0x00000379  /* DRAM delay count */
+#define MBYTE		(1024*1024)
+#define DRAM_DELAY	0x00000379  /* DRAM delay count */
 #define	_NOT_USED_	0xFFFFCC25
 
 const uint sdram_table[] =
diff --git a/board/versatile/flash.c b/board/versatile/flash.c
index 71533719f7..ca77c8a29e 100644
--- a/board/versatile/flash.c
+++ b/board/versatile/flash.c
@@ -92,7 +92,7 @@ static void flash_vpp(int on)
 	if (on)
 	    tmp |= VERSATILE_FLASHPROG_FLVPPEN;
 	else
-    	    tmp &= ~VERSATILE_FLASHPROG_FLVPPEN;
+	    tmp &= ~VERSATILE_FLASHPROG_FLVPPEN;
 
 	*(unsigned int *)(VERSATILE_FLASHCTRL) = tmp;
 }
diff --git a/board/versatile/versatile.c b/board/versatile/versatile.c
index 9d1a25ec8a..3b9b0207a3 100644
--- a/board/versatile/versatile.c
+++ b/board/versatile/versatile.c
@@ -104,7 +104,7 @@ void flash__init (void)
 /*************************************************************
  Routine:ether__init
  Description: take the Ethernet controller out of reset and wait
-	  		   for the EEPROM load to complete.
+			   for the EEPROM load to complete.
 *************************************************************/
 void ether__init (void)
 {
diff --git a/board/voiceblue/setup.S b/board/voiceblue/setup.S
index 78cd2b6bfe..cc50e8c395 100644
--- a/board/voiceblue/setup.S
+++ b/board/voiceblue/setup.S
@@ -273,7 +273,7 @@ ulocking:
 	mov	r0, #0x4000
 sdelay:
 	subs	r0, r0, #0x1
-	bne 	sdelay
+	bne	sdelay
 
 	/* back to arch calling code */
 	mov	pc, lr
diff --git a/board/w7o/post1.S b/board/w7o/post1.S
index 21d206e7cf..a6f46c8746 100644
--- a/board/w7o/post1.S
+++ b/board/w7o/post1.S
@@ -62,7 +62,7 @@
  * Switch to .data section.
  */
 	.section ".data"
-err_str: 	.asciz "*** POST ERROR   = "
+err_str:	.asciz "*** POST ERROR   = "
 warn_str:	.asciz "*** POST WARNING = "
 end_str:  .asciz "\r\n"
 
@@ -93,7 +93,7 @@ test_led:
 	stw	r0, +16(r1)		/* Save link register */
 	stw	r4, +8(r1)		/* save R4 */
 
-	WATCHDOG_RESET        		/* Reset the watchdog */
+	WATCHDOG_RESET			/* Reset the watchdog */
 
 	addi    r3, 0, ERR_FF		/* first test value is ffff */
 	addi	r4, r3, 0		/* save copy of pattern */
@@ -155,7 +155,7 @@ l2_loop:
 	addi	r31, r3, 0		/* save original size */
 
 	/* now kick the dog and test the mem */
-	WATCHDOG_RESET        		/* Reset the watchdog */
+	WATCHDOG_RESET			/* Reset the watchdog */
 	bl	Data_Buster		/* test crossed/shorted data lines */
 	addi	r3, r30, 0		/* get log2(memsize) */
 	addi	r4, r31, 0		/* get memsize */
@@ -257,7 +257,7 @@ clr_loop:
 	addi	r28, r28, 4		/* Increment to next word */
 	andi.	r27, r28, 0xffff	/* check for 2^16 loops */
 	bne	clr_skip		/* if not there, then skip */
-	WATCHDOG_RESET   		/* kick the dog every now and then */
+	WATCHDOG_RESET			/* kick the dog every now and then */
 clr_skip:
 	bdnz	clr_loop		/* Round and round... */
 
@@ -272,7 +272,7 @@ outside:
 	 * thus the sequence 0,1,2,4,8,..,2^(n-1)
 	 * setting the bit is done with the following shift functions.
 	 */
-	WATCHDOG_RESET   		/* Reset the watchdog */
+	WATCHDOG_RESET			/* Reset the watchdog */
 
 	addi	r31, 0, 1		/* r31 = 1 */
 	slw	r28, r31, r30		/* set bit coresponding to loop cnt */
@@ -301,20 +301,20 @@ inside:
 	bne	Casper			/*   we found a ghost! */
 
 	/* now close ghost ( inner ) loop */
-	addi 	r29, r29, 1		/* increment inner loop counter */
-	cmpw 	r29, r26		/* check for last inner loop */
+	addi	r29, r29, 1		/* increment inner loop counter */
+	cmpw	r29, r26		/* check for last inner loop */
 	blt		inside		/* do more inner loops */
 
 	/* now close referance ( outer ) loop */
-	addi 	r31, 0, 0 		/* r31 = zero */
+	addi	r31, 0, 0		/* r31 = zero */
 	stb	r31, 0(28)		/* zero out the altered address loc. */
 	/*
 	 * Increment and check for end, count is zero based.
 	 * With the ble, this gives us one more loops than
 	 * address bits for sequence 0,1,2,4,8,...2^(n-1)
 	*/
-	addi 	r30, r30, 1		/* increment outer loop counter */
-	cmpw 	r30, r26		/* check for last inner loop */
+	addi	r30, r30, 1		/* increment outer loop counter */
+	cmpw	r30, r26		/* check for last inner loop */
 	ble	outside			/* do more outer loops */
 
 	/* were done, lets go home */
@@ -391,7 +391,7 @@ fill_test:
 	mr	r28, r4
 	mr	r29, r5
 
-	WATCHDOG_RESET   		/* Reset the watchdog */
+	WATCHDOG_RESET			/* Reset the watchdog */
 
 	/* first fill memory with Value */
 	srawi	r31, r29, 2		/* convert bytes to longs */
@@ -401,10 +401,10 @@ ft_0:	stw	r28, 0(r30)		/* Store value */
 	addi	r30, r30, 4		/* Increment to next word */
 	andi.	r31, r30, 0xffff	/* check for 2^16 loops */
 	bne	ft_0a			/* if not there, then skip */
-	WATCHDOG_RESET   		/* kick the dog every now and then */
+	WATCHDOG_RESET			/* kick the dog every now and then */
 ft_0a:	bdnz	ft_0			/* Round and round... */
 
-	WATCHDOG_RESET   		/* Reset the watchdog */
+	WATCHDOG_RESET			/* Reset the watchdog */
 
 	/* Now confirm Value is in memory */
 	srawi	r31, r29, 2		/* convert bytes to longs */
@@ -419,7 +419,7 @@ ft_1:	lwz	r31, 0(r30)		/* get value from memory */
 	WATCHDOG_RESET			/* kick the dog every now and then */
 ft_1a:	bdnz	ft_1			/* Round and round... */
 
-	WATCHDOG_RESET   		/* Reset the watchdog */
+	WATCHDOG_RESET			/* Reset the watchdog */
 
 	b	fill_done		/* restore and return */
 
@@ -608,9 +608,9 @@ temp_uart_init:
 
 	/* output a few line feeds */
 	addi	r3, 0, '\n'		/* load line feed */
-	bl 	post_putc		/* output the char */
+	bl	post_putc		/* output the char */
 	addi	r3, 0, '\n'		/* load line feed */
-	bl 	post_putc		/* output the char */
+	bl	post_putc		/* output the char */
 
 	/* restore stack and return */
 	lwz	r0, +12(r1)		/* Get saved link register */
@@ -637,15 +637,15 @@ post_putc:
 
      addis   r31, 0, 0xef60		/* Point to uart base */
      ori     r31, r31, 0x0300
-     addis   r30, 0, 152 		/* Load about 10,000,000 ticks. */
+     addis   r30, 0, 152		/* Load about 10,000,000 ticks. */
 pputc_lp:
-	lbz     r29, 5(r31) 		/* Read Line Status Register */
+	lbz     r29, 5(r31)		/* Read Line Status Register */
 	andi.   r29, r29, 0x20		/* Check THRE status */
 	bne     thre_set		/* Branch if FIFO empty */
 	addic.  r30, r30, -1		/* Decrement and check if empty. */
 	bne     pputc_lp		/* Try, try again */
 	addi    r3, 0, -1		/* Load error code for timeout */
-	b       pputc_done 		/* Bail out with error code set */
+	b       pputc_done		/* Bail out with error code set */
 thre_set:
 	stb     r3, 0(r31)		/* Store character to UART */
 	addi	r3, 0, 0		/* clear error code */
@@ -671,7 +671,7 @@ post_puts:
 	stw	r0, +16(r1)		/* Save link register */
 	stw	r31, 8(r1)		/* save r31 - char pointer */
 
-	addi 	r31, r3, 0              /* move pointer to R31 */
+	addi	r31, r3, 0              /* move pointer to R31 */
 pputs_nxt:
 	lbz	r3, 0(r31)		/* Get next character */
 	addic.  r3, r3, 0		/* Check for zero */
@@ -679,13 +679,13 @@ pputs_nxt:
 	bl	post_putc		/* output the char */
 	addic.	r3, r3, 0		/* check for error */
 	bne	pputs_err
-	addi 	r31, r31, 1		/* point to next char */
-	b	pputs_nxt 		/* loop till term */
+	addi	r31, r31, 1		/* point to next char */
+	b	pputs_nxt		/* loop till term */
 pputs_err:
-	addi 	r3, 0, -1		/* set error code */
+	addi	r3, 0, -1		/* set error code */
 	b	pputs_end		/* were outa here */
 pputs_term:
-	addi 	r3, 0, 1		/* set success code */
+	addi	r3, 0, 1		/* set success code */
 	/* restore stack and return */
 pputs_end:
 	lwz	r31, 8(r1)		/* restore r27 - r31 from stack */
@@ -711,20 +711,20 @@ disp_hex:
 	stmw	r30, 8(r1)		/* save r30 - r31 on stack */
 					/* r31 output char */
 					/* r30 uart base address */
-	addi 	r30, 0, 8               /* Go through 8 nibbles. */
-	addi 	r31, r3, 0
+	addi	r30, 0, 8               /* Go through 8 nibbles. */
+	addi	r31, r3, 0
 pputh_nxt:
 	rlwinm	r31, r31, 4, 0, 31	/* Rotate next nibble into position */
-	andi. 	r3, r31, 0x0f		/* Get nibble. */
-	addi 	r3, r3, 0x30		/* Add zero's ASCII code. */
+	andi.	r3, r31, 0x0f		/* Get nibble. */
+	addi	r3, r3, 0x30		/* Add zero's ASCII code. */
 	cmpwi	r3, 0x03a
 	blt	pputh_out
-	addi 	r3, r3, 0x07            /* 0x27 for lower case. */
+	addi	r3, r3, 0x07            /* 0x27 for lower case. */
 pputh_out:
-	cmpw 	r30, r4
+	cmpw	r30, r4
 	bgt	pputh_skip
 	bl	post_putc
-	addic. 	r3, r3, 0 		/* check for error */
+	addic.	r3, r3, 0		/* check for error */
 	bne	pputh_err
 pputh_skip:
 	addic.	r30, r30, -1
@@ -732,7 +732,7 @@ pputh_skip:
 	xor	r3, r3, r3		/* Clear error code */
 	b	pputh_done
 pputh_err:
-	addi 	r3, 0, -1 		/* set error code */
+	addi	r3, 0, -1		/* set error code */
 pputh_done:
 	/* restore stack and return */
 	lmw	r30, 8(r1)		/*  restore r30 - r31 from stack */
diff --git a/board/w7o/u-boot.lds b/board/w7o/u-boot.lds
index c88bfd10f3..3373793c63 100644
--- a/board/w7o/u-boot.lds
+++ b/board/w7o/u-boot.lds
@@ -38,11 +38,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/w7o/u-boot.lds.debug b/board/w7o/u-boot.lds.debug
index 834d68d6ca..d3ffed300a 100644
--- a/board/w7o/u-boot.lds.debug
+++ b/board/w7o/u-boot.lds.debug
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/wepep250/lowlevel_init.S b/board/wepep250/lowlevel_init.S
index b172ceaa61..9bb091f509 100644
--- a/board/wepep250/lowlevel_init.S
+++ b/board/wepep250/lowlevel_init.S
@@ -41,9 +41,9 @@ lowlevel_init:
 	mov	r10, lr
 
 /*	setup memory - see 6.12 in [1]
- *	Step 1 	- wait 200 us
+ *	Step 1	- wait 200 us
  */
-	mov	r0,#0x2700      		/* wait 200 us @ 99.5 MHz */
+	mov	r0,#0x2700			/* wait 200 us @ 99.5 MHz */
 1:	subs	r0, r0, #1
 	bne	1b
 /*	TODO: complete step 1 for Synchronous Static memory*/
@@ -51,7 +51,7 @@ lowlevel_init:
 	ldr	r0, =0x48000000			/* MC_BASE */
 
 
-/* 	step 1.a - setup MSCx
+/*	step 1.a - setup MSCx
  */
 	ldr	r1, =0x000012B3			/* MSC0_RRR0(1) | MSC0_RDN0(2) | MSC0_RDF0(11) | MSC0_RT0(3) */
 	str	r1, [r0, #0x8]			/* MSC0_OFFSET */
@@ -111,7 +111,7 @@ lowlevel_init:
 /*	Step 5 - wait at least 200 us for SDRAM
  *	see section B. in [2]
  */
-	mov	r2,#0x2700      		/* wait 200 us @ 99.5 MHz */
+	mov	r2,#0x2700			/* wait 200 us @ 99.5 MHz */
 1:	subs	r2, r2, #1
 	bne	1b
 
diff --git a/board/westel/amx860/u-boot.lds b/board/westel/amx860/u-boot.lds
index ee598c2cfc..10b38ec356 100644
--- a/board/westel/amx860/u-boot.lds
+++ b/board/westel/amx860/u-boot.lds
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/westel/amx860/u-boot.lds.debug b/board/westel/amx860/u-boot.lds.debug
index 452c6c0a37..7a7a40c23e 100644
--- a/board/westel/amx860/u-boot.lds.debug
+++ b/board/westel/amx860/u-boot.lds.debug
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/xilinx/common/xdma_channel.c b/board/xilinx/common/xdma_channel.c
index 3d5fc75e36..f816138243 100644
--- a/board/xilinx/common/xdma_channel.c
+++ b/board/xilinx/common/xdma_channel.c
@@ -226,7 +226,7 @@ XDmaChannel_GetVersion(XDmaChannel * InstancePtr)
 * XST_SUCCESS is returned if the self test is successful, or one of the
 * following errors.
 *
-*	XST_DMA_RESET_REGISTER_ERROR 		Indicates the control register value
+*	XST_DMA_RESET_REGISTER_ERROR		Indicates the control register value
 *										after a reset was not correct
 *
 * NOTES:
@@ -475,7 +475,7 @@ XDmaChannel_GetStatus(XDmaChannel * InstancePtr)
 *	XDC_IXR_DMA_DONE_MASK		The dma operation is done
 *	XDC_IXR_DMA_ERROR_MASK	    The dma operation had an error
 *	XDC_IXR_PKT_DONE_MASK	    A packet is complete
-*	XDC_IXR_PKT_THRESHOLD_MASK 	The packet count threshold reached
+*	XDC_IXR_PKT_THRESHOLD_MASK	The packet count threshold reached
 *	XDC_IXR_PKT_WAIT_BOUND_MASK The packet wait bound reached
 *	XDC_IXR_SG_DISABLE_ACK_MASK The scatter gather disable completed
 *	XDC_IXR_BD_MASK				A buffer descriptor is done
@@ -533,7 +533,7 @@ XDmaChannel_SetIntrStatus(XDmaChannel * InstancePtr, u32 Status)
 *	XDC_IXR_DMA_DONE_MASK		The dma operation is done
 *	XDC_IXR_DMA_ERROR_MASK	    The dma operation had an error
 *	XDC_IXR_PKT_DONE_MASK	    A packet is complete
-*	XDC_IXR_PKT_THRESHOLD_MASK 	The packet count threshold reached
+*	XDC_IXR_PKT_THRESHOLD_MASK	The packet count threshold reached
 *	XDC_IXR_PKT_WAIT_BOUND_MASK The packet wait bound reached
 *	XDC_IXR_SG_DISABLE_ACK_MASK The scatter gather disable completed
 *	XDC_IXR_SG_END_MASK			Current descriptor was the end of the list
@@ -584,7 +584,7 @@ XDmaChannel_GetIntrStatus(XDmaChannel * InstancePtr)
 *	XDC_IXR_DMA_DONE_MASK		The dma operation is done
 *	XDC_IXR_DMA_ERROR_MASK	    The dma operation had an error
 *	XDC_IXR_PKT_DONE_MASK	    A packet is complete
-*	XDC_IXR_PKT_THRESHOLD_MASK 	The packet count threshold reached
+*	XDC_IXR_PKT_THRESHOLD_MASK	The packet count threshold reached
 *	XDC_IXR_PKT_WAIT_BOUND_MASK The packet wait bound reached
 *	XDC_IXR_SG_DISABLE_ACK_MASK The scatter gather disable completed
 *	XDC_IXR_SG_END_MASK			Current descriptor was the end of the list
@@ -638,7 +638,7 @@ XDmaChannel_SetIntrEnable(XDmaChannel * InstancePtr, u32 Enable)
 *	XDC_IXR_DMA_DONE_MASK		The dma operation is done
 *	XDC_IXR_DMA_ERROR_MASK	    The dma operation had an error
 *	XDC_IXR_PKT_DONE_MASK	    A packet is complete
-*	XDC_IXR_PKT_THRESHOLD_MASK 	The packet count threshold reached
+*	XDC_IXR_PKT_THRESHOLD_MASK	The packet count threshold reached
 *	XDC_IXR_PKT_WAIT_BOUND_MASK The packet wait bound reached
 *	XDC_IXR_SG_DISABLE_ACK_MASK The scatter gather disable completed
 *	XDC_IXR_BD_MASK				A buffer descriptor is done
diff --git a/board/xilinx/common/xdma_channel.h b/board/xilinx/common/xdma_channel.h
index 06976c3e04..4685982234 100644
--- a/board/xilinx/common/xdma_channel.h
+++ b/board/xilinx/common/xdma_channel.h
@@ -96,7 +96,7 @@
 * 1. Create a scatter gather list for the DMA channel which puts empty buffer
 *    descriptors into the list.
 * 2. Create buffer descriptors which describe the buffers to be filled with
-* 	 receive data or the buffers which contain data to be sent.
+*	 receive data or the buffers which contain data to be sent.
 * 3. Put buffer descriptors into the DMA channel scatter list such that scatter
 *    gather operations are requested.
 * 4. Commit the buffer descriptors in the list such that they are ready to be
@@ -208,7 +208,7 @@
 #define XDC_IXR_DMA_DONE_MASK		0x1UL	/* dma operation done */
 #define XDC_IXR_DMA_ERROR_MASK	    0x2UL	/* dma operation error */
 #define XDC_IXR_PKT_DONE_MASK	    0x4UL	/* packet done */
-#define XDC_IXR_PKT_THRESHOLD_MASK 	0x8UL	/* packet count threshold */
+#define XDC_IXR_PKT_THRESHOLD_MASK	0x8UL	/* packet count threshold */
 #define XDC_IXR_PKT_WAIT_BOUND_MASK 0x10UL	/* packet wait bound reached */
 #define XDC_IXR_SG_DISABLE_ACK_MASK 0x20UL	/* scatter gather disable
 						   acknowledge occurred */
diff --git a/board/xilinx/ml300/u-boot.lds b/board/xilinx/ml300/u-boot.lds
index 815d81dd39..2d32225d4f 100644
--- a/board/xilinx/ml300/u-boot.lds
+++ b/board/xilinx/ml300/u-boot.lds
@@ -34,11 +34,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/xilinx/ml300/u-boot.lds.debug b/board/xilinx/ml300/u-boot.lds.debug
index 88dcaf91bf..0552994f40 100644
--- a/board/xilinx/ml300/u-boot.lds.debug
+++ b/board/xilinx/ml300/u-boot.lds.debug
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/xpedite1k/u-boot.lds b/board/xpedite1k/u-boot.lds
index 044511b473..70b1e38f3c 100644
--- a/board/xpedite1k/u-boot.lds
+++ b/board/xpedite1k/u-boot.lds
@@ -43,11 +43,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/xpedite1k/u-boot.lds.debug b/board/xpedite1k/u-boot.lds.debug
index e0e20ca7fd..e0da854a4d 100644
--- a/board/xpedite1k/u-boot.lds.debug
+++ b/board/xpedite1k/u-boot.lds.debug
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/xsengine/lowlevel_init.S b/board/xsengine/lowlevel_init.S
index 309faabd92..b0b156124c 100644
--- a/board/xsengine/lowlevel_init.S
+++ b/board/xsengine/lowlevel_init.S
@@ -109,7 +109,7 @@ lowlevel_init:
    ldr r3, =OSCR	/* reset the OS Timer Count to zero */
    mov r2, #0
    str r2, [r3]
-   ldr r4, =0x300  	/* really 0x2E1 is about 200usec, so 0x300 should be plenty */
+   ldr r4, =0x300	/* really 0x2E1 is about 200usec, so 0x300 should be plenty */
 1:
    ldr r2, [r3]
    cmp r4, r2
@@ -144,7 +144,7 @@ mem_init:
    ldr r3, =OSCR	/* reset the OS Timer Count to zero */
    mov r2, #0
    str r2, [r3]
-   ldr r4, =0x300  	/* about 200 usec */
+   ldr r4, =0x300	/* about 200 usec */
 1:
    ldr r2, [r3]
    cmp r4, r2
diff --git a/board/zeus/u-boot.lds b/board/zeus/u-boot.lds
index 670c943328..d803625b5a 100644
--- a/board/zeus/u-boot.lds
+++ b/board/zeus/u-boot.lds
@@ -38,11 +38,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/common/cmd_autoscript.c b/common/cmd_autoscript.c
index 932f6388ff..13af93ec85 100644
--- a/common/cmd_autoscript.c
+++ b/common/cmd_autoscript.c
@@ -52,7 +52,7 @@
 int
 autoscript (ulong addr, const char *fit_uname)
 {
-	ulong 		len;
+	ulong		len;
 	image_header_t	*hdr;
 	ulong		*data;
 	char		*cmd;
diff --git a/common/cmd_dcr.c b/common/cmd_dcr.c
index a053343abe..439d07a65d 100644
--- a/common/cmd_dcr.c
+++ b/common/cmd_dcr.c
@@ -123,7 +123,7 @@ int do_getidcr (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	if (argc < 3) {
 		printf ("Usage:\n%s\n", cmdtp->usage);
 		return 1;
- 	}
+	}
 
 	/* Find out whether ther is '.' (dot) symbol in the first parameter. */
 	strncpy (buf, argv[1], sizeof(buf)-1);
diff --git a/common/cmd_fdc.c b/common/cmd_fdc.c
index bf283702d3..0293d186ab 100644
--- a/common/cmd_fdc.c
+++ b/common/cmd_fdc.c
@@ -46,24 +46,23 @@
 #define FALSE           0
 #endif
 
-
 /*#if defined(CONFIG_CMD_DATE) */
 /*#include <rtc.h> */
 /*#endif */
 
 #if defined(CONFIG_CMD_FDC) || defined(CONFIG_CMD_FDOS)
 
-
 typedef struct {
-	int						flags;		/* connected drives ect */
-	unsigned long blnr;			/* Logical block nr */
-	uchar					drive; 		/* drive no */
-	uchar					cmdlen; 	/* cmd length */
-	uchar					cmd[16]; 	/* cmd desc */
-	uchar					dma;			/* if > 0 dma enabled */
-	uchar					result[11];/* status information */
-	uchar					resultlen; /* lenght of result */
+	int		flags;		/* connected drives ect */
+	unsigned long	blnr;		/* Logical block nr */
+	uchar		drive;		/* drive no */
+	uchar		cmdlen;		/* cmd length */
+	uchar		cmd[16];	/* cmd desc */
+	uchar		dma;		/* if > 0 dma enabled */
+	uchar		result[11];	/* status information */
+	uchar		resultlen;	/* lenght of result */
 } FDC_COMMAND_STRUCT;
+
 /* flags: only the lower 8bit used:
  * bit 0 if set drive 0 is present
  * bit 1 if set drive 1 is present
@@ -75,31 +74,30 @@ typedef struct {
  * bit 7 if set disk in drive 4 is inserted
  */
 
-
 /* cmd indexes */
-#define COMMAND 		0
-#define DRIVE 			1
+#define COMMAND			0
+#define DRIVE			1
 #define CONFIG0			1
-#define SPEC_HUTSRT	1
-#define TRACK 			2
+#define SPEC_HUTSRT		1
+#define TRACK			2
 #define CONFIG1			2
 #define SPEC_HLT		2
-#define HEAD				3
+#define HEAD			3
 #define CONFIG2			3
-#define SECTOR 			4
-#define SECTOR_SIZE	5
-#define LAST_TRACK	6
-#define GAP					7
-#define DTL					8
+#define SECTOR			4
+#define SECTOR_SIZE		5
+#define LAST_TRACK		6
+#define GAP			7
+#define DTL			8
 /* result indexes */
-#define STATUS_0						0
-#define STATUS_PCN					1
-#define STATUS_1						1
-#define STATUS_2						2
-#define STATUS_TRACK				3
-#define STATUS_HEAD					4
-#define STATUS_SECT					5
-#define STATUS_SECT_SIZE		6
+#define STATUS_0		0
+#define STATUS_PCN		1
+#define STATUS_1		1
+#define STATUS_2		2
+#define STATUS_TRACK		3
+#define STATUS_HEAD		4
+#define STATUS_SECT		5
+#define STATUS_SECT_SIZE	6
 
 
 /* Register addresses */
@@ -114,34 +112,34 @@ typedef struct {
 #define FDC_DIR		FDC_BASE + 6	/* Digital Input Register */
 #define FDC_CCR		FDC_BASE + 7	/* Configuration Control */
 /* Commands */
-#define FDC_CMD_SENSE_INT 		0x08
-#define FDC_CMD_CONFIGURE 		0x13
-#define FDC_CMD_SPECIFY	 			0x03
-#define FDC_CMD_RECALIBRATE 	0x07
-#define FDC_CMD_READ				 	0x06
-#define FDC_CMD_READ_TRACK	 	0x02
-#define FDC_CMD_READ_ID			 	0x0A
-#define FDC_CMD_DUMP_REG		 	0x0E
-#define FDC_CMD_SEEK				 	0x0F
-
-#define FDC_CMD_SENSE_INT_LEN 		0x01
-#define FDC_CMD_CONFIGURE_LEN 		0x04
-#define FDC_CMD_SPECIFY_LEN	 			0x03
-#define FDC_CMD_RECALIBRATE_LEN 	0x02
-#define FDC_CMD_READ_LEN				 	0x09
-#define FDC_CMD_READ_TRACK_LEN	 	0x09
-#define FDC_CMD_READ_ID_LEN			 	0x02
-#define FDC_CMD_DUMP_REG_LEN		 	0x01
-#define FDC_CMD_SEEK_LEN				 	0x03
-
-#define FDC_FIFO_THR			0x0C
-#define FDC_FIFO_DIS			0x00
+#define FDC_CMD_SENSE_INT	0x08
+#define FDC_CMD_CONFIGURE	0x13
+#define FDC_CMD_SPECIFY		0x03
+#define FDC_CMD_RECALIBRATE	0x07
+#define FDC_CMD_READ		0x06
+#define FDC_CMD_READ_TRACK	0x02
+#define FDC_CMD_READ_ID		0x0A
+#define FDC_CMD_DUMP_REG	0x0E
+#define FDC_CMD_SEEK		0x0F
+
+#define FDC_CMD_SENSE_INT_LEN	0x01
+#define FDC_CMD_CONFIGURE_LEN	0x04
+#define FDC_CMD_SPECIFY_LEN	0x03
+#define FDC_CMD_RECALIBRATE_LEN	0x02
+#define FDC_CMD_READ_LEN	0x09
+#define FDC_CMD_READ_TRACK_LEN	0x09
+#define FDC_CMD_READ_ID_LEN	0x02
+#define FDC_CMD_DUMP_REG_LEN	0x01
+#define FDC_CMD_SEEK_LEN	0x03
+
+#define FDC_FIFO_THR		0x0C
+#define FDC_FIFO_DIS		0x00
 #define FDC_IMPLIED_SEEK	0x01
-#define FDC_POLL_DIS			0x00
-#define FDC_PRE_TRK				0x00
-#define FDC_CONFIGURE			FDC_FIFO_THR | (FDC_POLL_DIS<<4) | (FDC_FIFO_DIS<<5) | (FDC_IMPLIED_SEEK << 6)
-#define FDC_MFM_MODE			0x01 /* MFM enable */
-#define FDC_SKIP_MODE			0x00 /* skip enable */
+#define FDC_POLL_DIS		0x00
+#define FDC_PRE_TRK		0x00
+#define FDC_CONFIGURE		FDC_FIFO_THR | (FDC_POLL_DIS<<4) | (FDC_FIFO_DIS<<5) | (FDC_IMPLIED_SEEK << 6)
+#define FDC_MFM_MODE		0x01 /* MFM enable */
+#define FDC_SKIP_MODE		0x00 /* skip enable */
 
 #define FDC_TIME_OUT 100000 /* time out */
 #define	FDC_RW_RETRIES		3 /* read write retries */
@@ -150,18 +148,18 @@ typedef struct {
 
 /* Disk structure */
 typedef struct  {
-	unsigned int size;			/* nr of sectors total */
-	unsigned int sect;			/* sectors per track */
-	unsigned int head;			/* nr of heads */
-	unsigned int track;			/* nr of tracks */
-	unsigned int stretch;		/* !=0 means double track steps */
-	unsigned char	gap;			/* gap1 size */
-	unsigned char	rate;			/* data rate. |= 0x40 for perpendicular */
-	unsigned char	spec1;		/* stepping rate, head unload time */
-	unsigned char	fmt_gap;	/* gap2 size */
-	unsigned char hlt;			/* head load time */
-	unsigned char sect_code; /* Sector Size code */
-	const char	* name; 		/* used only for predefined formats */
+	unsigned int size;	/* nr of sectors total */
+	unsigned int sect;	/* sectors per track */
+	unsigned int head;	/* nr of heads */
+	unsigned int track;	/* nr of tracks */
+	unsigned int stretch;	/* !=0 means double track steps */
+	unsigned char	gap;	/* gap1 size */
+	unsigned char	rate;	/* data rate. |= 0x40 for perpendicular */
+	unsigned char	spec1;	/* stepping rate, head unload time */
+	unsigned char	fmt_gap;/* gap2 size */
+	unsigned char hlt;	/* head load time */
+	unsigned char sect_code;/* Sector Size code */
+	const char	* name;	/* used only for predefined formats */
 } FD_GEO_STRUCT;
 
 
@@ -342,7 +340,7 @@ int fdc_issue_cmd(FDC_COMMAND_STRUCT *pCMD,FD_GEO_STRUCT *pFG)
 		case FDC_CMD_CONFIGURE:
 			pCMD->cmd[CONFIG0]=0;
 			pCMD->cmd[CONFIG1]=FDC_CONFIGURE; /* FIFO Threshold, Poll, Enable FIFO */
-			pCMD->cmd[CONFIG2]=FDC_PRE_TRK; 	/* Precompensation Track */
+			pCMD->cmd[CONFIG2]=FDC_PRE_TRK;	/* Precompensation Track */
 			pCMD->cmdlen=FDC_CMD_CONFIGURE_LEN;
 			pCMD->resultlen=0;  /* no result */
 			break;
diff --git a/common/cmd_fdt.c b/common/cmd_fdt.c
index 7436a95153..ede65ae75a 100644
--- a/common/cmd_fdt.c
+++ b/common/cmd_fdt.c
@@ -464,13 +464,13 @@ static int fdt_valid(void)
 /*
  * Parse the user's input, partially heuristic.  Valid formats:
  * <0x00112233 4 05>	- an array of cells.  Numbers follow standard
- * 			C conventions.
+ *			C conventions.
  * [00 11 22 .. nn] - byte stream
  * "string"	- If the the value doesn't start with "<" or "[", it is
  *			treated as a string.  Note that the quotes are
  *			stripped by the parser before we get the string.
  * newval: An array of strings containing the new property as specified
- * 	on the command line
+ *	on the command line
  * count: The number of strings in the array
  * data: A bytestream to be placed in the property
  * len: The length of the resulting bytestream
diff --git a/common/cmd_i2c.c b/common/cmd_i2c.c
index c60ec99dad..aac7e9a6c5 100644
--- a/common/cmd_i2c.c
+++ b/common/cmd_i2c.c
@@ -266,8 +266,8 @@ int do_i2c_mw ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	}
 
 	/*
- 	 * Chip is always specified.
- 	 */
+	 * Chip is always specified.
+	 */
 	chip = simple_strtoul(argv[1], NULL, 16);
 
 	/*
@@ -353,8 +353,8 @@ int do_i2c_crc (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	}
 
 	/*
- 	 * Chip is always specified.
- 	 */
+	 * Chip is always specified.
+	 */
 	chip = simple_strtoul(argv[1], NULL, 16);
 
 	/*
@@ -444,8 +444,8 @@ mod_i2c_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char *argv[])
 		size = cmd_get_data_size(argv[0], 1);
 
 		/*
-	 	 * Chip is always specified.
-	 	 */
+		 * Chip is always specified.
+		 */
 		chip = simple_strtoul(argv[1], NULL, 16);
 
 		/*
@@ -1256,7 +1256,7 @@ int do_i2c(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 #if defined(CONFIG_I2C_CMD_TREE)
 U_BOOT_CMD(
 	i2c, 6, 1, do_i2c,
- 	"i2c     - I2C sub-system\n",
+	"i2c     - I2C sub-system\n",
 #if defined(CONFIG_I2C_MULTI_BUS)
 	"dev [dev] - show or set current I2C bus\n"
 #endif  /* CONFIG_I2C_MULTI_BUS */
@@ -1280,7 +1280,7 @@ U_BOOT_CMD(
 );
 
 U_BOOT_CMD(
- 	imm,	3,	1,	do_i2c_mm,
+	imm,	3,	1,	do_i2c_mm,
 	"imm     - i2c memory modify (auto-incrementing)\n",
 	"chip address[.0, .1, .2]\n"
 	"    - memory modify, auto increment address\n"
diff --git a/common/cmd_ide.c b/common/cmd_ide.c
index cac99d5fe7..65607022eb 100644
--- a/common/cmd_ide.c
+++ b/common/cmd_ide.c
@@ -1233,7 +1233,7 @@ static void ide_ident (block_dev_desc_t *dev_desc)
 	dev_desc->blksz=ATA_BLOCKSIZE;
 	dev_desc->lun=0; /* just to fill something in... */
 
-#if 0 	/* only used to test the powersaving mode,
+#if 0	/* only used to test the powersaving mode,
 	 * if enabled, the drive goes after 5 sec
 	 * in standby mode */
 	ide_outb (device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device));
@@ -1783,7 +1783,7 @@ unsigned char atapi_issue(int device,unsigned char* ccb,int ccblen, unsigned cha
 	}
 
 	output_data_shorts (device, (unsigned short *)ccb,ccblen/2); /* write command block */
- 	/* ATAPI Command written wait for completition */
+	/* ATAPI Command written wait for completition */
 	udelay (5000); /* device must set bsy */
 
 	mask = ATA_STAT_DRQ|ATA_STAT_BUSY|ATA_STAT_ERR;
@@ -1852,7 +1852,7 @@ AI_OUT:
  * returns, an request_sense will be issued
  */
 
-#define ATAPI_DRIVE_NOT_READY 	100
+#define ATAPI_DRIVE_NOT_READY	100
 #define ATAPI_UNIT_ATTN		10
 
 unsigned char atapi_issue_autoreq (int device,
diff --git a/common/cmd_log.c b/common/cmd_log.c
index b9f9ba0342..c6e72ac3c0 100644
--- a/common/cmd_log.c
+++ b/common/cmd_log.c
@@ -107,7 +107,7 @@ void logbuff_init_ptrs (void)
 	if ((s = getenv ("loglevel")) != NULL)
 		console_loglevel = (int)simple_strtoul (s, NULL, 10);
 
-	gd->post_log_word |= LOGBUFF_INITIALIZED;
+	gd->flags |= GD_FLG_LOGINIT;
 }
 
 void logbuff_reset (void)
@@ -168,7 +168,7 @@ static void logbuff_puts (const char *s)
 
 void logbuff_log(char *msg)
 {
-	if ((gd->post_log_word & LOGBUFF_INITIALIZED)) {
+	if ((gd->flags & GD_FLG_LOGINIT)) {
 		logbuff_printk (msg);
 	} else {
 		/* Can happen only for pre-relocated errors as logging */
diff --git a/common/cmd_mem.c b/common/cmd_mem.c
index 51aa71fca8..2606986db3 100644
--- a/common/cmd_mem.c
+++ b/common/cmd_mem.c
@@ -1201,56 +1201,56 @@ int do_mem_crc (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 /**************************************************/
 #if defined(CONFIG_CMD_MEMORY)
 U_BOOT_CMD(
-	md,     3,     1,      do_mem_md,
-	"md      - memory display\n",
-	"[.b, .w, .l] address [# of objects]\n    - memory display\n"
+	md,	3,	1,	do_mem_md,
+	"md	 - memory display\n",
+	"[.b, .w, .l] address [# of objects]\n	  - memory display\n"
 );
 
 
 U_BOOT_CMD(
-	mm,     2,      1,       do_mem_mm,
-	"mm      - memory modify (auto-incrementing)\n",
+	mm,	2,	1,	do_mem_mm,
+	"mm	 - memory modify (auto-incrementing)\n",
 	"[.b, .w, .l] address\n" "    - memory modify, auto increment address\n"
 );
 
 
 U_BOOT_CMD(
-	nm,     2,	    1,     	do_mem_nm,
-	"nm      - memory modify (constant address)\n",
+	nm,	2,	1,	do_mem_nm,
+	"nm	 - memory modify (constant address)\n",
 	"[.b, .w, .l] address\n    - memory modify, read and keep address\n"
 );
 
 U_BOOT_CMD(
-	mw,    4,    1,     do_mem_mw,
-	"mw      - memory write (fill)\n",
-	"[.b, .w, .l] address value [count]\n    - write memory\n"
+	mw,	4,	1,	do_mem_mw,
+	"mw	 - memory write (fill)\n",
+	"[.b, .w, .l] address value [count]\n	 - write memory\n"
 );
 
 U_BOOT_CMD(
-	cp,    4,    1,    do_mem_cp,
-	"cp      - memory copy\n",
+	cp,	4,	1,	do_mem_cp,
+	"cp	 - memory copy\n",
 	"[.b, .w, .l] source target count\n    - copy memory\n"
 );
 
 U_BOOT_CMD(
-	cmp,    4,     1,     do_mem_cmp,
-	"cmp     - memory compare\n",
+	cmp,	4,	1,	do_mem_cmp,
+	"cmp	 - memory compare\n",
 	"[.b, .w, .l] addr1 addr2 count\n    - compare memory\n"
 );
 
 #ifndef CONFIG_CRC32_VERIFY
 
 U_BOOT_CMD(
-	crc32,    4,    1,     do_mem_crc,
-	"crc32   - checksum calculation\n",
+	crc32,	4,	1,	do_mem_crc,
+	"crc32	 - checksum calculation\n",
 	"address count [addr]\n    - compute CRC32 checksum [save at addr]\n"
 );
 
 #else	/* CONFIG_CRC32_VERIFY */
 
 U_BOOT_CMD(
-	crc32,    5,    1,     do_mem_crc,
-	"crc32   - checksum calculation\n",
+	crc32,	5,	1,	do_mem_crc,
+	"crc32	 - checksum calculation\n",
 	"address count [addr]\n    - compute CRC32 checksum [save at addr]\n"
 	"-v address count crc\n    - verify crc of memory area\n"
 );
@@ -1258,45 +1258,45 @@ U_BOOT_CMD(
 #endif	/* CONFIG_CRC32_VERIFY */
 
 U_BOOT_CMD(
-	base,    2,    1,     do_mem_base,
-	"base    - print or set address offset\n",
+	base,	2,	1,	do_mem_base,
+	"base	 - print or set address offset\n",
 	"\n    - print address offset for memory commands\n"
 	"base off\n    - set address offset for memory commands to 'off'\n"
 );
 
 U_BOOT_CMD(
-	loop,    3,    1,    do_mem_loop,
-	"loop    - infinite loop on address range\n",
+	loop,	3,	1,	do_mem_loop,
+	"loop	 - infinite loop on address range\n",
 	"[.b, .w, .l] address number_of_objects\n"
 	"    - loop on a set of addresses\n"
 );
 
 #ifdef CONFIG_LOOPW
 U_BOOT_CMD(
-	loopw,    4,    1,    do_mem_loopw,
-	"loopw   - infinite write loop on address range\n",
+	loopw,	4,	1,	do_mem_loopw,
+	"loopw	 - infinite write loop on address range\n",
 	"[.b, .w, .l] address number_of_objects data_to_write\n"
 	"    - loop on a set of addresses\n"
 );
 #endif /* CONFIG_LOOPW */
 
 U_BOOT_CMD(
-	mtest,    4,    1,     do_mem_mtest,
-	"mtest   - simple RAM test\n",
+	mtest,	4,	1,	do_mem_mtest,
+	"mtest	 - simple RAM test\n",
 	"[start [end [pattern]]]\n"
 	"    - simple RAM read/write test\n"
 );
 
 #ifdef CONFIG_MX_CYCLIC
 U_BOOT_CMD(
-	mdc,     4,     1,      do_mem_mdc,
-	"mdc     - memory display cyclic\n",
+	mdc,	4,	1,	do_mem_mdc,
+	"mdc	 - memory display cyclic\n",
 	"[.b, .w, .l] address count delay(ms)\n    - memory display cyclic\n"
 );
 
 U_BOOT_CMD(
-	mwc,     4,     1,      do_mem_mwc,
-	"mwc     - memory write cyclic\n",
+	mwc,	4,	1,	do_mem_mwc,
+	"mwc	 - memory write cyclic\n",
 	"[.b, .w, .l] address value delay(ms)\n    - memory write cyclic\n"
 );
 #endif /* CONFIG_MX_CYCLIC */
diff --git a/common/cmd_pci.c b/common/cmd_pci.c
index 82d97178f5..89687015b2 100644
--- a/common/cmd_pci.c
+++ b/common/cmd_pci.c
@@ -173,7 +173,7 @@ static char *pci_classes_str(u8 class)
  * Subroutine:  pci_header_show_brief
  *
  * Description: Reads and prints the header of the
- * 		specified PCI device in short form.
+ *		specified PCI device in short form.
  *
  * Inputs:	dev      Bus+Device+Function number
  *
diff --git a/common/cmd_reginfo.c b/common/cmd_reginfo.c
index dd808edf2a..1669d74962 100644
--- a/common/cmd_reginfo.c
+++ b/common/cmd_reginfo.c
@@ -109,24 +109,24 @@ int do_reginfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	puts ("\nMemory (SDRAM) Configuration\n"
 	    "besra    besrsa   besrb    besrsb   bear     mcopt1   rtr      pmit\n");
 
-	mtdcr(memcfga,mem_besra); 	printf ("%08x ", mfdcr(memcfgd));
+	mtdcr(memcfga,mem_besra);	printf ("%08x ", mfdcr(memcfgd));
 	mtdcr(memcfga,mem_besrsa);	printf ("%08x ", mfdcr(memcfgd));
-	mtdcr(memcfga,mem_besrb); 	printf ("%08x ", mfdcr(memcfgd));
-	mtdcr(memcfga,mem_besrsb); 	printf ("%08x ", mfdcr(memcfgd));
-	mtdcr(memcfga,mem_bear); 	printf ("%08x ", mfdcr(memcfgd));
-	mtdcr(memcfga,mem_mcopt1); 	printf ("%08x ", mfdcr(memcfgd));
-	mtdcr(memcfga,mem_rtr); 	printf ("%08x ", mfdcr(memcfgd));
-	mtdcr(memcfga,mem_pmit); 	printf ("%08x ", mfdcr(memcfgd));
+	mtdcr(memcfga,mem_besrb);	printf ("%08x ", mfdcr(memcfgd));
+	mtdcr(memcfga,mem_besrsb);	printf ("%08x ", mfdcr(memcfgd));
+	mtdcr(memcfga,mem_bear);	printf ("%08x ", mfdcr(memcfgd));
+	mtdcr(memcfga,mem_mcopt1);	printf ("%08x ", mfdcr(memcfgd));
+	mtdcr(memcfga,mem_rtr);		printf ("%08x ", mfdcr(memcfgd));
+	mtdcr(memcfga,mem_pmit);	printf ("%08x ", mfdcr(memcfgd));
 
 	puts ("\n"
 	    "mb0cf    mb1cf    mb2cf    mb3cf    sdtr1    ecccf    eccerr\n");
-	mtdcr(memcfga,mem_mb0cf); 	printf ("%08x ", mfdcr(memcfgd));
-	mtdcr(memcfga,mem_mb1cf); 	printf ("%08x ", mfdcr(memcfgd));
-	mtdcr(memcfga,mem_mb2cf); 	printf ("%08x ", mfdcr(memcfgd));
-	mtdcr(memcfga,mem_mb3cf); 	printf ("%08x ", mfdcr(memcfgd));
-	mtdcr(memcfga,mem_sdtr1); 	printf ("%08x ", mfdcr(memcfgd));
-	mtdcr(memcfga,mem_ecccf); 	printf ("%08x ", mfdcr(memcfgd));
-	mtdcr(memcfga,mem_eccerr); 	printf ("%08x ", mfdcr(memcfgd));
+	mtdcr(memcfga,mem_mb0cf);	printf ("%08x ", mfdcr(memcfgd));
+	mtdcr(memcfga,mem_mb1cf);	printf ("%08x ", mfdcr(memcfgd));
+	mtdcr(memcfga,mem_mb2cf);	printf ("%08x ", mfdcr(memcfgd));
+	mtdcr(memcfga,mem_mb3cf);	printf ("%08x ", mfdcr(memcfgd));
+	mtdcr(memcfga,mem_sdtr1);	printf ("%08x ", mfdcr(memcfgd));
+	mtdcr(memcfga,mem_ecccf);	printf ("%08x ", mfdcr(memcfgd));
+	mtdcr(memcfga,mem_eccerr);	printf ("%08x ", mfdcr(memcfgd));
 
 	printf ("\n\n"
 	    "DMA Channels\n"
@@ -149,32 +149,32 @@ int do_reginfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	puts ("\n"
 	    "External Bus\n"
 	    "pbear    pbesr0   pbesr1   epcr\n");
-	mtdcr(ebccfga,pbear); 	printf ("%08x ", mfdcr(ebccfgd));
-	mtdcr(ebccfga,pbesr0); 	printf ("%08x ", mfdcr(ebccfgd));
-	mtdcr(ebccfga,pbesr1); 	printf ("%08x ", mfdcr(ebccfgd));
-	mtdcr(ebccfga,epcr); 	printf ("%08x ", mfdcr(ebccfgd));
+	mtdcr(ebccfga,pbear);	printf ("%08x ", mfdcr(ebccfgd));
+	mtdcr(ebccfga,pbesr0);	printf ("%08x ", mfdcr(ebccfgd));
+	mtdcr(ebccfga,pbesr1);	printf ("%08x ", mfdcr(ebccfgd));
+	mtdcr(ebccfga,epcr);	printf ("%08x ", mfdcr(ebccfgd));
 
 	puts ("\n"
 	    "pb0cr    pb0ap    pb1cr    pb1ap    pb2cr    pb2ap    pb3cr    pb3ap\n");
-	mtdcr(ebccfga,pb0cr); 	printf ("%08x ", mfdcr(ebccfgd));
-	mtdcr(ebccfga,pb0ap); 	printf ("%08x ", mfdcr(ebccfgd));
-	mtdcr(ebccfga,pb1cr); 	printf ("%08x ", mfdcr(ebccfgd));
-	mtdcr(ebccfga,pb1ap); 	printf ("%08x ", mfdcr(ebccfgd));
-	mtdcr(ebccfga,pb2cr); 	printf ("%08x ", mfdcr(ebccfgd));
-	mtdcr(ebccfga,pb2ap); 	printf ("%08x ", mfdcr(ebccfgd));
-	mtdcr(ebccfga,pb3cr); 	printf ("%08x ", mfdcr(ebccfgd));
-	mtdcr(ebccfga,pb3ap); 	printf ("%08x ", mfdcr(ebccfgd));
+	mtdcr(ebccfga,pb0cr);	printf ("%08x ", mfdcr(ebccfgd));
+	mtdcr(ebccfga,pb0ap);	printf ("%08x ", mfdcr(ebccfgd));
+	mtdcr(ebccfga,pb1cr);	printf ("%08x ", mfdcr(ebccfgd));
+	mtdcr(ebccfga,pb1ap);	printf ("%08x ", mfdcr(ebccfgd));
+	mtdcr(ebccfga,pb2cr);	printf ("%08x ", mfdcr(ebccfgd));
+	mtdcr(ebccfga,pb2ap);	printf ("%08x ", mfdcr(ebccfgd));
+	mtdcr(ebccfga,pb3cr);	printf ("%08x ", mfdcr(ebccfgd));
+	mtdcr(ebccfga,pb3ap);	printf ("%08x ", mfdcr(ebccfgd));
 
 	puts ("\n"
 	    "pb4cr    pb4ap    pb5cr    bp5ap    pb6cr    pb6ap    pb7cr    pb7ap\n");
-	mtdcr(ebccfga,pb4cr); 	printf ("%08x ", mfdcr(ebccfgd));
-	mtdcr(ebccfga,pb4ap); 	printf ("%08x ", mfdcr(ebccfgd));
-	mtdcr(ebccfga,pb5cr); 	printf ("%08x ", mfdcr(ebccfgd));
-	mtdcr(ebccfga,pb5ap); 	printf ("%08x ", mfdcr(ebccfgd));
-	mtdcr(ebccfga,pb6cr); 	printf ("%08x ", mfdcr(ebccfgd));
-	mtdcr(ebccfga,pb6ap); 	printf ("%08x ", mfdcr(ebccfgd));
-	mtdcr(ebccfga,pb7cr); 	printf ("%08x ", mfdcr(ebccfgd));
-	mtdcr(ebccfga,pb7ap); 	printf ("%08x ", mfdcr(ebccfgd));
+	mtdcr(ebccfga,pb4cr);	printf ("%08x ", mfdcr(ebccfgd));
+	mtdcr(ebccfga,pb4ap);	printf ("%08x ", mfdcr(ebccfgd));
+	mtdcr(ebccfga,pb5cr);	printf ("%08x ", mfdcr(ebccfgd));
+	mtdcr(ebccfga,pb5ap);	printf ("%08x ", mfdcr(ebccfgd));
+	mtdcr(ebccfga,pb6cr);	printf ("%08x ", mfdcr(ebccfgd));
+	mtdcr(ebccfga,pb6ap);	printf ("%08x ", mfdcr(ebccfgd));
+	mtdcr(ebccfga,pb7cr);	printf ("%08x ", mfdcr(ebccfgd));
+	mtdcr(ebccfga,pb7ap);	printf ("%08x ", mfdcr(ebccfgd));
 
 	puts ("\n\n");
 
@@ -196,12 +196,12 @@ int do_reginfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	puts ("\nMemory (SDRAM) Configuration\n"
 	    "mcopt1   rtr      pmit     mb0cf    mb1cf    sdtr1\n");
 
-	mtdcr(memcfga,mem_mcopt1); 	printf ("%08x ", mfdcr(memcfgd));
-	mtdcr(memcfga,mem_rtr); 	printf ("%08x ", mfdcr(memcfgd));
-	mtdcr(memcfga,mem_pmit); 	printf ("%08x ", mfdcr(memcfgd));
-	mtdcr(memcfga,mem_mb0cf); 	printf ("%08x ", mfdcr(memcfgd));
-	mtdcr(memcfga,mem_mb1cf); 	printf ("%08x ", mfdcr(memcfgd));
-	mtdcr(memcfga,mem_sdtr1); 	printf ("%08x ", mfdcr(memcfgd));
+	mtdcr(memcfga,mem_mcopt1);	printf ("%08x ", mfdcr(memcfgd));
+	mtdcr(memcfga,mem_rtr);		printf ("%08x ", mfdcr(memcfgd));
+	mtdcr(memcfga,mem_pmit);	printf ("%08x ", mfdcr(memcfgd));
+	mtdcr(memcfga,mem_mb0cf);	printf ("%08x ", mfdcr(memcfgd));
+	mtdcr(memcfga,mem_mb1cf);	printf ("%08x ", mfdcr(memcfgd));
+	mtdcr(memcfga,mem_sdtr1);	printf ("%08x ", mfdcr(memcfgd));
 
 	printf ("\n\n"
 	    "DMA Channels\n"
@@ -221,31 +221,31 @@ int do_reginfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	puts ("\n"
 	    "External Bus\n"
 	    "pbear    pbesr0   pbesr1   epcr\n");
-	mtdcr(ebccfga,pbear); 	printf ("%08x ", mfdcr(ebccfgd));
-	mtdcr(ebccfga,pbesr0); 	printf ("%08x ", mfdcr(ebccfgd));
-	mtdcr(ebccfga,pbesr1); 	printf ("%08x ", mfdcr(ebccfgd));
-	mtdcr(ebccfga,epcr); 	printf ("%08x ", mfdcr(ebccfgd));
+	mtdcr(ebccfga,pbear);	printf ("%08x ", mfdcr(ebccfgd));
+	mtdcr(ebccfga,pbesr0);	printf ("%08x ", mfdcr(ebccfgd));
+	mtdcr(ebccfga,pbesr1);	printf ("%08x ", mfdcr(ebccfgd));
+	mtdcr(ebccfga,epcr);	printf ("%08x ", mfdcr(ebccfgd));
 
 	puts ("\n"
 	    "pb0cr    pb0ap    pb1cr    pb1ap    pb2cr    pb2ap    pb3cr    pb3ap\n");
-	mtdcr(ebccfga,pb0cr); 	printf ("%08x ", mfdcr(ebccfgd));
-	mtdcr(ebccfga,pb0ap); 	printf ("%08x ", mfdcr(ebccfgd));
-	mtdcr(ebccfga,pb1cr); 	printf ("%08x ", mfdcr(ebccfgd));
-	mtdcr(ebccfga,pb1ap); 	printf ("%08x ", mfdcr(ebccfgd));
-	mtdcr(ebccfga,pb2cr); 	printf ("%08x ", mfdcr(ebccfgd));
-	mtdcr(ebccfga,pb2ap); 	printf ("%08x ", mfdcr(ebccfgd));
-	mtdcr(ebccfga,pb3cr); 	printf ("%08x ", mfdcr(ebccfgd));
-	mtdcr(ebccfga,pb3ap); 	printf ("%08x ", mfdcr(ebccfgd));
+	mtdcr(ebccfga,pb0cr);	printf ("%08x ", mfdcr(ebccfgd));
+	mtdcr(ebccfga,pb0ap);	printf ("%08x ", mfdcr(ebccfgd));
+	mtdcr(ebccfga,pb1cr);	printf ("%08x ", mfdcr(ebccfgd));
+	mtdcr(ebccfga,pb1ap);	printf ("%08x ", mfdcr(ebccfgd));
+	mtdcr(ebccfga,pb2cr);	printf ("%08x ", mfdcr(ebccfgd));
+	mtdcr(ebccfga,pb2ap);	printf ("%08x ", mfdcr(ebccfgd));
+	mtdcr(ebccfga,pb3cr);	printf ("%08x ", mfdcr(ebccfgd));
+	mtdcr(ebccfga,pb3ap);	printf ("%08x ", mfdcr(ebccfgd));
 
 	puts ("\n"
 	    "pb4cr    pb4ap\n");
-	mtdcr(ebccfga,pb4cr); 	printf ("%08x ", mfdcr(ebccfgd));
-	mtdcr(ebccfga,pb4ap); 	printf ("%08x ", mfdcr(ebccfgd));
+	mtdcr(ebccfga,pb4cr);	printf ("%08x ", mfdcr(ebccfgd));
+	mtdcr(ebccfga,pb4ap);	printf ("%08x ", mfdcr(ebccfgd));
 
 	puts ("\n\n");
 #elif defined(CONFIG_5xx)
 
-	volatile immap_t     	*immap  = (immap_t *)CFG_IMMR;
+	volatile immap_t	*immap  = (immap_t *)CFG_IMMR;
 	volatile memctl5xx_t	*memctl = &immap->im_memctl;
 	volatile sysconf5xx_t	*sysconf = &immap->im_siu_conf;
 	volatile sit5xx_t	*timers = &immap->im_sit;
@@ -382,7 +382,7 @@ int do_reginfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 
 #if defined(CONFIG_CMD_REGINFO)
 U_BOOT_CMD(
- 	reginfo,	2,	1,	do_reginfo,
+	reginfo,	2,	1,	do_reginfo,
 	"reginfo - print register information\n",
 );
 #endif
diff --git a/common/cmd_scsi.c b/common/cmd_scsi.c
index f49531e96b..69028f3b6b 100644
--- a/common/cmd_scsi.c
+++ b/common/cmd_scsi.c
@@ -393,7 +393,7 @@ int do_scsi (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 			}
 			printf ("Usage:\n%s\n", cmdtp->usage);
 			return 1;
-  	case 3:
+	case 3:
 			if (strncmp(argv[1],"dev",3) == 0) {
 				int dev = (int)simple_strtoul(argv[2], NULL, 10);
 				printf ("\nSCSI device %d: ", dev);
diff --git a/common/cmd_usb.c b/common/cmd_usb.c
index 23413b5103..9be86b874d 100644
--- a/common/cmd_usb.c
+++ b/common/cmd_usb.c
@@ -475,7 +475,7 @@ int do_usb (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 #ifdef CONFIG_USB_STORAGE
 		/* try to recognize storage devices immediately */
 		if (i >= 0)
-	 		usb_stor_curr_dev = usb_stor_scan(1);
+			usb_stor_curr_dev = usb_stor_scan(1);
 #endif
 		return 0;
 	}
diff --git a/common/cmd_vfd.c b/common/cmd_vfd.c
index 29c349dab9..104c310561 100644
--- a/common/cmd_vfd.c
+++ b/common/cmd_vfd.c
@@ -66,10 +66,10 @@ int do_vfd (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 }
 
 U_BOOT_CMD(
- 	vfd,	2,	0,	do_vfd,
- 	"vfd     - load a bitmap to the VFDs on TRAB\n",
- 	"/N\n"
- 	"    - load bitmap N to the VFDs (N is _decimal_ !!!)\n"
+	vfd,	2,	0,	do_vfd,
+	"vfd     - load a bitmap to the VFDs on TRAB\n",
+	"/N\n"
+	"    - load bitmap N to the VFDs (N is _decimal_ !!!)\n"
 	"vfd ADDR\n"
 	"    - load bitmap at address ADDR\n"
 );
diff --git a/common/command.c b/common/command.c
index af2f8cbf7b..861796d9a5 100644
--- a/common/command.c
+++ b/common/command.c
@@ -38,7 +38,7 @@ do_version (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 
 U_BOOT_CMD(
 	version,	1,		1,	do_version,
- 	"version - print monitor version\n",
+	"version - print monitor version\n",
 	NULL
 );
 
@@ -71,8 +71,8 @@ do_echo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 
 U_BOOT_CMD(
 	echo,	CFG_MAXARGS,	1,	do_echo,
- 	"echo    - echo args to console\n",
- 	"[args..]\n"
+	"echo    - echo args to console\n",
+	"[args..]\n"
 	"    - echo args to console; \\c suppresses newline\n"
 );
 
@@ -196,17 +196,15 @@ do_test (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 
 	expr = !expr;
 
-#if 0
-	printf(": returns %d\n", expr);
-#endif
+	debug (": returns %d\n", expr);
 
 	return expr;
 }
 
 U_BOOT_CMD(
 	test,	CFG_MAXARGS,	1,	do_test,
- 	"test    - minimal test like /bin/sh\n",
- 	"[args..]\n"
+	"test    - minimal test like /bin/sh\n",
+	"[args..]\n"
 	"    - test functionality\n"
 );
 
@@ -224,7 +222,7 @@ do_exit (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 
 U_BOOT_CMD(
 	exit,	2,	1,	do_exit,
- 	"exit    - exit script\n",
+	"exit    - exit script\n",
 	"    - exit functionality\n"
 );
 
@@ -317,12 +315,12 @@ int do_help (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 
 U_BOOT_CMD(
 	help,	CFG_MAXARGS,	1,	do_help,
- 	"help    - print online help\n",
- 	"[command ...]\n"
- 	"    - show help information (for 'command')\n"
- 	"'help' prints online help for the monitor commands.\n\n"
- 	"Without arguments, it prints a short usage message for all commands.\n\n"
- 	"To get detailed help information for specific commands you can type\n"
+	"help    - print online help\n",
+	"[command ...]\n"
+	"    - show help information (for 'command')\n"
+	"'help' prints online help for the monitor commands.\n\n"
+	"Without arguments, it prints a short usage message for all commands.\n\n"
+	"To get detailed help information for specific commands you can type\n"
   "'help' with one or more command names as arguments.\n"
 );
 
@@ -330,13 +328,13 @@ U_BOOT_CMD(
 #ifdef  CFG_LONGHELP
 cmd_tbl_t __u_boot_cmd_question_mark Struct_Section = {
 	"?",	CFG_MAXARGS,	1,	do_help,
- 	"?       - alias for 'help'\n",
+	"?       - alias for 'help'\n",
 	NULL
 };
 #else
 cmd_tbl_t __u_boot_cmd_question_mark Struct_Section = {
 	"?",	CFG_MAXARGS,	1,	do_help,
- 	"?       - alias for 'help'\n"
+	"?       - alias for 'help'\n"
 };
 #endif /* CFG_LONGHELP */
 
@@ -498,7 +496,7 @@ static int make_argv(char *s, int argvsz, char *argv[])
 		while ((*s == ' ') || (*s == '\t'))
 			++s;
 
-		if (*s == '\0') 	/* end of s, no more args	*/
+		if (*s == '\0')	/* end of s, no more args	*/
 			break;
 
 		argv[argc++] = s;	/* begin of argument string	*/
diff --git a/common/console.c b/common/console.c
index d8a0cb6c7e..1b095b1ca5 100644
--- a/common/console.c
+++ b/common/console.c
@@ -415,7 +415,7 @@ int console_init_r (void)
 	stdoutname = getenv ("stdout");
 	stderrname = getenv ("stderr");
 
-	if (OVERWRITE_CONSOLE == 0) { 	/* if not overwritten by config switch */
+	if (OVERWRITE_CONSOLE == 0) {	/* if not overwritten by config switch */
 		inputdev  = search_device (DEV_FLAGS_INPUT,  stdinname);
 		outputdev = search_device (DEV_FLAGS_OUTPUT, stdoutname);
 		errdev    = search_device (DEV_FLAGS_OUTPUT, stderrname);
diff --git a/common/env_dataflash.c b/common/env_dataflash.c
index 8a944324f2..294536461d 100644
--- a/common/env_dataflash.c
+++ b/common/env_dataflash.c
@@ -98,7 +98,7 @@ int env_init(void)
 		}
 	}
 
- 	return (0);
+	return (0);
 }
 
 #endif /* CFG_ENV_IS_IN_DATAFLASH */
diff --git a/common/env_nand.c b/common/env_nand.c
index 49742f5bfb..70d05ad15a 100644
--- a/common/env_nand.c
+++ b/common/env_nand.c
@@ -273,7 +273,7 @@ void env_relocate_spec (void)
 
 	total = CFG_ENV_SIZE;
 	ret = nand_read(&nand_info[0], CFG_ENV_OFFSET, &total, (u_char*)env_ptr);
-  	if (ret || total != CFG_ENV_SIZE)
+	if (ret || total != CFG_ENV_SIZE)
 		return use_default();
 
 	if (crc32(0, env_ptr->data, ENV_SIZE) != env_ptr->crc)
diff --git a/common/hush.c b/common/hush.c
index 582635c04c..b43f6185ac 100644
--- a/common/hush.c
+++ b/common/hush.c
@@ -1,4 +1,3 @@
-/* vi: set sw=4 ts=4: */
 /*
  * sh.c -- a prototype Bourne shell grammar parser
  *      Intended to follow the original Thompson and Ritchie
diff --git a/common/lists.c b/common/lists.c
index 3f117b568e..0dc090ab86 100644
--- a/common/lists.c
+++ b/common/lists.c
@@ -2,8 +2,8 @@
 #include <malloc.h>
 #include <lists.h>
 
-#define MAX(a,b) 	(((a)>(b)) ? (a) : (b))
-#define MIN(a,b) 	(((a)<(b)) ? (a) : (b))
+#define MAX(a,b)	(((a)>(b)) ? (a) : (b))
+#define MIN(a,b)	(((a)<(b)) ? (a) : (b))
 #define CAT4CHARS(a,b,c,d)	((a<<24) | (b<<16) | (c<<8) | d)
 
 /* increase list size by 10% every time it is full */
diff --git a/common/usb.c b/common/usb.c
index 2fa5254eb4..a0107dca53 100644
--- a/common/usb.c
+++ b/common/usb.c
@@ -48,6 +48,7 @@
 #include <command.h>
 #include <asm/processor.h>
 #include <linux/ctype.h>
+#include <asm/byteorder.h>
 
 #if defined(CONFIG_CMD_USB)
 
@@ -177,10 +178,10 @@ int usb_control_msg(struct usb_device *dev, unsigned int pipe,
 	/* set setup command */
 	setup_packet.requesttype = requesttype;
 	setup_packet.request = request;
-	setup_packet.value = swap_16(value);
-	setup_packet.index = swap_16(index);
-	setup_packet.length = swap_16(size);
- 	USB_PRINTF("usb_control_msg: request: 0x%X, requesttype: 0x%X\nvalue 0x%X index 0x%X length 0x%X\n",
+	setup_packet.value = cpu_to_le16(value);
+	setup_packet.index = cpu_to_le16(index);
+	setup_packet.length = cpu_to_le16(size);
+	USB_PRINTF("usb_control_msg: request: 0x%X, requesttype: 0x%X, value 0x%X index 0x%X length 0x%X\n",
 		request,requesttype,value,index,size);
 	dev->status=USB_ST_NOT_PROC; /*not yet processed */
 
@@ -300,7 +301,7 @@ int usb_parse_config(struct usb_device *dev, unsigned char *buffer, int cfgno)
 		return -1;
 	}
 	memcpy(&dev->config, buffer, buffer[0]);
-	dev->config.wTotalLength = swap_16(dev->config.wTotalLength);
+	le16_to_cpus(&(dev->config.wTotalLength));
 	dev->config.no_of_if = 0;
 
 	index = dev->config.bLength;
@@ -329,8 +330,7 @@ int usb_parse_config(struct usb_device *dev, unsigned char *buffer, int cfgno)
 				dev->config.if_desc[ifno].no_of_ep++; /* found an endpoint */
 				memcpy(&dev->config.if_desc[ifno].ep_desc[epno],
 					&buffer[index], buffer[index]);
-				dev->config.if_desc[ifno].ep_desc[epno].wMaxPacketSize =
-					swap_16(dev->config.if_desc[ifno].ep_desc[epno].wMaxPacketSize);
+				le16_to_cpus(&(dev->config.if_desc[ifno].ep_desc[epno].wMaxPacketSize));
 				USB_PRINTF("if %d, ep %d\n", ifno, epno);
 				break;
 			default:
@@ -387,7 +387,7 @@ int usb_clear_halt(struct usb_device *dev, int pipe)
 int usb_get_descriptor(struct usb_device *dev, unsigned char type, unsigned char index, void *buf, int size)
 {
 	int res;
- 	res = usb_control_msg(dev, usb_rcvctrlpipe(dev, 0),
+	res = usb_control_msg(dev, usb_rcvctrlpipe(dev, 0),
 			USB_REQ_GET_DESCRIPTOR, USB_DIR_IN,
 			(type << 8) + index, 0,
 			buf, size, USB_CNTL_TIMEOUT);
@@ -399,7 +399,7 @@ int usb_get_descriptor(struct usb_device *dev, unsigned char type, unsigned char
  */
 int usb_get_configuration_no(struct usb_device *dev,unsigned char *buffer,int cfgno)
 {
- 	int result;
+	int result;
 	unsigned int tmp;
 	struct usb_config_descriptor *config;
 
@@ -413,7 +413,7 @@ int usb_get_configuration_no(struct usb_device *dev,unsigned char *buffer,int cf
 			printf("config descriptor too short (expected %i, got %i)\n",8,result);
 		return -1;
 	}
-	tmp=swap_16(config->wTotalLength);
+	tmp = le16_to_cpu(config->wTotalLength);
 
 	if (tmp > USB_BUFSIZ) {
 		USB_PRINTF("usb_get_configuration_no: failed to get descriptor - too long: %d\n",
@@ -816,10 +816,10 @@ int usb_new_device(struct usb_device *dev)
 		return 1;
 	}
 	/* correct le values */
-	dev->descriptor.bcdUSB=swap_16(dev->descriptor.bcdUSB);
-	dev->descriptor.idVendor=swap_16(dev->descriptor.idVendor);
-	dev->descriptor.idProduct=swap_16(dev->descriptor.idProduct);
-	dev->descriptor.bcdDevice=swap_16(dev->descriptor.bcdDevice);
+	le16_to_cpus(&dev->descriptor.bcdUSB);
+	le16_to_cpus(&dev->descriptor.idVendor);
+	le16_to_cpus(&dev->descriptor.idProduct);
+	le16_to_cpus(&dev->descriptor.bcdDevice);
 	/* only support for one config for now */
 	usb_get_configuration_no(dev,&tmpbuf[0],0);
 	usb_parse_config(dev,&tmpbuf[0],0);
@@ -979,8 +979,8 @@ static int hub_port_reset(struct usb_device *dev, int port,
 			USB_HUB_PRINTF("get_port_status failed status %lX\n",dev->status);
 			return -1;
 		}
-		portstatus = swap_16(portsts.wPortStatus);
-		portchange = swap_16(portsts.wPortChange);
+		portstatus = le16_to_cpu(portsts.wPortStatus);
+		portchange = le16_to_cpu(portsts.wPortChange);
 		USB_HUB_PRINTF("portstatus %x, change %x, %s\n", portstatus ,portchange,
 			portstatus&(1<<USB_PORT_FEAT_LOWSPEED) ? "Low Speed" : "High Speed");
 		USB_HUB_PRINTF("STAT_C_CONNECTION = %d STAT_CONNECTION = %d  USB_PORT_STAT_ENABLE %d\n",
@@ -1024,8 +1024,8 @@ void usb_hub_port_connect_change(struct usb_device *dev, int port)
 		return;
 	}
 
-	portstatus = swap_16(portsts.wPortStatus);
-	portchange = swap_16(portsts.wPortChange);
+	portstatus = le16_to_cpu(portsts.wPortStatus);
+	portchange = le16_to_cpu(portsts.wPortChange);
 	USB_HUB_PRINTF("portstatus %x, change %x, %s\n", portstatus, portchange,
 		portstatus&(1<<USB_PORT_FEAT_LOWSPEED) ? "Low Speed" : "High Speed");
 
@@ -1099,7 +1099,7 @@ int usb_hub_configure(struct usb_device *dev)
 	}
 	memcpy((unsigned char *)&hub->desc,buffer,descriptor->bLength);
 	/* adjust 16bit values */
-	hub->desc.wHubCharacteristics=swap_16(descriptor->wHubCharacteristics);
+	hub->desc.wHubCharacteristics = le16_to_cpu(descriptor->wHubCharacteristics);
 	/* set the bitmap */
 	bitmap=(unsigned char *)&hub->desc.DeviceRemovable[0];
 	memset(bitmap,0xff,(USB_MAXCHILDREN+1+7)/8); /* devices not removable by default */
@@ -1161,11 +1161,11 @@ int usb_hub_configure(struct usb_device *dev)
 	}
 	hubsts = (struct usb_hub_status *)buffer;
 	USB_HUB_PRINTF("get_hub_status returned status %X, change %X\n",
-		swap_16(hubsts->wHubStatus),swap_16(hubsts->wHubChange));
+		le16_to_cpu(hubsts->wHubStatus),le16_to_cpu(hubsts->wHubChange));
 	USB_HUB_PRINTF("local power source is %s\n",
-		(swap_16(hubsts->wHubStatus) & HUB_STATUS_LOCAL_POWER) ? "lost (inactive)" : "good");
+		(le16_to_cpu(hubsts->wHubStatus) & HUB_STATUS_LOCAL_POWER) ? "lost (inactive)" : "good");
 	USB_HUB_PRINTF("%sover-current condition exists\n",
-		(swap_16(hubsts->wHubStatus) & HUB_STATUS_OVERCURRENT) ? "" : "no ");
+		(le16_to_cpu(hubsts->wHubStatus) & HUB_STATUS_OVERCURRENT) ? "" : "no ");
 	usb_hub_power_on(hub);
 	for (i = 0; i < dev->maxchild; i++) {
 		struct usb_port_status portsts;
@@ -1175,8 +1175,8 @@ int usb_hub_configure(struct usb_device *dev)
 			USB_HUB_PRINTF("get_port_status failed\n");
 			continue;
 		}
-		portstatus = swap_16(portsts.wPortStatus);
-		portchange = swap_16(portsts.wPortChange);
+		portstatus = le16_to_cpu(portsts.wPortStatus);
+		portchange = le16_to_cpu(portsts.wPortChange);
 		USB_HUB_PRINTF("Port %d Status %X Change %X\n",i+1,portstatus,portchange);
 		if (portchange & USB_PORT_STAT_C_CONNECTION) {
 			USB_HUB_PRINTF("port %d connection change\n", i + 1);
diff --git a/common/usb_kbd.c b/common/usb_kbd.c
index 1703b2339b..1e79208d7c 100644
--- a/common/usb_kbd.c
+++ b/common/usb_kbd.c
@@ -26,6 +26,7 @@
  */
 #include <common.h>
 #include <devices.h>
+#include <asm/byteorder.h>
 
 #ifdef CONFIG_USB_KEYBOARD
 
@@ -238,7 +239,7 @@ static void usb_kbd_setled(struct usb_device *dev)
 		leds|=1;
 	usb_control_msg(dev, usb_sndctrlpipe(dev, 0),
 		USB_REQ_SET_REPORT, USB_TYPE_CLASS | USB_RECIP_INTERFACE,
- 		0x200, iface->bInterfaceNumber,(void *)&leds, 1, 0);
+		0x200, iface->bInterfaceNumber,(void *)&leds, 1, 0);
 
 }
 
@@ -251,7 +252,7 @@ static int usb_kbd_translate(unsigned char scancode,unsigned char modifier,int p
 
 	if(pressed==0) {
 		/* key released */
- 		repeat_delay=0;
+		repeat_delay=0;
 		return 0;
 	}
 	if(pressed==2) {
@@ -475,14 +476,14 @@ static int fetch_item(unsigned char *start,unsigned char *end, struct hid_item *
 					break;
 				case 2:
 					if ((end - start) >= 2) {
-						item->data.u16 = swap_16((unsigned short *)start);
+						item->data.u16 = le16_to_cpu((unsigned short *)start);
 						start+=2;
 						return item->size;
 					}
 				case 3:
 					item->size++;
 					if ((end - start) >= 4) {
-						item->data.u32 = swap_32((unsigned long *)start);
+						item->data.u32 = le32_to_cpu((unsigned long *)start);
 						start+=4;
 						return item->size;
 					}
@@ -705,15 +706,15 @@ static int usb_kbd_get_hid_desc(struct usb_device *dev)
 	}
 	index=head->bLength;
 	config=(struct usb_config_descriptor *)&buffer[0];
-	len=swap_16(config->wTotalLength);
+	len=le16_to_cpu(config->wTotalLength);
 	/* Ok the first entry must be a configuration entry, now process the others */
 	head=(struct usb_descriptor_header *)&buffer[index];
 	while(index+1 < len) {
 		if(head->bDescriptorType==USB_DT_HID) {
 			printf("HID desc found\n");
 			memcpy(&usb_kbd_hid_desc,&buffer[index],buffer[index]);
-			usb_kbd_hid_desc.bcdHID=swap_16(usb_kbd_hid_desc.bcdHID);
-			usb_kbd_hid_desc.wDescriptorLength=swap_16(usb_kbd_hid_desc.wDescriptorLength);
+			le16_to_cpus(&usb_kbd_hid_desc.bcdHID);
+			le16_to_cpus(&usb_kbd_hid_desc.wDescriptorLength);
 			usb_kbd_display_hid(&usb_kbd_hid_desc);
 			len=0;
 			break;
diff --git a/common/usb_storage.c b/common/usb_storage.c
index 7c08f95775..3e113b4084 100644
--- a/common/usb_storage.c
+++ b/common/usb_storage.c
@@ -52,6 +52,7 @@
 
 #include <common.h>
 #include <command.h>
+#include <asm/byteorder.h>
 #include <asm/processor.h>
 
 
@@ -474,9 +475,9 @@ int usb_stor_BBB_comdat(ccb *srb, struct us_data *us)
 	/* always OUT to the ep */
 	pipe = usb_sndbulkpipe(us->pusb_dev, us->ep_out);
 
-	cbw.dCBWSignature = swap_32(CBWSIGNATURE);
-	cbw.dCBWTag = swap_32(CBWTag++);
-	cbw.dCBWDataTransferLength = swap_32(srb->datalen);
+	cbw.dCBWSignature = cpu_to_le32(CBWSIGNATURE);
+	cbw.dCBWTag = cpu_to_le32(CBWTag++);
+	cbw.dCBWDataTransferLength = cpu_to_le32(srb->datalen);
 	cbw.bCBWFlags = (dir_in? CBWFLAGS_IN : CBWFLAGS_OUT);
 	cbw.bCBWLUN = srb->lun;
 	cbw.bCDBLength = srb->cmdlen;
@@ -692,14 +693,14 @@ int usb_stor_BBB_transport(ccb *srb, struct us_data *us)
 	printf("\n");
 #endif
 	/* misuse pipe to get the residue */
-	pipe = swap_32(csw.dCSWDataResidue);
+	pipe = le32_to_cpu(csw.dCSWDataResidue);
 	if (pipe == 0 && srb->datalen != 0 && srb->datalen - data_actlen != 0)
 		pipe = srb->datalen - data_actlen;
-	if (CSWSIGNATURE != swap_32(csw.dCSWSignature)) {
+	if (CSWSIGNATURE != le32_to_cpu(csw.dCSWSignature)) {
 		USB_STOR_PRINTF("!CSWSIGNATURE\n");
 		usb_stor_BBB_reset(us);
 		return USB_STOR_TRANSPORT_FAILED;
-	} else if ((CBWTag - 1) != swap_32(csw.dCSWTag)) {
+	} else if ((CBWTag - 1) != le32_to_cpu(csw.dCSWTag)) {
 		USB_STOR_PRINTF("!Tag\n");
 		usb_stor_BBB_reset(us);
 		return USB_STOR_TRANSPORT_FAILED;
@@ -1222,18 +1223,9 @@ int usb_stor_get_info(struct usb_device *dev,struct us_data *ss,block_dev_desc_t
 	if(cap[0]>(0x200000 * 10)) /* greater than 10 GByte */
 		cap[0]>>=16;
 #endif
-#ifdef LITTLEENDIAN
-	cap[0] = ((unsigned long)(
-		(((unsigned long)(cap[0]) & (unsigned long)0x000000ffUL) << 24) |
-		(((unsigned long)(cap[0]) & (unsigned long)0x0000ff00UL) <<  8) |
-		(((unsigned long)(cap[0]) & (unsigned long)0x00ff0000UL) >>  8) |
-		(((unsigned long)(cap[0]) & (unsigned long)0xff000000UL) >> 24) ));
-	cap[1] = ((unsigned long)(
-		(((unsigned long)(cap[1]) & (unsigned long)0x000000ffUL) << 24) |
-		(((unsigned long)(cap[1]) & (unsigned long)0x0000ff00UL) <<  8) |
-		(((unsigned long)(cap[1]) & (unsigned long)0x00ff0000UL) >>  8) |
-		(((unsigned long)(cap[1]) & (unsigned long)0xff000000UL) >> 24) ));
-#endif
+	cap[0] = cpu_to_be32(cap[0]);
+	cap[1] = cpu_to_be32(cap[1]);
+
 	/* this assumes bigendian! */
 	cap[0] += 1;
 	capacity = &cap[0];
diff --git a/common/virtex2.c b/common/virtex2.c
index 1283ff610d..665a503ec7 100644
--- a/common/virtex2.c
+++ b/common/virtex2.c
@@ -84,7 +84,7 @@
  * an XC2V1000, if anyone can ever get ahold of one.
  */
 #ifndef CFG_FPGA_WAIT_INIT
-#define CFG_FPGA_WAIT_INIT 	CFG_HZ/2	/* 500 ms */
+#define CFG_FPGA_WAIT_INIT	CFG_HZ/2	/* 500 ms */
 #endif
 
 /*
diff --git a/config.mk b/config.mk
index 62fc1d5ddb..b08b7a7593 100644
--- a/config.mk
+++ b/config.mk
@@ -162,7 +162,7 @@ CPPFLAGS += -I$(OBJTREE)/include2 -I$(OBJTREE)/include
 endif
 
 CPPFLAGS += -I$(TOPDIR)/include
-CPPFLAGS += -fno-builtin -ffreestanding -nostdinc 	\
+CPPFLAGS += -fno-builtin -ffreestanding -nostdinc	\
 	-isystem $(gccincdir) -pipe $(PLATFORM_CPPFLAGS)
 
 ifdef BUILD_TAG
diff --git a/cpu/arm1136/mx31/serial.c b/cpu/arm1136/mx31/serial.c
index a829ba7dac..1cad8f9d8c 100644
--- a/cpu/arm1136/mx31/serial.c
+++ b/cpu/arm1136/mx31/serial.c
@@ -77,9 +77,9 @@
 #define  UCR1_UARTCLKEN  (1<<2)	 /* UART clock enabled */
 #define  UCR1_DOZE       (1<<1)	 /* Doze */
 #define  UCR1_UARTEN     (1<<0)	 /* UART enabled */
-#define  UCR2_ESCI     	 (1<<15) /* Escape seq interrupt enable */
-#define  UCR2_IRTS  	 (1<<14) /* Ignore RTS pin */
-#define  UCR2_CTSC  	 (1<<13) /* CTS pin control */
+#define  UCR2_ESCI	 (1<<15) /* Escape seq interrupt enable */
+#define  UCR2_IRTS	 (1<<14) /* Ignore RTS pin */
+#define  UCR2_CTSC	 (1<<13) /* CTS pin control */
 #define  UCR2_CTS        (1<<12) /* Clear to send */
 #define  UCR2_ESCEN      (1<<11) /* Escape enable */
 #define  UCR2_PREN       (1<<8)  /* Parity enable */
@@ -89,8 +89,8 @@
 #define  UCR2_RTSEN      (1<<4)	 /* Request to send interrupt enable */
 #define  UCR2_TXEN       (1<<2)	 /* Transmitter enabled */
 #define  UCR2_RXEN       (1<<1)	 /* Receiver enabled */
-#define  UCR2_SRST 	 (1<<0)	 /* SW reset */
-#define  UCR3_DTREN 	 (1<<13) /* DTR interrupt enable */
+#define  UCR2_SRST	 (1<<0)	 /* SW reset */
+#define  UCR3_DTREN	 (1<<13) /* DTR interrupt enable */
 #define  UCR3_PARERREN   (1<<12) /* Parity enable */
 #define  UCR3_FRAERREN   (1<<11) /* Frame error interrupt enable */
 #define  UCR3_DSR        (1<<10) /* Data set ready */
@@ -100,51 +100,51 @@
 #define  UCR3_RXDSEN	 (1<<6)  /* Receive status interrupt enable */
 #define  UCR3_AIRINTEN   (1<<5)  /* Async IR wake interrupt enable */
 #define  UCR3_AWAKEN	 (1<<4)  /* Async wake interrupt enable */
-#define  UCR3_REF25 	 (1<<3)  /* Ref freq 25 MHz */
-#define  UCR3_REF30 	 (1<<2)  /* Ref Freq 30 MHz */
-#define  UCR3_INVT  	 (1<<1)  /* Inverted Infrared transmission */
-#define  UCR3_BPEN  	 (1<<0)  /* Preset registers enable */
+#define  UCR3_REF25	 (1<<3)  /* Ref freq 25 MHz */
+#define  UCR3_REF30	 (1<<2)  /* Ref Freq 30 MHz */
+#define  UCR3_INVT	 (1<<1)  /* Inverted Infrared transmission */
+#define  UCR3_BPEN	 (1<<0)  /* Preset registers enable */
 #define  UCR4_CTSTL_32   (32<<10) /* CTS trigger level (32 chars) */
-#define  UCR4_INVR  	 (1<<9)  /* Inverted infrared reception */
-#define  UCR4_ENIRI 	 (1<<8)  /* Serial infrared interrupt enable */
-#define  UCR4_WKEN  	 (1<<7)  /* Wake interrupt enable */
-#define  UCR4_REF16 	 (1<<6)  /* Ref freq 16 MHz */
-#define  UCR4_IRSC  	 (1<<5)  /* IR special case */
-#define  UCR4_TCEN  	 (1<<3)  /* Transmit complete interrupt enable */
-#define  UCR4_BKEN  	 (1<<2)  /* Break condition interrupt enable */
-#define  UCR4_OREN  	 (1<<1)  /* Receiver overrun interrupt enable */
-#define  UCR4_DREN  	 (1<<0)  /* Recv data ready interrupt enable */
+#define  UCR4_INVR	 (1<<9)  /* Inverted infrared reception */
+#define  UCR4_ENIRI	 (1<<8)  /* Serial infrared interrupt enable */
+#define  UCR4_WKEN	 (1<<7)  /* Wake interrupt enable */
+#define  UCR4_REF16	 (1<<6)  /* Ref freq 16 MHz */
+#define  UCR4_IRSC	 (1<<5)  /* IR special case */
+#define  UCR4_TCEN	 (1<<3)  /* Transmit complete interrupt enable */
+#define  UCR4_BKEN	 (1<<2)  /* Break condition interrupt enable */
+#define  UCR4_OREN	 (1<<1)  /* Receiver overrun interrupt enable */
+#define  UCR4_DREN	 (1<<0)  /* Recv data ready interrupt enable */
 #define  UFCR_RXTL_SHF   0       /* Receiver trigger level shift */
 #define  UFCR_RFDIV      (7<<7)  /* Reference freq divider mask */
 #define  UFCR_TXTL_SHF   10      /* Transmitter trigger level shift */
 #define  USR1_PARITYERR  (1<<15) /* Parity error interrupt flag */
-#define  USR1_RTSS  	 (1<<14) /* RTS pin status */
-#define  USR1_TRDY  	 (1<<13) /* Transmitter ready interrupt/dma flag */
-#define  USR1_RTSD  	 (1<<12) /* RTS delta */
-#define  USR1_ESCF  	 (1<<11) /* Escape seq interrupt flag */
+#define  USR1_RTSS	 (1<<14) /* RTS pin status */
+#define  USR1_TRDY	 (1<<13) /* Transmitter ready interrupt/dma flag */
+#define  USR1_RTSD	 (1<<12) /* RTS delta */
+#define  USR1_ESCF	 (1<<11) /* Escape seq interrupt flag */
 #define  USR1_FRAMERR    (1<<10) /* Frame error interrupt flag */
 #define  USR1_RRDY       (1<<9)	 /* Receiver ready interrupt/dma flag */
 #define  USR1_TIMEOUT    (1<<7)	 /* Receive timeout interrupt status */
-#define  USR1_RXDS  	 (1<<6)	 /* Receiver idle interrupt flag */
+#define  USR1_RXDS	 (1<<6)	 /* Receiver idle interrupt flag */
 #define  USR1_AIRINT	 (1<<5)	 /* Async IR wake interrupt flag */
-#define  USR1_AWAKE 	 (1<<4)	 /* Aysnc wake interrupt flag */
-#define  USR2_ADET  	 (1<<15) /* Auto baud rate detect complete */
-#define  USR2_TXFE  	 (1<<14) /* Transmit buffer FIFO empty */
-#define  USR2_DTRF  	 (1<<13) /* DTR edge interrupt flag */
-#define  USR2_IDLE  	 (1<<12) /* Idle condition */
-#define  USR2_IRINT 	 (1<<8)	 /* Serial infrared interrupt flag */
-#define  USR2_WAKE  	 (1<<7)	 /* Wake */
-#define  USR2_RTSF  	 (1<<4)	 /* RTS edge interrupt flag */
-#define  USR2_TXDC  	 (1<<3)	 /* Transmitter complete */
-#define  USR2_BRCD  	 (1<<2)	 /* Break condition */
+#define  USR1_AWAKE	 (1<<4)	 /* Aysnc wake interrupt flag */
+#define  USR2_ADET	 (1<<15) /* Auto baud rate detect complete */
+#define  USR2_TXFE	 (1<<14) /* Transmit buffer FIFO empty */
+#define  USR2_DTRF	 (1<<13) /* DTR edge interrupt flag */
+#define  USR2_IDLE	 (1<<12) /* Idle condition */
+#define  USR2_IRINT	 (1<<8)	 /* Serial infrared interrupt flag */
+#define  USR2_WAKE	 (1<<7)	 /* Wake */
+#define  USR2_RTSF	 (1<<4)	 /* RTS edge interrupt flag */
+#define  USR2_TXDC	 (1<<3)	 /* Transmitter complete */
+#define  USR2_BRCD	 (1<<2)	 /* Break condition */
 #define  USR2_ORE        (1<<1)	 /* Overrun error */
 #define  USR2_RDR        (1<<0)	 /* Recv data ready */
 #define  UTS_FRCPERR	 (1<<13) /* Force parity error */
 #define  UTS_LOOP        (1<<12) /* Loop tx and rx */
 #define  UTS_TXEMPTY	 (1<<6)	 /* TxFIFO empty */
 #define  UTS_RXEMPTY	 (1<<5)	 /* RxFIFO empty */
-#define  UTS_TXFULL 	 (1<<4)	 /* TxFIFO full */
-#define  UTS_RXFULL 	 (1<<3)	 /* RxFIFO full */
+#define  UTS_TXFULL	 (1<<4)	 /* TxFIFO full */
+#define  UTS_RXFULL	 (1<<3)	 /* RxFIFO full */
 #define  UTS_SOFTRST	 (1<<0)	 /* Software reset */
 
 DECLARE_GLOBAL_DATA_PTR;
diff --git a/cpu/arm1136/start.S b/cpu/arm1136/start.S
index 56009d0fb3..51b664d935 100644
--- a/cpu/arm1136/start.S
+++ b/cpu/arm1136/start.S
@@ -131,7 +131,7 @@ reset:
 #ifdef CONFIG_OMAP2420H4
        /* Copy vectors to mask ROM indirect addr */
 	adr	r0, _start		/* r0 <- current position of code   */
- 		add     r0, r0, #4				/* skip reset vector			*/
+		add     r0, r0, #4				/* skip reset vector			*/
 	mov	r2, #64			/* r2 <- size to copy  */
 	add	r2, r0, r2		/* r2 <- source end address	    */
 	mov	r1, #SRAM_OFFSET0	  /* build vect addr */
diff --git a/cpu/arm720t/interrupts.c b/cpu/arm720t/interrupts.c
index 475607d95a..9854016d43 100644
--- a/cpu/arm720t/interrupts.c
+++ b/cpu/arm720t/interrupts.c
@@ -182,7 +182,7 @@ int interrupt_init (void)
 	PUT32(T0IR, 0);		/* disable all timer0 interrupts */
 	PUT32(T0TCR, 0);	/* disable timer0 */
 	PUT32(T0PR, CFG_SYS_CLK_FREQ / CFG_HZ);
- 	PUT32(T0MCR, 0);
+	PUT32(T0MCR, 0);
 	PUT32(T0TC, 0);
 	PUT32(T0TCR, 1);	/* enable timer0 */
 
diff --git a/cpu/arm720t/serial_netarm.c b/cpu/arm720t/serial_netarm.c
index bc6bf30b69..a593cbc32f 100644
--- a/cpu/arm720t/serial_netarm.c
+++ b/cpu/arm720t/serial_netarm.c
@@ -44,7 +44,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #endif
 
 /* wait until transmitter is ready for another character */
-#define TXWAITRDY(registers) 							\
+#define TXWAITRDY(registers)							\
 {										\
 	ulong tmo = get_timer(0) + 1 * CFG_HZ;					\
 	while (((registers)->status_a & NETARM_SER_STATA_TX_RDY) == 0 )	{	\
diff --git a/cpu/arm920t/at91rm9200/ether.c b/cpu/arm920t/at91rm9200/ether.c
index c8f56aa52d..f20e070343 100644
--- a/cpu/arm920t/at91rm9200/ether.c
+++ b/cpu/arm920t/at91rm9200/ether.c
@@ -105,7 +105,7 @@ void at91rm9200_EmacDisableMDIO (AT91PS_EMAC p_mac)
  * Arguments:
  *	dev - pointer to struct net_device
  *	RegisterAddress - unsigned char
- * 	pInput - pointer to value read from register
+ *	pInput - pointer to value read from register
  * Return value:
  *	TRUE - if data read successfully
  */
@@ -134,7 +134,7 @@ UCHAR at91rm9200_EmacReadPhy (AT91PS_EMAC p_mac,
  * Arguments:
  *	dev - pointer to struct net_device
  *	RegisterAddress - unsigned char
- * 	pOutput - pointer to value to be written in the register
+ *	pOutput - pointer to value to be written in the register
  * Return value:
  *	TRUE - if data read successfully
  */
diff --git a/cpu/arm920t/imx/serial.c b/cpu/arm920t/imx/serial.c
index 9dbaa569a0..6c56acbfde 100644
--- a/cpu/arm920t/imx/serial.c
+++ b/cpu/arm920t/imx/serial.c
@@ -115,7 +115,7 @@ int serial_init (void)
 	/* Enable FIFOs */
 	base->ucr2 |= UCR2_SRST | UCR2_RXEN | UCR2_TXEN;
 
-  	/* Clear status flags */
+	/* Clear status flags */
 	base->usr2 |= USR2_ADET  |
 	          USR2_DTRF  |
 	          USR2_IDLE  |
@@ -126,7 +126,7 @@ int serial_init (void)
 	          USR2_ORE   |
 	          USR2_RDR;
 
-  	/* Clear status flags */
+	/* Clear status flags */
 	base->usr1 |= USR1_PARITYERR |
 	          USR1_RTSD      |
 	          USR1_ESCF      |
diff --git a/cpu/arm920t/s3c24x0/usb_ohci.c b/cpu/arm920t/s3c24x0/usb_ohci.c
index 96e43d0fa6..b57c2d8950 100644
--- a/cpu/arm920t/s3c24x0/usb_ohci.c
+++ b/cpu/arm920t/s3c24x0/usb_ohci.c
@@ -971,13 +971,13 @@ static unsigned char root_hub_str_index1[] =
 
 /*-------------------------------------------------------------------------*/
 
-#define OK(x) 			len = (x); break
+#define OK(x)			len = (x); break
 #ifdef DEBUG
-#define WR_RH_STAT(x) 		{info("WR:status %#8x", (x));writel((x), &gohci.regs->roothub.status);}
-#define WR_RH_PORTSTAT(x) 	{info("WR:portstatus[%d] %#8x", wIndex-1, (x));writel((x), &gohci.regs->roothub.portstatus[wIndex-1]);}
+#define WR_RH_STAT(x)		{info("WR:status %#8x", (x));writel((x), &gohci.regs->roothub.status);}
+#define WR_RH_PORTSTAT(x)	{info("WR:portstatus[%d] %#8x", wIndex-1, (x));writel((x), &gohci.regs->roothub.portstatus[wIndex-1]);}
 #else
-#define WR_RH_STAT(x) 		writel((x), &gohci.regs->roothub.status)
-#define WR_RH_PORTSTAT(x) 	writel((x), &gohci.regs->roothub.portstatus[wIndex-1])
+#define WR_RH_STAT(x)		writel((x), &gohci.regs->roothub.status)
+#define WR_RH_PORTSTAT(x)	writel((x), &gohci.regs->roothub.portstatus[wIndex-1])
 #endif
 #define RD_RH_STAT		roothub_status(&gohci)
 #define RD_RH_PORTSTAT		roothub_portstatus(&gohci,wIndex-1)
@@ -1163,7 +1163,7 @@ pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe));
 		    data_buf [1] = 0x29;
 		    data_buf [2] = temp & RH_A_NDP;
 		    data_buf [3] = 0;
-		    if (temp & RH_A_PSM) 	/* per-port power switching? */
+		    if (temp & RH_A_PSM)	/* per-port power switching? */
 			data_buf [3] |= 0x1;
 		    if (temp & RH_A_NOCP)	/* no overcurrent reporting? */
 			data_buf [3] |= 0x10;
@@ -1188,9 +1188,9 @@ pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe));
 		    OK (len);
 		}
 
-	case RH_GET_CONFIGURATION: 	*(__u8 *) data_buf = 0x01; OK (1);
+	case RH_GET_CONFIGURATION:	*(__u8 *) data_buf = 0x01; OK (1);
 
-	case RH_SET_CONFIGURATION: 	WR_RH_STAT (0x10000); OK (0);
+	case RH_SET_CONFIGURATION:	WR_RH_STAT (0x10000); OK (0);
 
 	default:
 		dbg ("unsupported root hub command");
diff --git a/cpu/arm920t/s3c24x0/usb_ohci.h b/cpu/arm920t/s3c24x0/usb_ohci.h
index 5e9a0fdfc4..3af5fca804 100644
--- a/cpu/arm920t/s3c24x0/usb_ohci.h
+++ b/cpu/arm920t/s3c24x0/usb_ohci.h
@@ -11,30 +11,30 @@
 static int cc_to_error[16] = {
 
 /* mapping of the OHCI CC status to error codes */
-	/* No  Error  */               0,
-	/* CRC Error  */               USB_ST_CRC_ERR,
-	/* Bit Stuff  */               USB_ST_BIT_ERR,
-	/* Data Togg  */               USB_ST_CRC_ERR,
-	/* Stall      */               USB_ST_STALLED,
-	/* DevNotResp */               -1,
-	/* PIDCheck   */               USB_ST_BIT_ERR,
-	/* UnExpPID   */               USB_ST_BIT_ERR,
-	/* DataOver   */               USB_ST_BUF_ERR,
-	/* DataUnder  */               USB_ST_BUF_ERR,
-	/* reservd    */               -1,
-	/* reservd    */               -1,
-	/* BufferOver */               USB_ST_BUF_ERR,
-	/* BuffUnder  */               USB_ST_BUF_ERR,
-	/* Not Access */               -1,
-	/* Not Access */               -1
+	/* No  Error  */	       0,
+	/* CRC Error  */	       USB_ST_CRC_ERR,
+	/* Bit Stuff  */	       USB_ST_BIT_ERR,
+	/* Data Togg  */	       USB_ST_CRC_ERR,
+	/* Stall      */	       USB_ST_STALLED,
+	/* DevNotResp */	       -1,
+	/* PIDCheck   */	       USB_ST_BIT_ERR,
+	/* UnExpPID   */	       USB_ST_BIT_ERR,
+	/* DataOver   */	       USB_ST_BUF_ERR,
+	/* DataUnder  */	       USB_ST_BUF_ERR,
+	/* reservd    */	       -1,
+	/* reservd    */	       -1,
+	/* BufferOver */	       USB_ST_BUF_ERR,
+	/* BuffUnder  */	       USB_ST_BUF_ERR,
+	/* Not Access */	       -1,
+	/* Not Access */	       -1
 };
 
 /* ED States */
-#define ED_NEW 		0x00
-#define ED_UNLINK 	0x01
+#define ED_NEW		0x00
+#define ED_UNLINK	0x01
 #define ED_OPER		0x02
 #define ED_DEL		0x04
-#define ED_URB_DEL  	0x08
+#define ED_URB_DEL	0x08
 
 /* usb_ohci_ed */
 struct ed {
@@ -60,53 +60,53 @@ typedef struct ed ed_t;
 
 
 /* TD info field */
-#define TD_CC       0xf0000000
-#define TD_CC_GET(td_p) ((td_p >>28) & 0x0f)
-#define TD_CC_SET(td_p, cc) (td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28)
-#define TD_EC       0x0C000000
-#define TD_T        0x03000000
-#define TD_T_DATA0  0x02000000
-#define TD_T_DATA1  0x03000000
-#define TD_T_TOGGLE 0x00000000
-#define TD_R        0x00040000
-#define TD_DI       0x00E00000
-#define TD_DI_SET(X) (((X) & 0x07)<< 21)
-#define TD_DP       0x00180000
-#define TD_DP_SETUP 0x00000000
-#define TD_DP_IN    0x00100000
-#define TD_DP_OUT   0x00080000
-
-#define TD_ISO	    0x00010000
-#define TD_DEL      0x00020000
+#define TD_CC			0xf0000000
+#define TD_CC_GET(td_p)		((td_p >>28) & 0x0f)
+#define TD_CC_SET(td_p, cc)	(td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28)
+#define TD_EC			0x0C000000
+#define TD_T			0x03000000
+#define TD_T_DATA0		0x02000000
+#define TD_T_DATA1		0x03000000
+#define TD_T_TOGGLE		0x00000000
+#define TD_R			0x00040000
+#define TD_DI			0x00E00000
+#define TD_DI_SET(X)		(((X) & 0x07)<< 21)
+#define TD_DP			0x00180000
+#define TD_DP_SETUP		0x00000000
+#define TD_DP_IN		0x00100000
+#define TD_DP_OUT		0x00080000
+
+#define TD_ISO			0x00010000
+#define TD_DEL			0x00020000
 
 /* CC Codes */
-#define TD_CC_NOERROR      0x00
-#define TD_CC_CRC          0x01
-#define TD_CC_BITSTUFFING  0x02
-#define TD_CC_DATATOGGLEM  0x03
-#define TD_CC_STALL        0x04
-#define TD_DEVNOTRESP      0x05
-#define TD_PIDCHECKFAIL    0x06
-#define TD_UNEXPECTEDPID   0x07
-#define TD_DATAOVERRUN     0x08
-#define TD_DATAUNDERRUN    0x09
-#define TD_BUFFEROVERRUN   0x0C
-#define TD_BUFFERUNDERRUN  0x0D
-#define TD_NOTACCESSED     0x0F
+#define TD_CC_NOERROR		0x00
+#define TD_CC_CRC		0x01
+#define TD_CC_BITSTUFFING	0x02
+#define TD_CC_DATATOGGLEM	0x03
+#define TD_CC_STALL		0x04
+#define TD_DEVNOTRESP		0x05
+#define TD_PIDCHECKFAIL	0x06
+#define TD_UNEXPECTEDPID	0x07
+#define TD_DATAOVERRUN		0x08
+#define TD_DATAUNDERRUN	0x09
+#define TD_BUFFEROVERRUN	0x0C
+#define TD_BUFFERUNDERRUN	0x0D
+#define TD_NOTACCESSED		0x0F
 
 
 #define MAXPSW 1
 
 struct td {
 	__u32 hwINFO;
-  	__u32 hwCBP;		/* Current Buffer Pointer */
-  	__u32 hwNextTD;		/* Next TD Pointer */
-  	__u32 hwBE;		/* Memory Buffer End Pointer */
-
-  	__u8 unused;
-  	__u8 index;
-  	struct ed *ed;
-  	struct td *next_dl_td;
+	__u32 hwCBP;		/* Current Buffer Pointer */
+	__u32 hwNextTD;		/* Next TD Pointer */
+	__u32 hwBE;		/* Memory Buffer End Pointer */
+
+	__u8 unused;
+	__u8 index;
+	struct ed *ed;
+	struct td *next_dl_td;
 	struct usb_device *usb_dev;
 	int transfer_len;
 	__u32 data;
@@ -129,7 +129,7 @@ struct ohci_hcca {
 	__u16	frame_no;		/* current frame number */
 	__u16	pad1;			/* set to 0 on each frame_no change */
 	__u32	done_head;		/* info returned for an interrupt */
-	u8		reserved_for_hc[116];
+	u8	reserved_for_hc[116];
 } __attribute((aligned(256)));
 
 
@@ -140,7 +140,7 @@ struct ohci_hcca {
 
 /*
  * This is the structure of the OHCI controller's memory mapped I/O
- * region.  This is Memory Mapped I/O.  You must use the readl() and
+ * region.  This is Memory Mapped I/O.	You must use the readl() and
  * writel() macros defined in asm/io.h to access these!!
  */
 struct ohci_regs {
@@ -200,10 +200,10 @@ struct ohci_regs {
  * HcCommandStatus (cmdstatus) register masks
  */
 #define OHCI_HCR	(1 << 0)	/* host controller reset */
-#define OHCI_CLF  	(1 << 1)	/* control list filled */
-#define OHCI_BLF  	(1 << 2)	/* bulk list filled */
-#define OHCI_OCR  	(1 << 3)	/* ownership change request */
-#define OHCI_SOC  	(3 << 16)	/* scheduling overrun count */
+#define OHCI_CLF	(1 << 1)	/* control list filled */
+#define OHCI_BLF	(1 << 2)	/* bulk list filled */
+#define OHCI_OCR	(1 << 3)	/* ownership change request */
+#define OHCI_SOC	(3 << 16)	/* scheduling overrun count */
 
 /*
  * masks used with interrupt registers:
@@ -234,93 +234,93 @@ struct virt_root_hub {
 /* USB HUB CONSTANTS (not OHCI-specific; see hub.h) */
 
 /* destination of request */
-#define RH_INTERFACE               0x01
-#define RH_ENDPOINT                0x02
-#define RH_OTHER                   0x03
+#define RH_INTERFACE		0x01
+#define RH_ENDPOINT		0x02
+#define RH_OTHER		0x03
 
-#define RH_CLASS                   0x20
-#define RH_VENDOR                  0x40
+#define RH_CLASS		0x20
+#define RH_VENDOR		0x40
 
 /* Requests: bRequest << 8 | bmRequestType */
-#define RH_GET_STATUS           0x0080
-#define RH_CLEAR_FEATURE        0x0100
-#define RH_SET_FEATURE          0x0300
+#define RH_GET_STATUS		0x0080
+#define RH_CLEAR_FEATURE	0x0100
+#define RH_SET_FEATURE		0x0300
 #define RH_SET_ADDRESS		0x0500
 #define RH_GET_DESCRIPTOR	0x0680
-#define RH_SET_DESCRIPTOR       0x0700
+#define RH_SET_DESCRIPTOR	0x0700
 #define RH_GET_CONFIGURATION	0x0880
 #define RH_SET_CONFIGURATION	0x0900
-#define RH_GET_STATE            0x0280
-#define RH_GET_INTERFACE        0x0A80
-#define RH_SET_INTERFACE        0x0B00
-#define RH_SYNC_FRAME           0x0C80
+#define RH_GET_STATE		0x0280
+#define RH_GET_INTERFACE	0x0A80
+#define RH_SET_INTERFACE	0x0B00
+#define RH_SYNC_FRAME		0x0C80
 /* Our Vendor Specific Request */
-#define RH_SET_EP               0x2000
+#define RH_SET_EP		0x2000
 
 
 /* Hub port features */
-#define RH_PORT_CONNECTION         0x00
-#define RH_PORT_ENABLE             0x01
-#define RH_PORT_SUSPEND            0x02
-#define RH_PORT_OVER_CURRENT       0x03
-#define RH_PORT_RESET              0x04
-#define RH_PORT_POWER              0x08
-#define RH_PORT_LOW_SPEED          0x09
-
-#define RH_C_PORT_CONNECTION       0x10
-#define RH_C_PORT_ENABLE           0x11
-#define RH_C_PORT_SUSPEND          0x12
-#define RH_C_PORT_OVER_CURRENT     0x13
-#define RH_C_PORT_RESET            0x14
+#define RH_PORT_CONNECTION	0x00
+#define RH_PORT_ENABLE		0x01
+#define RH_PORT_SUSPEND		0x02
+#define RH_PORT_OVER_CURRENT	0x03
+#define RH_PORT_RESET		0x04
+#define RH_PORT_POWER		0x08
+#define RH_PORT_LOW_SPEED	0x09
+
+#define RH_C_PORT_CONNECTION	0x10
+#define RH_C_PORT_ENABLE	0x11
+#define RH_C_PORT_SUSPEND	0x12
+#define RH_C_PORT_OVER_CURRENT	0x13
+#define RH_C_PORT_RESET		0x14
 
 /* Hub features */
-#define RH_C_HUB_LOCAL_POWER       0x00
-#define RH_C_HUB_OVER_CURRENT      0x01
+#define RH_C_HUB_LOCAL_POWER	0x00
+#define RH_C_HUB_OVER_CURRENT	0x01
 
-#define RH_DEVICE_REMOTE_WAKEUP    0x00
-#define RH_ENDPOINT_STALL          0x01
+#define RH_DEVICE_REMOTE_WAKEUP 0x00
+#define RH_ENDPOINT_STALL	0x01
 
-#define RH_ACK                     0x01
-#define RH_REQ_ERR                 -1
-#define RH_NACK                    0x00
+#define RH_ACK			0x01
+#define RH_REQ_ERR		-1
+#define RH_NACK			0x00
 
 
 /* OHCI ROOT HUB REGISTER MASKS */
 
 /* roothub.portstatus [i] bits */
-#define RH_PS_CCS            0x00000001   	/* current connect status */
-#define RH_PS_PES            0x00000002   	/* port enable status*/
-#define RH_PS_PSS            0x00000004   	/* port suspend status */
-#define RH_PS_POCI           0x00000008   	/* port over current indicator */
-#define RH_PS_PRS            0x00000010  	/* port reset status */
-#define RH_PS_PPS            0x00000100   	/* port power status */
-#define RH_PS_LSDA           0x00000200    	/* low speed device attached */
-#define RH_PS_CSC            0x00010000 	/* connect status change */
-#define RH_PS_PESC           0x00020000   	/* port enable status change */
-#define RH_PS_PSSC           0x00040000    	/* port suspend status change */
-#define RH_PS_OCIC           0x00080000    	/* over current indicator change */
-#define RH_PS_PRSC           0x00100000   	/* port reset status change */
+#define RH_PS_CCS		0x00000001	/* current connect status */
+#define RH_PS_PES		0x00000002	/* port enable status*/
+#define RH_PS_PSS		0x00000004	/* port suspend status */
+#define RH_PS_POCI		0x00000008	/* port over current indicator */
+#define RH_PS_PRS		0x00000010	/* port reset status */
+#define RH_PS_PPS		0x00000100	/* port power status */
+#define RH_PS_LSDA		0x00000200	/* low speed device attached */
+#define RH_PS_CSC		0x00010000	/* connect status change */
+#define RH_PS_PESC		0x00020000	/* port enable status change */
+#define RH_PS_PSSC		0x00040000	/* port suspend status change */
+#define RH_PS_OCIC		0x00080000	/* over current indicator change */
+#define RH_PS_PRSC		0x00100000	/* port reset status change */
 
 /* roothub.status bits */
-#define RH_HS_LPS	     0x00000001		/* local power status */
-#define RH_HS_OCI	     0x00000002		/* over current indicator */
-#define RH_HS_DRWE	     0x00008000		/* device remote wakeup enable */
-#define RH_HS_LPSC	     0x00010000		/* local power status change */
-#define RH_HS_OCIC	     0x00020000		/* over current indicator change */
-#define RH_HS_CRWE	     0x80000000		/* clear remote wakeup enable */
+#define RH_HS_LPS		0x00000001	/* local power status */
+#define RH_HS_OCI		0x00000002	/* over current indicator */
+#define RH_HS_DRWE		0x00008000	/* device remote wakeup enable */
+#define RH_HS_LPSC		0x00010000	/* local power status change */
+#define RH_HS_OCIC		0x00020000	/* over current indicator change */
+#define RH_HS_CRWE		0x80000000	/* clear remote wakeup enable */
 
 /* roothub.b masks */
-#define RH_B_DR		0x0000ffff		/* device removable flags */
-#define RH_B_PPCM	0xffff0000		/* port power control mask */
+#define RH_B_DR			0x0000ffff	/* device removable flags */
+#define RH_B_PPCM		0xffff0000	/* port power control mask */
 
 /* roothub.a masks */
-#define	RH_A_NDP	(0xff << 0)		/* number of downstream ports */
-#define	RH_A_PSM	(1 << 8)		/* power switching mode */
-#define	RH_A_NPS	(1 << 9)		/* no power switching */
-#define	RH_A_DT		(1 << 10)		/* device type (mbz) */
-#define	RH_A_OCPM	(1 << 11)		/* over current protection mode */
-#define	RH_A_NOCP	(1 << 12)		/* no over current protection */
-#define	RH_A_POTPGT	(0xff << 24)		/* power on to power good time */
+#define	RH_A_NDP		(0xff << 0)	/* number of downstream ports */
+#define	RH_A_PSM		(1 << 8)	/* power switching mode */
+#define	RH_A_NPS		(1 << 9)	/* no power switching */
+#define	RH_A_DT			(1 << 10)	/* device type (mbz) */
+#define	RH_A_OCPM		(1 << 11)	/* over current protection mode */
+#define	RH_A_NOCP		(1 << 12)	/* no over current protection */
+#define	RH_A_POTPGT		(0xff << 24)	/* power on to power good time */
 
 /* urb */
 #define N_URB_TD 48
@@ -345,39 +345,39 @@ typedef struct
 
 
 typedef struct ohci {
-	struct ohci_hcca *hcca;		/* hcca */
-	/*dma_addr_t hcca_dma;*/
+	struct ohci_hcca *hcca;	/* hcca */
+	/*dma_addr_t hcca_dma; */
 
 	int irq;
-	int disabled;			/* e.g. got a UE, we're hung */
+	int disabled;		/* e.g. got a UE, we're hung */
 	int sleeping;
-	unsigned long flags;		/* for HC bugs */
+	unsigned long flags;	/* for HC bugs */
 
 	struct ohci_regs *regs;	/* OHCI controller's memory */
 
-	ed_t *ed_rm_list[2];     /* lists of all endpoints to be removed */
-	ed_t *ed_bulktail;       /* last endpoint of bulk list */
-	ed_t *ed_controltail;    /* last endpoint of control list */
+	ed_t *ed_rm_list[2];	/* lists of all endpoints to be removed */
+	ed_t *ed_bulktail;	/* last endpoint of bulk list */
+	ed_t *ed_controltail;	/* last endpoint of control list */
 	int intrstatus;
-	__u32 hc_control;		/* copy of the hc control reg */
+	__u32 hc_control;	/* copy of the hc control reg */
 	struct usb_device *dev[32];
 	struct virt_root_hub rh;
 
-	const char	*slot_name;
+	const char *slot_name;
 } ohci_t;
 
 #define NUM_EDS 8		/* num of preallocated endpoint descriptors */
 
 struct ohci_device {
-	ed_t 	ed[NUM_EDS];
+	ed_t ed[NUM_EDS];
 	int ed_cnt;
 };
 
 /* hcd */
 /* endpoint */
-static int ep_link(ohci_t * ohci, ed_t * ed);
-static int ep_unlink(ohci_t * ohci, ed_t * ed);
-static ed_t * ep_add_ed(struct usb_device * usb_dev, unsigned long pipe);
+static int ep_link (ohci_t * ohci, ed_t * ed);
+static int ep_unlink (ohci_t * ohci, ed_t * ed);
+static ed_t *ep_add_ed (struct usb_device *usb_dev, unsigned long pipe);
 
 /*-------------------------------------------------------------------------*/
 
@@ -385,22 +385,20 @@ static ed_t * ep_add_ed(struct usb_device * usb_dev, unsigned long pipe);
 #define NUM_TD 64
 
 /* +1 so we can align the storage */
-td_t gtd[NUM_TD+1];
+td_t gtd[NUM_TD + 1];
+
 /* pointers to aligned storage */
 td_t *ptd;
 
 /* TDs ... */
-static inline struct td *
-td_alloc (struct usb_device *usb_dev)
+static inline struct td *td_alloc (struct usb_device *usb_dev)
 {
 	int i;
-	struct td	*td;
+	struct td *td;
 
 	td = NULL;
-	for (i = 0; i < NUM_TD; i++)
-	{
-		if (ptd[i].usb_dev == NULL)
-		{
+	for (i = 0; i < NUM_TD; i++) {
+		if (ptd[i].usb_dev == NULL) {
 			td = &ptd[i];
 			td->usb_dev = usb_dev;
 			break;
@@ -410,8 +408,7 @@ td_alloc (struct usb_device *usb_dev)
 	return td;
 }
 
-static inline void
-ed_free (struct ed *ed)
+static inline void ed_free (struct ed *ed)
 {
 	ed->usb_dev = NULL;
 }
diff --git a/cpu/arm920t/start.S b/cpu/arm920t/start.S
index acc00ad970..62231f8566 100644
--- a/cpu/arm920t/start.S
+++ b/cpu/arm920t/start.S
@@ -212,7 +212,7 @@ stack_setup:
 clear_bss:
 	ldr	r0, _bss_start		/* find start of bss segment        */
 	ldr	r1, _bss_end		/* stop here                        */
-	mov 	r2, #0x00000000		/* clear                            */
+	mov	r2, #0x00000000		/* clear                            */
 
 clbss_l:str	r2, [r0]		/* clear loop...                    */
 	add	r0, r0, #4
@@ -377,31 +377,31 @@ cpu_init_crit:
 undefined_instruction:
 	get_bad_stack
 	bad_save_user_regs
-	bl 	do_undefined_instruction
+	bl	do_undefined_instruction
 
 	.align	5
 software_interrupt:
 	get_bad_stack
 	bad_save_user_regs
-	bl 	do_software_interrupt
+	bl	do_software_interrupt
 
 	.align	5
 prefetch_abort:
 	get_bad_stack
 	bad_save_user_regs
-	bl 	do_prefetch_abort
+	bl	do_prefetch_abort
 
 	.align	5
 data_abort:
 	get_bad_stack
 	bad_save_user_regs
-	bl 	do_data_abort
+	bl	do_data_abort
 
 	.align	5
 not_used:
 	get_bad_stack
 	bad_save_user_regs
-	bl 	do_not_used
+	bl	do_not_used
 
 #ifdef CONFIG_USE_IRQ
 
@@ -409,7 +409,7 @@ not_used:
 irq:
 	get_irq_stack
 	irq_save_user_regs
-	bl 	do_irq
+	bl	do_irq
 	irq_restore_user_regs
 
 	.align	5
@@ -417,7 +417,7 @@ fiq:
 	get_fiq_stack
 	/* someone ought to write a more effiction fiq_save_user_regs */
 	irq_save_user_regs
-	bl 	do_fiq
+	bl	do_fiq
 	irq_restore_user_regs
 
 #else
@@ -426,12 +426,12 @@ fiq:
 irq:
 	get_bad_stack
 	bad_save_user_regs
-	bl 	do_irq
+	bl	do_irq
 
 	.align	5
 fiq:
 	get_bad_stack
 	bad_save_user_regs
-	bl 	do_fiq
+	bl	do_fiq
 
 #endif
diff --git a/cpu/arm925t/start.S b/cpu/arm925t/start.S
index acd77426d3..5ddda54bdd 100644
--- a/cpu/arm925t/start.S
+++ b/cpu/arm925t/start.S
@@ -9,7 +9,7 @@
  *  Copyright (c) 2002	Alex Züpke <azu@sysgo.de>
  *  Copyright (c) 2002	Gary Jennejohn <gj@denx.de>
  *  Copyright (c) 2003	Richard Woodruff <r-woodruff2@ti.com>
- *  Copyright (c) 2003	Kshitij 	 <kshitij@ti.com>
+ *  Copyright (c) 2003	Kshitij	 <kshitij@ti.com>
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -200,7 +200,7 @@ stack_setup:
 clear_bss:
 	ldr	r0, _bss_start		/* find start of bss segment        */
 	ldr	r1, _bss_end		/* stop here                        */
-	mov 	r2, #0x00000000		/* clear                            */
+	mov	r2, #0x00000000		/* clear                            */
 
 clbss_l:str	r2, [r0]		/* clear loop...                    */
 	add	r0, r0, #4
@@ -357,31 +357,31 @@ cpu_init_crit:
 undefined_instruction:
 	get_bad_stack
 	bad_save_user_regs
-	bl 	do_undefined_instruction
+	bl	do_undefined_instruction
 
 	.align	5
 software_interrupt:
 	get_bad_stack
 	bad_save_user_regs
-	bl 	do_software_interrupt
+	bl	do_software_interrupt
 
 	.align	5
 prefetch_abort:
 	get_bad_stack
 	bad_save_user_regs
-	bl 	do_prefetch_abort
+	bl	do_prefetch_abort
 
 	.align	5
 data_abort:
 	get_bad_stack
 	bad_save_user_regs
-	bl 	do_data_abort
+	bl	do_data_abort
 
 	.align	5
 not_used:
 	get_bad_stack
 	bad_save_user_regs
-	bl 	do_not_used
+	bl	do_not_used
 
 #ifdef CONFIG_USE_IRQ
 
@@ -389,7 +389,7 @@ not_used:
 irq:
 	get_irq_stack
 	irq_save_user_regs
-	bl 	do_irq
+	bl	do_irq
 	irq_restore_user_regs
 
 	.align	5
@@ -397,7 +397,7 @@ fiq:
 	get_fiq_stack
 	/* someone ought to write a more effiction fiq_save_user_regs */
 	irq_save_user_regs
-	bl 	do_fiq
+	bl	do_fiq
 	irq_restore_user_regs
 
 #else
@@ -406,13 +406,13 @@ fiq:
 irq:
 	get_bad_stack
 	bad_save_user_regs
-	bl 	do_irq
+	bl	do_irq
 
 	.align	5
 fiq:
 	get_bad_stack
 	bad_save_user_regs
-	bl 	do_fiq
+	bl	do_fiq
 
 #endif
 
diff --git a/cpu/arm926ejs/davinci/dp83848.c b/cpu/arm926ejs/davinci/dp83848.c
index 5719845b34..2aa9ef128b 100644
--- a/cpu/arm926ejs/davinci/dp83848.c
+++ b/cpu/arm926ejs/davinci/dp83848.c
@@ -125,7 +125,7 @@ int dp83848_auto_negotiate(int phy_addr)
 	 * 10BaseTFD and HD, IEEE 802.3
 	 */
 	tmp = DP83848_NP | DP83848_TX_FDX | DP83848_TX_HDX |
-	 	DP83848_10_FDX | DP83848_10_HDX | DP83848_AN_IEEE_802_3;
+		DP83848_10_FDX | DP83848_10_HDX | DP83848_AN_IEEE_802_3;
 	dm644x_eth_phy_write(phy_addr, DP83848_ANA_REG, tmp);
 
 
diff --git a/cpu/arm926ejs/davinci/ether.c b/cpu/arm926ejs/davinci/ether.c
index 766bc7d66c..d286ec0c33 100644
--- a/cpu/arm926ejs/davinci/ether.c
+++ b/cpu/arm926ejs/davinci/ether.c
@@ -489,7 +489,7 @@ static void dm644x_eth_ch_teardown(int ch)
 			 dly--;
 			 udelay(1);
 			 if (dly == 0)
-			 	break;
+				break;
 		}
 		adap_emac->TX0CP = cnt;
 		adap_emac->TX0HDP = 0;
@@ -504,7 +504,7 @@ static void dm644x_eth_ch_teardown(int ch)
 			 dly--;
 			 udelay(1);
 			 if (dly == 0)
-			 	break;
+				break;
 		}
 		adap_emac->RX0CP = cnt;
 		adap_emac->RX0HDP = 0;
@@ -535,83 +535,85 @@ static int tx_send_loop = 0;
  * This function sends a single packet on the network and returns
  * positive number (number of bytes transmitted) or negative for error
  */
-static int dm644x_eth_send_packet(volatile void *packet, int length)
+static int dm644x_eth_send_packet (volatile void *packet, int length)
 {
 	int ret_status = -1;
+
 	tx_send_loop = 0;
 
 	/* Return error if no link */
-	if (!phy.get_link_speed(active_phy_addr))
-	{
-		printf("WARN: emac_send_packet: No link\n");
+	if (!phy.get_link_speed (active_phy_addr)) {
+		printf ("WARN: emac_send_packet: No link\n");
 		return (ret_status);
 	}
 
 	/* Check packet size and if < EMAC_MIN_ETHERNET_PKT_SIZE, pad it up */
-	if (length < EMAC_MIN_ETHERNET_PKT_SIZE)
-	{
+	if (length < EMAC_MIN_ETHERNET_PKT_SIZE) {
 		length = EMAC_MIN_ETHERNET_PKT_SIZE;
 	}
 
 	/* Populate the TX descriptor */
-	emac_tx_desc->next         = 0;
-	emac_tx_desc->buffer       = (u_int8_t *)packet;
+	emac_tx_desc->next = 0;
+	emac_tx_desc->buffer = (u_int8_t *) packet;
 	emac_tx_desc->buff_off_len = (length & 0xffff);
 	emac_tx_desc->pkt_flag_len = ((length & 0xffff) |
-			EMAC_CPPI_SOP_BIT |
-			EMAC_CPPI_OWNERSHIP_BIT |
-			EMAC_CPPI_EOP_BIT);
+				      EMAC_CPPI_SOP_BIT |
+				      EMAC_CPPI_OWNERSHIP_BIT |
+				      EMAC_CPPI_EOP_BIT);
 	/* Send the packet */
-	adap_emac->TX0HDP = (unsigned int)emac_tx_desc;
+	adap_emac->TX0HDP = (unsigned int) emac_tx_desc;
 
 	/* Wait for packet to complete or link down */
 	while (1) {
-	        if (!phy.get_link_speed(active_phy_addr)) {
-	        	dm644x_eth_ch_teardown(EMAC_CH_TX);
-	        	return (ret_status);
-	        }
-	        if (adap_emac->TXINTSTATRAW & 0x01) {
-	        	ret_status = length;
-	        	break;
+		if (!phy.get_link_speed (active_phy_addr)) {
+			dm644x_eth_ch_teardown (EMAC_CH_TX);
+			return (ret_status);
+		}
+		if (adap_emac->TXINTSTATRAW & 0x01) {
+			ret_status = length;
+			break;
 		}
-	        tx_send_loop++;
+		tx_send_loop++;
 	}
 
-	return(ret_status);
+	return (ret_status);
 }
 
 /*
  * This function handles receipt of a packet from the network
  */
-static int dm644x_eth_rcv_packet(void)
+static int dm644x_eth_rcv_packet (void)
 {
-	volatile emac_desc	*rx_curr_desc;
-	volatile emac_desc	*curr_desc;
-	volatile emac_desc	*tail_desc;
-	int			status, ret = -1;
+	volatile emac_desc *rx_curr_desc;
+	volatile emac_desc *curr_desc;
+	volatile emac_desc *tail_desc;
+	int status, ret = -1;
 
 	rx_curr_desc = emac_rx_active_head;
 	status = rx_curr_desc->pkt_flag_len;
 	if ((rx_curr_desc) && ((status & EMAC_CPPI_OWNERSHIP_BIT) == 0)) {
-	        if (status & EMAC_CPPI_RX_ERROR_FRAME) {
-	        	/* Error in packet - discard it and requeue desc */
-	        	printf("WARN: emac_rcv_pkt: Error in packet\n");
+		if (status & EMAC_CPPI_RX_ERROR_FRAME) {
+			/* Error in packet - discard it and requeue desc */
+			printf ("WARN: emac_rcv_pkt: Error in packet\n");
 		} else {
-			NetReceive(rx_curr_desc->buffer, (rx_curr_desc->buff_off_len & 0xffff));
+			NetReceive (rx_curr_desc->buffer,
+				    (rx_curr_desc->buff_off_len & 0xffff));
 			ret = rx_curr_desc->buff_off_len & 0xffff;
-	        }
+		}
 
-	        /* Ack received packet descriptor */
-	        adap_emac->RX0CP = (unsigned int)rx_curr_desc;
-	        curr_desc = rx_curr_desc;
-	        emac_rx_active_head = (volatile emac_desc *)rx_curr_desc->next;
+		/* Ack received packet descriptor */
+		adap_emac->RX0CP = (unsigned int) rx_curr_desc;
+		curr_desc = rx_curr_desc;
+		emac_rx_active_head =
+			(volatile emac_desc *) rx_curr_desc->next;
 
-	        if (status & EMAC_CPPI_EOQ_BIT) {
-	        	if (emac_rx_active_head) {
-	        		adap_emac->RX0HDP = (unsigned int)emac_rx_active_head;
+		if (status & EMAC_CPPI_EOQ_BIT) {
+			if (emac_rx_active_head) {
+				adap_emac->RX0HDP =
+					(unsigned int) emac_rx_active_head;
 			} else {
 				emac_rx_queue_active = 0;
-				printf("INFO:emac_rcv_packet: RX Queue not active\n");
+				printf ("INFO:emac_rcv_packet: RX Queue not active\n");
 			}
 		}
 
@@ -621,28 +623,29 @@ static int dm644x_eth_rcv_packet(void)
 		rx_curr_desc->next = 0;
 
 		if (emac_rx_active_head == 0) {
-			printf("INFO: emac_rcv_pkt: active queue head = 0\n");
+			printf ("INFO: emac_rcv_pkt: active queue head = 0\n");
 			emac_rx_active_head = curr_desc;
 			emac_rx_active_tail = curr_desc;
 			if (emac_rx_queue_active != 0) {
-				adap_emac->RX0HDP = (unsigned int)emac_rx_active_head;
-				printf("INFO: emac_rcv_pkt: active queue head = 0, HDP fired\n");
+				adap_emac->RX0HDP =
+					(unsigned int) emac_rx_active_head;
+				printf ("INFO: emac_rcv_pkt: active queue head = 0, HDP fired\n");
 				emac_rx_queue_active = 1;
 			}
 		} else {
 			tail_desc = emac_rx_active_tail;
 			emac_rx_active_tail = curr_desc;
-			tail_desc->next = (unsigned int)curr_desc;
+			tail_desc->next = (unsigned int) curr_desc;
 			status = tail_desc->pkt_flag_len;
 			if (status & EMAC_CPPI_EOQ_BIT) {
-				adap_emac->RX0HDP = (unsigned int)curr_desc;
+				adap_emac->RX0HDP = (unsigned int) curr_desc;
 				status &= ~EMAC_CPPI_EOQ_BIT;
 				tail_desc->pkt_flag_len = status;
 			}
 		}
-		return(ret);
+		return (ret);
 	}
-	return(0);
+	return (0);
 }
 
 #endif /* CONFIG_CMD_NET */
diff --git a/cpu/arm926ejs/davinci/lowlevel_init.S b/cpu/arm926ejs/davinci/lowlevel_init.S
index a87c112eca..0a4b2cf674 100644
--- a/cpu/arm926ejs/davinci/lowlevel_init.S
+++ b/cpu/arm926ejs/davinci/lowlevel_init.S
@@ -110,7 +110,7 @@ checkGemStatClkStop:
 	str	r10, [r6]
 
 	/*------------------------------------------------------*
-	 * DDR2 PLL Initialization			    	*
+	 * DDR2 PLL Initialization				*
 	 *------------------------------------------------------*/
 
 	/* Select the Clock Mode Depending on the Value written in the Boot Table by the run script */
@@ -547,7 +547,7 @@ VTP1Lock:
 
 	/*
 	 * Call board-specific lowlevel init.
- 	 * That MUST be present and THAT returns
+	 * That MUST be present and THAT returns
 	 * back to arch calling code with "mov pc, lr."
 	 */
 	b	dv_board_init
diff --git a/cpu/arm926ejs/davinci/nand.c b/cpu/arm926ejs/davinci/nand.c
index 127be9fcd4..ffc770fd1b 100644
--- a/cpu/arm926ejs/davinci/nand.c
+++ b/cpu/arm926ejs/davinci/nand.c
@@ -325,17 +325,17 @@ static void nand_flash_init(void)
 	 *                                                                  *
 	 *------------------------------------------------------------------*/
 	 acfg1 = 0
-	 	| (0 << 31 )	/* selectStrobe */
-	 	| (0 << 30 )	/* extWait */
-	 	| (1 << 26 )	/* writeSetup	10 ns */
-	 	| (3 << 20 )	/* writeStrobe	40 ns */
-	 	| (1 << 17 )	/* writeHold	10 ns */
-	 	| (1 << 13 )	/* readSetup	10 ns */
-	 	| (5 << 7 )	/* readStrobe	60 ns */
-	 	| (1 << 4 )	/* readHold	10 ns */
-	 	| (3 << 2 )	/* turnAround	?? ns */
-	 	| (0 << 0 )	/* asyncSize	8-bit bus */
-	 	;
+		| (0 << 31 )	/* selectStrobe */
+		| (0 << 30 )	/* extWait */
+		| (1 << 26 )	/* writeSetup	10 ns */
+		| (3 << 20 )	/* writeStrobe	40 ns */
+		| (1 << 17 )	/* writeHold	10 ns */
+		| (1 << 13 )	/* readSetup	10 ns */
+		| (5 << 7 )	/* readStrobe	60 ns */
+		| (1 << 4 )	/* readHold	10 ns */
+		| (3 << 2 )	/* turnAround	?? ns */
+		| (0 << 0 )	/* asyncSize	8-bit bus */
+		;
 
 	emif_regs = (emifregs)DAVINCI_ASYNC_EMIF_CNTRL_BASE;
 
diff --git a/cpu/arm926ejs/interrupts.c b/cpu/arm926ejs/interrupts.c
index 1819f6b078..7a41f0b12d 100644
--- a/cpu/arm926ejs/interrupts.c
+++ b/cpu/arm926ejs/interrupts.c
@@ -49,7 +49,7 @@ int interrupt_init (void)
 {
 	extern void timer_init(void);
 
-  	timer_init();
+	timer_init();
 
 	return 0;
 }
diff --git a/cpu/arm926ejs/start.S b/cpu/arm926ejs/start.S
index 297efe07c2..a61fa1847d 100644
--- a/cpu/arm926ejs/start.S
+++ b/cpu/arm926ejs/start.S
@@ -175,7 +175,7 @@ stack_setup:
 clear_bss:
 	ldr	r0, _bss_start		/* find start of bss segment        */
 	ldr	r1, _bss_end		/* stop here                        */
-	mov 	r2, #0x00000000		/* clear                            */
+	mov	r2, #0x00000000		/* clear                            */
 
 clbss_l:str	r2, [r0]		/* clear loop...                    */
 	add	r0, r0, #4
@@ -370,7 +370,7 @@ not_used:
 irq:
 	get_irq_stack
 	irq_save_user_regs
-	bl 	do_irq
+	bl	do_irq
 	irq_restore_user_regs
 
 	.align	5
@@ -378,7 +378,7 @@ fiq:
 	get_fiq_stack
 	/* someone ought to write a more effiction fiq_save_user_regs */
 	irq_save_user_regs
-	bl 	do_fiq
+	bl	do_fiq
 	irq_restore_user_regs
 
 #else
diff --git a/cpu/arm946es/start.S b/cpu/arm946es/start.S
index e8c908bf28..9e97f530f8 100644
--- a/cpu/arm946es/start.S
+++ b/cpu/arm946es/start.S
@@ -167,7 +167,7 @@ stack_setup:
 clear_bss:
 	ldr	r0, _bss_start		/* find start of bss segment        */
 	ldr	r1, _bss_end		/* stop here                        */
-	mov 	r2, #0x00000000		/* clear                            */
+	mov	r2, #0x00000000		/* clear                            */
 
 clbss_l:str	r2, [r0]		/* clear loop...                    */
 	add	r0, r0, #4
@@ -358,7 +358,7 @@ not_used:
 irq:
 	get_irq_stack
 	irq_save_user_regs
-	bl 	do_irq
+	bl	do_irq
 	irq_restore_user_regs
 
 	.align	5
@@ -366,7 +366,7 @@ fiq:
 	get_fiq_stack
 	/* someone ought to write a more effiction fiq_save_user_regs */
 	irq_save_user_regs
-	bl 	do_fiq
+	bl	do_fiq
 	irq_restore_user_regs
 
 #else
diff --git a/cpu/arm_intcm/start.S b/cpu/arm_intcm/start.S
index 75fe9174ab..d5778a046c 100644
--- a/cpu/arm_intcm/start.S
+++ b/cpu/arm_intcm/start.S
@@ -165,7 +165,7 @@ stack_setup:
 clear_bss:
 	ldr	r0, _bss_start		/* find start of bss segment        */
 	ldr	r1, _bss_end		/* stop here                        */
-	mov 	r2, #0x00000000		/* clear                            */
+	mov	r2, #0x00000000		/* clear                            */
 
 clbss_l:str	r2, [r0]		/* clear loop...                    */
 	add	r0, r0, #4
@@ -339,7 +339,7 @@ not_used:
 irq:
 	get_irq_stack
 	irq_save_user_regs
-	bl 	do_irq
+	bl	do_irq
 	irq_restore_user_regs
 
 	.align	5
@@ -348,7 +348,7 @@ fiq:
 	get_fiq_stack
 	/* someone ought to write a more effiction fiq_save_user_regs */
 	irq_save_user_regs
-	bl 	do_fiq
+	bl	do_fiq
 	irq_restore_user_regs
 
 #else
diff --git a/cpu/blackfin/flush.S b/cpu/blackfin/flush.S
index 8072b8643f..417f798f85 100644
--- a/cpu/blackfin/flush.S
+++ b/cpu/blackfin/flush.S
@@ -223,7 +223,7 @@ ENDPROC(_dcplb_flush)
 
 .align 4;
 page_prefix_table:
-.byte4 	0xFFFFFC00;	/* 1K */
+.byte4	0xFFFFFC00;	/* 1K */
 .byte4	0xFFFFF000;	/* 4K */
 .byte4	0xFFF00000;	/* 1M */
 .byte4	0xFFC00000;	/* 4M */
diff --git a/cpu/blackfin/i2c.c b/cpu/blackfin/i2c.c
index 47be2587d5..60f03d47a1 100644
--- a/cpu/blackfin/i2c.c
+++ b/cpu/blackfin/i2c.c
@@ -302,7 +302,7 @@ void i2c_init(int speed, int slaveaddr)
  * i2c_probe: - Test if a chip answers for a given i2c address
  *
  * @chip:	address of the chip which is searched for
- * @return: 	0 if a chip was found, -1 otherwhise
+ * @return:	0 if a chip was found, -1 otherwhise
  */
 
 int i2c_probe(uchar chip)
diff --git a/cpu/blackfin/serial.c b/cpu/blackfin/serial.c
index 0dfee51423..406d9d023d 100644
--- a/cpu/blackfin/serial.c
+++ b/cpu/blackfin/serial.c
@@ -4,7 +4,7 @@
  * Copyright (c) 2005-2008 Analog Devices Inc.
  *
  * Copyright (c) 2003	Bas Vermeulen <bas@buyways.nl>,
- * 			BuyWays B.V. (www.buyways.nl)
+ *			BuyWays B.V. (www.buyways.nl)
  *
  * Based heavily on:
  * blkfinserial.c: Serial driver for BlackFin DSP internal USRTs.
diff --git a/cpu/i386/sc520.c b/cpu/i386/sc520.c
index d0a7341882..640b25584a 100644
--- a/cpu/i386/sc520.c
+++ b/cpu/i386/sc520.c
@@ -406,7 +406,7 @@ void reset_timer(void)
 ulong get_timer(ulong base)
 {
 	/* fixme: 30 or 33 */
-	return 	read_mmcr_word(SC520_GPTMR0CNT) / 33;
+	return	read_mmcr_word(SC520_GPTMR0CNT) / 33;
 }
 
 void set_timer(ulong t)
diff --git a/cpu/i386/sc520_asm.S b/cpu/i386/sc520_asm.S
index 8fc713d93b..34322ea251 100644
--- a/cpu/i386/sc520_asm.S
+++ b/cpu/i386/sc520_asm.S
@@ -512,7 +512,7 @@ dram_done:
 	shrl	$2, %eax
 	movl	%eax, %ebx
 
-bank2: 	movl	(%edi), %eax
+bank2:	movl	(%edi), %eax
 	movl	%eax, %ecx
 	andl	$0x00800000, %ecx
 	jz	bank1
@@ -520,7 +520,7 @@ bank2: 	movl	(%edi), %eax
 	shll	$6, %eax
 	movl	%eax, %ebx
 
-bank1: 	movl	(%edi), %eax
+bank1:	movl	(%edi), %eax
 	movl	%eax, %ecx
 	andl	$0x00008000, %ecx
 	jz	bank0
@@ -528,7 +528,7 @@ bank1: 	movl	(%edi), %eax
 	shll	$14, %eax
 	movl	%eax, %ebx
 
-bank0: 	movl	(%edi), %eax
+bank0:	movl	(%edi), %eax
 	movl	%eax, %ecx
 	andl	$0x00000080, %ecx
 	jz	done
@@ -563,7 +563,7 @@ set_ecc:
 	xorl	%eax, %eax
 	shrl	$2, %ecx
 	cld
-	rep 	stosl
+	rep	stosl
 			/* enable read, write buffers */
 	movb    $0x11, %al
 	movl    $DBCTL, %edi
diff --git a/cpu/i386/start.S b/cpu/i386/start.S
index 51a27aa21d..264ac0940b 100644
--- a/cpu/i386/start.S
+++ b/cpu/i386/start.S
@@ -34,8 +34,8 @@
 .globl _i386boot_start
 _i386boot_start:
 _start:
-	movl    $0x18,%eax         	/* Load our segement registes, the
-					 * gdt have already been loaded by start16.S */
+	movl    $0x18,%eax	/* Load our segement registes, the
+				 * gdt have already been loaded by start16.S */
 	movw    %ax,%fs
 	movw	%ax,%ds
 	movw    %ax,%gs
@@ -76,7 +76,7 @@ mem_init_ret:
 	movl	$.progress0a, %ebp
 	jmp	show_boot_progress
 .progress0a:
-	jmp 	die
+	jmp	die
 mem_ok:
 
 	/* indicate progress */
@@ -138,7 +138,7 @@ data_fail:
 	movl	$.progress2a, %ebp
 	jmp	show_boot_progress
 .progress2a:
-	jmp 	die
+	jmp	die
 
 data_ok:
 
@@ -162,7 +162,7 @@ bss:
 	movl	$0, (%edi)
 	add	$4, %edi
 	loop	bss
-	jmp 	bss_ok
+	jmp	bss_ok
 
 bss_fail:
 	/* indicate (lack of) progress */
@@ -170,7 +170,7 @@ bss_fail:
 	movl	$.progress3a, %ebp
 	jmp	show_boot_progress
 .progress3a:
-	jmp 	die
+	jmp	die
 
 bss_ok:
 
diff --git a/cpu/i386/start16.S b/cpu/i386/start16.S
index 239f2ff39b..1ebb6bc8b6 100644
--- a/cpu/i386/start16.S
+++ b/cpu/i386/start16.S
@@ -39,74 +39,74 @@ start16:
 board_init16_ret:
 
 	/* Turn of cache (this might require a 486-class CPU) */
-	movl    %cr0, %eax
-	orl     $0x60000000,%eax
-	movl    %eax, %cr0
+	movl	%cr0, %eax
+	orl	$0x60000000,%eax
+	movl	%eax, %cr0
 	wbinvd
 
 	/* load the descriptor tables */
 o32 cs	lidt	idt_ptr
-o32 cs	lgdt    gdt_ptr
+o32 cs	lgdt	gdt_ptr
 
 
 	/* Now, we enter protected mode */
-	movl    %cr0, %eax
-	orl     $1,%eax
-	movl    %eax, %cr0
+	movl	%cr0, %eax
+	orl	$1,%eax
+	movl	%eax, %cr0
 
 	/* Flush the prefetch queue */
-	jmp     ff
+	jmp	ff
 ff:
 
 	/* Finally jump to the 32bit initialization code */
 	movw	$code32start, %ax
-	movw    %ax,%bp
+	movw	%ax,%bp
 o32 cs	ljmp	*(%bp)
 
 	/* 48-bit far pointer */
 code32start:
-	.long	_start                          /* offset */
-	.word	0x10                            /* segment */
+	.long	_start		/* offset */
+	.word	0x10		/* segment */
 
 idt_ptr:
-	.word	0				/* limit */
-	.long	0		       		/* base */
+	.word	0		/* limit */
+	.long	0		/* base */
 
 gdt_ptr:
-	.word	0x30			        /* limit (48 bytes = 6 GDT entries) */
-	.long	BOOT_SEG + gdt	        	/* base */
+	.word	0x30		/* limit (48 bytes = 6 GDT entries) */
+	.long	BOOT_SEG + gdt	/* base */
 
 	/* The GDT table ...
 	 *
-	 *       Selector	Type
-	 * 	 0x00		NULL
-	 * 	 0x08		Unused
+	 *	 Selector	Type
+	 *	 0x00		NULL
+	 *	 0x08		Unused
 	 *	 0x10		32bit code
 	 *	 0x18		32bit data/stack
 	 *	 0x20		16bit code
-	 *	 0x28	 	16bit data/stack
+	 *	 0x28		16bit data/stack
 	 */
 
 gdt:
-	.word	0, 0, 0, 0			/* NULL  */
-	.word	0, 0, 0, 0			/* unused */
-
-	.word	0xFFFF				/* 4Gb - (0x100000*0x1000 = 4Gb) */
-	.word	0				/* base address = 0 */
-	.word	0x9B00				/* code read/exec */
-	.word	0x00CF				/* granularity = 4096, 386 (+5th nibble of limit) */
-
-	.word	0xFFFF				/* 4Gb - (0x100000*0x1000 = 4Gb) */
-	.word	0x0				/* base address = 0 */
-	.word	0x9300				/* data read/write */
-	.word	0x00CF				/* granularity = 4096, 386 (+5th nibble of limit) */
-
-	.word	0xFFFF				/* 64kb */
-	.word	0				/* base address = 0 */
-	.word	0x9b00				/* data read/write */
-	.word	0x0010				/* granularity = 1  (+5th nibble of limit) */
-
-	.word	0xFFFF				/* 64kb */
-	.word	0				/* base address = 0 */
-	.word	0x9300				/* data read/write */
-	.word	0x0010				/* granularity = 1 (+5th nibble of limit) */
+	.word	0, 0, 0, 0	/* NULL  */
+	.word	0, 0, 0, 0	/* unused */
+
+	.word	0xFFFF		/* 4Gb - (0x100000*0x1000 = 4Gb) */
+	.word	0		/* base address = 0 */
+	.word	0x9B00		/* code read/exec */
+	.word	0x00CF		/* granularity = 4096, 386 (+5th nibble of limit) */
+
+	.word	0xFFFF		/* 4Gb - (0x100000*0x1000 = 4Gb) */
+	.word	0x0		/* base address = 0 */
+	.word	0x9300		/* data read/write */
+	.word	0x00CF		/* granularity = 4096, 386 (+5th nibble of limit) */
+
+	.word	0xFFFF		/* 64kb */
+	.word	0		/* base address = 0 */
+	.word	0x9b00		/* data read/write */
+	.word	0x0010		/* granularity = 1  (+5th nibble of limit) */
+
+	.word	0xFFFF		/* 64kb */
+	.word	0		/* base address = 0 */
+	.word	0x9300		/* data read/write */
+	.word	0x0010		/* granularity = 1 (+5th nibble of limit) */
diff --git a/cpu/ixp/npe/IxEthAcc.c b/cpu/ixp/npe/IxEthAcc.c
index d981649da6..061b24bb50 100644
--- a/cpu/ixp/npe/IxEthAcc.c
+++ b/cpu/ixp/npe/IxEthAcc.c
@@ -215,7 +215,7 @@ PUBLIC IxEthAccStatus ixEthAccPortInit( IxEthAccPortId portId)
 
    if ( ! IX_ETH_ACC_IS_SERVICE_INITIALIZED() )
    {
-   	return(IX_ETH_ACC_FAIL);
+	return(IX_ETH_ACC_FAIL);
    }
 
    /*
@@ -235,8 +235,8 @@ PUBLIC IxEthAccStatus ixEthAccPortInit( IxEthAccPortId portId)
 
    if ( IX_ETH_IS_PORT_INITIALIZED(portId) )
    {
-   	/* Already initialized */
-   	return(IX_ETH_ACC_FAIL);
+	/* Already initialized */
+	return(IX_ETH_ACC_FAIL);
    }
 
    if(ixEthAccMacInit(portId)!=IX_ETH_ACC_SUCCESS)
diff --git a/cpu/ixp/npe/IxEthAccCommon.c b/cpu/ixp/npe/IxEthAccCommon.c
index bda2c44792..211203dffd 100644
--- a/cpu/ixp/npe/IxEthAccCommon.c
+++ b/cpu/ixp/npe/IxEthAccCommon.c
@@ -96,7 +96,7 @@ extern IxEthAccInfo   ixEthAccDataInfo;
 IX_ETH_ACC_PRIVATE
 IxEthAccQregInfo ixEthAccQmgrRxDefaultTemplate =
   {
-    IX_ETH_ACC_RX_FRAME_ETH_Q, 	     /**< Queue ID */
+    IX_ETH_ACC_RX_FRAME_ETH_Q,	     /**< Queue ID */
     "Eth Rx Q",
     ixEthRxFrameQMCallback,          /**< Functional callback */
     (IxQMgrCallbackId) 0,	     /**< Callback tag	      */
@@ -104,7 +104,7 @@ IxEthAccQregInfo ixEthAccQmgrRxDefaultTemplate =
     IX_QMGR_Q_ENTRY_SIZE1,	     /**< Queue Entry Sizes - all Q entries are single word entries   */
     TRUE,			     /**< Enable Q notification at startup */
     IX_ETH_ACC_RX_FRAME_ETH_Q_SOURCE,/**< Q Condition to drive callback   */
-    IX_QMGR_Q_WM_LEVEL0, 	     /**< Q Low water mark */
+    IX_QMGR_Q_WM_LEVEL0,	     /**< Q Low water mark */
     IX_QMGR_Q_WM_LEVEL1,	     /**< Q High water mark - needed by NPE */
   };
 
@@ -116,7 +116,7 @@ IxEthAccQregInfo ixEthAccQmgrRxDefaultTemplate =
 IX_ETH_ACC_PRIVATE
 IxEthAccQregInfo ixEthAccQmgrRxSmallTemplate =
   {
-    IX_ETH_ACC_RX_FRAME_ETH_Q, 	     /**< Queue ID */
+    IX_ETH_ACC_RX_FRAME_ETH_Q,	     /**< Queue ID */
     "Eth Rx Q",
     ixEthRxFrameQMCallback,          /**< Functional callback */
     (IxQMgrCallbackId) 0,	     /**< Callback tag	      */
@@ -124,7 +124,7 @@ IxEthAccQregInfo ixEthAccQmgrRxSmallTemplate =
     IX_QMGR_Q_ENTRY_SIZE1,	     /**< Queue Entry Sizes - all Q entries are single word entries   */
     TRUE,			     /**< Enable Q notification at startup */
     IX_ETH_ACC_RX_FRAME_ETH_Q_SOURCE,/**< Q Condition to drive callback   */
-    IX_QMGR_Q_WM_LEVEL0, 	     /**< Q Low water mark */
+    IX_QMGR_Q_WM_LEVEL0,	     /**< Q Low water mark */
     IX_QMGR_Q_WM_LEVEL1,	     /**< Q High water mark - needed by NPE */
   };
 
@@ -146,7 +146,7 @@ IxEthAccQregInfo ixEthAccQmgrStaticInfo[]=
     IX_QMGR_Q_ENTRY_SIZE1,	     /**< Queue Entry Sizes - all Q entries are single word entries   */
     FALSE,			     /**< Disable Q notification at startup */
     IX_ETH_ACC_RX_FREE_BUFF_ENET0_Q_SOURCE, /**< Q Condition to drive callback  */
-    IX_QMGR_Q_WM_LEVEL0, 	     /***< Q Low water mark */
+    IX_QMGR_Q_WM_LEVEL0,	     /***< Q Low water mark */
     IX_QMGR_Q_WM_LEVEL64,	     /**< Q High water mark */
   },
 
@@ -159,7 +159,7 @@ IxEthAccQregInfo ixEthAccQmgrStaticInfo[]=
     IX_QMGR_Q_ENTRY_SIZE1,	     /**< Queue Entry Sizes - all Q entries are single word entries   */
     FALSE,			     /**< Disable Q notification at startup */
     IX_ETH_ACC_RX_FREE_BUFF_ENET1_Q_SOURCE,  /**< Q Condition to drive callback  */
-    IX_QMGR_Q_WM_LEVEL0, 	     /**< Q Low water mark */
+    IX_QMGR_Q_WM_LEVEL0,	     /**< Q Low water mark */
     IX_QMGR_Q_WM_LEVEL64,	     /**< Q High water mark */
   },
 #ifdef __ixp46X
@@ -172,7 +172,7 @@ IxEthAccQregInfo ixEthAccQmgrStaticInfo[]=
     IX_QMGR_Q_ENTRY_SIZE1,	     /**< Queue Entry Sizes - all Q entries are single word entries   */
     FALSE,			     /**< Disable Q notification at startup */
     IX_ETH_ACC_RX_FREE_BUFF_ENET2_Q_SOURCE,  /**< Q Condition to drive callback  */
-    IX_QMGR_Q_WM_LEVEL0, 	     /**< Q Low water mark */
+    IX_QMGR_Q_WM_LEVEL0,	     /**< Q Low water mark */
     IX_QMGR_Q_WM_LEVEL64,	     /**< Q High water mark */
   },
 #endif
@@ -185,7 +185,7 @@ IxEthAccQregInfo ixEthAccQmgrStaticInfo[]=
     IX_QMGR_Q_ENTRY_SIZE1,	     /**< Queue Entry Sizes - all Q entries are single word entries   */
     FALSE,			     /**< Disable Q notification at startup */
     IX_ETH_ACC_TX_FRAME_ENET0_Q_SOURCE,	 /**< Q Condition to drive callback  */
-    IX_QMGR_Q_WM_LEVEL0, 	     /**< Q Low water mark */
+    IX_QMGR_Q_WM_LEVEL0,	     /**< Q Low water mark */
     IX_QMGR_Q_WM_LEVEL64,	     /**< Q High water mark */
   },
 
@@ -198,7 +198,7 @@ IxEthAccQregInfo ixEthAccQmgrStaticInfo[]=
     IX_QMGR_Q_ENTRY_SIZE1,	     /**< Queue Entry Sizes - all Q entries are single word entries   */
     FALSE,			     /**< Disable Q notification at startup */
     IX_ETH_ACC_TX_FRAME_ENET1_Q_SOURCE,	     /**< Q Condition to drive callback  */
-    IX_QMGR_Q_WM_LEVEL0, 	     /**< Q Low water mark */
+    IX_QMGR_Q_WM_LEVEL0,	     /**< Q Low water mark */
     IX_QMGR_Q_WM_LEVEL64,	     /**< Q High water mark */
   },
 #ifdef __ixp46X
@@ -211,7 +211,7 @@ IxEthAccQregInfo ixEthAccQmgrStaticInfo[]=
     IX_QMGR_Q_ENTRY_SIZE1,	     /** Queue Entry Sizes - all Q entries are single ord entries   */
     FALSE,			     /** Disable Q notification at startup */
     IX_ETH_ACC_TX_FRAME_ENET2_Q_SOURCE,	     /** Q Condition to drive callback  */
-    IX_QMGR_Q_WM_LEVEL0, 	     /* No queues use almost empty */
+    IX_QMGR_Q_WM_LEVEL0,	     /* No queues use almost empty */
     IX_QMGR_Q_WM_LEVEL64,	      /** Q High water mark - needed used  */
   },
 #endif
@@ -224,7 +224,7 @@ IxEthAccQregInfo ixEthAccQmgrStaticInfo[]=
     IX_QMGR_Q_ENTRY_SIZE1,	     /**< Queue Entry Sizes - all Q entries are single word entries   */
     TRUE,			     /**< Enable Q notification at startup */
     IX_ETH_ACC_TX_FRAME_DONE_ETH_Q_SOURCE, /**< Q Condition to drive callback  */
-    IX_QMGR_Q_WM_LEVEL0, 	     /**< Q Low water mark */
+    IX_QMGR_Q_WM_LEVEL0,	     /**< Q Low water mark */
     IX_QMGR_Q_WM_LEVEL2,	     /**< Q High water mark - needed by NPE */
   },
 
diff --git a/cpu/ixp/npe/IxEthAccDataPlane.c b/cpu/ixp/npe/IxEthAccDataPlane.c
index e46fc9b25a..b62f0d016e 100644
--- a/cpu/ixp/npe/IxEthAccDataPlane.c
+++ b/cpu/ixp/npe/IxEthAccDataPlane.c
@@ -544,7 +544,7 @@ ixEthAccMbufFromRxQ(IX_OSAL_MBUF *mbuf)
 	    IX_OSAL_MBUF_MLEN(ptr) = (len >> IX_ETHNPE_ACC_LENGTH_OFFSET);
 
             /* get the next pointer */
- 	    PTR_NPE2VIRT(IX_OSAL_MBUF *,IX_ETHACC_NE_NEXT(ptr), nextPtr);
+	    PTR_NPE2VIRT(IX_OSAL_MBUF *,IX_ETHACC_NE_NEXT(ptr), nextPtr);
 	    if (nextPtr != NULL)
 	    {
 		nextPtr = (IX_OSAL_MBUF *)((UINT8 *)nextPtr - offsetof(IX_OSAL_MBUF,ix_ne));
diff --git a/cpu/ixp/npe/IxEthAccMac.c b/cpu/ixp/npe/IxEthAccMac.c
index d57e71678e..369ee91d94 100644
--- a/cpu/ixp/npe/IxEthAccMac.c
+++ b/cpu/ixp/npe/IxEthAccMac.c
@@ -2423,14 +2423,14 @@ ixEthAccMacStateUpdate(IxEthAccPortId portId)
         REG_READ(ixEthAccMacBase[portId],
 		 IX_ETH_ACC_MAC_RX_CNTRL1,
 		 regval);
- 	REG_WRITE(ixEthAccMacBase[portId],
+	REG_WRITE(ixEthAccMacBase[portId],
 		  IX_ETH_ACC_MAC_RX_CNTRL1,
 		  regval & ~IX_ETH_ACC_RX_CNTRL1_RX_EN);
 
         REG_READ(ixEthAccMacBase[portId],
 		 IX_ETH_ACC_MAC_TX_CNTRL1,
 		 regval);
- 	REG_WRITE(ixEthAccMacBase[portId],
+	REG_WRITE(ixEthAccMacBase[portId],
 		  IX_ETH_ACC_MAC_TX_CNTRL1,
 		  regval & ~IX_ETH_ACC_TX_CNTRL1_TX_EN);
     }
@@ -2493,7 +2493,7 @@ ixEthAccMacStateUpdate(IxEthAccPortId portId)
         REG_READ(ixEthAccMacBase[portId],
 		 IX_ETH_ACC_MAC_TX_CNTRL1,
 		 regval);
- 	REG_WRITE(ixEthAccMacBase[portId],
+	REG_WRITE(ixEthAccMacBase[portId],
 		  IX_ETH_ACC_MAC_TX_CNTRL1,
 		  regval | IX_ETH_ACC_TX_CNTRL1_TX_EN);
     }
diff --git a/cpu/ixp/npe/IxEthAccMii.c b/cpu/ixp/npe/IxEthAccMii.c
index 86368a4734..d282aa6725 100644
--- a/cpu/ixp/npe/IxEthAccMii.c
+++ b/cpu/ixp/npe/IxEthAccMii.c
@@ -324,7 +324,7 @@ ixEthAccMiiWriteRtn (UINT8 phyAddr,
 
 	/*The "GO" bit is reset to 0 when the write completes*/
 	if((regval & IX_ETH_ACC_MII_GO) == 0x0)
-	{	    	    
+	{		    
 	    break;
 	}
 	/* Sleep for a while */
diff --git a/cpu/ixp/npe/IxNpeDlImageMgr.c b/cpu/ixp/npe/IxNpeDlImageMgr.c
index 75b42f2f8f..ccc0da7ebd 100644
--- a/cpu/ixp/npe/IxNpeDlImageMgr.c
+++ b/cpu/ixp/npe/IxNpeDlImageMgr.c
@@ -164,7 +164,7 @@ ixNpeDlImageMgrImageIdCompare (IxNpeDlImageId *imageIdA,
 				 
 PRIVATE BOOL
 ixNpeDlImageMgrNpeFunctionIdCompare (IxNpeDlImageId *imageIdA,
-    				       IxNpeDlImageId *imageIdB);
+				       IxNpeDlImageId *imageIdB);
 
 #if 0
 PRIVATE IX_STATUS
diff --git a/cpu/ixp/npe/IxNpeDlNpeMgrUtils.c b/cpu/ixp/npe/IxNpeDlNpeMgrUtils.c
index 9dcf3c1e4d..18cac50208 100644
--- a/cpu/ixp/npe/IxNpeDlNpeMgrUtils.c
+++ b/cpu/ixp/npe/IxNpeDlNpeMgrUtils.c
@@ -613,9 +613,9 @@ ixNpeDlNpeMgrLogicalRegWrite (
 
     if (verify)
     {
-    	status = ixNpeDlNpeMgrLogicalRegRead (npeBaseAddress, regAddr,
-    						   regSize, ctxtNum, &retRegVal);
-    						   
+	status = ixNpeDlNpeMgrLogicalRegRead (npeBaseAddress, regAddr,
+						   regSize, ctxtNum, &retRegVal);
+						   
         if (IX_SUCCESS == status)
         {
             if (regVal != retRegVal)
diff --git a/cpu/ixp/npe/IxOsalIoMem.c b/cpu/ixp/npe/IxOsalIoMem.c
index 9e540c18e0..34df92bf79 100644
--- a/cpu/ixp/npe/IxOsalIoMem.c
+++ b/cpu/ixp/npe/IxOsalIoMem.c
@@ -281,7 +281,7 @@ ixOsalIoMemUnmap (UINT32 requestedAddress, UINT32 endianType)
  * Return value: corresponding physical address, or NULL 
  *               if there is no physical address addressable 
  *               by the given virtual address
- * OS: 	VxWorks, Linux, WinCE, QNX, eCos
+ * OS:	VxWorks, Linux, WinCE, QNX, eCos
  * Reentrant: Yes
  * IRQ safe: Yes
  */
@@ -310,7 +310,7 @@ ixOsalIoMemVirtToPhys (UINT32 virtualAddress, UINT32 requestedCoherency)
  * Return value: corresponding physical address, or NULL 
  *               if there is no physical address addressable 
  *               by the given virtual address
- * OS: 	VxWorks, Linux, WinCE, QNX, eCos
+ * OS:	VxWorks, Linux, WinCE, QNX, eCos
  * Reentrant: Yes
  * IRQ safe: Yes
  */
diff --git a/cpu/ixp/npe/IxQMgrAqmIf.c b/cpu/ixp/npe/IxQMgrAqmIf.c
index b27b3a2877..738651322c 100644
--- a/cpu/ixp/npe/IxQMgrAqmIf.c
+++ b/cpu/ixp/npe/IxQMgrAqmIf.c
@@ -209,7 +209,7 @@ ixQMgrAqmIfInit (void)
 	 */
 
 	/* AQM Queue access reg addresses, per queue */
-   	ixQMgrAqmIfQueAccRegAddr[i] = 
+	ixQMgrAqmIfQueAccRegAddr[i] = 
 	    (UINT32 *)(aqmBaseAddress + IX_QMGR_Q_ACCESS_ADDR_GET(i));
 	ixQMgrQInlinedReadWriteInfo[i].qAccRegAddr = 
 	    (volatile UINT32 *)(aqmBaseAddress + IX_QMGR_Q_ACCESS_ADDR_GET(i));
diff --git a/cpu/ixp/npe/IxQMgrQAccess.c b/cpu/ixp/npe/IxQMgrQAccess.c
index 2c3e302696..8885736246 100644
--- a/cpu/ixp/npe/IxQMgrQAccess.c
+++ b/cpu/ixp/npe/IxQMgrQAccess.c
@@ -360,7 +360,7 @@ ixQMgrQNumEntriesGet (IxQMgrQId qId,
 	    }
 	    else
 	    {
-  	       /* The queue is either empty, either moving,
+	       /* The queue is either empty, either moving,
 	        * Client can retry if they wish
 	        */
 		*numEntriesPtr = 0;
diff --git a/cpu/ixp/npe/include/IxDmaAcc.h b/cpu/ixp/npe/include/IxDmaAcc.h
index 53d2625591..45c7527de9 100644
--- a/cpu/ixp/npe/include/IxDmaAcc.h
+++ b/cpu/ixp/npe/include/IxDmaAcc.h
@@ -172,7 +172,7 @@ typedef UINT32 IxDmaAccRequestId;
 #define IX_DMA_REQUEST_FULL 16
 
 /**
- * @ingroup 	IxDmaAcc
+ * @ingroup	IxDmaAcc
  * @brief       DMA completion notification
  * This function is called to notify a client that the DMA has been completed
  * @param status @ref IxDmaReturnStatus [out] - reporting to client
@@ -181,11 +181,11 @@ typedef UINT32 IxDmaAccRequestId;
 typedef void (*IxDmaAccDmaCompleteCallback) (IxDmaReturnStatus status);
 
 /**
- * @ingroup 	IxDmaAcc
+ * @ingroup	IxDmaAcc
  * 
  * @fn ixDmaAccInit(IxNpeDlNpeId npeId)
  * 
- * @brief 	Initialise the DMA Access component
+ * @brief	Initialise the DMA Access component
  * This function will initialise the DMA Access component internals
  * @param npeId @ref IxNpeDlNpeId [in] - NPE to use for Dma Transfer
  * @return @li IX_SUCCESS succesfully initialised the component
@@ -196,7 +196,7 @@ PUBLIC IX_STATUS
 ixDmaAccInit(IxNpeDlNpeId npeId);
 
 /**
- * @ingroup 	IxDmaAcc
+ * @ingroup	IxDmaAcc
  * 
  * @fn ixDmaAccDmaTransfer(
     IxDmaAccDmaCompleteCallback callback,
@@ -225,8 +225,8 @@ ixDmaAccInit(IxNpeDlNpeId npeId);
  * @param AddressingMode @ref IxDmaAddressingMode [in] - The DMA addressing mode
  * @param TransferWidth	@ref IxDmaTransferWidth [in] - The DMA transfer width
  *
- * @return @li IX_DMA_SUCCESS 	Notification that the DMA request is succesful
- * @return @li IX_DMA_FAIL 	IxDmaAcc not yet initialised or some internal error has occured
+ * @return @li IX_DMA_SUCCESS	Notification that the DMA request is succesful
+ * @return @li IX_DMA_FAIL	IxDmaAcc not yet initialised or some internal error has occured
  * @return @li IX_DMA_INVALID_TRANSFER_WIDTH Transfer width is nit valid
  * @return @li IX_DMA_INVALID_TRANSFER_LENGTH Transfer length outside of valid range
  * @return @li IX_DMA_INVALID_TRANSFER_MODE Transfer Mode not valid
diff --git a/cpu/ixp/npe/include/IxEthAcc.h b/cpu/ixp/npe/include/IxEthAcc.h
index b424648e9d..ff706c451d 100644
--- a/cpu/ixp/npe/include/IxEthAcc.h
+++ b/cpu/ixp/npe/include/IxEthAcc.h
@@ -626,8 +626,8 @@ PUBLIC void ixEthAccUnload(void);
  *   required features.
  *
  * Dependant on Services: (Must be initialized before using this service may be initialized)
- * 	ixNPEmh - NPE Message handling service.
- * 	ixQmgr	- Queue Manager component.
+ *	ixNPEmh - NPE Message handling service.
+ *	ixQmgr	- Queue Manager component.
  *
  * @param portId  @ref IxEthAccPortId [in]
  *
@@ -745,7 +745,7 @@ typedef void (*IxEthAccPortTxDoneCallback) ( UINT32 callbackTag, IX_OSAL_MBUF *b
  *
  * @fn ixEthAccPortTxDoneCallbackRegister( IxEthAccPortId portId, 
 					   IxEthAccPortTxDoneCallback txCallbackFn, 
- 					   UINT32 callbackTag)
+					   UINT32 callbackTag)
  *
  * @brief Register a callback function to allow 
  * the transmitted buffers to return to the user.
diff --git a/cpu/ixp/npe/include/IxEthAccMii_p.h b/cpu/ixp/npe/include/IxEthAccMii_p.h
index aa42f9c2a1..568d4a0fa4 100644
--- a/cpu/ixp/npe/include/IxEthAccMii_p.h
+++ b/cpu/ixp/npe/include/IxEthAccMii_p.h
@@ -81,13 +81,13 @@
 #define IX_ETH_ACC_MII_STAT_REG	    0x1	/* Status Register */
 #define IX_ETH_ACC_MII_PHY_ID1_REG  0x2	/* PHY identifier 1 Register */
 #define IX_ETH_ACC_MII_PHY_ID2_REG  0x3	/* PHY identifier 2 Register */
-#define IX_ETH_ACC_MII_AN_ADS_REG   0x4	/* Auto-Negotiation 	  */
+#define IX_ETH_ACC_MII_AN_ADS_REG   0x4	/* Auto-Negotiation	  */
 					/* Advertisement Register */
-#define IX_ETH_ACC_MII_AN_PRTN_REG  0x5	/* Auto-Negotiation 	    */
+#define IX_ETH_ACC_MII_AN_PRTN_REG  0x5	/* Auto-Negotiation	    */
 					/* partner ability Register */
 #define IX_ETH_ACC_MII_AN_EXP_REG   0x6	/* Auto-Negotiation   */
 					/* Expansion Register */
-#define IX_ETH_ACC_MII_AN_NEXT_REG  0x7	/* Auto-Negotiation 	       */
+#define IX_ETH_ACC_MII_AN_NEXT_REG  0x7	/* Auto-Negotiation	       */
 					/* next-page transmit Register */
 
 IxEthAccStatus ixEthAccMdioShow (void);
diff --git a/cpu/ixp/npe/include/IxEthAcc_p.h b/cpu/ixp/npe/include/IxEthAcc_p.h
index 37c55605d3..0ee4123557 100644
--- a/cpu/ixp/npe/include/IxEthAcc_p.h
+++ b/cpu/ixp/npe/include/IxEthAcc_p.h
@@ -262,7 +262,7 @@ typedef struct
 {
   IxEthAccPortTxDoneCallback  txBufferDoneCallbackFn;
   UINT32  txCallbackTag;
-  IxEthAccDataPlaneQList 	txQ[IX_ETH_ACC_NUM_TX_PRIORITIES]; /**< Transmit Q */
+  IxEthAccDataPlaneQList	txQ[IX_ETH_ACC_NUM_TX_PRIORITIES]; /**< Transmit Q */
   IxEthAccSchedulerDiscipline schDiscipline; /**< Transmit Xscale QoS */
   IxQMgrQId txQueue; /**< txQueue for this port */
   IxEthAccTxDataStats stats; /**< Transmit s/w stats */
diff --git a/cpu/ixp/npe/include/IxEthMii.h b/cpu/ixp/npe/include/IxEthMii.h
index a1bfe06724..397253a947 100644
--- a/cpu/ixp/npe/include/IxEthMii.h
+++ b/cpu/ixp/npe/include/IxEthMii.h
@@ -106,9 +106,9 @@ PUBLIC IX_STATUS ixEthMiiPhyScan(BOOL phyPresent[], UINT32 maxPhyCount);
  * @ingroup IxEthMii
  *
  * @fn ixEthMiiPhyConfig(UINT32 phyAddr,
-   		         BOOL speed100, 
- 			 BOOL fullDuplex, 
- 			 BOOL autonegotiate)
+		         BOOL speed100, 
+			 BOOL fullDuplex, 
+			 BOOL autonegotiate)
  *
  *
  * @brief Configure a PHY
@@ -209,10 +209,10 @@ PUBLIC IX_STATUS ixEthMiiPhyReset(UINT32 phyAddr);
  * @ingroup IxEthMii
  *
  * @fn ixEthMiiLinkStatus(UINT32 phyAddr, 
- 			  BOOL *linkUp,
- 			  BOOL *speed100, 
- 			  BOOL *fullDuplex,
- 		          BOOL *autoneg)
+			  BOOL *linkUp,
+			  BOOL *speed100, 
+			  BOOL *fullDuplex,
+		          BOOL *autoneg)
  *
  * @brief Retrieve the current status of a PHY
  *   Retrieve the link, speed, duplex and autonegotiation status of a PHY
diff --git a/cpu/ixp/npe/include/IxI2cDrv.h b/cpu/ixp/npe/include/IxI2cDrv.h
index 2472f31a71..92c6b24b46 100644
--- a/cpu/ixp/npe/include/IxI2cDrv.h
+++ b/cpu/ixp/npe/include/IxI2cDrv.h
@@ -64,8 +64,8 @@
 /**
  * @ingroup IxI2cDrv
  * @brief The interval of micro/mili seconds the IXP will wait before it polls for
- * 			status from the ixI2cIntrXferStatus; Every 20us is 1 byte @
- * 			400Kbps and 4 bytes	@ 100Kbps. This is dependent on delay type selected
+ *			status from the ixI2cIntrXferStatus; Every 20us is 1 byte @
+ *			400Kbps and 4 bytes	@ 100Kbps. This is dependent on delay type selected
  *          through the API ixI2cDrvDelayTypeSelect.
  */
 #define IX_I2C_US_POLL_FOR_XFER_STATUS	20
diff --git a/cpu/ixp/npe/include/IxOsalAssert.h b/cpu/ixp/npe/include/IxOsalAssert.h
index 45cebcdaa6..04a4f515aa 100644
--- a/cpu/ixp/npe/include/IxOsalAssert.h
+++ b/cpu/ixp/npe/include/IxOsalAssert.h
@@ -1,6 +1,6 @@
 /*
  * @file        IxOsalAssert.h 
- * @author 	Intel Corporation
+ * @author	Intel Corporation
  * @date        25-08-2004
  *
  * @brief       description goes here
diff --git a/cpu/ixp/npe/include/IxOsalBackwardBufferMgt.h b/cpu/ixp/npe/include/IxOsalBackwardBufferMgt.h
index 5ac3f0cac0..4cf80d31eb 100644
--- a/cpu/ixp/npe/include/IxOsalBackwardBufferMgt.h
+++ b/cpu/ixp/npe/include/IxOsalBackwardBufferMgt.h
@@ -76,7 +76,7 @@ typedef IX_OSAL_MBUF_POOL IX_MBUF_POOL;
 #define IX_MBUF_MTYPE(m_blk_ptr) \
                 IX_OSAL_MBUF_MTYPE(m_blk_ptr)
 
-#define IX_MBUF_FLAGS(m_blk_ptr)   	\
+#define IX_MBUF_FLAGS(m_blk_ptr)	\
 		IX_OSAL_MBUF_FLAGS(m_blk_ptr)
 
 
diff --git a/cpu/ixp/npe/include/IxOsalBackwardMemMap.h b/cpu/ixp/npe/include/IxOsalBackwardMemMap.h
index 18f8f24df4..3881a3b6da 100644
--- a/cpu/ixp/npe/include/IxOsalBackwardMemMap.h
+++ b/cpu/ixp/npe/include/IxOsalBackwardMemMap.h
@@ -136,6 +136,6 @@
 
 #define IX_OSSERV_MEM_MAP(physAddr, size)		IX_OSAL_MEM_MAP(physAddr, size)
 
-#define IX_OSSERV_MEM_UNMAP(virtAddr) 			IX_OSAL_MEM_UNMAP(virtAddr)
+#define IX_OSSERV_MEM_UNMAP(virtAddr)			IX_OSAL_MEM_UNMAP(virtAddr)
 
 #endif /* IX_OSAL_BACKWARD_MEM_MAP_H */
diff --git a/cpu/ixp/npe/include/IxOsalIoMem.h b/cpu/ixp/npe/include/IxOsalIoMem.h
index ac0ce65703..ea6d64d000 100644
--- a/cpu/ixp/npe/include/IxOsalIoMem.h
+++ b/cpu/ixp/npe/include/IxOsalIoMem.h
@@ -1,6 +1,6 @@
 /*
  * @file        IxOsalIoMem.h
- * @author 	Intel Corporation
+ * @author	Intel Corporation
  * @date        25-08-2004
  *
  * @brief       description goes here
diff --git a/cpu/ixp/npe/include/IxOsalMemAccess.h b/cpu/ixp/npe/include/IxOsalMemAccess.h
index 2ad0ccfbb2..9e7fb87be5 100644
--- a/cpu/ixp/npe/include/IxOsalMemAccess.h
+++ b/cpu/ixp/npe/include/IxOsalMemAccess.h
@@ -410,7 +410,7 @@ ixOsalDataCoherentShortWriteSwap (volatile UINT16 * sAddr, UINT16 sData)
 #define IX_OSAL_READ_LONG(wAddr)            IX_OSAL_READ_LONG_BE(wAddr) 
 #define IX_OSAL_READ_SHORT(sAddr)	        IX_OSAL_READ_SHORT_BE(sAddr) 
 #define IX_OSAL_READ_BYTE(bAddr)	        IX_OSAL_READ_BYTE_BE(bAddr) 
-#define IX_OSAL_WRITE_LONG(wAddr, wData) 	IX_OSAL_WRITE_LONG_BE(wAddr, wData)
+#define IX_OSAL_WRITE_LONG(wAddr, wData)	IX_OSAL_WRITE_LONG_BE(wAddr, wData)
 #define IX_OSAL_WRITE_SHORT(sAddr, sData)	IX_OSAL_WRITE_SHORT_BE(sAddr, sData)
 #define IX_OSAL_WRITE_BYTE(bAddr, bData)	IX_OSAL_WRITE_BYTE_BE(bAddr, bData)
 
@@ -419,7 +419,7 @@ ixOsalDataCoherentShortWriteSwap (volatile UINT16 * sAddr, UINT16 sData)
 #define IX_OSAL_READ_LONG(wAddr)            IX_OSAL_READ_LONG_LE_AC(wAddr) 
 #define IX_OSAL_READ_SHORT(sAddr)	        IX_OSAL_READ_SHORT_LE_AC(sAddr) 
 #define IX_OSAL_READ_BYTE(bAddr)	        IX_OSAL_READ_BYTE_LE_AC(bAddr) 
-#define IX_OSAL_WRITE_LONG(wAddr, wData) 	IX_OSAL_WRITE_LONG_LE_AC(wAddr, wData)
+#define IX_OSAL_WRITE_LONG(wAddr, wData)	IX_OSAL_WRITE_LONG_LE_AC(wAddr, wData)
 #define IX_OSAL_WRITE_SHORT(sAddr, sData)	IX_OSAL_WRITE_SHORT_LE_AC(sAddr, sData)
 #define IX_OSAL_WRITE_BYTE(bAddr, bData)	IX_OSAL_WRITE_BYTE_LE_AC(bAddr, bData)
 
@@ -428,7 +428,7 @@ ixOsalDataCoherentShortWriteSwap (volatile UINT16 * sAddr, UINT16 sData)
 #define IX_OSAL_READ_LONG(wAddr)            IX_OSAL_READ_LONG_LE_DC(wAddr) 
 #define IX_OSAL_READ_SHORT(sAddr)	        IX_OSAL_READ_SHORT_LE_DC(sAddr) 
 #define IX_OSAL_READ_BYTE(bAddr)	        IX_OSAL_READ_BYTE_LE_DC(bAddr) 
-#define IX_OSAL_WRITE_LONG(wAddr, wData) 	IX_OSAL_WRITE_LONG_LE_DC(wAddr, wData)
+#define IX_OSAL_WRITE_LONG(wAddr, wData)	IX_OSAL_WRITE_LONG_LE_DC(wAddr, wData)
 #define IX_OSAL_WRITE_SHORT(sAddr, sData)	IX_OSAL_WRITE_SHORT_LE_DC(sAddr, sData)
 #define IX_OSAL_WRITE_BYTE(bAddr, bData)	IX_OSAL_WRITE_BYTE_LE_DC(bAddr, bData)
 
diff --git a/cpu/ixp/npe/include/IxOsalTypes.h b/cpu/ixp/npe/include/IxOsalTypes.h
index c617ec5781..a190a707e3 100644
--- a/cpu/ixp/npe/include/IxOsalTypes.h
+++ b/cpu/ixp/npe/include/IxOsalTypes.h
@@ -175,7 +175,7 @@ typedef volatile INT32 VINT32;
 
 
 #ifndef __inline__
-#define __inline__ 	IX_OSAL_INLINE
+#define __inline__	IX_OSAL_INLINE
 #endif
 
 
diff --git a/cpu/ixp/npe/include/IxQMgr.h b/cpu/ixp/npe/include/IxQMgr.h
index c083a2b322..165ed96e54 100644
--- a/cpu/ixp/npe/include/IxQMgr.h
+++ b/cpu/ixp/npe/include/IxQMgr.h
@@ -1134,7 +1134,7 @@ ixQMgrQRead (IxQMgrQId qId,
 	 * day scenario there are many entries in the queue
 	 * and the counter does not reach zero.
 	 */
- 	if (infoPtr->qReadCount-- == 0)
+	if (infoPtr->qReadCount-- == 0)
 	{
 	    /* There is maybe no entry in the queue
 	     * qReadCount is now negative, but will be corrected before
@@ -1475,7 +1475,7 @@ ixQMgrQWrite (IxQMgrQId qId,
 	    ++entry;
 	    IX_QMGR_INLINE_WRITE_LONG(++qAccRegAddr, *entry);
 	}
- 	entrySize = infoPtr->qEntrySizeInWords;
+	entrySize = infoPtr->qEntrySizeInWords;
     }
 
     /* overflow is available for lower queues only */
diff --git a/cpu/ixp/npe/include/IxQMgrAqmIf_p.h b/cpu/ixp/npe/include/IxQMgrAqmIf_p.h
index 7f5733c5d2..4f0f64d273 100644
--- a/cpu/ixp/npe/include/IxQMgrAqmIf_p.h
+++ b/cpu/ixp/npe/include/IxQMgrAqmIf_p.h
@@ -498,7 +498,7 @@ ixQMgrAqmIfQPop (IxQMgrQId qId,
     volatile UINT32 *accRegAddr;
 
     accRegAddr = (UINT32*)(aqmBaseAddress +
-    			   IX_QMGR_Q_ACCESS_ADDR_GET(qId));
+			   IX_QMGR_Q_ACCESS_ADDR_GET(qId));
 
     switch (numWords)
     {
@@ -533,7 +533,7 @@ ixQMgrAqmIfQPush (IxQMgrQId qId,
     volatile UINT32 *accRegAddr;
 
     accRegAddr = (UINT32*)(aqmBaseAddress +
-    			   IX_QMGR_Q_ACCESS_ADDR_GET(qId));
+			   IX_QMGR_Q_ACCESS_ADDR_GET(qId));
     
     switch (numWords)
     {
@@ -683,9 +683,9 @@ ixQMgrAqmIfRegisterBitCheck (IxQMgrQId qId,
      * multiple queues split accross registers
      */
     registerAddress = (UINT32*)(aqmBaseAddress +
-    				registerBaseAddrOffset +
-    				((qId / queuesPerRegWord) *
-    				 IX_QMGR_NUM_BYTES_PER_WORD));
+				registerBaseAddrOffset +
+				((qId / queuesPerRegWord) *
+				 IX_QMGR_NUM_BYTES_PER_WORD));
 
     /*
      * Get the status word
diff --git a/cpu/ixp/npe/include/IxQueueAssignments.h b/cpu/ixp/npe/include/IxQueueAssignments.h
index 0c1543fa79..f7194e72ec 100644
--- a/cpu/ixp/npe/include/IxQueueAssignments.h
+++ b/cpu/ixp/npe/include/IxQueueAssignments.h
@@ -409,7 +409,7 @@
 * @note THIS IS NOT USED - the Rx queues are read from EthDB QoS configuration
 * 
 */
-#define IX_ETH_ACC_RX_FRAME_ETH_Q 	(IX_QMGR_QUEUE_4)
+#define IX_ETH_ACC_RX_FRAME_ETH_Q	(IX_QMGR_QUEUE_4)
 
 /**
 *
diff --git a/cpu/ixp/pci.c b/cpu/ixp/pci.c
index 84c4339ee6..8c6b0b21b4 100644
--- a/cpu/ixp/pci.c
+++ b/cpu/ixp/pci.c
@@ -259,7 +259,7 @@ void pci_ixp_init (struct pci_controller *hose)
 
 /*
  ==========================================================
- 		Init IXP PCI
+		Init IXP PCI
  ==========================================================
 */
 	REG_READ (PCI_CSR_BASE, PCI_CSR_OFFSET, regval);
diff --git a/cpu/ixp/start.S b/cpu/ixp/start.S
index 757cfaa2d5..d4c8e33bc5 100644
--- a/cpu/ixp/start.S
+++ b/cpu/ixp/start.S
@@ -140,7 +140,7 @@ reset:
 	CPWAIT	r0
 
 	/* invalidate I & Data TLB */
-	mcr 	p15, 0, r0, c8, c7, 0
+	mcr	p15, 0, r0, c8, c7, 0
 	CPWAIT r0
 
 	/* drain write and fill buffers */
@@ -160,22 +160,22 @@ reset:
 
 	/* make sure flash is visible at 0 */
 #if 0
-	ldr 	r2, =IXP425_EXP_CFG0
+	ldr	r2, =IXP425_EXP_CFG0
 	ldr     r1, [r2]
 	orr     r1, r1, #0x80000000
 	str     r1, [r2]
 #endif
-	mov 	r1, #CFG_SDR_CONFIG
+	mov	r1, #CFG_SDR_CONFIG
 	ldr     r2, =IXP425_SDR_CONFIG
 	str     r1, [r2]
 
 	/* disable refresh cycles */
-	mov 	r1, #0
+	mov	r1, #0
 	ldr     r3, =IXP425_SDR_REFRESH
 	str	r1, [r3]
 
 	/* send nop command */
-	mov 	r1, #3
+	mov	r1, #3
 	ldr	r4, =IXP425_SDR_IR
 	str	r1, [r4]
 	DELAY_FOR 0x4000, r0
@@ -226,7 +226,7 @@ reset:
 	CPWAIT	r0
 
 	/* invalidate I & Data TLB */
-	mcr 	p15, 0, r0, c8, c7, 0
+	mcr	p15, 0, r0, c8, c7, 0
 	CPWAIT r0
 
 	/* drain write and fill buffers */
@@ -234,7 +234,7 @@ reset:
 	CPWAIT	r0
 
 	/* move flash to 0x50000000 */
-	ldr 	r2, =IXP425_EXP_CFG0
+	ldr	r2, =IXP425_EXP_CFG0
 	ldr     r1, [r2]
 	bic     r1, r1, #0x80000000
 	str     r1, [r2]
@@ -247,7 +247,7 @@ reset:
 	nop
 
 	/* invalidate I & Data TLB */
-	mcr 	p15, 0, r0, c8, c7, 0
+	mcr	p15, 0, r0, c8, c7, 0
 	CPWAIT r0
 
 	/* enable I cache */
@@ -293,7 +293,7 @@ stack_setup:
 clear_bss:
 	ldr	r0, _bss_start		/* find start of bss segment        */
 	ldr	r1, _bss_end		/* stop here                        */
-	mov 	r2, #0x00000000		/* clear                            */
+	mov	r2, #0x00000000		/* clear                            */
 
 clbss_l:str	r2, [r0]		/* clear loop...                    */
 	add	r0, r0, #4
@@ -482,13 +482,13 @@ fiq:
 .globl reset_cpu
 
 reset_cpu:
-	ldr 	r1, =0x482e
+	ldr	r1, =0x482e
 	ldr     r2, =IXP425_OSWK
 	str     r1, [r2]
-	ldr 	r1, =0x0fff
+	ldr	r1, =0x0fff
 	ldr     r2, =IXP425_OSWT
 	str     r1, [r2]
-	ldr 	r1, =0x5
+	ldr	r1, =0x5
 	ldr     r2, =IXP425_OSWE
 	str     r1, [r2]
 	b	reset_endless
diff --git a/cpu/leon2/start.S b/cpu/leon2/start.S
index 60d3fadef4..f23f499371 100644
--- a/cpu/leon2/start.S
+++ b/cpu/leon2/start.S
@@ -31,10 +31,10 @@
 
 /* Entry for traps which jump to a programmer-specified trap handler.  */
 #define TRAPR(H)  \
-	wr 	%g0, 0xfe0, %psr; \
-	mov 	%g0, %tbr; \
-	ba 	(H); \
-	mov 	%g0, %wim;
+	wr	%g0, 0xfe0, %psr; \
+	mov	%g0, %tbr; \
+	ba	(H); \
+	mov	%g0, %wim;
 
 #define TRAP(H) \
 	mov	%psr, %l0; \
@@ -42,10 +42,10 @@
 	nop; nop;
 
 #define TRAPI(ilevel) \
-	mov 	ilevel, %l7; \
-	mov 	%psr, %l0; \
-	b 	_irq_entry; \
-	mov 	%wim, %l3
+	mov	ilevel, %l7; \
+	mov	%psr, %l0; \
+	b	_irq_entry; \
+	mov	%wim, %l3
 
 /* Unexcpected trap will halt the processor by forcing it to error state */
 #undef BAD_TRAP
@@ -76,7 +76,7 @@ MINFRAME = (WINDOWSIZE + ARGPUSHSIZE + 4)
 #define SA(X)	(((X)+(STACK_ALIGN-1)) & ~(STACK_ALIGN-1))
 
 	.section ".start", "ax"
-	.globl 	_start, start, _trap_table
+	.globl	_start, start, _trap_table
 	.globl  _irq_entry, nmi_trap
 	.globl  _reset_reloc
 
@@ -515,7 +515,7 @@ _window_underflow:
 	nop; nop; nop
 	restore				! Two restores to get into the
 	restore				! window to restore
-	ld	[%sp + 0], %l0; 	! Restore window from the stack
+	ld	[%sp + 0], %l0;		! Restore window from the stack
 	ld	[%sp + 4], %l1;
 	ld	[%sp + 8], %l2;
 	ld	[%sp + 12], %l3;
@@ -547,7 +547,7 @@ _hwerr:
 	ta 0
 	nop
 	nop
-	b _hwerr 			! loop infinite
+	b _hwerr			! loop infinite
 	nop
 
 /* Registers to not touch at all. */
diff --git a/cpu/leon3/start.S b/cpu/leon3/start.S
index 2f1d099e37..d421898d88 100644
--- a/cpu/leon3/start.S
+++ b/cpu/leon3/start.S
@@ -31,10 +31,10 @@
 
 /* Entry for traps which jump to a programmer-specified trap handler.  */
 #define TRAPR(H)  \
-	wr 	%g0, 0xfe0, %psr; \
-	mov 	%g0, %tbr; \
-	ba 	(H); \
-	mov 	%g0, %wim;
+	wr	%g0, 0xfe0, %psr; \
+	mov	%g0, %tbr; \
+	ba	(H); \
+	mov	%g0, %wim;
 
 #define TRAP(H) \
 	mov	%psr, %l0; \
@@ -42,10 +42,10 @@
 	nop; nop;
 
 #define TRAPI(ilevel) \
-	mov 	ilevel, %l7; \
-	mov 	%psr, %l0; \
-	b 	_irq_entry; \
-	mov 	%wim, %l3
+	mov	ilevel, %l7; \
+	mov	%psr, %l0; \
+	b	_irq_entry; \
+	mov	%wim, %l3
 
 /* Unexcpected trap will halt the processor by forcing it to error state */
 #undef BAD_TRAP
@@ -76,7 +76,7 @@ MINFRAME = (WINDOWSIZE + ARGPUSHSIZE + 4)
 #define SA(X)	(((X)+(STACK_ALIGN-1)) & ~(STACK_ALIGN-1))
 
 	.section ".start", "ax"
-	.globl 	_start, start, _trap_table
+	.globl	_start, start, _trap_table
 	.globl  _irq_entry, nmi_trap
 	.globl  _reset_reloc
 
@@ -118,7 +118,7 @@ _trap_table:
 	TRAPI(13);			! 1d IRQ level 13
 	TRAPI(14);			! 1e IRQ level 14
 	TRAP(_nmi_trap);		! 1f IRQ level 15 /
-	                		! NMI (non maskable interrupt)
+					! NMI (non maskable interrupt)
 	BAD_TRAP;			! 20 r_register_access_error
 	BAD_TRAP;			! 21 instruction access error
 	BAD_TRAP;			! 22
@@ -470,7 +470,7 @@ _window_underflow:
 	nop; nop; nop
 	restore				! Two restores to get into the
 	restore				! window to restore
-	ld	[%sp + 0], %l0; 	! Restore window from the stack
+	ld	[%sp + 0], %l0;		! Restore window from the stack
 	ld	[%sp + 4], %l1;
 	ld	[%sp + 8], %l2;
 	ld	[%sp + 12], %l3;
@@ -502,7 +502,7 @@ _hwerr:
 	ta 0
 	nop
 	nop
-	b _hwerr 			! loop infinite
+	b _hwerr			! loop infinite
 	nop
 
 /* Registers to not touch at all. */
diff --git a/cpu/lh7a40x/start.S b/cpu/lh7a40x/start.S
index fb748cffc6..e4655d69b1 100644
--- a/cpu/lh7a40x/start.S
+++ b/cpu/lh7a40x/start.S
@@ -184,7 +184,7 @@ clear_bss:
 	@add	r0, r0, #4		/* start at first byte of bss       */
 					/*   why inc. 4 bytes past then?    */
 	ldr	r1, _bss_end		/* stop here                        */
-	mov 	r2, #0x00000000		/* clear                            */
+	mov	r2, #0x00000000		/* clear                            */
 
 clbss_l:str	r2, [r0]		/* clear loop...                    */
 	add	r0, r0, #4
@@ -347,31 +347,31 @@ cpu_init_crit:
 undefined_instruction:
 	get_bad_stack
 	bad_save_user_regs
-	bl 	do_undefined_instruction
+	bl	do_undefined_instruction
 
 	.align	5
 software_interrupt:
 	get_bad_stack
 	bad_save_user_regs
-	bl 	do_software_interrupt
+	bl	do_software_interrupt
 
 	.align	5
 prefetch_abort:
 	get_bad_stack
 	bad_save_user_regs
-	bl 	do_prefetch_abort
+	bl	do_prefetch_abort
 
 	.align	5
 data_abort:
 	get_bad_stack
 	bad_save_user_regs
-	bl 	do_data_abort
+	bl	do_data_abort
 
 	.align	5
 not_used:
 	get_bad_stack
 	bad_save_user_regs
-	bl 	do_not_used
+	bl	do_not_used
 
 #ifdef CONFIG_USE_IRQ
 
@@ -379,7 +379,7 @@ not_used:
 irq:
 	get_irq_stack
 	irq_save_user_regs
-	bl 	do_irq
+	bl	do_irq
 	irq_restore_user_regs
 
 	.align	5
@@ -387,7 +387,7 @@ fiq:
 	get_fiq_stack
 	/* someone ought to write a more effiction fiq_save_user_regs */
 	irq_save_user_regs
-	bl 	do_fiq
+	bl	do_fiq
 	irq_restore_user_regs
 
 #else
@@ -396,13 +396,13 @@ fiq:
 irq:
 	get_bad_stack
 	bad_save_user_regs
-	bl 	do_irq
+	bl	do_irq
 
 	.align	5
 fiq:
 	get_bad_stack
 	bad_save_user_regs
-	bl 	do_fiq
+	bl	do_fiq
 
 #endif
 
diff --git a/cpu/mcf523x/start.S b/cpu/mcf523x/start.S
index ad04c0984a..2b638dfef2 100644
--- a/cpu/mcf523x/start.S
+++ b/cpu/mcf523x/start.S
@@ -49,7 +49,7 @@
 _vectors:
 
 INITSP:		.long	0x00000000	/* Initial SP	*/
-INITPC:		.long	_START	/* Initial PC 		*/
+INITPC:		.long	_START	/* Initial PC		*/
 vector02:	.long	_FAULT	/* Access Error		*/
 vector03:	.long	_FAULT	/* Address Error	*/
 vector04:	.long	_FAULT	/* Illegal Instruction	*/
diff --git a/cpu/mcf52x2/start.S b/cpu/mcf52x2/start.S
index 2bc0df39ca..a05490432f 100644
--- a/cpu/mcf52x2/start.S
+++ b/cpu/mcf52x2/start.S
@@ -248,14 +248,14 @@ relocate_code:
  * We are done. Do not return, instead branch to second part of board
  * initialization, now running from RAM.
  */
- 	move.l	%a0, %a1
+	move.l	%a0, %a1
 	add.l	#(in_ram - CFG_MONITOR_BASE), %a1
 	jmp	(%a1)
 
 in_ram:
 
 clear_bss:
- 	/*
+	/*
 	 * Now clear BSS segment
 	 */
 	move.l	%a0, %a1
@@ -416,7 +416,7 @@ icache_enable:
 	 *  Note: The 5249 Documentation doesn't give a bit position for CINV!
 	 *  From the 5272 and the 5307 documentation, I have deduced that it is
 	 *  probably CACR[24]. Should someone say something to Motorola?
-	 *  	~Jeremy
+	 *	~Jeremy
 	 */
 	move.l	#0x01000000, %d0		/* Invalidate whole cache */
 	move.c	%d0,%CACR
diff --git a/cpu/mcf532x/start.S b/cpu/mcf532x/start.S
index a524f70783..c806f7a96e 100644
--- a/cpu/mcf532x/start.S
+++ b/cpu/mcf532x/start.S
@@ -49,7 +49,7 @@
 _vectors:
 
 INITSP:		.long	0x00000000	/* Initial SP	*/
-INITPC:		.long	_START	/* Initial PC 		*/
+INITPC:		.long	_START	/* Initial PC		*/
 vector02:	.long	_FAULT	/* Access Error		*/
 vector03:	.long	_FAULT	/* Address Error	*/
 vector04:	.long	_FAULT	/* Illegal Instruction	*/
diff --git a/cpu/mcf5445x/start.S b/cpu/mcf5445x/start.S
index 0c5194acdb..3241b278e1 100644
--- a/cpu/mcf5445x/start.S
+++ b/cpu/mcf5445x/start.S
@@ -54,7 +54,7 @@
 _vectors:
 
 INITSP:		.long	0x00000000	/* Initial SP	*/
-INITPC:		.long	_START	/* Initial PC 		*/
+INITPC:		.long	_START	/* Initial PC		*/
 vector02:	.long	_FAULT	/* Access Error		*/
 vector03:	.long	_FAULT	/* Address Error	*/
 vector04:	.long	_FAULT	/* Illegal Instruction	*/
diff --git a/cpu/mcf547x_8x/start.S b/cpu/mcf547x_8x/start.S
index c12d7a0fcb..8b8708d030 100644
--- a/cpu/mcf547x_8x/start.S
+++ b/cpu/mcf547x_8x/start.S
@@ -54,7 +54,7 @@
 _vectors:
 
 INITSP:		.long	0x00000000	/* Initial SP	*/
-INITPC:		.long	_START	/* Initial PC 		*/
+INITPC:		.long	_START	/* Initial PC		*/
 vector02:	.long	_FAULT	/* Access Error		*/
 vector03:	.long	_FAULT	/* Address Error	*/
 vector04:	.long	_FAULT	/* Illegal Instruction	*/
diff --git a/cpu/mips/asc_serial.c b/cpu/mips/asc_serial.c
index d95ec3fd2f..3498b61e8b 100644
--- a/cpu/mips/asc_serial.c
+++ b/cpu/mips/asc_serial.c
@@ -34,10 +34,10 @@
 
 /* Interrupt status register bits */
 #define FBS_ISR_AT	0x00000040	/* ASC transmit interrupt */
-#define FBS_ISR_AR 	0x00000020	/* ASC receive interrupt */
+#define FBS_ISR_AR	0x00000020	/* ASC receive interrupt */
 #define FBS_ISR_AE	0x00000010	/* ASC error interrupt */
 #define FBS_ISR_AB	0x00000008	/* ASC transmit buffer interrupt */
-#define FBS_ISR_AS      0x00000004 	/* ASC start of autobaud detection interrupt */
+#define FBS_ISR_AS      0x00000004	/* ASC start of autobaud detection interrupt */
 #define FBS_ISR_AF	0x00000002	/* ASC end of autobaud detection interrupt */
 
 #else
diff --git a/cpu/mips/au1x00_usb_ohci.h b/cpu/mips/au1x00_usb_ohci.h
index 4ef06ffdeb..631ef0a227 100644
--- a/cpu/mips/au1x00_usb_ohci.h
+++ b/cpu/mips/au1x00_usb_ohci.h
@@ -11,31 +11,31 @@
 static int cc_to_error[16] = {
 
 /* mapping of the OHCI CC status to error codes */
-	/* No  Error  */               0,
-	/* CRC Error  */               USB_ST_CRC_ERR,
-	/* Bit Stuff  */               USB_ST_BIT_ERR,
-	/* Data Togg  */               USB_ST_CRC_ERR,
-	/* Stall      */               USB_ST_STALLED,
-	/* DevNotResp */               -1,
-	/* PIDCheck   */               USB_ST_BIT_ERR,
-	/* UnExpPID   */               USB_ST_BIT_ERR,
-	/* DataOver   */               USB_ST_BUF_ERR,
-	/* DataUnder  */               USB_ST_BUF_ERR,
-	/* reservd    */               -1,
-	/* reservd    */               -1,
-	/* BufferOver */               USB_ST_BUF_ERR,
-	/* BuffUnder  */               USB_ST_BUF_ERR,
-	/* Not Access */               -1,
-	/* Not Access */               -1
+	/* No  Error  */	0,
+	/* CRC Error  */	USB_ST_CRC_ERR,
+	/* Bit Stuff  */	USB_ST_BIT_ERR,
+	/* Data Togg  */	USB_ST_CRC_ERR,
+	/* Stall      */	USB_ST_STALLED,
+	/* DevNotResp */	-1,
+	/* PIDCheck   */	USB_ST_BIT_ERR,
+	/* UnExpPID   */	USB_ST_BIT_ERR,
+	/* DataOver   */	USB_ST_BUF_ERR,
+	/* DataUnder  */	USB_ST_BUF_ERR,
+	/* reservd    */	-1,
+	/* reservd    */	-1,
+	/* BufferOver */	USB_ST_BUF_ERR,
+	/* BuffUnder  */	USB_ST_BUF_ERR,
+	/* Not Access */	-1,
+	/* Not Access */	-1
 };
 
 /* ED States */
 
-#define ED_NEW 		0x00
-#define ED_UNLINK 	0x01
+#define ED_NEW		0x00
+#define ED_UNLINK	0x01
 #define ED_OPER		0x02
 #define ED_DEL		0x04
-#define ED_URB_DEL  	0x08
+#define ED_URB_DEL	0x08
 
 /* usb_ohci_ed */
 struct ed {
@@ -61,54 +61,54 @@ typedef struct ed ed_t;
 
 
 /* TD info field */
-#define TD_CC       0xf0000000
-#define TD_CC_GET(td_p) ((td_p >>28) & 0x0f)
-#define TD_CC_SET(td_p, cc) (td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28)
-#define TD_EC       0x0C000000
-#define TD_T        0x03000000
-#define TD_T_DATA0  0x02000000
-#define TD_T_DATA1  0x03000000
-#define TD_T_TOGGLE 0x00000000
-#define TD_R        0x00040000
-#define TD_DI       0x00E00000
-#define TD_DI_SET(X) (((X) & 0x07)<< 21)
-#define TD_DP       0x00180000
-#define TD_DP_SETUP 0x00000000
-#define TD_DP_IN    0x00100000
-#define TD_DP_OUT   0x00080000
-
-#define TD_ISO	    0x00010000
-#define TD_DEL      0x00020000
+#define TD_CC			0xf0000000
+#define TD_CC_GET(td_p)		((td_p >>28) & 0x0f)
+#define TD_CC_SET(td_p, cc)	(td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28)
+#define TD_EC			0x0C000000
+#define TD_T			0x03000000
+#define TD_T_DATA0		0x02000000
+#define TD_T_DATA1		0x03000000
+#define TD_T_TOGGLE		0x00000000
+#define TD_R			0x00040000
+#define TD_DI			0x00E00000
+#define TD_DI_SET(X)		(((X) & 0x07)<< 21)
+#define TD_DP			0x00180000
+#define TD_DP_SETUP		0x00000000
+#define TD_DP_IN		0x00100000
+#define TD_DP_OUT		0x00080000
+
+#define TD_ISO			0x00010000
+#define TD_DEL			0x00020000
 
 /* CC Codes */
-#define TD_CC_NOERROR      0x00
-#define TD_CC_CRC          0x01
-#define TD_CC_BITSTUFFING  0x02
-#define TD_CC_DATATOGGLEM  0x03
-#define TD_CC_STALL        0x04
-#define TD_DEVNOTRESP      0x05
-#define TD_PIDCHECKFAIL    0x06
-#define TD_UNEXPECTEDPID   0x07
-#define TD_DATAOVERRUN     0x08
-#define TD_DATAUNDERRUN    0x09
-#define TD_BUFFEROVERRUN   0x0C
-#define TD_BUFFERUNDERRUN  0x0D
-#define TD_NOTACCESSED     0x0F
+#define TD_CC_NOERROR		0x00
+#define TD_CC_CRC		0x01
+#define TD_CC_BITSTUFFING	0x02
+#define TD_CC_DATATOGGLEM	0x03
+#define TD_CC_STALL		0x04
+#define TD_DEVNOTRESP		0x05
+#define TD_PIDCHECKFAIL		0x06
+#define TD_UNEXPECTEDPID	0x07
+#define TD_DATAOVERRUN		0x08
+#define TD_DATAUNDERRUN		0x09
+#define TD_BUFFEROVERRUN	0x0C
+#define TD_BUFFERUNDERRUN	0x0D
+#define TD_NOTACCESSED		0x0F
 
 
 #define MAXPSW 1
 
 struct td {
 	__u32 hwINFO;
-  	__u32 hwCBP;		/* Current Buffer Pointer */
-  	__u32 hwNextTD;		/* Next TD Pointer */
-  	__u32 hwBE;		/* Memory Buffer End Pointer */
-
-  	__u16 hwPSW[MAXPSW];
-  	__u8 unused;
-  	__u8 index;
-  	struct ed *ed;
-  	struct td *next_dl_td;
+	__u32 hwCBP;		/* Current Buffer Pointer */
+	__u32 hwNextTD;		/* Next TD Pointer */
+	__u32 hwBE;		/* Memory Buffer End Pointer */
+
+	__u16 hwPSW[MAXPSW];
+	__u8 unused;
+	__u8 index;
+	struct ed *ed;
+	struct td *next_dl_td;
 	struct usb_device *usb_dev;
 	int transfer_len;
 	__u32 data;
@@ -142,7 +142,7 @@ struct ohci_hcca {
 
 /*
  * This is the structure of the OHCI controller's memory mapped I/O
- * region.  This is Memory Mapped I/O.  You must use the readl() and
+ * region.  This is Memory Mapped I/O.	You must use the readl() and
  * writel() macros defined in asm/io.h to access these!!
  */
 struct ohci_regs {
@@ -202,10 +202,10 @@ struct ohci_regs {
  * HcCommandStatus (cmdstatus) register masks
  */
 #define OHCI_HCR	(1 << 0)	/* host controller reset */
-#define OHCI_CLF  	(1 << 1)	/* control list filled */
-#define OHCI_BLF  	(1 << 2)	/* bulk list filled */
-#define OHCI_OCR  	(1 << 3)	/* ownership change request */
-#define OHCI_SOC  	(3 << 16)	/* scheduling overrun count */
+#define OHCI_CLF	(1 << 1)	/* control list filled */
+#define OHCI_BLF	(1 << 2)	/* bulk list filled */
+#define OHCI_OCR	(1 << 3)	/* ownership change request */
+#define OHCI_SOC	(3 << 16)	/* scheduling overrun count */
 
 /*
  * masks used with interrupt registers:
@@ -236,101 +236,101 @@ struct virt_root_hub {
 /* USB HUB CONSTANTS (not OHCI-specific; see hub.h) */
 
 /* destination of request */
-#define RH_INTERFACE               0x01
-#define RH_ENDPOINT                0x02
-#define RH_OTHER                   0x03
+#define RH_INTERFACE		0x01
+#define RH_ENDPOINT		0x02
+#define RH_OTHER		0x03
 
-#define RH_CLASS                   0x20
-#define RH_VENDOR                  0x40
+#define RH_CLASS		0x20
+#define RH_VENDOR		0x40
 
 /* Requests: bRequest << 8 | bmRequestType */
-#define RH_GET_STATUS           0x0080
-#define RH_CLEAR_FEATURE        0x0100
-#define RH_SET_FEATURE          0x0300
+#define RH_GET_STATUS		0x0080
+#define RH_CLEAR_FEATURE	0x0100
+#define RH_SET_FEATURE		0x0300
 #define RH_SET_ADDRESS		0x0500
 #define RH_GET_DESCRIPTOR	0x0680
-#define RH_SET_DESCRIPTOR       0x0700
+#define RH_SET_DESCRIPTOR	0x0700
 #define RH_GET_CONFIGURATION	0x0880
 #define RH_SET_CONFIGURATION	0x0900
-#define RH_GET_STATE            0x0280
-#define RH_GET_INTERFACE        0x0A80
-#define RH_SET_INTERFACE        0x0B00
-#define RH_SYNC_FRAME           0x0C80
+#define RH_GET_STATE		0x0280
+#define RH_GET_INTERFACE	0x0A80
+#define RH_SET_INTERFACE	0x0B00
+#define RH_SYNC_FRAME		0x0C80
 /* Our Vendor Specific Request */
-#define RH_SET_EP               0x2000
+#define RH_SET_EP		0x2000
 
 
 /* Hub port features */
-#define RH_PORT_CONNECTION         0x00
-#define RH_PORT_ENABLE             0x01
-#define RH_PORT_SUSPEND            0x02
-#define RH_PORT_OVER_CURRENT       0x03
-#define RH_PORT_RESET              0x04
-#define RH_PORT_POWER              0x08
-#define RH_PORT_LOW_SPEED          0x09
-
-#define RH_C_PORT_CONNECTION       0x10
-#define RH_C_PORT_ENABLE           0x11
-#define RH_C_PORT_SUSPEND          0x12
-#define RH_C_PORT_OVER_CURRENT     0x13
-#define RH_C_PORT_RESET            0x14
+#define RH_PORT_CONNECTION	0x00
+#define RH_PORT_ENABLE		0x01
+#define RH_PORT_SUSPEND		0x02
+#define RH_PORT_OVER_CURRENT	0x03
+#define RH_PORT_RESET		0x04
+#define RH_PORT_POWER		0x08
+#define RH_PORT_LOW_SPEED	0x09
+
+#define RH_C_PORT_CONNECTION	0x10
+#define RH_C_PORT_ENABLE	0x11
+#define RH_C_PORT_SUSPEND	0x12
+#define RH_C_PORT_OVER_CURRENT	0x13
+#define RH_C_PORT_RESET		0x14
 
 /* Hub features */
-#define RH_C_HUB_LOCAL_POWER       0x00
-#define RH_C_HUB_OVER_CURRENT      0x01
+#define RH_C_HUB_LOCAL_POWER	0x00
+#define RH_C_HUB_OVER_CURRENT	0x01
 
-#define RH_DEVICE_REMOTE_WAKEUP    0x00
-#define RH_ENDPOINT_STALL          0x01
+#define RH_DEVICE_REMOTE_WAKEUP 0x00
+#define RH_ENDPOINT_STALL	0x01
 
-#define RH_ACK                     0x01
-#define RH_REQ_ERR                 -1
-#define RH_NACK                    0x00
+#define RH_ACK			0x01
+#define RH_REQ_ERR		-1
+#define RH_NACK			0x00
 
 
 /* OHCI ROOT HUB REGISTER MASKS */
 
 /* roothub.portstatus [i] bits */
-#define RH_PS_CCS            0x00000001   	/* current connect status */
-#define RH_PS_PES            0x00000002   	/* port enable status*/
-#define RH_PS_PSS            0x00000004   	/* port suspend status */
-#define RH_PS_POCI           0x00000008   	/* port over current indicator */
-#define RH_PS_PRS            0x00000010  	/* port reset status */
-#define RH_PS_PPS            0x00000100   	/* port power status */
-#define RH_PS_LSDA           0x00000200    	/* low speed device attached */
-#define RH_PS_CSC            0x00010000 	/* connect status change */
-#define RH_PS_PESC           0x00020000   	/* port enable status change */
-#define RH_PS_PSSC           0x00040000    	/* port suspend status change */
-#define RH_PS_OCIC           0x00080000    	/* over current indicator change */
-#define RH_PS_PRSC           0x00100000   	/* port reset status change */
+#define RH_PS_CCS		0x00000001	/* current connect status */
+#define RH_PS_PES		0x00000002	/* port enable status*/
+#define RH_PS_PSS		0x00000004	/* port suspend status */
+#define RH_PS_POCI		0x00000008	/* port over current indicator */
+#define RH_PS_PRS		0x00000010	/* port reset status */
+#define RH_PS_PPS		0x00000100	/* port power status */
+#define RH_PS_LSDA		0x00000200	/* low speed device attached */
+#define RH_PS_CSC		0x00010000	/* connect status change */
+#define RH_PS_PESC		0x00020000	/* port enable status change */
+#define RH_PS_PSSC		0x00040000	/* port suspend status change */
+#define RH_PS_OCIC		0x00080000	/* over current indicator change */
+#define RH_PS_PRSC		0x00100000	/* port reset status change */
 
 /* roothub.status bits */
-#define RH_HS_LPS	     0x00000001		/* local power status */
-#define RH_HS_OCI	     0x00000002		/* over current indicator */
-#define RH_HS_DRWE	     0x00008000		/* device remote wakeup enable */
-#define RH_HS_LPSC	     0x00010000		/* local power status change */
-#define RH_HS_OCIC	     0x00020000		/* over current indicator change */
-#define RH_HS_CRWE	     0x80000000		/* clear remote wakeup enable */
+#define RH_HS_LPS		0x00000001	/* local power status */
+#define RH_HS_OCI		0x00000002	/* over current indicator */
+#define RH_HS_DRWE		0x00008000	/* device remote wakeup enable */
+#define RH_HS_LPSC		0x00010000	/* local power status change */
+#define RH_HS_OCIC		0x00020000	/* over current indicator change */
+#define RH_HS_CRWE		0x80000000	/* clear remote wakeup enable */
 
 /* roothub.b masks */
-#define RH_B_DR		0x0000ffff		/* device removable flags */
-#define RH_B_PPCM	0xffff0000		/* port power control mask */
+#define RH_B_DR			0x0000ffff	/* device removable flags */
+#define RH_B_PPCM		0xffff0000	/* port power control mask */
 
 /* roothub.a masks */
-#define	RH_A_NDP	(0xff << 0)		/* number of downstream ports */
-#define	RH_A_PSM	(1 << 8)		/* power switching mode */
-#define	RH_A_NPS	(1 << 9)		/* no power switching */
-#define	RH_A_DT		(1 << 10)		/* device type (mbz) */
-#define	RH_A_OCPM	(1 << 11)		/* over current protection mode */
-#define	RH_A_NOCP	(1 << 12)		/* no over current protection */
-#define	RH_A_POTPGT	(0xff << 24)		/* power on to power good time */
+#define	RH_A_NDP		(0xff << 0)	/* number of downstream ports */
+#define	RH_A_PSM		(1 << 8)	/* power switching mode */
+#define	RH_A_NPS		(1 << 9)	/* no power switching */
+#define	RH_A_DT			(1 << 10)	/* device type (mbz) */
+#define	RH_A_OCPM		(1 << 11)	/* over current protection mode */
+#define	RH_A_NOCP		(1 << 12)	/* no over current protection */
+#define	RH_A_POTPGT		(0xff << 24)	/* power on to power good time */
 
 /* urb */
 #define N_URB_TD 48
 typedef struct
 {
 	ed_t *ed;
-	__u16 length;	/* number of tds associated with this request */
-	__u16 td_cnt;	/* number of tds already serviced */
+	__u16 length;		/* number of tds associated with this request */
+	__u16 td_cnt;		/* number of tds already serviced */
 	int   state;
 	unsigned long pipe;
 	int actual_length;
@@ -355,11 +355,11 @@ typedef struct ohci {
 	int sleeping;
 	unsigned long flags;		/* for HC bugs */
 
-	struct ohci_regs *regs;	/* OHCI controller's memory */
+	struct ohci_regs *regs;		/* OHCI controller's memory */
 
-	ed_t *ed_rm_list[2];     /* lists of all endpoints to be removed */
-	ed_t *ed_bulktail;       /* last endpoint of bulk list */
-	ed_t *ed_controltail;    /* last endpoint of control list */
+	ed_t *ed_rm_list[2];		/* lists of all endpoints to be removed */
+	ed_t *ed_bulktail;		/* last endpoint of bulk list */
+	ed_t *ed_controltail;		/* last endpoint of control list */
 	int intrstatus;
 	__u32 hc_control;		/* copy of the hc control reg */
 	struct usb_device *dev[32];
@@ -371,7 +371,7 @@ typedef struct ohci {
 #define NUM_EDS 8		/* num of preallocated endpoint descriptors */
 
 struct ohci_device {
-	ed_t 	ed[NUM_EDS];
+	ed_t	ed[NUM_EDS];
 	int ed_cnt;
 };
 
diff --git a/cpu/mips/incaip_wdt.S b/cpu/mips/incaip_wdt.S
index 2ebcc91139..329386bd33 100644
--- a/cpu/mips/incaip_wdt.S
+++ b/cpu/mips/incaip_wdt.S
@@ -51,7 +51,7 @@ disable_incaip_wdt:
 	and	t3, 0xFFFFFF01
 
 	or	t3, t2
-	or 	t3, 0xF0
+	or	t3, 0xF0
 
 	sw	t3, WD_CON0(t0)		/* write password */
 
diff --git a/cpu/mips/start.S b/cpu/mips/start.S
index 947128dd81..d881879d77 100644
--- a/cpu/mips/start.S
+++ b/cpu/mips/start.S
@@ -345,7 +345,7 @@ relocate_code:
 	jr	t0
 	nop
 
-	.word 	_gp
+	.word	_gp
 	.word	_GLOBAL_OFFSET_TABLE_
 	.word	uboot_end_data
 	.word	uboot_end
diff --git a/cpu/mpc512x/start.S b/cpu/mpc512x/start.S
index 5a9d8687f5..fb8acb5df6 100644
--- a/cpu/mpc512x/start.S
+++ b/cpu/mpc512x/start.S
@@ -219,7 +219,7 @@ boot_cold:
 	 * The SRAM window has a fixed size (256K), so only the start address
 	 * is necessary
 	 */
-	lis 	r4, START_REG(CFG_SRAM_BASE) & 0xff00
+	lis	r4, START_REG(CFG_SRAM_BASE) & 0xff00
 	stw	r4, SRAMBAR(r3)
 
 	/*
diff --git a/cpu/mpc5xx/config.mk b/cpu/mpc5xx/config.mk
index 6d66c32bee..157ddc5491 100644
--- a/cpu/mpc5xx/config.mk
+++ b/cpu/mpc5xx/config.mk
@@ -28,7 +28,7 @@
 #
 
 
-PLATFORM_RELFLAGS += 	-fPIC -ffixed-r14 -meabi
+PLATFORM_RELFLAGS +=	-fPIC -ffixed-r14 -meabi
 
 PLATFORM_CPPFLAGS +=	-DCONFIG_5xx -ffixed-r2 -mpowerpc -msoft-float
 
diff --git a/cpu/mpc5xx/cpu_init.c b/cpu/mpc5xx/cpu_init.c
index f4cd24bf7c..5bbb7986b4 100644
--- a/cpu/mpc5xx/cpu_init.c
+++ b/cpu/mpc5xx/cpu_init.c
@@ -23,7 +23,7 @@
  * File:		cpu_init.c
  *
  * Discription:		Contains initialisation functions to setup
- *    			the cpu properly
+ *			the cpu properly
  *
  */
 
@@ -118,6 +118,6 @@ void cpu_init_f (volatile immap_t * immr)
  */
 int cpu_init_r (void)
 {
-  	/* Nothing to do at the moment */
+	/* Nothing to do at the moment */
 	return (0);
 }
diff --git a/cpu/mpc5xx/serial.c b/cpu/mpc5xx/serial.c
index ac5556f05c..39f57a1210 100644
--- a/cpu/mpc5xx/serial.c
+++ b/cpu/mpc5xx/serial.c
@@ -24,8 +24,8 @@
  * File:		serial.c
  *
  * Discription:		Serial interface driver for SCI1 and SCI2.
- *     			Since this code will be called from ROM use
- * 			only non-static local variables.
+ *			Since this code will be called from ROM use
+ *			only non-static local variables.
  *
  */
 
diff --git a/cpu/mpc5xx/speed.c b/cpu/mpc5xx/speed.c
index 6a1fa155e2..7b7c5b9619 100644
--- a/cpu/mpc5xx/speed.c
+++ b/cpu/mpc5xx/speed.c
@@ -49,8 +49,8 @@ int get_clocks (void)
 	if(immr->im_clkrst.car_plprcr & PLPRCR_CSRC_MSK) {
 		gd->cpu_clk = vcoout / (2^(((immr->im_clkrst.car_sccr & SCCR_DFNL_MSK) >> SCCR_DFNL_SHIFT) + 1));
 	} else {
-    		gd->cpu_clk = vcoout / (2^(immr->im_clkrst.car_sccr & SCCR_DFNH_MSK));
-    	}
+		gd->cpu_clk = vcoout / (2^(immr->im_clkrst.car_sccr & SCCR_DFNH_MSK));
+	}
 
 #else /* CONFIG_5xx_GCLK_FREQ */
 	gd->bus_clk = CONFIG_5xx_GCLK_FREQ;
diff --git a/cpu/mpc5xx/spi.c b/cpu/mpc5xx/spi.c
index 81c9ddbd4e..3c187bee59 100644
--- a/cpu/mpc5xx/spi.c
+++ b/cpu/mpc5xx/spi.c
@@ -208,9 +208,9 @@ void spi_init_f (void)
 	 * Setup RAM
 	 */
 	for(i=0;i<32;i++) {
-	 	 qsmcm->qsmcm_recram[i]=0x0000;
-	 	 qsmcm->qsmcm_tranram[i]=0x0000;
-	 	 qsmcm->qsmcm_comdram[i]=0x00;
+		 qsmcm->qsmcm_recram[i]=0x0000;
+		 qsmcm->qsmcm_tranram[i]=0x0000;
+		 qsmcm->qsmcm_comdram[i]=0x00;
 	}
 	return;
 }
@@ -238,9 +238,9 @@ ssize_t short_spi_write (uchar *addr, int alen, uchar *buffer, int len)
 	immr = (immap_t *)  CFG_IMMR;
 	qsmcm = (qsmcm5xx_t *)&immr->im_qsmcm;
 	for(i=0;i<32;i++) {
-	 	 qsmcm->qsmcm_recram[i]=0x0000;
-	 	 qsmcm->qsmcm_tranram[i]=0x0000;
-	 	 qsmcm->qsmcm_comdram[i]=0x00;
+		 qsmcm->qsmcm_recram[i]=0x0000;
+		 qsmcm->qsmcm_tranram[i]=0x0000;
+		 qsmcm->qsmcm_comdram[i]=0x00;
 	}
 	qsmcm->qsmcm_tranram[0] =  SPI_EEPROM_WREN; /* write enable */
 	spi_xfer(1);
@@ -312,9 +312,9 @@ ssize_t short_spi_read (uchar *addr, int alen, uchar *buffer, int len)
 	qsmcm = (qsmcm5xx_t *)&immr->im_qsmcm;
 
 	for(i=0;i<32;i++) {
-	 	 qsmcm->qsmcm_recram[i]=0x0000;
-	 	 qsmcm->qsmcm_tranram[i]=0x0000;
-	 	 qsmcm->qsmcm_comdram[i]=0x00;
+		 qsmcm->qsmcm_recram[i]=0x0000;
+		 qsmcm->qsmcm_tranram[i]=0x0000;
+		 qsmcm->qsmcm_comdram[i]=0x00;
 	}
 	i=0;
 	qsmcm->qsmcm_tranram[i++] = (SPI_EEPROM_READ); /* READ memory array */
diff --git a/cpu/mpc5xx/traps.c b/cpu/mpc5xx/traps.c
index d22b89a1f5..78c820ae7e 100644
--- a/cpu/mpc5xx/traps.c
+++ b/cpu/mpc5xx/traps.c
@@ -223,8 +223,8 @@ void UnknownException(struct pt_regs *regs)
 void DebugException(struct pt_regs *regs)
 {
 	printf("Debugger trap at @ %lx\n", regs->nip );
-  	show_regs(regs);
+	show_regs(regs);
 #if defined(CONFIG_CMD_BEDBUG)
-  	do_bedbug_breakpoint( regs );
+	do_bedbug_breakpoint( regs );
 #endif
 }
diff --git a/cpu/mpc5xx/u-boot.lds b/cpu/mpc5xx/u-boot.lds
index 386a6e01f4..7434e3fb62 100644
--- a/cpu/mpc5xx/u-boot.lds
+++ b/cpu/mpc5xx/u-boot.lds
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/cpu/mpc5xxx/fec.c b/cpu/mpc5xxx/fec.c
index 2aded1a5f1..82640ab771 100644
--- a/cpu/mpc5xxx/fec.c
+++ b/cpu/mpc5xxx/fec.c
@@ -884,7 +884,7 @@ int mpc5xxx_fec_initialize(bd_t * bis)
 
 	fec = (mpc5xxx_fec_priv *)malloc(sizeof(*fec));
 	dev = (struct eth_device *)malloc(sizeof(*dev));
-   	memset(dev, 0, sizeof *dev);
+	memset(dev, 0, sizeof *dev);
 
 	fec->eth = (ethernet_regs *)MPC5XXX_FEC;
 	fec->tbdBase = (FEC_TBD *)FEC_BD_BASE;
diff --git a/cpu/mpc5xxx/u-boot-customlayout.lds b/cpu/mpc5xxx/u-boot-customlayout.lds
index bbb6cf8e04..38478601ab 100644
--- a/cpu/mpc5xxx/u-boot-customlayout.lds
+++ b/cpu/mpc5xxx/u-boot-customlayout.lds
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/cpu/mpc5xxx/u-boot.lds b/cpu/mpc5xxx/u-boot.lds
index db6c6f29a0..13fffb808f 100644
--- a/cpu/mpc5xxx/u-boot.lds
+++ b/cpu/mpc5xxx/u-boot.lds
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/cpu/mpc8220/u-boot.lds b/cpu/mpc8220/u-boot.lds
index ff4f3dce20..e34a9d4842 100644
--- a/cpu/mpc8220/u-boot.lds
+++ b/cpu/mpc8220/u-boot.lds
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/cpu/mpc824x/drivers/epic/epic2.S b/cpu/mpc824x/drivers/epic/epic2.S
index 8cc2fc60bb..52d19aae8e 100644
--- a/cpu/mpc824x/drivers/epic/epic2.S
+++ b/cpu/mpc824x/drivers/epic/epic2.S
@@ -169,7 +169,7 @@ epic_exception:
 	xor	r3,r3,r3
     xor r4,r4,r4
 	or    r3, r3, r6        /*  eumbbar in r3 */
-	andi. r4,r7,0x00ff   	/* Mask off bits, vector in r4 */
+	andi. r4,r7,0x00ff	/* Mask off bits, vector in r4 */
 
     stw     r4,0x04(r1)     /* save the vector value */
 
diff --git a/cpu/mpc824x/drivers/errors.h b/cpu/mpc824x/drivers/errors.h
index 887f284fc4..20794a2e89 100644
--- a/cpu/mpc824x/drivers/errors.h
+++ b/cpu/mpc824x/drivers/errors.h
@@ -61,7 +61,7 @@ to standardize the error handling in the current project */
    message back to the user.
 */
 /*----------------------------------------------------------------------*/
-/* these are specifically for the parser routines 			*/
+/* these are specifically for the parser routines			*/
 
 #define UNKNOWN_COMMAND		0xfb00 /* "unrecognized command " */
 #define UNKNOWN_REGISTER	0xfb01 /* "unknown register "*/
@@ -73,8 +73,8 @@ to standardize the error handling in the current project */
 #define UNIMPLEMENTED_STAGE	0xfb05 /* invalid rd or rmm parameter format */
 #define REG_NOT_WRITEABLE	0xfb06 /* "unknown operator in arguements"*/
 #define INVALID_FILENAME	0xfb07 /* "invalid download filename" */
-#define INVALID_BAUD_RATE	0xfb08 	/* invalid baud rate from sb command */
-#define UNSUPPORTED_REGISTER	0xfb09 	/* Special register is not supported */
+#define INVALID_BAUD_RATE	0xfb08	/* invalid baud rate from sb command */
+#define UNSUPPORTED_REGISTER	0xfb09	/* Special register is not supported */
 #define FOR_BOARD_ONLY		0xfb0a  /* "Not available for Unix." */
 
 
@@ -140,20 +140,20 @@ to standardize the error handling in the current project */
 #define INVALID_FLAG		0xfd0c	/* invalid flag */
 
 /*----------------------------------------------------------------------*/
-/* these are for the getarg toolbox 					*/
+/* these are for the getarg toolbox					*/
 
-#define INVALID_NUMBER_ARGS 	0xFE00 /* invalid number of commd arguements */
+#define INVALID_NUMBER_ARGS	0xFE00 /* invalid number of commd arguements */
 #define UNKNOWN_PARAMETER	0xFE01 /* "unknown type of parameter "*/
 
 
 /*----------------------------------------------------------------------*/
-/* these are for the tokenizer toolbox 					*/
+/* these are for the tokenizer toolbox					*/
 
-#define ILLEGAL_CHARACTER 	0xFF00 /* unrecognized char. in input stream*/
-#define TTL_NOT_SORTED 		0xFF01 /* token translation list not sorted */
-#define TTL_NOT_DEFINED 	0xFF02 /* token translation list not assigned*/
-#define INVALID_STRING 		0xFF03 /* unable to extract string from input */
-#define BUFFER_EMPTY 		0xFF04 /* "input buffer is empty" */
+#define ILLEGAL_CHARACTER	0xFF00 /* unrecognized char. in input stream*/
+#define TTL_NOT_SORTED		0xFF01 /* token translation list not sorted */
+#define TTL_NOT_DEFINED		0xFF02 /* token translation list not assigned*/
+#define INVALID_STRING		0xFF03 /* unable to extract string from input */
+#define BUFFER_EMPTY		0xFF04 /* "input buffer is empty" */
 #define INVALID_MODE		0xFF05 /* input buf is in an unrecognized mode*/
 #define TOK_INTERNAL_ERROR	0xFF06 /* "internal tokenizer error" */
 #define TOO_MANY_IBS		0xFF07 /* "too many open input buffers" */
@@ -172,7 +172,7 @@ to standardize the error handling in the current project */
 
 /* THESE are for the downloader */
 
-#define NOT_IN_S_RECORD_FORMAT 	0xf900 /* "not in S-Record Format" */
+#define NOT_IN_S_RECORD_FORMAT	0xf900 /* "not in S-Record Format" */
 #define UNREC_RECORD_TYPE	0xf901 /* "unrecognized record type" */
 #define CONVERSION_ERROR	0xf902 /* "ascii to int conversion error" */
 #define INVALID_MEMORY		0xf903 /* "bad s-record memory address " */
@@ -190,7 +190,7 @@ to standardize the error handling in the current project */
 /* these are for the DUART handling things */
 
 					/* "unrecognized serial port configuration" */
-#define UNKNOWN_PORT_STATE 	0xf700
+#define UNKNOWN_PORT_STATE	0xf700
 
 
 /* these are for the register toolbox */
@@ -208,5 +208,5 @@ to standardize the error handling in the current project */
 
 
 /*----------------------------------------------------------------------*/
-/* these are specifically for the flash routines 			*/
-#define FLASH_ERROR	 	0xf100		/* general flash error */
+/* these are specifically for the flash routines			*/
+#define FLASH_ERROR		0xf100		/* general flash error */
diff --git a/cpu/mpc824x/u-boot.lds b/cpu/mpc824x/u-boot.lds
index 1f2e7d7276..aa3050dbd7 100644
--- a/cpu/mpc824x/u-boot.lds
+++ b/cpu/mpc824x/u-boot.lds
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/cpu/mpc8260/i2c.c b/cpu/mpc8260/i2c.c
index 34bd3897f6..c3af7b6d83 100644
--- a/cpu/mpc8260/i2c.c
+++ b/cpu/mpc8260/i2c.c
@@ -191,10 +191,10 @@ static int i2c_setrate(int hz, int speed)
 
 			if ((diff >= 0) && (diff < bestspeed_diff))
 			{
-				bestspeed_diff 	= diff ;
-				bestspeed_modval 	= modval;
-				bestspeed_brgval 	= brgval;
-				bestspeed_filter 	= filter;
+				bestspeed_diff	= diff ;
+				bestspeed_modval	= modval;
+				bestspeed_brgval	= brgval;
+				bestspeed_filter	= filter;
 			}
 		}
 	}
@@ -242,7 +242,7 @@ void i2c_init(int speed, int slaveadd)
 	/*
 	 * initialise data in dual port ram:
 	 *
-	 * 	  dpaddr -> parameter ram (64 bytes)
+	 *	  dpaddr -> parameter ram (64 bytes)
 	 *         rbase -> rx BD         (NUM_RX_BDS * sizeof(I2C_BD) bytes)
 	 *         tbase -> tx BD         (NUM_TX_BDS * sizeof(I2C_BD) bytes)
 	 *                  tx buffer     (MAX_TX_SPACE bytes)
diff --git a/cpu/mpc8260/speed.h b/cpu/mpc8260/speed.h
index b66393bec5..3f32a143cc 100644
--- a/cpu/mpc8260/speed.h
+++ b/cpu/mpc8260/speed.h
@@ -28,10 +28,10 @@
  * SPEED_TMR3_PS = (GCLK / (16 * SPEED_FCOUNT3)) - 1
  *
  * SPEED_FCOUNT2	timer 2 counting frequency
- * GCLK	      		CPU clock
+ * GCLK			CPU clock
  * SPEED_TMR2_PS	prescaler
  */
-#define SPEED_TMR2_PS  	(250 - 1)	/* divide by 250	*/
+#define SPEED_TMR2_PS	(250 - 1)	/* divide by 250	*/
 
 /*-----------------------------------------------------------------------
  * Timer value for PIT
diff --git a/cpu/mpc8260/u-boot.lds b/cpu/mpc8260/u-boot.lds
index 6f500c42f2..39f2ce9de4 100644
--- a/cpu/mpc8260/u-boot.lds
+++ b/cpu/mpc8260/u-boot.lds
@@ -33,11 +33,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/cpu/mpc83xx/cpu_init.c b/cpu/mpc83xx/cpu_init.c
index fba5b02ece..fb184d816b 100644
--- a/cpu/mpc83xx/cpu_init.c
+++ b/cpu/mpc83xx/cpu_init.c
@@ -218,7 +218,7 @@ void cpu_init_f (volatile immap_t * im)
 	im->sysconf.lblaw[0].bar = CFG_LBLAWBAR0_PRELIM;
 	im->sysconf.lblaw[0].ar = CFG_LBLAWAR0_PRELIM;
 #else
-#error 	CFG_BR0_PRELIM, CFG_OR0_PRELIM, CFG_LBLAWBAR0_PRELIM & CFG_LBLAWAR0_PRELIM must be defined
+#error	CFG_BR0_PRELIM, CFG_OR0_PRELIM, CFG_LBLAWBAR0_PRELIM & CFG_LBLAWAR0_PRELIM must be defined
 #endif
 
 #if defined(CFG_BR1_PRELIM) && defined(CFG_OR1_PRELIM)
diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c
index 70cd410298..76f2474491 100644
--- a/cpu/mpc83xx/spd_sdram.c
+++ b/cpu/mpc83xx/spd_sdram.c
@@ -510,7 +510,7 @@ long int spd_sdram()
 	ddr->timing_cfg_1 =
 	    (((picos_to_clk(spd.trp * 250) & 0x07) << 28 ) |	/* PRETOACT */
 	     ((picos_to_clk(spd.tras * 1000) & 0x0f ) << 24 ) | /* ACTTOPRE */
-	     (trcd_clk << 20 ) |  				/* ACTTORW */
+	     (trcd_clk << 20 ) |				/* ACTTORW */
 	     (caslat_ctrl << 16 ) |				/* CASLAT */
 	     (trfc_low << 12 ) |				/* REFEC */
 	     ((twr_clk & 0x07) << 8) |				/* WRRREC */
diff --git a/cpu/mpc83xx/u-boot.lds b/cpu/mpc83xx/u-boot.lds
index 8da6f14725..99ad6759d8 100644
--- a/cpu/mpc83xx/u-boot.lds
+++ b/cpu/mpc83xx/u-boot.lds
@@ -31,11 +31,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c
index 74b210cd10..98733834e0 100644
--- a/cpu/mpc85xx/cpu.c
+++ b/cpu/mpc85xx/cpu.c
@@ -174,28 +174,33 @@ int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
 {
 	uint pvr;
 	uint ver;
+	unsigned long val, msr;
+
 	pvr = get_pvr();
 	ver = PVR_VER(pvr);
+
 	if (ver & 1){
 	/* e500 v2 core has reset control register */
 		volatile unsigned int * rstcr;
 		rstcr = (volatile unsigned int *)(CFG_IMMR + 0xE00B0);
 		*rstcr = 0x2;		/* HRESET_REQ */
-	}else{
+		udelay(100);
+	}
+
 	/*
+	 * Fallthrough if the code above failed
 	 * Initiate hard reset in debug control register DBCR0
 	 * Make sure MSR[DE] = 1
 	 */
-		unsigned long val, msr;
 
-		msr = mfmsr ();
-		msr |= MSR_DE;
-		mtmsr (msr);
+	msr = mfmsr ();
+	msr |= MSR_DE;
+	mtmsr (msr);
+
+	val = mfspr(DBCR0);
+	val |= 0x70000000;
+	mtspr(DBCR0,val);
 
-		val = mfspr(DBCR0);
-		val |= 0x70000000;
-		mtspr(DBCR0,val);
-	}
 	return 1;
 }
 
diff --git a/cpu/mpc85xx/qe_io.c b/cpu/mpc85xx/qe_io.c
index 98075bbe54..21ea38b7a6 100644
--- a/cpu/mpc85xx/qe_io.c
+++ b/cpu/mpc85xx/qe_io.c
@@ -34,7 +34,7 @@ void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign)
 	u32			pin_2bit_assign;
 	u32			pin_1bit_mask;
 	u32			tmp_val;
-	volatile ccsr_gur_t 	*gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+	volatile ccsr_gur_t	*gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
 	volatile par_io_t	*par_io = (volatile par_io_t *)
 						&(gur->qe_par_io);
 
diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S
index 15b804d9fc..2b5d90e278 100644
--- a/cpu/mpc85xx/start.S
+++ b/cpu/mpc85xx/start.S
@@ -89,7 +89,7 @@ _start_e500:
 	/* L1 */
 	li	r0,2
 	mtspr	L1CSR0,r0	/* invalidate d-cache */
-	mtspr	L1CSR1,r0 	/* invalidate i-cache */
+	mtspr	L1CSR1,r0	/* invalidate i-cache */
 
 	mfspr	r1,DBSR
 	mtspr	DBSR,r1		/* Clear all valid bits */
diff --git a/cpu/mpc86xx/spd_sdram.c b/cpu/mpc86xx/spd_sdram.c
index 8485841a45..5cc0c266f0 100644
--- a/cpu/mpc86xx/spd_sdram.c
+++ b/cpu/mpc86xx/spd_sdram.c
@@ -528,7 +528,7 @@ spd_init(unsigned char i2c_address, unsigned int ddr_num,
 			caslat -= 1;
 		else if (busfreq > max_data_rate) {
 			printf("DDR: Bus freq %d MHz is not fit for DDR rate %d MHz\n",
-		     	busfreq, max_data_rate);
+			busfreq, max_data_rate);
 			return 0;
 		}
 	}
diff --git a/cpu/mpc86xx/start.S b/cpu/mpc86xx/start.S
index c71c92659d..c39dc4681d 100644
--- a/cpu/mpc86xx/start.S
+++ b/cpu/mpc86xx/start.S
@@ -486,25 +486,25 @@ setup_bats:
 	.globl  early_bats
 early_bats:
 	/* IBAT 5 */
-	lis   	r4, CFG_IBAT5L@h
+	lis	r4, CFG_IBAT5L@h
 	ori     r4, r4, CFG_IBAT5L@l
-	lis   	r3, CFG_IBAT5U@h
+	lis	r3, CFG_IBAT5U@h
 	ori     r3, r3, CFG_IBAT5U@l
 	mtspr   IBAT5L, r4
 	mtspr   IBAT5U, r3
 	isync
 
 	/* DBAT 5 */
-	lis   	r4, CFG_DBAT5L@h
+	lis	r4, CFG_DBAT5L@h
 	ori     r4, r4, CFG_DBAT5L@l
-	lis   	r3, CFG_DBAT5U@h
+	lis	r3, CFG_DBAT5U@h
 	ori     r3, r3, CFG_DBAT5U@l
 	mtspr   DBAT5L, r4
 	mtspr   DBAT5U, r3
 	isync
 
 	/* IBAT 6 */
-	lis   	r4, CFG_IBAT6L@h
+	lis	r4, CFG_IBAT6L@h
 	ori     r4, r4, CFG_IBAT6L@l
 	lis	r3, CFG_IBAT6U@h
 	ori     r3, r3, CFG_IBAT6U@l
@@ -513,9 +513,9 @@ early_bats:
 	isync
 
 	/* DBAT 6 */
-	lis   	r4, CFG_DBAT6L@h
+	lis	r4, CFG_DBAT6L@h
 	ori     r4, r4, CFG_DBAT6L@l
-	lis   	r3, CFG_DBAT6U@h
+	lis	r3, CFG_DBAT6U@h
 	ori     r3, r3, CFG_DBAT6U@l
 	mtspr   DBAT6L, r4
 	mtspr   DBAT6U, r3
diff --git a/cpu/mpc8xx/i2c.c b/cpu/mpc8xx/i2c.c
index 6c59374e3f..f05b666b88 100644
--- a/cpu/mpc8xx/i2c.c
+++ b/cpu/mpc8xx/i2c.c
@@ -590,7 +590,7 @@ i2c_test_callback(int flags, int xnum)
 int i2c_probe(uchar chip)
 {
 	i2c_state_t state;
-  	int rc;
+	int rc;
 	uchar buf[1];
 
 	i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
diff --git a/cpu/mpc8xx/scc.c b/cpu/mpc8xx/scc.c
index 744dcdde91..09a3db107b 100644
--- a/cpu/mpc8xx/scc.c
+++ b/cpu/mpc8xx/scc.c
@@ -1,7 +1,7 @@
 /*
  * File:  scc.c
  * Description:
- * 	Basic ET HW initialization and packet RX/TX routines
+ *	Basic ET HW initialization and packet RX/TX routines
  *
  * NOTE  <<<IMPORTANT:  PLEASE READ>>>:
  *     Do not cache Rx/Tx buffers!
diff --git a/cpu/mpc8xx/video.c b/cpu/mpc8xx/video.c
index 918de67943..8bf8e469cc 100644
--- a/cpu/mpc8xx/video.c
+++ b/cpu/mpc8xx/video.c
@@ -115,9 +115,9 @@ DECLARE_GLOBAL_DATA_PTR;
 #define VIDEO_BURST_LEN		(VIDEO_COLS/8)
 
 #ifdef VIDEO_MODE_YUYV
-#define VIDEO_BG_COL 	0x80D880D8	/* Background color in YUYV format */
+#define VIDEO_BG_COL	0x80D880D8	/* Background color in YUYV format */
 #else
-#define VIDEO_BG_COL 	0xF8F8F8F8	/* Background color in RGB format */
+#define VIDEO_BG_COL	0xF8F8F8F8	/* Background color in RGB format */
 #endif
 
 /************************************************************************/
diff --git a/cpu/nios/asmi.c b/cpu/nios/asmi.c
index ce2863e5c6..c2cd8fead0 100644
--- a/cpu/nios/asmi.c
+++ b/cpu/nios/asmi.c
@@ -183,7 +183,7 @@ static void asmi_status_wr (unsigned char status)
  * Device information
  ***********************************************************************/
 typedef struct asmi_devinfo_t {
-	const char 	*name;		/* Device name */
+	const char	*name;		/* Device name */
 	unsigned char	id;		/* Device silicon id */
 	unsigned char	size;		/* Total size log2(bytes)*/
 	unsigned char	num_sects;	/* Number of sectors */
diff --git a/cpu/nios/start.S b/cpu/nios/start.S
index cb1af3c8b6..9e73941a5e 100644
--- a/cpu/nios/start.S
+++ b/cpu/nios/start.S
@@ -208,7 +208,7 @@ __start:
  * A control register that counts system clock cycles would be
  * a handy feature -- hint for Altera ;-)
  */
- 	.globl dly_clks
+	.globl dly_clks
 	/* Each loop is 4 instructions as delay slot is always
 	 * executed. Each instruction is approximately 4 clocks
 	 * (according to some lame info from Altera). So ...
diff --git a/cpu/nios2/start.S b/cpu/nios2/start.S
index 4c6e47066a..6c6f294b01 100644
--- a/cpu/nios2/start.S
+++ b/cpu/nios2/start.S
@@ -178,20 +178,20 @@ _reloc:
  * Instruction performance varies based on the core. For cores
  * with icache and static/dynamic branch prediction (II/f, II/s):
  *
- * 	Normal ALU (e.g. add, cmp, etc):	1 cycle
- * 	Branch (correctly predicted, taken):	2 cycles
+ *	Normal ALU (e.g. add, cmp, etc):	1 cycle
+ *	Branch (correctly predicted, taken):	2 cycles
  *	Negative offset is predicted (II/s).
  *
  * For cores without icache and no branch prediction (II/e):
  *
- * 	Normal ALU (e.g. add, cmp, etc):	6 cycles
- * 	Branch (no prediction):			6 cycles
+ *	Normal ALU (e.g. add, cmp, etc):	6 cycles
+ *	Branch (no prediction):			6 cycles
  *
  * For simplicity, if an instruction cache is implemented we
  * assume II/f or II/s. Otherwise, we use the II/e.
  *
  */
- 	.globl dly_clks
+	.globl dly_clks
 
 dly_clks:
 
diff --git a/cpu/ppc4xx/4xx_pci.c b/cpu/ppc4xx/4xx_pci.c
index 941d4dc788..c28c7ac86d 100644
--- a/cpu/ppc4xx/4xx_pci.c
+++ b/cpu/ppc4xx/4xx_pci.c
@@ -46,7 +46,7 @@
  *  10-Dec-99   Updated PCI_Write_CFG_Reg for pass2 errata #6               JWB
  *  11-Jan-00   Ensure PMMxMAs disabled before setting PMMxLAs. This is not
  *              really required after a reset since PMMxMAs are already
- * 	        disabled but is a good practice nonetheless.                JWB
+ *	        disabled but is a good practice nonetheless.                JWB
  *  12-Jun-01   stefan.roese@esd-electronics.com
  *              - PCI host/adapter handling reworked
  *  09-Jul-01   stefan.roese@esd-electronics.com
diff --git a/cpu/ppc4xx/4xx_pcie.c b/cpu/ppc4xx/4xx_pcie.c
index f9a1988d41..503facca30 100644
--- a/cpu/ppc4xx/4xx_pcie.c
+++ b/cpu/ppc4xx/4xx_pcie.c
@@ -444,8 +444,8 @@ static void ppc4xx_setup_utl(u32 port)
 
 /*
  * TODO: double check PCI express SDR based on the latest user manual
- * 		 Some registers specified here no longer exist.. has to be
- * 		 updated based on the final EAS spec.
+ *		 Some registers specified here no longer exist.. has to be
+ *		 updated based on the final EAS spec.
  */
 static int check_error(void)
 {
diff --git a/cpu/ppc4xx/i2c.c b/cpu/ppc4xx/i2c.c
index 47c264e222..d8be2cef1f 100644
--- a/cpu/ppc4xx/i2c.c
+++ b/cpu/ppc4xx/i2c.c
@@ -61,7 +61,7 @@ static void _i2c_bus_reset(void)
 	/* write 1 in IRQP IRQD LA ICT XFRA to clear these fields */
 	out_8((u8 *)IIC_EXTSTS, 0x8F);
 
-    	/* Place chip in the reset state */
+	/* Place chip in the reset state */
 	out_8((u8 *)IIC_XTCNTLSS, IIC_XTCNTLSS_SRST);
 
 	/* Check if bus is free */
diff --git a/cpu/ppc4xx/kgdb.S b/cpu/ppc4xx/kgdb.S
index 42b9546d3d..4227a4c15b 100644
--- a/cpu/ppc4xx/kgdb.S
+++ b/cpu/ppc4xx/kgdb.S
@@ -45,7 +45,7 @@ kgdb_flush_cache_all:
 	iccci   r0,r0		/* iccci invalidates the entire I cache */
 	/* dcache */
 	addi    r6,0,0x0000     /* clear GPR 6 */
-	addi    r7,r0, 128 	/* do loop for # of dcache lines */
+	addi    r7,r0, 128	/* do loop for # of dcache lines */
 				/* NOTE: dccci invalidates both */
 	mtctr   r7              /* ways in the D cache */
 ..dcloop:
diff --git a/cpu/ppc4xx/speed.c b/cpu/ppc4xx/speed.c
index 8b4e64a19c..ef47ffc952 100644
--- a/cpu/ppc4xx/speed.c
+++ b/cpu/ppc4xx/speed.c
@@ -1126,7 +1126,7 @@ void get_sys_info (sys_info_t * sysInfo)
 		m = sysInfo->pllFwdDiv * plb2xDiv * 2
 			* sysInfo->pllOpbDiv * sysInfo->pllExtBusDiv;
 		break;
-    	case PLL_FBK_PLL_LOCAL:
+	case PLL_FBK_PLL_LOCAL:
 		break;
 	default:
 		printf("%s unknown m\n", __FUNCTION__);
diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S
index a513b4507a..0008170128 100644
--- a/cpu/ppc4xx/start.S
+++ b/cpu/ppc4xx/start.S
@@ -852,7 +852,7 @@ _start:
 	mtdccr	r1			/* data cache */
 
 	addis	r1,r0,CFG_INIT_RAM_ADDR@h
-	ori	r1,r1,CFG_INIT_SP_OFFSET	  /* set up the stack to SDRAM */
+	ori	r1,r1,CFG_INIT_SP_OFFSET /* set up the stack to SDRAM */
 	li	r0, 0			/* Make room for stack frame header and */
 	stwu	r0, -4(r1)		/* clear final stack frame so that	*/
 	stwu	r0, -4(r1)		/* stack backtraces terminate cleanly	*/
@@ -947,11 +947,11 @@ _start:
 	/*----------------------------------------------------------------------- */
 	/* DMA Status, clear to come up clean */
 	/*----------------------------------------------------------------------- */
-	addis	r3,r0, 0xFFFF	      /* Clear all existing DMA status */
+	addis	r3,r0, 0xFFFF		/* Clear all existing DMA status */
 	ori	r3,r3, 0xFFFF
 	mtdcr	dmasr, r3
 
-	bl	ppc405ep_init	      /* do ppc405ep specific init */
+	bl	ppc405ep_init		/* do ppc405ep specific init */
 #endif /* CONFIG_405EP */
 
 #if defined(CFG_OCM_DATA_ADDR) && defined(CFG_OCM_DATA_SIZE)
@@ -1809,13 +1809,13 @@ ppc405ep_init:
 	!-----------------------------------------------------------------------
 	*/
 	mfdcr	r5, CPC0_PLLMR1
-	rlwinm	r4,r5,1,0x1	       /* get system clock source (SSCS) */
+	rlwinm	r4,r5,1,0x1		/* get system clock source (SSCS) */
 	cmpi	cr0,0,r4,0x1
 
-	beq    pll_done			  /* if SSCS =b'1' then PLL has */
-					  /* already been set */
-					  /* and CPU has been reset */
-					  /* so skip to next section */
+	beq    pll_done			/* if SSCS =b'1' then PLL has */
+					/* already been set */
+					/* and CPU has been reset */
+					/* so skip to next section */
 
 #ifdef CONFIG_BUBINGA
 	/*
@@ -1837,13 +1837,13 @@ ppc405ep_init:
 	lwz	r4, 0(r3)
 	addis	r5,0,NVRVFY1@h
 	addi	r5,r5,NVRVFY1@l
-	cmp	cr0,0,r4,r5	       /* Compare 1st NVRAM Magic number*/
+	cmp	cr0,0,r4,r5		/* Compare 1st NVRAM Magic number*/
 	bne	..no_pllset
 	addi	r3,r3,4
 	lwz	r4, 0(r3)
 	addis	r5,0,NVRVFY2@h
 	addi	r5,r5,NVRVFY2@l
-	cmp	cr0,0,r4,r5	       /* Compare 2 NVRAM Magic number */
+	cmp	cr0,0,r4,r5		/* Compare 2 NVRAM Magic number */
 	bne	..no_pllset
 	addi	r3,r3,8			/* Skip over conf_size */
 	lwz	r4, 4(r3)		/* Load PLLMR1 value from NVRAM */
@@ -1867,7 +1867,7 @@ ppc405ep_init:
 #if defined(CONFIG_ZEUS)
 	mfdcr	r4, CPC0_BOOT
 	andi.	r5, r4, CPC0_BOOT_SEP@l
-	bne	strap_1  	/* serial eeprom present */
+	bne	strap_1			/* serial eeprom present */
 	lis	r3,0x0000
 	addi	r3,r3,0x3030
 	lis	r4,0x8042
@@ -1879,10 +1879,10 @@ strap_1:
 	b	1f
 #endif
 
-	addis	r3,0,PLLMR0_DEFAULT@h	    /* PLLMR0 default value */
-	ori	r3,r3,PLLMR0_DEFAULT@l	   /* */
-	addis	r4,0,PLLMR1_DEFAULT@h	    /* PLLMR1 default value */
-	ori	r4,r4,PLLMR1_DEFAULT@l	   /* */
+	addis	r3,0,PLLMR0_DEFAULT@h	/* PLLMR0 default value */
+	ori	r3,r3,PLLMR0_DEFAULT@l	/* */
+	addis	r4,0,PLLMR1_DEFAULT@h	/* PLLMR1 default value */
+	ori	r4,r4,PLLMR1_DEFAULT@l	/* */
 
 #ifdef CONFIG_TAIHU
 	b	1f
@@ -1898,7 +1898,7 @@ strap_1:
 #endif /* CONFIG_TAIHU */
 
 1:
-	b	pll_write		  /* Write the CPC0_PLLMR with new value */
+	b	pll_write		/* Write the CPC0_PLLMR with new value */
 
 pll_done:
 	/*
@@ -1915,7 +1915,7 @@ pll_done:
 pci_wait:
 	bdnz	pci_wait
 
-	blr				  /* return to main code */
+	blr				/* return to main code */
 
 /*
 !-----------------------------------------------------------------------------
@@ -1936,20 +1936,20 @@ pci_wait:
 pll_write:
 	mfdcr  r5, CPC0_UCR
 	andis. r5,r5,0xFFFF
-	ori    r5,r5,0x0101		 /* Stop the UART clocks */
-	mtdcr  CPC0_UCR,r5		 /* Before changing PLL */
+	ori    r5,r5,0x0101		/* Stop the UART clocks */
+	mtdcr  CPC0_UCR,r5		/* Before changing PLL */
 
 	mfdcr  r5, CPC0_PLLMR1
-	rlwinm r5,r5,0,0x7FFFFFFF	 /* Disable PLL */
+	rlwinm r5,r5,0,0x7FFFFFFF	/* Disable PLL */
 	mtdcr	CPC0_PLLMR1,r5
-	oris   r5,r5,0x4000		 /* Set PLL Reset */
+	oris   r5,r5,0x4000		/* Set PLL Reset */
 	mtdcr	CPC0_PLLMR1,r5
 
-	mtdcr	CPC0_PLLMR0,r3		 /* Set clock dividers */
-	rlwinm r5,r4,0,0x3FFFFFFF	 /* Reset & Bypass new PLL dividers */
-	oris   r5,r5,0x4000		 /* Set PLL Reset */
-	mtdcr	CPC0_PLLMR1,r5		 /* Set clock dividers */
-	rlwinm r5,r5,0,0xBFFFFFFF	 /* Clear PLL Reset */
+	mtdcr	CPC0_PLLMR0,r3		/* Set clock dividers */
+	rlwinm r5,r4,0,0x3FFFFFFF	/* Reset & Bypass new PLL dividers */
+	oris   r5,r5,0x4000		/* Set PLL Reset */
+	mtdcr	CPC0_PLLMR1,r5		/* Set clock dividers */
+	rlwinm r5,r5,0,0xBFFFFFFF	/* Clear PLL Reset */
 	mtdcr	CPC0_PLLMR1,r5
 
 		/*
@@ -1970,9 +1970,9 @@ pll_wait:
 	 * Not sure if this is needed...
 	 */
 	addis r3,0,0x1000
-	mtspr dbcr0,r3		     /* This will cause a CPU core reset, and */
-				     /* execution will continue from the poweron */
-				     /* vector of 0xfffffffc */
+	mtspr dbcr0,r3			/* This will cause a CPU core reset, and */
+					/* execution will continue from the poweron */
+					/* vector of 0xfffffffc */
 #endif /* CONFIG_405EP */
 
 #if defined(CONFIG_440)
diff --git a/cpu/ppc4xx/usb_ohci.c b/cpu/ppc4xx/usb_ohci.c
index 7dbb288ebf..5dbd842274 100644
--- a/cpu/ppc4xx/usb_ohci.c
+++ b/cpu/ppc4xx/usb_ohci.c
@@ -1600,7 +1600,7 @@ int usb_lowlevel_init(void)
 	gohci.sleeping = 0;
 	gohci.irq = -1;
 #if defined(CONFIG_440EP)
- 	gohci.regs = (struct ohci_regs *)(CFG_PERIPHERAL_BASE | 0x1000);
+	gohci.regs = (struct ohci_regs *)(CFG_PERIPHERAL_BASE | 0x1000);
 #elif defined(CONFIG_440EPX) || defined(CFG_USB_HOST)
 	gohci.regs = (struct ohci_regs *)(CFG_USB_HOST);
 #endif
diff --git a/cpu/pxa/i2c.c b/cpu/pxa/i2c.c
index 92dd19f95f..df537c4351 100644
--- a/cpu/pxa/i2c.c
+++ b/cpu/pxa/i2c.c
@@ -45,7 +45,7 @@
 #include <asm/arch/pxa-regs.h>
 #include <i2c.h>
 
-/*#define	DEBUG_I2C 	1	/###* activate local debugging output  */
+/*#define	DEBUG_I2C	1	/###* activate local debugging output  */
 #define I2C_PXA_SLAVE_ADDR	0x1	/* slave pxa unit address           */
 
 #if (CFG_I2C_SPEED == 400000)
@@ -191,8 +191,8 @@ int i2c_transfer(struct i2c_msg *msg)
 		/* start receive */
 		ICR &= ~ICR_START;
 		ICR &= ~ICR_STOP;
-		if (msg->condition == I2C_COND_START) 	  ICR |= ICR_START;
-		if (msg->condition == I2C_COND_STOP)  	  ICR |= ICR_STOP;
+		if (msg->condition == I2C_COND_START)	  ICR |= ICR_START;
+		if (msg->condition == I2C_COND_STOP)	  ICR |= ICR_STOP;
 		if (msg->acknack   == I2C_ACKNAK_SENDNAK) ICR |=  ICR_ACKNAK;
 		if (msg->acknack   == I2C_ACKNAK_SENDACK) ICR &= ~ICR_ACKNAK;
 		ICR &= ~ICR_ALDIE;
@@ -267,7 +267,7 @@ void i2c_init(int speed, int slaveaddr)
  * i2c_probe: - Test if a chip answers for a given i2c address
  *
  * @chip:	address of the chip which is searched for
- * @return: 	0 if a chip was found, -1 otherwhise
+ * @return:	0 if a chip was found, -1 otherwhise
  */
 
 int i2c_probe(uchar chip)
diff --git a/cpu/s3c44b0/start.S b/cpu/s3c44b0/start.S
index 7affe87b3a..1d88c1c030 100644
--- a/cpu/s3c44b0/start.S
+++ b/cpu/s3c44b0/start.S
@@ -188,7 +188,7 @@ _start_armboot:	.word start_armboot
 #define WTCON (0x01c00000+0x130000)
 cpu_init_crit:
 	/* disable watch dog */
-	ldr 	r0, =WTCON
+	ldr	r0, =WTCON
 	ldr	r1, =0x0
 	str	r1, [r0]
 
@@ -211,7 +211,7 @@ cpu_init_crit:
 	ldr	r1, =PLLCON
 
 #if CONFIG_S3C44B0_CLOCK_SPEED==66
-	ldr	r0, =0x34031 	/* 66MHz (Quartz=11MHz) */
+	ldr	r0, =0x34031	/* 66MHz (Quartz=11MHz) */
 #elif CONFIG_S3C44B0_CLOCK_SPEED==75
 	ldr	r0, =0x610c1 /*B2: Xtal=20mhz Fclk=75MHz  */
 #else
diff --git a/cpu/sa1100/start.S b/cpu/sa1100/start.S
index 431ee656e8..910650d15b 100644
--- a/cpu/sa1100/start.S
+++ b/cpu/sa1100/start.S
@@ -157,7 +157,7 @@ stack_setup:
 clear_bss:
 	ldr	r0, _bss_start		/* find start of bss segment        */
 	ldr	r1, _bss_end		/* stop here                        */
-	mov 	r2, #0x00000000		/* clear                            */
+	mov	r2, #0x00000000		/* clear                            */
 
 clbss_l:str	r2, [r0]		/* clear loop...                    */
 	add	r0, r0, #4
@@ -349,31 +349,31 @@ cpu_init_crit:
 undefined_instruction:
 	get_bad_stack
 	bad_save_user_regs
-	bl 	do_undefined_instruction
+	bl	do_undefined_instruction
 
 	.align	5
 software_interrupt:
 	get_bad_stack
 	bad_save_user_regs
-	bl 	do_software_interrupt
+	bl	do_software_interrupt
 
 	.align	5
 prefetch_abort:
 	get_bad_stack
 	bad_save_user_regs
-	bl 	do_prefetch_abort
+	bl	do_prefetch_abort
 
 	.align	5
 data_abort:
 	get_bad_stack
 	bad_save_user_regs
-	bl 	do_data_abort
+	bl	do_data_abort
 
 	.align	5
 not_used:
 	get_bad_stack
 	bad_save_user_regs
-	bl 	do_not_used
+	bl	do_not_used
 
 #ifdef CONFIG_USE_IRQ
 
@@ -381,7 +381,7 @@ not_used:
 irq:
 	get_irq_stack
 	irq_save_user_regs
-	bl 	do_irq
+	bl	do_irq
 	irq_restore_user_regs
 
 	.align	5
@@ -389,7 +389,7 @@ fiq:
 	get_fiq_stack
 	/* someone ought to write a more effiction fiq_save_user_regs */
 	irq_save_user_regs
-	bl 	do_fiq
+	bl	do_fiq
 	irq_restore_user_regs
 
 #else
@@ -398,13 +398,13 @@ fiq:
 irq:
 	get_bad_stack
 	bad_save_user_regs
-	bl 	do_irq
+	bl	do_irq
 
 	.align	5
 fiq:
 	get_bad_stack
 	bad_save_user_regs
-	bl 	do_fiq
+	bl	do_fiq
 
 #endif
 
diff --git a/cpu/sh4/cache.c b/cpu/sh4/cache.c
index 4e744d7145..377005cd4d 100644
--- a/cpu/sh4/cache.c
+++ b/cpu/sh4/cache.c
@@ -72,9 +72,9 @@ static inline void cache_wback_all(void)
 	jump_to_P2();
 	for (i = 0; i < CACHE_OC_NUM_ENTRIES; i++){
 		for (j = 0; j < CACHE_OC_NUM_WAYS; j++) {
-      			addr = CACHE_OC_ADDRESS_ARRAY | (j << CACHE_OC_WAY_SHIFT)
+			addr = CACHE_OC_ADDRESS_ARRAY | (j << CACHE_OC_WAY_SHIFT)
 				| (i << CACHE_OC_ENTRY_SHIFT);
-      			data = inl(addr);
+			data = inl(addr);
 			if (data & CACHE_UPDATED) {
 				data &= ~CACHE_UPDATED;
 				outl(data, addr);
diff --git a/disk/part_iso.c b/disk/part_iso.c
index 4894630793..72ff8689d0 100644
--- a/disk/part_iso.c
+++ b/disk/part_iso.c
@@ -81,7 +81,7 @@ int get_partition_info_iso_verb(block_dev_desc_t * dev_desc, int part_num, disk_
 	/* the first sector (sector 0x10) must be a primary volume desc */
 	blkaddr=PVD_OFFSET;
 	if (dev_desc->block_read (dev_desc->dev, PVD_OFFSET, 1, (ulong *) tmpbuf) != 1)
-   	return (-1);
+	return (-1);
 	if(ppr->desctype!=0x01) {
 		if(verb)
 			printf ("** First descriptor is NOT a primary desc on %d:%d **\n",
@@ -103,7 +103,7 @@ int get_partition_info_iso_verb(block_dev_desc_t * dev_desc, int part_num, disk_
 	for(i=blkaddr;i<lastsect;i++) {
 		PRINTF("Reading block %d\n", i);
 		if (dev_desc->block_read (dev_desc->dev, i, 1, (ulong *) tmpbuf) != 1)
-  	 	return (-1);
+		return (-1);
 		if(ppr->desctype==0x00)
 			break; /* boot entry found */
 		if(ppr->desctype==0xff) {
@@ -113,7 +113,7 @@ int get_partition_info_iso_verb(block_dev_desc_t * dev_desc, int part_num, disk_
 			return (-1);
 		}
 	}
- 	/* boot entry found */
+	/* boot entry found */
 	if(strncmp(pbr->ident_str,"EL TORITO SPECIFICATION",23)!=0) {
 		if(verb)
 			printf ("** Wrong El Torito ident: %s on %d:%d **\n",
diff --git a/disk/part_iso.h b/disk/part_iso.h
index 2663578bf6..c139d4b631 100644
--- a/disk/part_iso.h
+++ b/disk/part_iso.h
@@ -41,8 +41,8 @@ typedef struct iso_pri_rec {
 	unsigned char desctype;			/* type of Volume descriptor: 0 = boot record, 1 = primary, 2 = Supplement, 3 = volume part 0xff trminator */
 	unsigned char stand_ident[5]; /* "CD001" */
 	unsigned char vers;					/* Version */
- 	unsigned char unused;
- 	char 					sysid[32];		/* system Identifier */
+	unsigned char unused;
+	char					sysid[32];		/* system Identifier */
 	char					volid[32];		/* volume Identifier */
 	unsigned char zeros1[8];		/* unused */
 	unsigned long volsiz_LE;		/* volume size Little Endian */
@@ -57,69 +57,69 @@ typedef struct iso_pri_rec {
 	unsigned long pathtablen_LE;/* Path Table size LE */
 	unsigned long pathtablen_BE;/* Path Table size BE */
 	unsigned long firstsek_LEpathtab1_LE; /* location of first occurrence of little endian type path table */
- 	unsigned long firstsek_LEpathtab2_LE; /* location of optional occurrence of little endian type path table */
- 	unsigned long firstsek_BEpathtab1_BE; /* location of first occurrence of big endian type path table */
- 	unsigned long firstsek_BEpathtab2_BE; /* location of optional occurrence of big endian type path table */
- 	unsigned char rootdir[34];	/* directory record for root dir */
- 	char 					volsetid[128];/* Volume set identifier */
- 	char					pubid[128];		/* Publisher identifier */
- 	char 					dataprepid[128]; /* data preparer identifier */
- 	char 					appid[128];		/* application identifier */
- 	char 					copyr[37];		/* copyright string */
- 	char 					abstractfileid[37]; /* abstract file identifier */
- 	char					bibliofileid[37]; /* bibliographic file identifier */
- 	unsigned char creationdate[17]; /* creation date */
- 	unsigned char modify[17];		/* modification date */
- 	unsigned char expire[17];		/* expiring date */
- 	unsigned char effective[17];/* effective date */
- 	unsigned char filestruc_ver;	/* file structur version */
+	unsigned long firstsek_LEpathtab2_LE; /* location of optional occurrence of little endian type path table */
+	unsigned long firstsek_BEpathtab1_BE; /* location of first occurrence of big endian type path table */
+	unsigned long firstsek_BEpathtab2_BE; /* location of optional occurrence of big endian type path table */
+	unsigned char rootdir[34];	/* directory record for root dir */
+	char					volsetid[128];/* Volume set identifier */
+	char					pubid[128];		/* Publisher identifier */
+	char					dataprepid[128]; /* data preparer identifier */
+	char					appid[128];		/* application identifier */
+	char					copyr[37];		/* copyright string */
+	char					abstractfileid[37]; /* abstract file identifier */
+	char					bibliofileid[37]; /* bibliographic file identifier */
+	unsigned char creationdate[17]; /* creation date */
+	unsigned char modify[17];		/* modification date */
+	unsigned char expire[17];		/* expiring date */
+	unsigned char effective[17];/* effective date */
+	unsigned char filestruc_ver;	/* file structur version */
 } iso_pri_rec_t;
 
 typedef struct iso_sup_rec {
 	unsigned char desctype;			/* type of Volume descriptor: 0 = boot record, 1 = primary, 2 = Supplement, 3 = volume part 0xff trminator */
 	unsigned char stand_ident[5]; /* "CD001" */
 	unsigned char vers;					/* Version */
- 	unsigned char volumeflags;	/* if bit 0 = 0 => all escape sequences are according ISO 2375 */
- 	char 					sysid[32];		/* system Identifier */
+	unsigned char volumeflags;	/* if bit 0 = 0 => all escape sequences are according ISO 2375 */
+	char					sysid[32];		/* system Identifier */
 	char					volid[32];		/* volume Identifier */
 	unsigned char zeros1[8];		/* unused */
- 	unsigned long volsiz_LE;		/* volume size Little Endian */
- 	unsigned long volsiz_BE;		/* volume size Big Endian */
- 	unsigned char escapeseq[32];/* Escape sequences */
+	unsigned long volsiz_LE;		/* volume size Little Endian */
+	unsigned long volsiz_BE;		/* volume size Big Endian */
+	unsigned char escapeseq[32];/* Escape sequences */
 	unsigned short setsize_LE;	/* volume set size LE */
- 	unsigned short setsize_BE;	/* volume set size BE */
- 	unsigned short seqnum_LE;		/* volume sequence number LE */
- 	unsigned short seqnum_BE;		/* volume sequence number BE */
- 	unsigned short secsize_LE;	/* sector size LE */
- 	unsigned short secsize_BE;	/* sector size BE */
+	unsigned short setsize_BE;	/* volume set size BE */
+	unsigned short seqnum_LE;		/* volume sequence number LE */
+	unsigned short seqnum_BE;		/* volume sequence number BE */
+	unsigned short secsize_LE;	/* sector size LE */
+	unsigned short secsize_BE;	/* sector size BE */
 	unsigned long pathtablen_LE;/* Path Table size LE */
 	unsigned long pathtablen_BE;/* Path Table size BE */
 	unsigned long firstsek_LEpathtab1_LE; /* location of first occurrence of little endian type path table */
- 	unsigned long firstsek_LEpathtab2_LE; /* location of optional occurrence of little endian type path table */
- 	unsigned long firstsek_BEpathtab1_BE; /* location of first occurrence of big endian type path table */
- 	unsigned long firstsek_BEpathtab2_BE; /* location of optional occurrence of big endian type path table */
- 	unsigned char rootdir[34];	/* directory record for root dir */
- 	char 					volsetid[128];/* Volume set identifier */
- 	char					pubid[128];		/* Publisher identifier */
- 	char 					dataprepid[128]; /* data preparer identifier */
- 	char 					appid[128];		/* application identifier */
- 	char 					copyr[37];		/* copyright string */
- 	char 					abstractfileid[37]; /* abstract file identifier */
- 	char					bibliofileid[37]; /* bibliographic file identifier */
- 	unsigned char creationdate[17]; /* creation date */
- 	unsigned char modify[17];		/* modification date */
- 	unsigned char expire[17];		/* expiring date */
- 	unsigned char effective[17];/* effective date */
- 	unsigned char filestruc_ver;	/* file structur version */
+	unsigned long firstsek_LEpathtab2_LE; /* location of optional occurrence of little endian type path table */
+	unsigned long firstsek_BEpathtab1_BE; /* location of first occurrence of big endian type path table */
+	unsigned long firstsek_BEpathtab2_BE; /* location of optional occurrence of big endian type path table */
+	unsigned char rootdir[34];	/* directory record for root dir */
+	char					volsetid[128];/* Volume set identifier */
+	char					pubid[128];		/* Publisher identifier */
+	char					dataprepid[128]; /* data preparer identifier */
+	char					appid[128];		/* application identifier */
+	char					copyr[37];		/* copyright string */
+	char					abstractfileid[37]; /* abstract file identifier */
+	char					bibliofileid[37]; /* bibliographic file identifier */
+	unsigned char creationdate[17]; /* creation date */
+	unsigned char modify[17];		/* modification date */
+	unsigned char expire[17];		/* expiring date */
+	unsigned char effective[17];/* effective date */
+	unsigned char filestruc_ver;	/* file structur version */
 }iso_sup_rec_t;
 
 typedef struct iso_part_rec {
 	unsigned char desctype;			/* type of Volume descriptor: 0 = boot record, 1 = primary, 2 = Supplement, 3 = volume part 0xff trminator */
 	unsigned char stand_ident[5]; /* "CD001" */
 	unsigned char vers;					/* Version */
- 	unsigned char unused;
- 	char 					sysid[32];		 /* system Identifier */
-	char					volid[32]; 		/* volume partition Identifier */
+	unsigned char unused;
+	char					sysid[32];		 /* system Identifier */
+	char					volid[32];		/* volume partition Identifier */
 	unsigned long partloc_LE;		/* volume partition location LE */
 	unsigned long partloc_BE;		/* volume partition location BE */
 	unsigned long partsiz_LE;		/* volume partition size LE */
@@ -131,8 +131,8 @@ typedef struct iso_val_entry {
 	unsigned char	header_id;		/* Header ID must be 0x01 */
 	unsigned char	platform;			/* Platform: 0=x86, 1=PowerPC, 2=MAC */
 	unsigned char res[2];				/* reserved */
-	char 					manu_str[0x18]; /* Ident String of manufacturer/developer */
-	unsigned char chk_sum[2]; 	/* Check sum (all words must be zero)  */
+	char					manu_str[0x18]; /* Ident String of manufacturer/developer */
+	unsigned char chk_sum[2];	/* Check sum (all words must be zero)  */
 	unsigned char key[2];				/* key[0]=55, key[1]=0xAA */
 } iso_val_entry_t;
 
@@ -140,7 +140,7 @@ typedef struct iso_header_entry {
 	unsigned char	header_id;		/* Header ID must be 0x90 or 0x91 */
 	unsigned char	platform;			/* Platform: 0=x86, 1=PowerPC, 2=MAC */
 	unsigned char numentry[2];	/* number of entries */
-	char 					id_str[0x1C]; /* Ident String of sectionr */
+	char					id_str[0x1C]; /* Ident String of sectionr */
 } iso_header_entry_t;
 
 
@@ -148,7 +148,7 @@ typedef struct iso_init_def_entry {
 	unsigned char	boot_ind;			/* Boot indicator 0x88=bootable 0=not bootable */
 	unsigned char	boot_media;		/* boot Media Type: 0=no Emulation, 1=1.2MB floppy, 2=1.44MB floppy, 3=2.88MB floppy 4=hd (0x80) */
 	unsigned char ld_seg[2];		/* Load segment (flat model=addr/10) */
-	unsigned char systype; 			/* System Type copy of byte5 of part table */
+	unsigned char systype;			/* System Type copy of byte5 of part table */
 	unsigned char res;					/* reserved */
 	unsigned char sec_cnt[2];		/* sector count in VIRTUAL Blocks (0x200) */
 	unsigned char rel_block_addr[4];	/* relative Block address */
diff --git a/doc/README-i386 b/doc/README-i386
index 02b753cbd7..c560d22f46 100644
--- a/doc/README-i386
+++ b/doc/README-i386
@@ -57,9 +57,9 @@ Daniel Engström, Omicron Ceti AB, daniel@omicron.se
 --- linux-2.4.19-orig/init/do_mounts.c	Sat Aug  3 02:39:46 2002
 +++ linux-2.4.19/init/do_mounts.c	Mon Sep 23 16:21:33 2002
 @@ -224,6 +224,14 @@
- 	{ "ftlc", 0x2c10 },
- 	{ "ftld", 0x2c18 },
- 	{ "mtdblock", 0x1f00 },
+	{ "ftlc", 0x2c10 },
+	{ "ftld", 0x2c18 },
+	{ "mtdblock", 0x1f00 },
 +	{ "mtdblock0", 0x1f00 },
 +	{ "mtdblock1", 0x1f01 },
 +	{ "mtdblock2", 0x1f02 },
@@ -68,7 +68,7 @@ Daniel Engström, Omicron Ceti AB, daniel@omicron.se
 +	{ "mtdblock5", 0x1f05 },
 +	{ "mtdblock6", 0x1f06 },
 +	{ "mtdblock7", 0x1f07 },
- 	{ NULL, 0 }
+	{ NULL, 0 }
  };
 
 -------------------
diff --git a/doc/README-integrator b/doc/README-integrator
index ce8a9d26ad..4daf3413aa 100644
--- a/doc/README-integrator
+++ b/doc/README-integrator
@@ -86,12 +86,12 @@ using the generic "arm_intcm" core:
 ap966_config			Integrator Core Module for ARM966E-S TM
 ap922_config			Integrator Core Module for ARM922T TM with ETM
 ap922_XA10_config		Integrator Core Module for ARM922T using Altera Excalibur
-ap7_config	       		** CM7TDMI
+ap7_config			** CM7TDMI
 integratorap_config
 ap_config
 
 
-cp966_config  			Integrator Core Module for ARM966E-S TM
+cp966_config			Integrator Core Module for ARM966E-S TM
 cp922_config			Integrator Core Module for ARM922T TM with ETM
 cp922_XA10_config		Integrator Core Module for ARM922T using Altera Excalibur
 cp1026_config			Integrator Core Module ARM1026EJ-S TM
diff --git a/doc/README.RPXlite b/doc/README.RPXlite
index c8ccc41eb0..c0238ae213 100644
--- a/doc/README.RPXlite
+++ b/doc/README.RPXlite
@@ -451,7 +451,7 @@ reg_config.txt:
 	PS   = 00
 	PARE = 0
 	WP   = 0
-	MS   = 1 				/* UPMA */
+	MS   = 1				/* UPMA */
 	V    = 1				/* Valid */
 
 	=> 0x0000 0081
@@ -486,7 +486,7 @@ reg_config.txt:
 	PS   = 00
 	PARE = 0
 	WP   = 0
-	MS   = 0 				/* GPCM */
+	MS   = 0				/* GPCM */
 	V    = 1				/* Valid */
 
 	=> 0xFA40 0001
@@ -513,7 +513,7 @@ reg_config.txt:
 	PS   = 01
 	PARE = 0
 	WP   = 0
-	MS   = 0 				/* GPCM */
+	MS   = 0				/* GPCM */
 	V    = 1				/* Valid */
 
 	=> 0xFA00 0401
diff --git a/doc/README.adnpesc1 b/doc/README.adnpesc1
index ded53210bd..5257f18b4b 100644
--- a/doc/README.adnpesc1
+++ b/doc/README.adnpesc1
@@ -184,7 +184,7 @@ you have to check-up the next environment variables:
 	- default is '0' (zero)
 
 	  NOTE:	You should avoid to save this variable with non zero
-	  	value to Flash. Otherwise it would be allow any
+		value to Flash. Otherwise it would be allow any
 		update process at any time!
 
 2. appl_entry_addr
diff --git a/doc/README.adnpesc1_base32 b/doc/README.adnpesc1_base32
index 657604458c..145e8cdade 100644
--- a/doc/README.adnpesc1_base32
+++ b/doc/README.adnpesc1_base32
@@ -192,7 +192,7 @@ IDE:	(TODO)
 	       :	      gap	       :
 	       |			       |
   0x00010020 ---32-----------16|15------------0-
-  	       |			       | \
+	       |			       | \
 	       |  register bank		       | |
 	       |   size = (real_size << 1)     | |
 	       |   real_size = 0x10	       | |
@@ -308,7 +308,7 @@ IDE:	(TODO)
 	+ 0x18 |- - - - - - - - - - - - - - - -| |
 	       |  slaveselect (1 bit)	 (rw)  | |
 	+ 0x14 |- - - - - - - - - - - - - - - -| |
-  SPI0	       |  		   (reserved)  | |
+  SPI0	       |		   (reserved)  | |
   [4]	+ 0x10 |- - - - - - - - - - - - - - - -|  > 0x00000020
 	       |  control (11 bit)	 (rw)  | |
 	+ 0x0c |- - - - - - - - - - - - - - - -| |
diff --git a/doc/README.console b/doc/README.console
index 6d477df75a..25c4f1d7df 100644
--- a/doc/README.console
+++ b/doc/README.console
@@ -97,8 +97,8 @@ SUPPORTED DRIVERS
 
 Working drivers:
 
-    serial 	(architecture dependent serial stuff)
-    video 	(mpc8xx video controller)
+    serial	(architecture dependent serial stuff)
+    video	(mpc8xx video controller)
 
 Work in progress:
 
@@ -114,5 +114,5 @@ TESTED CONFIGURATIONS
 The driver has been tested with the following configurations (see
 CREDITS for other contact informations):
 
-- MPC823FADS with AD7176 on a PAL TV (YCbYCr) 	- arsenio@tin.it
+- MPC823FADS with AD7176 on a PAL TV (YCbYCr)	- arsenio@tin.it
 - GENIETV    with AD7177 on a PAL TV (YCbYCr)	- arsenio@tin.it
diff --git a/doc/README.generic_usb_ohci b/doc/README.generic_usb_ohci
index c44c501474..147ea514ae 100644
--- a/doc/README.generic_usb_ohci
+++ b/doc/README.generic_usb_ohci
@@ -51,6 +51,12 @@ You'll need to define
 
 	CONFIG_PCI_OHCI
 
+If you have several USB PCI controllers, define
+
+	CONFIG_PCI_OHCI_DEVNO: number of the OHCI device in PCI list
+
+If undefined, the first instance found in PCI space will be used.
+
 PCI Controllers need to do byte swapping on register accesses, so they
 should to define:
 
diff --git a/doc/README.m54455evb b/doc/README.m54455evb
index 119a19d897..5c01f0dff1 100644
--- a/doc/README.m54455evb
+++ b/doc/README.m54455evb
@@ -83,7 +83,7 @@ CONFIG_CMD_DATE		-- enable to use date feature in u-boot
 CONFIG_MCFFEC		-- define to use common CF FEC driver
 CONFIG_NET_MULTI	-- define to use multi FEC in u-boot
 CONFIG_MII		-- enable to use MII driver
-CONFIG_CF_DOMII 	-- enable to use MII feature in cmd_mii.c
+CONFIG_CF_DOMII		-- enable to use MII feature in cmd_mii.c
 CFG_DISCOVER_PHY	-- enable PHY discovery
 CFG_RX_ETH_BUFFER	-- Set FEC Receive buffer
 CFG_FAULT_ECHO_LINK_DOWN--
@@ -107,7 +107,7 @@ CFG_ATA_IDE0_OFFSET	-- define ATA IDE0 offset
 CFG_ATA_DATA_OFFSET	-- define ATA data IO
 CFG_ATA_REG_OFFSET	-- define for normal register accesses
 CFG_ATA_ALT_OFFSET	-- define for alternate registers
-CFG_ATA_STRIDE      	-- define for Interval between registers
+CFG_ATA_STRIDE		-- define for Interval between registers
 _IO_BASE		-- define for IO base address
 
 CONFIG_MCFTMR		-- define to use DMA timer
diff --git a/doc/README.m68k b/doc/README.m68k
index 6dea2b567a..0c533f3fa9 100644
--- a/doc/README.m68k
+++ b/doc/README.m68k
@@ -4,9 +4,9 @@ U-Boot for Motorola M68K
 ====================================================================
 History
 
-August 08,2005; 	Jens Scharsig <esw@bus-elektronik.de>
+August 08,2005;		Jens Scharsig <esw@bus-elektronik.de>
 			MCF5282 implementation without preloader
-January 12, 2004; 	<josef.baumgartner@telex.de>
+January 12, 2004;	<josef.baumgartner@telex.de>
 ====================================================================
 
 This file contains status information for the port of U-Boot to the
@@ -82,8 +82,8 @@ Board specific code is located in: board/bus/EB+MCF-EV123
 
 To configure the board, type:
 
-make EB+MCF-EV123_config 		for external FLASH
-make EB+MCF-EV123_internal_config 	for internal FLASH
+make EB+MCF-EV123_config		for external FLASH
+make EB+MCF-EV123_internal_config	for internal FLASH
 
 
 4. CONFIGURATION OPTIONS/SETTINGS
@@ -149,7 +149,7 @@ CFG_RFD		-- defines the PLL Reduce Frecuency Devider
 CFG_CSx_BASE	-- defines the base address of chip select x
 CFG_CSx_SIZE	-- defines the memory size (address range) of chip select x
 CFG_CSx_WIDTH	-- defines the bus with of chip select x
-CFG_CSx_RO 	-- if set to 0 chip select x is read/wirte
+CFG_CSx_RO	-- if set to 0 chip select x is read/wirte
 			else chipselct is read only
 CFG_CSx_WS	-- defines the number of wait states  of chip select x
 
diff --git a/doc/README.marubun-pcmcia b/doc/README.marubun-pcmcia
index 3ed5cd33c4..6099da2fbf 100644
--- a/doc/README.marubun-pcmcia
+++ b/doc/README.marubun-pcmcia
@@ -19,7 +19,7 @@ U-Boot MARUBUN MR-SHPC-01 PCMCIA controller driver
 
 1. base source code
     The code is based on sources from the Linux kernel
-    	( arch/sh/kernel/cf-enabler.c ).
+	( arch/sh/kernel/cf-enabler.c ).
 
 2. How to use
     The options you have to specify in the config file are (with the
@@ -27,14 +27,14 @@ U-Boot MARUBUN MR-SHPC-01 PCMCIA controller driver
 
     * CONFIG_MARUBUN_PCCARD
 	If you want to use this device driver, should define CONFIG_MARUBUN_PCCARD.
-	ex. 	#define CONFIG_MARUBUN_PCCARD
+	ex.	#define CONFIG_MARUBUN_PCCARD
 
     * CONFIG_PCMCIA_SLOT_A
-    	Most devices have only one slot. You should define CONFIG_PCMCIA_SLOT_A .
+	Most devices have only one slot. You should define CONFIG_PCMCIA_SLOT_A .
 	ex.	#define CONFIG_PCMCIA_SLOT_A    1
 
     * CFG_MARUBUN_MRSHPC
-    	This is MR-SHPC-01 PCMCIA controler base address.
+	This is MR-SHPC-01 PCMCIA controler base address.
 	You should do the setting matched to your environment.
 	ex.  #define CFG_MARUBUN_MRSHPC 0xb03fffe0
 	     ( for MS7722SE01 environment )
diff --git a/doc/README.mpc8313erdb b/doc/README.mpc8313erdb
index 21580f9496..cd5668993c 100644
--- a/doc/README.mpc8313erdb
+++ b/doc/README.mpc8313erdb
@@ -22,7 +22,7 @@ Freescale MPC8313ERDB Board
 	0x8000_0000	0x8fff_ffff	PCI MEM		 256M
 	0x9000_0000	0x9fff_ffff	PCI_MMIO	 256M
 	0xe000_0000	0xe00f_ffff	IMMR		 1M
-	0xe200_0000	0xe20f_ffff	PCI IO	 	 16M
+	0xe200_0000	0xe20f_ffff	PCI IO		 16M
 	0xe280_0000	0xe280_7fff	NAND FLASH (CS1) 32K
 	0xf000_0000	0xf001_ffff	VSC7385 (CS2)	 128K
 	0xfa00_0000	0xfa00_7fff	Board Status/	 32K
diff --git a/doc/README.mpc8349itx b/doc/README.mpc8349itx
index 4ae03ae055..7f24623f76 100644
--- a/doc/README.mpc8349itx
+++ b/doc/README.mpc8349itx
@@ -17,7 +17,7 @@ Freescale MPC8349E-mITX and MPC8349E-mITX-GP Boards
 
 2.	Board Switches and Jumpers
 
-2.0 	Descriptions for all of the board jumpers can be found in the User
+2.0	Descriptions for all of the board jumpers can be found in the User
 	Guide.  Of particular interest to U-Boot developers is jumper J22:
 
 	Pos.	Name		Default		Description
@@ -88,8 +88,8 @@ Freescale MPC8349E-mITX and MPC8349E-mITX-GP Boards
 
 	include/configs/MPC8349ITX.h
 
-	CONFIG_MPC83XX	    	MPC83xx family
-	CONFIG_MPC8349	    	MPC8349 specific
+	CONFIG_MPC83XX		MPC83xx family
+	CONFIG_MPC8349		MPC8349 specific
 	CONFIG_MPC8349ITX		MPC8349E-mITX
 	CONFIG_MPC8349ITXGP		MPC8349E-mITX-GP
 
diff --git a/doc/README.mpc8360emds b/doc/README.mpc8360emds
index 5f202475b5..7c841cec06 100644
--- a/doc/README.mpc8360emds
+++ b/doc/README.mpc8360emds
@@ -1,7 +1,7 @@
 Freescale MPC8360EMDS Board
 -----------------------------------------
 1.	Board Switches and Jumpers
-1.0 	There are four Dual-In-Line Packages(DIP) Switches on MPC8360EMDS board
+1.0	There are four Dual-In-Line Packages(DIP) Switches on MPC8360EMDS board
 	For some reason, the HW designers describe the switch settings
 	in terms of 0 and 1, and then map that to physical switches where
 	the label "On" refers to logic 0 and "Off" is logic 1.
diff --git a/doc/README.mpc837xemds b/doc/README.mpc837xemds
index 78235952eb..a14da0f024 100644
--- a/doc/README.mpc837xemds
+++ b/doc/README.mpc837xemds
@@ -1,7 +1,7 @@
 Freescale MPC837xEMDS Board
 -----------------------------------------
 1.	Board Switches and Jumpers
-1.0 	There are four Dual-In-Line Packages(DIP) Switches on MPC837xEMDS board
+1.0	There are four Dual-In-Line Packages(DIP) Switches on MPC837xEMDS board
 	For some reason, the HW designers describe the switch settings
 	in terms of 0 and 1, and then map that to physical switches where
 	the label "On" refers to logic 0 and "Off" is logic 1.
diff --git a/doc/README.mpc8641hpcn b/doc/README.mpc8641hpcn
index ac56ccaf23..1c41d77ab0 100644
--- a/doc/README.mpc8641hpcn
+++ b/doc/README.mpc8641hpcn
@@ -55,7 +55,7 @@ Switches:
 							 halves (virtual banks)
 						  0	:: normal
 	SW5(3)	 = 0		CFG_FLASHWP	= 0	:: not protected
-	SW5(4)	 = 0 		CFG_PORTDIV	= 1	:: 2:1 for PD4
+	SW5(4)	 = 0		CFG_PORTDIV	= 1	:: 2:1 for PD4
 							   1:1 for PD6
 	SW5(5-6) = 11		CFG_PIXISOPT	= 11	:: s/w determined
 	SW5(7-8) = 11		CFG_LADOPT	= 11	:: s/w determined
diff --git a/doc/README.video b/doc/README.video
index c145d9be0d..34e199c2d2 100644
--- a/doc/README.video
+++ b/doc/README.video
@@ -26,5 +26,5 @@ U-Boot MPC8xx video controller driver
 
 The driver has been tested with the following configurations:
 
-- MPC823FADS with AD7176 on a PAL TV (YCbYCr) 	- arsenio@tin.it
+- MPC823FADS with AD7176 on a PAL TV (YCbYCr)	- arsenio@tin.it
 - GENIETV    with AD7177 on a PAL TV (YCbYCr)	- arsenio@tin.it
diff --git a/drivers/bios_emulator/bios.c b/drivers/bios_emulator/bios.c
index 70e9ce143b..d41511c1d4 100644
--- a/drivers/bios_emulator/bios.c
+++ b/drivers/bios_emulator/bios.c
@@ -36,8 +36,8 @@
 *
 * Description:  Module implementing the BIOS specific functions.
 *
-* 		Jason ported this file to u-boot to run the ATI video card
-* 		video BIOS.
+*		Jason ported this file to u-boot to run the ATI video card
+*		video BIOS.
 *
 ****************************************************************************/
 
diff --git a/drivers/block/Makefile b/drivers/block/Makefile
index dca3547919..5f1298dcdc 100644
--- a/drivers/block/Makefile
+++ b/drivers/block/Makefile
@@ -23,7 +23,7 @@
 
 include $(TOPDIR)/config.mk
 
-LIB 	:= $(obj)libblock.a
+LIB	:= $(obj)libblock.a
 
 COBJS-y += ahci.o
 COBJS-y += ata_piix.o
@@ -34,8 +34,8 @@ COBJS-y += sym53c8xx.o
 COBJS-y += systemace.o
 
 COBJS	:= $(COBJS-y)
-SRCS 	:= $(COBJS:.o=.c)
-OBJS 	:= $(addprefix $(obj),$(COBJS))
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
 
 all:	$(LIB)
 
diff --git a/drivers/block/sym53c8xx.c b/drivers/block/sym53c8xx.c
index 29eeccd9a8..87b63b742c 100644
--- a/drivers/block/sym53c8xx.c
+++ b/drivers/block/sym53c8xx.c
@@ -83,11 +83,11 @@ static unsigned int len_script_reselection;
 #endif
 
 
-static unsigned short scsi_int_mask;		/* shadow register for SCSI related interrupts */
+static unsigned short scsi_int_mask;	/* shadow register for SCSI related interrupts */
 static unsigned char  script_int_mask;	/* shadow register for SCRIPT related interrupts */
-static unsigned long script_select[8]; /* script for selection */
-static unsigned long script_msgout[8]; /* script for message out phase (NOT USED) */
-static unsigned long script_msgin[14]; /* script for message in phase */
+static unsigned long script_select[8];	/* script for selection */
+static unsigned long script_msgout[8];	/* script for message out phase (NOT USED) */
+static unsigned long script_msgin[14];	/* script for message in phase */
 static unsigned long script_msg_ext[32]; /* script for message in phase when more than 1 byte message */
 static unsigned long script_cmd[18];    /* script for command phase */
 static unsigned long script_data_in[8]; /* script for data in phase */
@@ -119,63 +119,146 @@ void handle_scsi_int(void);
 /********************************************************************************
  * reports SCSI errors to the user
  */
-void scsi_print_error(ccb *pccb)
+void scsi_print_error (ccb * pccb)
 {
 	int i;
-	printf("SCSI Error: Target %d LUN %d Command %02X\n",pccb->target, pccb->lun, pccb->cmd[0]);
-	printf("       CCB: ");
-	for(i=0;i<pccb->cmdlen;i++)
-		printf("%02X ",pccb->cmd[i]);
-	printf("(len=%d)\n",pccb->cmdlen);
-	printf("     Cntrl: ");
-	switch(pccb->contr_stat) {
-		case SIR_COMPLETE: 						printf("Complete (no Error)\n"); break;
-		case SIR_SEL_ATN_NO_MSG_OUT: 	printf("Selected with ATN no MSG out phase\n"); break;
-		case SIR_CMD_OUT_ILL_PH: 			printf("Command out illegal phase\n"); break;
-		case SIR_MSG_RECEIVED: 				printf("MSG received Error\n"); break;
-		case SIR_DATA_IN_ERR: 				printf("Data in Error\n"); break;
-		case SIR_DATA_OUT_ERR: 				printf("Data out Error\n"); break;
-		case SIR_SCRIPT_ERROR: 				printf("Script Error\n"); break;
-		case SIR_MSG_OUT_NO_CMD: 			printf("MSG out no Command phase\n"); break;
-		case SIR_MSG_OVER7: 					printf("MSG in over 7 bytes\n"); break;
-		case INT_ON_FY: 							printf("Interrupt on fly\n"); break;
-		case SCSI_SEL_TIME_OUT:				printf("SCSI Selection Timeout\n"); break;
-		case SCSI_HNS_TIME_OUT:				printf("SCSI Handshake Timeout\n"); break;
-		case SCSI_MA_TIME_OUT:				printf("SCSI Phase Error\n"); break;
-		case SCSI_UNEXP_DIS:					printf("SCSI unexpected disconnect\n"); break;
-		default:											printf("unknown status %lx\n",pccb->contr_stat); break;
+
+	printf ("SCSI Error: Target %d LUN %d Command %02X\n", pccb->target,
+		pccb->lun, pccb->cmd[0]);
+	printf ("       CCB: ");
+	for (i = 0; i < pccb->cmdlen; i++)
+		printf ("%02X ", pccb->cmd[i]);
+	printf ("(len=%d)\n", pccb->cmdlen);
+	printf ("     Cntrl: ");
+	switch (pccb->contr_stat) {
+	case SIR_COMPLETE:
+		printf ("Complete (no Error)\n");
+		break;
+	case SIR_SEL_ATN_NO_MSG_OUT:
+		printf ("Selected with ATN no MSG out phase\n");
+		break;
+	case SIR_CMD_OUT_ILL_PH:
+		printf ("Command out illegal phase\n");
+		break;
+	case SIR_MSG_RECEIVED:
+		printf ("MSG received Error\n");
+		break;
+	case SIR_DATA_IN_ERR:
+		printf ("Data in Error\n");
+		break;
+	case SIR_DATA_OUT_ERR:
+		printf ("Data out Error\n");
+		break;
+	case SIR_SCRIPT_ERROR:
+		printf ("Script Error\n");
+		break;
+	case SIR_MSG_OUT_NO_CMD:
+		printf ("MSG out no Command phase\n");
+		break;
+	case SIR_MSG_OVER7:
+		printf ("MSG in over 7 bytes\n");
+		break;
+	case INT_ON_FY:
+		printf ("Interrupt on fly\n");
+		break;
+	case SCSI_SEL_TIME_OUT:
+		printf ("SCSI Selection Timeout\n");
+		break;
+	case SCSI_HNS_TIME_OUT:
+		printf ("SCSI Handshake Timeout\n");
+		break;
+	case SCSI_MA_TIME_OUT:
+		printf ("SCSI Phase Error\n");
+		break;
+	case SCSI_UNEXP_DIS:
+		printf ("SCSI unexpected disconnect\n");
+		break;
+	default:
+		printf ("unknown status %lx\n", pccb->contr_stat);
+		break;
 	}
-	printf("     Sense: SK %x (",pccb->sense_buf[2]&0x0f);
-	switch(pccb->sense_buf[2]&0xf) {
-		case SENSE_NO_SENSE: printf("No Sense)"); break;
-		case SENSE_RECOVERED_ERROR: printf("Recovered Error)"); break;
-		case SENSE_NOT_READY:	printf("Not Ready)"); break;
-		case SENSE_MEDIUM_ERROR: printf("Medium Error)"); break;
-		case SENSE_HARDWARE_ERROR: printf("Hardware Error)"); break;
-		case SENSE_ILLEGAL_REQUEST: printf("Illegal request)"); break;
-		case SENSE_UNIT_ATTENTION: printf("Unit Attention)"); break;
-		case SENSE_DATA_PROTECT: printf("Data Protect)"); break;
-		case SENSE_BLANK_CHECK:	printf("Blank check)"); break;
-		case SENSE_VENDOR_SPECIFIC: printf("Vendor specific)"); break;
-		case SENSE_COPY_ABORTED: printf("Copy aborted)"); break;
-		case SENSE_ABORTED_COMMAND:	printf("Aborted Command)"); break;
-		case SENSE_VOLUME_OVERFLOW:	printf("Volume overflow)"); break;
-		case SENSE_MISCOMPARE: printf("Misscompare\n"); break;
-		default: printf("Illegal Sensecode\n"); break;
+	printf ("     Sense: SK %x (", pccb->sense_buf[2] & 0x0f);
+	switch (pccb->sense_buf[2] & 0xf) {
+	case SENSE_NO_SENSE:
+		printf ("No Sense)");
+		break;
+	case SENSE_RECOVERED_ERROR:
+		printf ("Recovered Error)");
+		break;
+	case SENSE_NOT_READY:
+		printf ("Not Ready)");
+		break;
+	case SENSE_MEDIUM_ERROR:
+		printf ("Medium Error)");
+		break;
+	case SENSE_HARDWARE_ERROR:
+		printf ("Hardware Error)");
+		break;
+	case SENSE_ILLEGAL_REQUEST:
+		printf ("Illegal request)");
+		break;
+	case SENSE_UNIT_ATTENTION:
+		printf ("Unit Attention)");
+		break;
+	case SENSE_DATA_PROTECT:
+		printf ("Data Protect)");
+		break;
+	case SENSE_BLANK_CHECK:
+		printf ("Blank check)");
+		break;
+	case SENSE_VENDOR_SPECIFIC:
+		printf ("Vendor specific)");
+		break;
+	case SENSE_COPY_ABORTED:
+		printf ("Copy aborted)");
+		break;
+	case SENSE_ABORTED_COMMAND:
+		printf ("Aborted Command)");
+		break;
+	case SENSE_VOLUME_OVERFLOW:
+		printf ("Volume overflow)");
+		break;
+	case SENSE_MISCOMPARE:
+		printf ("Misscompare\n");
+		break;
+	default:
+		printf ("Illegal Sensecode\n");
+		break;
 	}
-	printf(" ASC %x ASCQ %x\n",pccb->sense_buf[12],pccb->sense_buf[13]);
-	printf("    Status: ");
-	switch(pccb->status) {
-		case S_GOOD :	printf("Good\n"); break;
-		case S_CHECK_COND: printf("Check condition\n"); break;
-		case S_COND_MET: printf("Condition Met\n"); break;
-		case S_BUSY: printf("Busy\n"); break;
-		case S_INT: printf("Intermediate\n"); break;
-		case S_INT_COND_MET: printf("Intermediate condition met\n"); break;
-		case S_CONFLICT: printf("Reservation conflict\n"); break;
-		case S_TERMINATED: printf("Command terminated\n"); break;
-		case S_QUEUE_FULL: printf("Task set full\n"); break;
-		default: printf("unknown: %02X\n",pccb->status); break;
+	printf (" ASC %x ASCQ %x\n", pccb->sense_buf[12],
+		pccb->sense_buf[13]);
+	printf ("    Status: ");
+	switch (pccb->status) {
+	case S_GOOD:
+		printf ("Good\n");
+		break;
+	case S_CHECK_COND:
+		printf ("Check condition\n");
+		break;
+	case S_COND_MET:
+		printf ("Condition Met\n");
+		break;
+	case S_BUSY:
+		printf ("Busy\n");
+		break;
+	case S_INT:
+		printf ("Intermediate\n");
+		break;
+	case S_INT_COND_MET:
+		printf ("Intermediate condition met\n");
+		break;
+	case S_CONFLICT:
+		printf ("Reservation conflict\n");
+		break;
+	case S_TERMINATED:
+		printf ("Command terminated\n");
+		break;
+	case S_QUEUE_FULL:
+		printf ("Task set full\n");
+		break;
+	default:
+		printf ("unknown: %02X\n", pccb->status);
+		break;
 	}
 
 }
@@ -252,8 +335,7 @@ void handle_scsi_int(void)
 	if((stat & DIP)==DIP) { /* DMA Interrupt pending */
 		stat1=scsi_read_byte(DSTAT);
 #ifdef SCSI_SINGLE_STEP
-		if((stat1 & SSI)==SSI)
-		{
+		if((stat1 & SSI)==SSI) {
 			tt=in32r(scsi_mem_addr+DSP);
 			if(((tt)>=start_script_select) && ((tt)<start_script_select+len_script_select)) {
 				printf("select %d\n",(tt-start_script_select)>>2);
@@ -589,7 +671,7 @@ void scsi_issue(ccb *pccb)
 	int busdevfunc = pccb->priv;
 	int i;
 	unsigned short sstat;
- 	int retrycnt;  /* retry counter */
+	int retrycnt;  /* retry counter */
 	for(i=0;i<3;i++)
 		int_stat[i]=0; /* delete all int status */
 	/* struct pccb must be set-up correctly */
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index 2dd5a0e143..7e17360de5 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -23,13 +23,13 @@
 
 include $(TOPDIR)/config.mk
 
-LIB 	:= $(obj)libdma.a
+LIB	:= $(obj)libdma.a
 
 COBJS-y += MCD_tasksInit.o MCD_dmaApi.o MCD_tasks.o
 
 COBJS	:= $(COBJS-y)
-SRCS 	:= $(COBJS:.o=.c)
-OBJS 	:= $(addprefix $(obj),$(COBJS))
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
 
 all:	$(LIB)
 
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index 071ef00b15..534c015191 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -23,7 +23,7 @@
 
 include $(TOPDIR)/config.mk
 
-LIB 	:= $(obj)libi2c.a
+LIB	:= $(obj)libi2c.a
 
 COBJS-y += fsl_i2c.o
 COBJS-y += omap1510_i2c.o
@@ -32,8 +32,8 @@ COBJS-y += tsi108_i2c.o
 COBJS-y += mxc_i2c.o
 
 COBJS	:= $(COBJS-y)
-SRCS 	:= $(COBJS:.o=.c)
-OBJS 	:= $(addprefix $(obj),$(COBJS))
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
 
 all:	$(LIB)
 
diff --git a/drivers/input/Makefile b/drivers/input/Makefile
index df22cf9c6d..2933cb6451 100644
--- a/drivers/input/Makefile
+++ b/drivers/input/Makefile
@@ -23,15 +23,15 @@
 
 include $(TOPDIR)/config.mk
 
-LIB 	:= $(obj)libinput.a
+LIB	:= $(obj)libinput.a
 
 COBJS-y += i8042.o
 COBJS-y += keyboard.o
 COBJS-y += pc_keyb.o ps2ser.o ps2mult.o
 
 COBJS	:= $(COBJS-y)
-SRCS 	:= $(COBJS:.o=.c)
-OBJS 	:= $(addprefix $(obj),$(COBJS))
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
 
 all:	$(LIB)
 
diff --git a/drivers/input/keyboard.c b/drivers/input/keyboard.c
index 9975202d7a..54182a79b1 100644
--- a/drivers/input/keyboard.c
+++ b/drivers/input/keyboard.c
@@ -270,20 +270,20 @@ extern int overwrite_console (void);
 int kbd_init (void)
 {
 	int error;
-  	device_t kbddev ;
+	device_t kbddev ;
 	char *stdinname  = getenv ("stdin");
 
 	if(kbd_init_hw()==-1)
 		return -1;
-  	memset (&kbddev, 0, sizeof(kbddev));
-  	strcpy(kbddev.name, DEVNAME);
-  	kbddev.flags =  DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM;
-  	kbddev.putc = NULL ;
+	memset (&kbddev, 0, sizeof(kbddev));
+	strcpy(kbddev.name, DEVNAME);
+	kbddev.flags =  DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM;
+	kbddev.putc = NULL ;
 	kbddev.puts = NULL ;
 	kbddev.getc = kbd_getc ;
 	kbddev.tstc = kbd_testc ;
 
- 	error = device_register (&kbddev);
+	error = device_register (&kbddev);
 	if(error==0) {
 		/* check if this is the standard input device */
 		if(strcmp(stdinname,DEVNAME)==0) {
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 67521720e7..fe8d3d87e9 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -23,7 +23,7 @@
 
 include $(TOPDIR)/config.mk
 
-LIB 	:= $(obj)libmisc.a
+LIB	:= $(obj)libmisc.a
 
 COBJS-y += ali512x.o
 COBJS-y += ns87308.o
@@ -31,8 +31,8 @@ COBJS-y += status_led.o
 COBJS-$(CONFIG_FSL_LAW) += fsl_law.o
 
 COBJS	:= $(COBJS-y)
-SRCS 	:= $(COBJS:.o=.c)
-OBJS 	:= $(addprefix $(obj),$(COBJS))
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
 
 all:	$(LIB)
 
diff --git a/drivers/misc/ali512x.c b/drivers/misc/ali512x.c
index 7b7edc09af..90b45d98b8 100644
--- a/drivers/misc/ali512x.c
+++ b/drivers/misc/ali512x.c
@@ -262,7 +262,7 @@ void ali512x_set_kbc(int enabled, u8 kbc_irq, u8 mouse_irq)
  * SIO reigster 3 (CIO Address Selection) bit definitions:
  * bit 7   CIO index and data registers enabled
  * bit 1-0 CIO indirect registers port address select
- *     	 0  index = 0xE0 data = 0xE1
+ *	 0  index = 0xE0 data = 0xE1
  *       1  index = 0xE2 data = 0xE3
  *       2  index = 0xE4 data = 0xE5
  *       3  index = 0xEA data = 0xEB
diff --git a/drivers/mtd/at45.c b/drivers/mtd/at45.c
index dac987a43a..a9d13ff90e 100644
--- a/drivers/mtd/at45.c
+++ b/drivers/mtd/at45.c
@@ -140,8 +140,8 @@ AT91S_DataFlashStatus AT91F_DataFlashWaitReady(AT91PS_DataflashDesc
 }
 
 /*--------------------------------------------------------------------------*/
-/* Function Name       : AT91F_DataFlashContinuousRead 			    */
-/* Object              : Continuous stream Read 			    */
+/* Function Name       : AT91F_DataFlashContinuousRead			    */
+/* Object              : Continuous stream Read			    */
 /* Input Parameters    : DataFlash Service				    */
 /*						: <src> = dataflash address */
 /*                     : <*dataBuffer> = data buffer pointer		    */
@@ -205,7 +205,7 @@ AT91S_DataFlashStatus AT91F_DataFlashPagePgmBuf(AT91PS_DataFlash pDataFlash,
 /* Object              : Read a page in the SRAM Buffer 1 or 2		     */
 /* Input Parameters    : DataFlash Service				     */
 /*                     : Page concerned					     */
-/*                     : 						     */
+/*                     :						     */
 /* Return value		: State of the dataflash			     */
 /*---------------------------------------------------------------------------*/
 AT91S_DataFlashStatus AT91F_MainMemoryToBufferTransfert(
@@ -303,10 +303,10 @@ AT91S_DataFlashStatus AT91F_DataFlashWriteBuffer(
 
 /*---------------------------------------------------------------------------*/
 /* Function Name       : AT91F_PageErase                                     */
-/* Object              : Erase a page 					     */
+/* Object              : Erase a page					     */
 /* Input Parameters    : DataFlash Service				     */
 /*                     : Page concerned					     */
-/*                     : 						     */
+/*                     :						     */
 /* Return value		: State of the dataflash			     */
 /*---------------------------------------------------------------------------*/
 AT91S_DataFlashStatus AT91F_PageErase(
@@ -328,10 +328,10 @@ AT91S_DataFlashStatus AT91F_PageErase(
 
 /*---------------------------------------------------------------------------*/
 /* Function Name       : AT91F_BlockErase                                    */
-/* Object              : Erase a Block 					     */
+/* Object              : Erase a Block					     */
 /* Input Parameters    : DataFlash Service				     */
 /*                     : Page concerned					     */
-/*                     : 						     */
+/*                     :						     */
 /* Return value		: State of the dataflash			     */
 /*---------------------------------------------------------------------------*/
 AT91S_DataFlashStatus AT91F_BlockErase(
@@ -510,10 +510,10 @@ AT91S_DataFlashStatus AT91F_DataFlashWrite(AT91PS_DataFlash pDataFlash,
 }
 
 /*---------------------------------------------------------------------------*/
-/* Function Name       : AT91F_DataFlashRead 				     */
+/* Function Name       : AT91F_DataFlashRead				     */
 /* Object              : Read a block in dataflash			     */
-/* Input Parameters    : 						     */
-/* Return value		: 						     */
+/* Input Parameters    :						     */
+/* Return value		:						     */
 /*---------------------------------------------------------------------------*/
 int AT91F_DataFlashRead(AT91PS_DataFlash pDataFlash,
 			unsigned long addr, unsigned long size, char *buffer)
@@ -548,9 +548,9 @@ int AT91F_DataFlashRead(AT91PS_DataFlash pDataFlash,
 }
 
 /*---------------------------------------------------------------------------*/
-/* Function Name       : AT91F_DataflashProbe 				     */
-/* Object              : 						     */
-/* Input Parameters    : 						     */
+/* Function Name       : AT91F_DataflashProbe				     */
+/* Object              :						     */
+/* Input Parameters    :						     */
 /* Return value	       : Dataflash status register			     */
 /*---------------------------------------------------------------------------*/
 int AT91F_DataflashProbe(int cs, AT91PS_DataflashDesc pDesc)
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 244fa09b20..7bd22a0c9d 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -23,7 +23,7 @@
 
 include $(TOPDIR)/config.mk
 
-LIB 	:= $(obj)libnand.a
+LIB	:= $(obj)libnand.a
 
 COBJS-y += nand.o
 COBJS-y += nand_base.o
@@ -35,8 +35,8 @@ COBJS-y += nand_util.o
 COBJS-y += fsl_upm.o
 
 COBJS	:= $(COBJS-y)
-SRCS 	:= $(COBJS:.o=.c)
-OBJS 	:= $(addprefix $(obj),$(COBJS))
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
 
 all:	$(LIB)
 
diff --git a/drivers/mtd/nand/diskonchip.c b/drivers/mtd/nand/diskonchip.c
index e17af70d07..fdd85c159d 100644
--- a/drivers/mtd/nand/diskonchip.c
+++ b/drivers/mtd/nand/diskonchip.c
@@ -187,7 +187,7 @@ static int doc_ecc_decode (struct rs_control *rs, uint8_t *data, uint8_t *ecc)
 	/* Calc s[i] = s[i] / alpha^(v + i) */
 	for (i = 0; i < NROOTS; i++) {
 		if (syn[i])
- 			syn[i] = rs_modnn(rs, rs->index_of[s[i]] + (NN - FCR - i));
+			syn[i] = rs_modnn(rs, rs->index_of[s[i]] + (NN - FCR - i));
 	}
 	/* Call the decoder library */
 	nerr = decode_rs16(rs, NULL, NULL, 1019, syn, 0, errpos, 0, errval);
@@ -357,7 +357,7 @@ static void doc2000_readbuf(struct mtd_info *mtd,
 	struct nand_chip *this = mtd->priv;
 	struct doc_priv *doc = this->priv;
 	void __iomem *docptr = doc->virtadr;
- 	int i;
+	int i;
 
 	if (debug)printk("readbuf of %d bytes: ", len);
 
@@ -372,7 +372,7 @@ static void doc2000_readbuf_dword(struct mtd_info *mtd,
 	struct nand_chip *this = mtd->priv;
 	struct doc_priv *doc = this->priv;
 	void __iomem *docptr = doc->virtadr;
- 	int i;
+	int i;
 
 	if (debug) printk("readbuf_dword of %d bytes: ", len);
 
@@ -1710,7 +1710,7 @@ fail:
 
 static void release_nanddoc(void)
 {
- 	struct mtd_info *mtd, *nextmtd;
+	struct mtd_info *mtd, *nextmtd;
 	struct nand_chip *nand;
 	struct doc_priv *doc;
 
@@ -1739,7 +1739,7 @@ static int __init init_nanddoc(void)
 	 * generator polinomial degree = 4
 	 */
 	rs_decoder = init_rs(10, 0x409, FCR, 1, NROOTS);
- 	if (!rs_decoder) {
+	if (!rs_decoder) {
 		printk (KERN_ERR "DiskOnChip: Could not create a RS decoder\n");
 		return -ENOMEM;
 	}
diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index 2da1d4621c..5aef31cd18 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -10,7 +10,7 @@
  *	http://www.linux-mtd.infradead.org/tech/nand.html
  *
  *  Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
- * 		  2002 Thomas Gleixner (tglx@linutronix.de)
+ *		  2002 Thomas Gleixner (tglx@linutronix.de)
  *
  *  02-08-2004  tglx: support for strange chips, which cannot auto increment
  *		pages on read / read_oob
@@ -838,7 +838,7 @@ static int nand_wait(struct mtd_info *mtd, struct nand_chip *this, int state)
 	unsigned long	timeo;
 
 	if (state == FL_ERASING)
- 		timeo = (CFG_HZ * 400) / 1000;
+		timeo = (CFG_HZ * 400) / 1000;
 	else
 		timeo = (CFG_HZ * 20) / 1000;
 
@@ -876,7 +876,7 @@ static int nand_wait(struct mtd_info *mtd, struct nand_chip *this, int state)
  * nand_write_page - [GENERIC] write one page
  * @mtd:	MTD device structure
  * @this:	NAND chip structure
- * @page: 	startpage inside the chip, must be called with (page & this->pagemask)
+ * @page:	startpage inside the chip, must be called with (page & this->pagemask)
  * @oob_buf:	out of band data buffer
  * @oobsel:	out of band selecttion structre
  * @cached:	1 = enable cached programming if supported by chip
@@ -890,10 +890,10 @@ static int nand_wait(struct mtd_info *mtd, struct nand_chip *this, int state)
 static int nand_write_page (struct mtd_info *mtd, struct nand_chip *this, int page,
 	u_char *oob_buf,  struct nand_oobinfo *oobsel, int cached)
 {
-	int 	i, status;
+	int	i, status;
 	u_char	ecc_code[32];
 	int	eccmode = oobsel->useecc ? this->eccmode : NAND_ECC_NONE;
-	uint  	*oob_config = oobsel->eccpos;
+	uint	*oob_config = oobsel->eccpos;
 	int	datidx = 0, eccidx = 0, eccsteps = this->eccsteps;
 	int	eccbytes = 0;
 
@@ -970,7 +970,7 @@ static int nand_write_page (struct mtd_info *mtd, struct nand_chip *this, int pa
  * nand_verify_pages - [GENERIC] verify the chip contents after a write
  * @mtd:	MTD device structure
  * @this:	NAND chip structure
- * @page: 	startpage inside the chip, must be called with (page & this->pagemask)
+ * @page:	startpage inside the chip, must be called with (page & this->pagemask)
  * @numpages:	number of pages to verify
  * @oob_buf:	out of band data buffer
  * @oobsel:	out of band selecttion structre
@@ -988,10 +988,10 @@ static int nand_write_page (struct mtd_info *mtd, struct nand_chip *this, int pa
 static int nand_verify_pages (struct mtd_info *mtd, struct nand_chip *this, int page, int numpages,
 	u_char *oob_buf, struct nand_oobinfo *oobsel, int chipnr, int oobmode)
 {
-	int 	i, j, datidx = 0, oobofs = 0, res = -EIO;
+	int	i, j, datidx = 0, oobofs = 0, res = -EIO;
 	int	eccsteps = this->eccsteps;
 	int	hweccbytes;
-	u_char 	oobdata[64];
+	u_char	oobdata[64];
 
 	hweccbytes = (this->options & NAND_HWECC_SYNDROME) ? (oobsel->eccbytes / eccsteps) : 0;
 
@@ -1035,7 +1035,7 @@ static int nand_verify_pages (struct mtd_info *mtd, struct nand_chip *this, int
 					int idx = oobsel->eccpos[i];
 					if (oobdata[idx] != oob_buf[oobofs + idx] ) {
 						DEBUG (MTD_DEBUG_LEVEL0,
-					       	"%s: Failed ECC write "
+						"%s: Failed ECC write "
 						"verify, page 0x%08x, " "%6i bytes were succesful\n", __FUNCTION__, page, i);
 						goto out;
 					}
@@ -1739,7 +1739,7 @@ static int nand_write_ecc (struct mtd_info *mtd, loff_t to, size_t len,
 	/* Verify the remaining pages */
 cmp:
 	this->data_poi = bufstart;
- 	ret = nand_verify_pages (mtd, this, startpage, totalpages,
+	ret = nand_verify_pages (mtd, this, startpage, totalpages,
 		oobbuf, oobsel, chipnr, (eccbuf != NULL));
 	if (!ret)
 		*retlen = written;
diff --git a/drivers/mtd/nand/nand_bbt.c b/drivers/mtd/nand/nand_bbt.c
index 19a9bc2a5b..eff76d717c 100644
--- a/drivers/mtd/nand/nand_bbt.c
+++ b/drivers/mtd/nand/nand_bbt.c
@@ -34,9 +34,9 @@
  * number which indicates which of both tables is more up to date.
  *
  * The table uses 2 bits per block
- * 11b: 	block is good
- * 00b: 	block is factory marked bad
- * 01b, 10b: 	block is marked bad due to wear
+ * 11b:	block is good
+ * 00b:	block is factory marked bad
+ * 01b, 10b:	block is marked bad due to wear
  *
  * The memory bad block table uses the following scheme:
  * 00b:		block is good
@@ -739,7 +739,7 @@ static void mark_bbt_region (struct mtd_info *mtd, struct nand_bbt_descr *td)
 	for (i = 0; i < chips; i++) {
 		if ((td->options & NAND_BBT_ABSPAGE) ||
 		    !(td->options & NAND_BBT_WRITE)) {
-		    	if (td->pages[i] == -1) continue;
+			if (td->pages[i] == -1) continue;
 			block = td->pages[i] >> (this->bbt_erase_shift - this->page_shift);
 			block <<= 1;
 			oldval = this->bbt[(block >> 3)];
diff --git a/drivers/mtd/nand/nand_ids.c b/drivers/mtd/nand/nand_ids.c
index 524b6b19a7..7363490395 100644
--- a/drivers/mtd/nand/nand_ids.c
+++ b/drivers/mtd/nand/nand_ids.c
@@ -23,82 +23,82 @@
 *	Name. ID code, pagesize, chipsize in MegaByte, eraseblock size,
 *	options
 *
-* 	Pagesize; 0, 256, 512
-*	0 	get this information from the extended chip ID
+*	Pagesize; 0, 256, 512
+*	0	get this information from the extended chip ID
 +	256	256 Byte page size
 *	512	512 Byte page size
 */
 struct nand_flash_dev nand_flash_ids[] = {
-	{"NAND 1MiB 5V 8-bit", 		0x6e, 256, 1, 0x1000, 0},
-	{"NAND 2MiB 5V 8-bit", 		0x64, 256, 2, 0x1000, 0},
-	{"NAND 4MiB 5V 8-bit", 		0x6b, 512, 4, 0x2000, 0},
-	{"NAND 1MiB 3,3V 8-bit", 	0xe8, 256, 1, 0x1000, 0},
-	{"NAND 1MiB 3,3V 8-bit", 	0xec, 256, 1, 0x1000, 0},
-	{"NAND 2MiB 3,3V 8-bit", 	0xea, 256, 2, 0x1000, 0},
-	{"NAND 4MiB 3,3V 8-bit", 	0xd5, 512, 4, 0x2000, 0},
-	{"NAND 4MiB 3,3V 8-bit", 	0xe3, 512, 4, 0x2000, 0},
-	{"NAND 4MiB 3,3V 8-bit", 	0xe5, 512, 4, 0x2000, 0},
-	{"NAND 8MiB 3,3V 8-bit", 	0xd6, 512, 8, 0x2000, 0},
-
-	{"NAND 8MiB 1,8V 8-bit", 	0x39, 512, 8, 0x2000, 0},
-	{"NAND 8MiB 3,3V 8-bit", 	0xe6, 512, 8, 0x2000, 0},
-	{"NAND 8MiB 1,8V 16-bit", 	0x49, 512, 8, 0x2000, NAND_BUSWIDTH_16},
-	{"NAND 8MiB 3,3V 16-bit", 	0x59, 512, 8, 0x2000, NAND_BUSWIDTH_16},
-
-	{"NAND 16MiB 1,8V 8-bit", 	0x33, 512, 16, 0x4000, 0},
-	{"NAND 16MiB 3,3V 8-bit", 	0x73, 512, 16, 0x4000, 0},
-	{"NAND 16MiB 1,8V 16-bit", 	0x43, 512, 16, 0x4000, NAND_BUSWIDTH_16},
-	{"NAND 16MiB 3,3V 16-bit", 	0x53, 512, 16, 0x4000, NAND_BUSWIDTH_16},
-
-	{"NAND 32MiB 1,8V 8-bit", 	0x35, 512, 32, 0x4000, 0},
-	{"NAND 32MiB 3,3V 8-bit", 	0x75, 512, 32, 0x4000, 0},
-	{"NAND 32MiB 1,8V 16-bit", 	0x45, 512, 32, 0x4000, NAND_BUSWIDTH_16},
-	{"NAND 32MiB 3,3V 16-bit", 	0x55, 512, 32, 0x4000, NAND_BUSWIDTH_16},
-
-	{"NAND 64MiB 1,8V 8-bit", 	0x36, 512, 64, 0x4000, 0},
-	{"NAND 64MiB 3,3V 8-bit", 	0x76, 512, 64, 0x4000, 0},
-	{"NAND 64MiB 1,8V 16-bit", 	0x46, 512, 64, 0x4000, NAND_BUSWIDTH_16},
-	{"NAND 64MiB 3,3V 16-bit", 	0x56, 512, 64, 0x4000, NAND_BUSWIDTH_16},
-
-	{"NAND 128MiB 1,8V 8-bit", 	0x78, 512, 128, 0x4000, 0},
-	{"NAND 128MiB 3,3V 8-bit", 	0x79, 512, 128, 0x4000, 0},
-	{"NAND 128MiB 1,8V 16-bit", 	0x72, 512, 128, 0x4000, NAND_BUSWIDTH_16},
-	{"NAND 128MiB 3,3V 16-bit", 	0x74, 512, 128, 0x4000, NAND_BUSWIDTH_16},
-
-	{"NAND 256MiB 3,3V 8-bit", 	0x71, 512, 256, 0x4000, 0},
+	{"NAND 1MiB 5V 8-bit",		0x6e, 256, 1, 0x1000, 0},
+	{"NAND 2MiB 5V 8-bit",		0x64, 256, 2, 0x1000, 0},
+	{"NAND 4MiB 5V 8-bit",		0x6b, 512, 4, 0x2000, 0},
+	{"NAND 1MiB 3,3V 8-bit",	0xe8, 256, 1, 0x1000, 0},
+	{"NAND 1MiB 3,3V 8-bit",	0xec, 256, 1, 0x1000, 0},
+	{"NAND 2MiB 3,3V 8-bit",	0xea, 256, 2, 0x1000, 0},
+	{"NAND 4MiB 3,3V 8-bit",	0xd5, 512, 4, 0x2000, 0},
+	{"NAND 4MiB 3,3V 8-bit",	0xe3, 512, 4, 0x2000, 0},
+	{"NAND 4MiB 3,3V 8-bit",	0xe5, 512, 4, 0x2000, 0},
+	{"NAND 8MiB 3,3V 8-bit",	0xd6, 512, 8, 0x2000, 0},
+
+	{"NAND 8MiB 1,8V 8-bit",	0x39, 512, 8, 0x2000, 0},
+	{"NAND 8MiB 3,3V 8-bit",	0xe6, 512, 8, 0x2000, 0},
+	{"NAND 8MiB 1,8V 16-bit",	0x49, 512, 8, 0x2000, NAND_BUSWIDTH_16},
+	{"NAND 8MiB 3,3V 16-bit",	0x59, 512, 8, 0x2000, NAND_BUSWIDTH_16},
+
+	{"NAND 16MiB 1,8V 8-bit",	0x33, 512, 16, 0x4000, 0},
+	{"NAND 16MiB 3,3V 8-bit",	0x73, 512, 16, 0x4000, 0},
+	{"NAND 16MiB 1,8V 16-bit",	0x43, 512, 16, 0x4000, NAND_BUSWIDTH_16},
+	{"NAND 16MiB 3,3V 16-bit",	0x53, 512, 16, 0x4000, NAND_BUSWIDTH_16},
+
+	{"NAND 32MiB 1,8V 8-bit",	0x35, 512, 32, 0x4000, 0},
+	{"NAND 32MiB 3,3V 8-bit",	0x75, 512, 32, 0x4000, 0},
+	{"NAND 32MiB 1,8V 16-bit",	0x45, 512, 32, 0x4000, NAND_BUSWIDTH_16},
+	{"NAND 32MiB 3,3V 16-bit",	0x55, 512, 32, 0x4000, NAND_BUSWIDTH_16},
+
+	{"NAND 64MiB 1,8V 8-bit",	0x36, 512, 64, 0x4000, 0},
+	{"NAND 64MiB 3,3V 8-bit",	0x76, 512, 64, 0x4000, 0},
+	{"NAND 64MiB 1,8V 16-bit",	0x46, 512, 64, 0x4000, NAND_BUSWIDTH_16},
+	{"NAND 64MiB 3,3V 16-bit",	0x56, 512, 64, 0x4000, NAND_BUSWIDTH_16},
+
+	{"NAND 128MiB 1,8V 8-bit",	0x78, 512, 128, 0x4000, 0},
+	{"NAND 128MiB 3,3V 8-bit",	0x79, 512, 128, 0x4000, 0},
+	{"NAND 128MiB 1,8V 16-bit",	0x72, 512, 128, 0x4000, NAND_BUSWIDTH_16},
+	{"NAND 128MiB 3,3V 16-bit",	0x74, 512, 128, 0x4000, NAND_BUSWIDTH_16},
+
+	{"NAND 256MiB 3,3V 8-bit",	0x71, 512, 256, 0x4000, 0},
 
 	/* These are the new chips with large page size. The pagesize
 	* and the erasesize is determined from the extended id bytes
 	*/
 	/* 1 Gigabit */
-	{"NAND 128MiB 1,8V 8-bit", 	0xA1, 0, 128, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR},
-	{"NAND 128MiB 3,3V 8-bit", 	0xF1, 0, 128, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR},
-	{"NAND 128MiB 1,8V 16-bit", 	0xB1, 0, 128, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR},
-	{"NAND 128MiB 3,3V 16-bit", 	0xC1, 0, 128, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR},
+	{"NAND 128MiB 1,8V 8-bit",	0xA1, 0, 128, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR},
+	{"NAND 128MiB 3,3V 8-bit",	0xF1, 0, 128, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR},
+	{"NAND 128MiB 1,8V 16-bit",	0xB1, 0, 128, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR},
+	{"NAND 128MiB 3,3V 16-bit",	0xC1, 0, 128, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR},
 
 	/* 2 Gigabit */
-	{"NAND 256MiB 1,8V 8-bit", 	0xAA, 0, 256, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR},
-	{"NAND 256MiB 3,3V 8-bit", 	0xDA, 0, 256, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR},
-	{"NAND 256MiB 1,8V 16-bit", 	0xBA, 0, 256, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR},
-	{"NAND 256MiB 3,3V 16-bit", 	0xCA, 0, 256, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR},
+	{"NAND 256MiB 1,8V 8-bit",	0xAA, 0, 256, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR},
+	{"NAND 256MiB 3,3V 8-bit",	0xDA, 0, 256, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR},
+	{"NAND 256MiB 1,8V 16-bit",	0xBA, 0, 256, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR},
+	{"NAND 256MiB 3,3V 16-bit",	0xCA, 0, 256, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR},
 
 	/* 4 Gigabit */
-	{"NAND 512MiB 1,8V 8-bit", 	0xAC, 0, 512, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR},
-	{"NAND 512MiB 3,3V 8-bit", 	0xDC, 0, 512, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR},
-	{"NAND 512MiB 1,8V 16-bit", 	0xBC, 0, 512, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR},
-	{"NAND 512MiB 3,3V 16-bit", 	0xCC, 0, 512, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR},
+	{"NAND 512MiB 1,8V 8-bit",	0xAC, 0, 512, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR},
+	{"NAND 512MiB 3,3V 8-bit",	0xDC, 0, 512, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR},
+	{"NAND 512MiB 1,8V 16-bit",	0xBC, 0, 512, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR},
+	{"NAND 512MiB 3,3V 16-bit",	0xCC, 0, 512, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR},
 
 	/* 8 Gigabit */
-	{"NAND 1GiB 1,8V 8-bit", 	0xA3, 0, 1024, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR},
-	{"NAND 1GiB 3,3V 8-bit", 	0xD3, 0, 1024, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR},
-	{"NAND 1GiB 1,8V 16-bit", 	0xB3, 0, 1024, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR},
-	{"NAND 1GiB 3,3V 16-bit", 	0xC3, 0, 1024, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR},
+	{"NAND 1GiB 1,8V 8-bit",	0xA3, 0, 1024, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR},
+	{"NAND 1GiB 3,3V 8-bit",	0xD3, 0, 1024, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR},
+	{"NAND 1GiB 1,8V 16-bit",	0xB3, 0, 1024, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR},
+	{"NAND 1GiB 3,3V 16-bit",	0xC3, 0, 1024, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR},
 
 	/* 16 Gigabit */
-	{"NAND 2GiB 1,8V 8-bit", 	0xA5, 0, 2048, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR},
-	{"NAND 2GiB 3,3V 8-bit", 	0xD5, 0, 2048, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR},
-	{"NAND 2GiB 1,8V 16-bit", 	0xB5, 0, 2048, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR},
-	{"NAND 2GiB 3,3V 16-bit", 	0xC5, 0, 2048, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR},
+	{"NAND 2GiB 1,8V 8-bit",	0xA5, 0, 2048, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR},
+	{"NAND 2GiB 3,3V 8-bit",	0xD5, 0, 2048, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR},
+	{"NAND 2GiB 1,8V 16-bit",	0xB5, 0, 2048, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR},
+	{"NAND 2GiB 3,3V 16-bit",	0xC5, 0, 2048, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR},
 
 	/* Renesas AND 1 Gigabit. Those chips do not support extended id and have a strange page/block layout !
 	 * The chosen minimum erasesize is 4 * 2 * 2048 = 16384 Byte, as those chips have an array of 4 page planes
diff --git a/drivers/mtd/nand_legacy/Makefile b/drivers/mtd/nand_legacy/Makefile
index 95314d80ba..4e29c36e70 100644
--- a/drivers/mtd/nand_legacy/Makefile
+++ b/drivers/mtd/nand_legacy/Makefile
@@ -23,12 +23,12 @@
 
 include $(TOPDIR)/config.mk
 
-LIB 	:= $(obj)libnand_legacy.a
+LIB	:= $(obj)libnand_legacy.a
 
-COBJS 	:= nand_legacy.o
+COBJS	:= nand_legacy.o
 
-SRCS 	:= $(COBJS:.o=.c)
-OBJS 	:= $(addprefix $(obj),$(COBJS))
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
 
 all:	$(LIB)
 
diff --git a/drivers/mtd/nand_legacy/nand_legacy.c b/drivers/mtd/nand_legacy/nand_legacy.c
index 49d2ebb67d..fafefad60f 100644
--- a/drivers/mtd/nand_legacy/nand_legacy.c
+++ b/drivers/mtd/nand_legacy/nand_legacy.c
@@ -438,7 +438,7 @@ static int NanD_IdentChip(struct nand_chip *nand, int floor, int chip)
 				nand->erasesize  = nand_flash_ids[i].erasesize;
 				nand->chips_name = nand_flash_ids[i].name;
 				nand->bus16	 = nand_flash_ids[i].bus16;
- 				return 1;
+				return 1;
 			}
 			return 0;
 		}
@@ -638,10 +638,10 @@ static int nand_read_ecc(struct nand_chip *nand, size_t start, size_t len,
 		/* Send the read command */
 		NanD_Command(nand, NAND_CMD_READ0);
 		if (nand->bus16) {
- 			NanD_Address(nand, ADDR_COLUMN_PAGE,
+			NanD_Address(nand, ADDR_COLUMN_PAGE,
 				     (page << nand->page_shift) + (col >> 1));
 		} else {
- 			NanD_Address(nand, ADDR_COLUMN_PAGE,
+			NanD_Address(nand, ADDR_COLUMN_PAGE,
 				     (page << nand->page_shift) + col);
 		}
 
@@ -989,7 +989,7 @@ static int nand_write_ecc (struct nand_chip* nand, size_t to, size_t len,
 	NAND_WP_OFF();
 #endif
 
-    	NAND_ENABLE_CE(nand);  /* set pin low */
+	NAND_ENABLE_CE(nand);  /* set pin low */
 
 	/* Check the WP bit */
 	NanD_Command(nand, NAND_CMD_STATUS);
@@ -1037,7 +1037,7 @@ out:
 	/* De-select the NAND device */
 	NAND_DISABLE_CE(nand);  /* set pin high */
 #ifdef CONFIG_OMAP1510
-    	archflashwp(0,1);
+	archflashwp(0,1);
 #endif
 #ifdef CFG_NAND_WP
 	NAND_WP_ON();
@@ -1070,9 +1070,9 @@ int nand_read_oob(struct nand_chip* nand, size_t ofs, size_t len,
 	NAND_ENABLE_CE(nand);  /* set pin low */
 	NanD_Command(nand, NAND_CMD_READOOB);
 	if (nand->bus16) {
- 		NanD_Address(nand, ADDR_COLUMN_PAGE,
+		NanD_Address(nand, ADDR_COLUMN_PAGE,
 			     ((ofs >> nand->page_shift) << nand->page_shift) +
- 				((ofs & (nand->oobblock - 1)) >> 1));
+				((ofs & (nand->oobblock - 1)) >> 1));
 	} else {
 		NanD_Address(nand, ADDR_COLUMN_PAGE, ofs);
 	}
@@ -1126,11 +1126,11 @@ int nand_write_oob(struct nand_chip* nand, size_t ofs, size_t len,
 	/* issue the Read2 command to set the pointer to the Spare Data Area. */
 	NanD_Command(nand, NAND_CMD_READOOB);
 	if (nand->bus16) {
- 		NanD_Address(nand, ADDR_COLUMN_PAGE,
+		NanD_Address(nand, ADDR_COLUMN_PAGE,
 			     ((ofs >> nand->page_shift) << nand->page_shift) +
- 				((ofs & (nand->oobblock - 1)) >> 1));
+				((ofs & (nand->oobblock - 1)) >> 1));
 	} else {
- 		NanD_Address(nand, ADDR_COLUMN_PAGE, ofs);
+		NanD_Address(nand, ADDR_COLUMN_PAGE, ofs);
 	}
 
 	/* update address for 2M x 8bit devices. OOB starts on the second */
@@ -1145,11 +1145,11 @@ int nand_write_oob(struct nand_chip* nand, size_t ofs, size_t len,
 	/* issue the Serial Data In command to initial the Page Program process */
 	NanD_Command(nand, NAND_CMD_SEQIN);
 	if (nand->bus16) {
- 		NanD_Address(nand, ADDR_COLUMN_PAGE,
+		NanD_Address(nand, ADDR_COLUMN_PAGE,
 			     ((ofs >> nand->page_shift) << nand->page_shift) +
- 				((ofs & (nand->oobblock - 1)) >> 1));
+				((ofs & (nand->oobblock - 1)) >> 1));
 	} else {
- 		NanD_Address(nand, ADDR_COLUMN_PAGE, ofs);
+		NanD_Address(nand, ADDR_COLUMN_PAGE, ofs);
 	}
 
 	/* treat crossing 8-byte OOB data for 2M x 8bit devices */
@@ -1163,7 +1163,7 @@ int nand_write_oob(struct nand_chip* nand, size_t ofs, size_t len,
 		NanD_Command(nand, NAND_CMD_PAGEPROG);
 		NanD_Command(nand, NAND_CMD_STATUS);
 #ifdef NAND_NO_RB
-   		{ u_char ret_val;
+		{ u_char ret_val;
 			do {
 				ret_val = READ_NAND(nandptr); /* wait till ready */
 			} while ((ret_val & 0x40) != 0x40);
@@ -1322,7 +1322,7 @@ out:
 	/* De-select the NAND device */
 	NAND_DISABLE_CE(nand);  /* set pin high */
 #ifdef CONFIG_OMAP1510
-    	archflashwp(0,1);
+	archflashwp(0,1);
 #endif
 #ifdef CFG_NAND_WP
 	NAND_WP_ON();
diff --git a/drivers/net/3c589.c b/drivers/net/3c589.c
index 080b686e21..3f1e770efe 100644
--- a/drivers/net/3c589.c
+++ b/drivers/net/3c589.c
@@ -99,7 +99,7 @@ typedef unsigned long int dword;
 				})
 
 #define insw(args...)	mmio_insw(args)
-#define mmio_insw(r,b,l) 	({	int __i ;  \
+#define mmio_insw(r,b,l)	({	int __i ;  \
 					word *__b2;  \
 					__b2 = (word *) b;  \
 					for (__i = 0; __i < l; __i++) {  \
@@ -154,8 +154,8 @@ enum RxFilter {
 /* Register window 1 offsets, the window used in normal operation. */
 #define TX_FIFO		0x00
 #define RX_FIFO		0x00
-#define RX_STATUS 	0x08
-#define TX_STATUS 	0x0B
+#define RX_STATUS	0x08
+#define TX_STATUS	0x0B
 #define TX_FREE		0x0C	/* Remaining free bytes in Tx buffer. */
 
 
diff --git a/drivers/net/3c589.h b/drivers/net/3c589.h
index 6735bf9f63..8f8cf5be1d 100644
--- a/drivers/net/3c589.h
+++ b/drivers/net/3c589.h
@@ -64,7 +64,7 @@
 /*
  * some macros to acces long named fields
  */
-#define BASE 	(EL_BASE_ADDR)
+#define BASE	(EL_BASE_ADDR)
 
 /*
  * Commands to read/write EEPROM trough EEPROM command register (Window 0,
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 4131aad98d..5b031c9af1 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -23,7 +23,7 @@
 
 include $(TOPDIR)/config.mk
 
-LIB 	:= $(obj)libnet.a
+LIB	:= $(obj)libnet.a
 
 COBJS-y += 3c589.o
 COBJS-y += bcm570x.o bcm570x_autoneg.o 5701rls.o
@@ -68,8 +68,8 @@ COBJS-$(CONFIG_XILINX_EMAC) += xilinx_emac.o
 COBJS-$(CONFIG_XILINX_EMACLITE) += xilinx_emaclite.o
 
 COBJS	:= $(COBJS-y)
-SRCS 	:= $(COBJS:.o=.c)
-OBJS 	:= $(addprefix $(obj),$(COBJS))
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
 
 all:	$(LIB)
 
diff --git a/drivers/net/bcm570x.c b/drivers/net/bcm570x.c
index c8f4064224..5ad31d1fdb 100644
--- a/drivers/net/bcm570x.c
+++ b/drivers/net/bcm570x.c
@@ -27,7 +27,7 @@
 /*
  * PCI memory base for Ethernet device as well as device Interrupt.
  */
-#define BCM570X_MBAR 	0x80100000
+#define BCM570X_MBAR	0x80100000
 #define BCM570X_ILINE   1
 
 #define SECOND_USEC	1000000
diff --git a/drivers/net/bfin_mac.c b/drivers/net/bfin_mac.c
index afe122a337..fe56949989 100644
--- a/drivers/net/bfin_mac.c
+++ b/drivers/net/bfin_mac.c
@@ -35,7 +35,7 @@
 #define TXBUF_BASE_ADDR		0xFF800000
 #define TX_BUF_CNT		1
 
-#define TOUT_LOOP 		1000000
+#define TOUT_LOOP		1000000
 
 ADI_ETHER_BUFFER *txbuf[TX_BUF_CNT];
 ADI_ETHER_BUFFER *rxbuf[PKTBUFSRX];
diff --git a/drivers/net/dc2114x.c b/drivers/net/dc2114x.c
index 7238922614..1d728d8b30 100644
--- a/drivers/net/dc2114x.c
+++ b/drivers/net/dc2114x.c
@@ -212,14 +212,14 @@ static struct pci_device_id supported[] = {
 
 int dc21x4x_initialize(bd_t *bis)
 {
-	int             	idx=0;
-	int             	card_number = 0;
-	unsigned int           	cfrv;
-	unsigned char   	timer;
+	int			idx=0;
+	int			card_number = 0;
+	unsigned int		cfrv;
+	unsigned char		timer;
 	pci_dev_t		devbusfn;
 	unsigned int		iobase;
 	unsigned short		status;
-	struct eth_device* 	dev;
+	struct eth_device*	dev;
 
 	while(1) {
 		devbusfn =  pci_find_devices(supported, idx++);
@@ -490,7 +490,7 @@ static void send_setup_frame(struct eth_device* dev, bd_t *bis)
 {
 	int		i;
 	char	setup_frame[SETUP_FRAME_LEN];
-	char 	*pa = &setup_frame[0];
+	char	*pa = &setup_frame[0];
 
 	memset(pa, 0xff, SETUP_FRAME_LEN);
 
@@ -738,22 +738,22 @@ static void update_srom(struct eth_device *dev, bd_t *bis)
 {
 	int i;
 	static unsigned short eeprom[0x40] = {
-		0x140b, 0x6610, 0x0000, 0x0000, 	/* 00 */
-		0x0000, 0x0000, 0x0000, 0x0000, 	/* 04 */
-		0x00a3, 0x0103, 0x0000, 0x0000,  	/* 08 */
-		0x0000, 0x1f00, 0x0000, 0x0000, 	/* 0c */
-		0x0108, 0x038d, 0x0000, 0x0000,  	/* 10 */
-		0xe078, 0x0001, 0x0040, 0x0018, 	/* 14 */
-		0x0000, 0x0000, 0x0000, 0x0000,  	/* 18 */
-		0x0000, 0x0000, 0x0000, 0x0000, 	/* 1c */
-		0x0000, 0x0000, 0x0000, 0x0000,  	/* 20 */
-		0x0000, 0x0000, 0x0000, 0x0000, 	/* 24 */
-		0x0000, 0x0000, 0x0000, 0x0000,  	/* 28 */
-		0x0000, 0x0000, 0x0000, 0x0000, 	/* 2c */
-		0x0000, 0x0000, 0x0000, 0x0000,  	/* 30 */
-		0x0000, 0x0000, 0x0000, 0x0000, 	/* 34 */
-		0x0000, 0x0000, 0x0000, 0x0000,  	/* 38 */
-		0x0000, 0x0000, 0x0000, 0x4e07,		/* 3c */
+		0x140b, 0x6610, 0x0000, 0x0000,	/* 00 */
+		0x0000, 0x0000, 0x0000, 0x0000,	/* 04 */
+		0x00a3, 0x0103, 0x0000, 0x0000,	/* 08 */
+		0x0000, 0x1f00, 0x0000, 0x0000,	/* 0c */
+		0x0108, 0x038d, 0x0000, 0x0000,	/* 10 */
+		0xe078, 0x0001, 0x0040, 0x0018,	/* 14 */
+		0x0000, 0x0000, 0x0000, 0x0000,	/* 18 */
+		0x0000, 0x0000, 0x0000, 0x0000,	/* 1c */
+		0x0000, 0x0000, 0x0000, 0x0000,	/* 20 */
+		0x0000, 0x0000, 0x0000, 0x0000,	/* 24 */
+		0x0000, 0x0000, 0x0000, 0x0000,	/* 28 */
+		0x0000, 0x0000, 0x0000, 0x0000,	/* 2c */
+		0x0000, 0x0000, 0x0000, 0x0000,	/* 30 */
+		0x0000, 0x0000, 0x0000, 0x0000,	/* 34 */
+		0x0000, 0x0000, 0x0000, 0x0000,	/* 38 */
+		0x0000, 0x0000, 0x0000, 0x4e07,	/* 3c */
 	};
 
 	/* Ethernet Addr... */
@@ -761,8 +761,7 @@ static void update_srom(struct eth_device *dev, bd_t *bis)
 	eeprom[0x0b] = ((bis->bi_enetaddr[3] & 0xff) << 8) | (bis->bi_enetaddr[2] & 0xff);
 	eeprom[0x0c] = ((bis->bi_enetaddr[5] & 0xff) << 8) | (bis->bi_enetaddr[4] & 0xff);
 
-	for (i=0; i<0x40; i++)
-	{
+	for (i=0; i<0x40; i++) {
 		write_srom(dev, DE4X5_APROM, i, eeprom[i]);
 	}
 }
diff --git a/drivers/net/dm9000x.c b/drivers/net/dm9000x.c
index 6131b5c357..01e2f14a9d 100644
--- a/drivers/net/dm9000x.c
+++ b/drivers/net/dm9000x.c
@@ -17,17 +17,17 @@
   (C)Copyright 1997-1998 DAVICOM Semiconductor,Inc. All Rights Reserved.
 
 V0.11	06/20/2001	REG_0A bit3=1, default enable BP with DA match
-	06/22/2001 	Support DM9801 progrmming
-	 	 	E3: R25 = ((R24 + NF) & 0x00ff) | 0xf000
-		 	E4: R25 = ((R24 + NF) & 0x00ff) | 0xc200
-     		R17 = (R17 & 0xfff0) | NF + 3
-		 	E5: R25 = ((R24 + NF - 3) & 0x00ff) | 0xc200
-     		R17 = (R17 & 0xfff0) | NF
-
-v1.00               	modify by simon 2001.9.5
+	06/22/2001	Support DM9801 progrmming
+			E3: R25 = ((R24 + NF) & 0x00ff) | 0xf000
+			E4: R25 = ((R24 + NF) & 0x00ff) | 0xc200
+		R17 = (R17 & 0xfff0) | NF + 3
+			E5: R25 = ((R24 + NF - 3) & 0x00ff) | 0xc200
+		R17 = (R17 & 0xfff0) | NF
+
+v1.00			modify by simon 2001.9.5
 	                change for kernel 2.4.x
 
-v1.1   11/09/2001      	fix force mode bug
+v1.1   11/09/2001	fix force mode bug
 
 v1.2   03/18/2003       Weilun Huang <weilun_huang@davicom.com.tw>:
 			Fixed phy reset.
diff --git a/drivers/net/e1000.h b/drivers/net/e1000.h
index 822afc566f..851467d81c 100644
--- a/drivers/net/e1000.h
+++ b/drivers/net/e1000.h
@@ -15,7 +15,7 @@
 
   You should have received a copy of the GNU General Public License along with
   this program; if not, write to the Free Software Foundation, Inc., 59
-  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
+  Temple Place - Suite 330, Boston, MA	02111-1307, USA.
 
   The full GNU General Public License is included in this distribution in the
   file called LICENSE.
@@ -44,7 +44,7 @@
 #ifdef E1000_DEBUG
 #define E1000_DBG(args...)	printf("e1000: " args)
 #define DEBUGOUT(fmt,args...) printf(fmt ,##args)
-#define DEBUGFUNC()        printf("%s\n", __FUNCTION__);
+#define DEBUGFUNC()	   printf("%s\n", __FUNCTION__);
 #else
 #define E1000_DBG(args...)
 #define DEBUGFUNC()
@@ -193,35 +193,35 @@ struct e1000_phy_stats {
 };
 
 /* Error Codes */
-#define E1000_SUCCESS      			0
-#define E1000_ERR_EEPROM   			1
-#define E1000_ERR_PHY      			2
-#define E1000_ERR_CONFIG   			3
-#define E1000_ERR_PARAM    			4
-#define E1000_ERR_MAC_TYPE 			5
-#define E1000_ERR_PHY_TYPE 			6
-#define E1000_ERR_NOLINK   			7
-#define E1000_ERR_TIMEOUT  			8
-#define E1000_ERR_RESET   			9
-#define E1000_ERR_MASTER_REQUESTS_PENDING 	10
-#define E1000_ERR_HOST_INTERFACE_COMMAND 	11
-#define E1000_BLK_PHY_RESET   			12
+#define E1000_SUCCESS				0
+#define E1000_ERR_EEPROM			1
+#define E1000_ERR_PHY				2
+#define E1000_ERR_CONFIG			3
+#define E1000_ERR_PARAM				4
+#define E1000_ERR_MAC_TYPE			5
+#define E1000_ERR_PHY_TYPE			6
+#define E1000_ERR_NOLINK			7
+#define E1000_ERR_TIMEOUT			8
+#define E1000_ERR_RESET				9
+#define E1000_ERR_MASTER_REQUESTS_PENDING	10
+#define E1000_ERR_HOST_INTERFACE_COMMAND	11
+#define E1000_BLK_PHY_RESET			12
 
 /* PCI Device IDs */
-#define E1000_DEV_ID_82542          0x1000
+#define E1000_DEV_ID_82542	    0x1000
 #define E1000_DEV_ID_82543GC_FIBER  0x1001
 #define E1000_DEV_ID_82543GC_COPPER 0x1004
 #define E1000_DEV_ID_82544EI_COPPER 0x1008
 #define E1000_DEV_ID_82544EI_FIBER  0x1009
 #define E1000_DEV_ID_82544GC_COPPER 0x100C
 #define E1000_DEV_ID_82544GC_LOM    0x100D
-#define E1000_DEV_ID_82540EM        0x100E
+#define E1000_DEV_ID_82540EM	    0x100E
 #define E1000_DEV_ID_82540EM_LOM    0x1015
 #define E1000_DEV_ID_82545EM_COPPER 0x100F
 #define E1000_DEV_ID_82545EM_FIBER  0x1011
 #define E1000_DEV_ID_82546EB_COPPER 0x1010
 #define E1000_DEV_ID_82546EB_FIBER  0x1012
-#define E1000_DEV_ID_82541ER        0x1078
+#define E1000_DEV_ID_82541ER	    0x1078
 #define NUM_DEV_IDS 14
 
 #define NODE_ADDRESS_SIZE 6
@@ -240,24 +240,24 @@ struct e1000_phy_stats {
 #define FULL_DUPLEX 2
 
 /* The sizes (in bytes) of a ethernet packet */
-#define ENET_HEADER_SIZE             14
+#define ENET_HEADER_SIZE	     14
 #define MAXIMUM_ETHERNET_FRAME_SIZE  1518	/* With FCS */
 #define MINIMUM_ETHERNET_FRAME_SIZE  64	/* With FCS */
-#define ETHERNET_FCS_SIZE            4
+#define ETHERNET_FCS_SIZE	     4
 #define MAXIMUM_ETHERNET_PACKET_SIZE \
     (MAXIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE)
 #define MINIMUM_ETHERNET_PACKET_SIZE \
     (MINIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE)
-#define CRC_LENGTH                   ETHERNET_FCS_SIZE
-#define MAX_JUMBO_FRAME_SIZE         0x3F00
+#define CRC_LENGTH		     ETHERNET_FCS_SIZE
+#define MAX_JUMBO_FRAME_SIZE	     0x3F00
 
 /* 802.1q VLAN Packet Sizes */
-#define VLAN_TAG_SIZE                     4	/* 802.3ac tag (not DMAed) */
+#define VLAN_TAG_SIZE			  4	/* 802.3ac tag (not DMAed) */
 
 /* Ethertype field values */
 #define ETHERNET_IEEE_VLAN_TYPE 0x8100	/* 802.3ac packet */
-#define ETHERNET_IP_TYPE        0x0800	/* IP packets */
-#define ETHERNET_ARP_TYPE       0x0806	/* Address Resolution Protocol (ARP) */
+#define ETHERNET_IP_TYPE	0x0800	/* IP packets */
+#define ETHERNET_ARP_TYPE	0x0806	/* Address Resolution Protocol (ARP) */
 
 /* Packet Header defines */
 #define IP_PROTOCOL_TCP    6
@@ -269,7 +269,7 @@ struct e1000_phy_stats {
  *   o RXSEQ  = Receive Sequence Error
  */
 #define POLL_IMS_ENABLE_MASK ( \
-    E1000_IMS_RXDMT0 |         \
+    E1000_IMS_RXDMT0 |	       \
     E1000_IMS_RXSEQ)
 
 /* This defines the bits that are set in the Interrupt Mask
@@ -281,10 +281,10 @@ struct e1000_phy_stats {
  *   o LSC    = Link Status Change
  */
 #define IMS_ENABLE_MASK ( \
-    E1000_IMS_RXT0   |    \
-    E1000_IMS_TXDW   |    \
-    E1000_IMS_RXDMT0 |    \
-    E1000_IMS_RXSEQ  |    \
+    E1000_IMS_RXT0   |	  \
+    E1000_IMS_TXDW   |	  \
+    E1000_IMS_RXDMT0 |	  \
+    E1000_IMS_RXSEQ  |	  \
     E1000_IMS_LSC)
 
 /* The number of high/low register pairs in the RAR. The RAR (Receive Address
@@ -308,32 +308,32 @@ struct e1000_rx_desc {
 };
 
 /* Receive Decriptor bit definitions */
-#define E1000_RXD_STAT_DD       0x01	/* Descriptor Done */
-#define E1000_RXD_STAT_EOP      0x02	/* End of Packet */
-#define E1000_RXD_STAT_IXSM     0x04	/* Ignore checksum */
-#define E1000_RXD_STAT_VP       0x08	/* IEEE VLAN Packet */
-#define E1000_RXD_STAT_TCPCS    0x20	/* TCP xsum calculated */
-#define E1000_RXD_STAT_IPCS     0x40	/* IP xsum calculated */
-#define E1000_RXD_STAT_PIF      0x80	/* passed in-exact filter */
-#define E1000_RXD_ERR_CE        0x01	/* CRC Error */
-#define E1000_RXD_ERR_SE        0x02	/* Symbol Error */
-#define E1000_RXD_ERR_SEQ       0x04	/* Sequence Error */
-#define E1000_RXD_ERR_CXE       0x10	/* Carrier Extension Error */
-#define E1000_RXD_ERR_TCPE      0x20	/* TCP/UDP Checksum Error */
-#define E1000_RXD_ERR_IPE       0x40	/* IP Checksum Error */
-#define E1000_RXD_ERR_RXE       0x80	/* Rx Data Error */
+#define E1000_RXD_STAT_DD	0x01	/* Descriptor Done */
+#define E1000_RXD_STAT_EOP	0x02	/* End of Packet */
+#define E1000_RXD_STAT_IXSM	0x04	/* Ignore checksum */
+#define E1000_RXD_STAT_VP	0x08	/* IEEE VLAN Packet */
+#define E1000_RXD_STAT_TCPCS	0x20	/* TCP xsum calculated */
+#define E1000_RXD_STAT_IPCS	0x40	/* IP xsum calculated */
+#define E1000_RXD_STAT_PIF	0x80	/* passed in-exact filter */
+#define E1000_RXD_ERR_CE	0x01	/* CRC Error */
+#define E1000_RXD_ERR_SE	0x02	/* Symbol Error */
+#define E1000_RXD_ERR_SEQ	0x04	/* Sequence Error */
+#define E1000_RXD_ERR_CXE	0x10	/* Carrier Extension Error */
+#define E1000_RXD_ERR_TCPE	0x20	/* TCP/UDP Checksum Error */
+#define E1000_RXD_ERR_IPE	0x40	/* IP Checksum Error */
+#define E1000_RXD_ERR_RXE	0x80	/* Rx Data Error */
 #define E1000_RXD_SPC_VLAN_MASK 0x0FFF	/* VLAN ID is in lower 12 bits */
-#define E1000_RXD_SPC_PRI_MASK  0xE000	/* Priority is in upper 3 bits */
+#define E1000_RXD_SPC_PRI_MASK	0xE000	/* Priority is in upper 3 bits */
 #define E1000_RXD_SPC_PRI_SHIFT 0x000D	/* Priority is in upper 3 of 16 */
-#define E1000_RXD_SPC_CFI_MASK  0x1000	/* CFI is bit 12 */
+#define E1000_RXD_SPC_CFI_MASK	0x1000	/* CFI is bit 12 */
 #define E1000_RXD_SPC_CFI_SHIFT 0x000C	/* CFI is bit 12 */
 
 /* mask to determine if packets should be dropped due to frame errors */
 #define E1000_RXD_ERR_FRAME_ERR_MASK ( \
-    E1000_RXD_ERR_CE  |                \
-    E1000_RXD_ERR_SE  |                \
-    E1000_RXD_ERR_SEQ |                \
-    E1000_RXD_ERR_CXE |                \
+    E1000_RXD_ERR_CE  |		       \
+    E1000_RXD_ERR_SE  |		       \
+    E1000_RXD_ERR_SEQ |		       \
+    E1000_RXD_ERR_CXE |		       \
     E1000_RXD_ERR_RXE)
 
 /* Transmit Descriptor */
@@ -430,8 +430,8 @@ struct e1000_data_desc {
 };
 
 /* Filters */
-#define E1000_NUM_UNICAST          16	/* Unicast filter entries */
-#define E1000_MC_TBL_SIZE          128	/* Multicast Filter Table (4096 bits) */
+#define E1000_NUM_UNICAST	   16	/* Unicast filter entries */
+#define E1000_MC_TBL_SIZE	   128	/* Multicast Filter Table (4096 bits) */
 #define E1000_VLAN_FILTER_TBL_SIZE 128	/* VLAN Filter Table (4096 bits) */
 
 /* Receive Address Register */
@@ -451,8 +451,8 @@ struct e1000_ipv4_at_entry {
 
 /* Four wakeup IP addresses are supported */
 #define E1000_WAKEUP_IP_ADDRESS_COUNT_MAX 4
-#define E1000_IP4AT_SIZE                  E1000_WAKEUP_IP_ADDRESS_COUNT_MAX
-#define E1000_IP6AT_SIZE                  1
+#define E1000_IP4AT_SIZE		  E1000_WAKEUP_IP_ADDRESS_COUNT_MAX
+#define E1000_IP6AT_SIZE		  1
 
 /* IPv6 Address Table Entry */
 struct e1000_ipv6_at_entry {
@@ -481,7 +481,7 @@ struct e1000_ffvt_entry {
 #define E1000_FLEXIBLE_FILTER_COUNT_MAX 4
 
 /* Each Flexible Filter is at most 128 (0x80) bytes in length */
-#define E1000_FLEXIBLE_FILTER_SIZE_MAX  128
+#define E1000_FLEXIBLE_FILTER_SIZE_MAX	128
 
 #define E1000_FFLT_SIZE E1000_FLEXIBLE_FILTER_COUNT_MAX
 #define E1000_FFMT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
@@ -636,7 +636,7 @@ struct e1000_ffvt_entry {
 #define E1000_82542_FCAH     E1000_FCAH
 #define E1000_82542_FCT      E1000_FCT
 #define E1000_82542_VET      E1000_VET
-#define E1000_82542_RA       0x00040
+#define E1000_82542_RA	     0x00040
 #define E1000_82542_ICR      E1000_ICR
 #define E1000_82542_ITR      E1000_ITR
 #define E1000_82542_ICS      E1000_ICS
@@ -685,7 +685,7 @@ struct e1000_ffvt_entry {
 #define E1000_82542_MCC      E1000_MCC
 #define E1000_82542_LATECOL  E1000_LATECOL
 #define E1000_82542_COLC     E1000_COLC
-#define E1000_82542_DC       E1000_DC
+#define E1000_82542_DC	     E1000_DC
 #define E1000_82542_TNCRS    E1000_TNCRS
 #define E1000_82542_SEC      E1000_SEC
 #define E1000_82542_CEXTERR  E1000_CEXTERR
@@ -886,14 +886,14 @@ struct e1000_hw {
 
 /* Register Bit Masks */
 /* Device Control */
-#define E1000_CTRL_FD       0x00000001	/* Full duplex.0=half; 1=full */
-#define E1000_CTRL_BEM      0x00000002	/* Endian Mode.0=little,1=big */
+#define E1000_CTRL_FD	    0x00000001	/* Full duplex.0=half; 1=full */
+#define E1000_CTRL_BEM	    0x00000002	/* Endian Mode.0=little,1=big */
 #define E1000_CTRL_PRIOR    0x00000004	/* Priority on PCI. 0=rx,1=fair */
 #define E1000_CTRL_LRST     0x00000008	/* Link reset. 0=normal,1=reset */
-#define E1000_CTRL_TME      0x00000010	/* Test mode. 0=normal,1=test */
-#define E1000_CTRL_SLE      0x00000020	/* Serial Link on 0=dis,1=en */
+#define E1000_CTRL_TME	    0x00000010	/* Test mode. 0=normal,1=test */
+#define E1000_CTRL_SLE	    0x00000020	/* Serial Link on 0=dis,1=en */
 #define E1000_CTRL_ASDE     0x00000020	/* Auto-speed detect enable */
-#define E1000_CTRL_SLU      0x00000040	/* Set link up (Force Link) */
+#define E1000_CTRL_SLU	    0x00000040	/* Set link up (Force Link) */
 #define E1000_CTRL_ILOS     0x00000080	/* Invert Loss-Of Signal */
 #define E1000_CTRL_SPD_SEL  0x00000300	/* Speed Select Mask */
 #define E1000_CTRL_SPD_10   0x00000000	/* Force 10Mb */
@@ -910,30 +910,30 @@ struct e1000_hw {
 #define E1000_CTRL_SWDPIO1  0x00800000	/* SWDPIN 1 input or output */
 #define E1000_CTRL_SWDPIO2  0x01000000	/* SWDPIN 2 input or output */
 #define E1000_CTRL_SWDPIO3  0x02000000	/* SWDPIN 3 input or output */
-#define E1000_CTRL_RST      0x04000000	/* Global reset */
+#define E1000_CTRL_RST	    0x04000000	/* Global reset */
 #define E1000_CTRL_RFCE     0x08000000	/* Receive Flow Control enable */
 #define E1000_CTRL_TFCE     0x10000000	/* Transmit flow control enable */
-#define E1000_CTRL_RTE      0x20000000	/* Routing tag enable */
-#define E1000_CTRL_VME      0x40000000	/* IEEE VLAN mode enable */
+#define E1000_CTRL_RTE	    0x20000000	/* Routing tag enable */
+#define E1000_CTRL_VME	    0x40000000	/* IEEE VLAN mode enable */
 #define E1000_CTRL_PHY_RST  0x80000000	/* PHY Reset */
 
 /* Device Status */
-#define E1000_STATUS_FD         0x00000001	/* Full duplex.0=half,1=full */
-#define E1000_STATUS_LU         0x00000002	/* Link up.0=no,1=link */
-#define E1000_STATUS_FUNC_MASK  0x0000000C	/* PCI Function Mask */
-#define E1000_STATUS_FUNC_0     0x00000000	/* Function 0 */
-#define E1000_STATUS_FUNC_1     0x00000004	/* Function 1 */
-#define E1000_STATUS_TXOFF      0x00000010	/* transmission paused */
-#define E1000_STATUS_TBIMODE    0x00000020	/* TBI mode */
+#define E1000_STATUS_FD		0x00000001	/* Full duplex.0=half,1=full */
+#define E1000_STATUS_LU		0x00000002	/* Link up.0=no,1=link */
+#define E1000_STATUS_FUNC_MASK	0x0000000C	/* PCI Function Mask */
+#define E1000_STATUS_FUNC_0	0x00000000	/* Function 0 */
+#define E1000_STATUS_FUNC_1	0x00000004	/* Function 1 */
+#define E1000_STATUS_TXOFF	0x00000010	/* transmission paused */
+#define E1000_STATUS_TBIMODE	0x00000020	/* TBI mode */
 #define E1000_STATUS_SPEED_MASK 0x000000C0
-#define E1000_STATUS_SPEED_10   0x00000000	/* Speed 10Mb/s */
-#define E1000_STATUS_SPEED_100  0x00000040	/* Speed 100Mb/s */
+#define E1000_STATUS_SPEED_10	0x00000000	/* Speed 10Mb/s */
+#define E1000_STATUS_SPEED_100	0x00000040	/* Speed 100Mb/s */
 #define E1000_STATUS_SPEED_1000 0x00000080	/* Speed 1000Mb/s */
-#define E1000_STATUS_ASDV       0x00000300	/* Auto speed detect value */
-#define E1000_STATUS_MTXCKOK    0x00000400	/* MTX clock running OK */
-#define E1000_STATUS_PCI66      0x00000800	/* In 66Mhz slot */
-#define E1000_STATUS_BUS64      0x00001000	/* In 64 bit slot */
-#define E1000_STATUS_PCIX_MODE  0x00002000	/* PCI-X mode */
+#define E1000_STATUS_ASDV	0x00000300	/* Auto speed detect value */
+#define E1000_STATUS_MTXCKOK	0x00000400	/* MTX clock running OK */
+#define E1000_STATUS_PCI66	0x00000800	/* In 66Mhz slot */
+#define E1000_STATUS_BUS64	0x00001000	/* In 64 bit slot */
+#define E1000_STATUS_PCIX_MODE	0x00002000	/* PCI-X mode */
 #define E1000_STATUS_PCIX_SPEED 0x0000C000	/* PCI-X bus speed */
 
 /* Constants used to intrepret the masked PCI-X bus speed. */
@@ -942,17 +942,17 @@ struct e1000_hw {
 #define E1000_STATUS_PCIX_SPEED_133 0x00008000	/* PCI-X bus speed 100-133 MHz */
 
 /* EEPROM/Flash Control */
-#define E1000_EECD_SK        0x00000001	/* EEPROM Clock */
-#define E1000_EECD_CS        0x00000002	/* EEPROM Chip Select */
-#define E1000_EECD_DI        0x00000004	/* EEPROM Data In */
-#define E1000_EECD_DO        0x00000008	/* EEPROM Data Out */
+#define E1000_EECD_SK	     0x00000001	/* EEPROM Clock */
+#define E1000_EECD_CS	     0x00000002	/* EEPROM Chip Select */
+#define E1000_EECD_DI	     0x00000004	/* EEPROM Data In */
+#define E1000_EECD_DO	     0x00000008	/* EEPROM Data Out */
 #define E1000_EECD_FWE_MASK  0x00000030
 #define E1000_EECD_FWE_DIS   0x00000010	/* Disable FLASH writes */
 #define E1000_EECD_FWE_EN    0x00000020	/* Enable FLASH writes */
 #define E1000_EECD_FWE_SHIFT 4
 #define E1000_EECD_SIZE      0x00000200	/* EEPROM Size (0=64 word 1=256 word) */
-#define E1000_EECD_REQ       0x00000040	/* EEPROM Access Request */
-#define E1000_EECD_GNT       0x00000080	/* EEPROM Access Grant */
+#define E1000_EECD_REQ	     0x00000040	/* EEPROM Access Request */
+#define E1000_EECD_GNT	     0x00000080	/* EEPROM Access Grant */
 #define E1000_EECD_PRES      0x00000100	/* EEPROM Present */
 
 /* EEPROM Read */
@@ -964,27 +964,27 @@ struct e1000_hw {
 #define E1000_EERD_DATA_MASK  0xFFFF0000	/* Read Data */
 
 /* Extended Device Control */
-#define E1000_CTRL_EXT_GPI0_EN   0x00000001	/* Maps SDP4 to GPI0 */
-#define E1000_CTRL_EXT_GPI1_EN   0x00000002	/* Maps SDP5 to GPI1 */
+#define E1000_CTRL_EXT_GPI0_EN	 0x00000001	/* Maps SDP4 to GPI0 */
+#define E1000_CTRL_EXT_GPI1_EN	 0x00000002	/* Maps SDP5 to GPI1 */
 #define E1000_CTRL_EXT_PHYINT_EN E1000_CTRL_EXT_GPI1_EN
-#define E1000_CTRL_EXT_GPI2_EN   0x00000004	/* Maps SDP6 to GPI2 */
-#define E1000_CTRL_EXT_GPI3_EN   0x00000008	/* Maps SDP7 to GPI3 */
+#define E1000_CTRL_EXT_GPI2_EN	 0x00000004	/* Maps SDP6 to GPI2 */
+#define E1000_CTRL_EXT_GPI3_EN	 0x00000008	/* Maps SDP7 to GPI3 */
 #define E1000_CTRL_EXT_SDP4_DATA 0x00000010	/* Value of SW Defineable Pin 4 */
 #define E1000_CTRL_EXT_SDP5_DATA 0x00000020	/* Value of SW Defineable Pin 5 */
-#define E1000_CTRL_EXT_PHY_INT   E1000_CTRL_EXT_SDP5_DATA
+#define E1000_CTRL_EXT_PHY_INT	 E1000_CTRL_EXT_SDP5_DATA
 #define E1000_CTRL_EXT_SDP6_DATA 0x00000040	/* Value of SW Defineable Pin 6 */
-#define E1000_CTRL_EXT_SWDPIN6 	 0x00000040	/* SWDPIN 6 value */
+#define E1000_CTRL_EXT_SWDPIN6	 0x00000040	/* SWDPIN 6 value */
 #define E1000_CTRL_EXT_SDP7_DATA 0x00000080	/* Value of SW Defineable Pin 7 */
-#define E1000_CTRL_EXT_SWDPIN7 	 0x00000080	/* SWDPIN 7 value */
+#define E1000_CTRL_EXT_SWDPIN7	 0x00000080	/* SWDPIN 7 value */
 #define E1000_CTRL_EXT_SDP4_DIR  0x00000100	/* Direction of SDP4 0=in 1=out */
 #define E1000_CTRL_EXT_SDP5_DIR  0x00000200	/* Direction of SDP5 0=in 1=out */
 #define E1000_CTRL_EXT_SDP6_DIR  0x00000400	/* Direction of SDP6 0=in 1=out */
-#define E1000_CTRL_EXT_SWDPIO6   0x00000400	/* SWDPIN 6 Input or output */
+#define E1000_CTRL_EXT_SWDPIO6	 0x00000400	/* SWDPIN 6 Input or output */
 #define E1000_CTRL_EXT_SDP7_DIR  0x00000800	/* Direction of SDP7 0=in 1=out */
-#define E1000_CTRL_EXT_SWDPIO7   0x00000800	/* SWDPIN 7 Input or output */
-#define E1000_CTRL_EXT_ASDCHK    0x00001000	/* Initiate an ASD sequence */
-#define E1000_CTRL_EXT_EE_RST    0x00002000	/* Reinitialize from EEPROM */
-#define E1000_CTRL_EXT_IPS       0x00004000	/* Invert Power State */
+#define E1000_CTRL_EXT_SWDPIO7	 0x00000800	/* SWDPIN 7 Input or output */
+#define E1000_CTRL_EXT_ASDCHK	 0x00001000	/* Initiate an ASD sequence */
+#define E1000_CTRL_EXT_EE_RST	 0x00002000	/* Reinitialize from EEPROM */
+#define E1000_CTRL_EXT_IPS	 0x00004000	/* Invert Power State */
 #define E1000_CTRL_EXT_SPD_BYPS  0x00008000	/* Speed Select Bypass */
 #define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000
 #define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000
@@ -1010,152 +1010,152 @@ struct e1000_hw {
 /* LED Control */
 #define E1000_LEDCTL_LED0_MODE_MASK  0x0000000F
 #define E1000_LEDCTL_LED0_MODE_SHIFT 0
-#define E1000_LEDCTL_LED0_IVRT       0x00000040
+#define E1000_LEDCTL_LED0_IVRT	     0x00000040
 #define E1000_LEDCTL_LED0_BLINK      0x00000080
 #define E1000_LEDCTL_LED1_MODE_MASK  0x00000F00
 #define E1000_LEDCTL_LED1_MODE_SHIFT 8
-#define E1000_LEDCTL_LED1_IVRT       0x00004000
+#define E1000_LEDCTL_LED1_IVRT	     0x00004000
 #define E1000_LEDCTL_LED1_BLINK      0x00008000
 #define E1000_LEDCTL_LED2_MODE_MASK  0x000F0000
 #define E1000_LEDCTL_LED2_MODE_SHIFT 16
-#define E1000_LEDCTL_LED2_IVRT       0x00400000
+#define E1000_LEDCTL_LED2_IVRT	     0x00400000
 #define E1000_LEDCTL_LED2_BLINK      0x00800000
 #define E1000_LEDCTL_LED3_MODE_MASK  0x0F000000
 #define E1000_LEDCTL_LED3_MODE_SHIFT 24
-#define E1000_LEDCTL_LED3_IVRT       0x40000000
+#define E1000_LEDCTL_LED3_IVRT	     0x40000000
 #define E1000_LEDCTL_LED3_BLINK      0x80000000
 
-#define E1000_LEDCTL_MODE_LINK_10_1000  0x0
+#define E1000_LEDCTL_MODE_LINK_10_1000	0x0
 #define E1000_LEDCTL_MODE_LINK_100_1000 0x1
-#define E1000_LEDCTL_MODE_LINK_UP       0x2
-#define E1000_LEDCTL_MODE_ACTIVITY      0x3
+#define E1000_LEDCTL_MODE_LINK_UP	0x2
+#define E1000_LEDCTL_MODE_ACTIVITY	0x3
 #define E1000_LEDCTL_MODE_LINK_ACTIVITY 0x4
-#define E1000_LEDCTL_MODE_LINK_10       0x5
-#define E1000_LEDCTL_MODE_LINK_100      0x6
-#define E1000_LEDCTL_MODE_LINK_1000     0x7
-#define E1000_LEDCTL_MODE_PCIX_MODE     0x8
-#define E1000_LEDCTL_MODE_FULL_DUPLEX   0x9
-#define E1000_LEDCTL_MODE_COLLISION     0xA
-#define E1000_LEDCTL_MODE_BUS_SPEED     0xB
-#define E1000_LEDCTL_MODE_BUS_SIZE      0xC
-#define E1000_LEDCTL_MODE_PAUSED        0xD
-#define E1000_LEDCTL_MODE_LED_ON        0xE
-#define E1000_LEDCTL_MODE_LED_OFF       0xF
+#define E1000_LEDCTL_MODE_LINK_10	0x5
+#define E1000_LEDCTL_MODE_LINK_100	0x6
+#define E1000_LEDCTL_MODE_LINK_1000	0x7
+#define E1000_LEDCTL_MODE_PCIX_MODE	0x8
+#define E1000_LEDCTL_MODE_FULL_DUPLEX	0x9
+#define E1000_LEDCTL_MODE_COLLISION	0xA
+#define E1000_LEDCTL_MODE_BUS_SPEED	0xB
+#define E1000_LEDCTL_MODE_BUS_SIZE	0xC
+#define E1000_LEDCTL_MODE_PAUSED	0xD
+#define E1000_LEDCTL_MODE_LED_ON	0xE
+#define E1000_LEDCTL_MODE_LED_OFF	0xF
 
 /* Receive Address */
 #define E1000_RAH_AV  0x80000000	/* Receive descriptor valid */
 
 /* Interrupt Cause Read */
-#define E1000_ICR_TXDW    0x00000001	/* Transmit desc written back */
-#define E1000_ICR_TXQE    0x00000002	/* Transmit Queue empty */
-#define E1000_ICR_LSC     0x00000004	/* Link Status Change */
+#define E1000_ICR_TXDW	  0x00000001	/* Transmit desc written back */
+#define E1000_ICR_TXQE	  0x00000002	/* Transmit Queue empty */
+#define E1000_ICR_LSC	  0x00000004	/* Link Status Change */
 #define E1000_ICR_RXSEQ   0x00000008	/* rx sequence error */
 #define E1000_ICR_RXDMT0  0x00000010	/* rx desc min. threshold (0) */
-#define E1000_ICR_RXO     0x00000040	/* rx overrun */
-#define E1000_ICR_RXT0    0x00000080	/* rx timer intr (ring 0) */
-#define E1000_ICR_MDAC    0x00000200	/* MDIO access complete */
+#define E1000_ICR_RXO	  0x00000040	/* rx overrun */
+#define E1000_ICR_RXT0	  0x00000080	/* rx timer intr (ring 0) */
+#define E1000_ICR_MDAC	  0x00000200	/* MDIO access complete */
 #define E1000_ICR_RXCFG   0x00000400	/* RX /c/ ordered set */
 #define E1000_ICR_GPI_EN0 0x00000800	/* GP Int 0 */
 #define E1000_ICR_GPI_EN1 0x00001000	/* GP Int 1 */
 #define E1000_ICR_GPI_EN2 0x00002000	/* GP Int 2 */
 #define E1000_ICR_GPI_EN3 0x00004000	/* GP Int 3 */
 #define E1000_ICR_TXD_LOW 0x00008000
-#define E1000_ICR_SRPD    0x00010000
+#define E1000_ICR_SRPD	  0x00010000
 
 /* Interrupt Cause Set */
-#define E1000_ICS_TXDW    E1000_ICR_TXDW	/* Transmit desc written back */
-#define E1000_ICS_TXQE    E1000_ICR_TXQE	/* Transmit Queue empty */
-#define E1000_ICS_LSC     E1000_ICR_LSC	/* Link Status Change */
+#define E1000_ICS_TXDW	  E1000_ICR_TXDW	/* Transmit desc written back */
+#define E1000_ICS_TXQE	  E1000_ICR_TXQE	/* Transmit Queue empty */
+#define E1000_ICS_LSC	  E1000_ICR_LSC	/* Link Status Change */
 #define E1000_ICS_RXSEQ   E1000_ICR_RXSEQ	/* rx sequence error */
 #define E1000_ICS_RXDMT0  E1000_ICR_RXDMT0	/* rx desc min. threshold */
-#define E1000_ICS_RXO     E1000_ICR_RXO	/* rx overrun */
-#define E1000_ICS_RXT0    E1000_ICR_RXT0	/* rx timer intr */
-#define E1000_ICS_MDAC    E1000_ICR_MDAC	/* MDIO access complete */
+#define E1000_ICS_RXO	  E1000_ICR_RXO	/* rx overrun */
+#define E1000_ICS_RXT0	  E1000_ICR_RXT0	/* rx timer intr */
+#define E1000_ICS_MDAC	  E1000_ICR_MDAC	/* MDIO access complete */
 #define E1000_ICS_RXCFG   E1000_ICR_RXCFG	/* RX /c/ ordered set */
 #define E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0	/* GP Int 0 */
 #define E1000_ICS_GPI_EN1 E1000_ICR_GPI_EN1	/* GP Int 1 */
 #define E1000_ICS_GPI_EN2 E1000_ICR_GPI_EN2	/* GP Int 2 */
 #define E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3	/* GP Int 3 */
 #define E1000_ICS_TXD_LOW E1000_ICR_TXD_LOW
-#define E1000_ICS_SRPD    E1000_ICR_SRPD
+#define E1000_ICS_SRPD	  E1000_ICR_SRPD
 
 /* Interrupt Mask Set */
-#define E1000_IMS_TXDW    E1000_ICR_TXDW	/* Transmit desc written back */
-#define E1000_IMS_TXQE    E1000_ICR_TXQE	/* Transmit Queue empty */
-#define E1000_IMS_LSC     E1000_ICR_LSC	/* Link Status Change */
+#define E1000_IMS_TXDW	  E1000_ICR_TXDW	/* Transmit desc written back */
+#define E1000_IMS_TXQE	  E1000_ICR_TXQE	/* Transmit Queue empty */
+#define E1000_IMS_LSC	  E1000_ICR_LSC	/* Link Status Change */
 #define E1000_IMS_RXSEQ   E1000_ICR_RXSEQ	/* rx sequence error */
 #define E1000_IMS_RXDMT0  E1000_ICR_RXDMT0	/* rx desc min. threshold */
-#define E1000_IMS_RXO     E1000_ICR_RXO	/* rx overrun */
-#define E1000_IMS_RXT0    E1000_ICR_RXT0	/* rx timer intr */
-#define E1000_IMS_MDAC    E1000_ICR_MDAC	/* MDIO access complete */
+#define E1000_IMS_RXO	  E1000_ICR_RXO	/* rx overrun */
+#define E1000_IMS_RXT0	  E1000_ICR_RXT0	/* rx timer intr */
+#define E1000_IMS_MDAC	  E1000_ICR_MDAC	/* MDIO access complete */
 #define E1000_IMS_RXCFG   E1000_ICR_RXCFG	/* RX /c/ ordered set */
 #define E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0	/* GP Int 0 */
 #define E1000_IMS_GPI_EN1 E1000_ICR_GPI_EN1	/* GP Int 1 */
 #define E1000_IMS_GPI_EN2 E1000_ICR_GPI_EN2	/* GP Int 2 */
 #define E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3	/* GP Int 3 */
 #define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW
-#define E1000_IMS_SRPD    E1000_ICR_SRPD
+#define E1000_IMS_SRPD	  E1000_ICR_SRPD
 
 /* Interrupt Mask Clear */
-#define E1000_IMC_TXDW    E1000_ICR_TXDW	/* Transmit desc written back */
-#define E1000_IMC_TXQE    E1000_ICR_TXQE	/* Transmit Queue empty */
-#define E1000_IMC_LSC     E1000_ICR_LSC	/* Link Status Change */
+#define E1000_IMC_TXDW	  E1000_ICR_TXDW	/* Transmit desc written back */
+#define E1000_IMC_TXQE	  E1000_ICR_TXQE	/* Transmit Queue empty */
+#define E1000_IMC_LSC	  E1000_ICR_LSC	/* Link Status Change */
 #define E1000_IMC_RXSEQ   E1000_ICR_RXSEQ	/* rx sequence error */
 #define E1000_IMC_RXDMT0  E1000_ICR_RXDMT0	/* rx desc min. threshold */
-#define E1000_IMC_RXO     E1000_ICR_RXO	/* rx overrun */
-#define E1000_IMC_RXT0    E1000_ICR_RXT0	/* rx timer intr */
-#define E1000_IMC_MDAC    E1000_ICR_MDAC	/* MDIO access complete */
+#define E1000_IMC_RXO	  E1000_ICR_RXO	/* rx overrun */
+#define E1000_IMC_RXT0	  E1000_ICR_RXT0	/* rx timer intr */
+#define E1000_IMC_MDAC	  E1000_ICR_MDAC	/* MDIO access complete */
 #define E1000_IMC_RXCFG   E1000_ICR_RXCFG	/* RX /c/ ordered set */
 #define E1000_IMC_GPI_EN0 E1000_ICR_GPI_EN0	/* GP Int 0 */
 #define E1000_IMC_GPI_EN1 E1000_ICR_GPI_EN1	/* GP Int 1 */
 #define E1000_IMC_GPI_EN2 E1000_ICR_GPI_EN2	/* GP Int 2 */
 #define E1000_IMC_GPI_EN3 E1000_ICR_GPI_EN3	/* GP Int 3 */
 #define E1000_IMC_TXD_LOW E1000_ICR_TXD_LOW
-#define E1000_IMC_SRPD    E1000_ICR_SRPD
+#define E1000_IMC_SRPD	  E1000_ICR_SRPD
 
 /* Receive Control */
-#define E1000_RCTL_RST          0x00000001	/* Software reset */
-#define E1000_RCTL_EN           0x00000002	/* enable */
-#define E1000_RCTL_SBP          0x00000004	/* store bad packet */
-#define E1000_RCTL_UPE          0x00000008	/* unicast promiscuous enable */
-#define E1000_RCTL_MPE          0x00000010	/* multicast promiscuous enab */
-#define E1000_RCTL_LPE          0x00000020	/* long packet enable */
-#define E1000_RCTL_LBM_NO       0x00000000	/* no loopback mode */
-#define E1000_RCTL_LBM_MAC      0x00000040	/* MAC loopback mode */
-#define E1000_RCTL_LBM_SLP      0x00000080	/* serial link loopback mode */
-#define E1000_RCTL_LBM_TCVR     0x000000C0	/* tcvr loopback mode */
-#define E1000_RCTL_RDMTS_HALF   0x00000000	/* rx desc min threshold size */
-#define E1000_RCTL_RDMTS_QUAT   0x00000100	/* rx desc min threshold size */
-#define E1000_RCTL_RDMTS_EIGTH  0x00000200	/* rx desc min threshold size */
-#define E1000_RCTL_MO_SHIFT     12	/* multicast offset shift */
-#define E1000_RCTL_MO_0         0x00000000	/* multicast offset 11:0 */
-#define E1000_RCTL_MO_1         0x00001000	/* multicast offset 12:1 */
-#define E1000_RCTL_MO_2         0x00002000	/* multicast offset 13:2 */
-#define E1000_RCTL_MO_3         0x00003000	/* multicast offset 15:4 */
-#define E1000_RCTL_MDR          0x00004000	/* multicast desc ring 0 */
-#define E1000_RCTL_BAM          0x00008000	/* broadcast enable */
+#define E1000_RCTL_RST		0x00000001	/* Software reset */
+#define E1000_RCTL_EN		0x00000002	/* enable */
+#define E1000_RCTL_SBP		0x00000004	/* store bad packet */
+#define E1000_RCTL_UPE		0x00000008	/* unicast promiscuous enable */
+#define E1000_RCTL_MPE		0x00000010	/* multicast promiscuous enab */
+#define E1000_RCTL_LPE		0x00000020	/* long packet enable */
+#define E1000_RCTL_LBM_NO	0x00000000	/* no loopback mode */
+#define E1000_RCTL_LBM_MAC	0x00000040	/* MAC loopback mode */
+#define E1000_RCTL_LBM_SLP	0x00000080	/* serial link loopback mode */
+#define E1000_RCTL_LBM_TCVR	0x000000C0	/* tcvr loopback mode */
+#define E1000_RCTL_RDMTS_HALF	0x00000000	/* rx desc min threshold size */
+#define E1000_RCTL_RDMTS_QUAT	0x00000100	/* rx desc min threshold size */
+#define E1000_RCTL_RDMTS_EIGTH	0x00000200	/* rx desc min threshold size */
+#define E1000_RCTL_MO_SHIFT	12	/* multicast offset shift */
+#define E1000_RCTL_MO_0		0x00000000	/* multicast offset 11:0 */
+#define E1000_RCTL_MO_1		0x00001000	/* multicast offset 12:1 */
+#define E1000_RCTL_MO_2		0x00002000	/* multicast offset 13:2 */
+#define E1000_RCTL_MO_3		0x00003000	/* multicast offset 15:4 */
+#define E1000_RCTL_MDR		0x00004000	/* multicast desc ring 0 */
+#define E1000_RCTL_BAM		0x00008000	/* broadcast enable */
 /* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */
-#define E1000_RCTL_SZ_2048      0x00000000	/* rx buffer size 2048 */
-#define E1000_RCTL_SZ_1024      0x00010000	/* rx buffer size 1024 */
-#define E1000_RCTL_SZ_512       0x00020000	/* rx buffer size 512 */
-#define E1000_RCTL_SZ_256       0x00030000	/* rx buffer size 256 */
+#define E1000_RCTL_SZ_2048	0x00000000	/* rx buffer size 2048 */
+#define E1000_RCTL_SZ_1024	0x00010000	/* rx buffer size 1024 */
+#define E1000_RCTL_SZ_512	0x00020000	/* rx buffer size 512 */
+#define E1000_RCTL_SZ_256	0x00030000	/* rx buffer size 256 */
 /* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */
-#define E1000_RCTL_SZ_16384     0x00010000	/* rx buffer size 16384 */
-#define E1000_RCTL_SZ_8192      0x00020000	/* rx buffer size 8192 */
-#define E1000_RCTL_SZ_4096      0x00030000	/* rx buffer size 4096 */
-#define E1000_RCTL_VFE          0x00040000	/* vlan filter enable */
-#define E1000_RCTL_CFIEN        0x00080000	/* canonical form enable */
-#define E1000_RCTL_CFI          0x00100000	/* canonical form indicator */
-#define E1000_RCTL_DPF          0x00400000	/* discard pause frames */
-#define E1000_RCTL_PMCF         0x00800000	/* pass MAC control frames */
-#define E1000_RCTL_BSEX         0x02000000	/* Buffer size extension */
+#define E1000_RCTL_SZ_16384	0x00010000	/* rx buffer size 16384 */
+#define E1000_RCTL_SZ_8192	0x00020000	/* rx buffer size 8192 */
+#define E1000_RCTL_SZ_4096	0x00030000	/* rx buffer size 4096 */
+#define E1000_RCTL_VFE		0x00040000	/* vlan filter enable */
+#define E1000_RCTL_CFIEN	0x00080000	/* canonical form enable */
+#define E1000_RCTL_CFI		0x00100000	/* canonical form indicator */
+#define E1000_RCTL_DPF		0x00400000	/* discard pause frames */
+#define E1000_RCTL_PMCF		0x00800000	/* pass MAC control frames */
+#define E1000_RCTL_BSEX		0x02000000	/* Buffer size extension */
 
 /* Receive Descriptor */
 #define E1000_RDT_DELAY 0x0000ffff	/* Delay timer (1=1024us) */
-#define E1000_RDT_FPDB  0x80000000	/* Flush descriptor block */
+#define E1000_RDT_FPDB	0x80000000	/* Flush descriptor block */
 #define E1000_RDLEN_LEN 0x0007ff80	/* descriptor length */
-#define E1000_RDH_RDH   0x0000ffff	/* receive descriptor head */
-#define E1000_RDT_RDT   0x0000ffff	/* receive descriptor tail */
+#define E1000_RDH_RDH	0x0000ffff	/* receive descriptor head */
+#define E1000_RDT_RDT	0x0000ffff	/* receive descriptor tail */
 
 /* Flow Control */
 #define E1000_FCRTH_RTH  0x0000FFF8	/* Mask Bits[15:3] for RTH */
@@ -1178,35 +1178,35 @@ struct e1000_hw {
 #define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000	/* GRAN=1, WTHRESH=1 */
 
 /* Transmit Configuration Word */
-#define E1000_TXCW_FD         0x00000020	/* TXCW full duplex */
-#define E1000_TXCW_HD         0x00000040	/* TXCW half duplex */
+#define E1000_TXCW_FD	      0x00000020	/* TXCW full duplex */
+#define E1000_TXCW_HD	      0x00000040	/* TXCW half duplex */
 #define E1000_TXCW_PAUSE      0x00000080	/* TXCW sym pause request */
 #define E1000_TXCW_ASM_DIR    0x00000100	/* TXCW astm pause direction */
 #define E1000_TXCW_PAUSE_MASK 0x00000180	/* TXCW pause request mask */
-#define E1000_TXCW_RF         0x00003000	/* TXCW remote fault */
-#define E1000_TXCW_NP         0x00008000	/* TXCW next page */
-#define E1000_TXCW_CW         0x0000ffff	/* TxConfigWord mask */
-#define E1000_TXCW_TXC        0x40000000	/* Transmit Config control */
-#define E1000_TXCW_ANE        0x80000000	/* Auto-neg enable */
+#define E1000_TXCW_RF	      0x00003000	/* TXCW remote fault */
+#define E1000_TXCW_NP	      0x00008000	/* TXCW next page */
+#define E1000_TXCW_CW	      0x0000ffff	/* TxConfigWord mask */
+#define E1000_TXCW_TXC	      0x40000000	/* Transmit Config control */
+#define E1000_TXCW_ANE	      0x80000000	/* Auto-neg enable */
 
 /* Receive Configuration Word */
-#define E1000_RXCW_CW    0x0000ffff	/* RxConfigWord mask */
-#define E1000_RXCW_NC    0x04000000	/* Receive config no carrier */
-#define E1000_RXCW_IV    0x08000000	/* Receive config invalid */
-#define E1000_RXCW_CC    0x10000000	/* Receive config change */
-#define E1000_RXCW_C     0x20000000	/* Receive config */
+#define E1000_RXCW_CW	 0x0000ffff	/* RxConfigWord mask */
+#define E1000_RXCW_NC	 0x04000000	/* Receive config no carrier */
+#define E1000_RXCW_IV	 0x08000000	/* Receive config invalid */
+#define E1000_RXCW_CC	 0x10000000	/* Receive config change */
+#define E1000_RXCW_C	 0x20000000	/* Receive config */
 #define E1000_RXCW_SYNCH 0x40000000	/* Receive config synch */
-#define E1000_RXCW_ANC   0x80000000	/* Auto-neg complete */
+#define E1000_RXCW_ANC	 0x80000000	/* Auto-neg complete */
 
 /* Transmit Control */
-#define E1000_TCTL_RST    0x00000001	/* software reset */
-#define E1000_TCTL_EN     0x00000002	/* enable tx */
-#define E1000_TCTL_BCE    0x00000004	/* busy check enable */
-#define E1000_TCTL_PSP    0x00000008	/* pad short packets */
-#define E1000_TCTL_CT     0x00000ff0	/* collision threshold */
+#define E1000_TCTL_RST	  0x00000001	/* software reset */
+#define E1000_TCTL_EN	  0x00000002	/* enable tx */
+#define E1000_TCTL_BCE	  0x00000004	/* busy check enable */
+#define E1000_TCTL_PSP	  0x00000008	/* pad short packets */
+#define E1000_TCTL_CT	  0x00000ff0	/* collision threshold */
 #define E1000_TCTL_COLD   0x003ff000	/* collision distance */
 #define E1000_TCTL_SWXOFF 0x00400000	/* SW Xoff transmission */
-#define E1000_TCTL_PBE    0x00800000	/* Packet Burst Enable */
+#define E1000_TCTL_PBE	  0x00800000	/* Packet Burst Enable */
 #define E1000_TCTL_RTLC   0x01000000	/* Re-transmit on late collision */
 #define E1000_TCTL_NRTU   0x02000000	/* No Re-transmit on underrun */
 
@@ -1218,18 +1218,18 @@ struct e1000_hw {
 
 /* Definitions for power management and wakeup registers */
 /* Wake Up Control */
-#define E1000_WUC_APME       0x00000001	/* APM Enable */
+#define E1000_WUC_APME	     0x00000001	/* APM Enable */
 #define E1000_WUC_PME_EN     0x00000002	/* PME Enable */
 #define E1000_WUC_PME_STATUS 0x00000004	/* PME Status */
 #define E1000_WUC_APMPME     0x00000008	/* Assert PME on APM Wakeup */
 
 /* Wake Up Filter Control */
 #define E1000_WUFC_LNKC 0x00000001	/* Link Status Change Wakeup Enable */
-#define E1000_WUFC_MAG  0x00000002	/* Magic Packet Wakeup Enable */
-#define E1000_WUFC_EX   0x00000004	/* Directed Exact Wakeup Enable */
-#define E1000_WUFC_MC   0x00000008	/* Directed Multicast Wakeup Enable */
-#define E1000_WUFC_BC   0x00000010	/* Broadcast Wakeup Enable */
-#define E1000_WUFC_ARP  0x00000020	/* ARP Request Packet Wakeup Enable */
+#define E1000_WUFC_MAG	0x00000002	/* Magic Packet Wakeup Enable */
+#define E1000_WUFC_EX	0x00000004	/* Directed Exact Wakeup Enable */
+#define E1000_WUFC_MC	0x00000008	/* Directed Multicast Wakeup Enable */
+#define E1000_WUFC_BC	0x00000010	/* Broadcast Wakeup Enable */
+#define E1000_WUFC_ARP	0x00000020	/* ARP Request Packet Wakeup Enable */
 #define E1000_WUFC_IPV4 0x00000040	/* Directed IPv4 Packet Wakeup Enable */
 #define E1000_WUFC_IPV6 0x00000080	/* Directed IPv6 Packet Wakeup Enable */
 #define E1000_WUFC_FLX0 0x00010000	/* Flexible Filter 0 Enable */
@@ -1256,26 +1256,26 @@ struct e1000_hw {
 #define E1000_WUS_FLX_FILTERS 0x000F0000	/* Mask for the 4 flexible filters */
 
 /* Management Control */
-#define E1000_MANC_SMBUS_EN      0x00000001	/* SMBus Enabled - RO */
-#define E1000_MANC_ASF_EN        0x00000002	/* ASF Enabled - RO */
-#define E1000_MANC_R_ON_FORCE    0x00000004	/* Reset on Force TCO - RO */
-#define E1000_MANC_RMCP_EN       0x00000100	/* Enable RCMP 026Fh Filtering */
-#define E1000_MANC_0298_EN       0x00000200	/* Enable RCMP 0298h Filtering */
-#define E1000_MANC_IPV4_EN       0x00000400	/* Enable IPv4 */
-#define E1000_MANC_IPV6_EN       0x00000800	/* Enable IPv6 */
-#define E1000_MANC_SNAP_EN       0x00001000	/* Accept LLC/SNAP */
-#define E1000_MANC_ARP_EN        0x00002000	/* Enable ARP Request Filtering */
-#define E1000_MANC_NEIGHBOR_EN   0x00004000	/* Enable Neighbor Discovery
+#define E1000_MANC_SMBUS_EN	 0x00000001	/* SMBus Enabled - RO */
+#define E1000_MANC_ASF_EN	 0x00000002	/* ASF Enabled - RO */
+#define E1000_MANC_R_ON_FORCE	 0x00000004	/* Reset on Force TCO - RO */
+#define E1000_MANC_RMCP_EN	 0x00000100	/* Enable RCMP 026Fh Filtering */
+#define E1000_MANC_0298_EN	 0x00000200	/* Enable RCMP 0298h Filtering */
+#define E1000_MANC_IPV4_EN	 0x00000400	/* Enable IPv4 */
+#define E1000_MANC_IPV6_EN	 0x00000800	/* Enable IPv6 */
+#define E1000_MANC_SNAP_EN	 0x00001000	/* Accept LLC/SNAP */
+#define E1000_MANC_ARP_EN	 0x00002000	/* Enable ARP Request Filtering */
+#define E1000_MANC_NEIGHBOR_EN	 0x00004000	/* Enable Neighbor Discovery
 						 * Filtering */
-#define E1000_MANC_TCO_RESET     0x00010000	/* TCO Reset Occurred */
-#define E1000_MANC_RCV_TCO_EN    0x00020000	/* Receive TCO Packets Enabled */
+#define E1000_MANC_TCO_RESET	 0x00010000	/* TCO Reset Occurred */
+#define E1000_MANC_RCV_TCO_EN	 0x00020000	/* Receive TCO Packets Enabled */
 #define E1000_MANC_REPORT_STATUS 0x00040000	/* Status Reporting Enabled */
-#define E1000_MANC_SMB_REQ       0x01000000	/* SMBus Request */
-#define E1000_MANC_SMB_GNT       0x02000000	/* SMBus Grant */
-#define E1000_MANC_SMB_CLK_IN    0x04000000	/* SMBus Clock In */
-#define E1000_MANC_SMB_DATA_IN   0x08000000	/* SMBus Data In */
+#define E1000_MANC_SMB_REQ	 0x01000000	/* SMBus Request */
+#define E1000_MANC_SMB_GNT	 0x02000000	/* SMBus Grant */
+#define E1000_MANC_SMB_CLK_IN	 0x04000000	/* SMBus Clock In */
+#define E1000_MANC_SMB_DATA_IN	 0x08000000	/* SMBus Data In */
 #define E1000_MANC_SMB_DATA_OUT  0x10000000	/* SMBus Data Out */
-#define E1000_MANC_SMB_CLK_OUT   0x20000000	/* SMBus Clock Out */
+#define E1000_MANC_SMB_CLK_OUT	 0x20000000	/* SMBus Clock Out */
 
 #define E1000_MANC_SMB_DATA_OUT_SHIFT  28	/* SMBus Data Out Shift */
 #define E1000_MANC_SMB_CLK_OUT_SHIFT   29	/* SMBus Clock Out Shift */
@@ -1283,7 +1283,7 @@ struct e1000_hw {
 /* Wake Up Packet Length */
 #define E1000_WUPL_LENGTH_MASK 0x0FFF	/* Only the lower 12 bits are valid */
 
-#define E1000_MDALIGN          4096
+#define E1000_MDALIGN	       4096
 
 /* EEPROM Commands */
 #define EEPROM_READ_OPCODE  0x6	/* EERPOM read opcode */
@@ -1293,17 +1293,17 @@ struct e1000_hw {
 #define EEPROM_EWDS_OPCODE  0x10	/* EERPOM erast/write disable */
 
 /* EEPROM Word Offsets */
-#define EEPROM_COMPAT              0x0003
-#define EEPROM_ID_LED_SETTINGS     0x0004
+#define EEPROM_COMPAT		   0x0003
+#define EEPROM_ID_LED_SETTINGS	   0x0004
 #define EEPROM_INIT_CONTROL1_REG   0x000A
 #define EEPROM_INIT_CONTROL2_REG   0x000F
-#define EEPROM_FLASH_VERSION       0x0032
-#define EEPROM_CHECKSUM_REG        0x003F
+#define EEPROM_FLASH_VERSION	   0x0032
+#define EEPROM_CHECKSUM_REG	   0x003F
 
 /* Word definitions for ID LED Settings */
 #define ID_LED_RESERVED_0000 0x0000
 #define ID_LED_RESERVED_FFFF 0xFFFF
-#define ID_LED_DEFAULT       ((ID_LED_OFF1_ON2 << 12) | \
+#define ID_LED_DEFAULT	     ((ID_LED_OFF1_ON2 << 12) | \
 			      (ID_LED_OFF1_OFF2 << 8) | \
 			      (ID_LED_DEF1_DEF2 << 4) | \
 			      (ID_LED_DEF1_DEF2))
@@ -1311,7 +1311,7 @@ struct e1000_hw {
 #define ID_LED_DEF1_ON2      0x2
 #define ID_LED_DEF1_OFF2     0x3
 #define ID_LED_ON1_DEF2      0x4
-#define ID_LED_ON1_ON2       0x5
+#define ID_LED_ON1_ON2	     0x5
 #define ID_LED_ON1_OFF2      0x6
 #define ID_LED_OFF1_DEF2     0x7
 #define ID_LED_OFF1_ON2      0x8
@@ -1330,9 +1330,9 @@ struct e1000_hw {
 
 /* Mask bits for fields in Word 0x0f of the EEPROM */
 #define EEPROM_WORD0F_PAUSE_MASK 0x3000
-#define EEPROM_WORD0F_PAUSE      0x1000
-#define EEPROM_WORD0F_ASM_DIR    0x2000
-#define EEPROM_WORD0F_ANE        0x0800
+#define EEPROM_WORD0F_PAUSE	 0x1000
+#define EEPROM_WORD0F_ASM_DIR	 0x2000
+#define EEPROM_WORD0F_ANE	 0x0800
 #define EEPROM_WORD0F_SWPDIO_EXT 0x00F0
 
 /* For checksumming, the sum of all words in the EEPROM should equal 0xBABA. */
@@ -1340,19 +1340,19 @@ struct e1000_hw {
 
 /* EEPROM Map defines (WORD OFFSETS)*/
 #define EEPROM_NODE_ADDRESS_BYTE_0 0
-#define EEPROM_PBA_BYTE_1          8
+#define EEPROM_PBA_BYTE_1	   8
 
 /* EEPROM Map Sizes (Byte Counts) */
 #define PBA_SIZE 4
 
 /* Collision related configuration parameters */
-#define E1000_COLLISION_THRESHOLD       16
-#define E1000_CT_SHIFT                  4
-#define E1000_COLLISION_DISTANCE        64
-#define E1000_FDX_COLLISION_DISTANCE    E1000_COLLISION_DISTANCE
-#define E1000_HDX_COLLISION_DISTANCE    E1000_COLLISION_DISTANCE
+#define E1000_COLLISION_THRESHOLD	16
+#define E1000_CT_SHIFT			4
+#define E1000_COLLISION_DISTANCE	64
+#define E1000_FDX_COLLISION_DISTANCE	E1000_COLLISION_DISTANCE
+#define E1000_HDX_COLLISION_DISTANCE	E1000_COLLISION_DISTANCE
 #define E1000_GB_HDX_COLLISION_DISTANCE 512
-#define E1000_COLD_SHIFT                12
+#define E1000_COLD_SHIFT		12
 
 /* The number of Transmit and Receive Descriptors must be a multiple of 8 */
 #define REQ_TX_DESCRIPTOR_MULTIPLE  8
@@ -1369,11 +1369,11 @@ struct e1000_hw {
 
 #define DEFAULT_82542_TIPG_IPGR1 2
 #define DEFAULT_82543_TIPG_IPGR1 8
-#define E1000_TIPG_IPGR1_SHIFT  10
+#define E1000_TIPG_IPGR1_SHIFT	10
 
 #define DEFAULT_82542_TIPG_IPGR2 10
 #define DEFAULT_82543_TIPG_IPGR2 6
-#define E1000_TIPG_IPGR2_SHIFT  20
+#define E1000_TIPG_IPGR2_SHIFT	20
 
 #define E1000_TXDMAC_DPP 0x00000001
 
@@ -1384,11 +1384,11 @@ struct e1000_hw {
 #define TX_THRESHOLD_STOP      190
 #define TX_THRESHOLD_DISABLE   0
 #define TX_THRESHOLD_TIMER_MS  10000
-#define MIN_NUM_XMITS          1000
-#define IFS_MAX                80
-#define IFS_STEP               10
-#define IFS_MIN                40
-#define IFS_RATIO              4
+#define MIN_NUM_XMITS	       1000
+#define IFS_MAX		       80
+#define IFS_STEP	       10
+#define IFS_MIN		       40
+#define IFS_RATIO	       4
 
 /* PBA constants */
 #define E1000_PBA_16K 0x0010	/* 16KB, default TX allocation */
@@ -1399,12 +1399,12 @@ struct e1000_hw {
 /* Flow Control Constants */
 #define FLOW_CONTROL_ADDRESS_LOW  0x00C28001
 #define FLOW_CONTROL_ADDRESS_HIGH 0x00000100
-#define FLOW_CONTROL_TYPE         0x8808
+#define FLOW_CONTROL_TYPE	  0x8808
 
 /* The historical defaults for the flow control values are given below. */
-#define FC_DEFAULT_HI_THRESH        (0x8000)	/* 32KB */
-#define FC_DEFAULT_LO_THRESH        (0x4000)	/* 16KB */
-#define FC_DEFAULT_TX_TIMER         (0x100)	/* ~130 us */
+#define FC_DEFAULT_HI_THRESH	    (0x8000)	/* 32KB */
+#define FC_DEFAULT_LO_THRESH	    (0x4000)	/* 16KB */
+#define FC_DEFAULT_TX_TIMER	    (0x100)	/* ~130 us */
 
 /* Flow Control High-Watermark: 43464 bytes */
 #define E1000_FC_HIGH_THRESH 0xA9C8
@@ -1414,7 +1414,7 @@ struct e1000_hw {
 #define E1000_FC_PAUSE_TIME 0x0680
 
 /* PCIX Config space */
-#define PCIX_COMMAND_REGISTER    0xE6
+#define PCIX_COMMAND_REGISTER	 0xE6
 #define PCIX_STATUS_REGISTER_LO  0xE8
 #define PCIX_STATUS_REGISTER_HI  0xEA
 
@@ -1453,7 +1453,7 @@ struct e1000_hw {
 #define RECEIVE_BUFFER_ALIGN_SIZE  (256)
 
 /* The number of milliseconds we wait for auto-negotiation to complete */
-#define LINK_UP_TIMEOUT             500
+#define LINK_UP_TIMEOUT		    500
 
 #define E1000_TX_BUFFER_SIZE ((uint32_t)1514)
 
@@ -1463,14 +1463,14 @@ struct e1000_hw {
 /* TBI_ACCEPT macro definition:
  *
  * This macro requires:
- *      adapter = a pointer to struct e1000_hw
- *      status = the 8 bit status field of the RX descriptor with EOP set
- *      error = the 8 bit error field of the RX descriptor with EOP set
- *      length = the sum of all the length fields of the RX descriptors that
- *               make up the current frame
- *      last_byte = the last byte of the frame DMAed by the hardware
- *      max_frame_length = the maximum frame length we want to accept.
- *      min_frame_length = the minimum frame length we want to accept.
+ *	adapter = a pointer to struct e1000_hw
+ *	status = the 8 bit status field of the RX descriptor with EOP set
+ *	error = the 8 bit error field of the RX descriptor with EOP set
+ *	length = the sum of all the length fields of the RX descriptors that
+ *		 make up the current frame
+ *	last_byte = the last byte of the frame DMAed by the hardware
+ *	max_frame_length = the maximum frame length we want to accept.
+ *	min_frame_length = the minimum frame length we want to accept.
  *
  * This macro is a conditional that should be used in the interrupt
  * handler's Rx processing routine when RxErrors have been detected.
@@ -1478,11 +1478,11 @@ struct e1000_hw {
  * Typical use:
  *  ...
  *  if (TBI_ACCEPT) {
- *      accept_frame = TRUE;
- *      e1000_tbi_adjust_stats(adapter, MacAddress);
- *      frame_length--;
+ *	accept_frame = TRUE;
+ *	e1000_tbi_adjust_stats(adapter, MacAddress);
+ *	frame_length--;
  *  } else {
- *      accept_frame = FALSE;
+ *	accept_frame = FALSE;
  *  }
  *  ...
  */
@@ -1502,237 +1502,237 @@ struct e1000_hw {
 /* Bit definitions for the Management Data IO (MDIO) and Management Data
  * Clock (MDC) pins in the Device Control Register.
  */
-#define E1000_CTRL_PHY_RESET_DIR  E1000_CTRL_SWDPIO0
-#define E1000_CTRL_PHY_RESET      E1000_CTRL_SWDPIN0
-#define E1000_CTRL_MDIO_DIR       E1000_CTRL_SWDPIO2
-#define E1000_CTRL_MDIO           E1000_CTRL_SWDPIN2
-#define E1000_CTRL_MDC_DIR        E1000_CTRL_SWDPIO3
-#define E1000_CTRL_MDC            E1000_CTRL_SWDPIN3
-#define E1000_CTRL_PHY_RESET_DIR4 E1000_CTRL_EXT_SDP4_DIR
-#define E1000_CTRL_PHY_RESET4     E1000_CTRL_EXT_SDP4_DATA
+#define E1000_CTRL_PHY_RESET_DIR	E1000_CTRL_SWDPIO0
+#define E1000_CTRL_PHY_RESET		E1000_CTRL_SWDPIN0
+#define E1000_CTRL_MDIO_DIR		E1000_CTRL_SWDPIO2
+#define E1000_CTRL_MDIO			E1000_CTRL_SWDPIN2
+#define E1000_CTRL_MDC_DIR		E1000_CTRL_SWDPIO3
+#define E1000_CTRL_MDC			E1000_CTRL_SWDPIN3
+#define E1000_CTRL_PHY_RESET_DIR4	E1000_CTRL_EXT_SDP4_DIR
+#define E1000_CTRL_PHY_RESET4		E1000_CTRL_EXT_SDP4_DATA
 
 /* PHY 1000 MII Register/Bit Definitions */
 /* PHY Registers defined by IEEE */
-#define PHY_CTRL         0x00	/* Control Register */
-#define PHY_STATUS       0x01	/* Status Regiser */
-#define PHY_ID1          0x02	/* Phy Id Reg (word 1) */
-#define PHY_ID2          0x03	/* Phy Id Reg (word 2) */
-#define PHY_AUTONEG_ADV  0x04	/* Autoneg Advertisement */
-#define PHY_LP_ABILITY   0x05	/* Link Partner Ability (Base Page) */
-#define PHY_AUTONEG_EXP  0x06	/* Autoneg Expansion Reg */
-#define PHY_NEXT_PAGE_TX 0x07	/* Next Page TX */
-#define PHY_LP_NEXT_PAGE 0x08	/* Link Partner Next Page */
-#define PHY_1000T_CTRL   0x09	/* 1000Base-T Control Reg */
-#define PHY_1000T_STATUS 0x0A	/* 1000Base-T Status Reg */
-#define PHY_EXT_STATUS   0x0F	/* Extended Status Reg */
+#define PHY_CTRL			0x00	/* Control Register */
+#define PHY_STATUS			0x01	/* Status Regiser */
+#define PHY_ID1				0x02	/* Phy Id Reg (word 1) */
+#define PHY_ID2				0x03	/* Phy Id Reg (word 2) */
+#define PHY_AUTONEG_ADV		0x04	/* Autoneg Advertisement */
+#define PHY_LP_ABILITY			0x05	/* Link Partner Ability (Base Page) */
+#define PHY_AUTONEG_EXP		0x06	/* Autoneg Expansion Reg */
+#define PHY_NEXT_PAGE_TX		0x07	/* Next Page TX */
+#define PHY_LP_NEXT_PAGE		0x08	/* Link Partner Next Page */
+#define PHY_1000T_CTRL			0x09	/* 1000Base-T Control Reg */
+#define PHY_1000T_STATUS		0x0A	/* 1000Base-T Status Reg */
+#define PHY_EXT_STATUS			0x0F	/* Extended Status Reg */
 
 /* M88E1000 Specific Registers */
-#define M88E1000_PHY_SPEC_CTRL     0x10	/* PHY Specific Control Register */
-#define M88E1000_PHY_SPEC_STATUS   0x11	/* PHY Specific Status Register */
-#define M88E1000_INT_ENABLE        0x12	/* Interrupt Enable Register */
-#define M88E1000_INT_STATUS        0x13	/* Interrupt Status Register */
-#define M88E1000_EXT_PHY_SPEC_CTRL 0x14	/* Extended PHY Specific Control */
-#define M88E1000_RX_ERR_CNTR       0x15	/* Receive Error Counter */
+#define M88E1000_PHY_SPEC_CTRL		0x10	/* PHY Specific Control Register */
+#define M88E1000_PHY_SPEC_STATUS	0x11	/* PHY Specific Status Register */
+#define M88E1000_INT_ENABLE		0x12	/* Interrupt Enable Register */
+#define M88E1000_INT_STATUS		0x13	/* Interrupt Status Register */
+#define M88E1000_EXT_PHY_SPEC_CTRL	0x14	/* Extended PHY Specific Control */
+#define M88E1000_RX_ERR_CNTR		0x15	/* Receive Error Counter */
 
-#define MAX_PHY_REG_ADDRESS 	0x1F	/* 5 bit address bus (0-0x1F) */
+#define MAX_PHY_REG_ADDRESS		0x1F	/* 5 bit address bus (0-0x1F) */
 
 /* IGP01E1000 specifics */
-#define IGP01E1000_IEEE_REGS_PAGE  	0x0000
+#define IGP01E1000_IEEE_REGS_PAGE	0x0000
 #define IGP01E1000_IEEE_RESTART_AUTONEG 0x3300
-#define IGP01E1000_IEEE_FORCE_GIGA      0x0140
+#define IGP01E1000_IEEE_FORCE_GIGA	0x0140
 
 /* IGP01E1000 Specific Registers */
-#define IGP01E1000_PHY_PORT_CONFIG 	0x10 /* PHY Specific Port Config Register */
-#define IGP01E1000_PHY_PORT_STATUS 	0x11 /* PHY Specific Status Register */
-#define IGP01E1000_PHY_PORT_CTRL   	0x12 /* PHY Specific Control Register */
-#define IGP01E1000_PHY_LINK_HEALTH 	0x13 /* PHY Link Health Register */
-#define IGP01E1000_GMII_FIFO       	0x14 /* GMII FIFO Register */
-#define IGP01E1000_PHY_CHANNEL_QUALITY 	0x15 /* PHY Channel Quality Register */
-#define IGP02E1000_PHY_POWER_MGMT      	0x19
-#define IGP01E1000_PHY_PAGE_SELECT     	0x1F /* PHY Page Select Core Register */
+#define IGP01E1000_PHY_PORT_CONFIG	0x10 /* PHY Specific Port Config Register */
+#define IGP01E1000_PHY_PORT_STATUS	0x11 /* PHY Specific Status Register */
+#define IGP01E1000_PHY_PORT_CTRL	0x12 /* PHY Specific Control Register */
+#define IGP01E1000_PHY_LINK_HEALTH	0x13 /* PHY Link Health Register */
+#define IGP01E1000_GMII_FIFO		0x14 /* GMII FIFO Register */
+#define IGP01E1000_PHY_CHANNEL_QUALITY	0x15 /* PHY Channel Quality Register */
+#define IGP02E1000_PHY_POWER_MGMT	0x19
+#define IGP01E1000_PHY_PAGE_SELECT	0x1F /* PHY Page Select Core Register */
 
 /* PHY Control Register */
-#define MII_CR_SPEED_SELECT_MSB 0x0040	/* bits 6,13: 10=1000, 01=100, 00=10 */
-#define MII_CR_COLL_TEST_ENABLE 0x0080	/* Collision test enable */
-#define MII_CR_FULL_DUPLEX      0x0100	/* FDX =1, half duplex =0 */
-#define MII_CR_RESTART_AUTO_NEG 0x0200	/* Restart auto negotiation */
-#define MII_CR_ISOLATE          0x0400	/* Isolate PHY from MII */
-#define MII_CR_POWER_DOWN       0x0800	/* Power down */
-#define MII_CR_AUTO_NEG_EN      0x1000	/* Auto Neg Enable */
-#define MII_CR_SPEED_SELECT_LSB 0x2000	/* bits 6,13: 10=1000, 01=100, 00=10 */
-#define MII_CR_LOOPBACK         0x4000	/* 0 = normal, 1 = loopback */
-#define MII_CR_RESET            0x8000	/* 0 = normal, 1 = PHY reset */
+#define MII_CR_SPEED_SELECT_MSB		0x0040	/* bits 6,13: 10=1000, 01=100, 00=10 */
+#define MII_CR_COLL_TEST_ENABLE		0x0080	/* Collision test enable */
+#define MII_CR_FULL_DUPLEX		0x0100	/* FDX =1, half duplex =0 */
+#define MII_CR_RESTART_AUTO_NEG		0x0200	/* Restart auto negotiation */
+#define MII_CR_ISOLATE			0x0400	/* Isolate PHY from MII */
+#define MII_CR_POWER_DOWN		0x0800	/* Power down */
+#define MII_CR_AUTO_NEG_EN		0x1000	/* Auto Neg Enable */
+#define MII_CR_SPEED_SELECT_LSB		0x2000	/* bits 6,13: 10=1000, 01=100, 00=10 */
+#define MII_CR_LOOPBACK			0x4000	/* 0 = normal, 1 = loopback */
+#define MII_CR_RESET			0x8000	/* 0 = normal, 1 = PHY reset */
 
 /* PHY Status Register */
-#define MII_SR_EXTENDED_CAPS     0x0001	/* Extended register capabilities */
-#define MII_SR_JABBER_DETECT     0x0002	/* Jabber Detected */
-#define MII_SR_LINK_STATUS       0x0004	/* Link Status 1 = link */
-#define MII_SR_AUTONEG_CAPS      0x0008	/* Auto Neg Capable */
-#define MII_SR_REMOTE_FAULT      0x0010	/* Remote Fault Detect */
-#define MII_SR_AUTONEG_COMPLETE  0x0020	/* Auto Neg Complete */
-#define MII_SR_PREAMBLE_SUPPRESS 0x0040	/* Preamble may be suppressed */
-#define MII_SR_EXTENDED_STATUS   0x0100	/* Ext. status info in Reg 0x0F */
-#define MII_SR_100T2_HD_CAPS     0x0200	/* 100T2 Half Duplex Capable */
-#define MII_SR_100T2_FD_CAPS     0x0400	/* 100T2 Full Duplex Capable */
-#define MII_SR_10T_HD_CAPS       0x0800	/* 10T   Half Duplex Capable */
-#define MII_SR_10T_FD_CAPS       0x1000	/* 10T   Full Duplex Capable */
-#define MII_SR_100X_HD_CAPS      0x2000	/* 100X  Half Duplex Capable */
-#define MII_SR_100X_FD_CAPS      0x4000	/* 100X  Full Duplex Capable */
-#define MII_SR_100T4_CAPS        0x8000	/* 100T4 Capable */
+#define MII_SR_EXTENDED_CAPS		0x0001	/* Extended register capabilities */
+#define MII_SR_JABBER_DETECT		0x0002	/* Jabber Detected */
+#define MII_SR_LINK_STATUS		0x0004	/* Link Status 1 = link */
+#define MII_SR_AUTONEG_CAPS		0x0008	/* Auto Neg Capable */
+#define MII_SR_REMOTE_FAULT		0x0010	/* Remote Fault Detect */
+#define MII_SR_AUTONEG_COMPLETE		0x0020	/* Auto Neg Complete */
+#define MII_SR_PREAMBLE_SUPPRESS	0x0040	/* Preamble may be suppressed */
+#define MII_SR_EXTENDED_STATUS		0x0100	/* Ext. status info in Reg 0x0F */
+#define MII_SR_100T2_HD_CAPS		0x0200	/* 100T2 Half Duplex Capable */
+#define MII_SR_100T2_FD_CAPS		0x0400	/* 100T2 Full Duplex Capable */
+#define MII_SR_10T_HD_CAPS		0x0800	/* 10T	 Half Duplex Capable */
+#define MII_SR_10T_FD_CAPS		0x1000	/* 10T	 Full Duplex Capable */
+#define MII_SR_100X_HD_CAPS		0x2000	/* 100X  Half Duplex Capable */
+#define MII_SR_100X_FD_CAPS		0x4000	/* 100X  Full Duplex Capable */
+#define MII_SR_100T4_CAPS		0x8000	/* 100T4 Capable */
 
 /* Autoneg Advertisement Register */
-#define NWAY_AR_SELECTOR_FIELD 0x0001	/* indicates IEEE 802.3 CSMA/CD */
-#define NWAY_AR_10T_HD_CAPS    0x0020	/* 10T   Half Duplex Capable */
-#define NWAY_AR_10T_FD_CAPS    0x0040	/* 10T   Full Duplex Capable */
-#define NWAY_AR_100TX_HD_CAPS  0x0080	/* 100TX Half Duplex Capable */
-#define NWAY_AR_100TX_FD_CAPS  0x0100	/* 100TX Full Duplex Capable */
-#define NWAY_AR_100T4_CAPS     0x0200	/* 100T4 Capable */
-#define NWAY_AR_PAUSE          0x0400	/* Pause operation desired */
-#define NWAY_AR_ASM_DIR        0x0800	/* Asymmetric Pause Direction bit */
-#define NWAY_AR_REMOTE_FAULT   0x2000	/* Remote Fault detected */
-#define NWAY_AR_NEXT_PAGE      0x8000	/* Next Page ability supported */
+#define NWAY_AR_SELECTOR_FIELD		0x0001	/* indicates IEEE 802.3 CSMA/CD */
+#define NWAY_AR_10T_HD_CAPS		0x0020	/* 10T	 Half Duplex Capable */
+#define NWAY_AR_10T_FD_CAPS		0x0040	/* 10T	 Full Duplex Capable */
+#define NWAY_AR_100TX_HD_CAPS		0x0080	/* 100TX Half Duplex Capable */
+#define NWAY_AR_100TX_FD_CAPS		0x0100	/* 100TX Full Duplex Capable */
+#define NWAY_AR_100T4_CAPS		0x0200	/* 100T4 Capable */
+#define NWAY_AR_PAUSE			0x0400	/* Pause operation desired */
+#define NWAY_AR_ASM_DIR		0x0800	/* Asymmetric Pause Direction bit */
+#define NWAY_AR_REMOTE_FAULT		0x2000	/* Remote Fault detected */
+#define NWAY_AR_NEXT_PAGE		0x8000	/* Next Page ability supported */
 
 /* Link Partner Ability Register (Base Page) */
-#define NWAY_LPAR_SELECTOR_FIELD 0x0000	/* LP protocol selector field */
-#define NWAY_LPAR_10T_HD_CAPS    0x0020	/* LP is 10T   Half Duplex Capable */
-#define NWAY_LPAR_10T_FD_CAPS    0x0040	/* LP is 10T   Full Duplex Capable */
-#define NWAY_LPAR_100TX_HD_CAPS  0x0080	/* LP is 100TX Half Duplex Capable */
-#define NWAY_LPAR_100TX_FD_CAPS  0x0100	/* LP is 100TX Full Duplex Capable */
-#define NWAY_LPAR_100T4_CAPS     0x0200	/* LP is 100T4 Capable */
-#define NWAY_LPAR_PAUSE          0x0400	/* LP Pause operation desired */
-#define NWAY_LPAR_ASM_DIR        0x0800	/* LP Asymmetric Pause Direction bit */
-#define NWAY_LPAR_REMOTE_FAULT   0x2000	/* LP has detected Remote Fault */
-#define NWAY_LPAR_ACKNOWLEDGE    0x4000	/* LP has rx'd link code word */
-#define NWAY_LPAR_NEXT_PAGE      0x8000	/* Next Page ability supported */
+#define NWAY_LPAR_SELECTOR_FIELD	0x0000	/* LP protocol selector field */
+#define NWAY_LPAR_10T_HD_CAPS		0x0020	/* LP is 10T   Half Duplex Capable */
+#define NWAY_LPAR_10T_FD_CAPS		0x0040	/* LP is 10T   Full Duplex Capable */
+#define NWAY_LPAR_100TX_HD_CAPS	0x0080	/* LP is 100TX Half Duplex Capable */
+#define NWAY_LPAR_100TX_FD_CAPS	0x0100	/* LP is 100TX Full Duplex Capable */
+#define NWAY_LPAR_100T4_CAPS		0x0200	/* LP is 100T4 Capable */
+#define NWAY_LPAR_PAUSE			0x0400	/* LP Pause operation desired */
+#define NWAY_LPAR_ASM_DIR		0x0800	/* LP Asymmetric Pause Direction bit */
+#define NWAY_LPAR_REMOTE_FAULT		0x2000	/* LP has detected Remote Fault */
+#define NWAY_LPAR_ACKNOWLEDGE		0x4000	/* LP has rx'd link code word */
+#define NWAY_LPAR_NEXT_PAGE		0x8000	/* Next Page ability supported */
 
 /* Autoneg Expansion Register */
-#define NWAY_ER_LP_NWAY_CAPS      0x0001	/* LP has Auto Neg Capability */
-#define NWAY_ER_PAGE_RXD          0x0002	/* LP is 10T   Half Duplex Capable */
-#define NWAY_ER_NEXT_PAGE_CAPS    0x0004	/* LP is 10T   Full Duplex Capable */
-#define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008	/* LP is 100TX Half Duplex Capable */
-#define NWAY_ER_PAR_DETECT_FAULT  0x0100	/* LP is 100TX Full Duplex Capable */
+#define NWAY_ER_LP_NWAY_CAPS		0x0001	/* LP has Auto Neg Capability */
+#define NWAY_ER_PAGE_RXD		0x0002	/* LP is 10T   Half Duplex Capable */
+#define NWAY_ER_NEXT_PAGE_CAPS		0x0004	/* LP is 10T   Full Duplex Capable */
+#define NWAY_ER_LP_NEXT_PAGE_CAPS	0x0008	/* LP is 100TX Half Duplex Capable */
+#define NWAY_ER_PAR_DETECT_FAULT	0x0100	/* LP is 100TX Full Duplex Capable */
 
 /* Next Page TX Register */
-#define NPTX_MSG_CODE_FIELD 0x0001	/* NP msg code or unformatted data */
-#define NPTX_TOGGLE         0x0800	/* Toggles between exchanges
-					 * of different NP
-					 */
-#define NPTX_ACKNOWLDGE2    0x1000	/* 1 = will comply with msg
-					 * 0 = cannot comply with msg
-					 */
-#define NPTX_MSG_PAGE       0x2000	/* formatted(1)/unformatted(0) pg */
-#define NPTX_NEXT_PAGE      0x8000	/* 1 = addition NP will follow
-					 * 0 = sending last NP
-					 */
+#define NPTX_MSG_CODE_FIELD		0x0001	/* NP msg code or unformatted data */
+#define NPTX_TOGGLE			0x0800	/* Toggles between exchanges
+						 * of different NP
+						 */
+#define NPTX_ACKNOWLDGE2		0x1000	/* 1 = will comply with msg
+						 * 0 = cannot comply with msg
+						 */
+#define NPTX_MSG_PAGE			0x2000	/* formatted(1)/unformatted(0) pg */
+#define NPTX_NEXT_PAGE			0x8000	/* 1 = addition NP will follow
+						 * 0 = sending last NP
+						 */
 
 /* Link Partner Next Page Register */
-#define LP_RNPR_MSG_CODE_FIELD 0x0001	/* NP msg code or unformatted data */
-#define LP_RNPR_TOGGLE         0x0800	/* Toggles between exchanges
-					 * of different NP
-					 */
-#define LP_RNPR_ACKNOWLDGE2    0x1000	/* 1 = will comply with msg
-					 * 0 = cannot comply with msg
-					 */
-#define LP_RNPR_MSG_PAGE       0x2000	/* formatted(1)/unformatted(0) pg */
-#define LP_RNPR_ACKNOWLDGE     0x4000	/* 1 = ACK / 0 = NO ACK */
-#define LP_RNPR_NEXT_PAGE      0x8000	/* 1 = addition NP will follow
-					 * 0 = sending last NP
-					 */
+#define LP_RNPR_MSG_CODE_FIELD		0x0001	/* NP msg code or unformatted data */
+#define LP_RNPR_TOGGLE			0x0800	/* Toggles between exchanges
+						 * of different NP
+						 */
+#define LP_RNPR_ACKNOWLDGE2		0x1000	/* 1 = will comply with msg
+						 * 0 = cannot comply with msg
+						 */
+#define LP_RNPR_MSG_PAGE		0x2000	/* formatted(1)/unformatted(0) pg */
+#define LP_RNPR_ACKNOWLDGE		0x4000	/* 1 = ACK / 0 = NO ACK */
+#define LP_RNPR_NEXT_PAGE		0x8000	/* 1 = addition NP will follow
+						 * 0 = sending last NP
+						 */
 
 /* 1000BASE-T Control Register */
-#define CR_1000T_ASYM_PAUSE      0x0080	/* Advertise asymmetric pause bit */
-#define CR_1000T_HD_CAPS         0x0100	/* Advertise 1000T HD capability */
-#define CR_1000T_FD_CAPS         0x0200	/* Advertise 1000T FD capability  */
-#define CR_1000T_REPEATER_DTE    0x0400	/* 1=Repeater/switch device port */
-					/* 0=DTE device */
-#define CR_1000T_MS_VALUE        0x0800	/* 1=Configure PHY as Master */
-					/* 0=Configure PHY as Slave */
-#define CR_1000T_MS_ENABLE       0x1000	/* 1=Master/Slave manual config value */
-					/* 0=Automatic Master/Slave config */
-#define CR_1000T_TEST_MODE_NORMAL 0x0000	/* Normal Operation */
-#define CR_1000T_TEST_MODE_1     0x2000	/* Transmit Waveform test */
-#define CR_1000T_TEST_MODE_2     0x4000	/* Master Transmit Jitter test */
-#define CR_1000T_TEST_MODE_3     0x6000	/* Slave Transmit Jitter test */
-#define CR_1000T_TEST_MODE_4     0x8000	/* Transmitter Distortion test */
+#define CR_1000T_ASYM_PAUSE		0x0080	/* Advertise asymmetric pause bit */
+#define CR_1000T_HD_CAPS		0x0100	/* Advertise 1000T HD capability */
+#define CR_1000T_FD_CAPS		0x0200	/* Advertise 1000T FD capability  */
+#define CR_1000T_REPEATER_DTE		0x0400	/* 1=Repeater/switch device port */
+						/* 0=DTE device */
+#define CR_1000T_MS_VALUE		0x0800	/* 1=Configure PHY as Master */
+						/* 0=Configure PHY as Slave */
+#define CR_1000T_MS_ENABLE		0x1000	/* 1=Master/Slave manual config value */
+						/* 0=Automatic Master/Slave config */
+#define CR_1000T_TEST_MODE_NORMAL	0x0000	/* Normal Operation */
+#define CR_1000T_TEST_MODE_1		0x2000	/* Transmit Waveform test */
+#define CR_1000T_TEST_MODE_2		0x4000	/* Master Transmit Jitter test */
+#define CR_1000T_TEST_MODE_3		0x6000	/* Slave Transmit Jitter test */
+#define CR_1000T_TEST_MODE_4		0x8000	/* Transmitter Distortion test */
 
 /* 1000BASE-T Status Register */
-#define SR_1000T_IDLE_ERROR_CNT   0x00FF	/* Num idle errors since last read */
-#define SR_1000T_ASYM_PAUSE_DIR   0x0100	/* LP asymmetric pause direction bit */
-#define SR_1000T_LP_HD_CAPS       0x0400	/* LP is 1000T HD capable */
-#define SR_1000T_LP_FD_CAPS       0x0800	/* LP is 1000T FD capable */
-#define SR_1000T_REMOTE_RX_STATUS 0x1000	/* Remote receiver OK */
-#define SR_1000T_LOCAL_RX_STATUS  0x2000	/* Local receiver OK */
-#define SR_1000T_MS_CONFIG_RES    0x4000	/* 1=Local TX is Master, 0=Slave */
-#define SR_1000T_MS_CONFIG_FAULT  0x8000	/* Master/Slave config fault */
+#define SR_1000T_IDLE_ERROR_CNT	0x00FF	/* Num idle errors since last read */
+#define SR_1000T_ASYM_PAUSE_DIR	0x0100	/* LP asymmetric pause direction bit */
+#define SR_1000T_LP_HD_CAPS		0x0400	/* LP is 1000T HD capable */
+#define SR_1000T_LP_FD_CAPS		0x0800	/* LP is 1000T FD capable */
+#define SR_1000T_REMOTE_RX_STATUS	0x1000	/* Remote receiver OK */
+#define SR_1000T_LOCAL_RX_STATUS	0x2000	/* Local receiver OK */
+#define SR_1000T_MS_CONFIG_RES		0x4000	/* 1=Local TX is Master, 0=Slave */
+#define SR_1000T_MS_CONFIG_FAULT	0x8000	/* Master/Slave config fault */
 #define SR_1000T_REMOTE_RX_STATUS_SHIFT 12
-#define SR_1000T_LOCAL_RX_STATUS_SHIFT  13
+#define SR_1000T_LOCAL_RX_STATUS_SHIFT	13
 
 /* Extended Status Register */
-#define IEEE_ESR_1000T_HD_CAPS 0x1000	/* 1000T HD capable */
-#define IEEE_ESR_1000T_FD_CAPS 0x2000	/* 1000T FD capable */
-#define IEEE_ESR_1000X_HD_CAPS 0x4000	/* 1000X HD capable */
-#define IEEE_ESR_1000X_FD_CAPS 0x8000	/* 1000X FD capable */
+#define IEEE_ESR_1000T_HD_CAPS		0x1000	/* 1000T HD capable */
+#define IEEE_ESR_1000T_FD_CAPS		0x2000	/* 1000T FD capable */
+#define IEEE_ESR_1000X_HD_CAPS		0x4000	/* 1000X HD capable */
+#define IEEE_ESR_1000X_FD_CAPS		0x8000	/* 1000X FD capable */
 
-#define PHY_TX_POLARITY_MASK   0x0100	/* register 10h bit 8 (polarity bit) */
-#define PHY_TX_NORMAL_POLARITY 0	/* register 10h bit 8 (normal polarity) */
+#define PHY_TX_POLARITY_MASK		0x0100	/* register 10h bit 8 (polarity bit) */
+#define PHY_TX_NORMAL_POLARITY		0	/* register 10h bit 8 (normal polarity) */
 
-#define AUTO_POLARITY_DISABLE  0x0010	/* register 11h bit 4 */
-				      /* (0=enable, 1=disable) */
+#define AUTO_POLARITY_DISABLE		0x0010	/* register 11h bit 4 */
+						/* (0=enable, 1=disable) */
 
 /* M88E1000 PHY Specific Control Register */
-#define M88E1000_PSCR_JABBER_DISABLE    0x0001	/* 1=Jabber Function disabled */
+#define M88E1000_PSCR_JABBER_DISABLE	0x0001	/* 1=Jabber Function disabled */
 #define M88E1000_PSCR_POLARITY_REVERSAL 0x0002	/* 1=Polarity Reversal enabled */
-#define M88E1000_PSCR_SQE_TEST          0x0004	/* 1=SQE Test enabled */
-#define M88E1000_PSCR_CLK125_DISABLE    0x0010	/* 1=CLK125 low,
+#define M88E1000_PSCR_SQE_TEST		0x0004	/* 1=SQE Test enabled */
+#define M88E1000_PSCR_CLK125_DISABLE	0x0010	/* 1=CLK125 low,
 						 * 0=CLK125 toggling
 						 */
-#define M88E1000_PSCR_MDI_MANUAL_MODE  0x0000	/* MDI Crossover Mode bits 6:5 */
-					       /* Manual MDI configuration */
-#define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020	/* Manual MDIX configuration */
-#define M88E1000_PSCR_AUTO_X_1000T     0x0040	/* 1000BASE-T: Auto crossover,
+#define M88E1000_PSCR_MDI_MANUAL_MODE	0x0000	/* MDI Crossover Mode bits 6:5 */
+						/* Manual MDI configuration */
+#define M88E1000_PSCR_MDIX_MANUAL_MODE	0x0020	/* Manual MDIX configuration */
+#define M88E1000_PSCR_AUTO_X_1000T	0x0040	/* 1000BASE-T: Auto crossover,
 						 *  100BASE-TX/10BASE-T:
 						 *  MDI Mode
 						 */
-#define M88E1000_PSCR_AUTO_X_MODE      0x0060	/* Auto crossover enabled
+#define M88E1000_PSCR_AUTO_X_MODE	0x0060	/* Auto crossover enabled
 						 * all speeds.
 						 */
 #define M88E1000_PSCR_10BT_EXT_DIST_ENABLE 0x0080
-					/* 1=Enable Extended 10BASE-T distance
-					 * (Lower 10BASE-T RX Threshold)
-					 * 0=Normal 10BASE-T RX Threshold */
-#define M88E1000_PSCR_MII_5BIT_ENABLE      0x0100
-					/* 1=5-Bit interface in 100BASE-TX
-					 * 0=MII interface in 100BASE-TX */
-#define M88E1000_PSCR_SCRAMBLER_DISABLE    0x0200	/* 1=Scrambler disable */
-#define M88E1000_PSCR_FORCE_LINK_GOOD      0x0400	/* 1=Force link good */
-#define M88E1000_PSCR_ASSERT_CRS_ON_TX     0x0800	/* 1=Assert CRS on Transmit */
-
-#define M88E1000_PSCR_POLARITY_REVERSAL_SHIFT    1
-#define M88E1000_PSCR_AUTO_X_MODE_SHIFT          5
+						/* 1=Enable Extended 10BASE-T distance
+						 * (Lower 10BASE-T RX Threshold)
+						 * 0=Normal 10BASE-T RX Threshold */
+#define M88E1000_PSCR_MII_5BIT_ENABLE	0x0100
+						/* 1=5-Bit interface in 100BASE-TX
+						 * 0=MII interface in 100BASE-TX */
+#define M88E1000_PSCR_SCRAMBLER_DISABLE 0x0200	/* 1=Scrambler disable */
+#define M88E1000_PSCR_FORCE_LINK_GOOD	0x0400	/* 1=Force link good */
+#define M88E1000_PSCR_ASSERT_CRS_ON_TX	0x0800	/* 1=Assert CRS on Transmit */
+
+#define M88E1000_PSCR_POLARITY_REVERSAL_SHIFT	 1
+#define M88E1000_PSCR_AUTO_X_MODE_SHIFT		 5
 #define M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT 7
 
 /* M88E1000 PHY Specific Status Register */
-#define M88E1000_PSSR_JABBER             0x0001	/* 1=Jabber */
-#define M88E1000_PSSR_REV_POLARITY       0x0002	/* 1=Polarity reversed */
-#define M88E1000_PSSR_MDIX               0x0040	/* 1=MDIX; 0=MDI */
-#define M88E1000_PSSR_CABLE_LENGTH       0x0380	/* 0=<50M;1=50-80M;2=80-110M;
-						   * 3=110-140M;4=>140M */
-#define M88E1000_PSSR_LINK               0x0400	/* 1=Link up, 0=Link down */
-#define M88E1000_PSSR_SPD_DPLX_RESOLVED  0x0800	/* 1=Speed & Duplex resolved */
-#define M88E1000_PSSR_PAGE_RCVD          0x1000	/* 1=Page received */
-#define M88E1000_PSSR_DPLX               0x2000	/* 1=Duplex 0=Half Duplex */
-#define M88E1000_PSSR_SPEED              0xC000	/* Speed, bits 14:15 */
-#define M88E1000_PSSR_10MBS              0x0000	/* 00=10Mbs */
-#define M88E1000_PSSR_100MBS             0x4000	/* 01=100Mbs */
-#define M88E1000_PSSR_1000MBS            0x8000	/* 10=1000Mbs */
+#define M88E1000_PSSR_JABBER		0x0001	/* 1=Jabber */
+#define M88E1000_PSSR_REV_POLARITY	0x0002	/* 1=Polarity reversed */
+#define M88E1000_PSSR_MDIX		0x0040	/* 1=MDIX; 0=MDI */
+#define M88E1000_PSSR_CABLE_LENGTH	0x0380	/* 0=<50M;1=50-80M;2=80-110M;
+						 * 3=110-140M;4=>140M */
+#define M88E1000_PSSR_LINK		0x0400	/* 1=Link up, 0=Link down */
+#define M88E1000_PSSR_SPD_DPLX_RESOLVED 0x0800	/* 1=Speed & Duplex resolved */
+#define M88E1000_PSSR_PAGE_RCVD		0x1000	/* 1=Page received */
+#define M88E1000_PSSR_DPLX		0x2000	/* 1=Duplex 0=Half Duplex */
+#define M88E1000_PSSR_SPEED		0xC000	/* Speed, bits 14:15 */
+#define M88E1000_PSSR_10MBS		0x0000	/* 00=10Mbs */
+#define M88E1000_PSSR_100MBS		0x4000	/* 01=100Mbs */
+#define M88E1000_PSSR_1000MBS		0x8000	/* 10=1000Mbs */
 
 #define M88E1000_PSSR_REV_POLARITY_SHIFT 1
-#define M88E1000_PSSR_MDIX_SHIFT         6
+#define M88E1000_PSSR_MDIX_SHIFT	 6
 #define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7
 
 /* M88E1000 Extended PHY Specific Control Register */
-#define M88E1000_EPSCR_FIBER_LOOPBACK 0x4000	/* 1=Fiber loopback */
-#define M88E1000_EPSCR_DOWN_NO_IDLE   0x8000	/* 1=Lost lock detect enabled.
+#define M88E1000_EPSCR_FIBER_LOOPBACK	0x4000	/* 1=Fiber loopback */
+#define M88E1000_EPSCR_DOWN_NO_IDLE	0x8000	/* 1=Lost lock detect enabled.
 						 * Will assert lost lock and bring
 						 * link down if idle not seen
 						 * within 1ms in 1000BASE-T
@@ -1751,41 +1751,41 @@ struct e1000_hw {
 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X    0x0100
 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_2X    0x0200
 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_3X    0x0300
-#define M88E1000_EPSCR_TX_CLK_2_5     0x0060	/* 2.5 MHz TX_CLK */
-#define M88E1000_EPSCR_TX_CLK_25      0x0070	/* 25  MHz TX_CLK */
-#define M88E1000_EPSCR_TX_CLK_0       0x0000	/* NO  TX_CLK */
+#define M88E1000_EPSCR_TX_CLK_2_5	0x0060	/* 2.5 MHz TX_CLK */
+#define M88E1000_EPSCR_TX_CLK_25	0x0070	/* 25  MHz TX_CLK */
+#define M88E1000_EPSCR_TX_CLK_0	0x0000	/* NO  TX_CLK */
 
 /* Bit definitions for valid PHY IDs. */
-#define M88E1000_E_PHY_ID  0x01410C50
-#define M88E1000_I_PHY_ID  0x01410C30
-#define M88E1011_I_PHY_ID  0x01410C20
-#define M88E1000_12_PHY_ID M88E1000_E_PHY_ID
-#define M88E1000_14_PHY_ID M88E1000_E_PHY_ID
-#define IGP01E1000_I_PHY_ID  0x02A80380
+#define M88E1000_E_PHY_ID		0x01410C50
+#define M88E1000_I_PHY_ID		0x01410C30
+#define M88E1011_I_PHY_ID		0x01410C20
+#define M88E1000_12_PHY_ID		M88E1000_E_PHY_ID
+#define M88E1000_14_PHY_ID		M88E1000_E_PHY_ID
+#define IGP01E1000_I_PHY_ID		0x02A80380
 
 /* Miscellaneous PHY bit definitions. */
-#define PHY_PREAMBLE        0xFFFFFFFF
-#define PHY_SOF             0x01
-#define PHY_OP_READ         0x02
-#define PHY_OP_WRITE        0x01
-#define PHY_TURNAROUND      0x02
-#define PHY_PREAMBLE_SIZE   32
-#define MII_CR_SPEED_1000   0x0040
-#define MII_CR_SPEED_100    0x2000
-#define MII_CR_SPEED_10     0x0000
-#define E1000_PHY_ADDRESS   0x01
-#define PHY_AUTO_NEG_TIME   45	/* 4.5 Seconds */
-#define PHY_FORCE_TIME      20	/* 2.0 Seconds */
-#define PHY_REVISION_MASK   0xFFFFFFF0
-#define DEVICE_SPEED_MASK   0x00000300	/* Device Ctrl Reg Speed Mask */
-#define REG4_SPEED_MASK     0x01E0
-#define REG9_SPEED_MASK     0x0300
-#define ADVERTISE_10_HALF   0x0001
-#define ADVERTISE_10_FULL   0x0002
-#define ADVERTISE_100_HALF  0x0004
-#define ADVERTISE_100_FULL  0x0008
-#define ADVERTISE_1000_HALF 0x0010
-#define ADVERTISE_1000_FULL 0x0020
+#define PHY_PREAMBLE			0xFFFFFFFF
+#define PHY_SOF				0x01
+#define PHY_OP_READ			0x02
+#define PHY_OP_WRITE			0x01
+#define PHY_TURNAROUND			0x02
+#define PHY_PREAMBLE_SIZE		32
+#define MII_CR_SPEED_1000		0x0040
+#define MII_CR_SPEED_100		0x2000
+#define MII_CR_SPEED_10		0x0000
+#define E1000_PHY_ADDRESS		0x01
+#define PHY_AUTO_NEG_TIME		45	/* 4.5 Seconds */
+#define PHY_FORCE_TIME			20	/* 2.0 Seconds */
+#define PHY_REVISION_MASK		0xFFFFFFF0
+#define DEVICE_SPEED_MASK		0x00000300	/* Device Ctrl Reg Speed Mask */
+#define REG4_SPEED_MASK		0x01E0
+#define REG9_SPEED_MASK		0x0300
+#define ADVERTISE_10_HALF		0x0001
+#define ADVERTISE_10_FULL		0x0002
+#define ADVERTISE_100_HALF		0x0004
+#define ADVERTISE_100_FULL		0x0008
+#define ADVERTISE_1000_HALF		0x0010
+#define ADVERTISE_1000_FULL		0x0020
 #define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F	/* Everything but 1000-Half */
 
-#endif				/* _E1000_HW_H_ */
+#endif	/* _E1000_HW_H_ */
diff --git a/drivers/net/lan91c96.h b/drivers/net/lan91c96.h
index 7d33a821f3..5beddda040 100644
--- a/drivers/net/lan91c96.h
+++ b/drivers/net/lan91c96.h
@@ -31,7 +31,7 @@
  * information under www.smsc.com.
  *
  * Authors
- * 	Erik Stahlman				( erik@vt.edu )
+ *	Erik Stahlman				( erik@vt.edu )
  *	Daris A Nevil				( dnevil@snmc.com )
  *
  * History
@@ -58,7 +58,7 @@ void smc_set_mac_addr(const unsigned char *addr);
 
 typedef unsigned char			byte;
 typedef unsigned short			word;
-typedef unsigned long int 		dword;
+typedef unsigned long int		dword;
 
 /*
  * DEBUGGING LEVELS
@@ -88,8 +88,8 @@ typedef unsigned long int 		dword;
 
 #define	SMCREG(r)	(SMC_BASE_ADDRESS+((r)<<SMC_IO_SHIFT))
 
-#define	SMC_inl(r) 	(*((volatile dword *)SMCREG(r)))
-#define	SMC_inw(r) 	(*((volatile word *)SMCREG(r)))
+#define	SMC_inl(r)	(*((volatile dword *)SMCREG(r)))
+#define	SMC_inw(r)	(*((volatile word *)SMCREG(r)))
 #define SMC_inb(p) ({ \
 	unsigned int __p = p; \
 	unsigned int __v = SMC_inw(__p & ~1); \
@@ -122,7 +122,7 @@ typedef unsigned long int 		dword;
 					} \
 				})
 
-#define SMC_insl(r,b,l) 	({	int __i ;  \
+#define SMC_insl(r,b,l)		({	int __i ;  \
 					dword *__b2;  \
 					__b2 = (dword *) b;  \
 					for (__i = 0; __i < l; __i++) {  \
@@ -131,7 +131,7 @@ typedef unsigned long int 		dword;
 					};  \
 				})
 
-#define SMC_insw(r,b,l) 	({	int __i ;  \
+#define SMC_insw(r,b,l)		({	int __i ;  \
 					word *__b2;  \
 					__b2 = (word *) b;  \
 					for (__i = 0; __i < l; __i++) {  \
@@ -140,7 +140,7 @@ typedef unsigned long int 		dword;
 					};  \
 				})
 
-#define SMC_insb(r,b,l) 	({	int __i ;  \
+#define SMC_insb(r,b,l)		({	int __i ;  \
 					byte *__b2;  \
 					__b2 = (byte *) b;  \
 					for (__i = 0; __i < l; __i++) {  \
@@ -155,7 +155,7 @@ typedef unsigned long int 		dword;
  * We have only 16 Bit PCMCIA access on Socket 0
  */
 
-#define	SMC_inw(r) 	(*((volatile word *)(SMC_BASE_ADDRESS+(r))))
+#define	SMC_inw(r)	(*((volatile word *)(SMC_BASE_ADDRESS+(r))))
 #define  SMC_inb(r)	(((r)&1) ? SMC_inw((r)&~1)>>8 : SMC_inw(r)&0xFF)
 
 #define	SMC_outw(d,r)	(*((volatile word *)(SMC_BASE_ADDRESS+(r))) = d)
@@ -178,9 +178,9 @@ typedef unsigned long int 		dword;
 #endif
 
 #if 0
-#define	SMC_insw(r,b,l) 	insw(SMC_BASE_ADDRESS+(r), (b), (l))
+#define	SMC_insw(r,b,l)	insw(SMC_BASE_ADDRESS+(r), (b), (l))
 #else
-#define SMC_insw(r,b,l) 	({	int __i ;  \
+#define SMC_insw(r,b,l)	({	int __i ;  \
 					word *__b2;  \
 					__b2 = (word *) b;  \
 					for (__i = 0; __i < l; __i++) {  \
diff --git a/drivers/net/mcffec.c b/drivers/net/mcffec.c
index 71d19608ed..5ab4726ff5 100644
--- a/drivers/net/mcffec.c
+++ b/drivers/net/mcffec.c
@@ -208,7 +208,7 @@ int fec_recv(struct eth_device *dev)
 
 	for (;;) {
 #ifdef CFG_UNIFY_CACHE
-       		icache_invalid();
+		icache_invalid();
 #endif
 		/* section 16.9.23.2 */
 		if (info->rxbd[info->rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
diff --git a/drivers/net/natsemi.c b/drivers/net/natsemi.c
index 075d6c52c4..a523959812 100644
--- a/drivers/net/natsemi.c
+++ b/drivers/net/natsemi.c
@@ -62,58 +62,58 @@
 /* defines */
 #define EEPROM_SIZE 0xb /*12 16-bit chunks, or 24 bytes*/
 
-#define DSIZE     0x00000FFF
+#define DSIZE		0x00000FFF
 #define ETH_ALEN	6
-#define CRC_SIZE  4
-#define TOUT_LOOP   500000
-#define TX_BUF_SIZE    1536
-#define RX_BUF_SIZE    1536
-#define NUM_RX_DESC    4	/* Number of Rx descriptor registers. */
+#define CRC_SIZE	4
+#define TOUT_LOOP	500000
+#define TX_BUF_SIZE	1536
+#define RX_BUF_SIZE	1536
+#define NUM_RX_DESC	4	/* Number of Rx descriptor registers. */
 
 /* Offsets to the device registers.
    Unlike software-only systems, device drivers interact with complex hardware.
    It's not useful to define symbolic names for every register bit in the
    device.  */
 enum register_offsets {
-	ChipCmd 	= 0x00,
-	ChipConfig 	= 0x04,
-	EECtrl 		= 0x08,
-	IntrMask 	= 0x14,
-	IntrEnable 	= 0x18,
-	TxRingPtr 	= 0x20,
-	TxConfig 	= 0x24,
-	RxRingPtr 	= 0x30,
-	RxConfig 	= 0x34,
-	ClkRun 		= 0x3C,
-	RxFilterAddr 	= 0x48,
-	RxFilterData 	= 0x4C,
-	SiliconRev 	= 0x58,
-	PCIPM 		= 0x44,
+	ChipCmd	= 0x00,
+	ChipConfig	= 0x04,
+	EECtrl		= 0x08,
+	IntrMask	= 0x14,
+	IntrEnable	= 0x18,
+	TxRingPtr	= 0x20,
+	TxConfig	= 0x24,
+	RxRingPtr	= 0x30,
+	RxConfig	= 0x34,
+	ClkRun		= 0x3C,
+	RxFilterAddr	= 0x48,
+	RxFilterData	= 0x4C,
+	SiliconRev	= 0x58,
+	PCIPM		= 0x44,
 	BasicControl	= 0x80,
 	BasicStatus	= 0x84,
 	/* These are from the spec, around page 78... on a separate table. */
-	PGSEL 		= 0xCC,
-	PMDCSR 		= 0xE4,
-	TSTDAT 		= 0xFC,
-	DSPCFG 		= 0xF4,
-	SDCFG 		= 0x8C
+	PGSEL		= 0xCC,
+	PMDCSR		= 0xE4,
+	TSTDAT		= 0xFC,
+	DSPCFG		= 0xF4,
+	SDCFG		= 0x8C
 };
 
 /* Bit in ChipCmd. */
 enum ChipCmdBits {
-	ChipReset 	= 0x100,
-	RxReset 	= 0x20,
-	TxReset 	= 0x10,
-	RxOff 		= 0x08,
-	RxOn 		= 0x04,
-	TxOff 		= 0x02,
-	TxOn 		= 0x01
+	ChipReset	= 0x100,
+	RxReset		= 0x20,
+	TxReset		= 0x10,
+	RxOff		= 0x08,
+	RxOn		= 0x04,
+	TxOff		= 0x02,
+	TxOn		= 0x01
 };
 
 enum ChipConfigBits {
-	LinkSts 	= 0x80000000,
-	HundSpeed 	= 0x40000000,
-	FullDuplex 	= 0x20000000,
+	LinkSts	= 0x80000000,
+	HundSpeed	= 0x40000000,
+	FullDuplex	= 0x20000000,
 	TenPolarity	= 0x10000000,
 	AnegDone	= 0x08000000,
 	AnegEnBothBoth	= 0x0000E000,
@@ -127,58 +127,58 @@ enum ChipConfigBits {
 	SpeedMask	= 0x00004000,
 	AnegMask	= 0x00002000,
 	AnegDis10Half	= 0x00000000,
-	ExtPhy 		= 0x00001000,
-	PhyRst 		= 0x00000400,
-	PhyDis 		= 0x00000200,
+	ExtPhy		= 0x00001000,
+	PhyRst		= 0x00000400,
+	PhyDis		= 0x00000200,
 	BootRomDisable	= 0x00000004,
-	BEMode 		= 0x00000001,
+	BEMode		= 0x00000001,
 };
 
 enum TxConfig_bits {
-	TxDrthMask 	= 0x3f,
-	TxFlthMask 	= 0x3f00,
+	TxDrthMask	= 0x3f,
+	TxFlthMask	= 0x3f00,
 	TxMxdmaMask	= 0x700000,
-	TxMxdma_512 	= 0x0,
-	TxMxdma_4 	= 0x100000,
-	TxMxdma_8 	= 0x200000,
-	TxMxdma_16 	= 0x300000,
-	TxMxdma_32 	= 0x400000,
-	TxMxdma_64 	= 0x500000,
-	TxMxdma_128 	= 0x600000,
-	TxMxdma_256 	= 0x700000,
-	TxCollRetry 	= 0x800000,
-	TxAutoPad 	= 0x10000000,
-	TxMacLoop 	= 0x20000000,
-	TxHeartIgn 	= 0x40000000,
-	TxCarrierIgn 	= 0x80000000
+	TxMxdma_512	= 0x0,
+	TxMxdma_4	= 0x100000,
+	TxMxdma_8	= 0x200000,
+	TxMxdma_16	= 0x300000,
+	TxMxdma_32	= 0x400000,
+	TxMxdma_64	= 0x500000,
+	TxMxdma_128	= 0x600000,
+	TxMxdma_256	= 0x700000,
+	TxCollRetry	= 0x800000,
+	TxAutoPad	= 0x10000000,
+	TxMacLoop	= 0x20000000,
+	TxHeartIgn	= 0x40000000,
+	TxCarrierIgn	= 0x80000000
 };
 
 enum RxConfig_bits {
-	RxDrthMask 	= 0x3e,
-	RxMxdmaMask 	= 0x700000,
-	RxMxdma_512 	= 0x0,
-	RxMxdma_4 	= 0x100000,
-	RxMxdma_8 	= 0x200000,
-	RxMxdma_16 	= 0x300000,
-	RxMxdma_32 	= 0x400000,
-	RxMxdma_64 	= 0x500000,
-	RxMxdma_128 	= 0x600000,
-	RxMxdma_256 	= 0x700000,
-	RxAcceptLong 	= 0x8000000,
-	RxAcceptTx 	= 0x10000000,
-	RxAcceptRunt 	= 0x40000000,
-	RxAcceptErr 	= 0x80000000
+	RxDrthMask	= 0x3e,
+	RxMxdmaMask	= 0x700000,
+	RxMxdma_512	= 0x0,
+	RxMxdma_4	= 0x100000,
+	RxMxdma_8	= 0x200000,
+	RxMxdma_16	= 0x300000,
+	RxMxdma_32	= 0x400000,
+	RxMxdma_64	= 0x500000,
+	RxMxdma_128	= 0x600000,
+	RxMxdma_256	= 0x700000,
+	RxAcceptLong	= 0x8000000,
+	RxAcceptTx	= 0x10000000,
+	RxAcceptRunt	= 0x40000000,
+	RxAcceptErr	= 0x80000000
 };
 
 /* Bits in the RxMode register. */
 enum rx_mode_bits {
-	AcceptErr 		= 0x20,
-	AcceptRunt 		= 0x10,
-	AcceptBroadcast 	= 0xC0000000,
-	AcceptMulticast 	= 0x00200000,
-	AcceptAllMulticast 	= 0x20000000,
-	AcceptAllPhys 		= 0x10000000,
-	AcceptMyPhys 		= 0x08000000
+	AcceptErr	= 0x20,
+	AcceptRunt	= 0x10,
+	AcceptBroadcast	= 0xC0000000,
+	AcceptMulticast	= 0x00200000,
+	AcceptAllMulticast = 0x20000000,
+	AcceptAllPhys	= 0x10000000,
+	AcceptMyPhys	= 0x08000000
 };
 
 typedef struct _BufferDesc {
@@ -377,7 +377,7 @@ natsemi_initialize(bd_t * bis)
 		chip_config = INL(dev, ChipConfig);
 #ifdef NATSEMI_DEBUG
 		printf("%s: Transceiver status %#08X advertising %#08X\n",
-		       	dev->name, (int) INL(dev, BasicStatus), advertising);
+			dev->name, (int) INL(dev, BasicStatus), advertising);
 		printf("%s: Transceiver default autoneg. %s 10%s %s duplex.\n",
 			dev->name, chip_config & AnegMask ? "enabled, advertise" :
 			"disabled, force", chip_config & SpeedMask ? "0" : "",
@@ -550,7 +550,7 @@ mdio_read(struct eth_device *dev, int phy_id, int location)
  *
  * Arguments: struct eth_device *dev:          NIC data structure
  *
- * returns:  	int.
+ * returns:	int.
  */
 
 static int
@@ -693,8 +693,8 @@ natsemi_init_rxd(struct eth_device *dev)
 #ifdef NATSEMI_DEBUG
 		printf
 		    ("natsemi_init_rxd: rxd[%d]=%p link=%X cmdsts=%lX bufptr=%X\n",
-		     	i, &rxd[i], le32_to_cpu(rxd[i].link),
-		     		rxd[i].cmdsts, rxd[i].bufptr);
+			i, &rxd[i], le32_to_cpu(rxd[i].link),
+				rxd[i].cmdsts, rxd[i].bufptr);
 #endif
 	}
 
diff --git a/drivers/net/nicext.h b/drivers/net/nicext.h
index 4074972c07..ff422e7737 100644
--- a/drivers/net/nicext.h
+++ b/drivers/net/nicext.h
@@ -30,7 +30,7 @@
 /*
  * ioctl for NICE
  */
-#define SIOCNICE                   	SIOCDEVPRIVATE+7
+#define SIOCNICE	SIOCDEVPRIVATE+7
 
 /*
  * SIOCNICE:
diff --git a/drivers/net/ns8382x.c b/drivers/net/ns8382x.c
index f8b143a01a..c807dd4c7b 100644
--- a/drivers/net/ns8382x.c
+++ b/drivers/net/ns8382x.c
@@ -42,11 +42,11 @@
 /* Revision History
  * October 2002 mar	1.0
  *   Initial U-Boot Release.
- *   	Tested with Netgear GA622T (83820)
- *   	and SMC9452TX (83821)
- *   	NOTE: custom boards with these chips may (likely) require
- *   	a programmed EEPROM device (if present) in order to work
- *   	correctly.
+ *	Tested with Netgear GA622T (83820)
+ *	and SMC9452TX (83821)
+ *	NOTE: custom boards with these chips may (likely) require
+ *	a programmed EEPROM device (if present) in order to work
+ *	correctly.
 */
 
 /* Includes */
@@ -115,50 +115,50 @@ enum ChipConfigBits {
 #define SpeedStatus_Polarity ( GigSpeed | HundSpeed | FullDuplex)
 
 enum TxConfig_bits {
-	TxDrthMask 	= 0x000000ff,
-	TxFlthMask 	= 0x0000ff00,
+	TxDrthMask	= 0x000000ff,
+	TxFlthMask	= 0x0000ff00,
 	TxMxdmaMask	= 0x00700000,
-	TxMxdma_8 	= 0x00100000,
-	TxMxdma_16 	= 0x00200000,
-	TxMxdma_32 	= 0x00300000,
-	TxMxdma_64 	= 0x00400000,
-	TxMxdma_128 	= 0x00500000,
-	TxMxdma_256 	= 0x00600000,
-	TxMxdma_512 	= 0x00700000,
-	TxMxdma_1024 	= 0x00000000,
-	TxCollRetry 	= 0x00800000,
-	TxAutoPad 	= 0x10000000,
-	TxMacLoop 	= 0x20000000,
-	TxHeartIgn 	= 0x40000000,
-	TxCarrierIgn 	= 0x80000000
+	TxMxdma_8	= 0x00100000,
+	TxMxdma_16	= 0x00200000,
+	TxMxdma_32	= 0x00300000,
+	TxMxdma_64	= 0x00400000,
+	TxMxdma_128	= 0x00500000,
+	TxMxdma_256	= 0x00600000,
+	TxMxdma_512	= 0x00700000,
+	TxMxdma_1024	= 0x00000000,
+	TxCollRetry	= 0x00800000,
+	TxAutoPad	= 0x10000000,
+	TxMacLoop	= 0x20000000,
+	TxHeartIgn	= 0x40000000,
+	TxCarrierIgn	= 0x80000000
 };
 
 enum RxConfig_bits {
-	RxDrthMask 	= 0x0000003e,
-	RxMxdmaMask 	= 0x00700000,
-	RxMxdma_8 	= 0x00100000,
-	RxMxdma_16 	= 0x00200000,
-	RxMxdma_32 	= 0x00300000,
-	RxMxdma_64 	= 0x00400000,
-	RxMxdma_128 	= 0x00500000,
-	RxMxdma_256 	= 0x00600000,
-	RxMxdma_512 	= 0x00700000,
-	RxMxdma_1024 	= 0x00000000,
-	RxAcceptLenErr 	= 0x04000000,
-	RxAcceptLong 	= 0x08000000,
-	RxAcceptTx 	= 0x10000000,
-	RxStripCRC 	= 0x20000000,
-	RxAcceptRunt 	= 0x40000000,
-	RxAcceptErr 	= 0x80000000,
+	RxDrthMask	= 0x0000003e,
+	RxMxdmaMask	= 0x00700000,
+	RxMxdma_8	= 0x00100000,
+	RxMxdma_16	= 0x00200000,
+	RxMxdma_32	= 0x00300000,
+	RxMxdma_64	= 0x00400000,
+	RxMxdma_128	= 0x00500000,
+	RxMxdma_256	= 0x00600000,
+	RxMxdma_512	= 0x00700000,
+	RxMxdma_1024	= 0x00000000,
+	RxAcceptLenErr	= 0x04000000,
+	RxAcceptLong	= 0x08000000,
+	RxAcceptTx	= 0x10000000,
+	RxStripCRC	= 0x20000000,
+	RxAcceptRunt	= 0x40000000,
+	RxAcceptErr	= 0x80000000,
 };
 
 /* Bits in the RxMode register. */
 enum rx_mode_bits {
-	RxFilterEnable 		= 0x80000000,
-	AcceptAllBroadcast 	= 0x40000000,
-	AcceptAllMulticast 	= 0x20000000,
-	AcceptAllUnicast 	= 0x10000000,
-	AcceptPerfectMatch 	= 0x08000000,
+	RxFilterEnable		= 0x80000000,
+	AcceptAllBroadcast	= 0x40000000,
+	AcceptAllMulticast	= 0x20000000,
+	AcceptAllUnicast	= 0x10000000,
+	AcceptPerfectMatch	= 0x08000000,
 };
 
 typedef struct _BufferDesc {
@@ -527,7 +527,7 @@ mdio_write(struct eth_device *dev, int phy_id, int addr, int value)
  * Description: resets the ethernet controller chip and configures
  *    registers and data structures required for sending and receiving packets.
  * Arguments: struct eth_device *dev:       NIC data structure
- * returns:  	int.
+ * returns:	int.
  */
 
 static int
diff --git a/drivers/net/plb2800_eth.c b/drivers/net/plb2800_eth.c
index 0ae5d808a6..b8cc57aa78 100644
--- a/drivers/net/plb2800_eth.c
+++ b/drivers/net/plb2800_eth.c
@@ -333,7 +333,7 @@ static void plb2800_set_mac_addr(struct eth_device *dev, unsigned char * addr)
 	DA_LOOKUP = temp;
 
 	/* Set MA_LEARN register */
-	temp = 50 << MA_DEST_SHF; 	/* static entry */
+	temp = 50 << MA_DEST_SHF;	/* static entry */
 	MA_LEARN = temp;
 
 	/* set destination address */
diff --git a/drivers/net/rtl8019.h b/drivers/net/rtl8019.h
index 38116ad845..ae5163c431 100644
--- a/drivers/net/rtl8019.h
+++ b/drivers/net/rtl8019.h
@@ -30,88 +30,85 @@
 #include <asm/types.h>
 #include <config.h>
 
-
 #ifdef CONFIG_DRIVER_RTL8019
 
-#define		RTL8019_REG_00        		(RTL8019_BASE + 0x00)
-#define 	RTL8019_REG_01        		(RTL8019_BASE + 0x01)
-#define 	RTL8019_REG_02        		(RTL8019_BASE + 0x02)
-#define 	RTL8019_REG_03        		(RTL8019_BASE + 0x03)
-#define 	RTL8019_REG_04        		(RTL8019_BASE + 0x04)
-#define 	RTL8019_REG_05        		(RTL8019_BASE + 0x05)
-#define 	RTL8019_REG_06        		(RTL8019_BASE + 0x06)
-#define 	RTL8019_REG_07        		(RTL8019_BASE + 0x07)
-#define 	RTL8019_REG_08        		(RTL8019_BASE + 0x08)
-#define 	RTL8019_REG_09        		(RTL8019_BASE + 0x09)
-#define 	RTL8019_REG_0a        		(RTL8019_BASE + 0x0a)
-#define 	RTL8019_REG_0b        		(RTL8019_BASE + 0x0b)
-#define 	RTL8019_REG_0c        		(RTL8019_BASE + 0x0c)
-#define 	RTL8019_REG_0d        		(RTL8019_BASE + 0x0d)
-#define 	RTL8019_REG_0e       	 	(RTL8019_BASE + 0x0e)
-#define 	RTL8019_REG_0f        		(RTL8019_BASE + 0x0f)
-#define 	RTL8019_REG_10        		(RTL8019_BASE + 0x10)
-#define 	RTL8019_REG_1f        		(RTL8019_BASE + 0x1f)
-
-#define		RTL8019_COMMAND			RTL8019_REG_00
-#define		RTL8019_PAGESTART		RTL8019_REG_01
-#define		RTL8019_PAGESTOP		RTL8019_REG_02
-#define		RTL8019_BOUNDARY		RTL8019_REG_03
-#define		RTL8019_TRANSMITSTATUS		RTL8019_REG_04
-#define		RTL8019_TRANSMITPAGE		RTL8019_REG_04
-#define		RTL8019_TRANSMITBYTECOUNT0	RTL8019_REG_05
-#define		RTL8019_NCR 			RTL8019_REG_05
-#define		RTL8019_TRANSMITBYTECOUNT1 	RTL8019_REG_06
-#define		RTL8019_INTERRUPTSTATUS		RTL8019_REG_07
-#define		RTL8019_CURRENT 		RTL8019_REG_07
-#define		RTL8019_REMOTESTARTADDRESS0 	RTL8019_REG_08
-#define		RTL8019_CRDMA0  		RTL8019_REG_08
-#define		RTL8019_REMOTESTARTADDRESS1 	RTL8019_REG_09
-#define		RTL8019_CRDMA1 			RTL8019_REG_09
-#define		RTL8019_REMOTEBYTECOUNT0	RTL8019_REG_0a
-#define		RTL8019_REMOTEBYTECOUNT1	RTL8019_REG_0b
-#define		RTL8019_RECEIVESTATUS		RTL8019_REG_0c
-#define		RTL8019_RECEIVECONFIGURATION	RTL8019_REG_0c
-#define		RTL8019_TRANSMITCONFIGURATION	RTL8019_REG_0d
-#define		RTL8019_FAE_TALLY 		RTL8019_REG_0d
-#define		RTL8019_DATACONFIGURATION	RTL8019_REG_0e
-#define		RTL8019_CRC_TALLY 		RTL8019_REG_0e
-#define		RTL8019_INTERRUPTMASK		RTL8019_REG_0f
-#define		RTL8019_MISS_PKT_TALLY		RTL8019_REG_0f
-#define		RTL8019_PHYSICALADDRESS0	RTL8019_REG_01
-#define 	RTL8019_PHYSICALADDRESS1	RTL8019_REG_02
-#define		RTL8019_PHYSICALADDRESS2	RTL8019_REG_03
-#define		RTL8019_PHYSICALADDRESS3	RTL8019_REG_04
-#define		RTL8019_PHYSICALADDRESS4	RTL8019_REG_05
-#define		RTL8019_PHYSICALADDRESS5	RTL8019_REG_06
-#define		RTL8019_MULTIADDRESS0		RTL8019_REG_08
-#define		RTL8019_MULTIADDRESS1		RTL8019_REG_09
-#define		RTL8019_MULTIADDRESS2		RTL8019_REG_0a
-#define		RTL8019_MULTIADDRESS3		RTL8019_REG_0b
-#define		RTL8019_MULTIADDRESS4		RTL8019_REG_0c
-#define		RTL8019_MULTIADDRESS5		RTL8019_REG_0d
-#define		RTL8019_MULTIADDRESS6		RTL8019_REG_0e
-#define		RTL8019_MULTIADDRESS7		RTL8019_REG_0f
-#define		RTL8019_DMA_DATA		RTL8019_REG_10
-#define		RTL8019_RESET			RTL8019_REG_1f
-
+#define RTL8019_REG_00			(RTL8019_BASE + 0x00)
+#define	RTL8019_REG_01			(RTL8019_BASE + 0x01)
+#define	RTL8019_REG_02			(RTL8019_BASE + 0x02)
+#define	RTL8019_REG_03			(RTL8019_BASE + 0x03)
+#define	RTL8019_REG_04			(RTL8019_BASE + 0x04)
+#define	RTL8019_REG_05			(RTL8019_BASE + 0x05)
+#define	RTL8019_REG_06			(RTL8019_BASE + 0x06)
+#define	RTL8019_REG_07			(RTL8019_BASE + 0x07)
+#define	RTL8019_REG_08			(RTL8019_BASE + 0x08)
+#define	RTL8019_REG_09			(RTL8019_BASE + 0x09)
+#define	RTL8019_REG_0a			(RTL8019_BASE + 0x0a)
+#define	RTL8019_REG_0b			(RTL8019_BASE + 0x0b)
+#define	RTL8019_REG_0c			(RTL8019_BASE + 0x0c)
+#define	RTL8019_REG_0d			(RTL8019_BASE + 0x0d)
+#define	RTL8019_REG_0e			(RTL8019_BASE + 0x0e)
+#define	RTL8019_REG_0f			(RTL8019_BASE + 0x0f)
+#define	RTL8019_REG_10			(RTL8019_BASE + 0x10)
+#define	RTL8019_REG_1f			(RTL8019_BASE + 0x1f)
 
-#define 	RTL8019_PAGE0               	0x22
-#define   	RTL8019_PAGE1               	0x62
-#define   	RTL8019_PAGE0DMAWRITE       	0x12
-#define   	RTL8019_PAGE2DMAWRITE       	0x92
-#define   	RTL8019_REMOTEDMAWR         	0x12
-#define   	RTL8019_REMOTEDMARD         	0x0A
-#define   	RTL8019_ABORTDMAWR          	0x32
-#define   	RTL8019_ABORTDMARD          	0x2A
-#define   	RTL8019_PAGE0STOP           	0x21
-#define   	RTL8019_PAGE1STOP           	0x61
-#define   	RTL8019_TRANSMIT            	0x26
-#define   	RTL8019_TXINPROGRESS        	0x04
-#define   	RTL8019_SEND		    	0x1A
+#define RTL8019_COMMAND			RTL8019_REG_00
+#define RTL8019_PAGESTART		RTL8019_REG_01
+#define RTL8019_PAGESTOP		RTL8019_REG_02
+#define RTL8019_BOUNDARY		RTL8019_REG_03
+#define RTL8019_TRANSMITSTATUS		RTL8019_REG_04
+#define RTL8019_TRANSMITPAGE		RTL8019_REG_04
+#define RTL8019_TRANSMITBYTECOUNT0	RTL8019_REG_05
+#define RTL8019_NCR			RTL8019_REG_05
+#define RTL8019_TRANSMITBYTECOUNT1	RTL8019_REG_06
+#define RTL8019_INTERRUPTSTATUS		RTL8019_REG_07
+#define RTL8019_CURRENT			RTL8019_REG_07
+#define RTL8019_REMOTESTARTADDRESS0	RTL8019_REG_08
+#define RTL8019_CRDMA0			RTL8019_REG_08
+#define RTL8019_REMOTESTARTADDRESS1	RTL8019_REG_09
+#define RTL8019_CRDMA1			RTL8019_REG_09
+#define RTL8019_REMOTEBYTECOUNT0	RTL8019_REG_0a
+#define RTL8019_REMOTEBYTECOUNT1	RTL8019_REG_0b
+#define RTL8019_RECEIVESTATUS		RTL8019_REG_0c
+#define RTL8019_RECEIVECONFIGURATION	RTL8019_REG_0c
+#define RTL8019_TRANSMITCONFIGURATION	RTL8019_REG_0d
+#define RTL8019_FAE_TALLY		RTL8019_REG_0d
+#define RTL8019_DATACONFIGURATION	RTL8019_REG_0e
+#define RTL8019_CRC_TALLY		RTL8019_REG_0e
+#define RTL8019_INTERRUPTMASK		RTL8019_REG_0f
+#define RTL8019_MISS_PKT_TALLY		RTL8019_REG_0f
+#define RTL8019_PHYSICALADDRESS0	RTL8019_REG_01
+#define	RTL8019_PHYSICALADDRESS1	RTL8019_REG_02
+#define RTL8019_PHYSICALADDRESS2	RTL8019_REG_03
+#define RTL8019_PHYSICALADDRESS3	RTL8019_REG_04
+#define RTL8019_PHYSICALADDRESS4	RTL8019_REG_05
+#define RTL8019_PHYSICALADDRESS5	RTL8019_REG_06
+#define RTL8019_MULTIADDRESS0		RTL8019_REG_08
+#define RTL8019_MULTIADDRESS1		RTL8019_REG_09
+#define RTL8019_MULTIADDRESS2		RTL8019_REG_0a
+#define RTL8019_MULTIADDRESS3		RTL8019_REG_0b
+#define RTL8019_MULTIADDRESS4		RTL8019_REG_0c
+#define RTL8019_MULTIADDRESS5		RTL8019_REG_0d
+#define RTL8019_MULTIADDRESS6		RTL8019_REG_0e
+#define RTL8019_MULTIADDRESS7		RTL8019_REG_0f
+#define RTL8019_DMA_DATA		RTL8019_REG_10
+#define RTL8019_RESET			RTL8019_REG_1f
 
-#define		RTL8019_PSTART			0x4c
-#define		RTL8019_PSTOP			0x80
-#define		RTL8019_TPSTART			0x40
+#define	RTL8019_PAGE0			0x22
+#define	RTL8019_PAGE1			0x62
+#define	RTL8019_PAGE0DMAWRITE		0x12
+#define	RTL8019_PAGE2DMAWRITE		0x92
+#define	RTL8019_REMOTEDMAWR		0x12
+#define	RTL8019_REMOTEDMARD		0x0A
+#define	RTL8019_ABORTDMAWR		0x32
+#define	RTL8019_ABORTDMARD		0x2A
+#define	RTL8019_PAGE0STOP		0x21
+#define	RTL8019_PAGE1STOP		0x61
+#define	RTL8019_TRANSMIT		0x26
+#define	RTL8019_TXINPROGRESS		0x04
+#define	RTL8019_SEND			0x1A
 
+#define RTL8019_PSTART			0x4c
+#define RTL8019_PSTOP			0x80
+#define RTL8019_TPSTART			0x40
 
 #endif /*end of CONFIG_DRIVER_RTL8019*/
diff --git a/drivers/net/sk98lin/h/skdebug.h b/drivers/net/sk98lin/h/skdebug.h
index cf5b5ad332..5feda92e38 100644
--- a/drivers/net/sk98lin/h/skdebug.h
+++ b/drivers/net/sk98lin/h/skdebug.h
@@ -73,8 +73,8 @@
 #ifdef	DEBUG
 #ifndef SK_DBG_MSG
 #define SK_DBG_MSG(pAC,comp,cat,arg) \
-		if ( ((comp) & SK_DBG_CHKMOD(pAC)) && 	\
-		      ((cat) & SK_DBG_CHKCAT(pAC)) ) { 	\
+		if ( ((comp) & SK_DBG_CHKMOD(pAC)) &&	\
+		      ((cat) & SK_DBG_CHKCAT(pAC)) ) {	\
 			SK_DBG_PRINTF arg ;		\
 		}
 #endif
diff --git a/drivers/net/sk98lin/h/skdrv2nd.h b/drivers/net/sk98lin/h/skdrv2nd.h
index a311827aa7..a55005fc19 100644
--- a/drivers/net/sk98lin/h/skdrv2nd.h
+++ b/drivers/net/sk98lin/h/skdrv2nd.h
@@ -283,7 +283,7 @@ struct s_TxD {
 
 
 /* definition of flags in descriptor control field */
-#define	RX_CTRL_OWN_BMU 	UINT32_C(0x80000000)
+#define	RX_CTRL_OWN_BMU		UINT32_C(0x80000000)
 #define	RX_CTRL_STF		UINT32_C(0x40000000)
 #define	RX_CTRL_EOF		UINT32_C(0x20000000)
 #define	RX_CTRL_EOB_IRQ		UINT32_C(0x10000000)
@@ -295,7 +295,7 @@ struct s_TxD {
 #define RX_CTRL_CHECK_CSUM	UINT32_C(0x00560000)
 #define	RX_CTRL_LEN_MASK	UINT32_C(0x0000FFFF)
 
-#define	TX_CTRL_OWN_BMU 	UINT32_C(0x80000000)
+#define	TX_CTRL_OWN_BMU		UINT32_C(0x80000000)
 #define	TX_CTRL_STF		UINT32_C(0x40000000)
 #define	TX_CTRL_EOF		UINT32_C(0x20000000)
 #define	TX_CTRL_EOB_IRQ		UINT32_C(0x10000000)
diff --git a/drivers/net/sk98lin/h/skgedrv.h b/drivers/net/sk98lin/h/skgedrv.h
index 72ba9ce198..9810b39d40 100644
--- a/drivers/net/sk98lin/h/skgedrv.h
+++ b/drivers/net/sk98lin/h/skgedrv.h
@@ -58,15 +58,15 @@
  * Usually the events are defined by the destination module.
  * In case of the driver we put the definition of the events here.
  */
-#define SK_DRV_PORT_RESET		 1	/* The port needs to be reset */
-#define SK_DRV_NET_UP   		 2	/* The net is operational */
-#define SK_DRV_NET_DOWN			 3	/* The net is down */
-#define SK_DRV_SWITCH_SOFT		 4	/* Ports switch with both links connected */
-#define SK_DRV_SWITCH_HARD		 5	/* Port switch due to link failure */
-#define SK_DRV_RLMT_SEND		 6	/* Send a RLMT packet */
-#define SK_DRV_ADAP_FAIL		 7	/* The whole adapter fails */
-#define SK_DRV_PORT_FAIL		 8	/* One port fails */
+#define SK_DRV_PORT_RESET	 1	/* The port needs to be reset */
+#define SK_DRV_NET_UP		 2	/* The net is operational */
+#define SK_DRV_NET_DOWN		 3	/* The net is down */
+#define SK_DRV_SWITCH_SOFT	 4	/* Ports switch with both links connected */
+#define SK_DRV_SWITCH_HARD	 5	/* Port switch due to link failure */
+#define SK_DRV_RLMT_SEND	 6	/* Send a RLMT packet */
+#define SK_DRV_ADAP_FAIL	 7	/* The whole adapter fails */
+#define SK_DRV_PORT_FAIL	 8	/* One port fails */
 #define SK_DRV_SWITCH_INTERN	 9	/* Port switch by the driver itself */
-#define SK_DRV_POWER_DOWN		10	/* Power down mode */
+#define SK_DRV_POWER_DOWN	10	/* Power down mode */
 
 #endif	/* __INC_SKGEDRV_H_ */
diff --git a/drivers/net/sk98lin/h/skgehw.h b/drivers/net/sk98lin/h/skgehw.h
index 2c98427675..52dc83f8bc 100644
--- a/drivers/net/sk98lin/h/skgehw.h
+++ b/drivers/net/sk98lin/h/skgehw.h
@@ -110,10 +110,10 @@
  *
  * Revision 1.29  1999/01/26 08:55:48  malthoff
  * Bugfix: The 16 bit field relations inside the descriptor are
- * 	endianess dependend if the descriptor reversal feature
- * 	(PCI_REV_DESC bit in PCI_OUR_REG_2) is enabled.
- * 	Drivers which use this feature has to set the define
- * 	SK_USE_REV_DESC.
+ *	endianess dependend if the descriptor reversal feature
+ *	(PCI_REV_DESC bit in PCI_OUR_REG_2) is enabled.
+ *	Drivers which use this feature has to set the define
+ *	SK_USE_REV_DESC.
  *
  * Revision 1.28  1998/12/10 11:10:22  malthoff
  * bug fix: IS_IRQ_STAT and IS_IRQ_MST_ERR has been twisted.
@@ -274,7 +274,7 @@ extern "C" {
 #define BIT_10S		(1 << 10)
 #define BIT_9S		(1 << 9)
 #define BIT_8S		(1 << 8)
-#define BIT_7S 		(1 << 7)
+#define BIT_7S		(1 << 7)
 #define BIT_6S		(1 << 6)
 #define BIT_5S		(1 << 5)
 #define BIT_4S		(1 << 4)
@@ -340,27 +340,27 @@ extern "C" {
 #define PCI_SUB_VID		0x2c	/* 16 bit	Subsystem Vendor ID */
 #define PCI_SUB_ID		0x2e	/* 16 bit	Subsystem ID */
 #define PCI_BASE_ROM	0x30	/* 32 bit	Expansion ROM Base Address */
-#define PCI_CAP_PTR		0x34	/*  8 bit 	Capabilities Ptr */
+#define PCI_CAP_PTR		0x34	/*  8 bit	Capabilities Ptr */
 	/* Byte 35..3b:	reserved */
 #define PCI_IRQ_LINE	0x3c	/*  8 bit	Interrupt Line */
 #define PCI_IRQ_PIN		0x3d	/*  8 bit	Interrupt Pin */
 #define PCI_MIN_GNT		0x3e	/*  8 bit	Min_Gnt */
 #define PCI_MAX_LAT		0x3f	/*  8 bit	Max_Lat */
 	/* Device Dependent Region */
-#define PCI_OUR_REG_1	0x40	/* 32 bit 	Our Register 1 */
-#define PCI_OUR_REG_2	0x44	/* 32 bit 	Our Register 2 */
+#define PCI_OUR_REG_1	0x40	/* 32 bit	Our Register 1 */
+#define PCI_OUR_REG_2	0x44	/* 32 bit	Our Register 2 */
 	/* Power Management Region */
-#define PCI_PM_CAP_ID	0x48	/*  8 bit 	Power Management Cap. ID */
-#define PCI_PM_NITEM	0x49	/*  8 bit 	Next Item Ptr */
-#define PCI_PM_CAP_REG	0x4a	/* 16 bit 	Power Management Capabilities */
-#define PCI_PM_CTL_STS	0x4c	/* 16 bit 	Power Manag. Control/Status */
+#define PCI_PM_CAP_ID	0x48	/*  8 bit	Power Management Cap. ID */
+#define PCI_PM_NITEM	0x49	/*  8 bit	Next Item Ptr */
+#define PCI_PM_CAP_REG	0x4a	/* 16 bit	Power Management Capabilities */
+#define PCI_PM_CTL_STS	0x4c	/* 16 bit	Power Manag. Control/Status */
 	/* Byte 0x4e:	reserved */
-#define PCI_PM_DAT_REG	0x4f	/*  8 bit 	Power Manag. Data Register */
+#define PCI_PM_DAT_REG	0x4f	/*  8 bit	Power Manag. Data Register */
 	/* VPD Region */
-#define PCI_VPD_CAP_ID	0x50	/*  8 bit 	VPD Cap. ID */
-#define PCI_VPD_NITEM	0x51	/*  8 bit 	Next Item Ptr */
-#define PCI_VPD_ADR_REG	0x52	/* 16 bit 	VPD Address Register */
-#define PCI_VPD_DAT_REG	0x54	/* 32 bit 	VPD Data Register */
+#define PCI_VPD_CAP_ID	0x50	/*  8 bit	VPD Cap. ID */
+#define PCI_VPD_NITEM	0x51	/*  8 bit	Next Item Ptr */
+#define PCI_VPD_ADR_REG	0x52	/* 16 bit	VPD Address Register */
+#define PCI_VPD_DAT_REG	0x54	/* 32 bit	VPD Data Register */
 	/* Byte 0x58..0xff:	reserved */
 
 /*
@@ -530,7 +530,7 @@ extern "C" {
 #define PCI_PM_STATE_D0		0		/* D0:	Operational (default) */
 #define PCI_PM_STATE_D1		1		/* D1:	(YUKON only) */
 #define PCI_PM_STATE_D2		2		/* D2:	(YUKON only) */
-#define PCI_PM_STATE_D3 	3		/* D3:	HOT, Power Down and Reset */
+#define PCI_PM_STATE_D3		3		/* D3:	HOT, Power Down and Reset */
 
 /* VPD Region */
 /*	PCI_VPD_ADR_REG		16 bit	VPD Address Register */
@@ -602,7 +602,7 @@ extern "C" {
 #define B2_CONN_TYP		0x0118	/*  8 bit	Connector type */
 #define B2_PMD_TYP		0x0119	/*  8 bit	PMD type */
 #define B2_MAC_CFG		0x011a	/*  8 bit	MAC Configuration / Chip Revision */
-#define B2_CHIP_ID		0x011b	/*  8 bit 	Chip Identification Number */
+#define B2_CHIP_ID		0x011b	/*  8 bit	Chip Identification Number */
 	/* Eprom registers are currently of no use */
 #define B2_E_0			0x011c	/*  8 bit	EPROM Byte 0 (ext. SRAM size */
 #define B2_E_1			0x011d	/*  8 bit	EPROM Byte 1 (PHY type) */
@@ -623,7 +623,7 @@ extern "C" {
 #define B2_IRQM_VAL		0x0144	/* 32 bit	IRQ Moderation Timer Value */
 #define B2_IRQM_CTRL	0x0148	/*  8 bit	IRQ Moderation Timer Control */
 #define B2_IRQM_TEST	0x0149	/*  8 bit	IRQ Moderation Timer Test */
-#define B2_IRQM_MSK 	0x014c	/* 32 bit	IRQ Moderation Mask */
+#define B2_IRQM_MSK	0x014c	/* 32 bit	IRQ Moderation Mask */
 #define B2_IRQM_HWE_MSK 0x0150	/* 32 bit	IRQ Moderation HW Error Mask */
 	/* 0x0154 - 0x0157:	reserved */
 #define B2_TST_CTRL1	0x0158	/*  8 bit	Test Control Register 1 */
@@ -805,7 +805,7 @@ extern "C" {
  * use MR_ADDR() to access
  */
 #define RX_MFF_EA		0x0c00	/* 32 bit	Receive MAC FIFO End Address */
-#define RX_MFF_WP		0x0c04	/* 32 bit 	Receive MAC FIFO Write Pointer */
+#define RX_MFF_WP		0x0c04	/* 32 bit	Receive MAC FIFO Write Pointer */
 	/* 0x0c08 - 0x0c0b:	reserved */
 #define RX_MFF_RP		0x0c0c	/* 32 bit	Receive MAC FIFO Read Pointer */
 #define RX_MFF_PC		0x0c10	/* 32 bit	Receive MAC FIFO Packet Cnt */
@@ -837,13 +837,13 @@ extern "C" {
 #define RX_GMF_FL_MSK	0x0c4c	/* 32 bit	Rx GMAC FIFO Flush Mask */
 #define RX_GMF_FL_THR	0x0c50	/* 32 bit	Rx GMAC FIFO Flush Threshold */
 	/* 0x0c54 - 0x0c5f:	reserved */
-#define RX_GMF_WP		0x0c60	/* 32 bit 	Rx GMAC FIFO Write Pointer */
+#define RX_GMF_WP		0x0c60	/* 32 bit	Rx GMAC FIFO Write Pointer */
 	/* 0x0c64 - 0x0c67:	reserved */
-#define RX_GMF_WLEV		0x0c68	/* 32 bit 	Rx GMAC FIFO Write Level */
+#define RX_GMF_WLEV		0x0c68	/* 32 bit	Rx GMAC FIFO Write Level */
 	/* 0x0c6c - 0x0c6f:	reserved */
-#define RX_GMF_RP		0x0c70	/* 32 bit 	Rx GMAC FIFO Read Pointer */
+#define RX_GMF_RP		0x0c70	/* 32 bit	Rx GMAC FIFO Read Pointer */
 	/* 0x0c74 - 0x0c77:	reserved */
-#define RX_GMF_RLEV		0x0c78	/* 32 bit 	Rx GMAC FIFO Read Level */
+#define RX_GMF_RLEV		0x0c78	/* 32 bit	Rx GMAC FIFO Read Level */
 	/* 0x0c7c - 0x0c7f:	reserved */
 
 /*
@@ -860,7 +860,7 @@ extern "C" {
  * use MR_ADDR() to access
  */
 #define TX_MFF_EA		0x0d00	/* 32 bit	Transmit MAC FIFO End Address */
-#define TX_MFF_WP		0x0d04	/* 32 bit 	Transmit MAC FIFO WR Pointer */
+#define TX_MFF_WP		0x0d04	/* 32 bit	Transmit MAC FIFO WR Pointer */
 #define TX_MFF_WSP		0x0d08	/* 32 bit	Transmit MAC FIFO WR Shadow Ptr */
 #define TX_MFF_RP		0x0d0c	/* 32 bit	Transmit MAC FIFO RD Pointer */
 #define TX_MFF_PC		0x0d10	/* 32 bit	Transmit MAC FIFO Packet Cnt */
@@ -883,13 +883,13 @@ extern "C" {
 #define TX_GMF_AE_THR	0x0d44	/* 32 bit	Tx GMAC FIFO Almost Empty Thresh.*/
 #define TX_GMF_CTRL_T	0x0d48	/* 32 bit	Tx GMAC FIFO Control/Test */
 	/* 0x0d4c - 0x0d5f:	reserved */
-#define TX_GMF_WP		0x0d60	/* 32 bit 	Tx GMAC FIFO Write Pointer */
-#define TX_GMF_WSP		0x0d64	/* 32 bit 	Tx GMAC FIFO Write Shadow Ptr. */
-#define TX_GMF_WLEV		0x0d68	/* 32 bit 	Tx GMAC FIFO Write Level */
+#define TX_GMF_WP		0x0d60	/* 32 bit	Tx GMAC FIFO Write Pointer */
+#define TX_GMF_WSP		0x0d64	/* 32 bit	Tx GMAC FIFO Write Shadow Ptr. */
+#define TX_GMF_WLEV		0x0d68	/* 32 bit	Tx GMAC FIFO Write Level */
 	/* 0x0d6c - 0x0d6f:	reserved */
-#define TX_GMF_RP		0x0d70	/* 32 bit 	Tx GMAC FIFO Read Pointer */
-#define TX_GMF_RSTP		0x0d74	/* 32 bit 	Tx GMAC FIFO Restart Pointer */
-#define TX_GMF_RLEV		0x0d78	/* 32 bit 	Tx GMAC FIFO Read Level */
+#define TX_GMF_RP		0x0d70	/* 32 bit	Tx GMAC FIFO Read Pointer */
+#define TX_GMF_RSTP		0x0d74	/* 32 bit	Tx GMAC FIFO Restart Pointer */
+#define TX_GMF_RLEV		0x0d78	/* 32 bit	Tx GMAC FIFO Read Level */
 	/* 0x0d7c - 0x0d7f:	reserved */
 
 /*
@@ -1039,8 +1039,8 @@ extern "C" {
 /*	B0_ISRC		32 bit	Interrupt Source Register */
 /*	B0_IMSK		32 bit	Interrupt Mask Register */
 /*	B0_SP_ISRC	32 bit	Special Interrupt Source Reg */
-/*	B2_IRQM_MSK 	32 bit	IRQ Moderation Mask */
-#define IS_ALL_MSK		0xbfffffffL	/* 		All Interrupt bits */
+/*	B2_IRQM_MSK	32 bit	IRQ Moderation Mask */
+#define IS_ALL_MSK		0xbfffffffL	/*		All Interrupt bits */
 #define IS_HW_ERR		BIT_31		/* Interrupt HW Error */
 								/* Bit 30:	reserved */
 #define IS_PA_TO_RX1	BIT_29		/* Packet Arb Timeout Rx1 */
@@ -1085,7 +1085,7 @@ extern "C" {
 /*	B0_HWE_ISRC	32 bit	HW Error Interrupt Src Reg */
 /*	B0_HWE_IMSK	32 bit	HW Error Interrupt Mask Reg */
 /*	B2_IRQM_HWE_MSK 32 bit	IRQ Moderation HW Error Mask */
-#define IS_ERR_MSK		0x00000fffL	/* 		All Error bits */
+#define IS_ERR_MSK		0x00000fffL	/*		All Error bits */
 								/* Bit 31..14:	reserved */
 #define IS_IRQ_TIST_OV	BIT_13	/* Time Stamp Timer Overflow (YUKON only) */
 #define IS_IRQ_SENSOR	BIT_12	/* IRQ from Sensor (YUKON only) */
@@ -1112,7 +1112,7 @@ extern "C" {
 #define CFG_DIS_M2_CLK	BIT_1S		/* Disable Clock for 2nd MAC */
 #define CFG_SNG_MAC		BIT_0S		/* MAC Config: 0=2 MACs / 1=1 MAC*/
 
-/*	B2_CHIP_ID	 8 bit 	Chip Identification Number */
+/*	B2_CHIP_ID	 8 bit	Chip Identification Number */
 #define CHIP_ID_GENESIS	0x0a		/* Chip ID for GENESIS */
 #define CHIP_ID_YUKON	0xb0		/* Chip ID for YUKON */
 
@@ -1157,7 +1157,7 @@ extern "C" {
 #define DPT_START		BIT_1S	/* Start Descriptor Poll Timer */
 #define DPT_STOP		BIT_0S	/* Stop  Descriptor Poll Timer */
 
-/*	B2_E_3			 8 bit 	lower 4 bits used for HW self test result */
+/*	B2_E_3			 8 bit	lower 4 bits used for HW self test result */
 #define B2_E3_RES_MASK	0x0f
 
 /*	B2_TST_CTRL1	 8 bit	Test Control Register 1 */
@@ -1210,7 +1210,7 @@ extern "C" {
 #define I2C_BURST_LEN	BIT_4		/* Burst Len, 1/4 bytes */
 #define I2C_DEV_SIZE	(7L<<1)		/* Bit	3.. 1:	I2C Device Size	*/
 #define I2C_025K_DEV	(0L<<1)		/*		0: 256 Bytes or smal. */
-#define I2C_05K_DEV		(1L<<1)		/* 		1: 512	Bytes	*/
+#define I2C_05K_DEV		(1L<<1)		/*		1: 512	Bytes	*/
 #define I2C_1K_DEV		(2L<<1)		/*		2: 1024 Bytes	*/
 #define I2C_2K_DEV		(3L<<1)		/*		3: 2048	Bytes	*/
 #define I2C_4K_DEV		(4L<<1)		/*		4: 4096 Bytes	*/
@@ -1417,7 +1417,7 @@ extern "C" {
 #define F_WM_REACHED	BIT_25		/* Watermark reached */
 									/* reserved */
 #define F_FIFO_LEVEL	(0x1fL<<16)	/* Bit 23..16:	# of Qwords in FIFO */
-									/* Bit 15..11: 	reserved */
+									/* Bit 15..11:	reserved */
 #define F_WATER_MARK	0x0007ffL	/* Bit 10.. 0:	Watermark */
 
 /*	Q_T1	32 bit	Test Register 1 */
@@ -1501,12 +1501,12 @@ extern "C" {
 /* Receive and Transmit MAC FIFO Registers (GENESIS only) */
 
 /*	RX_MFF_EA	32 bit	Receive MAC FIFO End Address */
-/*	RX_MFF_WP	32 bit 	Receive MAC FIFO Write Pointer */
+/*	RX_MFF_WP	32 bit	Receive MAC FIFO Write Pointer */
 /*	RX_MFF_RP	32 bit	Receive MAC FIFO Read Pointer */
 /*	RX_MFF_PC	32 bit	Receive MAC FIFO Packet Counter */
 /*	RX_MFF_LEV	32 bit	Receive MAC FIFO Level */
 /*	TX_MFF_EA	32 bit	Transmit MAC FIFO End Address */
-/*	TX_MFF_WP	32 bit 	Transmit MAC FIFO Write Pointer */
+/*	TX_MFF_WP	32 bit	Transmit MAC FIFO Write Pointer */
 /*	TX_MFF_WSP	32 bit	Transmit MAC FIFO WR Shadow Pointer */
 /*	TX_MFF_RP	32 bit	Transmit MAC FIFO Read Pointer */
 /*	TX_MFF_PC	32 bit	Transmit MAC FIFO Packet Cnt */
@@ -1553,8 +1553,8 @@ extern "C" {
 
 #define MFF_TX_CTRL_DEF	(MFF_ENA_PKT_REC | MFF_ENA_TIM_PAT | MFF_ENA_FLUSH)
 
-/*	RX_MFF_TST2	 	 8 bit	Receive MAC FIFO Test Register 2 */
-/*	TX_MFF_TST2	 	 8 bit	Transmit MAC FIFO Test Register 2 */
+/*	RX_MFF_TST2		 8 bit	Receive MAC FIFO Test Register 2 */
+/*	TX_MFF_TST2		 8 bit	Transmit MAC FIFO Test Register 2 */
 								/* Bit 7:	reserved */
 #define MFF_WSP_T_ON	BIT_6S	/* Tx: Write Shadow Ptr TestOn */
 #define MFF_WSP_T_OFF	BIT_5S	/* Tx: Write Shadow Ptr TstOff */
@@ -1564,8 +1564,8 @@ extern "C" {
 #define MFF_PC_T_OFF	BIT_1S	/* Packet Counter Test Off */
 #define MFF_PC_INC		BIT_0S	/* Packet Counter Increment */
 
-/*	RX_MFF_TST1	 	 8 bit	Receive MAC FIFO Test Register 1 */
-/*	TX_MFF_TST1	 	 8 bit	Transmit MAC FIFO Test Register 1 */
+/*	RX_MFF_TST1		 8 bit	Receive MAC FIFO Test Register 1 */
+/*	TX_MFF_TST1		 8 bit	Transmit MAC FIFO Test Register 1 */
 					/* Bit 7:	reserved */
 #define MFF_WP_T_ON		BIT_6S	/* Write Pointer Test On */
 #define MFF_WP_T_OFF	BIT_5S	/* Write Pointer Test Off */
@@ -1593,7 +1593,7 @@ extern "C" {
 #define LED_START		BIT_2S	/* Start Timer */
 #define LED_STOP		BIT_1S	/* Stop Timer */
 #define LED_STATE		BIT_0S	/* Rx/Tx: LED State, 1=LED on */
-#define LED_CLR_IRQ		BIT_0S	/* Lnk: 	Clear Link IRQ */
+#define LED_CLR_IRQ		BIT_0S	/* Lnk:		Clear Link IRQ */
 
 /*	RX_LED_TST		 8 bit	Receive LED Cnt Test Register */
 /*	TX_LED_TST		 8 bit	Transmit LED Cnt Test Register */
@@ -1603,7 +1603,7 @@ extern "C" {
 #define LED_T_OFF		BIT_1S	/* LED Counter Test mode Off */
 #define LED_T_STEP		BIT_0S	/* LED Counter Step */
 
-/*	LNK_LED_REG	 	 8 bit	Link LED Register */
+/*	LNK_LED_REG		 8 bit	Link LED Register */
 								/* Bit 7.. 6:	reserved */
 #define LED_BLK_ON		BIT_5S	/* Link LED Blinking On */
 #define LED_BLK_OFF		BIT_4S	/* Link LED Blinking Off */
@@ -1616,18 +1616,18 @@ extern "C" {
 
 /*	RX_GMF_EA		32 bit	Rx GMAC FIFO End Address */
 /*	RX_GMF_AF_THR	32 bit	Rx GMAC FIFO Almost Full Thresh. */
-/*	RX_GMF_WP		32 bit 	Rx GMAC FIFO Write Pointer */
-/*	RX_GMF_WLEV		32 bit 	Rx GMAC FIFO Write Level */
-/*	RX_GMF_RP		32 bit 	Rx GMAC FIFO Read Pointer */
-/*	RX_GMF_RLEV		32 bit 	Rx GMAC FIFO Read Level */
+/*	RX_GMF_WP		32 bit	Rx GMAC FIFO Write Pointer */
+/*	RX_GMF_WLEV		32 bit	Rx GMAC FIFO Write Level */
+/*	RX_GMF_RP		32 bit	Rx GMAC FIFO Read Pointer */
+/*	RX_GMF_RLEV		32 bit	Rx GMAC FIFO Read Level */
 /*	TX_GMF_EA		32 bit	Tx GMAC FIFO End Address */
 /*	TX_GMF_AE_THR	32 bit	Tx GMAC FIFO Almost Empty Thresh.*/
-/*	TX_GMF_WP		32 bit 	Tx GMAC FIFO Write Pointer */
-/*	TX_GMF_WSP		32 bit 	Tx GMAC FIFO Write Shadow Ptr. */
-/*	TX_GMF_WLEV		32 bit 	Tx GMAC FIFO Write Level */
-/*	TX_GMF_RP		32 bit 	Tx GMAC FIFO Read Pointer */
-/*	TX_GMF_RSTP		32 bit 	Tx GMAC FIFO Restart Pointer */
-/*	TX_GMF_RLEV		32 bit 	Tx GMAC FIFO Read Level */
+/*	TX_GMF_WP		32 bit	Tx GMAC FIFO Write Pointer */
+/*	TX_GMF_WSP		32 bit	Tx GMAC FIFO Write Shadow Ptr. */
+/*	TX_GMF_WLEV		32 bit	Tx GMAC FIFO Write Level */
+/*	TX_GMF_RP		32 bit	Tx GMAC FIFO Read Pointer */
+/*	TX_GMF_RSTP		32 bit	Tx GMAC FIFO Restart Pointer */
+/*	TX_GMF_RLEV		32 bit	Tx GMAC FIFO Read Level */
 
 /*	RX_GMF_CTRL_T	32 bit	Rx GMAC FIFO Control/Test */
 						/* Bits 31..15:	reserved */
@@ -2211,11 +2211,11 @@ typedef	struct s_HwRxd {
  * PHY_WRITE()		write a 16 bit value to the PHY
  *
  * para:
- * 	IoC		I/O context needed for SK I/O macros
- * 	pPort	Pointer to port struct for PhyAddr
- * 	Mac		XMAC to access		values: MAC_1 or MAC_2
- * 	PhyReg	PHY Register to read or write
- * 	(p)Val	Value or pointer to the value which should be read or
+ *	IoC		I/O context needed for SK I/O macros
+ *	pPort	Pointer to port struct for PhyAddr
+ *	Mac		XMAC to access		values: MAC_1 or MAC_2
+ *	PhyReg	PHY Register to read or write
+ *	(p)Val	Value or pointer to the value which should be read or
  *			written.
  *
  * usage:	PHY_READ(IoC, pPort, MAC_1, PHY_CTRL, Value);
@@ -2224,26 +2224,26 @@ typedef	struct s_HwRxd {
  */
 #ifndef DEBUG
 #define PHY_READ(IoC, pPort, Mac, PhyReg, pVal) {						\
-	SK_U16 Mmu;  														\
+	SK_U16 Mmu;														\
 																		\
 	XM_OUT16((IoC), (Mac), XM_PHY_ADDR, (PhyReg) | (pPort)->PhyAddr);	\
 	XM_IN16((IoC), (Mac), XM_PHY_DATA, (pVal));							\
 	if ((pPort)->PhyType != SK_PHY_XMAC) {								\
-		do {  															\
+		do {															\
 			XM_IN16((IoC), (Mac), XM_MMU_CMD, &Mmu);					\
 		} while ((Mmu & XM_MMU_PHY_RDY) == 0);							\
 		XM_IN16((IoC), (Mac), XM_PHY_DATA, (pVal));						\
-	}  																	\
+	}																	\
 }
 #else
 #define PHY_READ(IoC, pPort, Mac, PhyReg, pVal) {						\
-	SK_U16 Mmu;  														\
+	SK_U16 Mmu;														\
 	int __i = 0;														\
 																		\
 	XM_OUT16((IoC), (Mac), XM_PHY_ADDR, (PhyReg) | (pPort)->PhyAddr);	\
 	XM_IN16((IoC), (Mac), XM_PHY_DATA, (pVal));							\
 	if ((pPort)->PhyType != SK_PHY_XMAC) {								\
-		do {  															\
+		do {															\
 			XM_IN16((IoC), (Mac), XM_MMU_CMD, &Mmu);					\
 			__i++;														\
 			if (__i > 100000) {											\
@@ -2254,7 +2254,7 @@ typedef	struct s_HwRxd {
 			}															\
 		} while ((Mmu & XM_MMU_PHY_RDY) == 0);							\
 		XM_IN16((IoC), (Mac), XM_PHY_DATA, (pVal));						\
-	}  																	\
+	}																	\
 }
 #endif /* DEBUG */
 
@@ -2262,17 +2262,17 @@ typedef	struct s_HwRxd {
 	SK_U16 Mmu;															\
 																		\
 	if ((pPort)->PhyType != SK_PHY_XMAC) {								\
-		do {  															\
+		do {															\
 			XM_IN16((IoC), (Mac), XM_MMU_CMD, &Mmu);					\
 		} while ((Mmu & XM_MMU_PHY_BUSY) != 0);							\
-	}  																	\
+	}																	\
 	XM_OUT16((IoC), (Mac), XM_PHY_ADDR, (PhyReg) | (pPort)->PhyAddr);	\
 	XM_OUT16((IoC), (Mac), XM_PHY_DATA, (Val));							\
 	if ((pPort)->PhyType != SK_PHY_XMAC) {								\
-		do {  															\
+		do {															\
 			XM_IN16((IoC), (Mac), XM_MMU_CMD, &Mmu);					\
 		} while ((Mmu & XM_MMU_PHY_BUSY) != 0);							\
-	}  																	\
+	}																	\
 }
 
 /*
diff --git a/drivers/net/sk98lin/h/skgei2c.h b/drivers/net/sk98lin/h/skgei2c.h
index e639f733c6..78c25f8633 100644
--- a/drivers/net/sk98lin/h/skgei2c.h
+++ b/drivers/net/sk98lin/h/skgei2c.h
@@ -186,7 +186,7 @@
  * To watch the statemachine (JS) use the timer in two ways instead of one as hitherto
  */
 #define	SK_TIMER_WATCH_STATEMACHINE	0	/* Watch the statemachine to finish in a specific time */
-#define	SK_TIMER_NEW_GAUGING    	1	/* Start a new gauging when timer expires */
+#define	SK_TIMER_NEW_GAUGING		1	/* Start a new gauging when timer expires */
 
 
 /*
@@ -200,7 +200,7 @@
 #define	SK_SEN_TEMP_LOW_ERR       0	/* Temperature Low  Err  Threshold */
 
 /* VCC which should be 5 V */
-#define	SK_SEN_PCI_5V_HIGH_ERR  	5588	/* Voltage PCI High Err  Threshold */
+#define	SK_SEN_PCI_5V_HIGH_ERR	5588	/* Voltage PCI High Err  Threshold */
 #define	SK_SEN_PCI_5V_HIGH_WARN     5346	/* Voltage PCI High Warn Threshold */
 #define	SK_SEN_PCI_5V_LOW_WARN		4664	/* Voltage PCI Low  Warn Threshold */
 #define	SK_SEN_PCI_5V_LOW_ERR		4422	/* Voltage PCI Low  Err  Threshold */
@@ -270,10 +270,10 @@
 /*
  * ASIC Core 1V5 voltage (YUKON only)
  */
-#define	SK_SEN_CORE_1V5_HIGH_ERR    1650	/* Voltage ASIC Core High Err Threshold */
+#define	SK_SEN_CORE_1V5_HIGH_ERR	1650	/* Voltage ASIC Core High Err Threshold */
 #define	SK_SEN_CORE_1V5_HIGH_WARN	1575	/* Voltage ASIC Core High Warn Threshold */
 #define	SK_SEN_CORE_1V5_LOW_WARN	1425	/* Voltage ASIC Core Low Warn Threshold */
-#define	SK_SEN_CORE_1V5_LOW_ERR 	1350	/* Voltage ASIC Core Low Err Threshold */
+#define	SK_SEN_CORE_1V5_LOW_ERR		1350	/* Voltage ASIC Core Low Err Threshold */
 
 /*
  * FAN 1 speed
@@ -285,7 +285,7 @@
  */
 #define	SK_SEN_FAN_HIGH_ERR		20000	/* FAN Speed High Err Threshold */
 #define	SK_SEN_FAN_HIGH_WARN	20000	/* FAN Speed High Warn Threshold */
-#define	SK_SEN_FAN_LOW_WARN 	5200	/* FAN Speed Low Warn Threshold */
+#define	SK_SEN_FAN_LOW_WARN	5200	/* FAN Speed Low Warn Threshold */
 #define	SK_SEN_FAN_LOW_ERR		4550	/* FAN Speed Low Err Threshold */
 
 /*
diff --git a/drivers/net/sk98lin/h/skgeinit.h b/drivers/net/sk98lin/h/skgeinit.h
index cdddef92b3..ef101d79ec 100644
--- a/drivers/net/sk98lin/h/skgeinit.h
+++ b/drivers/net/sk98lin/h/skgeinit.h
@@ -486,7 +486,7 @@ extern "C" {
 /* Link Speed Current State */
 #define SK_LSPEED_STAT_UNKNOWN		1
 #define SK_LSPEED_STAT_10MBPS		2
-#define SK_LSPEED_STAT_100MBPS 		3
+#define SK_LSPEED_STAT_100MBPS		3
 #define SK_LSPEED_STAT_1000MBPS		4
 #define SK_LSPEED_STAT_INDETERMINATED 5
 
diff --git a/drivers/net/sk98lin/h/skgepnm2.h b/drivers/net/sk98lin/h/skgepnm2.h
index 5c44f47719..e812f28b93 100644
--- a/drivers/net/sk98lin/h/skgepnm2.h
+++ b/drivers/net/sk98lin/h/skgepnm2.h
@@ -248,7 +248,7 @@ typedef struct s_OidTabEntry {
 enum SK_MACSTATS {
 	SK_PNMI_HTX				= 0,
 	SK_PNMI_HTX_OCTET,
-	SK_PNMI_HTX_OCTETHIGH 	= SK_PNMI_HTX_OCTET,
+	SK_PNMI_HTX_OCTETHIGH	= SK_PNMI_HTX_OCTET,
 	SK_PNMI_HTX_OCTETLOW,
 	SK_PNMI_HTX_BROADCAST,
 	SK_PNMI_HTX_MULTICAST,
diff --git a/drivers/net/sk98lin/h/skgepnmi.h b/drivers/net/sk98lin/h/skgepnmi.h
index 7532313ba8..c93e99cb2e 100644
--- a/drivers/net/sk98lin/h/skgepnmi.h
+++ b/drivers/net/sk98lin/h/skgepnmi.h
@@ -67,7 +67,7 @@
  *	Changed macro PHYS2INST. Added pAC to Interface
  *
  *	Revision 1.47  2001/02/07 08:28:23  mkunz
- *	- Added Oids: 	OID_SKGE_DIAG_ACTION
+ *	- Added Oids:	OID_SKGE_DIAG_ACTION
  *					OID_SKGE_DIAG_RESULT
  *					OID_SKGE_MULTICAST_LIST
  *					OID_SKGE_CURRENT_PACKET_FILTER
@@ -253,22 +253,22 @@
 /*
  * Event definitions
  */
-#define SK_PNMI_EVT_SIRQ_OVERFLOW		1	/* Counter overflow */
-#define SK_PNMI_EVT_SEN_WAR_LOW			2	/* Lower war thres exceeded */
-#define SK_PNMI_EVT_SEN_WAR_UPP			3	/* Upper war thres exceeded */
-#define SK_PNMI_EVT_SEN_ERR_LOW			4	/* Lower err thres exceeded */
-#define SK_PNMI_EVT_SEN_ERR_UPP			5	/* Upper err thres exceeded */
-#define SK_PNMI_EVT_CHG_EST_TIMER		6	/* Timer event for RLMT Chg */
+#define SK_PNMI_EVT_SIRQ_OVERFLOW	1	/* Counter overflow */
+#define SK_PNMI_EVT_SEN_WAR_LOW		2	/* Lower war thres exceeded */
+#define SK_PNMI_EVT_SEN_WAR_UPP		3	/* Upper war thres exceeded */
+#define SK_PNMI_EVT_SEN_ERR_LOW		4	/* Lower err thres exceeded */
+#define SK_PNMI_EVT_SEN_ERR_UPP		5	/* Upper err thres exceeded */
+#define SK_PNMI_EVT_CHG_EST_TIMER	6	/* Timer event for RLMT Chg */
 #define SK_PNMI_EVT_UTILIZATION_TIMER	7	/* Timer event for Utiliza. */
-#define SK_PNMI_EVT_CLEAR_COUNTER		8	/* Clear statistic counters */
-#define SK_PNMI_EVT_XMAC_RESET			9	/* XMAC will be reset */
+#define SK_PNMI_EVT_CLEAR_COUNTER	8	/* Clear statistic counters */
+#define SK_PNMI_EVT_XMAC_RESET		9	/* XMAC will be reset */
 
-#define SK_PNMI_EVT_RLMT_PORT_UP		10	/* Port came logically up */
-#define SK_PNMI_EVT_RLMT_PORT_DOWN		11	/* Port went logically down */
+#define SK_PNMI_EVT_RLMT_PORT_UP	10	/* Port came logically up */
+#define SK_PNMI_EVT_RLMT_PORT_DOWN	11	/* Port went logically down */
 #define SK_PNMI_EVT_RLMT_SEGMENTATION	13	/* Two SP root bridges found */
 #define SK_PNMI_EVT_RLMT_ACTIVE_DOWN	14	/* Port went logically down */
-#define SK_PNMI_EVT_RLMT_ACTIVE_UP		15	/* Port came logically up */
-#define SK_PNMI_EVT_RLMT_SET_NETS		16	/* 1. Parameter is number of nets
+#define SK_PNMI_EVT_RLMT_ACTIVE_UP	15	/* Port came logically up */
+#define SK_PNMI_EVT_RLMT_SET_NETS	16	/* 1. Parameter is number of nets
 												1 = single net; 2 = dual net */
 #define SK_PNMI_EVT_VCT_RESET		17	/* VCT port reset timer event started with SET. */
 
@@ -276,14 +276,14 @@
 /*
  * Return values
  */
-#define SK_PNMI_ERR_OK				0
-#define SK_PNMI_ERR_GENERAL			1
+#define SK_PNMI_ERR_OK			0
+#define SK_PNMI_ERR_GENERAL		1
 #define SK_PNMI_ERR_TOO_SHORT		2
 #define SK_PNMI_ERR_BAD_VALUE		3
 #define SK_PNMI_ERR_READ_ONLY		4
 #define SK_PNMI_ERR_UNKNOWN_OID		5
 #define SK_PNMI_ERR_UNKNOWN_INST	6
-#define SK_PNMI_ERR_UNKNOWN_NET 	7
+#define SK_PNMI_ERR_UNKNOWN_NET		7
 
 
 /*
@@ -329,11 +329,11 @@
  */
 #ifndef _NDIS_	/* Check, whether NDIS already included OIDs */
 
-#define OID_GEN_XMIT_OK					0x00020101
-#define OID_GEN_RCV_OK					0x00020102
-#define OID_GEN_XMIT_ERROR				0x00020103
-#define OID_GEN_RCV_ERROR				0x00020104
-#define OID_GEN_RCV_NO_BUFFER			0x00020105
+#define OID_GEN_XMIT_OK			0x00020101
+#define OID_GEN_RCV_OK			0x00020102
+#define OID_GEN_XMIT_ERROR		0x00020103
+#define OID_GEN_RCV_ERROR		0x00020104
+#define OID_GEN_RCV_NO_BUFFER		0x00020105
 
 /* #define OID_GEN_DIRECTED_BYTES_XMIT	0x00020201 */
 #define OID_GEN_DIRECTED_FRAMES_XMIT	0x00020202
@@ -342,27 +342,27 @@
 /* #define OID_GEN_BROADCAST_BYTES_XMIT	0x00020205 */
 #define OID_GEN_BROADCAST_FRAMES_XMIT	0x00020206
 /* #define OID_GEN_DIRECTED_BYTES_RCV	0x00020207 */
-#define OID_GEN_DIRECTED_FRAMES_RCV		0x00020208
+#define OID_GEN_DIRECTED_FRAMES_RCV	0x00020208
 /* #define OID_GEN_MULTICAST_BYTES_RCV	0x00020209 */
 #define OID_GEN_MULTICAST_FRAMES_RCV	0x0002020A
 /* #define OID_GEN_BROADCAST_BYTES_RCV	0x0002020B */
 #define OID_GEN_BROADCAST_FRAMES_RCV	0x0002020C
-#define OID_GEN_RCV_CRC_ERROR			0x0002020D
+#define OID_GEN_RCV_CRC_ERROR		0x0002020D
 #define OID_GEN_TRANSMIT_QUEUE_LENGTH	0x0002020E
 
-#define OID_802_3_PERMANENT_ADDRESS		0x01010101
-#define OID_802_3_CURRENT_ADDRESS		0x01010102
-/* #define OID_802_3_MULTICAST_LIST		0x01010103 */
+#define OID_802_3_PERMANENT_ADDRESS	0x01010101
+#define OID_802_3_CURRENT_ADDRESS	0x01010102
+/* #define OID_802_3_MULTICAST_LIST	0x01010103 */
 /* #define OID_802_3_MAXIMUM_LIST_SIZE	0x01010104 */
-/* #define OID_802_3_MAC_OPTIONS		0x01010105 */
+/* #define OID_802_3_MAC_OPTIONS	0x01010105 */
 
 #define OID_802_3_RCV_ERROR_ALIGNMENT	0x01020101
 #define OID_802_3_XMIT_ONE_COLLISION	0x01020102
 #define OID_802_3_XMIT_MORE_COLLISIONS	0x01020103
-#define OID_802_3_XMIT_DEFERRED			0x01020201
+#define OID_802_3_XMIT_DEFERRED		0x01020201
 #define OID_802_3_XMIT_MAX_COLLISIONS	0x01020202
-#define OID_802_3_RCV_OVERRUN			0x01020203
-#define OID_802_3_XMIT_UNDERRUN			0x01020204
+#define OID_802_3_RCV_OVERRUN		0x01020203
+#define OID_802_3_XMIT_UNDERRUN		0x01020204
 #define OID_802_3_XMIT_TIMES_CRS_LOST	0x01020206
 #define OID_802_3_XMIT_LATE_COLLISIONS	0x01020207
 
@@ -370,193 +370,193 @@
  * PnP and PM OIDs
  */
 #ifdef SK_POWER_MGMT
-#define OID_PNP_CAPABILITIES			0xFD010100
-#define OID_PNP_SET_POWER				0xFD010101
-#define OID_PNP_QUERY_POWER				0xFD010102
-#define OID_PNP_ADD_WAKE_UP_PATTERN		0xFD010103
+#define OID_PNP_CAPABILITIES		0xFD010100
+#define OID_PNP_SET_POWER		0xFD010101
+#define OID_PNP_QUERY_POWER		0xFD010102
+#define OID_PNP_ADD_WAKE_UP_PATTERN	0xFD010103
 #define OID_PNP_REMOVE_WAKE_UP_PATTERN	0xFD010104
-#define OID_PNP_ENABLE_WAKE_UP			0xFD010106
+#define OID_PNP_ENABLE_WAKE_UP		0xFD010106
 #endif /* SK_POWER_MGMT */
 
 #endif /* _NDIS_ */
 
-#define OID_SKGE_MDB_VERSION			0xFF010100
-#define OID_SKGE_SUPPORTED_LIST			0xFF010101
-#define OID_SKGE_VPD_FREE_BYTES			0xFF010102
-#define OID_SKGE_VPD_ENTRIES_LIST		0xFF010103
-#define OID_SKGE_VPD_ENTRIES_NUMBER		0xFF010104
-#define OID_SKGE_VPD_KEY				0xFF010105
-#define OID_SKGE_VPD_VALUE				0xFF010106
-#define OID_SKGE_VPD_ACCESS				0xFF010107
-#define OID_SKGE_VPD_ACTION				0xFF010108
-
-#define OID_SKGE_PORT_NUMBER			0xFF010110
-#define OID_SKGE_DEVICE_TYPE			0xFF010111
-#define OID_SKGE_DRIVER_DESCR			0xFF010112
-#define OID_SKGE_DRIVER_VERSION			0xFF010113
-#define OID_SKGE_HW_DESCR				0xFF010114
-#define OID_SKGE_HW_VERSION				0xFF010115
-#define OID_SKGE_CHIPSET				0xFF010116
-#define OID_SKGE_ACTION					0xFF010117
-#define OID_SKGE_RESULT					0xFF010118
-#define OID_SKGE_BUS_TYPE				0xFF010119
-#define OID_SKGE_BUS_SPEED				0xFF01011A
-#define OID_SKGE_BUS_WIDTH				0xFF01011B
+#define OID_SKGE_MDB_VERSION		0xFF010100
+#define OID_SKGE_SUPPORTED_LIST		0xFF010101
+#define OID_SKGE_VPD_FREE_BYTES		0xFF010102
+#define OID_SKGE_VPD_ENTRIES_LIST	0xFF010103
+#define OID_SKGE_VPD_ENTRIES_NUMBER	0xFF010104
+#define OID_SKGE_VPD_KEY		0xFF010105
+#define OID_SKGE_VPD_VALUE		0xFF010106
+#define OID_SKGE_VPD_ACCESS		0xFF010107
+#define OID_SKGE_VPD_ACTION		0xFF010108
+
+#define OID_SKGE_PORT_NUMBER		0xFF010110
+#define OID_SKGE_DEVICE_TYPE		0xFF010111
+#define OID_SKGE_DRIVER_DESCR		0xFF010112
+#define OID_SKGE_DRIVER_VERSION		0xFF010113
+#define OID_SKGE_HW_DESCR		0xFF010114
+#define OID_SKGE_HW_VERSION		0xFF010115
+#define OID_SKGE_CHIPSET		0xFF010116
+#define OID_SKGE_ACTION			0xFF010117
+#define OID_SKGE_RESULT			0xFF010118
+#define OID_SKGE_BUS_TYPE		0xFF010119
+#define OID_SKGE_BUS_SPEED		0xFF01011A
+#define OID_SKGE_BUS_WIDTH		0xFF01011B
 /* 0xFF01011C unused */
-#define OID_SKGE_DIAG_ACTION			0xFF01011D
-#define OID_SKGE_DIAG_RESULT			0xFF01011E
-#define OID_SKGE_MTU					0xFF01011F
-#define OID_SKGE_PHYS_CUR_ADDR			0xFF010120
-#define OID_SKGE_PHYS_FAC_ADDR			0xFF010121
-#define OID_SKGE_PMD					0xFF010122
-#define OID_SKGE_CONNECTOR				0xFF010123
-#define OID_SKGE_LINK_CAP				0xFF010124
-#define OID_SKGE_LINK_MODE				0xFF010125
-#define OID_SKGE_LINK_MODE_STATUS		0xFF010126
-#define OID_SKGE_LINK_STATUS			0xFF010127
-#define OID_SKGE_FLOWCTRL_CAP			0xFF010128
-#define OID_SKGE_FLOWCTRL_MODE			0xFF010129
-#define OID_SKGE_FLOWCTRL_STATUS		0xFF01012A
-#define OID_SKGE_PHY_OPERATION_CAP		0xFF01012B
-#define OID_SKGE_PHY_OPERATION_MODE		0xFF01012C
+#define OID_SKGE_DIAG_ACTION		0xFF01011D
+#define OID_SKGE_DIAG_RESULT		0xFF01011E
+#define OID_SKGE_MTU			0xFF01011F
+#define OID_SKGE_PHYS_CUR_ADDR		0xFF010120
+#define OID_SKGE_PHYS_FAC_ADDR		0xFF010121
+#define OID_SKGE_PMD			0xFF010122
+#define OID_SKGE_CONNECTOR		0xFF010123
+#define OID_SKGE_LINK_CAP		0xFF010124
+#define OID_SKGE_LINK_MODE		0xFF010125
+#define OID_SKGE_LINK_MODE_STATUS	0xFF010126
+#define OID_SKGE_LINK_STATUS		0xFF010127
+#define OID_SKGE_FLOWCTRL_CAP		0xFF010128
+#define OID_SKGE_FLOWCTRL_MODE		0xFF010129
+#define OID_SKGE_FLOWCTRL_STATUS	0xFF01012A
+#define OID_SKGE_PHY_OPERATION_CAP	0xFF01012B
+#define OID_SKGE_PHY_OPERATION_MODE	0xFF01012C
 #define OID_SKGE_PHY_OPERATION_STATUS	0xFF01012D
-#define OID_SKGE_MULTICAST_LIST			0xFF01012E
+#define OID_SKGE_MULTICAST_LIST		0xFF01012E
 #define OID_SKGE_CURRENT_PACKET_FILTER	0xFF01012F
 
-#define OID_SKGE_TRAP					0xFF010130
-#define OID_SKGE_TRAP_NUMBER			0xFF010131
+#define OID_SKGE_TRAP			0xFF010130
+#define OID_SKGE_TRAP_NUMBER		0xFF010131
 
-#define OID_SKGE_RLMT_MODE				0xFF010140
-#define OID_SKGE_RLMT_PORT_NUMBER		0xFF010141
-#define OID_SKGE_RLMT_PORT_ACTIVE		0xFF010142
+#define OID_SKGE_RLMT_MODE		0xFF010140
+#define OID_SKGE_RLMT_PORT_NUMBER	0xFF010141
+#define OID_SKGE_RLMT_PORT_ACTIVE	0xFF010142
 #define OID_SKGE_RLMT_PORT_PREFERRED	0xFF010143
 #define OID_SKGE_INTERMEDIATE_SUPPORT	0xFF010160
 
-#define OID_SKGE_SPEED_CAP				0xFF010170
-#define OID_SKGE_SPEED_MODE				0xFF010171
-#define OID_SKGE_SPEED_STATUS			0xFF010172
+#define OID_SKGE_SPEED_CAP		0xFF010170
+#define OID_SKGE_SPEED_MODE		0xFF010171
+#define OID_SKGE_SPEED_STATUS		0xFF010172
 
-#define OID_SKGE_SENSOR_NUMBER			0xFF020100
-#define OID_SKGE_SENSOR_INDEX			0xFF020101
-#define OID_SKGE_SENSOR_DESCR			0xFF020102
-#define OID_SKGE_SENSOR_TYPE			0xFF020103
-#define OID_SKGE_SENSOR_VALUE			0xFF020104
+#define OID_SKGE_SENSOR_NUMBER		0xFF020100
+#define OID_SKGE_SENSOR_INDEX		0xFF020101
+#define OID_SKGE_SENSOR_DESCR		0xFF020102
+#define OID_SKGE_SENSOR_TYPE		0xFF020103
+#define OID_SKGE_SENSOR_VALUE		0xFF020104
 #define OID_SKGE_SENSOR_WAR_THRES_LOW	0xFF020105
 #define OID_SKGE_SENSOR_WAR_THRES_UPP	0xFF020106
 #define OID_SKGE_SENSOR_ERR_THRES_LOW	0xFF020107
 #define OID_SKGE_SENSOR_ERR_THRES_UPP	0xFF020108
-#define OID_SKGE_SENSOR_STATUS			0xFF020109
-#define OID_SKGE_SENSOR_WAR_CTS			0xFF02010A
-#define OID_SKGE_SENSOR_ERR_CTS			0xFF02010B
-#define OID_SKGE_SENSOR_WAR_TIME		0xFF02010C
-#define OID_SKGE_SENSOR_ERR_TIME		0xFF02010D
-
-#define OID_SKGE_CHKSM_NUMBER			0xFF020110
-#define OID_SKGE_CHKSM_RX_OK_CTS		0xFF020111
+#define OID_SKGE_SENSOR_STATUS		0xFF020109
+#define OID_SKGE_SENSOR_WAR_CTS		0xFF02010A
+#define OID_SKGE_SENSOR_ERR_CTS		0xFF02010B
+#define OID_SKGE_SENSOR_WAR_TIME	0xFF02010C
+#define OID_SKGE_SENSOR_ERR_TIME	0xFF02010D
+
+#define OID_SKGE_CHKSM_NUMBER		0xFF020110
+#define OID_SKGE_CHKSM_RX_OK_CTS	0xFF020111
 #define OID_SKGE_CHKSM_RX_UNABLE_CTS	0xFF020112
-#define OID_SKGE_CHKSM_RX_ERR_CTS		0xFF020113
-#define OID_SKGE_CHKSM_TX_OK_CTS		0xFF020114
+#define OID_SKGE_CHKSM_RX_ERR_CTS	0xFF020113
+#define OID_SKGE_CHKSM_TX_OK_CTS	0xFF020114
 #define OID_SKGE_CHKSM_TX_UNABLE_CTS	0xFF020115
 
-#define OID_SKGE_STAT_TX				0xFF020120
-#define OID_SKGE_STAT_TX_OCTETS			0xFF020121
-#define OID_SKGE_STAT_TX_BROADCAST		0xFF020122
-#define OID_SKGE_STAT_TX_MULTICAST		0xFF020123
-#define OID_SKGE_STAT_TX_UNICAST		0xFF020124
-#define OID_SKGE_STAT_TX_LONGFRAMES		0xFF020125
-#define OID_SKGE_STAT_TX_BURST			0xFF020126
-#define OID_SKGE_STAT_TX_PFLOWC			0xFF020127
-#define OID_SKGE_STAT_TX_FLOWC			0xFF020128
-#define OID_SKGE_STAT_TX_SINGLE_COL		0xFF020129
-#define OID_SKGE_STAT_TX_MULTI_COL		0xFF02012A
-#define OID_SKGE_STAT_TX_EXCESS_COL		0xFF02012B
-#define OID_SKGE_STAT_TX_LATE_COL		0xFF02012C
-#define OID_SKGE_STAT_TX_DEFFERAL		0xFF02012D
-#define OID_SKGE_STAT_TX_EXCESS_DEF		0xFF02012E
-#define OID_SKGE_STAT_TX_UNDERRUN		0xFF02012F
-#define OID_SKGE_STAT_TX_CARRIER		0xFF020130
-/* #define OID_SKGE_STAT_TX_UTIL		0xFF020131 */
-#define OID_SKGE_STAT_TX_64				0xFF020132
-#define OID_SKGE_STAT_TX_127			0xFF020133
-#define OID_SKGE_STAT_TX_255			0xFF020134
-#define OID_SKGE_STAT_TX_511			0xFF020135
-#define OID_SKGE_STAT_TX_1023			0xFF020136
-#define OID_SKGE_STAT_TX_MAX			0xFF020137
-#define OID_SKGE_STAT_TX_SYNC			0xFF020138
+#define OID_SKGE_STAT_TX		0xFF020120
+#define OID_SKGE_STAT_TX_OCTETS		0xFF020121
+#define OID_SKGE_STAT_TX_BROADCAST	0xFF020122
+#define OID_SKGE_STAT_TX_MULTICAST	0xFF020123
+#define OID_SKGE_STAT_TX_UNICAST	0xFF020124
+#define OID_SKGE_STAT_TX_LONGFRAMES	0xFF020125
+#define OID_SKGE_STAT_TX_BURST		0xFF020126
+#define OID_SKGE_STAT_TX_PFLOWC		0xFF020127
+#define OID_SKGE_STAT_TX_FLOWC		0xFF020128
+#define OID_SKGE_STAT_TX_SINGLE_COL	0xFF020129
+#define OID_SKGE_STAT_TX_MULTI_COL	0xFF02012A
+#define OID_SKGE_STAT_TX_EXCESS_COL	0xFF02012B
+#define OID_SKGE_STAT_TX_LATE_COL	0xFF02012C
+#define OID_SKGE_STAT_TX_DEFFERAL	0xFF02012D
+#define OID_SKGE_STAT_TX_EXCESS_DEF	0xFF02012E
+#define OID_SKGE_STAT_TX_UNDERRUN	0xFF02012F
+#define OID_SKGE_STAT_TX_CARRIER	0xFF020130
+/* #define OID_SKGE_STAT_TX_UTIL	0xFF020131 */
+#define OID_SKGE_STAT_TX_64		0xFF020132
+#define OID_SKGE_STAT_TX_127		0xFF020133
+#define OID_SKGE_STAT_TX_255		0xFF020134
+#define OID_SKGE_STAT_TX_511		0xFF020135
+#define OID_SKGE_STAT_TX_1023		0xFF020136
+#define OID_SKGE_STAT_TX_MAX		0xFF020137
+#define OID_SKGE_STAT_TX_SYNC		0xFF020138
 #define OID_SKGE_STAT_TX_SYNC_OCTETS	0xFF020139
-#define OID_SKGE_STAT_RX				0xFF02013A
-#define OID_SKGE_STAT_RX_OCTETS			0xFF02013B
-#define OID_SKGE_STAT_RX_BROADCAST		0xFF02013C
-#define OID_SKGE_STAT_RX_MULTICAST		0xFF02013D
-#define OID_SKGE_STAT_RX_UNICAST		0xFF02013E
-#define OID_SKGE_STAT_RX_PFLOWC			0xFF02013F
-#define OID_SKGE_STAT_RX_FLOWC			0xFF020140
-#define OID_SKGE_STAT_RX_PFLOWC_ERR		0xFF020141
+#define OID_SKGE_STAT_RX		0xFF02013A
+#define OID_SKGE_STAT_RX_OCTETS		0xFF02013B
+#define OID_SKGE_STAT_RX_BROADCAST	0xFF02013C
+#define OID_SKGE_STAT_RX_MULTICAST	0xFF02013D
+#define OID_SKGE_STAT_RX_UNICAST	0xFF02013E
+#define OID_SKGE_STAT_RX_PFLOWC		0xFF02013F
+#define OID_SKGE_STAT_RX_FLOWC		0xFF020140
+#define OID_SKGE_STAT_RX_PFLOWC_ERR	0xFF020141
 #define OID_SKGE_STAT_RX_FLOWC_UNKWN	0xFF020142
-#define OID_SKGE_STAT_RX_BURST			0xFF020143
-#define OID_SKGE_STAT_RX_MISSED			0xFF020144
-#define OID_SKGE_STAT_RX_FRAMING		0xFF020145
-#define OID_SKGE_STAT_RX_OVERFLOW		0xFF020146
-#define OID_SKGE_STAT_RX_JABBER			0xFF020147
-#define OID_SKGE_STAT_RX_CARRIER		0xFF020148
-#define OID_SKGE_STAT_RX_IR_LENGTH		0xFF020149
-#define OID_SKGE_STAT_RX_SYMBOL			0xFF02014A
-#define OID_SKGE_STAT_RX_SHORTS			0xFF02014B
-#define OID_SKGE_STAT_RX_RUNT			0xFF02014C
-#define OID_SKGE_STAT_RX_CEXT			0xFF02014D
-#define OID_SKGE_STAT_RX_TOO_LONG		0xFF02014E
-#define OID_SKGE_STAT_RX_FCS			0xFF02014F
-/* #define OID_SKGE_STAT_RX_UTIL		0xFF020150 */
-#define OID_SKGE_STAT_RX_64				0xFF020151
-#define OID_SKGE_STAT_RX_127			0xFF020152
-#define OID_SKGE_STAT_RX_255			0xFF020153
-#define OID_SKGE_STAT_RX_511			0xFF020154
-#define OID_SKGE_STAT_RX_1023			0xFF020155
-#define OID_SKGE_STAT_RX_MAX			0xFF020156
-#define OID_SKGE_STAT_RX_LONGFRAMES		0xFF020157
-
-#define OID_SKGE_RLMT_CHANGE_CTS		0xFF020160
-#define OID_SKGE_RLMT_CHANGE_TIME		0xFF020161
-#define OID_SKGE_RLMT_CHANGE_ESTIM		0xFF020162
-#define OID_SKGE_RLMT_CHANGE_THRES		0xFF020163
-
-#define OID_SKGE_RLMT_PORT_INDEX		0xFF020164
-#define OID_SKGE_RLMT_STATUS			0xFF020165
-#define OID_SKGE_RLMT_TX_HELLO_CTS		0xFF020166
-#define OID_SKGE_RLMT_RX_HELLO_CTS		0xFF020167
-#define OID_SKGE_RLMT_TX_SP_REQ_CTS		0xFF020168
-#define OID_SKGE_RLMT_RX_SP_CTS			0xFF020169
+#define OID_SKGE_STAT_RX_BURST		0xFF020143
+#define OID_SKGE_STAT_RX_MISSED		0xFF020144
+#define OID_SKGE_STAT_RX_FRAMING	0xFF020145
+#define OID_SKGE_STAT_RX_OVERFLOW	0xFF020146
+#define OID_SKGE_STAT_RX_JABBER		0xFF020147
+#define OID_SKGE_STAT_RX_CARRIER	0xFF020148
+#define OID_SKGE_STAT_RX_IR_LENGTH	0xFF020149
+#define OID_SKGE_STAT_RX_SYMBOL		0xFF02014A
+#define OID_SKGE_STAT_RX_SHORTS		0xFF02014B
+#define OID_SKGE_STAT_RX_RUNT		0xFF02014C
+#define OID_SKGE_STAT_RX_CEXT		0xFF02014D
+#define OID_SKGE_STAT_RX_TOO_LONG	0xFF02014E
+#define OID_SKGE_STAT_RX_FCS		0xFF02014F
+/* #define OID_SKGE_STAT_RX_UTIL	0xFF020150 */
+#define OID_SKGE_STAT_RX_64		0xFF020151
+#define OID_SKGE_STAT_RX_127		0xFF020152
+#define OID_SKGE_STAT_RX_255		0xFF020153
+#define OID_SKGE_STAT_RX_511		0xFF020154
+#define OID_SKGE_STAT_RX_1023		0xFF020155
+#define OID_SKGE_STAT_RX_MAX		0xFF020156
+#define OID_SKGE_STAT_RX_LONGFRAMES	0xFF020157
+
+#define OID_SKGE_RLMT_CHANGE_CTS	0xFF020160
+#define OID_SKGE_RLMT_CHANGE_TIME	0xFF020161
+#define OID_SKGE_RLMT_CHANGE_ESTIM	0xFF020162
+#define OID_SKGE_RLMT_CHANGE_THRES	0xFF020163
+
+#define OID_SKGE_RLMT_PORT_INDEX	0xFF020164
+#define OID_SKGE_RLMT_STATUS		0xFF020165
+#define OID_SKGE_RLMT_TX_HELLO_CTS	0xFF020166
+#define OID_SKGE_RLMT_RX_HELLO_CTS	0xFF020167
+#define OID_SKGE_RLMT_TX_SP_REQ_CTS	0xFF020168
+#define OID_SKGE_RLMT_RX_SP_CTS		0xFF020169
 
 #define OID_SKGE_RLMT_MONITOR_NUMBER	0xFF010150
-#define OID_SKGE_RLMT_MONITOR_INDEX		0xFF010151
-#define OID_SKGE_RLMT_MONITOR_ADDR		0xFF010152
-#define OID_SKGE_RLMT_MONITOR_ERRS		0xFF010153
+#define OID_SKGE_RLMT_MONITOR_INDEX	0xFF010151
+#define OID_SKGE_RLMT_MONITOR_ADDR	0xFF010152
+#define OID_SKGE_RLMT_MONITOR_ERRS	0xFF010153
 #define OID_SKGE_RLMT_MONITOR_TIMESTAMP	0xFF010154
-#define OID_SKGE_RLMT_MONITOR_ADMIN		0xFF010155
-
-#define OID_SKGE_TX_SW_QUEUE_LEN		0xFF020170
-#define OID_SKGE_TX_SW_QUEUE_MAX		0xFF020171
-#define OID_SKGE_TX_RETRY				0xFF020172
-#define OID_SKGE_RX_INTR_CTS			0xFF020173
-#define OID_SKGE_TX_INTR_CTS			0xFF020174
-#define OID_SKGE_RX_NO_BUF_CTS			0xFF020175
-#define OID_SKGE_TX_NO_BUF_CTS			0xFF020176
-#define OID_SKGE_TX_USED_DESCR_NO		0xFF020177
-#define OID_SKGE_RX_DELIVERED_CTS		0xFF020178
+#define OID_SKGE_RLMT_MONITOR_ADMIN	0xFF010155
+
+#define OID_SKGE_TX_SW_QUEUE_LEN	0xFF020170
+#define OID_SKGE_TX_SW_QUEUE_MAX	0xFF020171
+#define OID_SKGE_TX_RETRY		0xFF020172
+#define OID_SKGE_RX_INTR_CTS		0xFF020173
+#define OID_SKGE_TX_INTR_CTS		0xFF020174
+#define OID_SKGE_RX_NO_BUF_CTS		0xFF020175
+#define OID_SKGE_TX_NO_BUF_CTS		0xFF020176
+#define OID_SKGE_TX_USED_DESCR_NO	0xFF020177
+#define OID_SKGE_RX_DELIVERED_CTS	0xFF020178
 #define OID_SKGE_RX_OCTETS_DELIV_CTS	0xFF020179
-#define OID_SKGE_RX_HW_ERROR_CTS		0xFF02017A
-#define OID_SKGE_TX_HW_ERROR_CTS		0xFF02017B
-#define OID_SKGE_IN_ERRORS_CTS			0xFF02017C
-#define OID_SKGE_OUT_ERROR_CTS			0xFF02017D
-#define OID_SKGE_ERR_RECOVERY_CTS		0xFF02017E
-#define OID_SKGE_SYSUPTIME				0xFF02017F
+#define OID_SKGE_RX_HW_ERROR_CTS	0xFF02017A
+#define OID_SKGE_TX_HW_ERROR_CTS	0xFF02017B
+#define OID_SKGE_IN_ERRORS_CTS		0xFF02017C
+#define OID_SKGE_OUT_ERROR_CTS		0xFF02017D
+#define OID_SKGE_ERR_RECOVERY_CTS	0xFF02017E
+#define OID_SKGE_SYSUPTIME		0xFF02017F
 
-#define OID_SKGE_ALL_DATA				0xFF020190
+#define OID_SKGE_ALL_DATA		0xFF020190
 
 /* Defines for VCT. */
-#define OID_SKGE_VCT_GET			0xFF020200
-#define OID_SKGE_VCT_SET			0xFF020201
-#define OID_SKGE_VCT_STATUS			0xFF020202
+#define OID_SKGE_VCT_GET		0xFF020200
+#define OID_SKGE_VCT_SET		0xFF020201
+#define OID_SKGE_VCT_STATUS		0xFF020202
 
 
 /* VCT struct to store a backup copy of VCT data after a port reset. */
@@ -578,20 +578,20 @@ typedef struct s_PnmiVct {
 
 
 /* VCT cable test status. */
-#define SK_PNMI_VCT_NORMAL_CABLE		0
-#define SK_PNMI_VCT_SHORT_CABLE			1
-#define SK_PNMI_VCT_OPEN_CABLE			2
-#define SK_PNMI_VCT_TEST_FAIL			3
-#define SK_PNMI_VCT_IMPEDANCE_MISMATCH		4
-
-#define	OID_SKGE_TRAP_SEN_WAR_LOW		500
-#define OID_SKGE_TRAP_SEN_WAR_UPP		501
-#define	OID_SKGE_TRAP_SEN_ERR_LOW		502
-#define OID_SKGE_TRAP_SEN_ERR_UPP		503
+#define SK_PNMI_VCT_NORMAL_CABLE	0
+#define SK_PNMI_VCT_SHORT_CABLE		1
+#define SK_PNMI_VCT_OPEN_CABLE		2
+#define SK_PNMI_VCT_TEST_FAIL		3
+#define SK_PNMI_VCT_IMPEDANCE_MISMATCH	4
+
+#define	OID_SKGE_TRAP_SEN_WAR_LOW	500
+#define OID_SKGE_TRAP_SEN_WAR_UPP	501
+#define	OID_SKGE_TRAP_SEN_ERR_LOW	502
+#define OID_SKGE_TRAP_SEN_ERR_UPP	503
 #define OID_SKGE_TRAP_RLMT_CHANGE_THRES	520
 #define OID_SKGE_TRAP_RLMT_CHANGE_PORT	521
 #define OID_SKGE_TRAP_RLMT_PORT_DOWN	522
-#define OID_SKGE_TRAP_RLMT_PORT_UP		523
+#define OID_SKGE_TRAP_RLMT_PORT_UP	523
 #define OID_SKGE_TRAP_RLMT_SEGMENTATION	524
 
 
@@ -775,7 +775,7 @@ typedef struct s_PnmiVct {
 /*
  * Structure definition for SkPnmiGetStruct and SkPnmiSetStruct
  */
-#define SK_PNMI_VPD_KEY_SIZE	5
+#define SK_PNMI_VPD_KEY_SIZE		5
 #define SK_PNMI_VPD_BUFSIZE		(VPD_SIZE)
 #define SK_PNMI_VPD_ENTRIES		(VPD_SIZE / 4)
 #define SK_PNMI_VPD_DATALEN		128 /*  Number of data bytes */
@@ -783,12 +783,12 @@ typedef struct s_PnmiVct {
 #define SK_PNMI_MULTICAST_LISTLEN	64
 #define SK_PNMI_SENSOR_ENTRIES		(SK_MAX_SENSORS)
 #define SK_PNMI_CHECKSUM_ENTRIES	3
-#define SK_PNMI_MAC_ENTRIES			(SK_MAX_MACS + 1)
+#define SK_PNMI_MAC_ENTRIES		(SK_MAX_MACS + 1)
 #define SK_PNMI_MONITOR_ENTRIES		20
 #define SK_PNMI_TRAP_ENTRIES		10
-#define SK_PNMI_TRAPLEN				128
-#define SK_PNMI_STRINGLEN1			80
-#define SK_PNMI_STRINGLEN2			25
+#define SK_PNMI_TRAPLEN			128
+#define SK_PNMI_STRINGLEN1		80
+#define SK_PNMI_STRINGLEN2		25
 #define SK_PNMI_TRAP_QUEUE_LEN		512
 
 typedef struct s_PnmiVpd {
@@ -992,12 +992,12 @@ typedef struct s_PnmiStrucData {
 /*
  * Various definitions
  */
-#define SK_PNMI_MAX_PROTOS		3
+#define SK_PNMI_MAX_PROTOS	3
 
-#define SK_PNMI_CNT_NO			66	/* Must have the value of the enum
-									 * SK_PNMI_MAX_IDX. Define SK_PNMI_CHECK
-									 * for check while init phase 1
-									 */
+#define SK_PNMI_CNT_NO		66	/* Must have the value of the enum
+					 * SK_PNMI_MAX_IDX. Define SK_PNMI_CHECK
+					 * for check while init phase 1
+					 */
 
 /*
  * Estimate data structure
@@ -1091,7 +1091,6 @@ typedef struct s_PnmiData {
 	SK_PNMI_VCT_TIMER VctTimeout[SK_MAX_MACS];
 } SK_PNMI;
 
-
 /*
  * Function prototypes
  */
diff --git a/drivers/net/sk98lin/h/skvpd.h b/drivers/net/sk98lin/h/skvpd.h
index 1be34c5a97..3159e27c26 100644
--- a/drivers/net/sk98lin/h/skvpd.h
+++ b/drivers/net/sk98lin/h/skvpd.h
@@ -126,7 +126,7 @@
  * Define READ and WRITE Constants.
  */
 
-#define VPD_DEV_ID_GENESIS 	0x4300
+#define VPD_DEV_ID_GENESIS	0x4300
 
 #define	VPD_SIZE_YUKON		256
 #define	VPD_SIZE_GENESIS	512
@@ -223,19 +223,19 @@ typedef	struct s_vpd_key {
 		if ((pAC)->DgT.DgUseCfgCycle)			\
 			SkPciWriteCfgDWord(pAC,Addr,Val);	\
 		else						\
-			SK_OUT32(pAC,PCI_C(Addr),Val); 		\
+			SK_OUT32(pAC,PCI_C(Addr),Val);		\
 		}
 #define VPD_IN8(pAC,Ioc,Addr,pVal) {			\
-		if ((pAC)->DgT.DgUseCfgCycle) 			\
+		if ((pAC)->DgT.DgUseCfgCycle)			\
 			SkPciReadCfgByte(pAC,Addr,pVal);	\
 		else						\
-			SK_IN8(pAC,PCI_C(Addr),pVal); 		\
+			SK_IN8(pAC,PCI_C(Addr),pVal);		\
 		}
 #define VPD_IN16(pAC,Ioc,Addr,pVal) {			\
-		if ((pAC)->DgT.DgUseCfgCycle) 			\
+		if ((pAC)->DgT.DgUseCfgCycle)			\
 			SkPciReadCfgWord(pAC,Addr,pVal);	\
 		else						\
-			SK_IN16(pAC,PCI_C(Addr),pVal); 		\
+			SK_IN16(pAC,PCI_C(Addr),pVal);		\
 		}
 #define VPD_IN32(pAC,Ioc,Addr,pVal) {			\
 		if ((pAC)->DgT.DgUseCfgCycle)			\
diff --git a/drivers/net/sk98lin/h/xmac_ii.h b/drivers/net/sk98lin/h/xmac_ii.h
index 2ef903a87d..09e21d68a4 100644
--- a/drivers/net/sk98lin/h/xmac_ii.h
+++ b/drivers/net/sk98lin/h/xmac_ii.h
@@ -237,7 +237,7 @@ extern "C" {
 #define XM_RX_CMD		0x0030	/* 16 bit r/w	Receive Command Register */
 #define XM_PHY_ADDR		0x0034	/* 16 bit r/w	PHY Address Register */
 #define XM_PHY_DATA		0x0038	/* 16 bit r/w	PHY Data Register */
-	/* 0x003c: 		reserved */
+	/* 0x003c:		reserved */
 #define XM_GP_PORT		0x0040	/* 32 bit r/w	General Purpose Port Register */
 #define XM_IMSK			0x0044	/* 16 bit r/w	Interrupt Mask Register */
 #define XM_ISRC			0x0048	/* 16 bit r/o	Interrupt Status Register */
@@ -248,14 +248,14 @@ extern "C" {
 #define XM_TX_THR		0x0064	/* 16 bit r/w	Tx Request Threshold */
 #define XM_HT_THR		0x0066	/* 16 bit r/w	Host Request Threshold */
 #define XM_PAUSE_DA		0x0068	/* NA reg r/w	Pause Destination Address */
-	/* 0x006e: 		reserved */
+	/* 0x006e:		reserved */
 #define XM_CTL_PARA		0x0070	/* 32 bit r/w	Control Parameter Register */
 #define XM_MAC_OPCODE	0x0074	/* 16 bit r/w	Opcode for MAC control frames */
 #define XM_MAC_PTIME	0x0076	/* 16 bit r/w	Pause time for MAC ctrl frames*/
 #define XM_TX_STAT		0x0078	/* 32 bit r/o	Tx Status LIFO Register */
 
 	/* 0x0080 - 0x00fc:	16 NA reg r/w	Exact Match Address Registers */
-	/* 				use the XM_EXM() macro to address */
+	/*				use the XM_EXM() macro to address */
 #define XM_EXM_START	0x0080	/* r/w	Start Address of the EXM Regs */
 
 	/*
@@ -413,7 +413,7 @@ extern "C" {
 #define XM_RX_IPG_CAP	(1<<6)	/* Bit  6	repl. type field with IPG */
 #define XM_RX_TP_MD		(1<<5)	/* Bit  5:	Enable transparent Mode */
 #define XM_RX_STRIP_FCS	(1<<4)	/* Bit  4:	Enable FCS Stripping */
-#define XM_RX_SELF_RX	(1<<3)	/* Bit  3: 	Enable Rx of own packets */
+#define XM_RX_SELF_RX	(1<<3)	/* Bit  3:	Enable Rx of own packets */
 #define XM_RX_SAM_LINE	(1<<2)	/* Bit  2: (sc)	Start utilization calculation */
 #define XM_RX_STRIP_PAD	(1<<1)	/* Bit  1:	Strip pad bytes of Rx frames */
 #define XM_RX_DIS_CEXT	(1<<0)	/* Bit  0:	Disable carrier ext. check */
@@ -510,7 +510,7 @@ extern "C" {
 									/* Bit 31..27:	reserved */
 #define XM_MD_ENA_REJ	(1L<<26)	/* Bit 26:	Enable Frame Reject */
 #define XM_MD_SPOE_E	(1L<<25)	/* Bit 25:	Send Pause on Edge */
-									/* 		extern generated */
+									/*		extern generated */
 #define XM_MD_TX_REP	(1L<<24)	/* Bit 24:	Transmit Repeater Mode */
 #define XM_MD_SPOFF_I	(1L<<23)	/* Bit 23:	Send Pause on FIFO full */
 									/*		intern generated */
@@ -548,7 +548,7 @@ extern "C" {
 								/* Bit 16..6:	reserved */
 #define XM_SC_SNP_RXC	(1<<5)	/* Bit  5: (sc)	Snap Rx Counters */
 #define XM_SC_SNP_TXC	(1<<4)	/* Bit  4: (sc)	Snap Tx Counters */
-#define XM_SC_CP_RXC	(1<<3)	/* Bit  3: 	Copy Rx Counters Continuously */
+#define XM_SC_CP_RXC	(1<<3)	/* Bit  3:	Copy Rx Counters Continuously */
 #define XM_SC_CP_TXC	(1<<2)	/* Bit  2:	Copy Tx Counters Continuously */
 #define XM_SC_CLR_RXC	(1<<1)	/* Bit  1: (sc)	Clear Rx Counters */
 #define XM_SC_CLR_TXC	(1<<0)	/* Bit  0: (sc) Clear Tx Counters */
@@ -1316,7 +1316,7 @@ extern "C" {
 #define PHY_M_PC_DIS_JABBER	(1<<0)	/* Bit  0:	Disable Jabber */
 
 #define PHY_M_PC_MDI_XMODE(x)	SHIFT5(x)
-#define PHY_M_PC_MAN_MDI	0    	/* 00 = Manual MDI configuration */
+#define PHY_M_PC_MAN_MDI	0	/* 00 = Manual MDI configuration */
 #define PHY_M_PC_MAN_MDIX	1		/* 01 = Manual MDIX configuration */
 #define PHY_M_PC_ENA_AUTO	3		/* 11 = Enable Automatic Crossover */
 
diff --git a/drivers/net/sk98lin/skge.c b/drivers/net/sk98lin/skge.c
index 61a6094230..e1d7e8720c 100644
--- a/drivers/net/sk98lin/skge.c
+++ b/drivers/net/sk98lin/skge.c
@@ -3,7 +3,7 @@
  * Name:    skge.c
  * Project:	GEnesis, PCI Gigabit Ethernet Adapter
  * Version:	$Revision: 1.46 $
- * Date:       	$Date: 2003/02/25 14:16:36 $
+ * Date:	$Date: 2003/02/25 14:16:36 $
  * Purpose:	The main driver source module
  *
  ******************************************************************************/
@@ -348,7 +348,7 @@
 #if 0
 #include	<linux/module.h>
 #include	<linux/init.h>
-#include 	<linux/proc_fs.h>
+#include	<linux/proc_fs.h>
 #endif
 #include	"h/skdrv1st.h"
 #include	"h/skdrv2nd.h"
@@ -501,7 +501,7 @@ static struct pci_device_id supported[] = {
 
 /*****************************************************************************
  *
- * 	skge_probe - find all SK-98xx adapters
+ *	skge_probe - find all SK-98xx adapters
  *
  * Description:
  *	This function scans the PCI bus for SK-98xx adapters. Resources for
@@ -646,7 +646,7 @@ int skge_probe (struct eth_device ** ret_dev)
 		dev->set_mac_address =	&SkGeSetMacAddr;
 		dev->do_ioctl =		&SkGeIoctl;
 		dev->change_mtu =	&SkGeChangeMtu;
-		dev->flags &= 		~IFF_RUNNING;
+		dev->flags &=		~IFF_RUNNING;
 #endif
 
 #ifdef SK_ZEROCOPY
@@ -793,7 +793,7 @@ int skge_probe (struct eth_device ** ret_dev)
 			dev->set_mac_address =	&SkGeSetMacAddr;
 			dev->do_ioctl =		&SkGeIoctl;
 			dev->change_mtu =	&SkGeChangeMtu;
-			dev->flags &= 		~IFF_RUNNING;
+			dev->flags &=		~IFF_RUNNING;
 #endif
 
 #ifdef SK_ZEROCOPY
@@ -857,7 +857,7 @@ int skge_probe (struct eth_device ** ret_dev)
 
 /*****************************************************************************
  *
- * 	FreeResources - release resources allocated for adapter
+ *	FreeResources - release resources allocated for adapter
  *
  * Description:
  *	This function releases the IRQ, unmaps the IO and
@@ -992,7 +992,7 @@ static int options[SK_MAX_CARD_PARAM] = {0, }; /* not used */
 
 /*****************************************************************************
  *
- * 	skge_init_module - module initialization function
+ *	skge_init_module - module initialization function
  *
  * Description:
  *	Very simple, only call skge_probe and return approriate result.
@@ -1020,7 +1020,7 @@ static int __init skge_init_module(void)
 
 /*****************************************************************************
  *
- * 	skge_cleanup_module - module unload function
+ *	skge_cleanup_module - module unload function
  *
  * Description:
  *	Disable adapter if it is still running, free resources,
@@ -1098,7 +1098,7 @@ module_exit(skge_cleanup_module);
 
 /*****************************************************************************
  *
- * 	SkGeBoardInit - do level 0 and 1 initialization
+ *	SkGeBoardInit - do level 0 and 1 initialization
  *
  * Description:
  *	This function prepares the board hardware for running. The desriptor
@@ -1262,7 +1262,7 @@ SK_BOOL	DualNet;
 
 /*****************************************************************************
  *
- * 	BoardAllocMem - allocate the memory for the descriptor rings
+ *	BoardAllocMem - allocate the memory for the descriptor rings
  *
  * Description:
  *	This function allocates the memory for all descriptor rings.
@@ -1360,7 +1360,7 @@ size_t		AllocLength;	/* length of complete descriptor area */
 
 /*****************************************************************************
  *
- * 	BoardInitMem - initiate the descriptor rings
+ *	BoardInitMem - initiate the descriptor rings
  *
  * Description:
  *	This function sets the descriptor rings up in memory.
@@ -1408,7 +1408,7 @@ int	TxDescrSize;	/* the size of a tx descriptor rounded up to alignment*/
 
 /*****************************************************************************
  *
- * 	SetupRing - create one descriptor ring
+ *	SetupRing - create one descriptor ring
  *
  * Description:
  *	This function creates one descriptor ring in the given memory area.
@@ -1477,7 +1477,7 @@ uintptr_t VNextDescr;	/* the virtual bus address of the next descriptor */
 
 /*****************************************************************************
  *
- * 	PortReInitBmu - re-initiate the descriptor rings for one port
+ *	PortReInitBmu - re-initiate the descriptor rings for one port
  *
  * Description:
  *	This function reinitializes the descriptor rings of one port
@@ -1998,7 +1998,7 @@ struct SK_NET_DEVICE	*dev)
 
 /*****************************************************************************
  *
- * 	SkGeXmit - Linux frame transmit function
+ *	SkGeXmit - Linux frame transmit function
  *
  * Description:
  *	The system calls this function to send frames onto the wire.
@@ -2078,7 +2078,7 @@ int			Rc;	/* return code of XmitFrame */
 
 /*****************************************************************************
  *
- * 	XmitFrame - fill one socket buffer into the transmit ring
+ *	XmitFrame - fill one socket buffer into the transmit ring
  *
  * Description:
  *	This function puts a message into the transmit descriptor ring
@@ -2099,7 +2099,7 @@ int			Rc;	/* return code of XmitFrame */
  *	< 0 - on failure: other problems ( -> return failure to upper layers)
  */
 static int XmitFrame(
-SK_AC 		*pAC,		/* pointer to adapter context */
+SK_AC		*pAC,		/* pointer to adapter context */
 TX_PORT		*pTxPort,	/* pointer to struct of port to send to */
 struct sk_buff	*pMessage)	/* pointer to send-message */
 {
@@ -2186,7 +2186,7 @@ int		BytesSend;
 
 /*****************************************************************************
  *
- * 	XmitFrameSG - fill one socket buffer into the transmit ring
+ *	XmitFrameSG - fill one socket buffer into the transmit ring
  *                (use SG and TCP/UDP hardware checksumming)
  *
  * Description:
@@ -2201,12 +2201,12 @@ int		BytesSend;
  */
 #if 0
 static int XmitFrameSG(
-SK_AC 		*pAC,			/* pointer to adapter context */
+SK_AC		*pAC,			/* pointer to adapter context */
 TX_PORT		*pTxPort,		/* pointer to struct of port to send to */
 struct sk_buff	*pMessage)	/* pointer to send-message */
 {
 
-	int 		i;
+	int		i;
 	int			BytesSend;
 	int			hlength;
 	int			protocol;
@@ -2374,7 +2374,7 @@ void dump_frag( SK_U8 *data, int length)
 
 /*****************************************************************************
  *
- * 	FreeTxDescriptors - release descriptors from the descriptor ring
+ *	FreeTxDescriptors - release descriptors from the descriptor ring
  *
  * Description:
  *	This function releases descriptors from a transmit ring if they
@@ -2444,7 +2444,7 @@ SK_U64	PhysAddr;	/* address of DMA mapping */
 
 /*****************************************************************************
  *
- * 	FillRxRing - fill the receive ring with valid descriptors
+ *	FillRxRing - fill the receive ring with valid descriptors
  *
  * Description:
  *	This function fills the receive ring descriptors with data
@@ -2476,7 +2476,7 @@ unsigned long	Flags;
 
 /*****************************************************************************
  *
- * 	FillRxDescriptor - fill one buffer into the receive ring
+ *	FillRxDescriptor - fill one buffer into the receive ring
  *
  * Description:
  *	The function allocates a new receive buffer and
@@ -2532,7 +2532,7 @@ SK_U64		PhysAddr;	/* physical address of a rx buffer */
 
 /*****************************************************************************
  *
- * 	ReQueueRxBuffer - fill one buffer back into the receive ring
+ *	ReQueueRxBuffer - fill one buffer back into the receive ring
  *
  * Description:
  *	Fill a given buffer back into the rx ring. The buffer
@@ -2566,7 +2566,7 @@ SK_U16		Length;		/* data fragment length */
 
 /*****************************************************************************
  *
- * 	ReceiveIrq - handle a receive IRQ
+ *	ReceiveIrq - handle a receive IRQ
  *
  * Description:
  *	This function is called when a receive IRQ is set.
@@ -2598,7 +2598,7 @@ unsigned int	NumBytes;
 unsigned int	ForRlmt;
 SK_BOOL			IsBc;
 SK_BOOL			IsMc;
-SK_BOOL  IsBadFrame; 			/* Bad frame */
+SK_BOOL  IsBadFrame;			/* Bad frame */
 
 SK_U32			FrameStat;
 unsigned short	Csum1;
@@ -2935,7 +2935,7 @@ rx_failed:
 
 /*****************************************************************************
  *
- * 	ClearAndStartRx - give a start receive command to BMU, clear IRQ
+ *	ClearAndStartRx - give a start receive command to BMU, clear IRQ
  *
  * Description:
  *	This function sends a start command and a clear interrupt
@@ -2955,7 +2955,7 @@ int	PortIndex)	/* index of the receive port (XMAC) */
 
 /*****************************************************************************
  *
- * 	ClearTxIrq - give a clear transmit IRQ command to BMU
+ *	ClearTxIrq - give a clear transmit IRQ command to BMU
  *
  * Description:
  *	This function sends a clear tx IRQ command for one
@@ -2975,7 +2975,7 @@ int	Prio)		/* priority or normal queue */
 
 /*****************************************************************************
  *
- * 	ClearRxRing - remove all buffers from the receive ring
+ *	ClearRxRing - remove all buffers from the receive ring
  *
  * Description:
  *	This function removes all receive buffers from the ring.
@@ -3052,7 +3052,7 @@ unsigned long	Flags;
 #if 0
 /*****************************************************************************
  *
- * 	SetQueueSizes - configure the sizes of rx and tx queues
+ *	SetQueueSizes - configure the sizes of rx and tx queues
  *
  * Description:
  *	This function assigns the sizes for active and passive port
@@ -3145,7 +3145,7 @@ if (pAC->RlmtNets == 1) {
 
 /*****************************************************************************
  *
- * 	SkGeSetMacAddr - Set the hardware MAC address
+ *	SkGeSetMacAddr - Set the hardware MAC address
  *
  * Description:
  *	This function sets the MAC address used by the adapter.
@@ -3188,7 +3188,7 @@ unsigned long	Flags;
 
 /*****************************************************************************
  *
- * 	SkGeSetRxMode - set receive mode
+ *	SkGeSetRxMode - set receive mode
  *
  * Description:
  *	This function sets the receive mode of an adapter. The adapter
@@ -3264,7 +3264,7 @@ unsigned long		Flags;
 
 /*****************************************************************************
  *
- * 	SkGeChangeMtu - set the MTU to another value
+ *	SkGeChangeMtu - set the MTU to another value
  *
  * Description:
  *	This function sets is called whenever the MTU size is changed
@@ -3282,7 +3282,7 @@ DEV_NET		*pOtherNet;
 SK_AC		*pAC;
 unsigned long	Flags;
 int		i;
-SK_EVPARA 	EvPara;
+SK_EVPARA	EvPara;
 
 	SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
 		("SkGeChangeMtu starts now...\n"));
@@ -3487,7 +3487,7 @@ SK_EVPARA 	EvPara;
 
 /*****************************************************************************
  *
- * 	SkGeStats - return ethernet device statistics
+ *	SkGeStats - return ethernet device statistics
  *
  * Description:
  *	This function return statistic data about the ethernet device
@@ -3560,7 +3560,7 @@ unsigned long	Flags;			/* for spin lock */
 
 /*****************************************************************************
  *
- * 	SkGeIoctl - IO-control function
+ *	SkGeIoctl - IO-control function
  *
  * Description:
  *	This function is called if an ioctl is issued on the device.
@@ -3619,7 +3619,7 @@ int		Size;
 
 /*****************************************************************************
  *
- * 	SkGeIocMib - handle a GetMib, SetMib- or PresetMib-ioctl message
+ *	SkGeIocMib - handle a GetMib, SetMib- or PresetMib-ioctl message
  *
  * Description:
  *	This function reads/writes the MIB data using PNMI (Private Network
@@ -3673,7 +3673,7 @@ SK_AC		*pAC;
 
 /*****************************************************************************
  *
- * 	GetConfiguration - read configuration information
+ *	GetConfiguration - read configuration information
  *
  * Description:
  *	This function reads per-adapter configuration information from
@@ -3717,7 +3717,7 @@ int	Capabilities[3][3] =
 
 	/* settings for port A */
 	/* settings link speed */
-	LinkSpeed = SK_LSPEED_AUTO; 	/* default: do auto select */
+	LinkSpeed = SK_LSPEED_AUTO;	/* default: do auto select */
 	if (Speed_A != NULL && pAC->Index<SK_MAX_CARD_PARAM &&
 		Speed_A[pAC->Index] != NULL) {
 		if (strcmp(Speed_A[pAC->Index],"")==0) {
@@ -3876,7 +3876,7 @@ int	Capabilities[3][3] =
 
 	/* settings for port B */
 	/* settings link speed */
-	LinkSpeed = SK_LSPEED_AUTO; 	/* default: do auto select */
+	LinkSpeed = SK_LSPEED_AUTO;	/* default: do auto select */
 	if (Speed_B != NULL && pAC->Index<SK_MAX_CARD_PARAM &&
 		Speed_B[pAC->Index] != NULL) {
 		if (strcmp(Speed_B[pAC->Index],"")==0) {
@@ -4100,7 +4100,7 @@ int	Capabilities[3][3] =
 
 /*****************************************************************************
  *
- * 	ProductStr - return a adapter identification string from vpd
+ *	ProductStr - return a adapter identification string from vpd
  *
  * Description:
  *	This function reads the product name string from the vpd area
diff --git a/drivers/net/sk98lin/skgeinit.c b/drivers/net/sk98lin/skgeinit.c
index a18dc0a488..e49685bb9c 100644
--- a/drivers/net/sk98lin/skgeinit.c
+++ b/drivers/net/sk98lin/skgeinit.c
@@ -585,7 +585,7 @@ int		Mode)		/* Mode may be SK_LED_DIS, SK_LED_ENA, SK_LED_TST */
  *	1:	configuration error
  */
 static int DoCalcAddr(
-SK_AC		*pAC, 			/* adapter context */
+SK_AC		*pAC,			/* adapter context */
 SK_GEPORT	*pPrt,			/* port index */
 int			QuSize,			/* size of the queue to configure in kB */
 SK_U32		*StartVal,		/* start value for address calculation */
@@ -1263,9 +1263,8 @@ int		Port)		/* Port Index (MAC_1 + n) */
 	pPrt = &pAC->GIni.GP[Port];
 
 	if (pPrt->PRxQSize == SK_MIN_RXQ_SIZE) {
-		RxQType = SK_RX_SRAM_Q; 	/* small Rx Queue */
-	}
-	else {
+		RxQType = SK_RX_SRAM_Q;		/* small Rx Queue */
+	} else {
 		RxQType = SK_RX_BRAM_Q;		/* big Rx Queue */
 	}
 
@@ -1354,7 +1353,7 @@ int		Port)		/* Port Index (MAC_1 + n) */
 
 	/*
 	 * Tx Queue: Release all local resets if the queue is used !
-	 * 		set watermark
+	 *		set watermark
 	 */
 	if (pPrt->PXSQSize != 0) {
 		SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), CSR_CLR_RESET);
@@ -1416,7 +1415,7 @@ int		QuIoOffs)	/* Queue IO Address Offset */
  *	It is possible to stop the receive and transmit path separate or
  *	both together.
  *
- *	Dir =	SK_STOP_TX 	Stops the transmit path only and resets the MAC.
+ *	Dir =	SK_STOP_TX	Stops the transmit path only and resets the MAC.
  *				The receive queue is still active and
  *				the pending Rx frames may be still transferred
  *				into the RxD.
diff --git a/drivers/net/sk98lin/skgepnmi.c b/drivers/net/sk98lin/skgepnmi.c
index b5d32b04c1..16fa3523ab 100644
--- a/drivers/net/sk98lin/skgepnmi.c
+++ b/drivers/net/sk98lin/skgepnmi.c
@@ -537,70 +537,70 @@ PNMI_STATIC void CheckVctStatus(SK_AC *, SK_IOC, char *, SK_U32, SK_U32);
  * mask returned by the pFnMacOverflow function
  */
 PNMI_STATIC const SK_U16 StatOvrflwBit[][SK_PNMI_MAC_TYPES] = {
-/* Bit0  */	{ SK_PNMI_HTX, 				SK_PNMI_HTX_UNICAST},
-/* Bit1  */	{ SK_PNMI_HTX_OCTETHIGH, 	SK_PNMI_HTX_BROADCAST},
-/* Bit2  */	{ SK_PNMI_HTX_OCTETLOW, 	SK_PNMI_HTX_PMACC},
-/* Bit3  */	{ SK_PNMI_HTX_BROADCAST, 	SK_PNMI_HTX_MULTICAST},
-/* Bit4  */	{ SK_PNMI_HTX_MULTICAST, 	SK_PNMI_HTX_OCTETLOW},
-/* Bit5  */	{ SK_PNMI_HTX_UNICAST, 		SK_PNMI_HTX_OCTETHIGH},
-/* Bit6  */	{ SK_PNMI_HTX_LONGFRAMES, 	SK_PNMI_HTX_64},
-/* Bit7  */	{ SK_PNMI_HTX_BURST, 		SK_PNMI_HTX_127},
-/* Bit8  */	{ SK_PNMI_HTX_PMACC, 		SK_PNMI_HTX_255},
-/* Bit9  */	{ SK_PNMI_HTX_MACC, 		SK_PNMI_HTX_511},
-/* Bit10 */	{ SK_PNMI_HTX_SINGLE_COL, 	SK_PNMI_HTX_1023},
-/* Bit11 */	{ SK_PNMI_HTX_MULTI_COL, 	SK_PNMI_HTX_MAX},
-/* Bit12 */	{ SK_PNMI_HTX_EXCESS_COL, 	SK_PNMI_HTX_LONGFRAMES},
-/* Bit13 */	{ SK_PNMI_HTX_LATE_COL, 	SK_PNMI_HTX_RESERVED},
-/* Bit14 */	{ SK_PNMI_HTX_DEFFERAL, 	SK_PNMI_HTX_COL},
-/* Bit15 */	{ SK_PNMI_HTX_EXCESS_DEF, 	SK_PNMI_HTX_LATE_COL},
-/* Bit16 */	{ SK_PNMI_HTX_UNDERRUN, 	SK_PNMI_HTX_EXCESS_COL},
-/* Bit17 */	{ SK_PNMI_HTX_CARRIER, 		SK_PNMI_HTX_MULTI_COL},
-/* Bit18 */	{ SK_PNMI_HTX_UTILUNDER, 	SK_PNMI_HTX_SINGLE_COL},
-/* Bit19 */	{ SK_PNMI_HTX_UTILOVER, 	SK_PNMI_HTX_UNDERRUN},
-/* Bit20 */	{ SK_PNMI_HTX_64, 			SK_PNMI_HTX_RESERVED},
-/* Bit21 */	{ SK_PNMI_HTX_127, 			SK_PNMI_HTX_RESERVED},
-/* Bit22 */	{ SK_PNMI_HTX_255, 			SK_PNMI_HTX_RESERVED},
-/* Bit23 */	{ SK_PNMI_HTX_511, 			SK_PNMI_HTX_RESERVED},
-/* Bit24 */	{ SK_PNMI_HTX_1023, 		SK_PNMI_HTX_RESERVED},
-/* Bit25 */	{ SK_PNMI_HTX_MAX, 			SK_PNMI_HTX_RESERVED},
-/* Bit26 */	{ SK_PNMI_HTX_RESERVED, 	SK_PNMI_HTX_RESERVED},
-/* Bit27 */	{ SK_PNMI_HTX_RESERVED, 	SK_PNMI_HTX_RESERVED},
-/* Bit28 */	{ SK_PNMI_HTX_RESERVED, 	SK_PNMI_HTX_RESERVED},
-/* Bit29 */	{ SK_PNMI_HTX_RESERVED, 	SK_PNMI_HTX_RESERVED},
-/* Bit30 */	{ SK_PNMI_HTX_RESERVED, 	SK_PNMI_HTX_RESERVED},
-/* Bit31 */	{ SK_PNMI_HTX_RESERVED, 	SK_PNMI_HTX_RESERVED},
-/* Bit32 */	{ SK_PNMI_HRX, 				SK_PNMI_HRX_UNICAST},
-/* Bit33 */	{ SK_PNMI_HRX_OCTETHIGH, 	SK_PNMI_HRX_BROADCAST},
-/* Bit34 */	{ SK_PNMI_HRX_OCTETLOW, 	SK_PNMI_HRX_PMACC},
-/* Bit35 */	{ SK_PNMI_HRX_BROADCAST, 	SK_PNMI_HRX_MULTICAST},
-/* Bit36 */	{ SK_PNMI_HRX_MULTICAST, 	SK_PNMI_HRX_FCS},
-/* Bit37 */	{ SK_PNMI_HRX_UNICAST, 		SK_PNMI_HRX_RESERVED},
-/* Bit38 */	{ SK_PNMI_HRX_PMACC, 		SK_PNMI_HRX_OCTETLOW},
-/* Bit39 */	{ SK_PNMI_HRX_MACC, 		SK_PNMI_HRX_OCTETHIGH},
-/* Bit40 */	{ SK_PNMI_HRX_PMACC_ERR, 	SK_PNMI_HRX_BADOCTETLOW},
+/* Bit0  */	{ SK_PNMI_HTX,			SK_PNMI_HTX_UNICAST},
+/* Bit1  */	{ SK_PNMI_HTX_OCTETHIGH,	SK_PNMI_HTX_BROADCAST},
+/* Bit2  */	{ SK_PNMI_HTX_OCTETLOW,		SK_PNMI_HTX_PMACC},
+/* Bit3  */	{ SK_PNMI_HTX_BROADCAST,	SK_PNMI_HTX_MULTICAST},
+/* Bit4  */	{ SK_PNMI_HTX_MULTICAST,	SK_PNMI_HTX_OCTETLOW},
+/* Bit5  */	{ SK_PNMI_HTX_UNICAST,		SK_PNMI_HTX_OCTETHIGH},
+/* Bit6  */	{ SK_PNMI_HTX_LONGFRAMES,	SK_PNMI_HTX_64},
+/* Bit7  */	{ SK_PNMI_HTX_BURST,		SK_PNMI_HTX_127},
+/* Bit8  */	{ SK_PNMI_HTX_PMACC,		SK_PNMI_HTX_255},
+/* Bit9  */	{ SK_PNMI_HTX_MACC,		SK_PNMI_HTX_511},
+/* Bit10 */	{ SK_PNMI_HTX_SINGLE_COL,	SK_PNMI_HTX_1023},
+/* Bit11 */	{ SK_PNMI_HTX_MULTI_COL,	SK_PNMI_HTX_MAX},
+/* Bit12 */	{ SK_PNMI_HTX_EXCESS_COL,	SK_PNMI_HTX_LONGFRAMES},
+/* Bit13 */	{ SK_PNMI_HTX_LATE_COL,		SK_PNMI_HTX_RESERVED},
+/* Bit14 */	{ SK_PNMI_HTX_DEFFERAL,		SK_PNMI_HTX_COL},
+/* Bit15 */	{ SK_PNMI_HTX_EXCESS_DEF,	SK_PNMI_HTX_LATE_COL},
+/* Bit16 */	{ SK_PNMI_HTX_UNDERRUN,		SK_PNMI_HTX_EXCESS_COL},
+/* Bit17 */	{ SK_PNMI_HTX_CARRIER,		SK_PNMI_HTX_MULTI_COL},
+/* Bit18 */	{ SK_PNMI_HTX_UTILUNDER,	SK_PNMI_HTX_SINGLE_COL},
+/* Bit19 */	{ SK_PNMI_HTX_UTILOVER,		SK_PNMI_HTX_UNDERRUN},
+/* Bit20 */	{ SK_PNMI_HTX_64,		SK_PNMI_HTX_RESERVED},
+/* Bit21 */	{ SK_PNMI_HTX_127,		SK_PNMI_HTX_RESERVED},
+/* Bit22 */	{ SK_PNMI_HTX_255,		SK_PNMI_HTX_RESERVED},
+/* Bit23 */	{ SK_PNMI_HTX_511,		SK_PNMI_HTX_RESERVED},
+/* Bit24 */	{ SK_PNMI_HTX_1023,		SK_PNMI_HTX_RESERVED},
+/* Bit25 */	{ SK_PNMI_HTX_MAX,		SK_PNMI_HTX_RESERVED},
+/* Bit26 */	{ SK_PNMI_HTX_RESERVED,		SK_PNMI_HTX_RESERVED},
+/* Bit27 */	{ SK_PNMI_HTX_RESERVED,		SK_PNMI_HTX_RESERVED},
+/* Bit28 */	{ SK_PNMI_HTX_RESERVED,		SK_PNMI_HTX_RESERVED},
+/* Bit29 */	{ SK_PNMI_HTX_RESERVED,		SK_PNMI_HTX_RESERVED},
+/* Bit30 */	{ SK_PNMI_HTX_RESERVED,		SK_PNMI_HTX_RESERVED},
+/* Bit31 */	{ SK_PNMI_HTX_RESERVED,		SK_PNMI_HTX_RESERVED},
+/* Bit32 */	{ SK_PNMI_HRX,			SK_PNMI_HRX_UNICAST},
+/* Bit33 */	{ SK_PNMI_HRX_OCTETHIGH,	SK_PNMI_HRX_BROADCAST},
+/* Bit34 */	{ SK_PNMI_HRX_OCTETLOW,		SK_PNMI_HRX_PMACC},
+/* Bit35 */	{ SK_PNMI_HRX_BROADCAST,	SK_PNMI_HRX_MULTICAST},
+/* Bit36 */	{ SK_PNMI_HRX_MULTICAST,	SK_PNMI_HRX_FCS},
+/* Bit37 */	{ SK_PNMI_HRX_UNICAST,		SK_PNMI_HRX_RESERVED},
+/* Bit38 */	{ SK_PNMI_HRX_PMACC,		SK_PNMI_HRX_OCTETLOW},
+/* Bit39 */	{ SK_PNMI_HRX_MACC,		SK_PNMI_HRX_OCTETHIGH},
+/* Bit40 */	{ SK_PNMI_HRX_PMACC_ERR,	SK_PNMI_HRX_BADOCTETLOW},
 /* Bit41 */	{ SK_PNMI_HRX_MACC_UNKWN,	SK_PNMI_HRX_BADOCTETHIGH},
-/* Bit42 */	{ SK_PNMI_HRX_BURST, 		SK_PNMI_HRX_UNDERSIZE},
-/* Bit43 */	{ SK_PNMI_HRX_MISSED, 		SK_PNMI_HRX_RUNT},
-/* Bit44 */	{ SK_PNMI_HRX_FRAMING, 		SK_PNMI_HRX_64},
-/* Bit45 */	{ SK_PNMI_HRX_OVERFLOW, 	SK_PNMI_HRX_127},
-/* Bit46 */	{ SK_PNMI_HRX_JABBER, 		SK_PNMI_HRX_255},
-/* Bit47 */	{ SK_PNMI_HRX_CARRIER, 		SK_PNMI_HRX_511},
-/* Bit48 */	{ SK_PNMI_HRX_IRLENGTH, 	SK_PNMI_HRX_1023},
-/* Bit49 */	{ SK_PNMI_HRX_SYMBOL, 		SK_PNMI_HRX_MAX},
-/* Bit50 */	{ SK_PNMI_HRX_SHORTS, 		SK_PNMI_HRX_LONGFRAMES},
-/* Bit51 */	{ SK_PNMI_HRX_RUNT, 		SK_PNMI_HRX_TOO_LONG},
-/* Bit52 */	{ SK_PNMI_HRX_TOO_LONG, 	SK_PNMI_HRX_JABBER},
-/* Bit53 */	{ SK_PNMI_HRX_FCS, 			SK_PNMI_HRX_RESERVED},
-/* Bit54 */	{ SK_PNMI_HRX_RESERVED, 	SK_PNMI_HRX_OVERFLOW},
-/* Bit55 */	{ SK_PNMI_HRX_CEXT, 		SK_PNMI_HRX_RESERVED},
-/* Bit56 */	{ SK_PNMI_HRX_UTILUNDER, 	SK_PNMI_HRX_RESERVED},
-/* Bit57 */	{ SK_PNMI_HRX_UTILOVER, 	SK_PNMI_HRX_RESERVED},
-/* Bit58 */	{ SK_PNMI_HRX_64, 			SK_PNMI_HRX_RESERVED},
-/* Bit59 */	{ SK_PNMI_HRX_127, 			SK_PNMI_HRX_RESERVED},
-/* Bit60 */	{ SK_PNMI_HRX_255, 			SK_PNMI_HRX_RESERVED},
-/* Bit61 */	{ SK_PNMI_HRX_511, 			SK_PNMI_HRX_RESERVED},
-/* Bit62 */	{ SK_PNMI_HRX_1023, 		SK_PNMI_HRX_RESERVED},
-/* Bit63 */	{ SK_PNMI_HRX_MAX, 			SK_PNMI_HRX_RESERVED}
+/* Bit42 */	{ SK_PNMI_HRX_BURST,		SK_PNMI_HRX_UNDERSIZE},
+/* Bit43 */	{ SK_PNMI_HRX_MISSED,		SK_PNMI_HRX_RUNT},
+/* Bit44 */	{ SK_PNMI_HRX_FRAMING,		SK_PNMI_HRX_64},
+/* Bit45 */	{ SK_PNMI_HRX_OVERFLOW,		SK_PNMI_HRX_127},
+/* Bit46 */	{ SK_PNMI_HRX_JABBER,		SK_PNMI_HRX_255},
+/* Bit47 */	{ SK_PNMI_HRX_CARRIER,		SK_PNMI_HRX_511},
+/* Bit48 */	{ SK_PNMI_HRX_IRLENGTH,		SK_PNMI_HRX_1023},
+/* Bit49 */	{ SK_PNMI_HRX_SYMBOL,		SK_PNMI_HRX_MAX},
+/* Bit50 */	{ SK_PNMI_HRX_SHORTS,		SK_PNMI_HRX_LONGFRAMES},
+/* Bit51 */	{ SK_PNMI_HRX_RUNT,		SK_PNMI_HRX_TOO_LONG},
+/* Bit52 */	{ SK_PNMI_HRX_TOO_LONG,		SK_PNMI_HRX_JABBER},
+/* Bit53 */	{ SK_PNMI_HRX_FCS,		SK_PNMI_HRX_RESERVED},
+/* Bit54 */	{ SK_PNMI_HRX_RESERVED,		SK_PNMI_HRX_OVERFLOW},
+/* Bit55 */	{ SK_PNMI_HRX_CEXT,		SK_PNMI_HRX_RESERVED},
+/* Bit56 */	{ SK_PNMI_HRX_UTILUNDER,	SK_PNMI_HRX_RESERVED},
+/* Bit57 */	{ SK_PNMI_HRX_UTILOVER,		SK_PNMI_HRX_RESERVED},
+/* Bit58 */	{ SK_PNMI_HRX_64,		SK_PNMI_HRX_RESERVED},
+/* Bit59 */	{ SK_PNMI_HRX_127,		SK_PNMI_HRX_RESERVED},
+/* Bit60 */	{ SK_PNMI_HRX_255,		SK_PNMI_HRX_RESERVED},
+/* Bit61 */	{ SK_PNMI_HRX_511,		SK_PNMI_HRX_RESERVED},
+/* Bit62 */	{ SK_PNMI_HRX_1023,		SK_PNMI_HRX_RESERVED},
+/* Bit63 */	{ SK_PNMI_HRX_MAX,		SK_PNMI_HRX_RESERVED}
 };
 
 /*
@@ -8253,7 +8253,7 @@ char		*pBuf,
 SK_U32		Offset,
 SK_U32		PhysPortIndex)
 {
-	SK_GEPORT 	*pPrt;
+	SK_GEPORT	*pPrt;
 	SK_PNMI_VCT	*pVctData;
 	SK_U32		RetCode;
 	SK_U8		LinkSpeedUsed;
diff --git a/drivers/net/sk98lin/skgesirq.c b/drivers/net/sk98lin/skgesirq.c
index e5a4f7ec10..c9763e7401 100644
--- a/drivers/net/sk98lin/skgesirq.c
+++ b/drivers/net/sk98lin/skgesirq.c
@@ -830,10 +830,10 @@ SK_U32	Istatus)	/* Interrupt status word */
 	SK_EVPARA	Para;
 	SK_U32		RegVal32;	/* Read register value */
 	SK_GEPORT	*pPrt;		/* GIni Port struct pointer */
-	unsigned 	Len;
+	unsigned	Len;
 	SK_U64		Octets;
-	SK_U16 		PhyInt;
-	SK_U16 		PhyIMsk;
+	SK_U16		PhyInt;
+	SK_U16		PhyIMsk;
 	int			i;
 
 	if ((Istatus & IS_HW_ERR) != 0) {
diff --git a/drivers/net/sk98lin/ski2c.c b/drivers/net/sk98lin/ski2c.c
index 2ab635a229..0c5d9b407e 100644
--- a/drivers/net/sk98lin/ski2c.c
+++ b/drivers/net/sk98lin/ski2c.c
@@ -281,7 +281,7 @@ static const char SysKonnectFileId[] =
 .			+-----------------+
 .			| Temperature and |
 .			| Voltage Sensor  |
-.			| 	LM80	  |
+.			|	LM80	  |
 .			+-----------------+
 .				|
 .				|
@@ -323,7 +323,7 @@ intro()
  */
 #ifndef I2C_SLOW_TIMING
 #define	T_CLK_LOW			1300L	/* clock low time in ns */
-#define	T_CLK_HIGH		 	 600L	/* clock high time in ns */
+#define	T_CLK_HIGH			 600L	/* clock high time in ns */
 #define T_DATA_IN_SETUP		 100L	/* data in Set-up Time */
 #define T_START_HOLD		 600L	/* start condition hold time */
 #define T_START_SETUP		 600L	/* start condition Set-up time */
diff --git a/drivers/net/sk98lin/sklm80.c b/drivers/net/sk98lin/sklm80.c
index 687572b1d2..0229877b59 100644
--- a/drivers/net/sk98lin/sklm80.c
+++ b/drivers/net/sk98lin/sklm80.c
@@ -122,7 +122,7 @@ static const char SysKonnectFileId[] =
 /*
  * read the register 'Reg' from the device 'Dev'
  *
- * return 	read error	-1
+ * return	read error	-1
  *		success		the read value
  */
 int	SkLm80RcvReg(
diff --git a/drivers/net/sk98lin/skproc.c b/drivers/net/sk98lin/skproc.c
index 4e340730e5..94a6a564ac 100644
--- a/drivers/net/sk98lin/skproc.c
+++ b/drivers/net/sk98lin/skproc.c
@@ -86,21 +86,20 @@
 #define SPECIALX	32		/* 0x */
 #define LARGE		64
 
-extern SK_AC				*pACList;
-extern struct net_device 	*SkGeRootDev;
+extern SK_AC *pACList;
+extern struct net_device *SkGeRootDev;
 
-extern char * SkNumber(
-	char * str,
-	long long num,
-	int base,
-	int size,
-	int precision,
-	int type);
+extern char *SkNumber (char *str,
+		       long long num,
+		       int base,
+		       int size,
+		       int precision,
+		       int type);
 
 
 /*****************************************************************************
  *
- * 	proc_read - print "summaries" entry
+ *	proc_read - print "summaries" entry
  *
  * Description:
  *  This function fills the proc entry with statistic data about
@@ -120,16 +119,16 @@ void *data)
 	int len = 0;
 	int t;
 	int i;
-	DEV_NET					*pNet;
-	SK_AC					*pAC;
-	char 					test_buf[100];
-	char					sens_msg[50];
-	unsigned long			Flags;
-	unsigned int			Size;
-	struct SK_NET_DEVICE 		*next;
-	struct SK_NET_DEVICE 		*SkgeProcDev = SkGeRootDev;
-
-	SK_PNMI_STRUCT_DATA 	*pPnmiStruct;
+	DEV_NET			*pNet;
+	SK_AC			*pAC;
+	char			test_buf[100];
+	char			sens_msg[50];
+	unsigned long		Flags;
+	unsigned int		Size;
+	struct SK_NET_DEVICE	*next;
+	struct SK_NET_DEVICE	*SkgeProcDev = SkGeRootDev;
+
+	SK_PNMI_STRUCT_DATA	*pPnmiStruct;
 	SK_PNMI_STAT		*pPnmiStat;
 	struct proc_dir_entry *file = (struct proc_dir_entry*) data;
 
@@ -393,31 +392,31 @@ void *data)
  */
 static long SkDoDiv (long long Dividend, int Divisor, long long *pErg)
 {
- long   	Rest;
- long long 	Ergebnis;
- long   	Akku;
+	long Rest;
+	long long Ergebnis;
+	long Akku;
 
 
- Akku  = Dividend >> 32;
+	Akku = Dividend >> 32;
 
- Ergebnis = ((long long) (Akku / Divisor)) << 32;
- Rest = Akku % Divisor ;
+	Ergebnis = ((long long) (Akku / Divisor)) << 32;
+	Rest = Akku % Divisor;
 
- Akku = Rest << 16;
- Akku |= ((Dividend & 0xFFFF0000) >> 16);
+	Akku = Rest << 16;
+	Akku |= ((Dividend & 0xFFFF0000) >> 16);
 
 
- Ergebnis += ((long long) (Akku / Divisor)) << 16;
- Rest = Akku % Divisor ;
+	Ergebnis += ((long long) (Akku / Divisor)) << 16;
+	Rest = Akku % Divisor;
 
- Akku = Rest << 16;
- Akku |= (Dividend & 0xFFFF);
+	Akku = Rest << 16;
+	Akku |= (Dividend & 0xFFFF);
 
- Ergebnis += (Akku / Divisor);
- Rest = Akku % Divisor ;
+	Ergebnis += (Akku / Divisor);
+	Rest = Akku % Divisor;
 
- *pErg = Ergebnis;
- return (Rest);
+	*pErg = Ergebnis;
+	return (Rest);
 }
 
 
diff --git a/drivers/net/sk98lin/skrlmt.c b/drivers/net/sk98lin/skrlmt.c
index f8a3b41f0f..14a6f40d8b 100644
--- a/drivers/net/sk98lin/skrlmt.c
+++ b/drivers/net/sk98lin/skrlmt.c
@@ -350,7 +350,7 @@ extern "C" {
 /* ----- Private RLMT defaults ----- */
 
 #define SK_RLMT_DEF_PREF_PORT	0					/* "Lower" port. */
-#define SK_RLMT_DEF_MODE 		SK_RLMT_CHECK_LINK	/* Default RLMT Mode. */
+#define SK_RLMT_DEF_MODE		SK_RLMT_CHECK_LINK	/* Default RLMT Mode. */
 
 /* ----- Private RLMT checking states ----- */
 
@@ -530,7 +530,7 @@ typedef struct s_SpTreeRlmtPacket {
 
 SK_MAC_ADDR	SkRlmtMcAddr =	{{0x01,  0x00,  0x5A,  0x52,  0x4C,  0x4D}};
 SK_MAC_ADDR	BridgeMcAddr =	{{0x01,  0x80,  0xC2,  0x00,  0x00,  0x00}};
-SK_MAC_ADDR	BcAddr = 		{{0xFF,  0xFF,  0xFF,  0xFF,  0xFF,  0xFF}};
+SK_MAC_ADDR	BcAddr =		{{0xFF,  0xFF,  0xFF,  0xFF,  0xFF,  0xFF}};
 
 /* local variables ************************************************************/
 
diff --git a/drivers/net/sk98lin/skvpd.c b/drivers/net/sk98lin/skvpd.c
index 3b81e67df8..429da8256e 100644
--- a/drivers/net/sk98lin/skvpd.c
+++ b/drivers/net/sk98lin/skvpd.c
@@ -288,10 +288,10 @@ int		addr)	/* VPD address */
 . write				1.8 ms		3.6 ms
 . internal write cyles		0.7 ms		7.0 ms
 . -------------------------------------------------------------------
-. over all program time	 	2.5 ms		10.6 ms
+. over all program time		2.5 ms		10.6 ms
 . read				1.3 ms		2.6 ms
 . -------------------------------------------------------------------
-. over all 			3.8 ms		13.2 ms
+. over all			3.8 ms		13.2 ms
 .
 
 
diff --git a/drivers/net/sk98lin/skxmac2.c b/drivers/net/sk98lin/skxmac2.c
index e6b5a95d4a..794600054a 100644
--- a/drivers/net/sk98lin/skxmac2.c
+++ b/drivers/net/sk98lin/skxmac2.c
@@ -1247,7 +1247,7 @@ int		Port)	/* Port Index (MAC_1 + n) */
  *  (Timing requirements: Broadcom: 400ns, Level One: none, National: 80ns).
  *
  * ATTENTION:
- * 	It is absolutely necessary to reset the SW_RST Bit first
+ *	It is absolutely necessary to reset the SW_RST Bit first
  *	before calling this function.
  *
  * Returns:
@@ -1351,7 +1351,7 @@ int		Port)	/* Port Index (MAC_1 + n) */
  * Description:
  *
  * ATTENTION:
- * 	It is absolutely necessary to reset the SW_RST Bit first
+ *	It is absolutely necessary to reset the SW_RST Bit first
  *	before calling this function.
  *
  * Returns:
@@ -1919,7 +1919,7 @@ int		Port)		/* Port Index (MAC_1 + n) */
 		/* Configuration Actions for Half Duplex Mode */
 		/*
 		 * XM_BURST = default value. We are probable not quick
-		 * 	enough at the 'XMAC' bus to burst 8kB.
+		 *	enough at the 'XMAC' bus to burst 8kB.
 		 *	The XMAC stops bursting if no transmit frames
 		 *	are available or the burst limit is exceeded.
 		 */
@@ -2879,8 +2879,8 @@ SK_U16	PhyStat)	/* PHY Status word to analyse */
  *
  * Returns:
  *	SK_AND_OK	o.k.
- *	SK_AND_DUP_CAP 	Duplex capability error happened
- *	SK_AND_OTHER 	Other error happened
+ *	SK_AND_DUP_CAP	Duplex capability error happened
+ *	SK_AND_OTHER	Other error happened
  */
 static int SkXmAutoNegDoneXmac(
 SK_AC	*pAC,		/* adapter context */
@@ -2962,8 +2962,8 @@ int		Port)		/* Port Index (MAC_1 + n) */
  *
  * Returns:
  *	SK_AND_OK	o.k.
- *	SK_AND_DUP_CAP 	Duplex capability error happened
- *	SK_AND_OTHER 	Other error happened
+ *	SK_AND_DUP_CAP	Duplex capability error happened
+ *	SK_AND_OTHER	Other error happened
  */
 static int SkXmAutoNegDoneBcom(
 SK_AC	*pAC,		/* adapter context */
@@ -3063,8 +3063,8 @@ int		Port)		/* Port Index (MAC_1 + n) */
  *
  * Returns:
  *	SK_AND_OK	o.k.
- *	SK_AND_DUP_CAP 	Duplex capability error happened
- *	SK_AND_OTHER 	Other error happened
+ *	SK_AND_DUP_CAP	Duplex capability error happened
+ *	SK_AND_OTHER	Other error happened
  */
 static int SkGmAutoNegDoneMarv(
 SK_AC	*pAC,		/* adapter context */
@@ -3168,8 +3168,8 @@ int		Port)		/* Port Index (MAC_1 + n) */
  *
  * Returns:
  *	SK_AND_OK	o.k.
- *	SK_AND_DUP_CAP 	Duplex capability error happened
- *	SK_AND_OTHER 	Other error happened
+ *	SK_AND_DUP_CAP	Duplex capability error happened
+ *	SK_AND_OTHER	Other error happened
  */
 static int SkXmAutoNegDoneLone(
 SK_AC	*pAC,		/* adapter context */
@@ -3273,8 +3273,8 @@ int		Port)		/* Port Index (MAC_1 + n) */
  *
  * Returns:
  *	SK_AND_OK	o.k.
- *	SK_AND_DUP_CAP 	Duplex capability error happened
- *	SK_AND_OTHER 	Other error happened
+ *	SK_AND_DUP_CAP	Duplex capability error happened
+ *	SK_AND_OTHER	Other error happened
  */
 static int SkXmAutoNegDoneNat(
 SK_AC	*pAC,		/* adapter context */
@@ -3295,8 +3295,8 @@ int		Port)		/* Port Index (MAC_1 + n) */
  *
  * Returns:
  *	SK_AND_OK	o.k.
- *	SK_AND_DUP_CAP 	Duplex capability error happened
- *	SK_AND_OTHER 	Other error happened
+ *	SK_AND_DUP_CAP	Duplex capability error happened
+ *	SK_AND_OTHER	Other error happened
  */
 int	SkMacAutoNegDone(
 SK_AC	*pAC,		/* adapter context */
@@ -4323,7 +4323,7 @@ SK_U64	*pStatus)	/* ptr for return overflow status value */
  */
 int SkGmCableDiagStatus(
 SK_AC	*pAC,		/* adapter context */
-SK_IOC	IoC,   		/* IO context */
+SK_IOC	IoC,		/* IO context */
 int		Port,		/* Port Index (MAC_1 + n) */
 SK_BOOL	StartTest)	/* flag for start / get result */
 {
diff --git a/drivers/net/smc91111.h b/drivers/net/smc91111.h
index 96ff04d369..967adddd74 100644
--- a/drivers/net/smc91111.h
+++ b/drivers/net/smc91111.h
@@ -31,7 +31,7 @@
  . information under www.smsc.com.
  .
  . Authors
- . 	Erik Stahlman				( erik@vt.edu )
+ .	Erik Stahlman				( erik@vt.edu )
  .	Daris A Nevil				( dnevil@snmc.com )
  .
  . History
@@ -56,7 +56,7 @@ void smc_set_mac_addr (const unsigned char *addr);
 
 typedef unsigned char			byte;
 typedef unsigned short			word;
-typedef unsigned long int 		dword;
+typedef unsigned long int		dword;
 
 /*
  . DEBUGGING LEVELS
@@ -77,8 +77,8 @@ typedef unsigned long int 		dword;
 #ifdef CONFIG_PXA250
 
 #ifdef CONFIG_XSENGINE
-#define	SMC_inl(r) 	(*((volatile dword *)(SMC_BASE_ADDRESS+(r<<1))))
-#define	SMC_inw(r) 	(*((volatile word *)(SMC_BASE_ADDRESS+(r<<1))))
+#define	SMC_inl(r)	(*((volatile dword *)(SMC_BASE_ADDRESS+(r<<1))))
+#define	SMC_inw(r)	(*((volatile word *)(SMC_BASE_ADDRESS+(r<<1))))
 #define SMC_inb(p)  ({ \
 	unsigned int __p = (unsigned int)(SMC_BASE_ADDRESS + (p<<1)); \
 	unsigned int __v = *(volatile unsigned short *)((__p) & ~2); \
@@ -99,8 +99,8 @@ typedef unsigned long int 		dword;
 	else ___v &= 0xff; \
 	___v; })
 #else
-#define	SMC_inl(r) 	(*((volatile dword *)(SMC_BASE_ADDRESS+(r))))
-#define	SMC_inw(r) 	(*((volatile word *)(SMC_BASE_ADDRESS+(r))))
+#define	SMC_inl(r)	(*((volatile dword *)(SMC_BASE_ADDRESS+(r))))
+#define	SMC_inw(r)	(*((volatile word *)(SMC_BASE_ADDRESS+(r))))
 #define SMC_inb(p)	({ \
 	unsigned int __p = (unsigned int)(SMC_BASE_ADDRESS + (p)); \
 	unsigned int __v = *(volatile unsigned short *)((__p) & ~1); \
@@ -149,28 +149,28 @@ typedef unsigned long int 		dword;
 					} \
 				})
 
-#define SMC_insl(r,b,l) 	({	int __i ;  \
+#define SMC_insl(r,b,l)		({	int __i ;  \
 					dword *__b2;  \
-			    		__b2 = (dword *) b;  \
-			    		for (__i = 0; __i < l; __i++) {  \
+					__b2 = (dword *) b;  \
+					for (__i = 0; __i < l; __i++) {  \
 					  *(__b2 + __i) = SMC_inl(r);  \
 					  SMC_inl(0);  \
 					};  \
 				})
 
-#define SMC_insw(r,b,l) 	({	int __i ;  \
+#define SMC_insw(r,b,l)		({	int __i ;  \
 					word *__b2;  \
-			    		__b2 = (word *) b;  \
-			    		for (__i = 0; __i < l; __i++) {  \
+					__b2 = (word *) b;  \
+					for (__i = 0; __i < l; __i++) {  \
 					  *(__b2 + __i) = SMC_inw(r);  \
 					  SMC_inw(0);  \
 					};  \
 				})
 
-#define SMC_insb(r,b,l) 	({	int __i ;  \
+#define SMC_insb(r,b,l)		({	int __i ;  \
 					byte *__b2;  \
-			    		__b2 = (byte *) b;  \
-			    		for (__i = 0; __i < l; __i++) {  \
+					__b2 = (byte *) b;  \
+					for (__i = 0; __i < l; __i++) {  \
 					  *(__b2 + __i) = SMC_inb(r);  \
 					  SMC_inb(0);  \
 					};  \
@@ -187,10 +187,10 @@ typedef unsigned long int 		dword;
        ((0x00FF0000UL & _x) >>  8) |		\
        (_x  >> 24)); })
 
-#define	SMC_inl(r) 	(SMC_LEON_SWAP32((*(volatile dword *)(SMC_BASE_ADDRESS+((r)<<0)))))
-#define	SMC_inl_nosw(r) 	((*(volatile dword *)(SMC_BASE_ADDRESS+((r)<<0))))
-#define	SMC_inw(r) 	(SMC_LEON_SWAP16((*(volatile word *)(SMC_BASE_ADDRESS+((r)<<0)))))
-#define	SMC_inw_nosw(r) 	((*(volatile word *)(SMC_BASE_ADDRESS+((r)<<0))))
+#define	SMC_inl(r)	(SMC_LEON_SWAP32((*(volatile dword *)(SMC_BASE_ADDRESS+((r)<<0)))))
+#define	SMC_inl_nosw(r)	((*(volatile dword *)(SMC_BASE_ADDRESS+((r)<<0))))
+#define	SMC_inw(r)	(SMC_LEON_SWAP16((*(volatile word *)(SMC_BASE_ADDRESS+((r)<<0)))))
+#define	SMC_inw_nosw(r)	((*(volatile word *)(SMC_BASE_ADDRESS+((r)<<0))))
 #define SMC_inb(p)	({ \
 	word ___v = SMC_inw((p) & ~1); \
 	if ((p) & 1) ___v >>= 8; \
@@ -221,7 +221,7 @@ typedef unsigned long int 		dword;
 					    SMC_outw_nosw( *(__b2 + __i), r); \
 					} \
 				}while(0)
-#define SMC_insl(r,b,l) 	do{	int __i ;  \
+#define SMC_insl(r,b,l)		do{	int __i ;  \
 					dword *__b2;  \
 					__b2 = (dword *) b;  \
 					for (__i = 0; __i < l; __i++) {  \
@@ -229,7 +229,7 @@ typedef unsigned long int 		dword;
 					};  \
 				}while(0)
 
-#define SMC_insw(r,b,l) 	do{	int __i ;  \
+#define SMC_insw(r,b,l)		do{	int __i ;  \
 					word *__b2;  \
 					__b2 = (word *) b;  \
 					for (__i = 0; __i < l; __i++) {  \
@@ -237,7 +237,7 @@ typedef unsigned long int 		dword;
 					};  \
 				}while(0)
 
-#define SMC_insb(r,b,l) 	do{	int __i ;  \
+#define SMC_insb(r,b,l)		do{	int __i ;  \
 					byte *__b2;  \
 					__b2 = (byte *) b;  \
 					for (__i = 0; __i < l; __i++) {  \
@@ -253,11 +253,11 @@ typedef unsigned long int 		dword;
  */
 
 #ifdef CONFIG_ADNPESC1
-#define	SMC_inw(r) 	(*((volatile word *)(SMC_BASE_ADDRESS+((r)<<1))))
+#define	SMC_inw(r)	(*((volatile word *)(SMC_BASE_ADDRESS+((r)<<1))))
 #elif CONFIG_BLACKFIN
-#define	SMC_inw(r) 	({ word __v = (*((volatile word *)(SMC_BASE_ADDRESS+(r)))); SSYNC(); __v;})
+#define	SMC_inw(r)	({ word __v = (*((volatile word *)(SMC_BASE_ADDRESS+(r)))); SSYNC(); __v;})
 #else
-#define	SMC_inw(r) 	(*((volatile word *)(SMC_BASE_ADDRESS+(r))))
+#define	SMC_inw(r)	(*((volatile word *)(SMC_BASE_ADDRESS+(r))))
 #endif
 #define  SMC_inb(r)	(((r)&1) ? SMC_inw((r)&~1)>>8 : SMC_inw(r)&0xFF)
 
@@ -287,12 +287,12 @@ typedef unsigned long int 		dword;
 #endif
 
 #if 0
-#define	SMC_insw(r,b,l) 	insw(SMC_BASE_ADDRESS+(r), (b), (l))
+#define	SMC_insw(r,b,l)	insw(SMC_BASE_ADDRESS+(r), (b), (l))
 #else
-#define SMC_insw(r,b,l) 	({	int __i ;  \
+#define SMC_insw(r,b,l)	({	int __i ;  \
 					word *__b2;  \
-			    		__b2 = (word *) b;  \
-			    		for (__i = 0; __i < l; __i++) {  \
+					__b2 = (word *) b;  \
+					for (__i = 0; __i < l; __i++) {  \
 					  *(__b2 + __i) = SMC_inw(r);  \
 					  SMC_inw(0);  \
 					};  \
@@ -304,15 +304,15 @@ typedef unsigned long int 		dword;
 #if defined(CONFIG_SMC_USE_32_BIT)
 
 #ifdef CONFIG_XSENGINE
-#define	SMC_inl(r) 	(*((volatile dword *)(SMC_BASE_ADDRESS+(r<<1))))
+#define	SMC_inl(r)	(*((volatile dword *)(SMC_BASE_ADDRESS+(r<<1))))
 #else
-#define	SMC_inl(r) 	(*((volatile dword *)(SMC_BASE_ADDRESS+(r))))
+#define	SMC_inl(r)	(*((volatile dword *)(SMC_BASE_ADDRESS+(r))))
 #endif
 
-#define SMC_insl(r,b,l) 	({	int __i ;  \
+#define SMC_insl(r,b,l)	({	int __i ;  \
 					dword *__b2;  \
-			    		__b2 = (dword *) b;  \
-			    		for (__i = 0; __i < l; __i++) {  \
+					__b2 = (dword *) b;  \
+					for (__i = 0; __i < l; __i++) {  \
 					  *(__b2 + __i) = SMC_inl(r);  \
 					  SMC_inl(0);  \
 					};  \
@@ -352,21 +352,21 @@ typedef unsigned long int 		dword;
  . Bank Select Register:
  .
  .		yyyy yyyy 0000 00xx
- .		xx 		= bank number
+ .		xx		= bank number
  .		yyyy yyyy	= 0x33, for identification purposes.
 */
 #define	BANK_SELECT		14
 
 /* Transmit Control Register */
 /* BANK 0  */
-#define	TCR_REG 	0x0000 	/* transmit control register */
+#define	TCR_REG		0x0000	/* transmit control register */
 #define TCR_ENABLE	0x0001	/* When 1 we can transmit */
 #define TCR_LOOP	0x0002	/* Controls output pin LBK */
 #define TCR_FORCOL	0x0004	/* When 1 will force a collision */
 #define TCR_PAD_EN	0x0080	/* When 1 will pad tx frames < 64 bytes w/0 */
 #define TCR_NOCRC	0x0100	/* When 1 will not append CRC to tx frames */
 #define TCR_MON_CSN	0x0400	/* When 1 tx monitors carrier */
-#define TCR_FDUPLX    	0x0800  /* When 1 enables full duplex operation */
+#define TCR_FDUPLX	0x0800  /* When 1 enables full duplex operation */
 #define TCR_STP_SQET	0x1000	/* When 1 stops tx if Signal Quality Error */
 #define	TCR_EPH_LOOP	0x2000	/* When 1 enables EPH block loopback */
 #define	TCR_SWFDUP	0x8000	/* When 1 enables Switched Full Duplex mode */
@@ -374,7 +374,7 @@ typedef unsigned long int 		dword;
 #define	TCR_CLEAR	0	/* do NOTHING */
 /* the default settings for the TCR register : */
 /* QUESTION: do I want to enable padding of short packets ? */
-#define	TCR_DEFAULT  	TCR_ENABLE
+#define	TCR_DEFAULT	TCR_ENABLE
 
 
 /* EPH Status Register */
@@ -406,7 +406,7 @@ typedef unsigned long int 		dword;
 #define	RCR_STRIP_CRC	0x0200	/* When set strips CRC from rx packets */
 #define	RCR_ABORT_ENB	0x0200	/* When set will abort rx on collision */
 #define	RCR_FILT_CAR	0x0400	/* When set filters leading 12 bit s of carrier */
-#define RCR_SOFTRST	0x8000 	/* resets the chip */
+#define RCR_SOFTRST	0x8000	/* resets the chip */
 
 /* the normal settings for the RCR register : */
 #define	RCR_DEFAULT	(RCR_STRIP_CRC | RCR_RXEN)
@@ -507,11 +507,11 @@ typedef unsigned long int 		dword;
 #define MMU_CMD_REG	0x0000
 #define MC_BUSY		1	/* When 1 the last release has not completed */
 #define MC_NOP		(0<<5)	/* No Op */
-#define	MC_ALLOC	(1<<5) 	/* OR with number of 256 byte packets */
+#define	MC_ALLOC	(1<<5)	/* OR with number of 256 byte packets */
 #define	MC_RESET	(2<<5)	/* Reset MMU to initial state */
-#define	MC_REMOVE	(3<<5) 	/* Remove the current rx packet */
-#define MC_RELEASE  	(4<<5) 	/* Remove and release the current rx packet */
-#define MC_FREEPKT  	(5<<5) 	/* Release packet in PNR register */
+#define	MC_REMOVE	(3<<5)	/* Remove the current rx packet */
+#define MC_RELEASE	(4<<5)	/* Remove and release the current rx packet */
+#define MC_FREEPKT	(5<<5)	/* Release packet in PNR register */
 #define MC_ENQUEUE	(6<<5)	/* Enqueue the packet for transmit */
 #define MC_RSTTXFIFO	(7<<5)	/* Reset the TX FIFOs */
 
@@ -543,7 +543,7 @@ typedef unsigned long int 		dword;
 /* BANK 2 */
 #define PTR_REG		0x0006
 #define	PTR_RCV		0x8000 /* 1=Receive area, 0=Transmit area */
-#define	PTR_AUTOINC 	0x4000 /* Auto increment the pointer on each access */
+#define	PTR_AUTOINC	0x4000 /* Auto increment the pointer on each access */
 #define PTR_READ	0x2000 /* When 1 the operation is a read */
 #define PTR_NOTEMPTY	0x0800 /* When 1 _do not_ write fifo DATA REG */
 
diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c
index c17dcf4371..5302cb5223 100644
--- a/drivers/net/smc911x.c
+++ b/drivers/net/smc911x.c
@@ -79,7 +79,7 @@ static inline void reg_write(u32 addr, u32 val)
 #define	RX_STS_MII_ERR				0x00000008
 #define	RX_STS_DRIBBLING			0x00000004
 #define	RX_STS_CRC_ERR				0x00000002
-#define RX_STATUS_FIFO_PEEK 	(CONFIG_DRIVER_SMC911X_BASE + 0x44)
+#define RX_STATUS_FIFO_PEEK	(CONFIG_DRIVER_SMC911X_BASE + 0x44)
 #define TX_STATUS_FIFO		(CONFIG_DRIVER_SMC911X_BASE + 0x48)
 #define	TX_STS_TAG				0xFFFF0000
 #define	TX_STS_ES				0x00008000
@@ -196,9 +196,9 @@ static inline void reg_write(u32 addr, u32 val)
 #define	HW_CFG_TX_FIF_SZ			0x000F0000  /* R/W */
 #define	HW_CFG_TR				0x00003000  /* R/W */
 #define	HW_CFG_PHY_CLK_SEL			0x00000060  /* R/W */
-#define	HW_CFG_PHY_CLK_SEL_INT_PHY 		0x00000000 /* R/W */
-#define	HW_CFG_PHY_CLK_SEL_EXT_PHY 		0x00000020 /* R/W */
-#define	HW_CFG_PHY_CLK_SEL_CLK_DIS 		0x00000040 /* R/W */
+#define	HW_CFG_PHY_CLK_SEL_INT_PHY		0x00000000 /* R/W */
+#define	HW_CFG_PHY_CLK_SEL_EXT_PHY		0x00000020 /* R/W */
+#define	HW_CFG_PHY_CLK_SEL_CLK_DIS		0x00000040 /* R/W */
 #define	HW_CFG_SMI_SEL				0x00000010  /* R/W */
 #define	HW_CFG_EXT_PHY_DET			0x00000008  /* RO */
 #define	HW_CFG_EXT_PHY_EN			0x00000004  /* R/W */
diff --git a/drivers/net/tigon3.h b/drivers/net/tigon3.h
index c03347fdc9..551107bc78 100644
--- a/drivers/net/tigon3.h
+++ b/drivers/net/tigon3.h
@@ -3238,7 +3238,7 @@ LM_VOID LM_MemWrInd (PLM_DEVICE_BLOCK pDevice, LM_UINT32 MemAddr,
 
 #define REG_WR_OFFSET(pDevice, Offset, Value32)                  \
 	(((Offset >=0x200 ) && (Offset < 0x400)) ||		 \
-	 ((pDevice)->EnablePciXFix == FALSE)) ?	   		 \
+	 ((pDevice)->EnablePciXFix == FALSE)) ?			 \
     (void) writel(Value32, ((LM_UINT8 *) (pDevice)->pMemView + Offset)) : \
     LM_RegWrInd(pDevice, Offset, Value32)
 
diff --git a/drivers/net/tsec.h b/drivers/net/tsec.h
index 597ea1d3c7..6a2338b46a 100644
--- a/drivers/net/tsec.h
+++ b/drivers/net/tsec.h
@@ -36,9 +36,9 @@
 
 #define MAC_ADDR_LEN 6
 
-/* #define TSEC_TIMEOUT 	1000000 */
+/* #define TSEC_TIMEOUT	1000000 */
 #define TSEC_TIMEOUT 1000
-#define TOUT_LOOP 	1000000
+#define TOUT_LOOP	1000000
 
 #define PHY_AUTONEGOTIATE_TIMEOUT	5000 /* in ms */
 
@@ -58,12 +58,12 @@
 
 #define MACCFG2_INIT_SETTINGS	0x00007205
 #define MACCFG2_FULL_DUPLEX	0x00000001
-#define MACCFG2_IF              0x00000300
+#define MACCFG2_IF		0x00000300
 #define MACCFG2_GMII		0x00000200
-#define MACCFG2_MII             0x00000100
+#define MACCFG2_MII		0x00000100
 
 #define ECNTRL_INIT_SETTINGS	0x00001000
-#define ECNTRL_TBI_MODE         0x00000020
+#define ECNTRL_TBI_MODE		0x00000020
 #define ECNTRL_R100		0x00000008
 #define ECNTRL_SGMII_MODE	0x00000002
 
@@ -76,21 +76,21 @@
 #define MIIMCFG_INIT_VALUE	0x00000003
 #define MIIMCFG_RESET		0x80000000
 
-#define MIIMIND_BUSY            0x00000001
-#define MIIMIND_NOTVALID        0x00000004
+#define MIIMIND_BUSY		0x00000001
+#define MIIMIND_NOTVALID	0x00000004
 
-#define MIIM_CONTROL            0x00
+#define MIIM_CONTROL		0x00
 #define MIIM_CONTROL_RESET	0x00009140
-#define MIIM_CONTROL_INIT       0x00001140
-#define MIIM_CONTROL_RESTART    0x00001340
-#define MIIM_ANEN               0x00001000
+#define MIIM_CONTROL_INIT	0x00001140
+#define MIIM_CONTROL_RESTART	0x00001340
+#define MIIM_ANEN		0x00001000
 
-#define MIIM_CR                 0x00
+#define MIIM_CR			0x00
 #define MIIM_CR_RST		0x00008000
-#define MIIM_CR_INIT	        0x00001000
+#define MIIM_CR_INIT		0x00001000
 
 #define MIIM_STATUS		0x1
-#define MIIM_STATUS_AN_DONE 	0x00000020
+#define MIIM_STATUS_AN_DONE	0x00000020
 #define MIIM_STATUS_LINK	0x0004
 #define PHY_BMSR_AUTN_ABLE	0x0008
 #define PHY_BMSR_AUTN_COMP	0x0020
@@ -120,16 +120,16 @@
 #define MIIM_BCM54xx_AUXSTATUS_LINKMODE_SHIFT	8
 
 /* Cicada Auxiliary Control/Status Register */
-#define MIIM_CIS8201_AUX_CONSTAT        0x1c
-#define MIIM_CIS8201_AUXCONSTAT_INIT    0x0004
-#define MIIM_CIS8201_AUXCONSTAT_DUPLEX  0x0020
-#define MIIM_CIS8201_AUXCONSTAT_SPEED   0x0018
-#define MIIM_CIS8201_AUXCONSTAT_GBIT    0x0010
-#define MIIM_CIS8201_AUXCONSTAT_100     0x0008
+#define MIIM_CIS8201_AUX_CONSTAT	0x1c
+#define MIIM_CIS8201_AUXCONSTAT_INIT	0x0004
+#define MIIM_CIS8201_AUXCONSTAT_DUPLEX	0x0020
+#define MIIM_CIS8201_AUXCONSTAT_SPEED	0x0018
+#define MIIM_CIS8201_AUXCONSTAT_GBIT	0x0010
+#define MIIM_CIS8201_AUXCONSTAT_100	0x0008
 
 /* Cicada Extended Control Register 1 */
-#define MIIM_CIS8201_EXT_CON1           0x17
-#define MIIM_CIS8201_EXTCON1_INIT       0x0000
+#define MIIM_CIS8201_EXT_CON1		0x17
+#define MIIM_CIS8201_EXTCON1_INIT	0x0000
 
 /* Cicada 8204 Extended PHY Control Register 1 */
 #define MIIM_CIS8204_EPHY_CON		0x17
@@ -145,21 +145,21 @@
 
 /* Entry for Vitesse VSC8244 regs starts here */
 /* Vitesse VSC8244 Auxiliary Control/Status Register */
-#define MIIM_VSC8244_AUX_CONSTAT        0x1c
-#define MIIM_VSC8244_AUXCONSTAT_INIT    0x0000
-#define MIIM_VSC8244_AUXCONSTAT_DUPLEX  0x0020
-#define MIIM_VSC8244_AUXCONSTAT_SPEED   0x0018
-#define MIIM_VSC8244_AUXCONSTAT_GBIT    0x0010
-#define MIIM_VSC8244_AUXCONSTAT_100     0x0008
-#define MIIM_CONTROL_INIT_LOOPBACK      0x4000
+#define MIIM_VSC8244_AUX_CONSTAT	0x1c
+#define MIIM_VSC8244_AUXCONSTAT_INIT	0x0000
+#define MIIM_VSC8244_AUXCONSTAT_DUPLEX	0x0020
+#define MIIM_VSC8244_AUXCONSTAT_SPEED	0x0018
+#define MIIM_VSC8244_AUXCONSTAT_GBIT	0x0010
+#define MIIM_VSC8244_AUXCONSTAT_100	0x0008
+#define MIIM_CONTROL_INIT_LOOPBACK	0x4000
 
 /* Vitesse VSC8244 Extended PHY Control Register 1 */
-#define MIIM_VSC8244_EPHY_CON           0x17
-#define MIIM_VSC8244_EPHYCON_INIT       0x0006
+#define MIIM_VSC8244_EPHY_CON		0x17
+#define MIIM_VSC8244_EPHYCON_INIT	0x0006
 
 /* Vitesse VSC8244 Serial LED Control Register */
-#define MIIM_VSC8244_LED_CON            0x1b
-#define MIIM_VSC8244_LEDCON_INIT        0xF011
+#define MIIM_VSC8244_LED_CON		0x1b
+#define MIIM_VSC8244_LEDCON_INIT	0xF011
 
 /* Entry for Vitesse VSC8601 regs starts here (Not complete) */
 /* Vitesse VSC8601 Extended PHY Control Register 1 */
@@ -168,11 +168,11 @@
 #define MIIM_VSC8601_SKEW_CTRL		0x1c
 
 /* 88E1011 PHY Status Register */
-#define MIIM_88E1011_PHY_STATUS         0x11
-#define MIIM_88E1011_PHYSTAT_SPEED      0xc000
-#define MIIM_88E1011_PHYSTAT_GBIT       0x8000
-#define MIIM_88E1011_PHYSTAT_100        0x4000
-#define MIIM_88E1011_PHYSTAT_DUPLEX     0x2000
+#define MIIM_88E1011_PHY_STATUS		0x11
+#define MIIM_88E1011_PHYSTAT_SPEED	0xc000
+#define MIIM_88E1011_PHYSTAT_GBIT	0x8000
+#define MIIM_88E1011_PHYSTAT_100	0x4000
+#define MIIM_88E1011_PHYSTAT_DUPLEX	0x2000
 #define MIIM_88E1011_PHYSTAT_SPDDONE	0x0800
 #define MIIM_88E1011_PHYSTAT_LINK	0x0400
 
@@ -189,7 +189,7 @@
 #define MIIM_M88E1145_RGMII_RX_DELAY	0x0080
 #define MIIM_M88E1145_RGMII_TX_DELAY	0x0002
 
-#define MIIM_88E1145_PHY_PAGE   29
+#define MIIM_88E1145_PHY_PAGE	29
 #define MIIM_88E1145_PHY_CAL_OV 30
 
 /* RTL8211B PHY Status Register */
@@ -220,12 +220,12 @@
 #define MIIM_DM9161_10BTCSR_INIT	0x7800
 
 /* LXT971 Status 2 registers */
-#define MIIM_LXT971_SR2              0x11  /* Status Register 2  */
+#define MIIM_LXT971_SR2		     0x11  /* Status Register 2  */
 #define MIIM_LXT971_SR2_SPEED_MASK 0x4200
-#define MIIM_LXT971_SR2_10HDX      0x0000  /*  10 Mbit half duplex selected */
-#define MIIM_LXT971_SR2_10FDX      0x0200  /*  10 Mbit full duplex selected */
-#define MIIM_LXT971_SR2_100HDX     0x4000  /* 100 Mbit half duplex selected */
-#define MIIM_LXT971_SR2_100FDX     0x4200  /* 100 Mbit full duplex selected */
+#define MIIM_LXT971_SR2_10HDX	   0x0000  /*  10 Mbit half duplex selected */
+#define MIIM_LXT971_SR2_10FDX	   0x0200  /*  10 Mbit full duplex selected */
+#define MIIM_LXT971_SR2_100HDX	   0x4000  /* 100 Mbit half duplex selected */
+#define MIIM_LXT971_SR2_100FDX	   0x4200  /* 100 Mbit full duplex selected */
 
 /* DP83865 Control register values */
 #define MIIM_DP83865_CR_INIT	0x9200
@@ -237,18 +237,18 @@
 #define MIIM_DP83865_SPD_100	0x0008
 #define MIIM_DP83865_DPX_FULL	0x0002
 
-#define MIIM_READ_COMMAND       0x00000001
+#define MIIM_READ_COMMAND	0x00000001
 
 #define MRBLR_INIT_SETTINGS	PKTSIZE_ALIGN
 
 #define MINFLR_INIT_SETTINGS	0x00000040
 
-#define DMACTRL_INIT_SETTINGS   0x000000c3
-#define DMACTRL_GRS             0x00000010
-#define DMACTRL_GTS             0x00000008
+#define DMACTRL_INIT_SETTINGS	0x000000c3
+#define DMACTRL_GRS		0x00000010
+#define DMACTRL_GTS		0x00000008
 
-#define TSTAT_CLEAR_THALT       0x80000000
-#define RSTAT_CLEAR_RHALT       0x00800000
+#define TSTAT_CLEAR_THALT	0x80000000
+#define RSTAT_CLEAR_RHALT	0x00800000
 
 
 #define IEVENT_INIT_CLEAR	0xffffffff
@@ -274,7 +274,7 @@
 #define IMASK_INIT_CLEAR	0x00000000
 #define IMASK_TXEEN		0x00400000
 #define IMASK_TXBEN		0x00200000
-#define IMASK_TXFEN             0x00100000
+#define IMASK_TXFEN		0x00100000
 #define IMASK_RXFEN0		0x00000080
 
 
@@ -296,7 +296,7 @@
 #define TXBD_RETRYLIMIT		0x0040
 #define	TXBD_RETRYCOUNTMASK	0x003c
 #define TXBD_UNDERRUN		0x0002
-#define TXBD_STATS              0x03ff
+#define TXBD_STATS		0x03ff
 
 /* RxBD status field bits */
 #define RXBD_EMPTY		0x8000
@@ -318,16 +318,16 @@
 
 typedef struct txbd8
 {
-	ushort       status;         /* Status Fields */
-	ushort       length;         /* Buffer length */
-	uint         bufPtr;         /* Buffer Pointer */
+	ushort	     status;	     /* Status Fields */
+	ushort	     length;	     /* Buffer length */
+	uint	     bufPtr;	     /* Buffer Pointer */
 } txbd8_t;
 
 typedef struct rxbd8
 {
-	ushort       status;         /* Status Fields */
-	ushort       length;         /* Buffer Length */
-	uint         bufPtr;         /* Buffer Pointer */
+	ushort	     status;	     /* Status Fields */
+	ushort	     length;	     /* Buffer Length */
+	uint	     bufPtr;	     /* Buffer Pointer */
 } rxbd8_t;
 
 typedef struct rmon_mib
@@ -431,21 +431,21 @@ typedef struct tsec
 
 	/* Transmit Control and Status Registers (0x2_n100) */
 	uint	tctrl;		/* Transmit Control */
-	uint 	tstat;		/* Transmit Status */
+	uint	tstat;		/* Transmit Status */
 	uint	res108;
 	uint	tbdlen;		/* Tx BD Data Length */
 	uint	res110[5];
-	uint	ctbptr;	        /* Current TxBD Pointer */
+	uint	ctbptr;		/* Current TxBD Pointer */
 	uint	res128[23];
 	uint	tbptr;		/* TxBD Pointer */
 	uint	res188[30];
 	/* (0x2_n200) */
-	uint        res200;
+	uint	res200;
 	uint	tbase;		/* TxBD Base Address */
 	uint	res208[42];
 	uint	ostbd;		/* Out of Sequence TxBD */
 	uint	ostbdp;		/* Out of Sequence Tx Data Buffer Pointer */
-	uint        res2b8[18];
+	uint	res2b8[18];
 
 	/* Receive Control and Status Registers (0x2_n300) */
 	uint	rctrl;		/* Receive Control */
@@ -453,17 +453,17 @@ typedef struct tsec
 	uint	res308;
 	uint	rbdlen;		/* RxBD Data Length */
 	uint	res310[4];
-	uint        res320;
-	uint	crbptr; 	/* Current Receive Buffer Pointer */
+	uint	res320;
+	uint	crbptr;	/* Current Receive Buffer Pointer */
 	uint	res328[6];
-	uint	mrblr;  	/* Maximum Receive Buffer Length */
+	uint	mrblr;	/* Maximum Receive Buffer Length */
 	uint	res344[16];
-	uint	rbptr;   	/* RxBD Pointer */
-	uint        res388[30];
+	uint	rbptr;	/* RxBD Pointer */
+	uint	res388[30];
 	/* (0x2_n400) */
-	uint        res400;
-	uint	rbase;  	/* RxBD Base Address */
-	uint        res408[62];
+	uint	res400;
+	uint	rbase;	/* RxBD Base Address */
+	uint	res408[62];
 
 	/* MAC Registers (0x2_n500) */
 	uint	maccfg1;	/* MAC Configuration #1 */
@@ -500,12 +500,12 @@ typedef struct tsec
 	/* Hash Function Registers (0x2_n800) */
 	tsec_hash_t	hash;
 
-	uint        res900[128];
+	uint	res900[128];
 
 	/* Pattern Registers (0x2_nb00) */
-	uint        resb00[62];
-	uint        attr;          /* Default Attribute Register */
-	uint        attreli;       /* Default Attribute Extract Length and Index */
+	uint	resb00[62];
+	uint	attr;	   /* Default Attribute Register */
+	uint	attreli;	   /* Default Attribute Extract Length and Index */
 
 	/* TSEC Future Expansion Space (0x2_nc00-0x2_nffc) */
 	uint	resc00[256];
@@ -535,18 +535,18 @@ struct tsec_private {
  * mii_reg:  The register to read or write
  *
  * mii_data:  For writes, the value to put in the register.
- * 	A value of -1 indicates this is a read.
+ *	A value of -1 indicates this is a read.
  *
  * funct: A function pointer which is invoked for each command.
- * 	For reads, this function will be passed the value read
+ *	For reads, this function will be passed the value read
  *	from the PHY, and process it.
  *	For writes, the result of this function will be written
  *	to the PHY register
  */
 struct phy_cmd {
-    uint mii_reg;
-    uint mii_data;
-    uint (*funct) (uint mii_reg, struct tsec_private* priv);
+	uint mii_reg;
+	uint mii_data;
+	uint (*funct) (uint mii_reg, struct tsec_private * priv);
 };
 
 /* struct phy_info: a structure which defines attributes for a PHY
@@ -562,18 +562,18 @@ struct phy_cmd {
  * commands which tell the driver what to do to the PHY.
  */
 struct phy_info {
-    uint id;
-    char *name;
-    uint shift;
-    /* Called to configure the PHY, and modify the controller
-     * based on the results */
-    struct phy_cmd *config;
-
-    /* Called when starting up the controller */
-    struct phy_cmd *startup;
-
-    /* Called when bringing down the controller */
-    struct phy_cmd *shutdown;
+	uint id;
+	char *name;
+	uint shift;
+	/* Called to configure the PHY, and modify the controller
+	 * based on the results */
+	struct phy_cmd *config;
+
+	/* Called when starting up the controller */
+	struct phy_cmd *startup;
+
+	/* Called when bringing down the controller */
+	struct phy_cmd *shutdown;
 };
 
 #endif /* __TSEC_H */
diff --git a/drivers/net/uli526x.c b/drivers/net/uli526x.c
index d64845fec8..79d29ae822 100644
--- a/drivers/net/uli526x.c
+++ b/drivers/net/uli526x.c
@@ -412,7 +412,7 @@ static void uli526x_init(struct eth_device *dev)
 	}
 	/* Media Mode Process */
 	if (!(db->media_mode & ULI526X_AUTO))
-		db->op_mode = db->media_mode; 	/* Force Mode */
+		db->op_mode = db->media_mode;	/* Force Mode */
 
 	/* Initialize Transmit/Receive decriptor and CR3/4 */
 	uli526x_descriptor_init(db, db->ioaddr);
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index ad1b7ddb43..dec93b94d7 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -23,7 +23,7 @@
 
 include $(TOPDIR)/config.mk
 
-LIB 	:= $(obj)libpci.a
+LIB	:= $(obj)libpci.a
 
 COBJS-y += fsl_pci_init.o
 COBJS-y += pci.o
@@ -36,8 +36,8 @@ COBJS-$(CONFIG_SH7751_PCI) +=pci_sh7751.o
 COBJS-$(CONFIG_SH7780_PCI) +=pci_sh7780.o
 
 COBJS	:= $(COBJS-y)
-SRCS 	:= $(COBJS:.o=.c)
-OBJS 	:= $(addprefix $(obj),$(COBJS))
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
 
 all:	$(LIB)
 
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index b820d5e853..b3ae3b152c 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -38,8 +38,8 @@
 #include <pci.h>
 
 #define PCI_HOSE_OP(rw, size, type)					\
-int pci_hose_##rw##_config_##size(struct pci_controller *hose, 		\
-				  pci_dev_t dev, 			\
+int pci_hose_##rw##_config_##size(struct pci_controller *hose,		\
+				  pci_dev_t dev,			\
 				  int offset, type value)		\
 {									\
 	return hose->rw##_##size(hose, dev, offset, value);		\
@@ -77,7 +77,7 @@ PCI_OP(write, dword, u32, )
 
 #define PCI_READ_VIA_DWORD_OP(size, type, off_mask)			\
 int pci_hose_read_config_##size##_via_dword(struct pci_controller *hose,\
-					pci_dev_t dev, 			\
+					pci_dev_t dev,			\
 					int offset, type val)		\
 {									\
 	u32 val32;							\
@@ -94,7 +94,7 @@ int pci_hose_read_config_##size##_via_dword(struct pci_controller *hose,\
 
 #define PCI_WRITE_VIA_DWORD_OP(size, type, off_mask, val_mask)		\
 int pci_hose_write_config_##size##_via_dword(struct pci_controller *hose,\
-					     pci_dev_t dev, 		\
+					     pci_dev_t dev,		\
 					     int offset, type val)	\
 {									\
 	u32 val32, mask, ldata, shift;					\
diff --git a/drivers/pci/pci_indirect.c b/drivers/pci/pci_indirect.c
index a8220fb411..55517a8fed 100644
--- a/drivers/pci/pci_indirect.c
+++ b/drivers/pci/pci_indirect.c
@@ -33,17 +33,17 @@ extern void		out_le32 (volatile unsigned *addr, unsigned int val);
 #if defined(CONFIG_MPC8260)
 #define INDIRECT_PCI_OP(rw, size, type, op, mask)			 \
 static int								 \
-indirect_##rw##_config_##size(struct pci_controller *hose, 		 \
+indirect_##rw##_config_##size(struct pci_controller *hose,		 \
 			      pci_dev_t dev, int offset, type val)	 \
 {									 \
 	u32 b, d,f;							 \
 	b = PCI_BUS(dev); d = PCI_DEV(dev); f = PCI_FUNC(dev);		 \
 	b = b - hose->first_busno;					 \
 	dev = PCI_BDF(b, d, f);						 \
-	out_le32(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000000); 	 \
+	out_le32(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000000);	 \
 	sync();								 \
 	cfg_##rw(val, hose->cfg_data + (offset & mask), type, op);	 \
-	return 0;    					 		 \
+	return 0;							 \
 }
 #elif defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
 #define INDIRECT_PCI_OP(rw, size, type, op, mask)                        \
@@ -63,7 +63,7 @@ indirect_##rw##_config_##size(struct pci_controller *hose,               \
 #elif defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SPE)
 #define INDIRECT_PCI_OP(rw, size, type, op, mask)			 \
 static int								 \
-indirect_##rw##_config_##size(struct pci_controller *hose, 		 \
+indirect_##rw##_config_##size(struct pci_controller *hose,		 \
 			      pci_dev_t dev, int offset, type val)	 \
 {									 \
 	u32 b, d,f;							 \
@@ -75,36 +75,36 @@ indirect_##rw##_config_##size(struct pci_controller *hose, 		 \
 	else                                                             \
 		out_le32(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000000); \
 	cfg_##rw(val, hose->cfg_data + (offset & mask), type, op);	 \
-	return 0;    					 		 \
+	return 0;							 \
 }
 #else
 #define INDIRECT_PCI_OP(rw, size, type, op, mask)			 \
 static int								 \
-indirect_##rw##_config_##size(struct pci_controller *hose, 		 \
+indirect_##rw##_config_##size(struct pci_controller *hose,		 \
 			      pci_dev_t dev, int offset, type val)	 \
 {									 \
 	u32 b, d,f;							 \
 	b = PCI_BUS(dev); d = PCI_DEV(dev); f = PCI_FUNC(dev);		 \
 	b = b - hose->first_busno;					 \
 	dev = PCI_BDF(b, d, f);						 \
-	out_le32(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000000); 	 \
+	out_le32(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000000);	 \
 	cfg_##rw(val, hose->cfg_data + (offset & mask), type, op);	 \
-	return 0;    					 		 \
+	return 0;							 \
 }
 #endif
 
 #define INDIRECT_PCI_OP_ERRATA6(rw, size, type, op, mask)		 \
 static int								 \
-indirect_##rw##_config_##size(struct pci_controller *hose, 		 \
+indirect_##rw##_config_##size(struct pci_controller *hose,		 \
 			      pci_dev_t dev, int offset, type val)	 \
 {									 \
 	unsigned int msr = mfmsr();					 \
 	mtmsr(msr & ~(MSR_EE | MSR_CE));				 \
-	out_le32(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000000); 	 \
+	out_le32(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000000);	 \
 	cfg_##rw(val, hose->cfg_data + (offset & mask), type, op);	 \
-	out_le32(hose->cfg_addr, 0x00000000); 				 \
+	out_le32(hose->cfg_addr, 0x00000000);				 \
 	mtmsr(msr);							 \
-	return 0;    					 		 \
+	return 0;							 \
 }
 
 INDIRECT_PCI_OP(read, byte, u8 *, in_8, 3)
diff --git a/drivers/pci/pci_sh7780.c b/drivers/pci/pci_sh7780.c
index d63d67d2dc..2d04b4fc61 100644
--- a/drivers/pci/pci_sh7780.c
+++ b/drivers/pci/pci_sh7780.c
@@ -42,9 +42,9 @@
 #define SH7780_PCICR_CFIN	0x00000001
 
 #define p4_in(addr)			*((vu_long *)addr)
-#define p4_out(data,addr) 	*(vu_long *)(addr) = (data)
+#define p4_out(data,addr)	*(vu_long *)(addr) = (data)
 #define p4_inw(addr)		*((vu_short *)addr)
-#define p4_outw(data,addr) 	*(vu_short *)(addr) = (data)
+#define p4_outw(data,addr)	*(vu_short *)(addr) = (data)
 
 int pci_sh4_read_config_dword(struct pci_controller *hose,
 				    pci_dev_t dev, int offset, u32 *value)
diff --git a/drivers/pci/w83c553f.c b/drivers/pci/w83c553f.c
index 5d82ed4dd4..9ea08a2565 100644
--- a/drivers/pci/w83c553f.c
+++ b/drivers/pci/w83c553f.c
@@ -182,7 +182,7 @@ void initialise_dma(void)
 			rvalue1 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH0SEL|W83C553F_MODE_TT_VERIFY);
 			rvalue2 = (W83C553F_MODE_TM_CASCADE|W83C553F_MODE_CH0SEL);
 			break;
-	    	case 1:
+		case 1:
 			rvalue1 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH1SEL|W83C553F_MODE_TT_VERIFY);
 			rvalue2 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH1SEL|W83C553F_MODE_TT_VERIFY);
 			break;
diff --git a/drivers/pcmcia/Makefile b/drivers/pcmcia/Makefile
index 53a485d0d1..ac4378a0bd 100644
--- a/drivers/pcmcia/Makefile
+++ b/drivers/pcmcia/Makefile
@@ -23,7 +23,7 @@
 
 include $(TOPDIR)/config.mk
 
-LIB 	:= $(obj)libpcmcia.a
+LIB	:= $(obj)libpcmcia.a
 
 COBJS-$(CONFIG_I82365) += i82365.o
 COBJS-y += mpc8xx_pcmcia.o
@@ -34,8 +34,8 @@ COBJS-y += tqm8xx_pcmcia.o
 COBJS-y += marubun_pcmcia.o
 
 COBJS	:= $(COBJS-y)
-SRCS 	:= $(COBJS:.o=.c)
-OBJS 	:= $(addprefix $(obj),$(COBJS))
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
 
 all:	$(LIB)
 
diff --git a/drivers/pcmcia/marubun_pcmcia.c b/drivers/pcmcia/marubun_pcmcia.c
index 2479a6662a..a213092334 100644
--- a/drivers/pcmcia/marubun_pcmcia.c
+++ b/drivers/pcmcia/marubun_pcmcia.c
@@ -39,7 +39,7 @@
 	        && (defined(CONFIG_MARUBUN_PCCARD))
 
 /* MR-SHPC-01 register */
-#define MRSHPC_MODE   	(CFG_MARUBUN_MRSHPC + 4)
+#define MRSHPC_MODE	(CFG_MARUBUN_MRSHPC + 4)
 #define MRSHPC_OPTION   (CFG_MARUBUN_MRSHPC + 6)
 #define MRSHPC_CSR      (CFG_MARUBUN_MRSHPC + 8)
 #define MRSHPC_ISR      (CFG_MARUBUN_MRSHPC + 10)
diff --git a/drivers/pcmcia/mpc8xx_pcmcia.c b/drivers/pcmcia/mpc8xx_pcmcia.c
index 8a34cd3054..14477a4487 100644
--- a/drivers/pcmcia/mpc8xx_pcmcia.c
+++ b/drivers/pcmcia/mpc8xx_pcmcia.c
@@ -61,18 +61,18 @@ static const u_int m8xx_size_to_gray[M8XX_SIZES_NO] =
 
 #ifdef	CONFIG_HMI10
 #define	HMI10_FRAM_TIMING	(	PCMCIA_SHT(2)	\
- 				|	PCMCIA_SST(2)	\
- 				|	PCMCIA_SL(4))
+				|	PCMCIA_SST(2)	\
+				|	PCMCIA_SL(4))
 #endif
 
 #if	defined(CONFIG_LWMON) || defined(CONFIG_NSCU)
 #define	CFG_PCMCIA_TIMING	(	PCMCIA_SHT(9)	\
- 				|	PCMCIA_SST(3)	\
- 				|	PCMCIA_SL(12))
+				|	PCMCIA_SST(3)	\
+				|	PCMCIA_SL(12))
 #else
 #define	CFG_PCMCIA_TIMING	(	PCMCIA_SHT(2)	\
- 				|	PCMCIA_SST(4)	\
- 				|	PCMCIA_SL(9))
+				|	PCMCIA_SST(4)	\
+				|	PCMCIA_SL(9))
 #endif
 
 /* -------------------------------------------------------------------- */
diff --git a/drivers/pcmcia/tqm8xx_pcmcia.c b/drivers/pcmcia/tqm8xx_pcmcia.c
index 132c7a5169..cc980c2ea3 100644
--- a/drivers/pcmcia/tqm8xx_pcmcia.c
+++ b/drivers/pcmcia/tqm8xx_pcmcia.c
@@ -296,10 +296,10 @@ int pcmcia_voltage_set(int slot, int vcc, int vpp)
 	power_off(slot);
 
 	switch(vcc) {
-		case  0: 			break;
+		case  0:			break;
 		case 33: power_on_3_3(slot);	break;
 		case 50: power_on_5_0(slot);	break;
-		default: 			goto done;
+		default:			goto done;
 	}
 
 	/* Checking supported voltages */
diff --git a/drivers/qe/Makefile b/drivers/qe/Makefile
index ec5aa738aa..45a2fff62c 100644
--- a/drivers/qe/Makefile
+++ b/drivers/qe/Makefile
@@ -22,13 +22,13 @@
 
 include $(TOPDIR)/config.mk
 
-LIB 	:= $(obj)qe.a
+LIB	:= $(obj)qe.a
 
 COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
-COBJS 	:= qe.o uccf.o uec.o uec_phy.o $(COBJS-y)
+COBJS	:= qe.o uccf.o uec.o uec_phy.o $(COBJS-y)
 
-SRCS 	:= $(COBJS:.o=.c)
-OBJS 	:= $(addprefix $(obj),$(COBJS))
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
 
 all:	$(LIB)
 
diff --git a/drivers/qe/qe.h b/drivers/qe/qe.h
index 741ed7fa4a..a55555f661 100644
--- a/drivers/qe/qe.h
+++ b/drivers/qe/qe.h
@@ -40,7 +40,7 @@ typedef enum qe_snum_state {
 } qe_snum_state_e;
 
 typedef struct qe_snum {
-	u8		num;   /* snum  */
+	u8		num;   /* snum	*/
 	qe_snum_state_e	state; /* state */
 } qe_snum_t;
 
@@ -154,30 +154,30 @@ typedef enum qe_clock {
 	QE_BRG14,    /* Baud Rate Generator 14 */
 	QE_BRG15,    /* Baud Rate Generator 15 */
 	QE_BRG16,    /* Baud Rate Generator 16 */
-	QE_CLK1,     /* Clock  1               */
-	QE_CLK2,     /* Clock  2               */
-	QE_CLK3,     /* Clock  3               */
-	QE_CLK4,     /* Clock  4               */
-	QE_CLK5,     /* Clock  5               */
-	QE_CLK6,     /* Clock  6               */
-	QE_CLK7,     /* Clock  7               */
-	QE_CLK8,     /* Clock  8               */
-	QE_CLK9,     /* Clock  9               */
-	QE_CLK10,    /* Clock 10               */
-	QE_CLK11,    /* Clock 11               */
-	QE_CLK12,    /* Clock 12               */
-	QE_CLK13,    /* Clock 13               */
-	QE_CLK14,    /* Clock 14               */
-	QE_CLK15,    /* Clock 15               */
-	QE_CLK16,    /* Clock 16               */
-	QE_CLK17,    /* Clock 17               */
-	QE_CLK18,    /* Clock 18               */
-	QE_CLK19,    /* Clock 19               */
-	QE_CLK20,    /* Clock 20               */
-	QE_CLK21,    /* Clock 21               */
-	QE_CLK22,    /* Clock 22               */
-	QE_CLK23,    /* Clock 23               */
-	QE_CLK24,    /* Clock 24               */
+	QE_CLK1,     /* Clock  1	       */
+	QE_CLK2,     /* Clock  2	       */
+	QE_CLK3,     /* Clock  3	       */
+	QE_CLK4,     /* Clock  4	       */
+	QE_CLK5,     /* Clock  5	       */
+	QE_CLK6,     /* Clock  6	       */
+	QE_CLK7,     /* Clock  7	       */
+	QE_CLK8,     /* Clock  8	       */
+	QE_CLK9,     /* Clock  9	       */
+	QE_CLK10,    /* Clock 10	       */
+	QE_CLK11,    /* Clock 11	       */
+	QE_CLK12,    /* Clock 12	       */
+	QE_CLK13,    /* Clock 13	       */
+	QE_CLK14,    /* Clock 14	       */
+	QE_CLK15,    /* Clock 15	       */
+	QE_CLK16,    /* Clock 16	       */
+	QE_CLK17,    /* Clock 17	       */
+	QE_CLK18,    /* Clock 18	       */
+	QE_CLK19,    /* Clock 19	       */
+	QE_CLK20,    /* Clock 20	       */
+	QE_CLK21,    /* Clock 21	       */
+	QE_CLK22,    /* Clock 22	       */
+	QE_CLK23,    /* Clock 23	       */
+	QE_CLK24,    /* Clock 24	       */
 	QE_CLK_DUMMY
 } qe_clock_e;
 
@@ -237,34 +237,34 @@ typedef enum qe_clock {
  */
 struct qe_firmware {
 	struct qe_header {
-		u32 length;  /* Length of the entire structure, in bytes */
-		u8 magic[3];    /* Set to { 'Q', 'E', 'F' } */
-		u8 version;     /* Version of this layout. First ver is '1' */
+		u32 length;	/* Length of the entire structure, in bytes */
+		u8 magic[3];	/* Set to { 'Q', 'E', 'F' } */
+		u8 version;	/* Version of this layout. First ver is '1' */
 	} header;
-	u8 id[62];      /* Null-terminated identifier string */
-	u8 split;	/* 0 = shared I-RAM, 1 = split I-RAM */
-	u8 count;       /* Number of microcode[] structures */
+	u8 id[62];		/* Null-terminated identifier string */
+	u8 split;		/* 0 = shared I-RAM, 1 = split I-RAM */
+	u8 count;		/* Number of microcode[] structures */
 	struct {
-		u16 model;   	/* The SOC model  */
-		u8 major;       	/* The SOC revision major */
-		u8 minor;       	/* The SOC revision minor */
+		u16 model;	/* The SOC model  */
+		u8 major;	/* The SOC revision major */
+		u8 minor;	/* The SOC revision minor */
 	} __attribute__ ((packed)) soc;
-	u8 padding[4];			/* Reserved, for alignment */
-	u64 extended_modes;		/* Extended modes */
+	u8 padding[4];		/* Reserved, for alignment */
+	u64 extended_modes;	/* Extended modes */
 	u32 vtraps[8];		/* Virtual trap addresses */
-	u8 reserved[4];			/* Reserved, for future expansion */
+	u8 reserved[4];		/* Reserved, for future expansion */
 	struct qe_microcode {
-		u8 id[32];      	/* Null-terminated identifier */
-		u32 traps[16];       /* Trap addresses, 0 == ignore */
-		u32 eccr;    	/* The value for the ECCR register */
-		u32 iram_offset;     /* Offset into I-RAM for the code */
-		u32 count;   	/* Number of 32-bit words of the code */
-		u32 code_offset;     /* Offset of the actual microcode */
-		u8 major;       	/* The microcode version major */
-		u8 minor;       	/* The microcode version minor */
-		u8 revision;		/* The microcode version revision */
-		u8 padding;		/* Reserved, for alignment */
-		u8 reserved[4];		/* Reserved, for future expansion */
+		u8 id[32];	/* Null-terminated identifier */
+		u32 traps[16];	/* Trap addresses, 0 == ignore */
+		u32 eccr;	/* The value for the ECCR register */
+		u32 iram_offset;/* Offset into I-RAM for the code */
+		u32 count;	/* Number of 32-bit words of the code */
+		u32 code_offset;/* Offset of the actual microcode */
+		u8 major;	/* The microcode version major */
+		u8 minor;	/* The microcode version minor */
+		u8 revision;	/* The microcode version revision */
+		u8 padding;	/* Reserved, for alignment */
+		u8 reserved[4];	/* Reserved, for future expansion */
 	} __attribute__ ((packed)) microcode[1];
 	/* All microcode binaries should be located here */
 	/* CRC32 should be located here, after the microcode binaries */
diff --git a/drivers/qe/uccf.c b/drivers/qe/uccf.c
index c5477e0d7e..4a327ab48f 100644
--- a/drivers/qe/uccf.c
+++ b/drivers/qe/uccf.c
@@ -369,7 +369,7 @@ int ucc_fast_init(ucc_fast_info_t *uf_info, ucc_fast_private_t  **uccf_ret)
 		out_be16(&uf_regs->urfset, UCC_GETH_URFSET_INIT);
 		out_be16(&uf_regs->utfs, UCC_GETH_UTFS_INIT);
 		out_be16(&uf_regs->utfet, UCC_GETH_UTFET_INIT);
- 		out_be16(&uf_regs->utftt, UCC_GETH_UTFTT_INIT);
+		out_be16(&uf_regs->utftt, UCC_GETH_UTFTT_INIT);
 	}
 
 	/* Rx clock routing */
diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c
index d34430c659..d2c430b8a6 100644
--- a/drivers/qe/uec.c
+++ b/drivers/qe/uec.c
@@ -381,7 +381,7 @@ static int uec_set_mac_duplex(uec_private_t *uec, int duplex)
 static int uec_set_mac_if_mode(uec_private_t *uec, enet_interface_e if_mode)
 {
 	enet_interface_e	enet_if_mode;
-	uec_info_t 		*uec_info;
+	uec_info_t		*uec_info;
 	uec_t			*uec_regs;
 	u32			upsmr;
 	u32			maccfg2;
diff --git a/drivers/qe/uec.h b/drivers/qe/uec.h
index 7762de6a8d..e357a92bbd 100644
--- a/drivers/qe/uec.h
+++ b/drivers/qe/uec.h
@@ -709,7 +709,7 @@ typedef struct uec_private {
 	int				grace_stopped_rx;
 	int				the_first_run;
 	/* PHY specific */
-	struct uec_mii_info 		*mii_info;
+	struct uec_mii_info		*mii_info;
 	int				oldspeed;
 	int				oldduplex;
 	int				oldlink;
diff --git a/drivers/rtc/date.c b/drivers/rtc/date.c
index a83a7235ab..d30ad92a70 100644
--- a/drivers/rtc/date.c
+++ b/drivers/rtc/date.c
@@ -36,8 +36,8 @@
 #define SECDAY			86400L
 #define SECYR			(SECDAY * 365)
 #define	leapyear(year)		((year) % 4 == 0)
-#define	days_in_year(a) 	(leapyear(a) ? 366 : 365)
-#define	days_in_month(a) 	(month_days[(a) - 1])
+#define	days_in_year(a)		(leapyear(a) ? 366 : 365)
+#define	days_in_month(a)	(month_days[(a) - 1])
 
 static int month_days[12] = {
 	31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31
diff --git a/drivers/rtc/ds12887.c b/drivers/rtc/ds12887.c
index 57a446d305..990ebba263 100644
--- a/drivers/rtc/ds12887.c
+++ b/drivers/rtc/ds12887.c
@@ -35,14 +35,14 @@
 #define RTC_MINUTES			0x02
 #define RTC_MINUTES_ALARM		0x03
 #define RTC_HOURS			0x04
-#define RTC_HOURS_ALARM 		0x05
-#define RTC_DAY_OF_WEEK 		0x06
+#define RTC_HOURS_ALARM			0x05
+#define RTC_DAY_OF_WEEK			0x06
 #define RTC_DATE_OF_MONTH		0x07
 #define RTC_MONTH			0x08
 #define RTC_YEAR			0x09
-#define RTC_CONTROL_A 			0x0A
-#define RTC_CONTROL_B 			0x0B
-#define RTC_CONTROL_C 			0x0C
+#define RTC_CONTROL_A			0x0A
+#define RTC_CONTROL_B			0x0B
+#define RTC_CONTROL_C			0x0C
 #define RTC_CONTROL_D			0x0D
 
 #define RTC_CA_UIP			0x80
diff --git a/drivers/rtc/ds1302.c b/drivers/rtc/ds1302.c
index 3a856c840a..e4e9154754 100644
--- a/drivers/rtc/ds1302.c
+++ b/drivers/rtc/ds1302.c
@@ -66,7 +66,7 @@ struct ds1302_st
 	unsigned char month:4;
 
 	unsigned char zero4:5;
-	unsigned char day:3; 		/* day of week */
+	unsigned char day:3;		/* day of week */
 
 	unsigned char year10:4;
 	unsigned char year:4;
@@ -191,7 +191,7 @@ write_ser_drv(unsigned char addr, unsigned char *buf, int count)
 void
 rtc_init(void)
 {
-    	struct ds1302_st bbclk;
+	struct ds1302_st bbclk;
 	unsigned char b;
 	int mod;
 
diff --git a/drivers/rtc/mc146818.c b/drivers/rtc/mc146818.c
index 70f7017a3f..7c4fe36e90 100644
--- a/drivers/rtc/mc146818.c
+++ b/drivers/rtc/mc146818.c
@@ -38,21 +38,21 @@ static void  rtc_write (uchar reg, uchar val);
 static uchar bin2bcd   (unsigned int n);
 static unsigned bcd2bin(uchar c);
 
-#define RTC_PORT_MC146818		CFG_ISA_IO_BASE_ADDRESS +  0x70
-#define RTC_SECONDS       	0x00
-#define RTC_SECONDS_ALARM 	0x01
-#define RTC_MINUTES 				0x02
-#define RTC_MINUTES_ALARM 	0x03
-#define RTC_HOURS 					0x04
-#define RTC_HOURS_ALARM 		0x05
-#define RTC_DAY_OF_WEEK 		0x06
-#define RTC_DATE_OF_MONTH 	0x07
-#define RTC_MONTH 					0x08
-#define RTC_YEAR 						0x09
-#define RTC_CONFIG_A 				0x0A
-#define RTC_CONFIG_B 				0x0B
-#define RTC_CONFIG_C 				0x0C
-#define RTC_CONFIG_D 				0x0D
+#define RTC_PORT_MC146818	CFG_ISA_IO_BASE_ADDRESS +  0x70
+#define RTC_SECONDS		0x00
+#define RTC_SECONDS_ALARM	0x01
+#define RTC_MINUTES		0x02
+#define RTC_MINUTES_ALARM	0x03
+#define RTC_HOURS		0x04
+#define RTC_HOURS_ALARM		0x05
+#define RTC_DAY_OF_WEEK		0x06
+#define RTC_DATE_OF_MONTH	0x07
+#define RTC_MONTH		0x08
+#define RTC_YEAR		0x09
+#define RTC_CONFIG_A		0x0A
+#define RTC_CONFIG_B		0x0B
+#define RTC_CONFIG_C		0x0C
+#define RTC_CONFIG_D		0x0D
 
 
 /* ------------------------------------------------------------------------- */
@@ -62,12 +62,12 @@ int rtc_get (struct rtc_time *tmp)
 	uchar sec, min, hour, mday, wday, mon, year;
   /* here check if rtc can be accessed */
 	while((rtc_read(RTC_CONFIG_A)&0x80)==0x80);
-	sec		= rtc_read (RTC_SECONDS);
-	min		= rtc_read (RTC_MINUTES);
+	sec	= rtc_read (RTC_SECONDS);
+	min	= rtc_read (RTC_MINUTES);
 	hour	= rtc_read (RTC_HOURS);
 	mday	= rtc_read (RTC_DATE_OF_MONTH);
 	wday	= rtc_read (RTC_DAY_OF_WEEK);
-	mon		= rtc_read (RTC_MONTH);
+	mon	= rtc_read (RTC_MONTH);
 	year	= rtc_read (RTC_YEAR);
 #ifdef CONFIG_AMIGAONEG3SE
 	wday -= 1; /* VIA 686 stores Sunday = 1, Monday = 2, ... */
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index ee2b780857..c9e797e8c0 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -23,7 +23,7 @@
 
 include $(TOPDIR)/config.mk
 
-LIB 	:= $(obj)libserial.a
+LIB	:= $(obj)libserial.a
 
 COBJS-y += atmel_usart.o
 COBJS-y += mcfuart.o
@@ -39,8 +39,8 @@ COBJS-y += serial_sh.o
 COBJS-y += usbtty.o
 
 COBJS	:= $(COBJS-y)
-SRCS 	:= $(COBJS:.o=.c)
-OBJS 	:= $(addprefix $(obj),$(COBJS))
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
 
 all:	$(LIB)
 
diff --git a/drivers/serial/serial_max3100.c b/drivers/serial/serial_max3100.c
index 35c5596985..0611fc1dd4 100644
--- a/drivers/serial/serial_max3100.c
+++ b/drivers/serial/serial_max3100.c
@@ -94,7 +94,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define MAX3100_CTS	(1 <<  9)		/* clear-to-send bit (inverted ~CTS pin)   */
 
 /* data register bits (both directions) */
-#define MAX3100_R 	(1 << 15)		/* receive bit    */
+#define MAX3100_R	(1 << 15)		/* receive bit    */
 #define MAX3100_T	(1 << 14)		/* transmit bit   */
 #define MAX3100_P	(1 <<  8)		/* parity bit     */
 #define MAX3100_D_MASK	0x00FF                  /* data bits mask */
diff --git a/drivers/serial/serial_sh.c b/drivers/serial/serial_sh.c
index 522f96d5db..aa4ff35333 100644
--- a/drivers/serial/serial_sh.c
+++ b/drivers/serial/serial_sh.c
@@ -42,7 +42,7 @@
 # define SCFRDR	(vu_char  *)(SCIF_BASE + 0x24)
 #else
 # define SCFTDR (vu_char  *)(SCIF_BASE + 0xC)
-# define SCFSR 	(vu_short *)(SCIF_BASE + 0x10)
+# define SCFSR	(vu_short *)(SCIF_BASE + 0x10)
 # define SCFRDR (vu_char  *)(SCIF_BASE + 0x14)
 #endif
 
@@ -50,19 +50,19 @@
 	defined(CONFIG_CPU_SH7785)
 # define SCRFDR	(vu_short *)(SCIF_BASE + 0x20)
 # define SCSPTR	(vu_short *)(SCIF_BASE + 0x24)
-# define SCLSR   (vu_short *)(SCIF_BASE + 0x28)
+# define SCLSR	(vu_short *)(SCIF_BASE + 0x28)
 # define SCRER	(vu_short *)(SCIF_BASE + 0x2C)
 # define LSR_ORER	1
 # define FIFOLEVEL_MASK	0xFF
 #elif defined(CONFIG_CPU_SH7750) || \
 	defined(CONFIG_CPU_SH7751) || \
 	defined(CONFIG_CPU_SH7722)
-# define SCSPTR 	(vu_short *)(SCIF_BASE + 0x20)
-# define SCLSR 	(vu_short *)(SCIF_BASE + 0x24)
+# define SCSPTR	(vu_short *)(SCIF_BASE + 0x20)
+# define SCLSR	(vu_short *)(SCIF_BASE + 0x24)
 # define LSR_ORER	1
 # define FIFOLEVEL_MASK	0x1F
 #elif defined(CONFIG_CPU_SH7720)
-# define SCLSR   (vu_short *)(SCIF_BASE + 0x24)
+# define SCLSR	 (vu_short *)(SCIF_BASE + 0x24)
 # define LSR_ORER	0x0200
 # define FIFOLEVEL_MASK	0x1F
 #elif defined(CONFIG_CPU_SH7710)
@@ -79,17 +79,17 @@
 # define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)
 #endif
 
-#define SCR_RE 		(1 << 4)
-#define SCR_TE 		(1 << 5)
+#define SCR_RE		(1 << 4)
+#define SCR_TE		(1 << 5)
 #define FCR_RFRST	(1 << 1) /* RFCL */
 #define FCR_TFRST	(1 << 2) /* TFCL */
-#define FSR_DR   	(1 << 0)
-#define FSR_RDF  	(1 << 1)
-#define FSR_FER  	(1 << 3)
-#define FSR_BRK  	(1 << 4)
-#define FSR_FER  	(1 << 3)
-#define FSR_TEND 	(1 << 6)
-#define FSR_ER   	(1 << 7)
+#define FSR_DR		(1 << 0)
+#define FSR_RDF		(1 << 1)
+#define FSR_FER		(1 << 3)
+#define FSR_BRK		(1 << 4)
+#define FSR_FER		(1 << 3)
+#define FSR_TEND	(1 << 6)
+#define FSR_ER		(1 << 7)
 
 /*----------------------------------------------------------------------*/
 
@@ -156,8 +156,8 @@ int serial_tstc (void)
 	return serial_rx_fifo_level() ? 1 : 0;
 }
 
-#define FSR_ERR_CLEAR   0x0063
-#define RDRF_CLEAR      0x00fc
+#define FSR_ERR_CLEAR	0x0063
+#define RDRF_CLEAR	0x00fc
 void handle_error( void ){
 
 	(void)*SCFSR ;
diff --git a/drivers/serial/usbtty.c b/drivers/serial/usbtty.c
index a3b50131df..cc2bdac479 100644
--- a/drivers/serial/usbtty.c
+++ b/drivers/serial/usbtty.c
@@ -31,7 +31,7 @@
 #include "usb_cdc_acm.h"
 #include "usbdescriptors.h"
 #include <config.h>		/* If defined, override Linux identifiers with
-			   	 * vendor specific ones */
+				 * vendor specific ones */
 
 #if 0
 #define TTYDBG(fmt,args...)\
@@ -123,7 +123,7 @@ static struct usb_configuration_descriptor	*configuration_descriptor = 0;
 static struct usb_device_descriptor device_descriptor = {
 	.bLength = sizeof(struct usb_device_descriptor),
 	.bDescriptorType =	USB_DT_DEVICE,
-	.bcdUSB = 		cpu_to_le16(USB_BCD_VERSION),
+	.bcdUSB =		cpu_to_le16(USB_BCD_VERSION),
 	.bDeviceSubClass =	0x00,
 	.bDeviceProtocol =	0x00,
 	.bMaxPacketSize0 =	EP0_MAX_PACKET_SIZE,
@@ -163,11 +163,11 @@ static struct acm_config_desc acm_configuration_descriptors[NUM_CONFIGS] = {
 		.configuration_desc ={
 			.bLength =
 				sizeof(struct usb_configuration_descriptor),
-    			.bDescriptorType = USB_DT_CONFIG,
+			.bDescriptorType = USB_DT_CONFIG,
 			.wTotalLength =
 				cpu_to_le16(sizeof(struct acm_config_desc)),
-	    		.bNumInterfaces = NUM_ACM_INTERFACES,
-    			.bConfigurationValue = 1,
+			.bNumInterfaces = NUM_ACM_INTERFACES,
+			.bConfigurationValue = 1,
 			.iConfiguration = STR_CONFIG,
 			.bmAttributes =
 				BMATTRIBUTE_SELF_POWERED|BMATTRIBUTE_RESERVED,
@@ -269,9 +269,9 @@ static struct acm_config_desc acm_configuration_descriptors[NUM_CONFIGS] = {
 };
 
 static struct rs232_emu rs232_desc={
-		.dter 		=  	115200,
-	   	.stop_bits	=	0x00,
-	   	.parity		=	0x00,
+		.dter		=	115200,
+		.stop_bits	=	0x00,
+		.parity		=	0x00,
 		.data_bits	=	0x08
 };
 
@@ -322,7 +322,7 @@ gserial_configuration_descriptors[NUM_CONFIGS] ={
 					COMMUNICATIONS_NO_PROTOCOL,
 				.iInterface = STR_DATA_INTERFACE
 			},
-  		},
+		},
 		.data_endpoints  = {
 			{
 				.bLength =
@@ -342,7 +342,7 @@ gserial_configuration_descriptors[NUM_CONFIGS] ={
 				.bmAttributes =		USB_ENDPOINT_XFER_BULK,
 				.wMaxPacketSize =
 					cpu_to_le16(CONFIG_USBD_SERIAL_IN_PKTSIZE),
-				.bInterval = 		0xFF,
+				.bInterval =		0xFF,
 			},
 			{
 				.bLength =
@@ -350,7 +350,7 @@ gserial_configuration_descriptors[NUM_CONFIGS] ={
 				.bDescriptorType =	USB_DT_ENDPOINT,
 				.bEndpointAddress =	0x03 | USB_DIR_IN,
 				.bmAttributes =		USB_ENDPOINT_XFER_INT,
-    				.wMaxPacketSize =
+				.wMaxPacketSize =
 					cpu_to_le16(CONFIG_USBD_SERIAL_INT_PKTSIZE),
 				.bInterval =		0xFF,
 			},
@@ -953,14 +953,14 @@ int usbtty_cdc_setup(struct usb_device_request *request, struct urb *urb)
 {
 	switch (request->bRequest){
 
-	   	case ACM_SET_CONTROL_LINE_STATE:	/* Implies DTE ready */
+		case ACM_SET_CONTROL_LINE_STATE:	/* Implies DTE ready */
 			break;
-	   	case ACM_SEND_ENCAPSULATED_COMMAND :	/* Required */
+		case ACM_SEND_ENCAPSULATED_COMMAND :	/* Required */
 			break;
 		case ACM_SET_LINE_ENCODING :		/* DTE stop/parity bits
 							 * per character */
 			break;
-	   	case ACM_GET_ENCAPSULATED_RESPONSE :	/* request response */
+		case ACM_GET_ENCAPSULATED_RESPONSE :	/* request response */
 			break;
 		case ACM_GET_LINE_ENCODING :		/* request DTE rate,
 							 * stop/parity bits */
@@ -968,7 +968,7 @@ int usbtty_cdc_setup(struct usb_device_request *request, struct urb *urb)
 			urb->actual_length = sizeof(rs232_desc);
 
 			break;
-	 	default:
+		default:
 			return 1;
 	}
 	return 0;
diff --git a/drivers/serial/usbtty.h b/drivers/serial/usbtty.h
index 8154e3072e..71c47bc5d9 100644
--- a/drivers/serial/usbtty.h
+++ b/drivers/serial/usbtty.h
@@ -36,7 +36,7 @@
 /* If no VendorID/ProductID is defined in config.h, pretend to be Linux
  * DO NOT Reuse this Vendor/Product setup with protocol incompatible devices */
 
-#define CONFIG_USBD_VENDORID 0x0525 	/* Linux/NetChip */
+#define CONFIG_USBD_VENDORID 0x0525	/* Linux/NetChip */
 #define CONFIG_USBD_PRODUCTID_GSERIAL 0xa4a6	/* gserial */
 #define CONFIG_USBD_PRODUCTID_CDCACM  0xa4a7	/* CDC ACM */
 #define CONFIG_USBD_MANUFACTURER "Das U-Boot"
@@ -55,8 +55,8 @@
 
 #define USBTTY_DEVICE_CLASS	COMMUNICATIONS_DEVICE_CLASS
 
-#define USBTTY_BCD_DEVICE 	0x00
-#define USBTTY_MAXPOWER	  	0x00
+#define USBTTY_BCD_DEVICE	0x00
+#define USBTTY_MAXPOWER		0x00
 
 #define STR_LANG		0x00
 #define STR_MANUFACTURER	0x01
diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c
index b2e3ab9b67..c166ec5023 100644
--- a/drivers/spi/mxc_spi.c
+++ b/drivers/spi/mxc_spi.c
@@ -48,7 +48,7 @@
 #define MXC_CSPICTRL_POL	(1 << 4)
 #define MXC_CSPICTRL_PHA	(1 << 5)
 #define MXC_CSPICTRL_SSCTL	(1 << 6)
-#define MXC_CSPICTRL_SSPOL 	(1 << 7)
+#define MXC_CSPICTRL_SSPOL	(1 << 7)
 #define MXC_CSPICTRL_CHIPSELECT(x)	(((x) & 0x3) << 24)
 #define MXC_CSPICTRL_BITCOUNT(x)	(((x) & 0x1f) << 8)
 #define MXC_CSPICTRL_DATARATE(x)	(((x) & 0x7) << 16)
diff --git a/drivers/usb/Makefile b/drivers/usb/Makefile
index f8ea167b12..252b00e652 100644
--- a/drivers/usb/Makefile
+++ b/drivers/usb/Makefile
@@ -23,7 +23,7 @@
 
 include $(TOPDIR)/config.mk
 
-LIB 	:= $(obj)libusb.a
+LIB	:= $(obj)libusb.a
 
 COBJS-y += isp116x-hcd.o
 COBJS-y += sl811_usb.o
@@ -34,8 +34,8 @@ COBJS-y += usbdcore_mpc8xx.o
 COBJS-y += usbdcore_omap1510.o
 
 COBJS	:= $(COBJS-y)
-SRCS 	:= $(COBJS:.o=.c)
-OBJS 	:= $(addprefix $(obj),$(COBJS))
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
 
 all:	$(LIB)
 
diff --git a/drivers/usb/isp116x-hcd.c b/drivers/usb/isp116x-hcd.c
index ac6703056c..6b9b23bc6e 100644
--- a/drivers/usb/isp116x-hcd.c
+++ b/drivers/usb/isp116x-hcd.c
@@ -135,7 +135,7 @@ static int isp116x_reset(struct isp116x *isp116x);
 			r, isp116x_read_reg32(d, r));		\
 	} else {						\
 		DBG("%-12s[%02x]:     %04x", #r,		\
-			r, isp116x_read_reg16(d, r));  		\
+			r, isp116x_read_reg16(d, r));		\
 	}							\
 }
 
diff --git a/drivers/usb/sl811_usb.c b/drivers/usb/sl811_usb.c
index c1f8427c96..159cc25275 100644
--- a/drivers/usb/sl811_usb.c
+++ b/drivers/usb/sl811_usb.c
@@ -264,7 +264,7 @@ static int sl811_send_packet(struct usb_device *dev, unsigned long pipe, __u8 *b
 			ctrl &= ~SL811_USB_CTRL_SOF;
 
 		sl811_write(SL811_CTRL_A, ctrl);
- 		while (!(sl811_read(SL811_INTRSTS) & SL811_INTR_DONE_A)) {
+		while (!(sl811_read(SL811_INTRSTS) & SL811_INTR_DONE_A)) {
 			if (5*CFG_HZ < get_timer(time_start)) {
 				printf("USB transmit timed out\n");
 				return -USB_ST_CRC_ERR;
diff --git a/drivers/usb/usb_ohci.c b/drivers/usb/usb_ohci.c
index ee0f2e45b1..fd60edbb3d 100644
--- a/drivers/usb/usb_ohci.c
+++ b/drivers/usb/usb_ohci.c
@@ -53,6 +53,9 @@
 
 #if defined(CONFIG_PCI_OHCI)
 # include <pci.h>
+#if !defined(CONFIG_PCI_OHCI_DEVNO)
+#define CONFIG_PCI_OHCI_DEVNO	0
+#endif
 #endif
 
 #include <malloc.h>
@@ -1218,9 +1221,9 @@ pkt_print(NULL, dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe
 	}
 
 	bmRType_bReq  = cmd->requesttype | (cmd->request << 8);
-	wValue	      = cpu_to_le16 (cmd->value);
-	wIndex	      = cpu_to_le16 (cmd->index);
-	wLength	      = cpu_to_le16 (cmd->length);
+	wValue	      = le16_to_cpu (cmd->value);
+	wIndex	      = le16_to_cpu (cmd->index);
+	wLength	      = le16_to_cpu (cmd->length);
 
 	info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x",
 		dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength);
@@ -1818,7 +1821,7 @@ int usb_lowlevel_init(void)
 	gohci.sleeping = 0;
 	gohci.irq = -1;
 #ifdef CONFIG_PCI_OHCI
-	pdev = pci_find_devices(ohci_pci_ids, 0);
+	pdev = pci_find_devices(ohci_pci_ids, CONFIG_PCI_OHCI_DEVNO);
 
 	if (pdev != -1) {
 		u16 vid, did;
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 0e40f2afa9..9d2f65b7f8 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -23,7 +23,7 @@
 
 include $(TOPDIR)/config.mk
 
-LIB 	:= $(obj)libvideo.a
+LIB	:= $(obj)libvideo.a
 
 COBJS-y += ati_radeon_fb.o
 COBJS-y += cfb_console.o
@@ -36,8 +36,8 @@ COBJS-y += smiLynxEM.o
 COBJS-y += videomodes.o
 
 COBJS	:= $(COBJS-y)
-SRCS 	:= $(COBJS:.o=.c)
-OBJS 	:= $(addprefix $(obj),$(COBJS))
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
 
 all:	$(LIB)
 
diff --git a/drivers/video/ati_radeon_fb.h b/drivers/video/ati_radeon_fb.h
index b5c4b8b577..e981f95246 100644
--- a/drivers/video/ati_radeon_fb.h
+++ b/drivers/video/ati_radeon_fb.h
@@ -47,20 +47,20 @@ struct radeonfb_info {
 	char name[20];
 
 	struct pci_device_id	pdev;
-	u16 			family;
+	u16			family;
 
-	u32 			fb_base_phys;
-	u32 			mmio_base_phys;
+	u32			fb_base_phys;
+	u32			mmio_base_phys;
 
-	void 			*mmio_base;
-	void 			*fb_base;
+	void			*mmio_base;
+	void			*fb_base;
 
 	u32			video_ram;
 	u32			mapped_vram;
 	int			vram_width;
 	int			vram_ddr;
 
-	u32 			fb_local_base;
+	u32			fb_local_base;
 };
 
 #define INREG8(addr)		readb((rinfo->mmio_base)+addr)
@@ -202,7 +202,7 @@ struct radeon_regs {
 	u32		crtc2_pitch;
 
 	/* Flat panel regs */
-	u32 		fp_crtc_h_total_disp;
+	u32		fp_crtc_h_total_disp;
 	u32		fp_crtc_v_total_disp;
 	u32		fp_gen_cntl;
 	u32		fp2_gen_cntl;
diff --git a/examples/sched.c b/examples/sched.c
index ae01e0b05d..b32766fed1 100644
--- a/examples/sched.c
+++ b/examples/sched.c
@@ -199,7 +199,7 @@ static void thread_yield (void)
 
 	PDEBUG ("thread_yield: current tid=%d", current_tid);
 
-#define SWITCH(new) 							\
+#define SWITCH(new)							\
 	if(lthreads[new].state == STATE_RUNNABLE) {			\
 		PDEBUG("thread_yield: %d match, ctx=0x%08x",		\
 			new,						\
@@ -207,11 +207,11 @@ static void thread_yield (void)
 		if(setjmp(lthreads[current_tid].context) == 0) {	\
 			current_tid = new;				\
 			PDEBUG("thread_yield: tid %d returns 0",	\
-				new); 					\
+				new);					\
 			longjmp(lthreads[new].context, 1);		\
 		} else {						\
 			PDEBUG("thread_yield: tid %d returns 1",	\
-				new); 					\
+				new);					\
 			return;						\
 		}							\
 	}
diff --git a/examples/smc91111_eeprom.c b/examples/smc91111_eeprom.c
index f5d8c6ab42..62347c7e32 100644
--- a/examples/smc91111_eeprom.c
+++ b/examples/smc91111_eeprom.c
@@ -41,7 +41,7 @@
 #define SMC_BASE_ADDRESS CONFIG_SMC91111_BASE
 #define EEPROM		0x1;
 #define MAC		0x2;
-#define	UNKNOWN 	0x4;
+#define	UNKNOWN		0x4;
 
 void dump_reg (void);
 void dump_eeprom (void);
diff --git a/examples/timer.c b/examples/timer.c
index 13ec06f02c..6628b21de9 100644
--- a/examples/timer.c
+++ b/examples/timer.c
@@ -253,7 +253,7 @@ int timer (int argc, char *argv[])
 			);
 #endif
 	    } else {
-	    	printf ("\nEnter: q - quit, b - start timer, e - stop timer, ? - get status\n");
+		printf ("\nEnter: q - quit, b - start timer, e - stop timer, ? - get status\n");
 	    }
 	    printf (usage);
 	}
diff --git a/fs/jffs2/jffs2_1pass.c b/fs/jffs2/jffs2_1pass.c
index a3304384f2..1993dc2359 100644
--- a/fs/jffs2/jffs2_1pass.c
+++ b/fs/jffs2/jffs2_1pass.c
@@ -52,7 +52,7 @@
  * for a bootloader as small and simple as possible. Instead of worring about
  * unneccesary data copies, node scans, etc, I just optimized for the known
  * common case, a kernel, which looks like:
- * 	(1) most pages are 4096 bytes
+ *	(1) most pages are 4096 bytes
  *	(2) version numbers are somewhat sorted in acsending order
  *	(3) multiple compressed blocks making up one page is uncommon
  *
@@ -125,13 +125,13 @@
 #include "jffs2_private.h"
 
 
-#define	NODE_CHUNK  	1024	/* size of memory allocation chunk in b_nodes */
-#define	SPIN_BLKSIZE	18  	/* spin after having scanned 1<<BLKSIZE bytes */
+#define	NODE_CHUNK	1024	/* size of memory allocation chunk in b_nodes */
+#define	SPIN_BLKSIZE	18	/* spin after having scanned 1<<BLKSIZE bytes */
 
 /* Debugging switches */
 #undef	DEBUG_DIRENTS		/* print directory entry list after scan */
 #undef	DEBUG_FRAGMENTS		/* print fragment list after scan */
-#undef	DEBUG   			/* enable debugging messages */
+#undef	DEBUG			/* enable debugging messages */
 
 
 #ifdef  DEBUG
@@ -741,7 +741,7 @@ jffs2_1pass_find_inode(struct b_lists * pL, const char *name, u32 pino)
 			}
 
 			if (jDir->version == version && inode != 0) {
-			    	/* I'm pretty sure this isn't legal */
+				/* I'm pretty sure this isn't legal */
 				putstr(" ** ERROR ** ");
 				putnstr(jDir->name, jDir->nsize);
 				putLabeledWord(" has dup version =", version);
@@ -959,13 +959,13 @@ jffs2_1pass_resolve_inode(struct b_lists * pL, u32 ino)
 	for(b = pL->dir.listHead; b; b = b->next) {
 		jDir = (struct jffs2_raw_dirent *) get_node_mem(b->offset);
 		if (ino == jDir->ino) {
-		    	if (jDir->version < version) {
+			if (jDir->version < version) {
 				put_fl_mem(jDir);
 				continue;
 			}
 
 			if (jDir->version == version && jDirFoundType) {
-			    	/* I'm pretty sure this isn't legal */
+				/* I'm pretty sure this isn't legal */
 				putstr(" ** ERROR ** ");
 				putnstr(jDir->name, jDir->nsize);
 				putLabeledWord(" has dup version (resolve) = ",
@@ -1151,7 +1151,7 @@ dump_dirents(struct b_lists *pL)
 		putLabeledWord("\tbuild_list: type = ", jDir->type);
 		putLabeledWord("\tbuild_list: node_crc = ", jDir->node_crc);
 		putLabeledWord("\tbuild_list: name_crc = ", jDir->name_crc);
-		putLabeledWord("\tbuild_list: offset = ", b->offset); 	/* FIXME: ? [RS] */
+		putLabeledWord("\tbuild_list: offset = ", b->offset);	/* FIXME: ? [RS] */
 		b = b->next;
 		put_fl_mem(jDir);
 	}
@@ -1183,7 +1183,7 @@ jffs2_1pass_build_lists(struct part_info * part)
 
 	/* start at the beginning of the partition */
 	while (offset < max) {
-	    	if ((oldoffset >> SPIN_BLKSIZE) != (offset >> SPIN_BLKSIZE)) {
+		if ((oldoffset >> SPIN_BLKSIZE) != (offset >> SPIN_BLKSIZE)) {
 			printf("\b\b%c ", spinner[counter++ % sizeof(spinner)]);
 			oldoffset = offset;
 		}
diff --git a/fs/jffs2/jffs2_nand_1pass.c b/fs/jffs2/jffs2_nand_1pass.c
index 3a4c64985a..d95f5513b9 100644
--- a/fs/jffs2/jffs2_nand_1pass.c
+++ b/fs/jffs2/jffs2_nand_1pass.c
@@ -758,7 +758,7 @@ dump_dirents(struct b_lists *pL)
 		putLabeledWord("\tbuild_list: type = ", jDir->type);
 		putLabeledWord("\tbuild_list: node_crc = ", jDir->node_crc);
 		putLabeledWord("\tbuild_list: name_crc = ", jDir->name_crc);
-		putLabeledWord("\tbuild_list: offset = ", b->offset); 	/* FIXME: ? [RS] */
+		putLabeledWord("\tbuild_list: offset = ", b->offset);	/* FIXME: ? [RS] */
 		b = b->next;
 		put_fl_mem(jDir);
 	}
diff --git a/fs/reiserfs/dev.c b/fs/reiserfs/dev.c
index 6b36c06b5c..46dc41463f 100644
--- a/fs/reiserfs/dev.c
+++ b/fs/reiserfs/dev.c
@@ -35,7 +35,7 @@ int reiserfs_set_blk_dev(block_dev_desc_t *rbdd, int part)
 	reiserfs_block_dev_desc = rbdd;
 
 	if (part == 0) {
- 		/* disk doesn't use partition table */
+		/* disk doesn't use partition table */
 		part_info.start = 0;
 		part_info.size = rbdd->lba;
 		part_info.blksz = rbdd->blksz;
diff --git a/fs/reiserfs/mode_string.c b/fs/reiserfs/mode_string.c
index ae98834df4..3e57ee4a93 100644
--- a/fs/reiserfs/mode_string.c
+++ b/fs/reiserfs/mode_string.c
@@ -1,4 +1,3 @@
-/* vi: set sw=4 ts=4: */
 /*
  * mode_string implementation for busybox
  *
diff --git a/fs/reiserfs/reiserfs_private.h b/fs/reiserfs/reiserfs_private.h
index d0197cb804..ef7eaf01a2 100644
--- a/fs/reiserfs/reiserfs_private.h
+++ b/fs/reiserfs/reiserfs_private.h
@@ -44,37 +44,37 @@
 /* This is the new super block of a journaling reiserfs system */
 struct reiserfs_super_block
 {
-  __u32 s_block_count;			/* blocks count         */
-  __u32 s_free_blocks;                  /* free blocks count    */
-  __u32 s_root_block;           	/* root block number    */
-  __u32 s_journal_block;           	/* journal block number    */
-  __u32 s_journal_dev;           	/* journal device number  */
-  __u32 s_journal_size; 		/* size of the journal on FS creation.  used to make sure they don't overflow it */
-  __u32 s_journal_trans_max;            /* max number of blocks in a transaction.  */
-  __u32 s_journal_magic;                /* random value made on fs creation */
-  __u32 s_journal_max_batch;            /* max number of blocks to batch into a trans */
-  __u32 s_journal_max_commit_age;       /* in seconds, how old can an async commit be */
-  __u32 s_journal_max_trans_age;        /* in seconds, how old can a transaction be */
-  __u16 s_blocksize;                   	/* block size           */
-  __u16 s_oid_maxsize;			/* max size of object id array  */
+  __u32 s_block_count;			/* blocks count		*/
+  __u32 s_free_blocks;			/* free blocks count	*/
+  __u32 s_root_block;			/* root block number	*/
+  __u32 s_journal_block;		/* journal block number    */
+  __u32 s_journal_dev;			/* journal device number  */
+  __u32 s_journal_size;			/* size of the journal on FS creation.	used to make sure they don't overflow it */
+  __u32 s_journal_trans_max;		/* max number of blocks in a transaction.  */
+  __u32 s_journal_magic;		/* random value made on fs creation */
+  __u32 s_journal_max_batch;		/* max number of blocks to batch into a trans */
+  __u32 s_journal_max_commit_age;	/* in seconds, how old can an async commit be */
+  __u32 s_journal_max_trans_age;	/* in seconds, how old can a transaction be */
+  __u16 s_blocksize;			/* block size		*/
+  __u16 s_oid_maxsize;			/* max size of object id array	*/
   __u16 s_oid_cursize;			/* current size of object id array */
-  __u16 s_state;                       	/* valid or error       */
-  char s_magic[16];                     /* reiserfs magic string indicates that file system is reiserfs */
-  __u16 s_tree_height;                  /* height of disk tree */
-  __u16 s_bmap_nr;                      /* amount of bitmap blocks needed to address each block of file system */
+  __u16 s_state;			/* valid or error	*/
+  char s_magic[16];			/* reiserfs magic string indicates that file system is reiserfs */
+  __u16 s_tree_height;			/* height of disk tree */
+  __u16 s_bmap_nr;			/* amount of bitmap blocks needed to address each block of file system */
   __u16 s_version;
   char s_unused[128];			/* zero filled by mkreiserfs */
 };
 
 
-#define sb_root_block(sbp)            (__le32_to_cpu((sbp)->s_root_block))
-#define sb_journal_block(sbp)         (__le32_to_cpu((sbp)->s_journal_block))
+#define sb_root_block(sbp)	      (__le32_to_cpu((sbp)->s_root_block))
+#define sb_journal_block(sbp)	      (__le32_to_cpu((sbp)->s_journal_block))
 #define set_sb_journal_block(sbp,v)   ((sbp)->s_journal_block = __cpu_to_le32(v))
-#define sb_journal_size(sbp)          (__le32_to_cpu((sbp)->s_journal_size))
-#define sb_blocksize(sbp)             (__le16_to_cpu((sbp)->s_blocksize))
+#define sb_journal_size(sbp)	      (__le32_to_cpu((sbp)->s_journal_size))
+#define sb_blocksize(sbp)	      (__le16_to_cpu((sbp)->s_blocksize))
 #define set_sb_blocksize(sbp,v)       ((sbp)->s_blocksize = __cpu_to_le16(v))
-#define sb_version(sbp)               (__le16_to_cpu((sbp)->s_version))
-#define set_sb_version(sbp,v)         ((sbp)->s_version = __cpu_to_le16(v))
+#define sb_version(sbp)		      (__le16_to_cpu((sbp)->s_version))
+#define set_sb_version(sbp,v)	      ((sbp)->s_version = __cpu_to_le16(v))
 
 
 #define REISERFS_MAX_SUPPORTED_VERSION 2
@@ -137,7 +137,7 @@ struct offset_v1
    * hashing the name and using few bits (23 or more) of the resulting
    * hash, and generation number that allows distinguishing names with
    * hash collisions. If number of collisions overflows generation
-   * number, we return EEXIST.  High order bit is 0 always
+   * number, we return EEXIST.	High order bit is 0 always
    */
   __u32 k_offset;
   __u32 k_uniqueness;
@@ -153,7 +153,7 @@ struct offset_v2 {
    * hashing the name and using few bits (23 or more) of the resulting
    * hash, and generation number that allows distinguishing names with
    * hash collisions. If number of collisions overflows generation
-   * number, we return EEXIST.  High order bit is 0 always
+   * number, we return EEXIST.	High order bit is 0 always
    */
 
 #if defined(__LITTLE_ENDIAN_BITFIELD)
@@ -192,8 +192,8 @@ static inline loff_t offset_v2_k_offset( const struct offset_v2 *v2 )
     return tmp.offset_v2.k_offset;
 }
 #elif (__BYTE_ORDER == __LITTLE_ENDIAN)
-# define offset_v2_k_type(v2)           ((v2)->k_type)
-# define offset_v2_k_offset(v2)         ((v2)->k_offset)
+# define offset_v2_k_type(v2)		((v2)->k_type)
+# define offset_v2_k_offset(v2)		((v2)->k_offset)
 #else
 #error "__BYTE_ORDER must be __LITTLE_ENDIAN or __BIG_ENDIAN"
 #endif
@@ -219,14 +219,14 @@ struct key
    or internal node, and not the header of an unformatted node. */
 struct block_head
 {
-  __u16 blk_level;        /* Level of a block in the tree. */
-  __u16 blk_nr_item;      /* Number of keys/items in a block. */
+  __u16 blk_level;	  /* Level of a block in the tree. */
+  __u16 blk_nr_item;	  /* Number of keys/items in a block. */
   __u16 blk_free_space;   /* Block free space in bytes. */
   struct key  blk_right_delim_key; /* Right delimiting key for this block (supported for leaf level nodes
 				      only) */
 };
 #define BLKH_SIZE (sizeof (struct block_head))
-#define DISK_LEAF_NODE_LEVEL  1 /* Leaf node level.                       */
+#define DISK_LEAF_NODE_LEVEL  1 /* Leaf node level.			  */
 
 struct item_head
 {
@@ -245,7 +245,7 @@ struct item_head
 		   number of directory entries in the directory item. */
 		__u16 ih_entry_count;
 	} __attribute__ ((__packed__)) u;
-	__u16 ih_item_len;           /* total size of the item body */
+	__u16 ih_item_len;	     /* total size of the item body */
 	__u16 ih_item_location;      /* an offset to the item body
 				      * within the block */
 	__u16 ih_version;	     /* 0 for all old items, 2 for new
@@ -254,13 +254,13 @@ struct item_head
 					done */
 } __attribute__ ((__packed__));
 
-/* size of item header     */
+/* size of item header	   */
 #define IH_SIZE (sizeof (struct item_head))
 
 #define ITEM_VERSION_1 0
 #define ITEM_VERSION_2 1
 
-#define ih_version(ih)    (__le16_to_cpu((ih)->ih_version))
+#define ih_version(ih)	  (__le16_to_cpu((ih)->ih_version))
 
 #define IH_KEY_OFFSET(ih) (ih_version(ih) == ITEM_VERSION_1 \
 			   ? __le32_to_cpu((ih)->ih_key.u.v1.k_offset) \
@@ -271,13 +271,13 @@ struct item_head
 				 : offset_v2_k_type(&((ih)->ih_key.u.v2)) == V2_##type)
 
 /***************************************************************************/
-/*                      DISK CHILD                                         */
+/*			DISK CHILD					   */
 /***************************************************************************/
 /* Disk child pointer: The pointer from an internal node of the tree
    to a node that is on disk. */
 struct disk_child {
-  __u32       dc_block_number;              /* Disk child's block number. */
-  __u16       dc_size;		            /* Disk child's used space.   */
+  __u32       dc_block_number;		    /* Disk child's block number. */
+  __u16       dc_size;			    /* Disk child's used space.   */
   __u16       dc_reserved;
 };
 
@@ -297,7 +297,7 @@ struct stat_data_v1
     __u16 sd_gid;		/* group */
     __u32 sd_size;	/* file size */
     __u32 sd_atime;	/* time of last access */
-    __u32 sd_mtime;	/* time file was last modified  */
+    __u32 sd_mtime;	/* time file was last modified	*/
     __u32 sd_ctime;	/* time inode (stat data) was last changed (except changes to sd_atime and sd_mtime) */
     union {
 	__u32 sd_rdev;
@@ -314,25 +314,25 @@ struct stat_data_v1
 				   policy.  Someday.  -Hans */
 } __attribute__ ((__packed__));
 
-#define stat_data_v1(ih)        (ih_version(ih) == ITEM_VERSION_1)
-#define sd_v1_mode(sdp)         ((sdp)->sd_mode)
-#define sd_v1_nlink(sdp)        (__le16_to_cpu((sdp)->sd_nlink))
-#define sd_v1_uid(sdp)          (__le16_to_cpu((sdp)->sd_uid))
-#define sd_v1_gid(sdp)          (__le16_to_cpu((sdp)->sd_gid))
-#define sd_v1_size(sdp)         (__le32_to_cpu((sdp)->sd_size))
-#define sd_v1_mtime(sdp)        (__le32_to_cpu((sdp)->sd_mtime))
+#define stat_data_v1(ih)	(ih_version(ih) == ITEM_VERSION_1)
+#define sd_v1_mode(sdp)		((sdp)->sd_mode)
+#define sd_v1_nlink(sdp)	(__le16_to_cpu((sdp)->sd_nlink))
+#define sd_v1_uid(sdp)		(__le16_to_cpu((sdp)->sd_uid))
+#define sd_v1_gid(sdp)		(__le16_to_cpu((sdp)->sd_gid))
+#define sd_v1_size(sdp)		(__le32_to_cpu((sdp)->sd_size))
+#define sd_v1_mtime(sdp)	(__le32_to_cpu((sdp)->sd_mtime))
 
 /* Stat Data on disk (reiserfs version of UFS disk inode minus the
    address blocks) */
 struct stat_data {
     __u16 sd_mode;	/* file type, permissions */
-    __u16 sd_attrs;     /* persistent inode flags */
+    __u16 sd_attrs;	/* persistent inode flags */
     __u32 sd_nlink;	/* number of hard links */
     __u64 sd_size;	/* file size */
     __u32 sd_uid;		/* owner */
     __u32 sd_gid;		/* group */
     __u32 sd_atime;	/* time of last access */
-    __u32 sd_mtime;	/* time file was last modified  */
+    __u32 sd_mtime;	/* time file was last modified	*/
     __u32 sd_ctime;	/* time inode (stat data) was last changed (except changes to sd_atime and sd_mtime) */
     __u32 sd_blocks;
     union {
@@ -350,16 +350,16 @@ struct stat_data {
   } __attribute__ ((__packed__)) u;
 } __attribute__ ((__packed__));
 
-#define stat_data_v2(ih)        (ih_version(ih) == ITEM_VERSION_2)
-#define sd_v2_mode(sdp)         (__le16_to_cpu((sdp)->sd_mode))
-#define sd_v2_nlink(sdp)        (__le32_to_cpu((sdp)->sd_nlink))
-#define sd_v2_size(sdp)         (__le64_to_cpu((sdp)->sd_size))
-#define sd_v2_uid(sdp)          (__le32_to_cpu((sdp)->sd_uid))
-#define sd_v2_gid(sdp)          (__le32_to_cpu((sdp)->sd_gid))
-#define sd_v2_mtime(sdp)        (__le32_to_cpu((sdp)->sd_mtime))
+#define stat_data_v2(ih)	(ih_version(ih) == ITEM_VERSION_2)
+#define sd_v2_mode(sdp)		(__le16_to_cpu((sdp)->sd_mode))
+#define sd_v2_nlink(sdp)	(__le32_to_cpu((sdp)->sd_nlink))
+#define sd_v2_size(sdp)		(__le64_to_cpu((sdp)->sd_size))
+#define sd_v2_uid(sdp)		(__le32_to_cpu((sdp)->sd_uid))
+#define sd_v2_gid(sdp)		(__le32_to_cpu((sdp)->sd_gid))
+#define sd_v2_mtime(sdp)	(__le32_to_cpu((sdp)->sd_mtime))
 
-#define sd_mode(sdp)         (__le16_to_cpu((sdp)->sd_mode))
-#define sd_size(sdp)         (__le32_to_cpu((sdp)->sd_size))
+#define sd_mode(sdp)	     (__le16_to_cpu((sdp)->sd_mode))
+#define sd_size(sdp)	     (__le32_to_cpu((sdp)->sd_size))
 #define sd_size_hi(sdp)      (__le32_to_cpu((sdp)->sd_size_hi))
 
 struct reiserfs_de_head
@@ -376,11 +376,11 @@ struct reiserfs_de_head
 };
 
 #define DEH_SIZE (sizeof (struct reiserfs_de_head))
-#define deh_offset(p_deh)         (__le32_to_cpu((p_deh)->deh_offset))
-#define deh_dir_id(p_deh)         (__le32_to_cpu((p_deh)->deh_dir_id))
-#define deh_objectid(p_deh)       (__le32_to_cpu((p_deh)->deh_objectid))
-#define deh_location(p_deh)       (__le16_to_cpu((p_deh)->deh_location))
-#define deh_state(p_deh)          (__le16_to_cpu((p_deh)->deh_state))
+#define deh_offset(p_deh)	  (__le32_to_cpu((p_deh)->deh_offset))
+#define deh_dir_id(p_deh)	  (__le32_to_cpu((p_deh)->deh_dir_id))
+#define deh_objectid(p_deh)	  (__le32_to_cpu((p_deh)->deh_objectid))
+#define deh_location(p_deh)	  (__le16_to_cpu((p_deh)->deh_location))
+#define deh_state(p_deh)	  (__le16_to_cpu((p_deh)->deh_state))
 
 
 #define DEH_Statdata (1 << 0)			/* not used now */
@@ -413,7 +413,7 @@ struct reiserfs_de_head
 #define S_ISLNK(mode) (((mode) & 0170000) == 0120000)
 
 #define PATH_MAX       1024	/* include/linux/limits.h */
-#define MAX_LINK_COUNT    5	/* number of symbolic links to follow */
+#define MAX_LINK_COUNT	  5	/* number of symbolic links to follow */
 
 /* The size of the node cache */
 #define FSYSREISER_CACHE_SIZE 24*1024
@@ -449,9 +449,9 @@ struct fsys_reiser_info
   /* The current depth of the reiser tree. */
   __u16 tree_depth;
   /* SECTOR_SIZE << blocksize_shift == blocksize. */
-  __u8  blocksize_shift;
+  __u8	blocksize_shift;
   /* 1 << full_blocksize_shift == blocksize. */
-  __u8  fullblocksize_shift;
+  __u8	fullblocksize_shift;
   /* The reiserfs block size  (must be a power of 2) */
   __u16 blocksize;
   /* The number of cached tree nodes */
@@ -466,14 +466,14 @@ struct fsys_reiser_info
 /* The cached s+tree blocks in FSYS_BUF,  see below
  * for a more detailed description.
  */
-#define ROOT     ((char *) ((int) FSYS_BUF))
+#define ROOT	 ((char *) ((int) FSYS_BUF))
 #define CACHE(i) (ROOT + ((i) << INFO->fullblocksize_shift))
-#define LEAF     CACHE (DISK_LEAF_NODE_LEVEL)
+#define LEAF	 CACHE (DISK_LEAF_NODE_LEVEL)
 
 #define BLOCKHEAD(cache) ((struct block_head *) cache)
-#define ITEMHEAD         ((struct item_head  *) ((int) LEAF + BLKH_SIZE))
-#define KEY(cache)       ((struct key        *) ((int) cache + BLKH_SIZE))
-#define DC(cache)        ((struct disk_child *) \
+#define ITEMHEAD	 ((struct item_head  *) ((int) LEAF + BLKH_SIZE))
+#define KEY(cache)	 ((struct key	     *) ((int) cache + BLKH_SIZE))
+#define DC(cache)	 ((struct disk_child *) \
 			  ((int) cache + BLKH_SIZE + KEY_SIZE * nr_item))
 /* The fsys_reiser_info block.
  */
@@ -487,8 +487,8 @@ struct fsys_reiser_info
  * this list is stopped with a 0xffffffff marker and the remaining
  * uncommitted transactions aren't cached.
  */
-#define JOURNAL_START    ((__u32 *) (INFO + 1))
-#define JOURNAL_END      ((__u32 *) (FSYS_BUF + FSYS_BUFLEN))
+#define JOURNAL_START	 ((__u32 *) (INFO + 1))
+#define JOURNAL_END	 ((__u32 *) (FSYS_BUF + FSYS_BUFLEN))
 
 
 static __inline__ unsigned long
diff --git a/include/ACEX1K.h b/include/ACEX1K.h
index f249d6402d..6ea0eed952 100644
--- a/include/ACEX1K.h
+++ b/include/ACEX1K.h
@@ -73,9 +73,9 @@ typedef struct {
  * Filesize of an *.rbf file is 166965 Bytes
  */
 #if 0
-#define Altera_EP1K100_SIZE  	1337000/8	/* 167125 Bytes */
+#define Altera_EP1K100_SIZE	1337000/8	/* 167125 Bytes */
 #endif
-#define Altera_EP1K100_SIZE  	(166965*8)
+#define Altera_EP1K100_SIZE	(166965*8)
 
 #define Altera_EP2C35_SIZE	883905
 
diff --git a/include/SA-1100.h b/include/SA-1100.h
index 9985783e58..7589df238a 100644
--- a/include/SA-1100.h
+++ b/include/SA-1100.h
@@ -1,20 +1,20 @@
 /*
- *	FILE    	SA-1100.h
+ *	FILE		SA-1100.h
  *
- *	Version 	1.2
- *	Author  	Copyright (c) Marc A. Viredaz, 1998
- *	        	DEC Western Research Laboratory, Palo Alto, CA
- *	Date    	January 1998 (April 1997)
- *	System  	StrongARM SA-1100
+ *	Version		1.2
+ *	Author		Copyright (c) Marc A. Viredaz, 1998
+ *			DEC Western Research Laboratory, Palo Alto, CA
+ *	Date		January 1998 (April 1997)
+ *	System		StrongARM SA-1100
  *	Language	C or ARM Assembly
- *	Purpose 	Definition of constants related to the StrongARM
- *	        	SA-1100 microprocessor (Advanced RISC Machine (ARM)
- *	        	architecture version 4). This file is based on the
- *	        	StrongARM SA-1100 data sheet version 2.2.
+ *	Purpose		Definition of constants related to the StrongARM
+ *			SA-1100 microprocessor (Advanced RISC Machine (ARM)
+ *			architecture version 4). This file is based on the
+ *			StrongARM SA-1100 data sheet version 2.2.
  *
- *	        	Language-specific definitions are selected by the
- *	        	macro "LANGUAGE", which should be defined as either
- *	        	"C" (default) or "Assembly".
+ *			Language-specific definitions are selected by the
+ *			macro "LANGUAGE", which should be defined as either
+ *			"C" (default) or "Assembly".
  */
 
 
@@ -32,17 +32,17 @@
 
 #include <asm/arch-sa1100/bitfield.h>
 
-#define C       	0
+#define C		0
 #define Assembly	1
 
 
 #if LANGUAGE == C
-typedef unsigned short  Word16 ;
-typedef unsigned int    Word32 ;
-typedef Word32          Word ;
-typedef Word            Quad [4] ;
-typedef void            *Address ;
-typedef void            (*ExcpHndlr) (void) ;
+typedef unsigned short	Word16 ;
+typedef unsigned int	Word32 ;
+typedef Word32		Word ;
+typedef Word		Quad [4] ;
+typedef void		*Address ;
+typedef void		(*ExcpHndlr) (void) ;
 #endif /* LANGUAGE == C */
 
 
@@ -50,65 +50,65 @@ typedef void            (*ExcpHndlr) (void) ;
  * Memory
  */
 
-#define MemBnkSp	0x08000000	/* Memory Bank Space [byte]        */
+#define MemBnkSp	0x08000000	/* Memory Bank Space [byte]	   */
 
 #define StMemBnkSp	MemBnkSp	/* Static Memory Bank Space [byte] */
-#define StMemBnk0Sp	StMemBnkSp	/* Static Memory Bank 0 Space      */
-					/* [byte]                          */
-#define StMemBnk1Sp	StMemBnkSp	/* Static Memory Bank 1 Space      */
-					/* [byte]                          */
-#define StMemBnk2Sp	StMemBnkSp	/* Static Memory Bank 2 Space      */
-					/* [byte]                          */
-#define StMemBnk3Sp	StMemBnkSp	/* Static Memory Bank 3 Space      */
-					/* [byte]                          */
-
-#define DRAMBnkSp	MemBnkSp	/* DRAM Bank Space [byte]          */
-#define DRAMBnk0Sp	DRAMBnkSp	/* DRAM Bank 0 Space [byte]        */
-#define DRAMBnk1Sp	DRAMBnkSp	/* DRAM Bank 1 Space [byte]        */
-#define DRAMBnk2Sp	DRAMBnkSp	/* DRAM Bank 2 Space [byte]        */
-#define DRAMBnk3Sp	DRAMBnkSp	/* DRAM Bank 3 Space [byte]        */
+#define StMemBnk0Sp	StMemBnkSp	/* Static Memory Bank 0 Space	   */
+					/* [byte]			   */
+#define StMemBnk1Sp	StMemBnkSp	/* Static Memory Bank 1 Space	   */
+					/* [byte]			   */
+#define StMemBnk2Sp	StMemBnkSp	/* Static Memory Bank 2 Space	   */
+					/* [byte]			   */
+#define StMemBnk3Sp	StMemBnkSp	/* Static Memory Bank 3 Space	   */
+					/* [byte]			   */
+
+#define DRAMBnkSp	MemBnkSp	/* DRAM Bank Space [byte]	   */
+#define DRAMBnk0Sp	DRAMBnkSp	/* DRAM Bank 0 Space [byte]	   */
+#define DRAMBnk1Sp	DRAMBnkSp	/* DRAM Bank 1 Space [byte]	   */
+#define DRAMBnk2Sp	DRAMBnkSp	/* DRAM Bank 2 Space [byte]	   */
+#define DRAMBnk3Sp	DRAMBnkSp	/* DRAM Bank 3 Space [byte]	   */
 
 #define ZeroMemSp	MemBnkSp	/* Zero Memory bank Space [byte]   */
 
-#define _StMemBnk(Nb)	        	/* Static Memory Bank [0..3]       */ \
+#define _StMemBnk(Nb)			/* Static Memory Bank [0..3]	   */ \
 			(0x00000000 + (Nb)*StMemBnkSp)
-#define _StMemBnk0	_StMemBnk (0)	/* Static Memory Bank 0            */
-#define _StMemBnk1	_StMemBnk (1)	/* Static Memory Bank 1            */
-#define _StMemBnk2	_StMemBnk (2)	/* Static Memory Bank 2            */
-#define _StMemBnk3	_StMemBnk (3)	/* Static Memory Bank 3            */
+#define _StMemBnk0	_StMemBnk (0)	/* Static Memory Bank 0		   */
+#define _StMemBnk1	_StMemBnk (1)	/* Static Memory Bank 1		   */
+#define _StMemBnk2	_StMemBnk (2)	/* Static Memory Bank 2		   */
+#define _StMemBnk3	_StMemBnk (3)	/* Static Memory Bank 3		   */
 
 #if LANGUAGE == C
-typedef Quad    	StMemBnkType [StMemBnkSp/sizeof (Quad)] ;
-#define StMemBnk	        	/* Static Memory Bank [0..3]       */ \
+typedef Quad		StMemBnkType [StMemBnkSp/sizeof (Quad)] ;
+#define StMemBnk			/* Static Memory Bank [0..3]	   */ \
 			((StMemBnkType *) io_p2v (_StMemBnk (0)))
-#define StMemBnk0	(StMemBnk [0])	/* Static Memory Bank 0            */
-#define StMemBnk1	(StMemBnk [1])	/* Static Memory Bank 1            */
-#define StMemBnk2	(StMemBnk [2])	/* Static Memory Bank 2            */
-#define StMemBnk3	(StMemBnk [3])	/* Static Memory Bank 3            */
+#define StMemBnk0	(StMemBnk [0])	/* Static Memory Bank 0		   */
+#define StMemBnk1	(StMemBnk [1])	/* Static Memory Bank 1		   */
+#define StMemBnk2	(StMemBnk [2])	/* Static Memory Bank 2		   */
+#define StMemBnk3	(StMemBnk [3])	/* Static Memory Bank 3		   */
 #endif /* LANGUAGE == C */
 
-#define _DRAMBnk(Nb)	        	/* DRAM Bank [0..3]                */ \
+#define _DRAMBnk(Nb)			/* DRAM Bank [0..3]		   */ \
 			(0xC0000000 + (Nb)*DRAMBnkSp)
-#define _DRAMBnk0	_DRAMBnk (0)	/* DRAM Bank 0                     */
-#define _DRAMBnk1	_DRAMBnk (1)	/* DRAM Bank 1                     */
-#define _DRAMBnk2	_DRAMBnk (2)	/* DRAM Bank 2                     */
-#define _DRAMBnk3	_DRAMBnk (3)	/* DRAM Bank 3                     */
+#define _DRAMBnk0	_DRAMBnk (0)	/* DRAM Bank 0			   */
+#define _DRAMBnk1	_DRAMBnk (1)	/* DRAM Bank 1			   */
+#define _DRAMBnk2	_DRAMBnk (2)	/* DRAM Bank 2			   */
+#define _DRAMBnk3	_DRAMBnk (3)	/* DRAM Bank 3			   */
 
 #if LANGUAGE == C
-typedef Quad    	DRAMBnkType [DRAMBnkSp/sizeof (Quad)] ;
-#define DRAMBnk 	        	/* DRAM Bank [0..3]                */ \
+typedef Quad		DRAMBnkType [DRAMBnkSp/sizeof (Quad)] ;
+#define DRAMBnk				/* DRAM Bank [0..3]		   */ \
 			((DRAMBnkType *) io_p2v (_DRAMBnk (0)))
-#define DRAMBnk0	(DRAMBnk [0])	/* DRAM Bank 0                     */
-#define DRAMBnk1	(DRAMBnk [1])	/* DRAM Bank 1                     */
-#define DRAMBnk2	(DRAMBnk [2])	/* DRAM Bank 2                     */
-#define DRAMBnk3	(DRAMBnk [3])	/* DRAM Bank 3                     */
+#define DRAMBnk0	(DRAMBnk [0])	/* DRAM Bank 0			   */
+#define DRAMBnk1	(DRAMBnk [1])	/* DRAM Bank 1			   */
+#define DRAMBnk2	(DRAMBnk [2])	/* DRAM Bank 2			   */
+#define DRAMBnk3	(DRAMBnk [3])	/* DRAM Bank 3			   */
 #endif /* LANGUAGE == C */
 
-#define _ZeroMem	0xE0000000	/* Zero Memory bank                */
+#define _ZeroMem	0xE0000000	/* Zero Memory bank		   */
 
 #if LANGUAGE == C
-typedef Quad    	ZeroMemType [ZeroMemSp/sizeof (Quad)] ;
-#define ZeroMem 	        	/* Zero Memory bank                */ \
+typedef Quad		ZeroMemType [ZeroMemSp/sizeof (Quad)] ;
+#define ZeroMem				/* Zero Memory bank		   */ \
 			(*((ZeroMemType *) io_p2v (_ZeroMem)))
 #endif /* LANGUAGE == C */
 
@@ -118,60 +118,60 @@ typedef Quad    	ZeroMemType [ZeroMemSp/sizeof (Quad)] ;
  */
 
 #define PCMCIAPrtSp	0x04000000	/* PCMCIA Partition Space [byte]   */
-#define PCMCIASp	(4*PCMCIAPrtSp)	/* PCMCIA Space [byte]             */
-#define PCMCIAIOSp	PCMCIAPrtSp	/* PCMCIA I/O Space [byte]         */
+#define PCMCIASp	(4*PCMCIAPrtSp)	/* PCMCIA Space [byte]		   */
+#define PCMCIAIOSp	PCMCIAPrtSp	/* PCMCIA I/O Space [byte]	   */
 #define PCMCIAAttrSp	PCMCIAPrtSp	/* PCMCIA Attribute Space [byte]   */
-#define PCMCIAMemSp	PCMCIAPrtSp	/* PCMCIA Memory Space [byte]      */
+#define PCMCIAMemSp	PCMCIAPrtSp	/* PCMCIA Memory Space [byte]	   */
 
-#define PCMCIA0Sp	PCMCIASp	/* PCMCIA 0 Space [byte]           */
-#define PCMCIA0IOSp	PCMCIAIOSp	/* PCMCIA 0 I/O Space [byte]       */
+#define PCMCIA0Sp	PCMCIASp	/* PCMCIA 0 Space [byte]	   */
+#define PCMCIA0IOSp	PCMCIAIOSp	/* PCMCIA 0 I/O Space [byte]	   */
 #define PCMCIA0AttrSp	PCMCIAAttrSp	/* PCMCIA 0 Attribute Space [byte] */
 #define PCMCIA0MemSp	PCMCIAMemSp	/* PCMCIA 0 Memory Space [byte]    */
 
-#define PCMCIA1Sp	PCMCIASp	/* PCMCIA 1 Space [byte]           */
-#define PCMCIA1IOSp	PCMCIAIOSp	/* PCMCIA 1 I/O Space [byte]       */
+#define PCMCIA1Sp	PCMCIASp	/* PCMCIA 1 Space [byte]	   */
+#define PCMCIA1IOSp	PCMCIAIOSp	/* PCMCIA 1 I/O Space [byte]	   */
 #define PCMCIA1AttrSp	PCMCIAAttrSp	/* PCMCIA 1 Attribute Space [byte] */
 #define PCMCIA1MemSp	PCMCIAMemSp	/* PCMCIA 1 Memory Space [byte]    */
 
-#define _PCMCIA(Nb)	        	/* PCMCIA [0..1]                   */ \
+#define _PCMCIA(Nb)			/* PCMCIA [0..1]		   */ \
 			(0x20000000 + (Nb)*PCMCIASp)
-#define _PCMCIAIO(Nb)	_PCMCIA (Nb)	/* PCMCIA I/O [0..1]               */
-#define _PCMCIAAttr(Nb)	        	/* PCMCIA Attribute [0..1]         */ \
+#define _PCMCIAIO(Nb)	_PCMCIA (Nb)	/* PCMCIA I/O [0..1]		   */
+#define _PCMCIAAttr(Nb)			/* PCMCIA Attribute [0..1]	   */ \
 			(_PCMCIA (Nb) + 2*PCMCIAPrtSp)
-#define _PCMCIAMem(Nb)	        	/* PCMCIA Memory [0..1]            */ \
+#define _PCMCIAMem(Nb)			/* PCMCIA Memory [0..1]		   */ \
 			(_PCMCIA (Nb) + 3*PCMCIAPrtSp)
 
-#define _PCMCIA0	_PCMCIA (0)	/* PCMCIA 0                        */
-#define _PCMCIA0IO	_PCMCIAIO (0)	/* PCMCIA 0 I/O                    */
-#define _PCMCIA0Attr	_PCMCIAAttr (0)	/* PCMCIA 0 Attribute              */
-#define _PCMCIA0Mem	_PCMCIAMem (0)	/* PCMCIA 0 Memory                 */
+#define _PCMCIA0	_PCMCIA (0)	/* PCMCIA 0			   */
+#define _PCMCIA0IO	_PCMCIAIO (0)	/* PCMCIA 0 I/O			   */
+#define _PCMCIA0Attr	_PCMCIAAttr (0)	/* PCMCIA 0 Attribute		   */
+#define _PCMCIA0Mem	_PCMCIAMem (0)	/* PCMCIA 0 Memory		   */
 
-#define _PCMCIA1	_PCMCIA (1)	/* PCMCIA 1                        */
-#define _PCMCIA1IO	_PCMCIAIO (1)	/* PCMCIA 1 I/O                    */
-#define _PCMCIA1Attr	_PCMCIAAttr (1)	/* PCMCIA 1 Attribute              */
-#define _PCMCIA1Mem	_PCMCIAMem (1)	/* PCMCIA 1 Memory                 */
+#define _PCMCIA1	_PCMCIA (1)	/* PCMCIA 1			   */
+#define _PCMCIA1IO	_PCMCIAIO (1)	/* PCMCIA 1 I/O			   */
+#define _PCMCIA1Attr	_PCMCIAAttr (1)	/* PCMCIA 1 Attribute		   */
+#define _PCMCIA1Mem	_PCMCIAMem (1)	/* PCMCIA 1 Memory		   */
 
 #if LANGUAGE == C
 
-typedef Quad    	PCMCIAPrtType [PCMCIAPrtSp/sizeof (Quad)] ;
+typedef Quad		PCMCIAPrtType [PCMCIAPrtSp/sizeof (Quad)] ;
 typedef PCMCIAPrtType	PCMCIAType [PCMCIASp/PCMCIAPrtSp] ;
 
-#define PCMCIA0 	        	/* PCMCIA 0                        */ \
+#define PCMCIA0				/* PCMCIA 0			   */ \
 			(*((PCMCIAType *) io_p2v (_PCMCIA0)))
-#define PCMCIA0IO	        	/* PCMCIA 0 I/O                    */ \
+#define PCMCIA0IO			/* PCMCIA 0 I/O			   */ \
 			(*((PCMCIAPrtType *) io_p2v (_PCMCIA0IO)))
-#define PCMCIA0Attr	        	/* PCMCIA 0 Attribute              */ \
+#define PCMCIA0Attr			/* PCMCIA 0 Attribute		   */ \
 			(*((PCMCIAPrtType *) io_p2v (_PCMCIA0Attr)))
-#define PCMCIA0Mem	        	/* PCMCIA 0 Memory                 */ \
+#define PCMCIA0Mem			/* PCMCIA 0 Memory		   */ \
 			(*((PCMCIAPrtType *) io_p2v (_PCMCIA0Mem)))
 
-#define PCMCIA1 	        	/* PCMCIA 1                        */ \
+#define PCMCIA1				/* PCMCIA 1			   */ \
 			(*((PCMCIAType *) io_p2v (_PCMCIA1)))
-#define PCMCIA1IO	        	/* PCMCIA 1 I/O                    */ \
+#define PCMCIA1IO			/* PCMCIA 1 I/O			   */ \
 			(*((PCMCIAPrtType *) io_p2v (_PCMCIA1IO)))
-#define PCMCIA1Attr	        	/* PCMCIA 1 Attribute              */ \
+#define PCMCIA1Attr			/* PCMCIA 1 Attribute		   */ \
 			(*((PCMCIAPrtType *) io_p2v (_PCMCIA1Attr)))
-#define PCMCIA1Mem	        	/* PCMCIA 1 Memory                 */ \
+#define PCMCIA1Mem			/* PCMCIA 1 Memory		   */ \
 			(*((PCMCIAPrtType *) io_p2v (_PCMCIA1Mem)))
 
 #endif /* LANGUAGE == C */
@@ -181,254 +181,254 @@ typedef PCMCIAPrtType	PCMCIAType [PCMCIASp/PCMCIAPrtSp] ;
  * Universal Serial Bus (USB) Device Controller (UDC) control registers
  *
  * Registers
- *    Ser0UDCCR 	Serial port 0 Universal Serial Bus (USB) Device
- *              	Controller (UDC) Control Register (read/write).
- *    Ser0UDCAR 	Serial port 0 Universal Serial Bus (USB) Device
- *              	Controller (UDC) Address Register (read/write).
+ *    Ser0UDCCR		Serial port 0 Universal Serial Bus (USB) Device
+ *			Controller (UDC) Control Register (read/write).
+ *    Ser0UDCAR		Serial port 0 Universal Serial Bus (USB) Device
+ *			Controller (UDC) Address Register (read/write).
  *    Ser0UDCOMP	Serial port 0 Universal Serial Bus (USB) Device
- *              	Controller (UDC) Output Maximum Packet size register
- *              	(read/write).
+ *			Controller (UDC) Output Maximum Packet size register
+ *			(read/write).
  *    Ser0UDCIMP	Serial port 0 Universal Serial Bus (USB) Device
- *              	Controller (UDC) Input Maximum Packet size register
- *              	(read/write).
+ *			Controller (UDC) Input Maximum Packet size register
+ *			(read/write).
  *    Ser0UDCCS0	Serial port 0 Universal Serial Bus (USB) Device
- *              	Controller (UDC) Control/Status register end-point 0
- *              	(read/write).
+ *			Controller (UDC) Control/Status register end-point 0
+ *			(read/write).
  *    Ser0UDCCS1	Serial port 0 Universal Serial Bus (USB) Device
- *              	Controller (UDC) Control/Status register end-point 1
- *              	(output, read/write).
+ *			Controller (UDC) Control/Status register end-point 1
+ *			(output, read/write).
  *    Ser0UDCCS2	Serial port 0 Universal Serial Bus (USB) Device
- *              	Controller (UDC) Control/Status register end-point 2
- *              	(input, read/write).
- *    Ser0UDCD0 	Serial port 0 Universal Serial Bus (USB) Device
- *              	Controller (UDC) Data register end-point 0
- *              	(read/write).
- *    Ser0UDCWC 	Serial port 0 Universal Serial Bus (USB) Device
- *              	Controller (UDC) Write Count register end-point 0
- *              	(read).
- *    Ser0UDCDR 	Serial port 0 Universal Serial Bus (USB) Device
- *              	Controller (UDC) Data Register (read/write).
- *    Ser0UDCSR 	Serial port 0 Universal Serial Bus (USB) Device
- *              	Controller (UDC) Status Register (read/write).
+ *			Controller (UDC) Control/Status register end-point 2
+ *			(input, read/write).
+ *    Ser0UDCD0		Serial port 0 Universal Serial Bus (USB) Device
+ *			Controller (UDC) Data register end-point 0
+ *			(read/write).
+ *    Ser0UDCWC		Serial port 0 Universal Serial Bus (USB) Device
+ *			Controller (UDC) Write Count register end-point 0
+ *			(read).
+ *    Ser0UDCDR		Serial port 0 Universal Serial Bus (USB) Device
+ *			Controller (UDC) Data Register (read/write).
+ *    Ser0UDCSR		Serial port 0 Universal Serial Bus (USB) Device
+ *			Controller (UDC) Status Register (read/write).
  */
 
 #define _Ser0UDCCR	0x80000000	/* Ser. port 0 UDC Control Reg.    */
 #define _Ser0UDCAR	0x80000004	/* Ser. port 0 UDC Address Reg.    */
 #define _Ser0UDCOMP	0x80000008	/* Ser. port 0 UDC Output Maximum  */
-					/* Packet size reg.                */
+					/* Packet size reg.		   */
 #define _Ser0UDCIMP	0x8000000C	/* Ser. port 0 UDC Input Maximum   */
-					/* Packet size reg.                */
+					/* Packet size reg.		   */
 #define _Ser0UDCCS0	0x80000010	/* Ser. port 0 UDC Control/Status  */
-					/* reg. end-point 0                */
+					/* reg. end-point 0		   */
 #define _Ser0UDCCS1	0x80000014	/* Ser. port 0 UDC Control/Status  */
-					/* reg. end-point 1 (output)       */
+					/* reg. end-point 1 (output)	   */
 #define _Ser0UDCCS2	0x80000018	/* Ser. port 0 UDC Control/Status  */
-					/* reg. end-point 2 (input)        */
-#define _Ser0UDCD0	0x8000001C	/* Ser. port 0 UDC Data reg.       */
-					/* end-point 0                     */
-#define _Ser0UDCWC	0x80000020	/* Ser. port 0 UDC Write Count     */
-					/* reg. end-point 0                */
-#define _Ser0UDCDR	0x80000028	/* Ser. port 0 UDC Data Reg.       */
-#define _Ser0UDCSR	0x80000030	/* Ser. port 0 UDC Status Reg.     */
+					/* reg. end-point 2 (input)	   */
+#define _Ser0UDCD0	0x8000001C	/* Ser. port 0 UDC Data reg.	   */
+					/* end-point 0			   */
+#define _Ser0UDCWC	0x80000020	/* Ser. port 0 UDC Write Count	   */
+					/* reg. end-point 0		   */
+#define _Ser0UDCDR	0x80000028	/* Ser. port 0 UDC Data Reg.	   */
+#define _Ser0UDCSR	0x80000030	/* Ser. port 0 UDC Status Reg.	   */
 
 #if LANGUAGE == C
-#define Ser0UDCCR	        	/* Ser. port 0 UDC Control Reg.    */ \
+#define Ser0UDCCR			/* Ser. port 0 UDC Control Reg.    */ \
 			(*((volatile Word *) io_p2v (_Ser0UDCCR)))
-#define Ser0UDCAR	        	/* Ser. port 0 UDC Address Reg.    */ \
+#define Ser0UDCAR			/* Ser. port 0 UDC Address Reg.    */ \
 			(*((volatile Word *) io_p2v (_Ser0UDCAR)))
-#define Ser0UDCOMP	        	/* Ser. port 0 UDC Output Maximum  */ \
-					/* Packet size reg.                */ \
+#define Ser0UDCOMP			/* Ser. port 0 UDC Output Maximum  */ \
+					/* Packet size reg.		   */ \
 			(*((volatile Word *) io_p2v (_Ser0UDCOMP)))
-#define Ser0UDCIMP	        	/* Ser. port 0 UDC Input Maximum   */ \
-					/* Packet size reg.                */ \
+#define Ser0UDCIMP			/* Ser. port 0 UDC Input Maximum   */ \
+					/* Packet size reg.		   */ \
 			(*((volatile Word *) io_p2v (_Ser0UDCIMP)))
-#define Ser0UDCCS0	        	/* Ser. port 0 UDC Control/Status  */ \
-					/* reg. end-point 0                */ \
+#define Ser0UDCCS0			/* Ser. port 0 UDC Control/Status  */ \
+					/* reg. end-point 0		   */ \
 			(*((volatile Word *) io_p2v (_Ser0UDCCS0)))
-#define Ser0UDCCS1	        	/* Ser. port 0 UDC Control/Status  */ \
-					/* reg. end-point 1 (output)       */ \
+#define Ser0UDCCS1			/* Ser. port 0 UDC Control/Status  */ \
+					/* reg. end-point 1 (output)	   */ \
 			(*((volatile Word *) io_p2v (_Ser0UDCCS1)))
-#define Ser0UDCCS2	        	/* Ser. port 0 UDC Control/Status  */ \
-					/* reg. end-point 2 (input)        */ \
+#define Ser0UDCCS2			/* Ser. port 0 UDC Control/Status  */ \
+					/* reg. end-point 2 (input)	   */ \
 			(*((volatile Word *) io_p2v (_Ser0UDCCS2)))
-#define Ser0UDCD0	        	/* Ser. port 0 UDC Data reg.       */ \
-					/* end-point 0                     */ \
+#define Ser0UDCD0			/* Ser. port 0 UDC Data reg.	   */ \
+					/* end-point 0			   */ \
 			(*((volatile Word *) io_p2v (_Ser0UDCD0)))
-#define Ser0UDCWC	        	/* Ser. port 0 UDC Write Count     */ \
-					/* reg. end-point 0                */ \
+#define Ser0UDCWC			/* Ser. port 0 UDC Write Count	   */ \
+					/* reg. end-point 0		   */ \
 			(*((volatile Word *) io_p2v (_Ser0UDCWC)))
-#define Ser0UDCDR	        	/* Ser. port 0 UDC Data Reg.       */ \
+#define Ser0UDCDR			/* Ser. port 0 UDC Data Reg.	   */ \
 			(*((volatile Word *) io_p2v (_Ser0UDCDR)))
-#define Ser0UDCSR	        	/* Ser. port 0 UDC Status Reg.     */ \
+#define Ser0UDCSR			/* Ser. port 0 UDC Status Reg.	   */ \
 			(*((volatile Word *) io_p2v (_Ser0UDCSR)))
 #endif /* LANGUAGE == C */
 
-#define UDCCR_UDD	0x00000001	/* UDC Disable                     */
-#define UDCCR_UDA	0x00000002	/* UDC Active (read)               */
+#define UDCCR_UDD	0x00000001	/* UDC Disable			   */
+#define UDCCR_UDA	0x00000002	/* UDC Active (read)		   */
 #define UDCCR_RESIM	0x00000004	/* Resume Interrupt Mask, per errata */
-#define UDCCR_EIM	0x00000008	/* End-point 0 Interrupt Mask      */
-					/* (disable)                       */
-#define UDCCR_RIM	0x00000010	/* Receive Interrupt Mask          */
-					/* (disable)                       */
-#define UDCCR_TIM	0x00000020	/* Transmit Interrupt Mask         */
-					/* (disable)                       */
+#define UDCCR_EIM	0x00000008	/* End-point 0 Interrupt Mask	   */
+					/* (disable)			   */
+#define UDCCR_RIM	0x00000010	/* Receive Interrupt Mask	   */
+					/* (disable)			   */
+#define UDCCR_TIM	0x00000020	/* Transmit Interrupt Mask	   */
+					/* (disable)			   */
 #define UDCCR_SRM	0x00000040	/* Suspend/Resume interrupt Mask   */
-					/* (disable)                       */
+					/* (disable)			   */
 #define UDCCR_SUSIM	UDCCR_SRM	/* Per errata, SRM just masks suspend */
 #define UDCCR_REM	0x00000080	/* REset interrupt Mask (disable)  */
 
-#define UDCAR_ADD	Fld (7, 0)	/* function ADDress                */
+#define UDCAR_ADD	Fld (7, 0)	/* function ADDress		   */
 
 #define UDCOMP_OUTMAXP	Fld (8, 0)	/* OUTput MAXimum Packet size - 1  */
-					/* [byte]                          */
-#define UDCOMP_OutMaxPkt(Size)  	/* Output Maximum Packet size      */ \
-					/* [1..256 byte]                   */ \
+					/* [byte]			   */
+#define UDCOMP_OutMaxPkt(Size)		/* Output Maximum Packet size	   */ \
+					/* [1..256 byte]		   */ \
 			(((Size) - 1) << FShft (UDCOMP_OUTMAXP))
 
 #define UDCIMP_INMAXP	Fld (8, 0)	/* INput MAXimum Packet size - 1   */
-					/* [byte]                          */
-#define UDCIMP_InMaxPkt(Size)   	/* Input Maximum Packet size       */ \
-					/* [1..256 byte]                   */ \
+					/* [byte]			   */
+#define UDCIMP_InMaxPkt(Size)		/* Input Maximum Packet size	   */ \
+					/* [1..256 byte]		   */ \
 			(((Size) - 1) << FShft (UDCIMP_INMAXP))
 
-#define UDCCS0_OPR	0x00000001	/* Output Packet Ready (read)      */
-#define UDCCS0_IPR	0x00000002	/* Input Packet Ready              */
-#define UDCCS0_SST	0x00000004	/* Sent STall                      */
-#define UDCCS0_FST	0x00000008	/* Force STall                     */
-#define UDCCS0_DE	0x00000010	/* Data End                        */
-#define UDCCS0_SE	0x00000020	/* Setup End (read)                */
+#define UDCCS0_OPR	0x00000001	/* Output Packet Ready (read)	   */
+#define UDCCS0_IPR	0x00000002	/* Input Packet Ready		   */
+#define UDCCS0_SST	0x00000004	/* Sent STall			   */
+#define UDCCS0_FST	0x00000008	/* Force STall			   */
+#define UDCCS0_DE	0x00000010	/* Data End			   */
+#define UDCCS0_SE	0x00000020	/* Setup End (read)		   */
 #define UDCCS0_SO	0x00000040	/* Serviced Output packet ready    */
-					/* (write)                         */
-#define UDCCS0_SSE	0x00000080	/* Serviced Setup End (write)      */
+					/* (write)			   */
+#define UDCCS0_SSE	0x00000080	/* Serviced Setup End (write)	   */
 
 #define UDCCS1_RFS	0x00000001	/* Receive FIFO 12-bytes or more   */
-					/* Service request (read)          */
-#define UDCCS1_RPC	0x00000002	/* Receive Packet Complete         */
-#define UDCCS1_RPE	0x00000004	/* Receive Packet Error (read)     */
-#define UDCCS1_SST	0x00000008	/* Sent STall                      */
-#define UDCCS1_FST	0x00000010	/* Force STall                     */
+					/* Service request (read)	   */
+#define UDCCS1_RPC	0x00000002	/* Receive Packet Complete	   */
+#define UDCCS1_RPE	0x00000004	/* Receive Packet Error (read)	   */
+#define UDCCS1_SST	0x00000008	/* Sent STall			   */
+#define UDCCS1_FST	0x00000010	/* Force STall			   */
 #define UDCCS1_RNE	0x00000020	/* Receive FIFO Not Empty (read)   */
 
 #define UDCCS2_TFS	0x00000001	/* Transmit FIFO 8-bytes or less   */
-					/* Service request (read)          */
-#define UDCCS2_TPC	0x00000002	/* Transmit Packet Complete        */
+					/* Service request (read)	   */
+#define UDCCS2_TPC	0x00000002	/* Transmit Packet Complete	   */
 #define UDCCS2_TPE	0x00000004	/* Transmit Packet Error (read)    */
-#define UDCCS2_TUR	0x00000008	/* Transmit FIFO Under-Run         */
-#define UDCCS2_SST	0x00000010	/* Sent STall                      */
-#define UDCCS2_FST	0x00000020	/* Force STall                     */
+#define UDCCS2_TUR	0x00000008	/* Transmit FIFO Under-Run	   */
+#define UDCCS2_SST	0x00000010	/* Sent STall			   */
+#define UDCCS2_FST	0x00000020	/* Force STall			   */
 
-#define UDCD0_DATA	Fld (8, 0)	/* receive/transmit DATA FIFOs     */
+#define UDCD0_DATA	Fld (8, 0)	/* receive/transmit DATA FIFOs	   */
 
-#define UDCWC_WC	Fld (4, 0)	/* Write Count                     */
+#define UDCWC_WC	Fld (4, 0)	/* Write Count			   */
 
-#define UDCDR_DATA	Fld (8, 0)	/* receive/transmit DATA FIFOs     */
+#define UDCDR_DATA	Fld (8, 0)	/* receive/transmit DATA FIFOs	   */
 
 #define UDCSR_EIR	0x00000001	/* End-point 0 Interrupt Request   */
-#define UDCSR_RIR	0x00000002	/* Receive Interrupt Request       */
-#define UDCSR_TIR	0x00000004	/* Transmit Interrupt Request      */
-#define UDCSR_SUSIR	0x00000008	/* SUSpend Interrupt Request       */
-#define UDCSR_RESIR	0x00000010	/* RESume Interrupt Request        */
-#define UDCSR_RSTIR	0x00000020	/* ReSeT Interrupt Request         */
+#define UDCSR_RIR	0x00000002	/* Receive Interrupt Request	   */
+#define UDCSR_TIR	0x00000004	/* Transmit Interrupt Request	   */
+#define UDCSR_SUSIR	0x00000008	/* SUSpend Interrupt Request	   */
+#define UDCSR_RESIR	0x00000010	/* RESume Interrupt Request	   */
+#define UDCSR_RSTIR	0x00000020	/* ReSeT Interrupt Request	   */
 
 
 /*
  * Universal Asynchronous Receiver/Transmitter (UART) control registers
  *
  * Registers
- *    Ser1UTCR0 	Serial port 1 Universal Asynchronous
- *              	Receiver/Transmitter (UART) Control Register 0
- *              	(read/write).
- *    Ser1UTCR1 	Serial port 1 Universal Asynchronous
- *              	Receiver/Transmitter (UART) Control Register 1
- *              	(read/write).
- *    Ser1UTCR2 	Serial port 1 Universal Asynchronous
- *              	Receiver/Transmitter (UART) Control Register 2
- *              	(read/write).
- *    Ser1UTCR3 	Serial port 1 Universal Asynchronous
- *              	Receiver/Transmitter (UART) Control Register 3
- *              	(read/write).
- *    Ser1UTDR  	Serial port 1 Universal Asynchronous
- *              	Receiver/Transmitter (UART) Data Register
- *              	(read/write).
- *    Ser1UTSR0 	Serial port 1 Universal Asynchronous
- *              	Receiver/Transmitter (UART) Status Register 0
- *              	(read/write).
- *    Ser1UTSR1 	Serial port 1 Universal Asynchronous
- *              	Receiver/Transmitter (UART) Status Register 1 (read).
+ *    Ser1UTCR0		Serial port 1 Universal Asynchronous
+ *			Receiver/Transmitter (UART) Control Register 0
+ *			(read/write).
+ *    Ser1UTCR1		Serial port 1 Universal Asynchronous
+ *			Receiver/Transmitter (UART) Control Register 1
+ *			(read/write).
+ *    Ser1UTCR2		Serial port 1 Universal Asynchronous
+ *			Receiver/Transmitter (UART) Control Register 2
+ *			(read/write).
+ *    Ser1UTCR3		Serial port 1 Universal Asynchronous
+ *			Receiver/Transmitter (UART) Control Register 3
+ *			(read/write).
+ *    Ser1UTDR		Serial port 1 Universal Asynchronous
+ *			Receiver/Transmitter (UART) Data Register
+ *			(read/write).
+ *    Ser1UTSR0		Serial port 1 Universal Asynchronous
+ *			Receiver/Transmitter (UART) Status Register 0
+ *			(read/write).
+ *    Ser1UTSR1		Serial port 1 Universal Asynchronous
+ *			Receiver/Transmitter (UART) Status Register 1 (read).
  *
- *    Ser2UTCR0 	Serial port 2 Universal Asynchronous
- *              	Receiver/Transmitter (UART) Control Register 0
- *              	(read/write).
- *    Ser2UTCR1 	Serial port 2 Universal Asynchronous
- *              	Receiver/Transmitter (UART) Control Register 1
- *              	(read/write).
- *    Ser2UTCR2 	Serial port 2 Universal Asynchronous
- *              	Receiver/Transmitter (UART) Control Register 2
- *              	(read/write).
- *    Ser2UTCR3 	Serial port 2 Universal Asynchronous
- *              	Receiver/Transmitter (UART) Control Register 3
- *              	(read/write).
- *    Ser2UTCR4 	Serial port 2 Universal Asynchronous
- *              	Receiver/Transmitter (UART) Control Register 4
- *              	(read/write).
- *    Ser2UTDR  	Serial port 2 Universal Asynchronous
- *              	Receiver/Transmitter (UART) Data Register
- *              	(read/write).
- *    Ser2UTSR0 	Serial port 2 Universal Asynchronous
- *              	Receiver/Transmitter (UART) Status Register 0
- *              	(read/write).
- *    Ser2UTSR1 	Serial port 2 Universal Asynchronous
- *              	Receiver/Transmitter (UART) Status Register 1 (read).
+ *    Ser2UTCR0		Serial port 2 Universal Asynchronous
+ *			Receiver/Transmitter (UART) Control Register 0
+ *			(read/write).
+ *    Ser2UTCR1		Serial port 2 Universal Asynchronous
+ *			Receiver/Transmitter (UART) Control Register 1
+ *			(read/write).
+ *    Ser2UTCR2		Serial port 2 Universal Asynchronous
+ *			Receiver/Transmitter (UART) Control Register 2
+ *			(read/write).
+ *    Ser2UTCR3		Serial port 2 Universal Asynchronous
+ *			Receiver/Transmitter (UART) Control Register 3
+ *			(read/write).
+ *    Ser2UTCR4		Serial port 2 Universal Asynchronous
+ *			Receiver/Transmitter (UART) Control Register 4
+ *			(read/write).
+ *    Ser2UTDR		Serial port 2 Universal Asynchronous
+ *			Receiver/Transmitter (UART) Data Register
+ *			(read/write).
+ *    Ser2UTSR0		Serial port 2 Universal Asynchronous
+ *			Receiver/Transmitter (UART) Status Register 0
+ *			(read/write).
+ *    Ser2UTSR1		Serial port 2 Universal Asynchronous
+ *			Receiver/Transmitter (UART) Status Register 1 (read).
  *
- *    Ser3UTCR0 	Serial port 3 Universal Asynchronous
- *              	Receiver/Transmitter (UART) Control Register 0
- *              	(read/write).
- *    Ser3UTCR1 	Serial port 3 Universal Asynchronous
- *              	Receiver/Transmitter (UART) Control Register 1
- *              	(read/write).
- *    Ser3UTCR2 	Serial port 3 Universal Asynchronous
- *              	Receiver/Transmitter (UART) Control Register 2
- *              	(read/write).
- *    Ser3UTCR3 	Serial port 3 Universal Asynchronous
- *              	Receiver/Transmitter (UART) Control Register 3
- *              	(read/write).
- *    Ser3UTDR  	Serial port 3 Universal Asynchronous
- *              	Receiver/Transmitter (UART) Data Register
- *              	(read/write).
- *    Ser3UTSR0 	Serial port 3 Universal Asynchronous
- *              	Receiver/Transmitter (UART) Status Register 0
- *              	(read/write).
- *    Ser3UTSR1 	Serial port 3 Universal Asynchronous
- *              	Receiver/Transmitter (UART) Status Register 1 (read).
+ *    Ser3UTCR0		Serial port 3 Universal Asynchronous
+ *			Receiver/Transmitter (UART) Control Register 0
+ *			(read/write).
+ *    Ser3UTCR1		Serial port 3 Universal Asynchronous
+ *			Receiver/Transmitter (UART) Control Register 1
+ *			(read/write).
+ *    Ser3UTCR2		Serial port 3 Universal Asynchronous
+ *			Receiver/Transmitter (UART) Control Register 2
+ *			(read/write).
+ *    Ser3UTCR3		Serial port 3 Universal Asynchronous
+ *			Receiver/Transmitter (UART) Control Register 3
+ *			(read/write).
+ *    Ser3UTDR		Serial port 3 Universal Asynchronous
+ *			Receiver/Transmitter (UART) Data Register
+ *			(read/write).
+ *    Ser3UTSR0		Serial port 3 Universal Asynchronous
+ *			Receiver/Transmitter (UART) Status Register 0
+ *			(read/write).
+ *    Ser3UTSR1		Serial port 3 Universal Asynchronous
+ *			Receiver/Transmitter (UART) Status Register 1 (read).
  *
  * Clocks
  *    fxtl, Txtl	Frequency, period of the system crystal (3.6864 MHz
- *              	or 3.5795 MHz).
- *    fua, Tua  	Frequency, period of the UART communication.
+ *			or 3.5795 MHz).
+ *    fua, Tua		Frequency, period of the UART communication.
  */
 
-#define _UTCR0(Nb)	        	/* UART Control Reg. 0 [1..3]      */ \
+#define _UTCR0(Nb)			/* UART Control Reg. 0 [1..3]	   */ \
 			(0x80010000 + ((Nb) - 1)*0x00020000)
-#define _UTCR1(Nb)	        	/* UART Control Reg. 1 [1..3]      */ \
+#define _UTCR1(Nb)			/* UART Control Reg. 1 [1..3]	   */ \
 			(0x80010004 + ((Nb) - 1)*0x00020000)
-#define _UTCR2(Nb)	        	/* UART Control Reg. 2 [1..3]      */ \
+#define _UTCR2(Nb)			/* UART Control Reg. 2 [1..3]	   */ \
 			(0x80010008 + ((Nb) - 1)*0x00020000)
-#define _UTCR3(Nb)	        	/* UART Control Reg. 3 [1..3]      */ \
+#define _UTCR3(Nb)			/* UART Control Reg. 3 [1..3]	   */ \
 			(0x8001000C + ((Nb) - 1)*0x00020000)
-#define _UTCR4(Nb)	        	/* UART Control Reg. 4 [2]         */ \
+#define _UTCR4(Nb)			/* UART Control Reg. 4 [2]	   */ \
 			(0x80010010 + ((Nb) - 1)*0x00020000)
-#define _UTDR(Nb)	        	/* UART Data Reg. [1..3]           */ \
+#define _UTDR(Nb)			/* UART Data Reg. [1..3]	   */ \
 			(0x80010014 + ((Nb) - 1)*0x00020000)
-#define _UTSR0(Nb)	        	/* UART Status Reg. 0 [1..3]       */ \
+#define _UTSR0(Nb)			/* UART Status Reg. 0 [1..3]	   */ \
 			(0x8001001C + ((Nb) - 1)*0x00020000)
-#define _UTSR1(Nb)	        	/* UART Status Reg. 1 [1..3]       */ \
+#define _UTSR1(Nb)			/* UART Status Reg. 1 [1..3]	   */ \
 			(0x80010020 + ((Nb) - 1)*0x00020000)
 
 #define _Ser1UTCR0	_UTCR0 (1)	/* Ser. port 1 UART Control Reg. 0 */
 #define _Ser1UTCR1	_UTCR1 (1)	/* Ser. port 1 UART Control Reg. 1 */
 #define _Ser1UTCR2	_UTCR2 (1)	/* Ser. port 1 UART Control Reg. 2 */
 #define _Ser1UTCR3	_UTCR3 (1)	/* Ser. port 1 UART Control Reg. 3 */
-#define _Ser1UTDR	_UTDR (1)	/* Ser. port 1 UART Data Reg.      */
+#define _Ser1UTDR	_UTDR (1)	/* Ser. port 1 UART Data Reg.	   */
 #define _Ser1UTSR0	_UTSR0 (1)	/* Ser. port 1 UART Status Reg. 0  */
 #define _Ser1UTSR1	_UTSR1 (1)	/* Ser. port 1 UART Status Reg. 1  */
 
@@ -437,7 +437,7 @@ typedef PCMCIAPrtType	PCMCIAType [PCMCIASp/PCMCIAPrtSp] ;
 #define _Ser2UTCR2	_UTCR2 (2)	/* Ser. port 2 UART Control Reg. 2 */
 #define _Ser2UTCR3	_UTCR3 (2)	/* Ser. port 2 UART Control Reg. 3 */
 #define _Ser2UTCR4	_UTCR4 (2)	/* Ser. port 2 UART Control Reg. 4 */
-#define _Ser2UTDR	_UTDR (2)	/* Ser. port 2 UART Data Reg.      */
+#define _Ser2UTDR	_UTDR (2)	/* Ser. port 2 UART Data Reg.	   */
 #define _Ser2UTSR0	_UTSR0 (2)	/* Ser. port 2 UART Status Reg. 0  */
 #define _Ser2UTSR1	_UTSR1 (2)	/* Ser. port 2 UART Status Reg. 1  */
 
@@ -445,57 +445,57 @@ typedef PCMCIAPrtType	PCMCIAType [PCMCIASp/PCMCIAPrtSp] ;
 #define _Ser3UTCR1	_UTCR1 (3)	/* Ser. port 3 UART Control Reg. 1 */
 #define _Ser3UTCR2	_UTCR2 (3)	/* Ser. port 3 UART Control Reg. 2 */
 #define _Ser3UTCR3	_UTCR3 (3)	/* Ser. port 3 UART Control Reg. 3 */
-#define _Ser3UTDR	_UTDR (3)	/* Ser. port 3 UART Data Reg.      */
+#define _Ser3UTDR	_UTDR (3)	/* Ser. port 3 UART Data Reg.	   */
 #define _Ser3UTSR0	_UTSR0 (3)	/* Ser. port 3 UART Status Reg. 0  */
 #define _Ser3UTSR1	_UTSR1 (3)	/* Ser. port 3 UART Status Reg. 1  */
 
 #if LANGUAGE == C
 
-#define Ser1UTCR0	        	/* Ser. port 1 UART Control Reg. 0 */ \
+#define Ser1UTCR0			/* Ser. port 1 UART Control Reg. 0 */ \
 			(*((volatile Word *) io_p2v (_Ser1UTCR0)))
-#define Ser1UTCR1	        	/* Ser. port 1 UART Control Reg. 1 */ \
+#define Ser1UTCR1			/* Ser. port 1 UART Control Reg. 1 */ \
 			(*((volatile Word *) io_p2v (_Ser1UTCR1)))
-#define Ser1UTCR2	        	/* Ser. port 1 UART Control Reg. 2 */ \
+#define Ser1UTCR2			/* Ser. port 1 UART Control Reg. 2 */ \
 			(*((volatile Word *) io_p2v (_Ser1UTCR2)))
-#define Ser1UTCR3	        	/* Ser. port 1 UART Control Reg. 3 */ \
+#define Ser1UTCR3			/* Ser. port 1 UART Control Reg. 3 */ \
 			(*((volatile Word *) io_p2v (_Ser1UTCR3)))
-#define Ser1UTDR	        	/* Ser. port 1 UART Data Reg.      */ \
+#define Ser1UTDR			/* Ser. port 1 UART Data Reg.	   */ \
 			(*((volatile Word *) io_p2v (_Ser1UTDR)))
-#define Ser1UTSR0	        	/* Ser. port 1 UART Status Reg. 0  */ \
+#define Ser1UTSR0			/* Ser. port 1 UART Status Reg. 0  */ \
 			(*((volatile Word *) io_p2v (_Ser1UTSR0)))
-#define Ser1UTSR1	        	/* Ser. port 1 UART Status Reg. 1  */ \
+#define Ser1UTSR1			/* Ser. port 1 UART Status Reg. 1  */ \
 			(*((volatile Word *) io_p2v (_Ser1UTSR1)))
 
-#define Ser2UTCR0	        	/* Ser. port 2 UART Control Reg. 0 */ \
+#define Ser2UTCR0			/* Ser. port 2 UART Control Reg. 0 */ \
 			(*((volatile Word *) io_p2v (_Ser2UTCR0)))
-#define Ser2UTCR1	        	/* Ser. port 2 UART Control Reg. 1 */ \
+#define Ser2UTCR1			/* Ser. port 2 UART Control Reg. 1 */ \
 			(*((volatile Word *) io_p2v (_Ser2UTCR1)))
-#define Ser2UTCR2	        	/* Ser. port 2 UART Control Reg. 2 */ \
+#define Ser2UTCR2			/* Ser. port 2 UART Control Reg. 2 */ \
 			(*((volatile Word *) io_p2v (_Ser2UTCR2)))
-#define Ser2UTCR3	        	/* Ser. port 2 UART Control Reg. 3 */ \
+#define Ser2UTCR3			/* Ser. port 2 UART Control Reg. 3 */ \
 			(*((volatile Word *) io_p2v (_Ser2UTCR3)))
-#define Ser2UTCR4	        	/* Ser. port 2 UART Control Reg. 4 */ \
+#define Ser2UTCR4			/* Ser. port 2 UART Control Reg. 4 */ \
 			(*((volatile Word *) io_p2v (_Ser2UTCR4)))
-#define Ser2UTDR	        	/* Ser. port 2 UART Data Reg.      */ \
+#define Ser2UTDR			/* Ser. port 2 UART Data Reg.	   */ \
 			(*((volatile Word *) io_p2v (_Ser2UTDR)))
-#define Ser2UTSR0	        	/* Ser. port 2 UART Status Reg. 0  */ \
+#define Ser2UTSR0			/* Ser. port 2 UART Status Reg. 0  */ \
 			(*((volatile Word *) io_p2v (_Ser2UTSR0)))
-#define Ser2UTSR1	        	/* Ser. port 2 UART Status Reg. 1  */ \
+#define Ser2UTSR1			/* Ser. port 2 UART Status Reg. 1  */ \
 			(*((volatile Word *) io_p2v (_Ser2UTSR1)))
 
-#define Ser3UTCR0	        	/* Ser. port 3 UART Control Reg. 0 */ \
+#define Ser3UTCR0			/* Ser. port 3 UART Control Reg. 0 */ \
 			(*((volatile Word *) io_p2v (_Ser3UTCR0)))
-#define Ser3UTCR1	        	/* Ser. port 3 UART Control Reg. 1 */ \
+#define Ser3UTCR1			/* Ser. port 3 UART Control Reg. 1 */ \
 			(*((volatile Word *) io_p2v (_Ser3UTCR1)))
-#define Ser3UTCR2	        	/* Ser. port 3 UART Control Reg. 2 */ \
+#define Ser3UTCR2			/* Ser. port 3 UART Control Reg. 2 */ \
 			(*((volatile Word *) io_p2v (_Ser3UTCR2)))
-#define Ser3UTCR3	        	/* Ser. port 3 UART Control Reg. 3 */ \
+#define Ser3UTCR3			/* Ser. port 3 UART Control Reg. 3 */ \
 			(*((volatile Word *) io_p2v (_Ser3UTCR3)))
-#define Ser3UTDR	        	/* Ser. port 3 UART Data Reg.      */ \
+#define Ser3UTDR			/* Ser. port 3 UART Data Reg.	   */ \
 			(*((volatile Word *) io_p2v (_Ser3UTDR)))
-#define Ser3UTSR0	        	/* Ser. port 3 UART Status Reg. 0  */ \
+#define Ser3UTSR0			/* Ser. port 3 UART Status Reg. 0  */ \
 			(*((volatile Word *) io_p2v (_Ser3UTSR0)))
-#define Ser3UTSR1	        	/* Ser. port 3 UART Status Reg. 1  */ \
+#define Ser3UTSR1			/* Ser. port 3 UART Status Reg. 1  */ \
 			(*((volatile Word *) io_p2v (_Ser3UTSR1)))
 
 #elif LANGUAGE == Assembly
@@ -526,89 +526,89 @@ typedef PCMCIAPrtType	PCMCIAType [PCMCIASp/PCMCIAPrtSp] ;
 
 #endif /* LANGUAGE == C */
 
-#define UTCR0_PE	0x00000001	/* Parity Enable                   */
-#define UTCR0_OES	0x00000002	/* Odd/Even parity Select          */
-#define UTCR0_OddPar	(UTCR0_OES*0)	/*  Odd Parity                     */
-#define UTCR0_EvenPar	(UTCR0_OES*1)	/*  Even Parity                    */
-#define UTCR0_SBS	0x00000004	/* Stop Bit Select                 */
-#define UTCR0_1StpBit	(UTCR0_SBS*0)	/*  1 Stop Bit per frame           */
-#define UTCR0_2StpBit	(UTCR0_SBS*1)	/*  2 Stop Bits per frame          */
-#define UTCR0_DSS	0x00000008	/* Data Size Select                */
-#define UTCR0_7BitData	(UTCR0_DSS*0)	/*  7-Bit Data                     */
-#define UTCR0_8BitData	(UTCR0_DSS*1)	/*  8-Bit Data                     */
-#define UTCR0_SCE	0x00000010	/* Sample Clock Enable             */
-					/* (ser. port 1: GPIO [18],        */
-					/* ser. port 3: GPIO [20])         */
-#define UTCR0_RCE	0x00000020	/* Receive Clock Edge select       */
-#define UTCR0_RcRsEdg	(UTCR0_RCE*0)	/*  Receive clock Rising-Edge      */
-#define UTCR0_RcFlEdg	(UTCR0_RCE*1)	/*  Receive clock Falling-Edge     */
-#define UTCR0_TCE	0x00000040	/* Transmit Clock Edge select      */
-#define UTCR0_TrRsEdg	(UTCR0_TCE*0)	/*  Transmit clock Rising-Edge     */
+#define UTCR0_PE	0x00000001	/* Parity Enable		   */
+#define UTCR0_OES	0x00000002	/* Odd/Even parity Select	   */
+#define UTCR0_OddPar	(UTCR0_OES*0)	/*  Odd Parity			   */
+#define UTCR0_EvenPar	(UTCR0_OES*1)	/*  Even Parity			   */
+#define UTCR0_SBS	0x00000004	/* Stop Bit Select		   */
+#define UTCR0_1StpBit	(UTCR0_SBS*0)	/*  1 Stop Bit per frame	   */
+#define UTCR0_2StpBit	(UTCR0_SBS*1)	/*  2 Stop Bits per frame	   */
+#define UTCR0_DSS	0x00000008	/* Data Size Select		   */
+#define UTCR0_7BitData	(UTCR0_DSS*0)	/*  7-Bit Data			   */
+#define UTCR0_8BitData	(UTCR0_DSS*1)	/*  8-Bit Data			   */
+#define UTCR0_SCE	0x00000010	/* Sample Clock Enable		   */
+					/* (ser. port 1: GPIO [18],	   */
+					/* ser. port 3: GPIO [20])	   */
+#define UTCR0_RCE	0x00000020	/* Receive Clock Edge select	   */
+#define UTCR0_RcRsEdg	(UTCR0_RCE*0)	/*  Receive clock Rising-Edge	   */
+#define UTCR0_RcFlEdg	(UTCR0_RCE*1)	/*  Receive clock Falling-Edge	   */
+#define UTCR0_TCE	0x00000040	/* Transmit Clock Edge select	   */
+#define UTCR0_TrRsEdg	(UTCR0_TCE*0)	/*  Transmit clock Rising-Edge	   */
 #define UTCR0_TrFlEdg	(UTCR0_TCE*1)	/*  Transmit clock Falling-Edge    */
-#define UTCR0_Ser2IrDA	        	/* Ser. port 2 IrDA settings       */ \
+#define UTCR0_Ser2IrDA			/* Ser. port 2 IrDA settings	   */ \
 			(UTCR0_1StpBit + UTCR0_8BitData)
 
 #define UTCR1_BRD	Fld (4, 0)	/* Baud Rate Divisor/16 - 1 [11:8] */
 #define UTCR2_BRD	Fld (8, 0)	/* Baud Rate Divisor/16 - 1  [7:0] */
 					/* fua = fxtl/(16*(BRD[11:0] + 1)) */
 					/* Tua = 16*(BRD [11:0] + 1)*Txtl  */
-#define UTCR1_BdRtDiv(Div)      	/*  Baud Rate Divisor [16..65536]  */ \
+#define UTCR1_BdRtDiv(Div)		/*  Baud Rate Divisor [16..65536]  */ \
 			(((Div) - 16)/16 >> FSize (UTCR2_BRD) << \
 			 FShft (UTCR1_BRD))
-#define UTCR2_BdRtDiv(Div)      	/*  Baud Rate Divisor [16..65536]  */ \
+#define UTCR2_BdRtDiv(Div)		/*  Baud Rate Divisor [16..65536]  */ \
 			(((Div) - 16)/16 & FAlnMsk (UTCR2_BRD) << \
 			 FShft (UTCR2_BRD))
 					/*  fua = fxtl/(16*Floor (Div/16)) */
 					/*  Tua = 16*Floor (Div/16)*Txtl   */
-#define UTCR1_CeilBdRtDiv(Div)  	/*  Ceil. of BdRtDiv [16..65536]   */ \
+#define UTCR1_CeilBdRtDiv(Div)		/*  Ceil. of BdRtDiv [16..65536]   */ \
 			(((Div) - 1)/16 >> FSize (UTCR2_BRD) << \
 			 FShft (UTCR1_BRD))
-#define UTCR2_CeilBdRtDiv(Div)  	/*  Ceil. of BdRtDiv [16..65536]   */ \
+#define UTCR2_CeilBdRtDiv(Div)		/*  Ceil. of BdRtDiv [16..65536]   */ \
 			(((Div) - 1)/16 & FAlnMsk (UTCR2_BRD) << \
 			 FShft (UTCR2_BRD))
 					/*  fua = fxtl/(16*Ceil (Div/16))  */
 					/*  Tua = 16*Ceil (Div/16)*Txtl    */
 
-#define UTCR3_RXE	0x00000001	/* Receive Enable                  */
-#define UTCR3_TXE	0x00000002	/* Transmit Enable                 */
-#define UTCR3_BRK	0x00000004	/* BReaK mode                      */
+#define UTCR3_RXE	0x00000001	/* Receive Enable		   */
+#define UTCR3_TXE	0x00000002	/* Transmit Enable		   */
+#define UTCR3_BRK	0x00000004	/* BReaK mode			   */
 #define UTCR3_RIE	0x00000008	/* Receive FIFO 1/3-to-2/3-full or */
-					/* more Interrupt Enable           */
+					/* more Interrupt Enable	   */
 #define UTCR3_TIE	0x00000010	/* Transmit FIFO 1/2-full or less  */
-					/* Interrupt Enable                */
-#define UTCR3_LBM	0x00000020	/* Look-Back Mode                  */
-#define UTCR3_Ser2IrDA	        	/* Ser. port 2 IrDA settings (RIE, */ \
+					/* Interrupt Enable		   */
+#define UTCR3_LBM	0x00000020	/* Look-Back Mode		   */
+#define UTCR3_Ser2IrDA			/* Ser. port 2 IrDA settings (RIE, */ \
 					/* TIE, LBM can be set or cleared) */ \
 			(UTCR3_RXE + UTCR3_TXE)
 
 #define UTCR4_HSE	0x00000001	/* Hewlett-Packard Serial InfraRed */
-					/* (HP-SIR) modulation Enable      */
+					/* (HP-SIR) modulation Enable	   */
 #define UTCR4_NRZ	(UTCR4_HSE*0)	/*  Non-Return to Zero modulation  */
-#define UTCR4_HPSIR	(UTCR4_HSE*1)	/*  HP-SIR modulation              */
-#define UTCR4_LPM	0x00000002	/* Low-Power Mode                  */
-#define UTCR4_Z3_16Bit	(UTCR4_LPM*0)	/*  Zero pulse = 3/16 Bit time     */
-#define UTCR4_Z1_6us	(UTCR4_LPM*1)	/*  Zero pulse = 1.6 us            */
+#define UTCR4_HPSIR	(UTCR4_HSE*1)	/*  HP-SIR modulation		   */
+#define UTCR4_LPM	0x00000002	/* Low-Power Mode		   */
+#define UTCR4_Z3_16Bit	(UTCR4_LPM*0)	/*  Zero pulse = 3/16 Bit time	   */
+#define UTCR4_Z1_6us	(UTCR4_LPM*1)	/*  Zero pulse = 1.6 us		   */
 
-#define UTDR_DATA	Fld (8, 0)	/* receive/transmit DATA FIFOs     */
-#if 0           	        	/* Hidden receive FIFO bits        */
+#define UTDR_DATA	Fld (8, 0)	/* receive/transmit DATA FIFOs	   */
+#if 0					/* Hidden receive FIFO bits	   */
 #define UTDR_PRE	0x00000100	/*  receive PaRity Error (read)    */
 #define UTDR_FRE	0x00000200	/*  receive FRaming Error (read)   */
 #define UTDR_ROR	0x00000400	/*  Receive FIFO Over-Run (read)   */
 #endif /* 0 */
 
 #define UTSR0_TFS	0x00000001	/* Transmit FIFO 1/2-full or less  */
-					/* Service request (read)          */
+					/* Service request (read)	   */
 #define UTSR0_RFS	0x00000002	/* Receive FIFO 1/3-to-2/3-full or */
-					/* more Service request (read)     */
-#define UTSR0_RID	0x00000004	/* Receiver IDle                   */
-#define UTSR0_RBB	0x00000008	/* Receive Beginning of Break      */
-#define UTSR0_REB	0x00000010	/* Receive End of Break            */
-#define UTSR0_EIF	0x00000020	/* Error In FIFO (read)            */
+					/* more Service request (read)	   */
+#define UTSR0_RID	0x00000004	/* Receiver IDle		   */
+#define UTSR0_RBB	0x00000008	/* Receive Beginning of Break	   */
+#define UTSR0_REB	0x00000010	/* Receive End of Break		   */
+#define UTSR0_EIF	0x00000020	/* Error In FIFO (read)		   */
 
-#define UTSR1_TBY	0x00000001	/* Transmitter BusY (read)         */
+#define UTSR1_TBY	0x00000001	/* Transmitter BusY (read)	   */
 #define UTSR1_RNE	0x00000002	/* Receive FIFO Not Empty (read)   */
 #define UTSR1_TNF	0x00000004	/* Transmit FIFO Not Full (read)   */
-#define UTSR1_PRE	0x00000008	/* receive PaRity Error (read)     */
+#define UTSR1_PRE	0x00000008	/* receive PaRity Error (read)	   */
 #define UTSR1_FRE	0x00000010	/* receive FRaming Error (read)    */
 #define UTSR1_ROR	0x00000020	/* Receive FIFO Over-Run (read)    */
 
@@ -617,27 +617,27 @@ typedef PCMCIAPrtType	PCMCIAType [PCMCIASp/PCMCIAPrtSp] ;
  * Synchronous Data Link Controller (SDLC) control registers
  *
  * Registers
- *    Ser1SDCR0 	Serial port 1 Synchronous Data Link Controller (SDLC)
- *              	Control Register 0 (read/write).
- *    Ser1SDCR1 	Serial port 1 Synchronous Data Link Controller (SDLC)
- *              	Control Register 1 (read/write).
- *    Ser1SDCR2 	Serial port 1 Synchronous Data Link Controller (SDLC)
- *              	Control Register 2 (read/write).
- *    Ser1SDCR3 	Serial port 1 Synchronous Data Link Controller (SDLC)
- *              	Control Register 3 (read/write).
- *    Ser1SDCR4 	Serial port 1 Synchronous Data Link Controller (SDLC)
- *              	Control Register 4 (read/write).
- *    Ser1SDDR  	Serial port 1 Synchronous Data Link Controller (SDLC)
- *              	Data Register (read/write).
- *    Ser1SDSR0 	Serial port 1 Synchronous Data Link Controller (SDLC)
- *              	Status Register 0 (read/write).
- *    Ser1SDSR1 	Serial port 1 Synchronous Data Link Controller (SDLC)
- *              	Status Register 1 (read/write).
+ *    Ser1SDCR0		Serial port 1 Synchronous Data Link Controller (SDLC)
+ *			Control Register 0 (read/write).
+ *    Ser1SDCR1		Serial port 1 Synchronous Data Link Controller (SDLC)
+ *			Control Register 1 (read/write).
+ *    Ser1SDCR2		Serial port 1 Synchronous Data Link Controller (SDLC)
+ *			Control Register 2 (read/write).
+ *    Ser1SDCR3		Serial port 1 Synchronous Data Link Controller (SDLC)
+ *			Control Register 3 (read/write).
+ *    Ser1SDCR4		Serial port 1 Synchronous Data Link Controller (SDLC)
+ *			Control Register 4 (read/write).
+ *    Ser1SDDR		Serial port 1 Synchronous Data Link Controller (SDLC)
+ *			Data Register (read/write).
+ *    Ser1SDSR0		Serial port 1 Synchronous Data Link Controller (SDLC)
+ *			Status Register 0 (read/write).
+ *    Ser1SDSR1		Serial port 1 Synchronous Data Link Controller (SDLC)
+ *			Status Register 1 (read/write).
  *
  * Clocks
  *    fxtl, Txtl	Frequency, period of the system crystal (3.6864 MHz
- *              	or 3.5795 MHz).
- *    fsd, Tsd  	Frequency, period of the SDLC communication.
+ *			or 3.5795 MHz).
+ *    fsd, Tsd		Frequency, period of the SDLC communication.
  */
 
 #define _Ser1SDCR0	0x80020060	/* Ser. port 1 SDLC Control Reg. 0 */
@@ -645,110 +645,110 @@ typedef PCMCIAPrtType	PCMCIAType [PCMCIASp/PCMCIAPrtSp] ;
 #define _Ser1SDCR2	0x80020068	/* Ser. port 1 SDLC Control Reg. 2 */
 #define _Ser1SDCR3	0x8002006C	/* Ser. port 1 SDLC Control Reg. 3 */
 #define _Ser1SDCR4	0x80020070	/* Ser. port 1 SDLC Control Reg. 4 */
-#define _Ser1SDDR	0x80020078	/* Ser. port 1 SDLC Data Reg.      */
+#define _Ser1SDDR	0x80020078	/* Ser. port 1 SDLC Data Reg.	   */
 #define _Ser1SDSR0	0x80020080	/* Ser. port 1 SDLC Status Reg. 0  */
 #define _Ser1SDSR1	0x80020084	/* Ser. port 1 SDLC Status Reg. 1  */
 
 #if LANGUAGE == C
-#define Ser1SDCR0	        	/* Ser. port 1 SDLC Control Reg. 0 */ \
+#define Ser1SDCR0			/* Ser. port 1 SDLC Control Reg. 0 */ \
 			(*((volatile Word *) io_p2v (_Ser1SDCR0)))
-#define Ser1SDCR1	        	/* Ser. port 1 SDLC Control Reg. 1 */ \
+#define Ser1SDCR1			/* Ser. port 1 SDLC Control Reg. 1 */ \
 			(*((volatile Word *) io_p2v (_Ser1SDCR1)))
-#define Ser1SDCR2	        	/* Ser. port 1 SDLC Control Reg. 2 */ \
+#define Ser1SDCR2			/* Ser. port 1 SDLC Control Reg. 2 */ \
 			(*((volatile Word *) io_p2v (_Ser1SDCR2)))
-#define Ser1SDCR3	        	/* Ser. port 1 SDLC Control Reg. 3 */ \
+#define Ser1SDCR3			/* Ser. port 1 SDLC Control Reg. 3 */ \
 			(*((volatile Word *) io_p2v (_Ser1SDCR3)))
-#define Ser1SDCR4	        	/* Ser. port 1 SDLC Control Reg. 4 */ \
+#define Ser1SDCR4			/* Ser. port 1 SDLC Control Reg. 4 */ \
 			(*((volatile Word *) io_p2v (_Ser1SDCR4)))
-#define Ser1SDDR	        	/* Ser. port 1 SDLC Data Reg.      */ \
+#define Ser1SDDR			/* Ser. port 1 SDLC Data Reg.	   */ \
 			(*((volatile Word *) io_p2v (_Ser1SDDR)))
-#define Ser1SDSR0	        	/* Ser. port 1 SDLC Status Reg. 0  */ \
+#define Ser1SDSR0			/* Ser. port 1 SDLC Status Reg. 0  */ \
 			(*((volatile Word *) io_p2v (_Ser1SDSR0)))
-#define Ser1SDSR1	        	/* Ser. port 1 SDLC Status Reg. 1  */ \
+#define Ser1SDSR1			/* Ser. port 1 SDLC Status Reg. 1  */ \
 			(*((volatile Word *) io_p2v (_Ser1SDSR1)))
 #endif /* LANGUAGE == C */
 
-#define SDCR0_SUS	0x00000001	/* SDLC/UART Select                */
-#define SDCR0_SDLC	(SDCR0_SUS*0)	/*  SDLC mode (TXD1 & RXD1)        */
-#define SDCR0_UART	(SDCR0_SUS*1)	/*  UART mode (TXD1 & RXD1)        */
+#define SDCR0_SUS	0x00000001	/* SDLC/UART Select		   */
+#define SDCR0_SDLC	(SDCR0_SUS*0)	/*  SDLC mode (TXD1 & RXD1)	   */
+#define SDCR0_UART	(SDCR0_SUS*1)	/*  UART mode (TXD1 & RXD1)	   */
 #define SDCR0_SDF	0x00000002	/* Single/Double start Flag select */
-#define SDCR0_SglFlg	(SDCR0_SDF*0)	/*  Single start Flag              */
-#define SDCR0_DblFlg	(SDCR0_SDF*1)	/*  Double start Flag              */
-#define SDCR0_LBM	0x00000004	/* Look-Back Mode                  */
-#define SDCR0_BMS	0x00000008	/* Bit Modulation Select           */
-#define SDCR0_FM0	(SDCR0_BMS*0)	/*  Freq. Modulation zero (0)      */
+#define SDCR0_SglFlg	(SDCR0_SDF*0)	/*  Single start Flag		   */
+#define SDCR0_DblFlg	(SDCR0_SDF*1)	/*  Double start Flag		   */
+#define SDCR0_LBM	0x00000004	/* Look-Back Mode		   */
+#define SDCR0_BMS	0x00000008	/* Bit Modulation Select	   */
+#define SDCR0_FM0	(SDCR0_BMS*0)	/*  Freq. Modulation zero (0)	   */
 #define SDCR0_NRZ	(SDCR0_BMS*1)	/*  Non-Return to Zero modulation  */
 #define SDCR0_SCE	0x00000010	/* Sample Clock Enable (GPIO [16]) */
 #define SDCR0_SCD	0x00000020	/* Sample Clock Direction select   */
-					/* (GPIO [16])                     */
-#define SDCR0_SClkIn	(SDCR0_SCD*0)	/*  Sample Clock Input             */
-#define SDCR0_SClkOut	(SDCR0_SCD*1)	/*  Sample Clock Output            */
-#define SDCR0_RCE	0x00000040	/* Receive Clock Edge select       */
-#define SDCR0_RcRsEdg	(SDCR0_RCE*0)	/*  Receive clock Rising-Edge      */
-#define SDCR0_RcFlEdg	(SDCR0_RCE*1)	/*  Receive clock Falling-Edge     */
-#define SDCR0_TCE	0x00000080	/* Transmit Clock Edge select      */
-#define SDCR0_TrRsEdg	(SDCR0_TCE*0)	/*  Transmit clock Rising-Edge     */
+					/* (GPIO [16])			   */
+#define SDCR0_SClkIn	(SDCR0_SCD*0)	/*  Sample Clock Input		   */
+#define SDCR0_SClkOut	(SDCR0_SCD*1)	/*  Sample Clock Output		   */
+#define SDCR0_RCE	0x00000040	/* Receive Clock Edge select	   */
+#define SDCR0_RcRsEdg	(SDCR0_RCE*0)	/*  Receive clock Rising-Edge	   */
+#define SDCR0_RcFlEdg	(SDCR0_RCE*1)	/*  Receive clock Falling-Edge	   */
+#define SDCR0_TCE	0x00000080	/* Transmit Clock Edge select	   */
+#define SDCR0_TrRsEdg	(SDCR0_TCE*0)	/*  Transmit clock Rising-Edge	   */
 #define SDCR0_TrFlEdg	(SDCR0_TCE*1)	/*  Transmit clock Falling-Edge    */
 
-#define SDCR1_AAF	0x00000001	/* Abort After Frame enable        */
-					/* (GPIO [17])                     */
-#define SDCR1_TXE	0x00000002	/* Transmit Enable                 */
-#define SDCR1_RXE	0x00000004	/* Receive Enable                  */
+#define SDCR1_AAF	0x00000001	/* Abort After Frame enable	   */
+					/* (GPIO [17])			   */
+#define SDCR1_TXE	0x00000002	/* Transmit Enable		   */
+#define SDCR1_RXE	0x00000004	/* Receive Enable		   */
 #define SDCR1_RIE	0x00000008	/* Receive FIFO 1/3-to-2/3-full or */
-					/* more Interrupt Enable           */
+					/* more Interrupt Enable	   */
 #define SDCR1_TIE	0x00000010	/* Transmit FIFO 1/2-full or less  */
-					/* Interrupt Enable                */
-#define SDCR1_AME	0x00000020	/* Address Match Enable            */
+					/* Interrupt Enable		   */
+#define SDCR1_AME	0x00000020	/* Address Match Enable		   */
 #define SDCR1_TUS	0x00000040	/* Transmit FIFO Under-run Select  */
-#define SDCR1_EFrmURn	(SDCR1_TUS*0)	/*  End Frame on Under-Run         */
-#define SDCR1_AbortURn	(SDCR1_TUS*1)	/*  Abort on Under-Run             */
+#define SDCR1_EFrmURn	(SDCR1_TUS*0)	/*  End Frame on Under-Run	   */
+#define SDCR1_AbortURn	(SDCR1_TUS*1)	/*  Abort on Under-Run		   */
 #define SDCR1_RAE	0x00000080	/* Receive Abort interrupt Enable  */
 
-#define SDCR2_AMV	Fld (8, 0)	/* Address Match Value             */
+#define SDCR2_AMV	Fld (8, 0)	/* Address Match Value		   */
 
 #define SDCR3_BRD	Fld (4, 0)	/* Baud Rate Divisor/16 - 1 [11:8] */
 #define SDCR4_BRD	Fld (8, 0)	/* Baud Rate Divisor/16 - 1  [7:0] */
 					/* fsd = fxtl/(16*(BRD[11:0] + 1)) */
 					/* Tsd = 16*(BRD[11:0] + 1)*Txtl   */
-#define SDCR3_BdRtDiv(Div)      	/*  Baud Rate Divisor [16..65536]  */ \
+#define SDCR3_BdRtDiv(Div)		/*  Baud Rate Divisor [16..65536]  */ \
 			(((Div) - 16)/16 >> FSize (SDCR4_BRD) << \
 			 FShft (SDCR3_BRD))
-#define SDCR4_BdRtDiv(Div)      	/*  Baud Rate Divisor [16..65536]  */ \
+#define SDCR4_BdRtDiv(Div)		/*  Baud Rate Divisor [16..65536]  */ \
 			(((Div) - 16)/16 & FAlnMsk (SDCR4_BRD) << \
 			 FShft (SDCR4_BRD))
 					/*  fsd = fxtl/(16*Floor (Div/16)) */
 					/*  Tsd = 16*Floor (Div/16)*Txtl   */
-#define SDCR3_CeilBdRtDiv(Div)  	/*  Ceil. of BdRtDiv [16..65536]   */ \
+#define SDCR3_CeilBdRtDiv(Div)		/*  Ceil. of BdRtDiv [16..65536]   */ \
 			(((Div) - 1)/16 >> FSize (SDCR4_BRD) << \
 			 FShft (SDCR3_BRD))
-#define SDCR4_CeilBdRtDiv(Div)  	/*  Ceil. of BdRtDiv [16..65536]   */ \
+#define SDCR4_CeilBdRtDiv(Div)		/*  Ceil. of BdRtDiv [16..65536]   */ \
 			(((Div) - 1)/16 & FAlnMsk (SDCR4_BRD) << \
 			 FShft (SDCR4_BRD))
 					/*  fsd = fxtl/(16*Ceil (Div/16))  */
 					/*  Tsd = 16*Ceil (Div/16)*Txtl    */
 
-#define SDDR_DATA	Fld (8, 0)	/* receive/transmit DATA FIFOs     */
-#if 0           	        	/* Hidden receive FIFO bits        */
+#define SDDR_DATA	Fld (8, 0)	/* receive/transmit DATA FIFOs	   */
+#if 0					/* Hidden receive FIFO bits	   */
 #define SDDR_EOF	0x00000100	/*  receive End-Of-Frame (read)    */
-#define SDDR_CRE	0x00000200	/*  receive CRC Error (read)       */
+#define SDDR_CRE	0x00000200	/*  receive CRC Error (read)	   */
 #define SDDR_ROR	0x00000400	/*  Receive FIFO Over-Run (read)   */
 #endif /* 0 */
 
-#define SDSR0_EIF	0x00000001	/* Error In FIFO (read)            */
-#define SDSR0_TUR	0x00000002	/* Transmit FIFO Under-Run         */
-#define SDSR0_RAB	0x00000004	/* Receive ABort                   */
+#define SDSR0_EIF	0x00000001	/* Error In FIFO (read)		   */
+#define SDSR0_TUR	0x00000002	/* Transmit FIFO Under-Run	   */
+#define SDSR0_RAB	0x00000004	/* Receive ABort		   */
 #define SDSR0_TFS	0x00000008	/* Transmit FIFO 1/2-full or less  */
-					/* Service request (read)          */
+					/* Service request (read)	   */
 #define SDSR0_RFS	0x00000010	/* Receive FIFO 1/3-to-2/3-full or */
-					/* more Service request (read)     */
+					/* more Service request (read)	   */
 
 #define SDSR1_RSY	0x00000001	/* Receiver SYnchronized (read)    */
-#define SDSR1_TBY	0x00000002	/* Transmitter BusY (read)         */
+#define SDSR1_TBY	0x00000002	/* Transmitter BusY (read)	   */
 #define SDSR1_RNE	0x00000004	/* Receive FIFO Not Empty (read)   */
 #define SDSR1_TNF	0x00000008	/* Transmit FIFO Not Full (read)   */
-#define SDSR1_RTD	0x00000010	/* Receive Transition Detected     */
-#define SDSR1_EOF	0x00000020	/* receive End-Of-Frame (read)     */
-#define SDSR1_CRE	0x00000040	/* receive CRC Error (read)        */
+#define SDSR1_RTD	0x00000010	/* Receive Transition Detected	   */
+#define SDSR1_EOF	0x00000020	/* receive End-Of-Frame (read)	   */
+#define SDSR1_CRE	0x00000040	/* receive CRC Error (read)	   */
 #define SDSR1_ROR	0x00000080	/* Receive FIFO Over-Run (read)    */
 
 
@@ -756,159 +756,159 @@ typedef PCMCIAPrtType	PCMCIAType [PCMCIASp/PCMCIAPrtSp] ;
  * High-Speed Serial to Parallel controller (HSSP) control registers
  *
  * Registers
- *    Ser2HSCR0 	Serial port 2 High-Speed Serial to Parallel
- *              	controller (HSSP) Control Register 0 (read/write).
- *    Ser2HSCR1 	Serial port 2 High-Speed Serial to Parallel
- *              	controller (HSSP) Control Register 1 (read/write).
- *    Ser2HSDR  	Serial port 2 High-Speed Serial to Parallel
- *              	controller (HSSP) Data Register (read/write).
- *    Ser2HSSR0 	Serial port 2 High-Speed Serial to Parallel
- *              	controller (HSSP) Status Register 0 (read/write).
- *    Ser2HSSR1 	Serial port 2 High-Speed Serial to Parallel
- *              	controller (HSSP) Status Register 1 (read).
- *    Ser2HSCR2 	Serial port 2 High-Speed Serial to Parallel
- *              	controller (HSSP) Control Register 2 (read/write).
- *              	[The HSCR2 register is only implemented in
- *              	versions 2.0 (rev. = 8) and higher of the StrongARM
- *              	SA-1100.]
+ *    Ser2HSCR0		Serial port 2 High-Speed Serial to Parallel
+ *			controller (HSSP) Control Register 0 (read/write).
+ *    Ser2HSCR1		Serial port 2 High-Speed Serial to Parallel
+ *			controller (HSSP) Control Register 1 (read/write).
+ *    Ser2HSDR		Serial port 2 High-Speed Serial to Parallel
+ *			controller (HSSP) Data Register (read/write).
+ *    Ser2HSSR0		Serial port 2 High-Speed Serial to Parallel
+ *			controller (HSSP) Status Register 0 (read/write).
+ *    Ser2HSSR1		Serial port 2 High-Speed Serial to Parallel
+ *			controller (HSSP) Status Register 1 (read).
+ *    Ser2HSCR2		Serial port 2 High-Speed Serial to Parallel
+ *			controller (HSSP) Control Register 2 (read/write).
+ *			[The HSCR2 register is only implemented in
+ *			versions 2.0 (rev. = 8) and higher of the StrongARM
+ *			SA-1100.]
  */
 
 #define _Ser2HSCR0	0x80040060	/* Ser. port 2 HSSP Control Reg. 0 */
 #define _Ser2HSCR1	0x80040064	/* Ser. port 2 HSSP Control Reg. 1 */
-#define _Ser2HSDR	0x8004006C	/* Ser. port 2 HSSP Data Reg.      */
+#define _Ser2HSDR	0x8004006C	/* Ser. port 2 HSSP Data Reg.	   */
 #define _Ser2HSSR0	0x80040074	/* Ser. port 2 HSSP Status Reg. 0  */
 #define _Ser2HSSR1	0x80040078	/* Ser. port 2 HSSP Status Reg. 1  */
 #define _Ser2HSCR2	0x90060028	/* Ser. port 2 HSSP Control Reg. 2 */
 
 #if LANGUAGE == C
-#define Ser2HSCR0	        	/* Ser. port 2 HSSP Control Reg. 0 */ \
+#define Ser2HSCR0			/* Ser. port 2 HSSP Control Reg. 0 */ \
 			(*((volatile Word *) io_p2v (_Ser2HSCR0)))
-#define Ser2HSCR1	        	/* Ser. port 2 HSSP Control Reg. 1 */ \
+#define Ser2HSCR1			/* Ser. port 2 HSSP Control Reg. 1 */ \
 			(*((volatile Word *) io_p2v (_Ser2HSCR1)))
-#define Ser2HSDR	        	/* Ser. port 2 HSSP Data Reg.      */ \
+#define Ser2HSDR			/* Ser. port 2 HSSP Data Reg.	   */ \
 			(*((volatile Word *) io_p2v (_Ser2HSDR)))
-#define Ser2HSSR0	        	/* Ser. port 2 HSSP Status Reg. 0  */ \
+#define Ser2HSSR0			/* Ser. port 2 HSSP Status Reg. 0  */ \
 			(*((volatile Word *) io_p2v (_Ser2HSSR0)))
-#define Ser2HSSR1	        	/* Ser. port 2 HSSP Status Reg. 1  */ \
+#define Ser2HSSR1			/* Ser. port 2 HSSP Status Reg. 1  */ \
 			(*((volatile Word *) io_p2v (_Ser2HSSR1)))
-#define Ser2HSCR2	        	/* Ser. port 2 HSSP Control Reg. 2 */ \
+#define Ser2HSCR2			/* Ser. port 2 HSSP Control Reg. 2 */ \
 			(*((volatile Word *) io_p2v (_Ser2HSCR2)))
 #endif /* LANGUAGE == C */
 
-#define HSCR0_ITR	0x00000001	/* IrDA Transmission Rate          */
+#define HSCR0_ITR	0x00000001	/* IrDA Transmission Rate	   */
 #define HSCR0_UART	(HSCR0_ITR*0)	/*  UART mode (115.2 kb/s if IrDA) */
-#define HSCR0_HSSP	(HSCR0_ITR*1)	/*  HSSP mode (4 Mb/s)             */
-#define HSCR0_LBM	0x00000002	/* Look-Back Mode                  */
+#define HSCR0_HSSP	(HSCR0_ITR*1)	/*  HSSP mode (4 Mb/s)		   */
+#define HSCR0_LBM	0x00000002	/* Look-Back Mode		   */
 #define HSCR0_TUS	0x00000004	/* Transmit FIFO Under-run Select  */
-#define HSCR0_EFrmURn	(HSCR0_TUS*0)	/*  End Frame on Under-Run         */
-#define HSCR0_AbortURn	(HSCR0_TUS*1)	/*  Abort on Under-Run             */
-#define HSCR0_TXE	0x00000008	/* Transmit Enable                 */
-#define HSCR0_RXE	0x00000010	/* Receive Enable                  */
+#define HSCR0_EFrmURn	(HSCR0_TUS*0)	/*  End Frame on Under-Run	   */
+#define HSCR0_AbortURn	(HSCR0_TUS*1)	/*  Abort on Under-Run		   */
+#define HSCR0_TXE	0x00000008	/* Transmit Enable		   */
+#define HSCR0_RXE	0x00000010	/* Receive Enable		   */
 #define HSCR0_RIE	0x00000020	/* Receive FIFO 2/5-to-3/5-full or */
-					/* more Interrupt Enable           */
+					/* more Interrupt Enable	   */
 #define HSCR0_TIE	0x00000040	/* Transmit FIFO 1/2-full or less  */
-					/* Interrupt Enable                */
-#define HSCR0_AME	0x00000080	/* Address Match Enable            */
+					/* Interrupt Enable		   */
+#define HSCR0_AME	0x00000080	/* Address Match Enable		   */
 
-#define HSCR1_AMV	Fld (8, 0)	/* Address Match Value             */
+#define HSCR1_AMV	Fld (8, 0)	/* Address Match Value		   */
 
-#define HSDR_DATA	Fld (8, 0)	/* receive/transmit DATA FIFOs     */
-#if 0           	        	/* Hidden receive FIFO bits        */
+#define HSDR_DATA	Fld (8, 0)	/* receive/transmit DATA FIFOs	   */
+#if 0					/* Hidden receive FIFO bits	   */
 #define HSDR_EOF	0x00000100	/*  receive End-Of-Frame (read)    */
-#define HSDR_CRE	0x00000200	/*  receive CRC Error (read)       */
+#define HSDR_CRE	0x00000200	/*  receive CRC Error (read)	   */
 #define HSDR_ROR	0x00000400	/*  Receive FIFO Over-Run (read)   */
 #endif /* 0 */
 
-#define HSSR0_EIF	0x00000001	/* Error In FIFO (read)            */
-#define HSSR0_TUR	0x00000002	/* Transmit FIFO Under-Run         */
-#define HSSR0_RAB	0x00000004	/* Receive ABort                   */
+#define HSSR0_EIF	0x00000001	/* Error In FIFO (read)		   */
+#define HSSR0_TUR	0x00000002	/* Transmit FIFO Under-Run	   */
+#define HSSR0_RAB	0x00000004	/* Receive ABort		   */
 #define HSSR0_TFS	0x00000008	/* Transmit FIFO 1/2-full or less  */
-					/* Service request (read)          */
+					/* Service request (read)	   */
 #define HSSR0_RFS	0x00000010	/* Receive FIFO 2/5-to-3/5-full or */
-					/* more Service request (read)     */
-#define HSSR0_FRE	0x00000020	/* receive FRaming Error           */
+					/* more Service request (read)	   */
+#define HSSR0_FRE	0x00000020	/* receive FRaming Error	   */
 
 #define HSSR1_RSY	0x00000001	/* Receiver SYnchronized (read)    */
-#define HSSR1_TBY	0x00000002	/* Transmitter BusY (read)         */
+#define HSSR1_TBY	0x00000002	/* Transmitter BusY (read)	   */
 #define HSSR1_RNE	0x00000004	/* Receive FIFO Not Empty (read)   */
 #define HSSR1_TNF	0x00000008	/* Transmit FIFO Not Full (read)   */
-#define HSSR1_EOF	0x00000010	/* receive End-Of-Frame (read)     */
-#define HSSR1_CRE	0x00000020	/* receive CRC Error (read)        */
+#define HSSR1_EOF	0x00000010	/* receive End-Of-Frame (read)	   */
+#define HSSR1_CRE	0x00000020	/* receive CRC Error (read)	   */
 #define HSSR1_ROR	0x00000040	/* Receive FIFO Over-Run (read)    */
 
 #define HSCR2_TXP	0x00040000	/* Transmit data Polarity (TXD_2)  */
-#define HSCR2_TrDataL	(HSCR2_TXP*0)	/*  Transmit Data active Low       */
-					/*  (inverted)                     */
-#define HSCR2_TrDataH	(HSCR2_TXP*1)	/*  Transmit Data active High      */
-					/*  (non-inverted)                 */
+#define HSCR2_TrDataL	(HSCR2_TXP*0)	/*  Transmit Data active Low	   */
+					/*  (inverted)			   */
+#define HSCR2_TrDataH	(HSCR2_TXP*1)	/*  Transmit Data active High	   */
+					/*  (non-inverted)		   */
 #define HSCR2_RXP	0x00080000	/* Receive data Polarity (RXD_2)   */
-#define HSCR2_RcDataL	(HSCR2_RXP*0)	/*  Receive Data active Low        */
-					/*  (inverted)                     */
-#define HSCR2_RcDataH	(HSCR2_RXP*1)	/*  Receive Data active High       */
-					/*  (non-inverted)                 */
+#define HSCR2_RcDataL	(HSCR2_RXP*0)	/*  Receive Data active Low	   */
+					/*  (inverted)			   */
+#define HSCR2_RcDataH	(HSCR2_RXP*1)	/*  Receive Data active High	   */
+					/*  (non-inverted)		   */
 
 
 /*
  * Multi-media Communications Port (MCP) control registers
  *
  * Registers
- *    Ser4MCCR0 	Serial port 4 Multi-media Communications Port (MCP)
- *              	Control Register 0 (read/write).
- *    Ser4MCDR0 	Serial port 4 Multi-media Communications Port (MCP)
- *              	Data Register 0 (audio, read/write).
- *    Ser4MCDR1 	Serial port 4 Multi-media Communications Port (MCP)
- *              	Data Register 1 (telecom, read/write).
- *    Ser4MCDR2 	Serial port 4 Multi-media Communications Port (MCP)
- *              	Data Register 2 (CODEC registers, read/write).
- *    Ser4MCSR  	Serial port 4 Multi-media Communications Port (MCP)
- *              	Status Register (read/write).
- *    Ser4MCCR1 	Serial port 4 Multi-media Communications Port (MCP)
- *              	Control Register 1 (read/write).
- *              	[The MCCR1 register is only implemented in
- *              	versions 2.0 (rev. = 8) and higher of the StrongARM
- *              	SA-1100.]
+ *    Ser4MCCR0		Serial port 4 Multi-media Communications Port (MCP)
+ *			Control Register 0 (read/write).
+ *    Ser4MCDR0		Serial port 4 Multi-media Communications Port (MCP)
+ *			Data Register 0 (audio, read/write).
+ *    Ser4MCDR1		Serial port 4 Multi-media Communications Port (MCP)
+ *			Data Register 1 (telecom, read/write).
+ *    Ser4MCDR2		Serial port 4 Multi-media Communications Port (MCP)
+ *			Data Register 2 (CODEC registers, read/write).
+ *    Ser4MCSR		Serial port 4 Multi-media Communications Port (MCP)
+ *			Status Register (read/write).
+ *    Ser4MCCR1		Serial port 4 Multi-media Communications Port (MCP)
+ *			Control Register 1 (read/write).
+ *			[The MCCR1 register is only implemented in
+ *			versions 2.0 (rev. = 8) and higher of the StrongARM
+ *			SA-1100.]
  *
  * Clocks
- *    fmc, Tmc  	Frequency, period of the MCP communication (10 MHz,
- *              	12 MHz, or GPIO [21]).
+ *    fmc, Tmc		Frequency, period of the MCP communication (10 MHz,
+ *			12 MHz, or GPIO [21]).
  *    faud, Taud	Frequency, period of the audio sampling.
  *    ftcm, Ttcm	Frequency, period of the telecom sampling.
  */
 
 #define _Ser4MCCR0	0x80060000	/* Ser. port 4 MCP Control Reg. 0  */
-#define _Ser4MCDR0	0x80060008	/* Ser. port 4 MCP Data Reg. 0     */
-					/* (audio)                         */
-#define _Ser4MCDR1	0x8006000C	/* Ser. port 4 MCP Data Reg. 1     */
-					/* (telecom)                       */
-#define _Ser4MCDR2	0x80060010	/* Ser. port 4 MCP Data Reg. 2     */
-					/* (CODEC reg.)                    */
-#define _Ser4MCSR	0x80060018	/* Ser. port 4 MCP Status Reg.     */
+#define _Ser4MCDR0	0x80060008	/* Ser. port 4 MCP Data Reg. 0	   */
+					/* (audio)			   */
+#define _Ser4MCDR1	0x8006000C	/* Ser. port 4 MCP Data Reg. 1	   */
+					/* (telecom)			   */
+#define _Ser4MCDR2	0x80060010	/* Ser. port 4 MCP Data Reg. 2	   */
+					/* (CODEC reg.)			   */
+#define _Ser4MCSR	0x80060018	/* Ser. port 4 MCP Status Reg.	   */
 #define _Ser4MCCR1	0x90060030	/* Ser. port 4 MCP Control Reg. 1  */
 
 #if LANGUAGE == C
-#define Ser4MCCR0	        	/* Ser. port 4 MCP Control Reg. 0  */ \
+#define Ser4MCCR0			/* Ser. port 4 MCP Control Reg. 0  */ \
 			(*((volatile Word *) io_p2v (_Ser4MCCR0)))
-#define Ser4MCDR0	        	/* Ser. port 4 MCP Data Reg. 0     */ \
-					/* (audio)                         */ \
+#define Ser4MCDR0			/* Ser. port 4 MCP Data Reg. 0	   */ \
+					/* (audio)			   */ \
 			(*((volatile Word *) io_p2v (_Ser4MCDR0)))
-#define Ser4MCDR1	        	/* Ser. port 4 MCP Data Reg. 1     */ \
-					/* (telecom)                       */ \
+#define Ser4MCDR1			/* Ser. port 4 MCP Data Reg. 1	   */ \
+					/* (telecom)			   */ \
 			(*((volatile Word *) io_p2v (_Ser4MCDR1)))
-#define Ser4MCDR2	        	/* Ser. port 4 MCP Data Reg. 2     */ \
-					/* (CODEC reg.)                    */ \
+#define Ser4MCDR2			/* Ser. port 4 MCP Data Reg. 2	   */ \
+					/* (CODEC reg.)			   */ \
 			(*((volatile Word *) io_p2v (_Ser4MCDR2)))
-#define Ser4MCSR	        	/* Ser. port 4 MCP Status Reg.     */ \
+#define Ser4MCSR			/* Ser. port 4 MCP Status Reg.	   */ \
 			(*((volatile Word *) io_p2v (_Ser4MCSR)))
-#define Ser4MCCR1	        	/* Ser. port 4 MCP Control Reg. 1  */ \
+#define Ser4MCCR1			/* Ser. port 4 MCP Control Reg. 1  */ \
 			(*((volatile Word *) io_p2v (_Ser4MCCR1)))
 #endif /* LANGUAGE == C */
 
 #define MCCR0_ASD	Fld (7, 0)	/* Audio Sampling rate Divisor/32  */
-					/* [6..127]                        */
-					/* faud = fmc/(32*ASD)             */
-					/* Taud = 32*ASD*Tmc               */
-#define MCCR0_AudSmpDiv(Div)    	/*  Audio Sampling rate Divisor    */ \
-					/*  [192..4064]                    */ \
+					/* [6..127]			   */
+					/* faud = fmc/(32*ASD)		   */
+					/* Taud = 32*ASD*Tmc		   */
+#define MCCR0_AudSmpDiv(Div)		/*  Audio Sampling rate Divisor    */ \
+					/*  [192..4064]			   */ \
 			((Div)/32 << FShft (MCCR0_ASD))
 					/*  faud = fmc/(32*Floor (Div/32)) */
 					/*  Taud = 32*Floor (Div/32)*Tmc   */
@@ -916,12 +916,12 @@ typedef PCMCIAPrtType	PCMCIAType [PCMCIASp/PCMCIAPrtSp] ;
 			(((Div) + 31)/32 << FShft (MCCR0_ASD))
 					/*  faud = fmc/(32*Ceil (Div/32))  */
 					/*  Taud = 32*Ceil (Div/32)*Tmc    */
-#define MCCR0_TSD	Fld (7, 8)	/* Telecom Sampling rate           */
-					/* Divisor/32 [16..127]            */
-					/* ftcm = fmc/(32*TSD)             */
-					/* Ttcm = 32*TSD*Tmc               */
-#define MCCR0_TcmSmpDiv(Div)    	/*  Telecom Sampling rate Divisor  */ \
-					/*  [512..4064]                    */ \
+#define MCCR0_TSD	Fld (7, 8)	/* Telecom Sampling rate	   */
+					/* Divisor/32 [16..127]		   */
+					/* ftcm = fmc/(32*TSD)		   */
+					/* Ttcm = 32*TSD*Tmc		   */
+#define MCCR0_TcmSmpDiv(Div)		/*  Telecom Sampling rate Divisor  */ \
+					/*  [512..4064]			   */ \
 			((Div)/32 << FShft (MCCR0_TSD))
 					/*  ftcm = fmc/(32*Floor (Div/32)) */
 					/*  Ttcm = 32*Floor (Div/32)*Tmc   */
@@ -929,460 +929,460 @@ typedef PCMCIAPrtType	PCMCIAType [PCMCIASp/PCMCIAPrtSp] ;
 			(((Div) + 31)/32 << FShft (MCCR0_TSD))
 					/*  ftcm = fmc/(32*Ceil (Div/32))  */
 					/*  Ttcm = 32*Ceil (Div/32)*Tmc    */
-#define MCCR0_MCE	0x00010000	/* MCP Enable                      */
-#define MCCR0_ECS	0x00020000	/* External Clock Select           */
+#define MCCR0_MCE	0x00010000	/* MCP Enable			   */
+#define MCCR0_ECS	0x00020000	/* External Clock Select	   */
 #define MCCR0_IntClk	(MCCR0_ECS*0)	/*  Internal Clock (10 or 12 MHz)  */
-#define MCCR0_ExtClk	(MCCR0_ECS*1)	/*  External Clock (GPIO [21])     */
-#define MCCR0_ADM	0x00040000	/* A/D (audio/telecom) data        */
-					/* sampling/storing Mode           */
-#define MCCR0_VldBit	(MCCR0_ADM*0)	/*  Valid Bit storing mode         */
+#define MCCR0_ExtClk	(MCCR0_ECS*1)	/*  External Clock (GPIO [21])	   */
+#define MCCR0_ADM	0x00040000	/* A/D (audio/telecom) data	   */
+					/* sampling/storing Mode	   */
+#define MCCR0_VldBit	(MCCR0_ADM*0)	/*  Valid Bit storing mode	   */
 #define MCCR0_SmpCnt	(MCCR0_ADM*1)	/*  Sampling Counter storing mode  */
 #define MCCR0_TTE	0x00080000	/* Telecom Transmit FIFO 1/2-full  */
-					/* or less interrupt Enable        */
+					/* or less interrupt Enable	   */
 #define MCCR0_TRE	0x00100000	/* Telecom Receive FIFO 1/2-full   */
-					/* or more interrupt Enable        */
+					/* or more interrupt Enable	   */
 #define MCCR0_ATE	0x00200000	/* Audio Transmit FIFO 1/2-full    */
-					/* or less interrupt Enable        */
+					/* or less interrupt Enable	   */
 #define MCCR0_ARE	0x00400000	/* Audio Receive FIFO 1/2-full or  */
-					/* more interrupt Enable           */
-#define MCCR0_LBM	0x00800000	/* Look-Back Mode                  */
+					/* more interrupt Enable	   */
+#define MCCR0_LBM	0x00800000	/* Look-Back Mode		   */
 #define MCCR0_ECP	Fld (2, 24)	/* External Clock Prescaler - 1    */
-#define MCCR0_ExtClkDiv(Div)    	/*  External Clock Divisor [1..4]  */ \
+#define MCCR0_ExtClkDiv(Div)		/*  External Clock Divisor [1..4]  */ \
 			(((Div) - 1) << FShft (MCCR0_ECP))
 
-#define MCDR0_DATA	Fld (12, 4)	/* receive/transmit audio DATA     */
-					/* FIFOs                           */
+#define MCDR0_DATA	Fld (12, 4)	/* receive/transmit audio DATA	   */
+					/* FIFOs			   */
 
 #define MCDR1_DATA	Fld (14, 2)	/* receive/transmit telecom DATA   */
-					/* FIFOs                           */
+					/* FIFOs			   */
 
-					/* receive/transmit CODEC reg.     */
-					/* FIFOs:                          */
-#define MCDR2_DATA	Fld (16, 0)	/*  reg. DATA                      */
-#define MCDR2_RW	0x00010000	/*  reg. Read/Write (transmit)     */
-#define MCDR2_Rd	(MCDR2_RW*0)	/*   reg. Read                     */
-#define MCDR2_Wr	(MCDR2_RW*1)	/*   reg. Write                    */
-#define MCDR2_ADD	Fld (4, 17)	/*  reg. ADDress                   */
+					/* receive/transmit CODEC reg.	   */
+					/* FIFOs:			   */
+#define MCDR2_DATA	Fld (16, 0)	/*  reg. DATA			   */
+#define MCDR2_RW	0x00010000	/*  reg. Read/Write (transmit)	   */
+#define MCDR2_Rd	(MCDR2_RW*0)	/*   reg. Read			   */
+#define MCDR2_Wr	(MCDR2_RW*1)	/*   reg. Write			   */
+#define MCDR2_ADD	Fld (4, 17)	/*  reg. ADDress		   */
 
 #define MCSR_ATS	0x00000001	/* Audio Transmit FIFO 1/2-full    */
 					/* or less Service request (read)  */
 #define MCSR_ARS	0x00000002	/* Audio Receive FIFO 1/2-full or  */
-					/* more Service request (read)     */
+					/* more Service request (read)	   */
 #define MCSR_TTS	0x00000004	/* Telecom Transmit FIFO 1/2-full  */
 					/* or less Service request (read)  */
 #define MCSR_TRS	0x00000008	/* Telecom Receive FIFO 1/2-full   */
 					/* or more Service request (read)  */
 #define MCSR_ATU	0x00000010	/* Audio Transmit FIFO Under-run   */
-#define MCSR_ARO	0x00000020	/* Audio Receive FIFO Over-run     */
+#define MCSR_ARO	0x00000020	/* Audio Receive FIFO Over-run	   */
 #define MCSR_TTU	0x00000040	/* Telecom Transmit FIFO Under-run */
 #define MCSR_TRO	0x00000080	/* Telecom Receive FIFO Over-run   */
 #define MCSR_ANF	0x00000100	/* Audio transmit FIFO Not Full    */
-					/* (read)                          */
+					/* (read)			   */
 #define MCSR_ANE	0x00000200	/* Audio receive FIFO Not Empty    */
-					/* (read)                          */
+					/* (read)			   */
 #define MCSR_TNF	0x00000400	/* Telecom transmit FIFO Not Full  */
-					/* (read)                          */
+					/* (read)			   */
 #define MCSR_TNE	0x00000800	/* Telecom receive FIFO Not Empty  */
-					/* (read)                          */
+					/* (read)			   */
 #define MCSR_CWC	0x00001000	/* CODEC register Write Completed  */
-					/* (read)                          */
+					/* (read)			   */
 #define MCSR_CRC	0x00002000	/* CODEC register Read Completed   */
-					/* (read)                          */
-#define MCSR_ACE	0x00004000	/* Audio CODEC Enabled (read)      */
+					/* (read)			   */
+#define MCSR_ACE	0x00004000	/* Audio CODEC Enabled (read)	   */
 #define MCSR_TCE	0x00008000	/* Telecom CODEC Enabled (read)    */
 
-#define MCCR1_CFS	0x00100000	/* Clock Freq. Select              */
-#define MCCR1_F12MHz	(MCCR1_CFS*0)	/*  Freq. (fmc) = ~ 12 MHz         */
-					/*  (11.981 MHz)                   */
-#define MCCR1_F10MHz	(MCCR1_CFS*1)	/*  Freq. (fmc) = ~ 10 MHz         */
-					/*  (9.585 MHz)                    */
+#define MCCR1_CFS	0x00100000	/* Clock Freq. Select		   */
+#define MCCR1_F12MHz	(MCCR1_CFS*0)	/*  Freq. (fmc) = ~ 12 MHz	   */
+					/*  (11.981 MHz)		   */
+#define MCCR1_F10MHz	(MCCR1_CFS*1)	/*  Freq. (fmc) = ~ 10 MHz	   */
+					/*  (9.585 MHz)			   */
 
 
 /*
  * Synchronous Serial Port (SSP) control registers
  *
  * Registers
- *    Ser4SSCR0 	Serial port 4 Synchronous Serial Port (SSP) Control
- *              	Register 0 (read/write).
- *    Ser4SSCR1 	Serial port 4 Synchronous Serial Port (SSP) Control
- *              	Register 1 (read/write).
- *              	[Bits SPO and SP are only implemented in versions 2.0
- *              	(rev. = 8) and higher of the StrongARM SA-1100.]
- *    Ser4SSDR  	Serial port 4 Synchronous Serial Port (SSP) Data
- *              	Register (read/write).
- *    Ser4SSSR  	Serial port 4 Synchronous Serial Port (SSP) Status
- *              	Register (read/write).
+ *    Ser4SSCR0		Serial port 4 Synchronous Serial Port (SSP) Control
+ *			Register 0 (read/write).
+ *    Ser4SSCR1		Serial port 4 Synchronous Serial Port (SSP) Control
+ *			Register 1 (read/write).
+ *			[Bits SPO and SP are only implemented in versions 2.0
+ *			(rev. = 8) and higher of the StrongARM SA-1100.]
+ *    Ser4SSDR		Serial port 4 Synchronous Serial Port (SSP) Data
+ *			Register (read/write).
+ *    Ser4SSSR		Serial port 4 Synchronous Serial Port (SSP) Status
+ *			Register (read/write).
  *
  * Clocks
  *    fxtl, Txtl	Frequency, period of the system crystal (3.6864 MHz
- *              	or 3.5795 MHz).
- *    fss, Tss  	Frequency, period of the SSP communication.
+ *			or 3.5795 MHz).
+ *    fss, Tss		Frequency, period of the SSP communication.
  */
 
 #define _Ser4SSCR0	0x80070060	/* Ser. port 4 SSP Control Reg. 0  */
 #define _Ser4SSCR1	0x80070064	/* Ser. port 4 SSP Control Reg. 1  */
-#define _Ser4SSDR	0x8007006C	/* Ser. port 4 SSP Data Reg.       */
-#define _Ser4SSSR	0x80070074	/* Ser. port 4 SSP Status Reg.     */
+#define _Ser4SSDR	0x8007006C	/* Ser. port 4 SSP Data Reg.	   */
+#define _Ser4SSSR	0x80070074	/* Ser. port 4 SSP Status Reg.	   */
 
 #if LANGUAGE == C
-#define Ser4SSCR0	        	/* Ser. port 4 SSP Control Reg. 0  */ \
+#define Ser4SSCR0			/* Ser. port 4 SSP Control Reg. 0  */ \
 			(*((volatile Word *) io_p2v (_Ser4SSCR0)))
-#define Ser4SSCR1	        	/* Ser. port 4 SSP Control Reg. 1  */ \
+#define Ser4SSCR1			/* Ser. port 4 SSP Control Reg. 1  */ \
 			(*((volatile Word *) io_p2v (_Ser4SSCR1)))
-#define Ser4SSDR	        	/* Ser. port 4 SSP Data Reg.       */ \
+#define Ser4SSDR			/* Ser. port 4 SSP Data Reg.	   */ \
 			(*((volatile Word *) io_p2v (_Ser4SSDR)))
-#define Ser4SSSR	        	/* Ser. port 4 SSP Status Reg.     */ \
+#define Ser4SSSR			/* Ser. port 4 SSP Status Reg.	   */ \
 			(*((volatile Word *) io_p2v (_Ser4SSSR)))
 #endif /* LANGUAGE == C */
 
 #define SSCR0_DSS	Fld (4, 0)	/* Data Size - 1 Select [3..15]    */
-#define SSCR0_DataSize(Size)    	/*  Data Size Select [4..16]       */ \
+#define SSCR0_DataSize(Size)		/*  Data Size Select [4..16]	   */ \
 			(((Size) - 1) << FShft (SSCR0_DSS))
-#define SSCR0_FRF	Fld (2, 4)	/* FRame Format                    */
-#define SSCR0_Motorola	        	/*  Motorola Serial Peripheral     */ \
-					/*  Interface (SPI) format         */ \
+#define SSCR0_FRF	Fld (2, 4)	/* FRame Format			   */
+#define SSCR0_Motorola			/*  Motorola Serial Peripheral	   */ \
+					/*  Interface (SPI) format	   */ \
 			(0 << FShft (SSCR0_FRF))
-#define SSCR0_TI	        	/*  Texas Instruments Synchronous  */ \
-					/*  Serial format                  */ \
+#define SSCR0_TI			/*  Texas Instruments Synchronous  */ \
+					/*  Serial format		   */ \
 			(1 << FShft (SSCR0_FRF))
-#define SSCR0_National	        	/*  National Microwire format      */ \
+#define SSCR0_National			/*  National Microwire format	   */ \
 			(2 << FShft (SSCR0_FRF))
-#define SSCR0_SSE	0x00000080	/* SSP Enable                      */
+#define SSCR0_SSE	0x00000080	/* SSP Enable			   */
 #define SSCR0_SCR	Fld (8, 8)	/* Serial Clock Rate divisor/2 - 1 */
-					/* fss = fxtl/(2*(SCR + 1))        */
-					/* Tss = 2*(SCR + 1)*Txtl          */
-#define SSCR0_SerClkDiv(Div)    	/*  Serial Clock Divisor [2..512]  */ \
+					/* fss = fxtl/(2*(SCR + 1))	   */
+					/* Tss = 2*(SCR + 1)*Txtl	   */
+#define SSCR0_SerClkDiv(Div)		/*  Serial Clock Divisor [2..512]  */ \
 			(((Div) - 2)/2 << FShft (SSCR0_SCR))
 					/*  fss = fxtl/(2*Floor (Div/2))   */
-					/*  Tss = 2*Floor (Div/2)*Txtl     */
+					/*  Tss = 2*Floor (Div/2)*Txtl	   */
 #define SSCR0_CeilSerClkDiv(Div)	/*  Ceil. of SerClkDiv [2..512]    */ \
 			(((Div) - 1)/2 << FShft (SSCR0_SCR))
 					/*  fss = fxtl/(2*Ceil (Div/2))    */
-					/*  Tss = 2*Ceil (Div/2)*Txtl      */
+					/*  Tss = 2*Ceil (Div/2)*Txtl	   */
 
 #define SSCR1_RIE	0x00000001	/* Receive FIFO 1/2-full or more   */
-					/* Interrupt Enable                */
+					/* Interrupt Enable		   */
 #define SSCR1_TIE	0x00000002	/* Transmit FIFO 1/2-full or less  */
-					/* Interrupt Enable                */
-#define SSCR1_LBM	0x00000004	/* Look-Back Mode                  */
+					/* Interrupt Enable		   */
+#define SSCR1_LBM	0x00000004	/* Look-Back Mode		   */
 #define SSCR1_SPO	0x00000008	/* Sample clock (SCLK) POlarity    */
-#define SSCR1_SClkIactL	(SSCR1_SPO*0)	/*  Sample Clock Inactive Low      */
-#define SSCR1_SClkIactH	(SSCR1_SPO*1)	/*  Sample Clock Inactive High     */
-#define SSCR1_SP	0x00000010	/* Sample clock (SCLK) Phase       */
+#define SSCR1_SClkIactL	(SSCR1_SPO*0)	/*  Sample Clock Inactive Low	   */
+#define SSCR1_SClkIactH	(SSCR1_SPO*1)	/*  Sample Clock Inactive High	   */
+#define SSCR1_SP	0x00000010	/* Sample clock (SCLK) Phase	   */
 #define SSCR1_SClk1P	(SSCR1_SP*0)	/*  Sample Clock active 1 Period   */
 					/*  after frame (SFRM, 1st edge)   */
 #define SSCR1_SClk1_2P	(SSCR1_SP*1)	/*  Sample Clock active 1/2 Period */
 					/*  after frame (SFRM, 1st edge)   */
-#define SSCR1_ECS	0x00000020	/* External Clock Select           */
-#define SSCR1_IntClk	(SSCR1_ECS*0)	/*  Internal Clock                 */
-#define SSCR1_ExtClk	(SSCR1_ECS*1)	/*  External Clock (GPIO [19])     */
+#define SSCR1_ECS	0x00000020	/* External Clock Select	   */
+#define SSCR1_IntClk	(SSCR1_ECS*0)	/*  Internal Clock		   */
+#define SSCR1_ExtClk	(SSCR1_ECS*1)	/*  External Clock (GPIO [19])	   */
 
-#define SSDR_DATA	Fld (16, 0)	/* receive/transmit DATA FIFOs     */
+#define SSDR_DATA	Fld (16, 0)	/* receive/transmit DATA FIFOs	   */
 
 #define SSSR_TNF	0x00000002	/* Transmit FIFO Not Full (read)   */
 #define SSSR_RNE	0x00000004	/* Receive FIFO Not Empty (read)   */
-#define SSSR_BSY	0x00000008	/* SSP BuSY (read)                 */
+#define SSSR_BSY	0x00000008	/* SSP BuSY (read)		   */
 #define SSSR_TFS	0x00000010	/* Transmit FIFO 1/2-full or less  */
-					/* Service request (read)          */
+					/* Service request (read)	   */
 #define SSSR_RFS	0x00000020	/* Receive FIFO 1/2-full or more   */
-					/* Service request (read)          */
-#define SSSR_ROR	0x00000040	/* Receive FIFO Over-Run           */
+					/* Service request (read)	   */
+#define SSSR_ROR	0x00000040	/* Receive FIFO Over-Run	   */
 
 
 /*
  * Operating System (OS) timer control registers
  *
  * Registers
- *    OSMR0     	Operating System (OS) timer Match Register 0
- *              	(read/write).
- *    OSMR1     	Operating System (OS) timer Match Register 1
- *              	(read/write).
- *    OSMR2     	Operating System (OS) timer Match Register 2
- *              	(read/write).
- *    OSMR3     	Operating System (OS) timer Match Register 3
- *              	(read/write).
- *    OSCR      	Operating System (OS) timer Counter Register
- *              	(read/write).
- *    OSSR      	Operating System (OS) timer Status Register
- *              	(read/write).
- *    OWER      	Operating System (OS) timer Watch-dog Enable Register
- *              	(read/write).
- *    OIER      	Operating System (OS) timer Interrupt Enable Register
- *              	(read/write).
+ *    OSMR0		Operating System (OS) timer Match Register 0
+ *			(read/write).
+ *    OSMR1		Operating System (OS) timer Match Register 1
+ *			(read/write).
+ *    OSMR2		Operating System (OS) timer Match Register 2
+ *			(read/write).
+ *    OSMR3		Operating System (OS) timer Match Register 3
+ *			(read/write).
+ *    OSCR		Operating System (OS) timer Counter Register
+ *			(read/write).
+ *    OSSR		Operating System (OS) timer Status Register
+ *			(read/write).
+ *    OWER		Operating System (OS) timer Watch-dog Enable Register
+ *			(read/write).
+ *    OIER		Operating System (OS) timer Interrupt Enable Register
+ *			(read/write).
  */
 
-#define _OSMR(Nb)	        	/* OS timer Match Reg. [0..3]      */ \
+#define _OSMR(Nb)			/* OS timer Match Reg. [0..3]	   */ \
 			(0x90000000 + (Nb)*4)
-#define _OSMR0  	_OSMR (0)	/* OS timer Match Reg. 0           */
-#define _OSMR1  	_OSMR (1)	/* OS timer Match Reg. 1           */
-#define _OSMR2  	_OSMR (2)	/* OS timer Match Reg. 2           */
-#define _OSMR3  	_OSMR (3)	/* OS timer Match Reg. 3           */
-#define _OSCR   	0x90000010	/* OS timer Counter Reg.           */
-#define _OSSR   	0x90000014	/* OS timer Status Reg.            */
-#define _OWER   	0x90000018	/* OS timer Watch-dog Enable Reg.  */
-#define _OIER   	0x9000001C	/* OS timer Interrupt Enable Reg.  */
+#define _OSMR0		_OSMR (0)	/* OS timer Match Reg. 0	   */
+#define _OSMR1		_OSMR (1)	/* OS timer Match Reg. 1	   */
+#define _OSMR2		_OSMR (2)	/* OS timer Match Reg. 2	   */
+#define _OSMR3		_OSMR (3)	/* OS timer Match Reg. 3	   */
+#define _OSCR		0x90000010	/* OS timer Counter Reg.	   */
+#define _OSSR		0x90000014	/* OS timer Status Reg.		   */
+#define _OWER		0x90000018	/* OS timer Watch-dog Enable Reg.  */
+#define _OIER		0x9000001C	/* OS timer Interrupt Enable Reg.  */
 
 #if LANGUAGE == C
-#define OSMR    	        	/* OS timer Match Reg. [0..3]      */ \
+#define OSMR				/* OS timer Match Reg. [0..3]	   */ \
 			((volatile Word *) io_p2v (_OSMR (0)))
-#define OSMR0   	(OSMR [0])	/* OS timer Match Reg. 0           */
-#define OSMR1   	(OSMR [1])	/* OS timer Match Reg. 1           */
-#define OSMR2   	(OSMR [2])	/* OS timer Match Reg. 2           */
-#define OSMR3   	(OSMR [3])	/* OS timer Match Reg. 3           */
-#define OSCR    	        	/* OS timer Counter Reg.           */ \
+#define OSMR0		(OSMR [0])	/* OS timer Match Reg. 0	   */
+#define OSMR1		(OSMR [1])	/* OS timer Match Reg. 1	   */
+#define OSMR2		(OSMR [2])	/* OS timer Match Reg. 2	   */
+#define OSMR3		(OSMR [3])	/* OS timer Match Reg. 3	   */
+#define OSCR				/* OS timer Counter Reg.	   */ \
 			(*((volatile Word *) io_p2v (_OSCR)))
-#define OSSR    	        	/* OS timer Status Reg.            */ \
+#define OSSR				/* OS timer Status Reg.		   */ \
 			(*((volatile Word *) io_p2v (_OSSR)))
-#define OWER    	        	/* OS timer Watch-dog Enable Reg.  */ \
+#define OWER				/* OS timer Watch-dog Enable Reg.  */ \
 			(*((volatile Word *) io_p2v (_OWER)))
-#define OIER    	        	/* OS timer Interrupt Enable Reg.  */ \
+#define OIER				/* OS timer Interrupt Enable Reg.  */ \
 			(*((volatile Word *) io_p2v (_OIER)))
 #endif /* LANGUAGE == C */
 
-#define OSSR_M(Nb)	        	/* Match detected [0..3]           */ \
+#define OSSR_M(Nb)			/* Match detected [0..3]	   */ \
 			(0x00000001 << (Nb))
-#define OSSR_M0 	OSSR_M (0)	/* Match detected 0                */
-#define OSSR_M1 	OSSR_M (1)	/* Match detected 1                */
-#define OSSR_M2 	OSSR_M (2)	/* Match detected 2                */
-#define OSSR_M3 	OSSR_M (3)	/* Match detected 3                */
+#define OSSR_M0		OSSR_M (0)	/* Match detected 0		   */
+#define OSSR_M1		OSSR_M (1)	/* Match detected 1		   */
+#define OSSR_M2		OSSR_M (2)	/* Match detected 2		   */
+#define OSSR_M3		OSSR_M (3)	/* Match detected 3		   */
 
-#define OWER_WME	0x00000001	/* Watch-dog Match Enable          */
-					/* (set only)                      */
+#define OWER_WME	0x00000001	/* Watch-dog Match Enable	   */
+					/* (set only)			   */
 
-#define OIER_E(Nb)	        	/* match interrupt Enable [0..3]   */ \
+#define OIER_E(Nb)			/* match interrupt Enable [0..3]   */ \
 			(0x00000001 << (Nb))
-#define OIER_E0 	OIER_E (0)	/* match interrupt Enable 0        */
-#define OIER_E1 	OIER_E (1)	/* match interrupt Enable 1        */
-#define OIER_E2 	OIER_E (2)	/* match interrupt Enable 2        */
-#define OIER_E3 	OIER_E (3)	/* match interrupt Enable 3        */
+#define OIER_E0		OIER_E (0)	/* match interrupt Enable 0	   */
+#define OIER_E1		OIER_E (1)	/* match interrupt Enable 1	   */
+#define OIER_E2		OIER_E (2)	/* match interrupt Enable 2	   */
+#define OIER_E3		OIER_E (3)	/* match interrupt Enable 3	   */
 
 
 /*
  * Real-Time Clock (RTC) control registers
  *
  * Registers
- *    RTAR      	Real-Time Clock (RTC) Alarm Register (read/write).
- *    RCNR      	Real-Time Clock (RTC) CouNt Register (read/write).
- *    RTTR      	Real-Time Clock (RTC) Trim Register (read/write).
- *    RTSR      	Real-Time Clock (RTC) Status Register (read/write).
+ *    RTAR		Real-Time Clock (RTC) Alarm Register (read/write).
+ *    RCNR		Real-Time Clock (RTC) CouNt Register (read/write).
+ *    RTTR		Real-Time Clock (RTC) Trim Register (read/write).
+ *    RTSR		Real-Time Clock (RTC) Status Register (read/write).
  *
  * Clocks
  *    frtx, Trtx	Frequency, period of the real-time clock crystal
- *              	(32.768 kHz nominal).
+ *			(32.768 kHz nominal).
  *    frtc, Trtc	Frequency, period of the real-time clock counter
- *              	(1 Hz nominal).
+ *			(1 Hz nominal).
  */
 
-#define _RTAR   	0x90010000	/* RTC Alarm Reg.                  */
-#define _RCNR   	0x90010004	/* RTC CouNt Reg.                  */
-#define _RTTR   	0x90010008	/* RTC Trim Reg.                   */
-#define _RTSR   	0x90010010	/* RTC Status Reg.                 */
+#define _RTAR		0x90010000	/* RTC Alarm Reg.		   */
+#define _RCNR		0x90010004	/* RTC CouNt Reg.		   */
+#define _RTTR		0x90010008	/* RTC Trim Reg.		   */
+#define _RTSR		0x90010010	/* RTC Status Reg.		   */
 
 #if LANGUAGE == C
-#define RTAR    	        	/* RTC Alarm Reg.                  */ \
+#define RTAR				/* RTC Alarm Reg.		   */ \
 			(*((volatile Word *) io_p2v (_RTAR)))
-#define RCNR    	        	/* RTC CouNt Reg.                  */ \
+#define RCNR				/* RTC CouNt Reg.		   */ \
 			(*((volatile Word *) io_p2v (_RCNR)))
-#define RTTR    	        	/* RTC Trim Reg.                   */ \
+#define RTTR				/* RTC Trim Reg.		   */ \
 			(*((volatile Word *) io_p2v (_RTTR)))
-#define RTSR    	        	/* RTC Status Reg.                 */ \
+#define RTSR				/* RTC Status Reg.		   */ \
 			(*((volatile Word *) io_p2v (_RTSR)))
 #endif /* LANGUAGE == C */
 
-#define RTTR_C  	Fld (16, 0)	/* clock divider Count - 1         */
-#define RTTR_D  	Fld (10, 16)	/* trim Delete count               */
+#define RTTR_C		Fld (16, 0)	/* clock divider Count - 1	   */
+#define RTTR_D		Fld (10, 16)	/* trim Delete count		   */
 					/* frtc = (1023*(C + 1) - D)*frtx/ */
-					/*        (1023*(C + 1)^2)         */
+					/*	  (1023*(C + 1)^2)	   */
 					/* Trtc = (1023*(C + 1)^2)*Trtx/   */
-					/*        (1023*(C + 1) - D)       */
+					/*	  (1023*(C + 1) - D)	   */
 
-#define RTSR_AL 	0x00000001	/* ALarm detected                  */
-#define RTSR_HZ 	0x00000002	/* 1 Hz clock detected             */
-#define RTSR_ALE	0x00000004	/* ALarm interrupt Enable          */
-#define RTSR_HZE	0x00000008	/* 1 Hz clock interrupt Enable     */
+#define RTSR_AL		0x00000001	/* ALarm detected		   */
+#define RTSR_HZ		0x00000002	/* 1 Hz clock detected		   */
+#define RTSR_ALE	0x00000004	/* ALarm interrupt Enable	   */
+#define RTSR_HZE	0x00000008	/* 1 Hz clock interrupt Enable	   */
 
 
 /*
  * Power Manager (PM) control registers
  *
  * Registers
- *    PMCR      	Power Manager (PM) Control Register (read/write).
- *    PSSR      	Power Manager (PM) Sleep Status Register (read/write).
- *    PSPR      	Power Manager (PM) Scratch-Pad Register (read/write).
- *    PWER      	Power Manager (PM) Wake-up Enable Register
- *              	(read/write).
- *    PCFR      	Power Manager (PM) general ConFiguration Register
- *              	(read/write).
- *    PPCR      	Power Manager (PM) Phase-Locked Loop (PLL)
- *              	Configuration Register (read/write).
- *    PGSR      	Power Manager (PM) General-Purpose Input/Output (GPIO)
- *              	Sleep state Register (read/write, see GPIO pins).
- *    POSR      	Power Manager (PM) Oscillator Status Register (read).
+ *    PMCR		Power Manager (PM) Control Register (read/write).
+ *    PSSR		Power Manager (PM) Sleep Status Register (read/write).
+ *    PSPR		Power Manager (PM) Scratch-Pad Register (read/write).
+ *    PWER		Power Manager (PM) Wake-up Enable Register
+ *			(read/write).
+ *    PCFR		Power Manager (PM) general ConFiguration Register
+ *			(read/write).
+ *    PPCR		Power Manager (PM) Phase-Locked Loop (PLL)
+ *			Configuration Register (read/write).
+ *    PGSR		Power Manager (PM) General-Purpose Input/Output (GPIO)
+ *			Sleep state Register (read/write, see GPIO pins).
+ *    POSR		Power Manager (PM) Oscillator Status Register (read).
  *
  * Clocks
  *    fxtl, Txtl	Frequency, period of the system crystal (3.6864 MHz
- *              	or 3.5795 MHz).
+ *			or 3.5795 MHz).
  *    fcpu, Tcpu	Frequency, period of the CPU core clock (CCLK).
  */
 
-#define _PMCR   	0x90020000	/* PM Control Reg.                 */
-#define _PSSR   	0x90020004	/* PM Sleep Status Reg.            */
-#define _PSPR   	0x90020008	/* PM Scratch-Pad Reg.             */
-#define _PWER   	0x9002000C	/* PM Wake-up Enable Reg.          */
-#define _PCFR   	0x90020010	/* PM general ConFiguration Reg.   */
-#define _PPCR   	0x90020014	/* PM PLL Configuration Reg.       */
-#define _PGSR   	0x90020018	/* PM GPIO Sleep state Reg.        */
-#define _POSR   	0x9002001C	/* PM Oscillator Status Reg.       */
+#define _PMCR		0x90020000	/* PM Control Reg.		   */
+#define _PSSR		0x90020004	/* PM Sleep Status Reg.		   */
+#define _PSPR		0x90020008	/* PM Scratch-Pad Reg.		   */
+#define _PWER		0x9002000C	/* PM Wake-up Enable Reg.	   */
+#define _PCFR		0x90020010	/* PM general ConFiguration Reg.   */
+#define _PPCR		0x90020014	/* PM PLL Configuration Reg.	   */
+#define _PGSR		0x90020018	/* PM GPIO Sleep state Reg.	   */
+#define _POSR		0x9002001C	/* PM Oscillator Status Reg.	   */
 
 #if LANGUAGE == C
-#define PMCR    	        	/* PM Control Reg.                 */ \
+#define PMCR				/* PM Control Reg.		   */ \
 			(*((volatile Word *) io_p2v (_PMCR)))
-#define PSSR    	        	/* PM Sleep Status Reg.            */ \
+#define PSSR				/* PM Sleep Status Reg.		   */ \
 			(*((volatile Word *) io_p2v (_PSSR)))
-#define PSPR    	        	/* PM Scratch-Pad Reg.             */ \
+#define PSPR				/* PM Scratch-Pad Reg.		   */ \
 			(*((volatile Word *) io_p2v (_PSPR)))
-#define PWER    	        	/* PM Wake-up Enable Reg.          */ \
+#define PWER				/* PM Wake-up Enable Reg.	   */ \
 			(*((volatile Word *) io_p2v (_PWER)))
-#define PCFR    	        	/* PM general ConFiguration Reg.   */ \
+#define PCFR				/* PM general ConFiguration Reg.   */ \
 			(*((volatile Word *) io_p2v (_PCFR)))
-#define PPCR    	        	/* PM PLL Configuration Reg.       */ \
+#define PPCR				/* PM PLL Configuration Reg.	   */ \
 			(*((volatile Word *) io_p2v (_PPCR)))
-#define PGSR    	        	/* PM GPIO Sleep state Reg.        */ \
+#define PGSR				/* PM GPIO Sleep state Reg.	   */ \
 			(*((volatile Word *) io_p2v (_PGSR)))
-#define POSR    	        	/* PM Oscillator Status Reg.       */ \
+#define POSR				/* PM Oscillator Status Reg.	   */ \
 			(*((volatile Word *) io_p2v (_POSR)))
 
 #elif LANGUAGE == Assembly
-#define PMCR          	(io_p2v (_PMCR))
-#define PSSR          	(io_p2v (_PSSR))
-#define PSPR          	(io_p2v (_PSPR))
-#define PWER          	(io_p2v (_PWER))
-#define PCFR          	(io_p2v (_PCFR))
-#define PPCR          	(io_p2v (_PPCR))
-#define PGSR          	(io_p2v (_PGSR))
-#define POSR          	(io_p2v (_POSR))
+#define PMCR		(io_p2v (_PMCR))
+#define PSSR		(io_p2v (_PSSR))
+#define PSPR		(io_p2v (_PSPR))
+#define PWER		(io_p2v (_PWER))
+#define PCFR		(io_p2v (_PCFR))
+#define PPCR		(io_p2v (_PPCR))
+#define PGSR		(io_p2v (_PGSR))
+#define POSR		(io_p2v (_POSR))
 
 #endif /* LANGUAGE == C */
 
-#define PMCR_SF 	0x00000001	/* Sleep Force (set only)          */
+#define PMCR_SF		0x00000001	/* Sleep Force (set only)	   */
 
-#define PSSR_SS 	0x00000001	/* Software Sleep                  */
-#define PSSR_BFS	0x00000002	/* Battery Fault Status            */
-					/* (BATT_FAULT)                    */
+#define PSSR_SS		0x00000001	/* Software Sleep		   */
+#define PSSR_BFS	0x00000002	/* Battery Fault Status		   */
+					/* (BATT_FAULT)			   */
 #define PSSR_VFS	0x00000004	/* Vdd Fault Status (VDD_FAULT)    */
-#define PSSR_DH 	0x00000008	/* DRAM control Hold               */
-#define PSSR_PH 	0x00000010	/* Peripheral control Hold         */
-
-#define PWER_GPIO(Nb)	GPIO_GPIO (Nb)	/* GPIO [0..27] wake-up enable     */
-#define PWER_GPIO0	PWER_GPIO (0)	/* GPIO  [0] wake-up enable        */
-#define PWER_GPIO1	PWER_GPIO (1)	/* GPIO  [1] wake-up enable        */
-#define PWER_GPIO2	PWER_GPIO (2)	/* GPIO  [2] wake-up enable        */
-#define PWER_GPIO3	PWER_GPIO (3)	/* GPIO  [3] wake-up enable        */
-#define PWER_GPIO4	PWER_GPIO (4)	/* GPIO  [4] wake-up enable        */
-#define PWER_GPIO5	PWER_GPIO (5)	/* GPIO  [5] wake-up enable        */
-#define PWER_GPIO6	PWER_GPIO (6)	/* GPIO  [6] wake-up enable        */
-#define PWER_GPIO7	PWER_GPIO (7)	/* GPIO  [7] wake-up enable        */
-#define PWER_GPIO8	PWER_GPIO (8)	/* GPIO  [8] wake-up enable        */
-#define PWER_GPIO9	PWER_GPIO (9)	/* GPIO  [9] wake-up enable        */
-#define PWER_GPIO10	PWER_GPIO (10)	/* GPIO [10] wake-up enable        */
-#define PWER_GPIO11	PWER_GPIO (11)	/* GPIO [11] wake-up enable        */
-#define PWER_GPIO12	PWER_GPIO (12)	/* GPIO [12] wake-up enable        */
-#define PWER_GPIO13	PWER_GPIO (13)	/* GPIO [13] wake-up enable        */
-#define PWER_GPIO14	PWER_GPIO (14)	/* GPIO [14] wake-up enable        */
-#define PWER_GPIO15	PWER_GPIO (15)	/* GPIO [15] wake-up enable        */
-#define PWER_GPIO16	PWER_GPIO (16)	/* GPIO [16] wake-up enable        */
-#define PWER_GPIO17	PWER_GPIO (17)	/* GPIO [17] wake-up enable        */
-#define PWER_GPIO18	PWER_GPIO (18)	/* GPIO [18] wake-up enable        */
-#define PWER_GPIO19	PWER_GPIO (19)	/* GPIO [19] wake-up enable        */
-#define PWER_GPIO20	PWER_GPIO (20)	/* GPIO [20] wake-up enable        */
-#define PWER_GPIO21	PWER_GPIO (21)	/* GPIO [21] wake-up enable        */
-#define PWER_GPIO22	PWER_GPIO (22)	/* GPIO [22] wake-up enable        */
-#define PWER_GPIO23	PWER_GPIO (23)	/* GPIO [23] wake-up enable        */
-#define PWER_GPIO24	PWER_GPIO (24)	/* GPIO [24] wake-up enable        */
-#define PWER_GPIO25	PWER_GPIO (25)	/* GPIO [25] wake-up enable        */
-#define PWER_GPIO26	PWER_GPIO (26)	/* GPIO [26] wake-up enable        */
-#define PWER_GPIO27	PWER_GPIO (27)	/* GPIO [27] wake-up enable        */
-#define PWER_RTC	0x80000000	/* RTC alarm wake-up enable        */
+#define PSSR_DH		0x00000008	/* DRAM control Hold		   */
+#define PSSR_PH		0x00000010	/* Peripheral control Hold	   */
+
+#define PWER_GPIO(Nb)	GPIO_GPIO (Nb)	/* GPIO [0..27] wake-up enable	   */
+#define PWER_GPIO0	PWER_GPIO (0)	/* GPIO  [0] wake-up enable	   */
+#define PWER_GPIO1	PWER_GPIO (1)	/* GPIO  [1] wake-up enable	   */
+#define PWER_GPIO2	PWER_GPIO (2)	/* GPIO  [2] wake-up enable	   */
+#define PWER_GPIO3	PWER_GPIO (3)	/* GPIO  [3] wake-up enable	   */
+#define PWER_GPIO4	PWER_GPIO (4)	/* GPIO  [4] wake-up enable	   */
+#define PWER_GPIO5	PWER_GPIO (5)	/* GPIO  [5] wake-up enable	   */
+#define PWER_GPIO6	PWER_GPIO (6)	/* GPIO  [6] wake-up enable	   */
+#define PWER_GPIO7	PWER_GPIO (7)	/* GPIO  [7] wake-up enable	   */
+#define PWER_GPIO8	PWER_GPIO (8)	/* GPIO  [8] wake-up enable	   */
+#define PWER_GPIO9	PWER_GPIO (9)	/* GPIO  [9] wake-up enable	   */
+#define PWER_GPIO10	PWER_GPIO (10)	/* GPIO [10] wake-up enable	   */
+#define PWER_GPIO11	PWER_GPIO (11)	/* GPIO [11] wake-up enable	   */
+#define PWER_GPIO12	PWER_GPIO (12)	/* GPIO [12] wake-up enable	   */
+#define PWER_GPIO13	PWER_GPIO (13)	/* GPIO [13] wake-up enable	   */
+#define PWER_GPIO14	PWER_GPIO (14)	/* GPIO [14] wake-up enable	   */
+#define PWER_GPIO15	PWER_GPIO (15)	/* GPIO [15] wake-up enable	   */
+#define PWER_GPIO16	PWER_GPIO (16)	/* GPIO [16] wake-up enable	   */
+#define PWER_GPIO17	PWER_GPIO (17)	/* GPIO [17] wake-up enable	   */
+#define PWER_GPIO18	PWER_GPIO (18)	/* GPIO [18] wake-up enable	   */
+#define PWER_GPIO19	PWER_GPIO (19)	/* GPIO [19] wake-up enable	   */
+#define PWER_GPIO20	PWER_GPIO (20)	/* GPIO [20] wake-up enable	   */
+#define PWER_GPIO21	PWER_GPIO (21)	/* GPIO [21] wake-up enable	   */
+#define PWER_GPIO22	PWER_GPIO (22)	/* GPIO [22] wake-up enable	   */
+#define PWER_GPIO23	PWER_GPIO (23)	/* GPIO [23] wake-up enable	   */
+#define PWER_GPIO24	PWER_GPIO (24)	/* GPIO [24] wake-up enable	   */
+#define PWER_GPIO25	PWER_GPIO (25)	/* GPIO [25] wake-up enable	   */
+#define PWER_GPIO26	PWER_GPIO (26)	/* GPIO [26] wake-up enable	   */
+#define PWER_GPIO27	PWER_GPIO (27)	/* GPIO [27] wake-up enable	   */
+#define PWER_RTC	0x80000000	/* RTC alarm wake-up enable	   */
 
 #define PCFR_OPDE	0x00000001	/* Oscillator Power-Down Enable    */
 #define PCFR_ClkRun	(PCFR_OPDE*0)	/*  Clock Running in sleep mode    */
 #define PCFR_ClkStp	(PCFR_OPDE*1)	/*  Clock Stopped in sleep mode    */
-#define PCFR_FP 	0x00000002	/* Float PCMCIA pins               */
-#define PCFR_PCMCIANeg	(PCFR_FP*0)	/*  PCMCIA pins Negated (1)        */
-#define PCFR_PCMCIAFlt	(PCFR_FP*1)	/*  PCMCIA pins Floating           */
-#define PCFR_FS 	0x00000004	/* Float Static memory pins        */
+#define PCFR_FP		0x00000002	/* Float PCMCIA pins		   */
+#define PCFR_PCMCIANeg	(PCFR_FP*0)	/*  PCMCIA pins Negated (1)	   */
+#define PCFR_PCMCIAFlt	(PCFR_FP*1)	/*  PCMCIA pins Floating	   */
+#define PCFR_FS		0x00000004	/* Float Static memory pins	   */
 #define PCFR_StMemNeg	(PCFR_FS*0)	/*  Static Memory pins Negated (1) */
 #define PCFR_StMemFlt	(PCFR_FS*1)	/*  Static Memory pins Floating    */
-#define PCFR_FO 	0x00000008	/* Force RTC oscillator            */
-					/* (32.768 kHz) enable On          */
+#define PCFR_FO		0x00000008	/* Force RTC oscillator		   */
+					/* (32.768 kHz) enable On	   */
 
-#define PPCR_CCF	Fld (5, 0)	/* CPU core Clock (CCLK) Freq.     */
-#define PPCR_Fx16	        	/*  Freq. x 16 (fcpu = 16*fxtl)    */ \
+#define PPCR_CCF	Fld (5, 0)	/* CPU core Clock (CCLK) Freq.	   */
+#define PPCR_Fx16			/*  Freq. x 16 (fcpu = 16*fxtl)    */ \
 			(0x00 << FShft (PPCR_CCF))
-#define PPCR_Fx20	        	/*  Freq. x 20 (fcpu = 20*fxtl)    */ \
+#define PPCR_Fx20			/*  Freq. x 20 (fcpu = 20*fxtl)    */ \
 			(0x01 << FShft (PPCR_CCF))
-#define PPCR_Fx24	        	/*  Freq. x 24 (fcpu = 24*fxtl)    */ \
+#define PPCR_Fx24			/*  Freq. x 24 (fcpu = 24*fxtl)    */ \
 			(0x02 << FShft (PPCR_CCF))
-#define PPCR_Fx28	        	/*  Freq. x 28 (fcpu = 28*fxtl)    */ \
+#define PPCR_Fx28			/*  Freq. x 28 (fcpu = 28*fxtl)    */ \
 			(0x03 << FShft (PPCR_CCF))
-#define PPCR_Fx32	        	/*  Freq. x 32 (fcpu = 32*fxtl)    */ \
+#define PPCR_Fx32			/*  Freq. x 32 (fcpu = 32*fxtl)    */ \
 			(0x04 << FShft (PPCR_CCF))
-#define PPCR_Fx36	        	/*  Freq. x 36 (fcpu = 36*fxtl)    */ \
+#define PPCR_Fx36			/*  Freq. x 36 (fcpu = 36*fxtl)    */ \
 			(0x05 << FShft (PPCR_CCF))
-#define PPCR_Fx40	        	/*  Freq. x 40 (fcpu = 40*fxtl)    */ \
+#define PPCR_Fx40			/*  Freq. x 40 (fcpu = 40*fxtl)    */ \
 			(0x06 << FShft (PPCR_CCF))
-#define PPCR_Fx44	        	/*  Freq. x 44 (fcpu = 44*fxtl)    */ \
+#define PPCR_Fx44			/*  Freq. x 44 (fcpu = 44*fxtl)    */ \
 			(0x07 << FShft (PPCR_CCF))
-#define PPCR_Fx48	        	/*  Freq. x 48 (fcpu = 48*fxtl)    */ \
+#define PPCR_Fx48			/*  Freq. x 48 (fcpu = 48*fxtl)    */ \
 			(0x08 << FShft (PPCR_CCF))
-#define PPCR_Fx52	        	/*  Freq. x 52 (fcpu = 52*fxtl)    */ \
+#define PPCR_Fx52			/*  Freq. x 52 (fcpu = 52*fxtl)    */ \
 			(0x09 << FShft (PPCR_CCF))
-#define PPCR_Fx56	        	/*  Freq. x 56 (fcpu = 56*fxtl)    */ \
+#define PPCR_Fx56			/*  Freq. x 56 (fcpu = 56*fxtl)    */ \
 			(0x0A << FShft (PPCR_CCF))
-#define PPCR_Fx60	        	/*  Freq. x 60 (fcpu = 60*fxtl)    */ \
+#define PPCR_Fx60			/*  Freq. x 60 (fcpu = 60*fxtl)    */ \
 			(0x0B << FShft (PPCR_CCF))
-#define PPCR_Fx64	        	/*  Freq. x 64 (fcpu = 64*fxtl)    */ \
+#define PPCR_Fx64			/*  Freq. x 64 (fcpu = 64*fxtl)    */ \
 			(0x0C << FShft (PPCR_CCF))
-#define PPCR_Fx68	        	/*  Freq. x 68 (fcpu = 68*fxtl)    */ \
+#define PPCR_Fx68			/*  Freq. x 68 (fcpu = 68*fxtl)    */ \
 			(0x0D << FShft (PPCR_CCF))
-#define PPCR_Fx72	        	/*  Freq. x 72 (fcpu = 72*fxtl)    */ \
+#define PPCR_Fx72			/*  Freq. x 72 (fcpu = 72*fxtl)    */ \
 			(0x0E << FShft (PPCR_CCF))
-#define PPCR_Fx76	        	/*  Freq. x 76 (fcpu = 76*fxtl)    */ \
+#define PPCR_Fx76			/*  Freq. x 76 (fcpu = 76*fxtl)    */ \
 			(0x0F << FShft (PPCR_CCF))
-					/*  3.6864 MHz crystal (fxtl):     */
-#define PPCR_F59_0MHz	PPCR_Fx16	/*   Freq. (fcpu) =  59.0 MHz      */
-#define PPCR_F73_7MHz	PPCR_Fx20	/*   Freq. (fcpu) =  73.7 MHz      */
-#define PPCR_F88_5MHz	PPCR_Fx24	/*   Freq. (fcpu) =  88.5 MHz      */
-#define PPCR_F103_2MHz	PPCR_Fx28	/*   Freq. (fcpu) = 103.2 MHz      */
-#define PPCR_F118_0MHz	PPCR_Fx32	/*   Freq. (fcpu) = 118.0 MHz      */
-#define PPCR_F132_7MHz	PPCR_Fx36	/*   Freq. (fcpu) = 132.7 MHz      */
-#define PPCR_F147_5MHz	PPCR_Fx40	/*   Freq. (fcpu) = 147.5 MHz      */
-#define PPCR_F162_2MHz	PPCR_Fx44	/*   Freq. (fcpu) = 162.2 MHz      */
-#define PPCR_F176_9MHz	PPCR_Fx48	/*   Freq. (fcpu) = 176.9 MHz      */
-#define PPCR_F191_7MHz	PPCR_Fx52	/*   Freq. (fcpu) = 191.7 MHz      */
-#define PPCR_F206_4MHz	PPCR_Fx56	/*   Freq. (fcpu) = 206.4 MHz      */
-#define PPCR_F221_2MHz	PPCR_Fx60	/*   Freq. (fcpu) = 221.2 MHz      */
-#define PPCR_F239_6MHz	PPCR_Fx64	/*   Freq. (fcpu) = 239.6 MHz      */
-#define PPCR_F250_7MHz	PPCR_Fx68	/*   Freq. (fcpu) = 250.7 MHz      */
-#define PPCR_F265_4MHz	PPCR_Fx72	/*   Freq. (fcpu) = 265.4 MHz      */
-#define PPCR_F280_2MHz	PPCR_Fx76	/*   Freq. (fcpu) = 280.2 MHz      */
-					/*  3.5795 MHz crystal (fxtl):     */
-#define PPCR_F57_3MHz	PPCR_Fx16	/*   Freq. (fcpu) =  57.3 MHz      */
-#define PPCR_F71_6MHz	PPCR_Fx20	/*   Freq. (fcpu) =  71.6 MHz      */
-#define PPCR_F85_9MHz	PPCR_Fx24	/*   Freq. (fcpu) =  85.9 MHz      */
-#define PPCR_F100_2MHz	PPCR_Fx28	/*   Freq. (fcpu) = 100.2 MHz      */
-#define PPCR_F114_5MHz	PPCR_Fx32	/*   Freq. (fcpu) = 114.5 MHz      */
-#define PPCR_F128_9MHz	PPCR_Fx36	/*   Freq. (fcpu) = 128.9 MHz      */
-#define PPCR_F143_2MHz	PPCR_Fx40	/*   Freq. (fcpu) = 143.2 MHz      */
-#define PPCR_F157_5MHz	PPCR_Fx44	/*   Freq. (fcpu) = 157.5 MHz      */
-#define PPCR_F171_8MHz	PPCR_Fx48	/*   Freq. (fcpu) = 171.8 MHz      */
-#define PPCR_F186_1MHz	PPCR_Fx52	/*   Freq. (fcpu) = 186.1 MHz      */
-#define PPCR_F200_5MHz	PPCR_Fx56	/*   Freq. (fcpu) = 200.5 MHz      */
-#define PPCR_F214_8MHz	PPCR_Fx60	/*   Freq. (fcpu) = 214.8 MHz      */
-#define PPCR_F229_1MHz	PPCR_Fx64	/*   Freq. (fcpu) = 229.1 MHz      */
-#define PPCR_F243_4MHz	PPCR_Fx68	/*   Freq. (fcpu) = 243.4 MHz      */
-#define PPCR_F257_7MHz	PPCR_Fx72	/*   Freq. (fcpu) = 257.7 MHz      */
-#define PPCR_F272_0MHz	PPCR_Fx76	/*   Freq. (fcpu) = 272.0 MHz      */
+					/*  3.6864 MHz crystal (fxtl):	   */
+#define PPCR_F59_0MHz	PPCR_Fx16	/*   Freq. (fcpu) =  59.0 MHz	   */
+#define PPCR_F73_7MHz	PPCR_Fx20	/*   Freq. (fcpu) =  73.7 MHz	   */
+#define PPCR_F88_5MHz	PPCR_Fx24	/*   Freq. (fcpu) =  88.5 MHz	   */
+#define PPCR_F103_2MHz	PPCR_Fx28	/*   Freq. (fcpu) = 103.2 MHz	   */
+#define PPCR_F118_0MHz	PPCR_Fx32	/*   Freq. (fcpu) = 118.0 MHz	   */
+#define PPCR_F132_7MHz	PPCR_Fx36	/*   Freq. (fcpu) = 132.7 MHz	   */
+#define PPCR_F147_5MHz	PPCR_Fx40	/*   Freq. (fcpu) = 147.5 MHz	   */
+#define PPCR_F162_2MHz	PPCR_Fx44	/*   Freq. (fcpu) = 162.2 MHz	   */
+#define PPCR_F176_9MHz	PPCR_Fx48	/*   Freq. (fcpu) = 176.9 MHz	   */
+#define PPCR_F191_7MHz	PPCR_Fx52	/*   Freq. (fcpu) = 191.7 MHz	   */
+#define PPCR_F206_4MHz	PPCR_Fx56	/*   Freq. (fcpu) = 206.4 MHz	   */
+#define PPCR_F221_2MHz	PPCR_Fx60	/*   Freq. (fcpu) = 221.2 MHz	   */
+#define PPCR_F239_6MHz	PPCR_Fx64	/*   Freq. (fcpu) = 239.6 MHz	   */
+#define PPCR_F250_7MHz	PPCR_Fx68	/*   Freq. (fcpu) = 250.7 MHz	   */
+#define PPCR_F265_4MHz	PPCR_Fx72	/*   Freq. (fcpu) = 265.4 MHz	   */
+#define PPCR_F280_2MHz	PPCR_Fx76	/*   Freq. (fcpu) = 280.2 MHz	   */
+					/*  3.5795 MHz crystal (fxtl):	   */
+#define PPCR_F57_3MHz	PPCR_Fx16	/*   Freq. (fcpu) =  57.3 MHz	   */
+#define PPCR_F71_6MHz	PPCR_Fx20	/*   Freq. (fcpu) =  71.6 MHz	   */
+#define PPCR_F85_9MHz	PPCR_Fx24	/*   Freq. (fcpu) =  85.9 MHz	   */
+#define PPCR_F100_2MHz	PPCR_Fx28	/*   Freq. (fcpu) = 100.2 MHz	   */
+#define PPCR_F114_5MHz	PPCR_Fx32	/*   Freq. (fcpu) = 114.5 MHz	   */
+#define PPCR_F128_9MHz	PPCR_Fx36	/*   Freq. (fcpu) = 128.9 MHz	   */
+#define PPCR_F143_2MHz	PPCR_Fx40	/*   Freq. (fcpu) = 143.2 MHz	   */
+#define PPCR_F157_5MHz	PPCR_Fx44	/*   Freq. (fcpu) = 157.5 MHz	   */
+#define PPCR_F171_8MHz	PPCR_Fx48	/*   Freq. (fcpu) = 171.8 MHz	   */
+#define PPCR_F186_1MHz	PPCR_Fx52	/*   Freq. (fcpu) = 186.1 MHz	   */
+#define PPCR_F200_5MHz	PPCR_Fx56	/*   Freq. (fcpu) = 200.5 MHz	   */
+#define PPCR_F214_8MHz	PPCR_Fx60	/*   Freq. (fcpu) = 214.8 MHz	   */
+#define PPCR_F229_1MHz	PPCR_Fx64	/*   Freq. (fcpu) = 229.1 MHz	   */
+#define PPCR_F243_4MHz	PPCR_Fx68	/*   Freq. (fcpu) = 243.4 MHz	   */
+#define PPCR_F257_7MHz	PPCR_Fx72	/*   Freq. (fcpu) = 257.7 MHz	   */
+#define PPCR_F272_0MHz	PPCR_Fx76	/*   Freq. (fcpu) = 272.0 MHz	   */
 
 #define POSR_OOK	0x00000001	/* RTC Oscillator (32.768 kHz) OK  */
 
@@ -1391,75 +1391,75 @@ typedef PCMCIAPrtType	PCMCIAType [PCMCIASp/PCMCIAPrtSp] ;
  * Reset Controller (RC) control registers
  *
  * Registers
- *    RSRR      	Reset Controller (RC) Software Reset Register
- *              	(read/write).
- *    RCSR      	Reset Controller (RC) Status Register (read/write).
+ *    RSRR		Reset Controller (RC) Software Reset Register
+ *			(read/write).
+ *    RCSR		Reset Controller (RC) Status Register (read/write).
  */
 
-#define _RSRR   	0x90030000	/* RC Software Reset Reg.          */
-#define _RCSR   	0x90030004	/* RC Status Reg.                  */
+#define _RSRR		0x90030000	/* RC Software Reset Reg.	   */
+#define _RCSR		0x90030004	/* RC Status Reg.		   */
 
 #if LANGUAGE == C
-#define RSRR    	        	/* RC Software Reset Reg.          */ \
+#define RSRR				/* RC Software Reset Reg.	   */ \
 			(*((volatile Word *) io_p2v (_RSRR)))
-#define RCSR    	        	/* RC Status Reg.                  */ \
+#define RCSR				/* RC Status Reg.		   */ \
 			(*((volatile Word *) io_p2v (_RCSR)))
 #endif /* LANGUAGE == C */
 
-#define RSRR_SWR	0x00000001	/* SoftWare Reset (set only)       */
+#define RSRR_SWR	0x00000001	/* SoftWare Reset (set only)	   */
 
-#define RCSR_HWR	0x00000001	/* HardWare Reset                  */
-#define RCSR_SWR	0x00000002	/* SoftWare Reset                  */
-#define RCSR_WDR	0x00000004	/* Watch-Dog Reset                 */
-#define RCSR_SMR	0x00000008	/* Sleep-Mode Reset                */
+#define RCSR_HWR	0x00000001	/* HardWare Reset		   */
+#define RCSR_SWR	0x00000002	/* SoftWare Reset		   */
+#define RCSR_WDR	0x00000004	/* Watch-Dog Reset		   */
+#define RCSR_SMR	0x00000008	/* Sleep-Mode Reset		   */
 
 
 /*
  * Test unit control registers
  *
  * Registers
- *    TUCR      	Test Unit Control Register (read/write).
+ *    TUCR		Test Unit Control Register (read/write).
  */
 
-#define _TUCR   	0x90030008	/* Test Unit Control Reg.          */
+#define _TUCR		0x90030008	/* Test Unit Control Reg.	   */
 
 #if LANGUAGE == C
-#define TUCR    	        	/* Test Unit Control Reg.          */ \
+#define TUCR				/* Test Unit Control Reg.	   */ \
 			(*((volatile Word *) io_p2v (_TUCR)))
 #endif /* LANGUAGE == C */
 
-#define TUCR_TIC	0x00000040	/* TIC mode                        */
-#define TUCR_TTST	0x00000080	/* Trim TeST mode                  */
-#define TUCR_RCRC	0x00000100	/* Richard's Cyclic Redundancy     */
-					/* Check                           */
-#define TUCR_PMD	0x00000200	/* Power Management Disable        */
-#define TUCR_MR 	0x00000400	/* Memory Request mode             */
+#define TUCR_TIC	0x00000040	/* TIC mode			   */
+#define TUCR_TTST	0x00000080	/* Trim TeST mode		   */
+#define TUCR_RCRC	0x00000100	/* Richard's Cyclic Redundancy	   */
+					/* Check			   */
+#define TUCR_PMD	0x00000200	/* Power Management Disable	   */
+#define TUCR_MR		0x00000400	/* Memory Request mode		   */
 #define TUCR_NoMB	(TUCR_MR*0)	/*  No Memory Bus request & grant  */
 #define TUCR_MBGPIO	(TUCR_MR*1)	/*  Memory Bus request (MBREQ) &   */
 					/*  grant (MBGNT) on GPIO [22:21]  */
-#define TUCR_CTB	Fld (3, 20)	/* Clock Test Bits                 */
-#define TUCR_FDC	0x00800000	/* RTC Force Delete Count          */
+#define TUCR_CTB	Fld (3, 20)	/* Clock Test Bits		   */
+#define TUCR_FDC	0x00800000	/* RTC Force Delete Count	   */
 #define TUCR_FMC	0x01000000	/* Force Michelle's Control mode   */
 #define TUCR_TMC	0x02000000	/* RTC Trimmer Multiplexer Control */
-#define TUCR_DPS	0x04000000	/* Disallow Pad Sleep              */
+#define TUCR_DPS	0x04000000	/* Disallow Pad Sleep		   */
 #define TUCR_TSEL	Fld (3, 29)	/* clock Test SELect on GPIO [27]  */
-#define TUCR_32_768kHz	        	/*  32.768 kHz osc. on GPIO [27]   */ \
+#define TUCR_32_768kHz			/*  32.768 kHz osc. on GPIO [27]   */ \
 			(0 << FShft (TUCR_TSEL))
-#define TUCR_3_6864MHz	        	/*  3.6864 MHz osc. on GPIO [27]   */ \
+#define TUCR_3_6864MHz			/*  3.6864 MHz osc. on GPIO [27]   */ \
 			(1 << FShft (TUCR_TSEL))
-#define TUCR_VDD	        	/*  VDD ring osc./16 on GPIO [27]  */ \
+#define TUCR_VDD			/*  VDD ring osc./16 on GPIO [27]  */ \
 			(2 << FShft (TUCR_TSEL))
-#define TUCR_96MHzPLL	        	/*  96 MHz PLL/4 on GPIO [27]      */ \
+#define TUCR_96MHzPLL			/*  96 MHz PLL/4 on GPIO [27]	   */ \
 			(3 << FShft (TUCR_TSEL))
-#define TUCR_Clock	        	/*  internal (fcpu/2) & 32.768 kHz */ \
-					/*  Clocks on GPIO [26:27]         */ \
+#define TUCR_Clock			/*  internal (fcpu/2) & 32.768 kHz */ \
+					/*  Clocks on GPIO [26:27]	   */ \
 			(4 << FShft (TUCR_TSEL))
-#define TUCR_3_6864MHzA	        	/*  3.6864 MHz osc. on GPIO [27]   */ \
-					/*  (Alternative)                  */ \
+#define TUCR_3_6864MHzA			/*  3.6864 MHz osc. on GPIO [27]   */ \
+					/*  (Alternative)		   */ \
 			(5 << FShft (TUCR_TSEL))
-#define TUCR_MainPLL	        	/*  Main PLL/16 on GPIO [27]       */ \
+#define TUCR_MainPLL			/*  Main PLL/16 on GPIO [27]	   */ \
 			(6 << FShft (TUCR_TSEL))
-#define TUCR_VDDL	        	/*  VDDL ring osc./4 on GPIO [27]  */ \
+#define TUCR_VDDL			/*  VDDL ring osc./4 on GPIO [27]  */ \
 			(7 << FShft (TUCR_TSEL))
 
 
@@ -1467,52 +1467,52 @@ typedef PCMCIAPrtType	PCMCIAType [PCMCIASp/PCMCIAPrtSp] ;
  * General-Purpose Input/Output (GPIO) control registers
  *
  * Registers
- *    GPLR      	General-Purpose Input/Output (GPIO) Pin Level
- *              	Register (read).
- *    GPDR      	General-Purpose Input/Output (GPIO) Pin Direction
- *              	Register (read/write).
- *    GPSR      	General-Purpose Input/Output (GPIO) Pin output Set
- *              	Register (write).
- *    GPCR      	General-Purpose Input/Output (GPIO) Pin output Clear
- *              	Register (write).
- *    GRER      	General-Purpose Input/Output (GPIO) Rising-Edge
- *              	detect Register (read/write).
- *    GFER      	General-Purpose Input/Output (GPIO) Falling-Edge
- *              	detect Register (read/write).
- *    GEDR      	General-Purpose Input/Output (GPIO) Edge Detect
- *              	status Register (read/write).
- *    GAFR      	General-Purpose Input/Output (GPIO) Alternate
- *              	Function Register (read/write).
+ *    GPLR		General-Purpose Input/Output (GPIO) Pin Level
+ *			Register (read).
+ *    GPDR		General-Purpose Input/Output (GPIO) Pin Direction
+ *			Register (read/write).
+ *    GPSR		General-Purpose Input/Output (GPIO) Pin output Set
+ *			Register (write).
+ *    GPCR		General-Purpose Input/Output (GPIO) Pin output Clear
+ *			Register (write).
+ *    GRER		General-Purpose Input/Output (GPIO) Rising-Edge
+ *			detect Register (read/write).
+ *    GFER		General-Purpose Input/Output (GPIO) Falling-Edge
+ *			detect Register (read/write).
+ *    GEDR		General-Purpose Input/Output (GPIO) Edge Detect
+ *			status Register (read/write).
+ *    GAFR		General-Purpose Input/Output (GPIO) Alternate
+ *			Function Register (read/write).
  *
  * Clock
  *    fcpu, Tcpu	Frequency, period of the CPU core clock (CCLK).
  */
 
-#define _GPLR   	0x90040000	/* GPIO Pin Level Reg.             */
-#define _GPDR   	0x90040004	/* GPIO Pin Direction Reg.         */
-#define _GPSR   	0x90040008	/* GPIO Pin output Set Reg.        */
-#define _GPCR   	0x9004000C	/* GPIO Pin output Clear Reg.      */
-#define _GRER   	0x90040010	/* GPIO Rising-Edge detect Reg.    */
-#define _GFER   	0x90040014	/* GPIO Falling-Edge detect Reg.   */
-#define _GEDR   	0x90040018	/* GPIO Edge Detect status Reg.    */
-#define _GAFR   	0x9004001C	/* GPIO Alternate Function Reg.    */
+#define _GPLR		0x90040000	/* GPIO Pin Level Reg.		   */
+#define _GPDR		0x90040004	/* GPIO Pin Direction Reg.	   */
+#define _GPSR		0x90040008	/* GPIO Pin output Set Reg.	   */
+#define _GPCR		0x9004000C	/* GPIO Pin output Clear Reg.	   */
+#define _GRER		0x90040010	/* GPIO Rising-Edge detect Reg.    */
+#define _GFER		0x90040014	/* GPIO Falling-Edge detect Reg.   */
+#define _GEDR		0x90040018	/* GPIO Edge Detect status Reg.    */
+#define _GAFR		0x9004001C	/* GPIO Alternate Function Reg.    */
 
 #if LANGUAGE == C
-#define GPLR    	        	/* GPIO Pin Level Reg.             */ \
+#define GPLR				/* GPIO Pin Level Reg.		   */ \
 			(*((volatile Word *) io_p2v (_GPLR)))
-#define GPDR    	        	/* GPIO Pin Direction Reg.         */ \
+#define GPDR				/* GPIO Pin Direction Reg.	   */ \
 			(*((volatile Word *) io_p2v (_GPDR)))
-#define GPSR    	        	/* GPIO Pin output Set Reg.        */ \
+#define GPSR				/* GPIO Pin output Set Reg.	   */ \
 			(*((volatile Word *) io_p2v (_GPSR)))
-#define GPCR    	        	/* GPIO Pin output Clear Reg.      */ \
+#define GPCR				/* GPIO Pin output Clear Reg.	   */ \
 			(*((volatile Word *) io_p2v (_GPCR)))
-#define GRER    	        	/* GPIO Rising-Edge detect Reg.    */ \
+#define GRER				/* GPIO Rising-Edge detect Reg.    */ \
 			(*((volatile Word *) io_p2v (_GRER)))
-#define GFER    	        	/* GPIO Falling-Edge detect Reg.   */ \
+#define GFER				/* GPIO Falling-Edge detect Reg.   */ \
 			(*((volatile Word *) io_p2v (_GFER)))
-#define GEDR    	        	/* GPIO Edge Detect status Reg.    */ \
+#define GEDR				/* GPIO Edge Detect status Reg.    */ \
 			(*((volatile Word *) io_p2v (_GEDR)))
-#define GAFR    	        	/* GPIO Alternate Function Reg.    */ \
+#define GAFR				/* GPIO Alternate Function Reg.    */ \
 			(*((volatile Word *) io_p2v (_GAFR)))
 #elif LANGUAGE == Assembly
 
@@ -1530,280 +1530,280 @@ typedef PCMCIAPrtType	PCMCIAType [PCMCIASp/PCMCIAPrtSp] ;
 #define GPIO_MIN	(0)
 #define GPIO_MAX	(27)
 
-#define GPIO_GPIO(Nb)	        	/* GPIO [0..27]                    */ \
+#define GPIO_GPIO(Nb)			/* GPIO [0..27]			   */ \
 			(0x00000001 << (Nb))
-#define GPIO_GPIO0	GPIO_GPIO (0)	/* GPIO  [0]                       */
-#define GPIO_GPIO1	GPIO_GPIO (1)	/* GPIO  [1]                       */
-#define GPIO_GPIO2	GPIO_GPIO (2)	/* GPIO  [2]                       */
-#define GPIO_GPIO3	GPIO_GPIO (3)	/* GPIO  [3]                       */
-#define GPIO_GPIO4	GPIO_GPIO (4)	/* GPIO  [4]                       */
-#define GPIO_GPIO5	GPIO_GPIO (5)	/* GPIO  [5]                       */
-#define GPIO_GPIO6	GPIO_GPIO (6)	/* GPIO  [6]                       */
-#define GPIO_GPIO7	GPIO_GPIO (7)	/* GPIO  [7]                       */
-#define GPIO_GPIO8	GPIO_GPIO (8)	/* GPIO  [8]                       */
-#define GPIO_GPIO9	GPIO_GPIO (9)	/* GPIO  [9]                       */
-#define GPIO_GPIO10	GPIO_GPIO (10)	/* GPIO [10]                       */
-#define GPIO_GPIO11	GPIO_GPIO (11)	/* GPIO [11]                       */
-#define GPIO_GPIO12	GPIO_GPIO (12)	/* GPIO [12]                       */
-#define GPIO_GPIO13	GPIO_GPIO (13)	/* GPIO [13]                       */
-#define GPIO_GPIO14	GPIO_GPIO (14)	/* GPIO [14]                       */
-#define GPIO_GPIO15	GPIO_GPIO (15)	/* GPIO [15]                       */
-#define GPIO_GPIO16	GPIO_GPIO (16)	/* GPIO [16]                       */
-#define GPIO_GPIO17	GPIO_GPIO (17)	/* GPIO [17]                       */
-#define GPIO_GPIO18	GPIO_GPIO (18)	/* GPIO [18]                       */
-#define GPIO_GPIO19	GPIO_GPIO (19)	/* GPIO [19]                       */
-#define GPIO_GPIO20	GPIO_GPIO (20)	/* GPIO [20]                       */
-#define GPIO_GPIO21	GPIO_GPIO (21)	/* GPIO [21]                       */
-#define GPIO_GPIO22	GPIO_GPIO (22)	/* GPIO [22]                       */
-#define GPIO_GPIO23	GPIO_GPIO (23)	/* GPIO [23]                       */
-#define GPIO_GPIO24	GPIO_GPIO (24)	/* GPIO [24]                       */
-#define GPIO_GPIO25	GPIO_GPIO (25)	/* GPIO [25]                       */
-#define GPIO_GPIO26	GPIO_GPIO (26)	/* GPIO [26]                       */
-#define GPIO_GPIO27	GPIO_GPIO (27)	/* GPIO [27]                       */
-
-#define GPIO_LDD(Nb)	        	/* LCD Data [8..15] (O)            */ \
+#define GPIO_GPIO0	GPIO_GPIO (0)	/* GPIO  [0]			   */
+#define GPIO_GPIO1	GPIO_GPIO (1)	/* GPIO  [1]			   */
+#define GPIO_GPIO2	GPIO_GPIO (2)	/* GPIO  [2]			   */
+#define GPIO_GPIO3	GPIO_GPIO (3)	/* GPIO  [3]			   */
+#define GPIO_GPIO4	GPIO_GPIO (4)	/* GPIO  [4]			   */
+#define GPIO_GPIO5	GPIO_GPIO (5)	/* GPIO  [5]			   */
+#define GPIO_GPIO6	GPIO_GPIO (6)	/* GPIO  [6]			   */
+#define GPIO_GPIO7	GPIO_GPIO (7)	/* GPIO  [7]			   */
+#define GPIO_GPIO8	GPIO_GPIO (8)	/* GPIO  [8]			   */
+#define GPIO_GPIO9	GPIO_GPIO (9)	/* GPIO  [9]			   */
+#define GPIO_GPIO10	GPIO_GPIO (10)	/* GPIO [10]			   */
+#define GPIO_GPIO11	GPIO_GPIO (11)	/* GPIO [11]			   */
+#define GPIO_GPIO12	GPIO_GPIO (12)	/* GPIO [12]			   */
+#define GPIO_GPIO13	GPIO_GPIO (13)	/* GPIO [13]			   */
+#define GPIO_GPIO14	GPIO_GPIO (14)	/* GPIO [14]			   */
+#define GPIO_GPIO15	GPIO_GPIO (15)	/* GPIO [15]			   */
+#define GPIO_GPIO16	GPIO_GPIO (16)	/* GPIO [16]			   */
+#define GPIO_GPIO17	GPIO_GPIO (17)	/* GPIO [17]			   */
+#define GPIO_GPIO18	GPIO_GPIO (18)	/* GPIO [18]			   */
+#define GPIO_GPIO19	GPIO_GPIO (19)	/* GPIO [19]			   */
+#define GPIO_GPIO20	GPIO_GPIO (20)	/* GPIO [20]			   */
+#define GPIO_GPIO21	GPIO_GPIO (21)	/* GPIO [21]			   */
+#define GPIO_GPIO22	GPIO_GPIO (22)	/* GPIO [22]			   */
+#define GPIO_GPIO23	GPIO_GPIO (23)	/* GPIO [23]			   */
+#define GPIO_GPIO24	GPIO_GPIO (24)	/* GPIO [24]			   */
+#define GPIO_GPIO25	GPIO_GPIO (25)	/* GPIO [25]			   */
+#define GPIO_GPIO26	GPIO_GPIO (26)	/* GPIO [26]			   */
+#define GPIO_GPIO27	GPIO_GPIO (27)	/* GPIO [27]			   */
+
+#define GPIO_LDD(Nb)			/* LCD Data [8..15] (O)		   */ \
 			GPIO_GPIO ((Nb) - 6)
-#define GPIO_LDD8	GPIO_LDD (8)	/* LCD Data  [8] (O)               */
-#define GPIO_LDD9	GPIO_LDD (9)	/* LCD Data  [9] (O)               */
-#define GPIO_LDD10	GPIO_LDD (10)	/* LCD Data [10] (O)               */
-#define GPIO_LDD11	GPIO_LDD (11)	/* LCD Data [11] (O)               */
-#define GPIO_LDD12	GPIO_LDD (12)	/* LCD Data [12] (O)               */
-#define GPIO_LDD13	GPIO_LDD (13)	/* LCD Data [13] (O)               */
-#define GPIO_LDD14	GPIO_LDD (14)	/* LCD Data [14] (O)               */
-#define GPIO_LDD15	GPIO_LDD (15)	/* LCD Data [15] (O)               */
-					/* ser. port 4:                    */
-#define GPIO_SSP_TXD	GPIO_GPIO (10)	/*  SSP Transmit Data (O)          */
-#define GPIO_SSP_RXD	GPIO_GPIO (11)	/*  SSP Receive Data (I)           */
-#define GPIO_SSP_SCLK	GPIO_GPIO (12)	/*  SSP Sample CLocK (O)           */
-#define GPIO_SSP_SFRM	GPIO_GPIO (13)	/*  SSP Sample FRaMe (O)           */
-					/* ser. port 1:                    */
-#define GPIO_UART_TXD	GPIO_GPIO (14)	/*  UART Transmit Data (O)         */
-#define GPIO_UART_RXD	GPIO_GPIO (15)	/*  UART Receive Data (I)          */
-#define GPIO_SDLC_SCLK	GPIO_GPIO (16)	/*  SDLC Sample CLocK (I/O)        */
-#define GPIO_SDLC_AAF	GPIO_GPIO (17)	/*  SDLC Abort After Frame (O)     */
-#define GPIO_UART_SCLK1	GPIO_GPIO (18)	/*  UART Sample CLocK 1 (I)        */
-					/* ser. port 4:                    */
-#define GPIO_SSP_CLK	GPIO_GPIO (19)	/*  SSP external CLocK (I)         */
-					/* ser. port 3:                    */
-#define GPIO_UART_SCLK3	GPIO_GPIO (20)	/*  UART Sample CLocK 3 (I)        */
-					/* ser. port 4:                    */
-#define GPIO_MCP_CLK	GPIO_GPIO (21)	/*  MCP CLocK (I)                  */
-					/* test controller:                */
-#define GPIO_TIC_ACK	GPIO_GPIO (21)	/*  TIC ACKnowledge (O)            */
-#define GPIO_MBGNT	GPIO_GPIO (21)	/*  Memory Bus GraNT (O)           */
-#define GPIO_TREQA	GPIO_GPIO (22)	/*  TIC REQuest A (I)              */
-#define GPIO_MBREQ	GPIO_GPIO (22)	/*  Memory Bus REQuest (I)         */
-#define GPIO_TREQB	GPIO_GPIO (23)	/*  TIC REQuest B (I)              */
-#define GPIO_1Hz	GPIO_GPIO (25)	/* 1 Hz clock (O)                  */
+#define GPIO_LDD8	GPIO_LDD (8)	/* LCD Data  [8] (O)		   */
+#define GPIO_LDD9	GPIO_LDD (9)	/* LCD Data  [9] (O)		   */
+#define GPIO_LDD10	GPIO_LDD (10)	/* LCD Data [10] (O)		   */
+#define GPIO_LDD11	GPIO_LDD (11)	/* LCD Data [11] (O)		   */
+#define GPIO_LDD12	GPIO_LDD (12)	/* LCD Data [12] (O)		   */
+#define GPIO_LDD13	GPIO_LDD (13)	/* LCD Data [13] (O)		   */
+#define GPIO_LDD14	GPIO_LDD (14)	/* LCD Data [14] (O)		   */
+#define GPIO_LDD15	GPIO_LDD (15)	/* LCD Data [15] (O)		   */
+					/* ser. port 4:			   */
+#define GPIO_SSP_TXD	GPIO_GPIO (10)	/*  SSP Transmit Data (O)	   */
+#define GPIO_SSP_RXD	GPIO_GPIO (11)	/*  SSP Receive Data (I)	   */
+#define GPIO_SSP_SCLK	GPIO_GPIO (12)	/*  SSP Sample CLocK (O)	   */
+#define GPIO_SSP_SFRM	GPIO_GPIO (13)	/*  SSP Sample FRaMe (O)	   */
+					/* ser. port 1:			   */
+#define GPIO_UART_TXD	GPIO_GPIO (14)	/*  UART Transmit Data (O)	   */
+#define GPIO_UART_RXD	GPIO_GPIO (15)	/*  UART Receive Data (I)	   */
+#define GPIO_SDLC_SCLK	GPIO_GPIO (16)	/*  SDLC Sample CLocK (I/O)	   */
+#define GPIO_SDLC_AAF	GPIO_GPIO (17)	/*  SDLC Abort After Frame (O)	   */
+#define GPIO_UART_SCLK1	GPIO_GPIO (18)	/*  UART Sample CLocK 1 (I)	   */
+					/* ser. port 4:			   */
+#define GPIO_SSP_CLK	GPIO_GPIO (19)	/*  SSP external CLocK (I)	   */
+					/* ser. port 3:			   */
+#define GPIO_UART_SCLK3	GPIO_GPIO (20)	/*  UART Sample CLocK 3 (I)	   */
+					/* ser. port 4:			   */
+#define GPIO_MCP_CLK	GPIO_GPIO (21)	/*  MCP CLocK (I)		   */
+					/* test controller:		   */
+#define GPIO_TIC_ACK	GPIO_GPIO (21)	/*  TIC ACKnowledge (O)		   */
+#define GPIO_MBGNT	GPIO_GPIO (21)	/*  Memory Bus GraNT (O)	   */
+#define GPIO_TREQA	GPIO_GPIO (22)	/*  TIC REQuest A (I)		   */
+#define GPIO_MBREQ	GPIO_GPIO (22)	/*  Memory Bus REQuest (I)	   */
+#define GPIO_TREQB	GPIO_GPIO (23)	/*  TIC REQuest B (I)		   */
+#define GPIO_1Hz	GPIO_GPIO (25)	/* 1 Hz clock (O)		   */
 #define GPIO_RCLK	GPIO_GPIO (26)	/* internal (R) CLocK (O, fcpu/2)  */
-#define GPIO_32_768kHz	GPIO_GPIO (27)	/* 32.768 kHz clock (O, RTC)       */
+#define GPIO_32_768kHz	GPIO_GPIO (27)	/* 32.768 kHz clock (O, RTC)	   */
 
-#define GPDR_In 	0       	/* Input                           */
-#define GPDR_Out	1       	/* Output                          */
+#define GPDR_In		0		/* Input			   */
+#define GPDR_Out	1		/* Output			   */
 
 
 /*
  * Interrupt Controller (IC) control registers
  *
  * Registers
- *    ICIP      	Interrupt Controller (IC) Interrupt ReQuest (IRQ)
- *              	Pending register (read).
- *    ICMR      	Interrupt Controller (IC) Mask Register (read/write).
- *    ICLR      	Interrupt Controller (IC) Level Register (read/write).
- *    ICCR      	Interrupt Controller (IC) Control Register
- *              	(read/write).
- *              	[The ICCR register is only implemented in versions 2.0
- *              	(rev. = 8) and higher of the StrongARM SA-1100.]
- *    ICFP      	Interrupt Controller (IC) Fast Interrupt reQuest
- *              	(FIQ) Pending register (read).
- *    ICPR      	Interrupt Controller (IC) Pending Register (read).
- *              	[The ICPR register is active low (inverted) in
- *              	versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the
- *              	StrongARM SA-1100, it is active high (non-inverted) in
- *              	versions 2.0 (rev. = 8) and higher.]
+ *    ICIP		Interrupt Controller (IC) Interrupt ReQuest (IRQ)
+ *			Pending register (read).
+ *    ICMR		Interrupt Controller (IC) Mask Register (read/write).
+ *    ICLR		Interrupt Controller (IC) Level Register (read/write).
+ *    ICCR		Interrupt Controller (IC) Control Register
+ *			(read/write).
+ *			[The ICCR register is only implemented in versions 2.0
+ *			(rev. = 8) and higher of the StrongARM SA-1100.]
+ *    ICFP		Interrupt Controller (IC) Fast Interrupt reQuest
+ *			(FIQ) Pending register (read).
+ *    ICPR		Interrupt Controller (IC) Pending Register (read).
+ *			[The ICPR register is active low (inverted) in
+ *			versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the
+ *			StrongARM SA-1100, it is active high (non-inverted) in
+ *			versions 2.0 (rev. = 8) and higher.]
  */
 
-#define _ICIP   	0x90050000	/* IC IRQ Pending reg.             */
-#define _ICMR   	0x90050004	/* IC Mask Reg.                    */
-#define _ICLR   	0x90050008	/* IC Level Reg.                   */
-#define _ICCR   	0x9005000C	/* IC Control Reg.                 */
-#define _ICFP   	0x90050010	/* IC FIQ Pending reg.             */
-#define _ICPR   	0x90050020	/* IC Pending Reg.                 */
+#define _ICIP		0x90050000	/* IC IRQ Pending reg.		   */
+#define _ICMR		0x90050004	/* IC Mask Reg.			   */
+#define _ICLR		0x90050008	/* IC Level Reg.		   */
+#define _ICCR		0x9005000C	/* IC Control Reg.		   */
+#define _ICFP		0x90050010	/* IC FIQ Pending reg.		   */
+#define _ICPR		0x90050020	/* IC Pending Reg.		   */
 
 #if LANGUAGE == C
-#define ICIP    	        	/* IC IRQ Pending reg.             */ \
+#define ICIP				/* IC IRQ Pending reg.		   */ \
 			(*((volatile Word *) io_p2v (_ICIP)))
-#define ICMR    	        	/* IC Mask Reg.                    */ \
+#define ICMR				/* IC Mask Reg.			   */ \
 			(*((volatile Word *) io_p2v (_ICMR)))
-#define ICLR    	        	/* IC Level Reg.                   */ \
+#define ICLR				/* IC Level Reg.		   */ \
 			(*((volatile Word *) io_p2v (_ICLR)))
-#define ICCR    	        	/* IC Control Reg.                 */ \
+#define ICCR				/* IC Control Reg.		   */ \
 			(*((volatile Word *) io_p2v (_ICCR)))
-#define ICFP    	        	/* IC FIQ Pending reg.             */ \
+#define ICFP				/* IC FIQ Pending reg.		   */ \
 			(*((volatile Word *) io_p2v (_ICFP)))
-#define ICPR    	        	/* IC Pending Reg.                 */ \
+#define ICPR				/* IC Pending Reg.		   */ \
 			(*((volatile Word *) io_p2v (_ICPR)))
 #endif /* LANGUAGE == C */
 
-#define IC_GPIO(Nb)	        	/* GPIO [0..10]                    */ \
+#define IC_GPIO(Nb)			/* GPIO [0..10]			   */ \
 			(0x00000001 << (Nb))
-#define IC_GPIO0	IC_GPIO (0)	/* GPIO  [0]                       */
-#define IC_GPIO1	IC_GPIO (1)	/* GPIO  [1]                       */
-#define IC_GPIO2	IC_GPIO (2)	/* GPIO  [2]                       */
-#define IC_GPIO3	IC_GPIO (3)	/* GPIO  [3]                       */
-#define IC_GPIO4	IC_GPIO (4)	/* GPIO  [4]                       */
-#define IC_GPIO5	IC_GPIO (5)	/* GPIO  [5]                       */
-#define IC_GPIO6	IC_GPIO (6)	/* GPIO  [6]                       */
-#define IC_GPIO7	IC_GPIO (7)	/* GPIO  [7]                       */
-#define IC_GPIO8	IC_GPIO (8)	/* GPIO  [8]                       */
-#define IC_GPIO9	IC_GPIO (9)	/* GPIO  [9]                       */
-#define IC_GPIO10	IC_GPIO (10)	/* GPIO [10]                       */
-#define IC_GPIO11_27	0x00000800	/* GPIO [11:27] (ORed)             */
-#define IC_LCD  	0x00001000	/* LCD controller                  */
-#define IC_Ser0UDC	0x00002000	/* Ser. port 0 UDC                 */
-#define IC_Ser1SDLC	0x00004000	/* Ser. port 1 SDLC                */
-#define IC_Ser1UART	0x00008000	/* Ser. port 1 UART                */
-#define IC_Ser2ICP	0x00010000	/* Ser. port 2 ICP                 */
-#define IC_Ser3UART	0x00020000	/* Ser. port 3 UART                */
-#define IC_Ser4MCP	0x00040000	/* Ser. port 4 MCP                 */
-#define IC_Ser4SSP	0x00080000	/* Ser. port 4 SSP                 */
-#define IC_DMA(Nb)	        	/* DMA controller channel [0..5]   */ \
+#define IC_GPIO0	IC_GPIO (0)	/* GPIO  [0]			   */
+#define IC_GPIO1	IC_GPIO (1)	/* GPIO  [1]			   */
+#define IC_GPIO2	IC_GPIO (2)	/* GPIO  [2]			   */
+#define IC_GPIO3	IC_GPIO (3)	/* GPIO  [3]			   */
+#define IC_GPIO4	IC_GPIO (4)	/* GPIO  [4]			   */
+#define IC_GPIO5	IC_GPIO (5)	/* GPIO  [5]			   */
+#define IC_GPIO6	IC_GPIO (6)	/* GPIO  [6]			   */
+#define IC_GPIO7	IC_GPIO (7)	/* GPIO  [7]			   */
+#define IC_GPIO8	IC_GPIO (8)	/* GPIO  [8]			   */
+#define IC_GPIO9	IC_GPIO (9)	/* GPIO  [9]			   */
+#define IC_GPIO10	IC_GPIO (10)	/* GPIO [10]			   */
+#define IC_GPIO11_27	0x00000800	/* GPIO [11:27] (ORed)		   */
+#define IC_LCD		0x00001000	/* LCD controller		   */
+#define IC_Ser0UDC	0x00002000	/* Ser. port 0 UDC		   */
+#define IC_Ser1SDLC	0x00004000	/* Ser. port 1 SDLC		   */
+#define IC_Ser1UART	0x00008000	/* Ser. port 1 UART		   */
+#define IC_Ser2ICP	0x00010000	/* Ser. port 2 ICP		   */
+#define IC_Ser3UART	0x00020000	/* Ser. port 3 UART		   */
+#define IC_Ser4MCP	0x00040000	/* Ser. port 4 MCP		   */
+#define IC_Ser4SSP	0x00080000	/* Ser. port 4 SSP		   */
+#define IC_DMA(Nb)			/* DMA controller channel [0..5]   */ \
 			(0x00100000 << (Nb))
-#define IC_DMA0 	IC_DMA (0)	/* DMA controller channel 0        */
-#define IC_DMA1 	IC_DMA (1)	/* DMA controller channel 1        */
-#define IC_DMA2 	IC_DMA (2)	/* DMA controller channel 2        */
-#define IC_DMA3 	IC_DMA (3)	/* DMA controller channel 3        */
-#define IC_DMA4 	IC_DMA (4)	/* DMA controller channel 4        */
-#define IC_DMA5 	IC_DMA (5)	/* DMA controller channel 5        */
-#define IC_OST(Nb)	        	/* OS Timer match [0..3]           */ \
+#define IC_DMA0		IC_DMA (0)	/* DMA controller channel 0	   */
+#define IC_DMA1		IC_DMA (1)	/* DMA controller channel 1	   */
+#define IC_DMA2		IC_DMA (2)	/* DMA controller channel 2	   */
+#define IC_DMA3		IC_DMA (3)	/* DMA controller channel 3	   */
+#define IC_DMA4		IC_DMA (4)	/* DMA controller channel 4	   */
+#define IC_DMA5		IC_DMA (5)	/* DMA controller channel 5	   */
+#define IC_OST(Nb)			/* OS Timer match [0..3]	   */ \
 			(0x04000000 << (Nb))
-#define IC_OST0 	IC_OST (0)	/* OS Timer match 0                */
-#define IC_OST1 	IC_OST (1)	/* OS Timer match 1                */
-#define IC_OST2 	IC_OST (2)	/* OS Timer match 2                */
-#define IC_OST3 	IC_OST (3)	/* OS Timer match 3                */
-#define IC_RTC1Hz	0x40000000	/* RTC 1 Hz clock                  */
-#define IC_RTCAlrm	0x80000000	/* RTC Alarm                       */
-
-#define ICLR_IRQ	0       	/* Interrupt ReQuest               */
-#define ICLR_FIQ	1       	/* Fast Interrupt reQuest          */
-
-#define ICCR_DIM	0x00000001	/* Disable Idle-mode interrupt     */
-					/* Mask                            */
+#define IC_OST0		IC_OST (0)	/* OS Timer match 0		   */
+#define IC_OST1		IC_OST (1)	/* OS Timer match 1		   */
+#define IC_OST2		IC_OST (2)	/* OS Timer match 2		   */
+#define IC_OST3		IC_OST (3)	/* OS Timer match 3		   */
+#define IC_RTC1Hz	0x40000000	/* RTC 1 Hz clock		   */
+#define IC_RTCAlrm	0x80000000	/* RTC Alarm			   */
+
+#define ICLR_IRQ	0		/* Interrupt ReQuest		   */
+#define ICLR_FIQ	1		/* Fast Interrupt reQuest	   */
+
+#define ICCR_DIM	0x00000001	/* Disable Idle-mode interrupt	   */
+					/* Mask				   */
 #define ICCR_IdleAllInt	(ICCR_DIM*0)	/*  Idle-mode All Interrupt enable */
-					/*  (ICMR ignored)                 */
+					/*  (ICMR ignored)		   */
 #define ICCR_IdleMskInt	(ICCR_DIM*1)	/*  Idle-mode non-Masked Interrupt */
-					/*  enable (ICMR used)             */
+					/*  enable (ICMR used)		   */
 
 
 /*
  * Peripheral Pin Controller (PPC) control registers
  *
  * Registers
- *    PPDR      	Peripheral Pin Controller (PPC) Pin Direction
- *              	Register (read/write).
- *    PPSR      	Peripheral Pin Controller (PPC) Pin State Register
- *              	(read/write).
- *    PPAR      	Peripheral Pin Controller (PPC) Pin Assignment
- *              	Register (read/write).
- *    PSDR      	Peripheral Pin Controller (PPC) Sleep-mode pin
- *              	Direction Register (read/write).
- *    PPFR      	Peripheral Pin Controller (PPC) Pin Flag Register
- *              	(read).
+ *    PPDR		Peripheral Pin Controller (PPC) Pin Direction
+ *			Register (read/write).
+ *    PPSR		Peripheral Pin Controller (PPC) Pin State Register
+ *			(read/write).
+ *    PPAR		Peripheral Pin Controller (PPC) Pin Assignment
+ *			Register (read/write).
+ *    PSDR		Peripheral Pin Controller (PPC) Sleep-mode pin
+ *			Direction Register (read/write).
+ *    PPFR		Peripheral Pin Controller (PPC) Pin Flag Register
+ *			(read).
  */
 
-#define _PPDR   	0x90060000	/* PPC Pin Direction Reg.          */
-#define _PPSR   	0x90060004	/* PPC Pin State Reg.              */
-#define _PPAR   	0x90060008	/* PPC Pin Assignment Reg.         */
-#define _PSDR   	0x9006000C	/* PPC Sleep-mode pin Direction    */
-					/* Reg.                            */
-#define _PPFR   	0x90060010	/* PPC Pin Flag Reg.               */
+#define _PPDR		0x90060000	/* PPC Pin Direction Reg.	   */
+#define _PPSR		0x90060004	/* PPC Pin State Reg.		   */
+#define _PPAR		0x90060008	/* PPC Pin Assignment Reg.	   */
+#define _PSDR		0x9006000C	/* PPC Sleep-mode pin Direction    */
+					/* Reg.				   */
+#define _PPFR		0x90060010	/* PPC Pin Flag Reg.		   */
 
 #if LANGUAGE == C
-#define PPDR    	        	/* PPC Pin Direction Reg.          */ \
+#define PPDR				/* PPC Pin Direction Reg.	   */ \
 			(*((volatile Word *) io_p2v (_PPDR)))
-#define PPSR    	        	/* PPC Pin State Reg.              */ \
+#define PPSR				/* PPC Pin State Reg.		   */ \
 			(*((volatile Word *) io_p2v (_PPSR)))
-#define PPAR    	        	/* PPC Pin Assignment Reg.         */ \
+#define PPAR				/* PPC Pin Assignment Reg.	   */ \
 			(*((volatile Word *) io_p2v (_PPAR)))
-#define PSDR    	        	/* PPC Sleep-mode pin Direction    */ \
-					/* Reg.                            */ \
+#define PSDR				/* PPC Sleep-mode pin Direction    */ \
+					/* Reg.				   */ \
 			(*((volatile Word *) io_p2v (_PSDR)))
-#define PPFR    	        	/* PPC Pin Flag Reg.               */ \
+#define PPFR				/* PPC Pin Flag Reg.		   */ \
 			(*((volatile Word *) io_p2v (_PPFR)))
 #endif /* LANGUAGE == C */
 
-#define PPC_LDD(Nb)	        	/* LCD Data [0..7]                 */ \
+#define PPC_LDD(Nb)			/* LCD Data [0..7]		   */ \
 			(0x00000001 << (Nb))
-#define PPC_LDD0	PPC_LDD (0)	/* LCD Data [0]                    */
-#define PPC_LDD1	PPC_LDD (1)	/* LCD Data [1]                    */
-#define PPC_LDD2	PPC_LDD (2)	/* LCD Data [2]                    */
-#define PPC_LDD3	PPC_LDD (3)	/* LCD Data [3]                    */
-#define PPC_LDD4	PPC_LDD (4)	/* LCD Data [4]                    */
-#define PPC_LDD5	PPC_LDD (5)	/* LCD Data [5]                    */
-#define PPC_LDD6	PPC_LDD (6)	/* LCD Data [6]                    */
-#define PPC_LDD7	PPC_LDD (7)	/* LCD Data [7]                    */
-#define PPC_L_PCLK	0x00000100	/* LCD Pixel CLocK                 */
-#define PPC_L_LCLK	0x00000200	/* LCD Line CLocK                  */
-#define PPC_L_FCLK	0x00000400	/* LCD Frame CLocK                 */
-#define PPC_L_BIAS	0x00000800	/* LCD AC BIAS                     */
-					/* ser. port 1:                    */
-#define PPC_TXD1	0x00001000	/*  SDLC/UART Transmit Data 1      */
-#define PPC_RXD1	0x00002000	/*  SDLC/UART Receive Data 1       */
-					/* ser. port 2:                    */
-#define PPC_TXD2	0x00004000	/*  IPC Transmit Data 2            */
-#define PPC_RXD2	0x00008000	/*  IPC Receive Data 2             */
-					/* ser. port 3:                    */
-#define PPC_TXD3	0x00010000	/*  UART Transmit Data 3           */
-#define PPC_RXD3	0x00020000	/*  UART Receive Data 3            */
-					/* ser. port 4:                    */
-#define PPC_TXD4	0x00040000	/*  MCP/SSP Transmit Data 4        */
-#define PPC_RXD4	0x00080000	/*  MCP/SSP Receive Data 4         */
-#define PPC_SCLK	0x00100000	/*  MCP/SSP Sample CLocK           */
-#define PPC_SFRM	0x00200000	/*  MCP/SSP Sample FRaMe           */
-
-#define PPDR_In 	0       	/* Input                           */
-#define PPDR_Out	1       	/* Output                          */
-
-					/* ser. port 1:                    */
-#define PPAR_UPR	0x00001000	/*  UART Pin Reassignment          */
-#define PPAR_UARTTR	(PPAR_UPR*0)	/*   UART on TXD_1 & RXD_1         */
-#define PPAR_UARTGPIO	(PPAR_UPR*1)	/*   UART on GPIO [14:15]          */
-					/* ser. port 4:                    */
-#define PPAR_SPR	0x00040000	/*  SSP Pin Reassignment           */
+#define PPC_LDD0	PPC_LDD (0)	/* LCD Data [0]			   */
+#define PPC_LDD1	PPC_LDD (1)	/* LCD Data [1]			   */
+#define PPC_LDD2	PPC_LDD (2)	/* LCD Data [2]			   */
+#define PPC_LDD3	PPC_LDD (3)	/* LCD Data [3]			   */
+#define PPC_LDD4	PPC_LDD (4)	/* LCD Data [4]			   */
+#define PPC_LDD5	PPC_LDD (5)	/* LCD Data [5]			   */
+#define PPC_LDD6	PPC_LDD (6)	/* LCD Data [6]			   */
+#define PPC_LDD7	PPC_LDD (7)	/* LCD Data [7]			   */
+#define PPC_L_PCLK	0x00000100	/* LCD Pixel CLocK		   */
+#define PPC_L_LCLK	0x00000200	/* LCD Line CLocK		   */
+#define PPC_L_FCLK	0x00000400	/* LCD Frame CLocK		   */
+#define PPC_L_BIAS	0x00000800	/* LCD AC BIAS			   */
+					/* ser. port 1:			   */
+#define PPC_TXD1	0x00001000	/*  SDLC/UART Transmit Data 1	   */
+#define PPC_RXD1	0x00002000	/*  SDLC/UART Receive Data 1	   */
+					/* ser. port 2:			   */
+#define PPC_TXD2	0x00004000	/*  IPC Transmit Data 2		   */
+#define PPC_RXD2	0x00008000	/*  IPC Receive Data 2		   */
+					/* ser. port 3:			   */
+#define PPC_TXD3	0x00010000	/*  UART Transmit Data 3	   */
+#define PPC_RXD3	0x00020000	/*  UART Receive Data 3		   */
+					/* ser. port 4:			   */
+#define PPC_TXD4	0x00040000	/*  MCP/SSP Transmit Data 4	   */
+#define PPC_RXD4	0x00080000	/*  MCP/SSP Receive Data 4	   */
+#define PPC_SCLK	0x00100000	/*  MCP/SSP Sample CLocK	   */
+#define PPC_SFRM	0x00200000	/*  MCP/SSP Sample FRaMe	   */
+
+#define PPDR_In		0		/* Input			   */
+#define PPDR_Out	1		/* Output			   */
+
+					/* ser. port 1:			   */
+#define PPAR_UPR	0x00001000	/*  UART Pin Reassignment	   */
+#define PPAR_UARTTR	(PPAR_UPR*0)	/*   UART on TXD_1 & RXD_1	   */
+#define PPAR_UARTGPIO	(PPAR_UPR*1)	/*   UART on GPIO [14:15]	   */
+					/* ser. port 4:			   */
+#define PPAR_SPR	0x00040000	/*  SSP Pin Reassignment	   */
 #define PPAR_SSPTRSS	(PPAR_SPR*0)	/*   SSP on TXD_C, RXD_C, SCLK_C,  */
-					/*   & SFRM_C                      */
-#define PPAR_SSPGPIO	(PPAR_SPR*1)	/*   SSP on GPIO [10:13]           */
+					/*   & SFRM_C			   */
+#define PPAR_SSPGPIO	(PPAR_SPR*1)	/*   SSP on GPIO [10:13]	   */
 
-#define PSDR_OutL	0       	/* Output Low in sleep mode        */
-#define PSDR_Flt	1       	/* Floating (input) in sleep mode  */
+#define PSDR_OutL	0		/* Output Low in sleep mode	   */
+#define PSDR_Flt	1		/* Floating (input) in sleep mode  */
 
-#define PPFR_LCD	0x00000001	/* LCD controller                  */
+#define PPFR_LCD	0x00000001	/* LCD controller		   */
 #define PPFR_SP1TX	0x00001000	/* Ser. Port 1 SDLC/UART Transmit  */
 #define PPFR_SP1RX	0x00002000	/* Ser. Port 1 SDLC/UART Receive   */
-#define PPFR_SP2TX	0x00004000	/* Ser. Port 2 ICP Transmit        */
-#define PPFR_SP2RX	0x00008000	/* Ser. Port 2 ICP Receive         */
-#define PPFR_SP3TX	0x00010000	/* Ser. Port 3 UART Transmit       */
-#define PPFR_SP3RX	0x00020000	/* Ser. Port 3 UART Receive        */
-#define PPFR_SP4	0x00040000	/* Ser. Port 4 MCP/SSP             */
-#define PPFR_PerEn	0       	/* Peripheral Enabled              */
-#define PPFR_PPCEn	1       	/* PPC Enabled                     */
+#define PPFR_SP2TX	0x00004000	/* Ser. Port 2 ICP Transmit	   */
+#define PPFR_SP2RX	0x00008000	/* Ser. Port 2 ICP Receive	   */
+#define PPFR_SP3TX	0x00010000	/* Ser. Port 3 UART Transmit	   */
+#define PPFR_SP3RX	0x00020000	/* Ser. Port 3 UART Receive	   */
+#define PPFR_SP4	0x00040000	/* Ser. Port 4 MCP/SSP		   */
+#define PPFR_PerEn	0		/* Peripheral Enabled		   */
+#define PPFR_PPCEn	1		/* PPC Enabled			   */
 
 
 /*
  * Dynamic Random-Access Memory (DRAM) control registers
  *
  * Registers
- *    MDCNFG    	Memory system: Dynamic Random-Access Memory (DRAM)
- *              	CoNFiGuration register (read/write).
- *    MDCAS0    	Memory system: Dynamic Random-Access Memory (DRAM)
- *              	Column Address Strobe (CAS) shift register 0
- *              	(read/write).
- *    MDCAS1    	Memory system: Dynamic Random-Access Memory (DRAM)
- *              	Column Address Strobe (CAS) shift register 1
- *              	(read/write).
- *    MDCAS2    	Memory system: Dynamic Random-Access Memory (DRAM)
- *              	Column Address Strobe (CAS) shift register 2
- *              	(read/write).
+ *    MDCNFG		Memory system: Dynamic Random-Access Memory (DRAM)
+ *			CoNFiGuration register (read/write).
+ *    MDCAS0		Memory system: Dynamic Random-Access Memory (DRAM)
+ *			Column Address Strobe (CAS) shift register 0
+ *			(read/write).
+ *    MDCAS1		Memory system: Dynamic Random-Access Memory (DRAM)
+ *			Column Address Strobe (CAS) shift register 1
+ *			(read/write).
+ *    MDCAS2		Memory system: Dynamic Random-Access Memory (DRAM)
+ *			Column Address Strobe (CAS) shift register 2
+ *			(read/write).
  *
  * Clocks
  *    fcpu, Tcpu	Frequency, period of the CPU core clock (CCLK).
@@ -1811,23 +1811,23 @@ typedef PCMCIAPrtType	PCMCIAType [PCMCIASp/PCMCIAPrtSp] ;
  *    fcas, Tcas	Frequency, period of the DRAM CAS shift registers.
  */
 
-					/* Memory system:                  */
-#define _MDCNFG 	0xA0000000	/*  DRAM CoNFiGuration reg.        */
-#define _MDCAS(Nb)	        	/*  DRAM CAS shift reg. [0..3]     */ \
+					/* Memory system:		   */
+#define _MDCNFG		0xA0000000	/*  DRAM CoNFiGuration reg.	   */
+#define _MDCAS(Nb)			/*  DRAM CAS shift reg. [0..3]	   */ \
 			(0xA0000004 + (Nb)*4)
-#define _MDCAS0 	_MDCAS (0)	/*  DRAM CAS shift reg. 0          */
-#define _MDCAS1 	_MDCAS (1)	/*  DRAM CAS shift reg. 1          */
-#define _MDCAS2 	_MDCAS (2)	/*  DRAM CAS shift reg. 2          */
+#define _MDCAS0		_MDCAS (0)	/*  DRAM CAS shift reg. 0	   */
+#define _MDCAS1		_MDCAS (1)	/*  DRAM CAS shift reg. 1	   */
+#define _MDCAS2		_MDCAS (2)	/*  DRAM CAS shift reg. 2	   */
 
 #if LANGUAGE == C
-					/* Memory system:                  */
-#define MDCNFG  	        	/*  DRAM CoNFiGuration reg.        */ \
+					/* Memory system:		   */
+#define MDCNFG				/*  DRAM CoNFiGuration reg.	   */ \
 			(*((volatile Word *) io_p2v (_MDCNFG)))
-#define MDCAS   	        	/*  DRAM CAS shift reg. [0..3]     */ \
+#define MDCAS				/*  DRAM CAS shift reg. [0..3]	   */ \
 			((volatile Word *) io_p2v (_MDCAS (0)))
-#define MDCAS0  	(MDCAS [0])	/*  DRAM CAS shift reg. 0          */
-#define MDCAS1  	(MDCAS [1])	/*  DRAM CAS shift reg. 1          */
-#define MDCAS2  	(MDCAS [2])	/*  DRAM CAS shift reg. 2          */
+#define MDCAS0		(MDCAS [0])	/*  DRAM CAS shift reg. 0	   */
+#define MDCAS1		(MDCAS [1])	/*  DRAM CAS shift reg. 1	   */
+#define MDCAS2		(MDCAS [2])	/*  DRAM CAS shift reg. 2	   */
 
 #elif LANGUAGE == Assembly
 
@@ -1836,58 +1836,58 @@ typedef PCMCIAPrtType	PCMCIAType [PCMCIASp/PCMCIAPrtSp] ;
 #endif /* LANGUAGE == C */
 
 /* SA1100 MDCNFG values */
-#define MDCNFG_DE(Nb)	        	/* DRAM Enable bank [0..3]         */ \
+#define MDCNFG_DE(Nb)			/* DRAM Enable bank [0..3]	   */ \
 			(0x00000001 << (Nb))
-#define MDCNFG_DE0	MDCNFG_DE (0)	/* DRAM Enable bank 0              */
-#define MDCNFG_DE1	MDCNFG_DE (1)	/* DRAM Enable bank 1              */
-#define MDCNFG_DE2	MDCNFG_DE (2)	/* DRAM Enable bank 2              */
-#define MDCNFG_DE3	MDCNFG_DE (3)	/* DRAM Enable bank 3              */
-#define MDCNFG_DRAC	Fld (2, 4)	/* DRAM Row Address Count - 9      */
-#define MDCNFG_RowAdd(Add)      	/*  Row Address count [9..12]      */ \
+#define MDCNFG_DE0	MDCNFG_DE (0)	/* DRAM Enable bank 0		   */
+#define MDCNFG_DE1	MDCNFG_DE (1)	/* DRAM Enable bank 1		   */
+#define MDCNFG_DE2	MDCNFG_DE (2)	/* DRAM Enable bank 2		   */
+#define MDCNFG_DE3	MDCNFG_DE (3)	/* DRAM Enable bank 3		   */
+#define MDCNFG_DRAC	Fld (2, 4)	/* DRAM Row Address Count - 9	   */
+#define MDCNFG_RowAdd(Add)		/*  Row Address count [9..12]	   */ \
 			(((Add) - 9) << FShft (MDCNFG_DRAC))
 #define MDCNFG_CDB2	0x00000040	/* shift reg. Clock Divide By 2    */
-					/* (fcas = fcpu/2)                 */
+					/* (fcas = fcpu/2)		   */
 #define MDCNFG_TRP	Fld (4, 7)	/* Time RAS Pre-charge - 1 [Tmem]  */
-#define MDCNFG_PrChrg(Tcpu)     	/*  Pre-Charge time [2..32 Tcpu]   */ \
+#define MDCNFG_PrChrg(Tcpu)		/*  Pre-Charge time [2..32 Tcpu]   */ \
 			(((Tcpu) - 2)/2 << FShft (MDCNFG_TRP))
-#define MDCNFG_CeilPrChrg(Tcpu) 	/*  Ceil. of PrChrg [2..32 Tcpu]   */ \
+#define MDCNFG_CeilPrChrg(Tcpu)		/*  Ceil. of PrChrg [2..32 Tcpu]   */ \
 			(((Tcpu) - 1)/2 << FShft (MDCNFG_TRP))
-#define MDCNFG_TRASR	Fld (4, 11)	/* Time RAS Refresh - 1 [Tmem]     */
-#define MDCNFG_Ref(Tcpu)        	/*  Refresh time [2..32 Tcpu]      */ \
+#define MDCNFG_TRASR	Fld (4, 11)	/* Time RAS Refresh - 1 [Tmem]	   */
+#define MDCNFG_Ref(Tcpu)		/*  Refresh time [2..32 Tcpu]	   */ \
 			(((Tcpu) - 2)/2 << FShft (MDCNFG_TRASR))
-#define MDCNFG_CeilRef(Tcpu)    	/*  Ceil. of Ref [2..32 Tcpu]      */ \
+#define MDCNFG_CeilRef(Tcpu)		/*  Ceil. of Ref [2..32 Tcpu]	   */ \
 			(((Tcpu) - 1)/2 << FShft (MDCNFG_TRASR))
-#define MDCNFG_TDL	Fld (2, 15)	/* Time Data Latch [Tcpu]          */
-#define MDCNFG_DataLtch(Tcpu)   	/*  Data Latch delay [0..3 Tcpu]   */ \
+#define MDCNFG_TDL	Fld (2, 15)	/* Time Data Latch [Tcpu]	   */
+#define MDCNFG_DataLtch(Tcpu)		/*  Data Latch delay [0..3 Tcpu]   */ \
 			((Tcpu) << FShft (MDCNFG_TDL))
 #define MDCNFG_DRI	Fld (15, 17)	/* min. DRAM Refresh Interval/4    */
-					/* [Tmem]                          */
-#define MDCNFG_RefInt(Tcpu)     	/*  min. Refresh Interval          */ \
-					/*  [0..262136 Tcpu]               */ \
+					/* [Tmem]			   */
+#define MDCNFG_RefInt(Tcpu)		/*  min. Refresh Interval	   */ \
+					/*  [0..262136 Tcpu]		   */ \
 			((Tcpu)/8 << FShft (MDCNFG_DRI))
 
 /* SA1110 MDCNFG values */
-#define MDCNFG_SA1110_DE0	0x00000001	/* DRAM Enable bank 0        */
-#define MDCNFG_SA1110_DE1	0x00000002 	/* DRAM Enable bank 1        */
+#define MDCNFG_SA1110_DE0	0x00000001	/* DRAM Enable bank 0	     */
+#define MDCNFG_SA1110_DE1	0x00000002	/* DRAM Enable bank 1	     */
 #define MDCNFG_SA1110_DTIM0	0x00000004	/* DRAM timing type 0/1      */
-#define MDCNFG_SA1110_DWID0	0x00000008	/* DRAM bus width 0/1        */
+#define MDCNFG_SA1110_DWID0	0x00000008	/* DRAM bus width 0/1	     */
 #define MDCNFG_SA1110_DRAC0	Fld(3, 4)	/* DRAM row addr bit count   */
-						/* bank 0/1                  */
+						/* bank 0/1		     */
 #define MDCNFG_SA1110_CDB20	0x00000080	/* Mem Clock divide by 2 0/1 */
-#define MDCNFG_SA1110_TRP0	Fld(3, 8)	/* RAS precharge 0/1         */
+#define MDCNFG_SA1110_TRP0	Fld(3, 8)	/* RAS precharge 0/1	     */
 #define MDCNFG_SA1110_TDL0	Fld(2, 12)	/* Data input latch after CAS*/
-						/* deassertion 0/1           */
+						/* deassertion 0/1	     */
 #define MDCNFG_SA1110_TWR0	Fld(2, 14)	/* SDRAM write recovery 0/1  */
-#define MDCNFG_SA1110_DE2	0x00010000	/* DRAM Enable bank 0        */
-#define MDCNFG_SA1110_DE3	0x00020000 	/* DRAM Enable bank 1        */
+#define MDCNFG_SA1110_DE2	0x00010000	/* DRAM Enable bank 0	     */
+#define MDCNFG_SA1110_DE3	0x00020000	/* DRAM Enable bank 1	     */
 #define MDCNFG_SA1110_DTIM2	0x00040000	/* DRAM timing type 0/1      */
-#define MDCNFG_SA1110_DWID2	0x00080000	/* DRAM bus width 0/1        */
+#define MDCNFG_SA1110_DWID2	0x00080000	/* DRAM bus width 0/1	     */
 #define MDCNFG_SA1110_DRAC2	Fld(3, 20)	/* DRAM row addr bit count   */
-						/* bank 0/1                  */
+						/* bank 0/1		     */
 #define MDCNFG_SA1110_CDB22	0x00800000	/* Mem Clock divide by 2 0/1 */
-#define MDCNFG_SA1110_TRP2	Fld(3, 24)	/* RAS precharge 0/1         */
+#define MDCNFG_SA1110_TRP2	Fld(3, 24)	/* RAS precharge 0/1	     */
 #define MDCNFG_SA1110_TDL2	Fld(2, 28)	/* Data input latch after CAS*/
-						/* deassertion 0/1           */
+						/* deassertion 0/1	     */
 #define MDCNFG_SA1110_TWR2	Fld(2, 30)	/* SDRAM write recovery 0/1  */
 
 
@@ -1895,32 +1895,32 @@ typedef PCMCIAPrtType	PCMCIAType [PCMCIASp/PCMCIAPrtSp] ;
  * Static memory control registers
  *
  * Registers
- *    MSC0      	Memory system: Static memory Control register 0
- *              	(read/write).
- *    MSC1      	Memory system: Static memory Control register 1
- *              	(read/write).
+ *    MSC0		Memory system: Static memory Control register 0
+ *			(read/write).
+ *    MSC1		Memory system: Static memory Control register 1
+ *			(read/write).
  *
  * Clocks
  *    fcpu, Tcpu	Frequency, period of the CPU core clock (CCLK).
  *    fmem, Tmem	Frequency, period of the memory clock (fmem = fcpu/2).
  */
 
-					/* Memory system:                  */
-#define _MSC(Nb)	        	/*  Static memory Control reg.     */ \
-					/*  [0..1]                         */ \
+					/* Memory system:		   */
+#define _MSC(Nb)			/*  Static memory Control reg.	   */ \
+					/*  [0..1]			   */ \
 			(0xA0000010 + (Nb)*4)
-#define _MSC0   	_MSC (0)	/*  Static memory Control reg. 0   */
-#define _MSC1   	_MSC (1)	/*  Static memory Control reg. 1   */
+#define _MSC0		_MSC (0)	/*  Static memory Control reg. 0   */
+#define _MSC1		_MSC (1)	/*  Static memory Control reg. 1   */
 #define _MSC2		0xA000002C	/*  Static memory Control reg. 2, not contiguous   */
 
 #if LANGUAGE == C
-					/* Memory system:                  */
-#define MSC     	        	/*  Static memory Control reg.     */ \
-					/*  [0..1]                         */ \
+					/* Memory system:		   */
+#define MSC				/*  Static memory Control reg.	   */ \
+					/*  [0..1]			   */ \
 			((volatile Word *) io_p2v (_MSC (0)))
-#define MSC0    	(MSC [0])	/*  Static memory Control reg. 0   */
-#define MSC1    	(MSC [1])	/*  Static memory Control reg. 1   */
-#define MSC2    	(*(volatile Word *) io_p2v (_MSC2))	/*  Static memory Control reg. 2   */
+#define MSC0		(MSC [0])	/*  Static memory Control reg. 0   */
+#define MSC1		(MSC [1])	/*  Static memory Control reg. 1   */
+#define MSC2		(*(volatile Word *) io_p2v (_MSC2))	/*  Static memory Control reg. 2   */
 
 #elif LANGUAGE == Assembly
 
@@ -1930,54 +1930,54 @@ typedef PCMCIAPrtType	PCMCIAType [PCMCIASp/PCMCIAPrtSp] ;
 
 #endif /* LANGUAGE == C */
 
-#define MSC_Bnk(Nb)	        	/* static memory Bank [0..3]       */ \
+#define MSC_Bnk(Nb)			/* static memory Bank [0..3]	   */ \
 			Fld (16, ((Nb) Modulo 2)*16)
-#define MSC0_Bnk0	MSC_Bnk (0)	/* static memory Bank 0            */
-#define MSC0_Bnk1	MSC_Bnk (1)	/* static memory Bank 1            */
-#define MSC1_Bnk2	MSC_Bnk (2)	/* static memory Bank 2            */
-#define MSC1_Bnk3	MSC_Bnk (3)	/* static memory Bank 3            */
+#define MSC0_Bnk0	MSC_Bnk (0)	/* static memory Bank 0		   */
+#define MSC0_Bnk1	MSC_Bnk (1)	/* static memory Bank 1		   */
+#define MSC1_Bnk2	MSC_Bnk (2)	/* static memory Bank 2		   */
+#define MSC1_Bnk3	MSC_Bnk (3)	/* static memory Bank 3		   */
 
-#define MSC_RT  	Fld (2, 0)	/* ROM/static memory Type          */
-#define MSC_NonBrst	        	/*  Non-Burst static memory        */ \
+#define MSC_RT		Fld (2, 0)	/* ROM/static memory Type	   */
+#define MSC_NonBrst			/*  Non-Burst static memory	   */ \
 			(0 << FShft (MSC_RT))
-#define MSC_SRAM	        	/*  32-bit byte-writable SRAM      */ \
+#define MSC_SRAM			/*  32-bit byte-writable SRAM	   */ \
 			(1 << FShft (MSC_RT))
-#define MSC_Brst4	        	/*  Burst-of-4 static memory       */ \
+#define MSC_Brst4			/*  Burst-of-4 static memory	   */ \
 			(2 << FShft (MSC_RT))
-#define MSC_Brst8	        	/*  Burst-of-8 static memory       */ \
+#define MSC_Brst8			/*  Burst-of-8 static memory	   */ \
 			(3 << FShft (MSC_RT))
-#define MSC_RBW 	0x0004  	/* ROM/static memory Bus Width     */
-#define MSC_32BitStMem	(MSC_RBW*0)	/*  32-Bit Static Memory           */
-#define MSC_16BitStMem	(MSC_RBW*1)	/*  16-Bit Static Memory           */
-#define MSC_RDF 	Fld (5, 3)	/* ROM/static memory read Delay    */
-					/* First access - 1(.5) [Tmem]     */
-#define MSC_1stRdAcc(Tcpu)      	/*  1st Read Access time (burst    */ \
+#define MSC_RBW		0x0004		/* ROM/static memory Bus Width	   */
+#define MSC_32BitStMem	(MSC_RBW*0)	/*  32-Bit Static Memory	   */
+#define MSC_16BitStMem	(MSC_RBW*1)	/*  16-Bit Static Memory	   */
+#define MSC_RDF		Fld (5, 3)	/* ROM/static memory read Delay    */
+					/* First access - 1(.5) [Tmem]	   */
+#define MSC_1stRdAcc(Tcpu)		/*  1st Read Access time (burst    */ \
 					/*  static memory) [3..65 Tcpu]    */ \
 			((((Tcpu) - 3)/2) << FShft (MSC_RDF))
-#define MSC_Ceil1stRdAcc(Tcpu)  	/*  Ceil. of 1stRdAcc [3..65 Tcpu] */ \
+#define MSC_Ceil1stRdAcc(Tcpu)		/*  Ceil. of 1stRdAcc [3..65 Tcpu] */ \
 			((((Tcpu) - 2)/2) << FShft (MSC_RDF))
-#define MSC_RdAcc(Tcpu)	        	/*  Read Access time (non-burst    */ \
+#define MSC_RdAcc(Tcpu)			/*  Read Access time (non-burst    */ \
 					/*  static memory) [2..64 Tcpu]    */ \
 			((((Tcpu) - 2)/2) << FShft (MSC_RDF))
-#define MSC_CeilRdAcc(Tcpu)     	/*  Ceil. of RdAcc [2..64 Tcpu]    */ \
+#define MSC_CeilRdAcc(Tcpu)		/*  Ceil. of RdAcc [2..64 Tcpu]    */ \
 			((((Tcpu) - 1)/2) << FShft (MSC_RDF))
-#define MSC_RDN 	Fld (5, 8)	/* ROM/static memory read Delay    */
-					/* Next access - 1 [Tmem]          */
-#define MSC_NxtRdAcc(Tcpu)      	/*  Next Read Access time (burst   */ \
+#define MSC_RDN		Fld (5, 8)	/* ROM/static memory read Delay    */
+					/* Next access - 1 [Tmem]	   */
+#define MSC_NxtRdAcc(Tcpu)		/*  Next Read Access time (burst   */ \
 					/*  static memory) [2..64 Tcpu]    */ \
 			((((Tcpu) - 2)/2) << FShft (MSC_RDN))
-#define MSC_CeilNxtRdAcc(Tcpu)  	/*  Ceil. of NxtRdAcc [2..64 Tcpu] */ \
+#define MSC_CeilNxtRdAcc(Tcpu)		/*  Ceil. of NxtRdAcc [2..64 Tcpu] */ \
 			((((Tcpu) - 1)/2) << FShft (MSC_RDN))
-#define MSC_WrAcc(Tcpu)	        	/*  Write Access time (non-burst   */ \
+#define MSC_WrAcc(Tcpu)			/*  Write Access time (non-burst   */ \
 					/*  static memory) [2..64 Tcpu]    */ \
 			((((Tcpu) - 2)/2) << FShft (MSC_RDN))
-#define MSC_CeilWrAcc(Tcpu)     	/*  Ceil. of WrAcc [2..64 Tcpu]    */ \
+#define MSC_CeilWrAcc(Tcpu)		/*  Ceil. of WrAcc [2..64 Tcpu]    */ \
 			((((Tcpu) - 1)/2) << FShft (MSC_RDN))
-#define MSC_RRR 	Fld (3, 13)	/* ROM/static memory RecoveRy      */
-					/* time/2 [Tmem]                   */
-#define MSC_Rec(Tcpu)	        	/*  Recovery time [0..28 Tcpu]     */ \
+#define MSC_RRR		Fld (3, 13)	/* ROM/static memory RecoveRy	   */
+					/* time/2 [Tmem]		   */
+#define MSC_Rec(Tcpu)			/*  Recovery time [0..28 Tcpu]	   */ \
 			(((Tcpu)/4) << FShft (MSC_RRR))
-#define MSC_CeilRec(Tcpu)       	/*  Ceil. of Rec [0..28 Tcpu]      */ \
+#define MSC_CeilRec(Tcpu)		/*  Ceil. of Rec [0..28 Tcpu]	   */ \
 			((((Tcpu) + 3)/4) << FShft (MSC_RRR))
 
 
@@ -1986,8 +1986,8 @@ typedef PCMCIAPrtType	PCMCIAType [PCMCIASp/PCMCIAPrtSp] ;
  * register
  *
  * Register
- *    MECR      	Memory system: Expansion memory bus (PCMCIA)
- *              	Configuration Register (read/write).
+ *    MECR		Memory system: Expansion memory bus (PCMCIA)
+ *			Configuration Register (read/write).
  *
  * Clocks
  *    fcpu, Tcpu	Frequency, period of the CPU core clock (CCLK).
@@ -1995,37 +1995,37 @@ typedef PCMCIAPrtType	PCMCIAType [PCMCIASp/PCMCIAPrtSp] ;
  *    fbclk, Tbclk	Frequency, period of the PCMCIA clock (BCLK).
  */
 
-					/* Memory system:                  */
-#define _MECR   	0xA0000018	/*  Expansion memory bus (PCMCIA)  */
-					/*  Configuration Reg.             */
+					/* Memory system:		   */
+#define _MECR		0xA0000018	/*  Expansion memory bus (PCMCIA)  */
+					/*  Configuration Reg.		   */
 
 #if LANGUAGE == C
-					/* Memory system:                  */
-#define MECR    	        	/*  Expansion memory bus (PCMCIA)  */ \
-					/*  Configuration Reg.             */ \
+					/* Memory system:		   */
+#define MECR				/*  Expansion memory bus (PCMCIA)  */ \
+					/*  Configuration Reg.		   */ \
 			(*((volatile Word *) io_p2v (_MECR)))
 #endif /* LANGUAGE == C */
 
-#define MECR_PCMCIA(Nb)	        	/* PCMCIA [0..1]                   */ \
+#define MECR_PCMCIA(Nb)			/* PCMCIA [0..1]		   */ \
 			Fld (15, (Nb)*16)
-#define MECR_PCMCIA0	MECR_PCMCIA (0)	/* PCMCIA 0                        */
-#define MECR_PCMCIA1	MECR_PCMCIA (1)	/* PCMCIA 1                        */
+#define MECR_PCMCIA0	MECR_PCMCIA (0)	/* PCMCIA 0			   */
+#define MECR_PCMCIA1	MECR_PCMCIA (1)	/* PCMCIA 1			   */
 
-#define MECR_BSIO	Fld (5, 0)	/* BCLK Select I/O - 1 [Tmem]      */
-#define MECR_IOClk(Tcpu)        	/*  I/O Clock [2..64 Tcpu]         */ \
+#define MECR_BSIO	Fld (5, 0)	/* BCLK Select I/O - 1 [Tmem]	   */
+#define MECR_IOClk(Tcpu)		/*  I/O Clock [2..64 Tcpu]	   */ \
 			((((Tcpu) - 2)/2) << FShft (MECR_BSIO))
-#define MECR_CeilIOClk(Tcpu)    	/*  Ceil. of IOClk [2..64 Tcpu]    */ \
+#define MECR_CeilIOClk(Tcpu)		/*  Ceil. of IOClk [2..64 Tcpu]    */ \
 			((((Tcpu) - 1)/2) << FShft (MECR_BSIO))
-#define MECR_BSA	Fld (5, 5)	/* BCLK Select Attribute - 1       */
-					/* [Tmem]                          */
-#define MECR_AttrClk(Tcpu)      	/*  Attribute Clock [2..64 Tcpu]   */ \
+#define MECR_BSA	Fld (5, 5)	/* BCLK Select Attribute - 1	   */
+					/* [Tmem]			   */
+#define MECR_AttrClk(Tcpu)		/*  Attribute Clock [2..64 Tcpu]   */ \
 			((((Tcpu) - 2)/2) << FShft (MECR_BSA))
-#define MECR_CeilAttrClk(Tcpu)  	/*  Ceil. of AttrClk [2..64 Tcpu]  */ \
+#define MECR_CeilAttrClk(Tcpu)		/*  Ceil. of AttrClk [2..64 Tcpu]  */ \
 			((((Tcpu) - 1)/2) << FShft (MECR_BSA))
 #define MECR_BSM	Fld (5, 10)	/* BCLK Select Memory - 1 [Tmem]   */
-#define MECR_MemClk(Tcpu)       	/*  Memory Clock [2..64 Tcpu]      */ \
+#define MECR_MemClk(Tcpu)		/*  Memory Clock [2..64 Tcpu]	   */ \
 			((((Tcpu) - 2)/2) << FShft (MECR_BSM))
-#define MECR_CeilMemClk(Tcpu)   	/*  Ceil. of MemClk [2..64 Tcpu]   */ \
+#define MECR_CeilMemClk(Tcpu)		/*  Ceil. of MemClk [2..64 Tcpu]   */ \
 			((((Tcpu) - 1)/2) << FShft (MECR_BSM))
 
 /*
@@ -2035,7 +2035,7 @@ typedef PCMCIAPrtType	PCMCIAType [PCMCIASp/PCMCIAPrtSp] ;
 #define _MDREFR		0xA000001C
 
 #if LANGUAGE == C
-					/* Memory system:                  */
+					/* Memory system:		   */
 #define MDREFR \
 			(*((volatile Word *) io_p2v (_MDREFR)))
 
@@ -2064,769 +2064,769 @@ typedef PCMCIAPrtType	PCMCIAType [PCMCIASp/PCMCIAPrtSp] ;
  * Direct Memory Access (DMA) control registers
  *
  * Registers
- *    DDAR0     	Direct Memory Access (DMA) Device Address Register
- *              	channel 0 (read/write).
- *    DCSR0     	Direct Memory Access (DMA) Control and Status
- *              	Register channel 0 (read/write).
- *    DBSA0     	Direct Memory Access (DMA) Buffer Start address
- *              	register A channel 0 (read/write).
- *    DBTA0     	Direct Memory Access (DMA) Buffer Transfer count
- *              	register A channel 0 (read/write).
- *    DBSB0     	Direct Memory Access (DMA) Buffer Start address
- *              	register B channel 0 (read/write).
- *    DBTB0     	Direct Memory Access (DMA) Buffer Transfer count
- *              	register B channel 0 (read/write).
+ *    DDAR0		Direct Memory Access (DMA) Device Address Register
+ *			channel 0 (read/write).
+ *    DCSR0		Direct Memory Access (DMA) Control and Status
+ *			Register channel 0 (read/write).
+ *    DBSA0		Direct Memory Access (DMA) Buffer Start address
+ *			register A channel 0 (read/write).
+ *    DBTA0		Direct Memory Access (DMA) Buffer Transfer count
+ *			register A channel 0 (read/write).
+ *    DBSB0		Direct Memory Access (DMA) Buffer Start address
+ *			register B channel 0 (read/write).
+ *    DBTB0		Direct Memory Access (DMA) Buffer Transfer count
+ *			register B channel 0 (read/write).
  *
- *    DDAR1     	Direct Memory Access (DMA) Device Address Register
- *              	channel 1 (read/write).
- *    DCSR1     	Direct Memory Access (DMA) Control and Status
- *              	Register channel 1 (read/write).
- *    DBSA1     	Direct Memory Access (DMA) Buffer Start address
- *              	register A channel 1 (read/write).
- *    DBTA1     	Direct Memory Access (DMA) Buffer Transfer count
- *              	register A channel 1 (read/write).
- *    DBSB1     	Direct Memory Access (DMA) Buffer Start address
- *              	register B channel 1 (read/write).
- *    DBTB1     	Direct Memory Access (DMA) Buffer Transfer count
- *              	register B channel 1 (read/write).
+ *    DDAR1		Direct Memory Access (DMA) Device Address Register
+ *			channel 1 (read/write).
+ *    DCSR1		Direct Memory Access (DMA) Control and Status
+ *			Register channel 1 (read/write).
+ *    DBSA1		Direct Memory Access (DMA) Buffer Start address
+ *			register A channel 1 (read/write).
+ *    DBTA1		Direct Memory Access (DMA) Buffer Transfer count
+ *			register A channel 1 (read/write).
+ *    DBSB1		Direct Memory Access (DMA) Buffer Start address
+ *			register B channel 1 (read/write).
+ *    DBTB1		Direct Memory Access (DMA) Buffer Transfer count
+ *			register B channel 1 (read/write).
  *
- *    DDAR2     	Direct Memory Access (DMA) Device Address Register
- *              	channel 2 (read/write).
- *    DCSR2     	Direct Memory Access (DMA) Control and Status
- *              	Register channel 2 (read/write).
- *    DBSA2     	Direct Memory Access (DMA) Buffer Start address
- *              	register A channel 2 (read/write).
- *    DBTA2     	Direct Memory Access (DMA) Buffer Transfer count
- *              	register A channel 2 (read/write).
- *    DBSB2     	Direct Memory Access (DMA) Buffer Start address
- *              	register B channel 2 (read/write).
- *    DBTB2     	Direct Memory Access (DMA) Buffer Transfer count
- *              	register B channel 2 (read/write).
+ *    DDAR2		Direct Memory Access (DMA) Device Address Register
+ *			channel 2 (read/write).
+ *    DCSR2		Direct Memory Access (DMA) Control and Status
+ *			Register channel 2 (read/write).
+ *    DBSA2		Direct Memory Access (DMA) Buffer Start address
+ *			register A channel 2 (read/write).
+ *    DBTA2		Direct Memory Access (DMA) Buffer Transfer count
+ *			register A channel 2 (read/write).
+ *    DBSB2		Direct Memory Access (DMA) Buffer Start address
+ *			register B channel 2 (read/write).
+ *    DBTB2		Direct Memory Access (DMA) Buffer Transfer count
+ *			register B channel 2 (read/write).
  *
- *    DDAR3     	Direct Memory Access (DMA) Device Address Register
- *              	channel 3 (read/write).
- *    DCSR3     	Direct Memory Access (DMA) Control and Status
- *              	Register channel 3 (read/write).
- *    DBSA3     	Direct Memory Access (DMA) Buffer Start address
- *              	register A channel 3 (read/write).
- *    DBTA3     	Direct Memory Access (DMA) Buffer Transfer count
- *              	register A channel 3 (read/write).
- *    DBSB3     	Direct Memory Access (DMA) Buffer Start address
- *              	register B channel 3 (read/write).
- *    DBTB3     	Direct Memory Access (DMA) Buffer Transfer count
- *              	register B channel 3 (read/write).
+ *    DDAR3		Direct Memory Access (DMA) Device Address Register
+ *			channel 3 (read/write).
+ *    DCSR3		Direct Memory Access (DMA) Control and Status
+ *			Register channel 3 (read/write).
+ *    DBSA3		Direct Memory Access (DMA) Buffer Start address
+ *			register A channel 3 (read/write).
+ *    DBTA3		Direct Memory Access (DMA) Buffer Transfer count
+ *			register A channel 3 (read/write).
+ *    DBSB3		Direct Memory Access (DMA) Buffer Start address
+ *			register B channel 3 (read/write).
+ *    DBTB3		Direct Memory Access (DMA) Buffer Transfer count
+ *			register B channel 3 (read/write).
  *
- *    DDAR4     	Direct Memory Access (DMA) Device Address Register
- *              	channel 4 (read/write).
- *    DCSR4     	Direct Memory Access (DMA) Control and Status
- *              	Register channel 4 (read/write).
- *    DBSA4     	Direct Memory Access (DMA) Buffer Start address
- *              	register A channel 4 (read/write).
- *    DBTA4     	Direct Memory Access (DMA) Buffer Transfer count
- *              	register A channel 4 (read/write).
- *    DBSB4     	Direct Memory Access (DMA) Buffer Start address
- *              	register B channel 4 (read/write).
- *    DBTB4     	Direct Memory Access (DMA) Buffer Transfer count
- *              	register B channel 4 (read/write).
+ *    DDAR4		Direct Memory Access (DMA) Device Address Register
+ *			channel 4 (read/write).
+ *    DCSR4		Direct Memory Access (DMA) Control and Status
+ *			Register channel 4 (read/write).
+ *    DBSA4		Direct Memory Access (DMA) Buffer Start address
+ *			register A channel 4 (read/write).
+ *    DBTA4		Direct Memory Access (DMA) Buffer Transfer count
+ *			register A channel 4 (read/write).
+ *    DBSB4		Direct Memory Access (DMA) Buffer Start address
+ *			register B channel 4 (read/write).
+ *    DBTB4		Direct Memory Access (DMA) Buffer Transfer count
+ *			register B channel 4 (read/write).
  *
- *    DDAR5     	Direct Memory Access (DMA) Device Address Register
- *              	channel 5 (read/write).
- *    DCSR5     	Direct Memory Access (DMA) Control and Status
- *              	Register channel 5 (read/write).
- *    DBSA5     	Direct Memory Access (DMA) Buffer Start address
- *              	register A channel 5 (read/write).
- *    DBTA5     	Direct Memory Access (DMA) Buffer Transfer count
- *              	register A channel 5 (read/write).
- *    DBSB5     	Direct Memory Access (DMA) Buffer Start address
- *              	register B channel 5 (read/write).
- *    DBTB5     	Direct Memory Access (DMA) Buffer Transfer count
- *              	register B channel 5 (read/write).
+ *    DDAR5		Direct Memory Access (DMA) Device Address Register
+ *			channel 5 (read/write).
+ *    DCSR5		Direct Memory Access (DMA) Control and Status
+ *			Register channel 5 (read/write).
+ *    DBSA5		Direct Memory Access (DMA) Buffer Start address
+ *			register A channel 5 (read/write).
+ *    DBTA5		Direct Memory Access (DMA) Buffer Transfer count
+ *			register A channel 5 (read/write).
+ *    DBSB5		Direct Memory Access (DMA) Buffer Start address
+ *			register B channel 5 (read/write).
+ *    DBTB5		Direct Memory Access (DMA) Buffer Transfer count
+ *			register B channel 5 (read/write).
  */
 
-#define DMASp   	0x00000020	/* DMA control reg. Space [byte]   */
+#define DMASp		0x00000020	/* DMA control reg. Space [byte]   */
 
-#define _DDAR(Nb)	        	/* DMA Device Address Reg.         */ \
-					/* channel [0..5]                  */ \
+#define _DDAR(Nb)			/* DMA Device Address Reg.	   */ \
+					/* channel [0..5]		   */ \
 			(0xB0000000 + (Nb)*DMASp)
-#define _SetDCSR(Nb)	        	/* Set DMA Control & Status Reg.   */ \
-					/* channel [0..5] (write)          */ \
+#define _SetDCSR(Nb)			/* Set DMA Control & Status Reg.   */ \
+					/* channel [0..5] (write)	   */ \
 			(0xB0000004 + (Nb)*DMASp)
-#define _ClrDCSR(Nb)	        	/* Clear DMA Control & Status Reg. */ \
-					/* channel [0..5] (write)          */ \
+#define _ClrDCSR(Nb)			/* Clear DMA Control & Status Reg. */ \
+					/* channel [0..5] (write)	   */ \
 			(0xB0000008 + (Nb)*DMASp)
-#define _RdDCSR(Nb)	        	/* Read DMA Control & Status Reg.  */ \
-					/* channel [0..5] (read)           */ \
+#define _RdDCSR(Nb)			/* Read DMA Control & Status Reg.  */ \
+					/* channel [0..5] (read)	   */ \
 			(0xB000000C + (Nb)*DMASp)
-#define _DBSA(Nb)	        	/* DMA Buffer Start address reg. A */ \
-					/* channel [0..5]                  */ \
+#define _DBSA(Nb)			/* DMA Buffer Start address reg. A */ \
+					/* channel [0..5]		   */ \
 			(0xB0000010 + (Nb)*DMASp)
-#define _DBTA(Nb)	        	/* DMA Buffer Transfer count       */ \
-					/* reg. A channel [0..5]           */ \
+#define _DBTA(Nb)			/* DMA Buffer Transfer count	   */ \
+					/* reg. A channel [0..5]	   */ \
 			(0xB0000014 + (Nb)*DMASp)
-#define _DBSB(Nb)	        	/* DMA Buffer Start address reg. B */ \
-					/* channel [0..5]                  */ \
+#define _DBSB(Nb)			/* DMA Buffer Start address reg. B */ \
+					/* channel [0..5]		   */ \
 			(0xB0000018 + (Nb)*DMASp)
-#define _DBTB(Nb)	        	/* DMA Buffer Transfer count       */ \
-					/* reg. B channel [0..5]           */ \
+#define _DBTB(Nb)			/* DMA Buffer Transfer count	   */ \
+					/* reg. B channel [0..5]	   */ \
 			(0xB000001C + (Nb)*DMASp)
 
-#define _DDAR0  	_DDAR (0)	/* DMA Device Address Reg.         */
-					/* channel 0                       */
+#define _DDAR0		_DDAR (0)	/* DMA Device Address Reg.	   */
+					/* channel 0			   */
 #define _SetDCSR0	_SetDCSR (0)	/* Set DMA Control & Status Reg.   */
-					/* channel 0 (write)               */
+					/* channel 0 (write)		   */
 #define _ClrDCSR0	_ClrDCSR (0)	/* Clear DMA Control & Status Reg. */
-					/* channel 0 (write)               */
+					/* channel 0 (write)		   */
 #define _RdDCSR0	_RdDCSR (0)	/* Read DMA Control & Status Reg.  */
-					/* channel 0 (read)                */
-#define _DBSA0  	_DBSA (0)	/* DMA Buffer Start address reg. A */
-					/* channel 0                       */
-#define _DBTA0  	_DBTA (0)	/* DMA Buffer Transfer count       */
-					/* reg. A channel 0                */
-#define _DBSB0  	_DBSB (0)	/* DMA Buffer Start address reg. B */
-					/* channel 0                       */
-#define _DBTB0  	_DBTB (0)	/* DMA Buffer Transfer count       */
-					/* reg. B channel 0                */
-
-#define _DDAR1  	_DDAR (1)	/* DMA Device Address Reg.         */
-					/* channel 1                       */
+					/* channel 0 (read)		   */
+#define _DBSA0		_DBSA (0)	/* DMA Buffer Start address reg. A */
+					/* channel 0			   */
+#define _DBTA0		_DBTA (0)	/* DMA Buffer Transfer count	   */
+					/* reg. A channel 0		   */
+#define _DBSB0		_DBSB (0)	/* DMA Buffer Start address reg. B */
+					/* channel 0			   */
+#define _DBTB0		_DBTB (0)	/* DMA Buffer Transfer count	   */
+					/* reg. B channel 0		   */
+
+#define _DDAR1		_DDAR (1)	/* DMA Device Address Reg.	   */
+					/* channel 1			   */
 #define _SetDCSR1	_SetDCSR (1)	/* Set DMA Control & Status Reg.   */
-					/* channel 1 (write)               */
+					/* channel 1 (write)		   */
 #define _ClrDCSR1	_ClrDCSR (1)	/* Clear DMA Control & Status Reg. */
-					/* channel 1 (write)               */
+					/* channel 1 (write)		   */
 #define _RdDCSR1	_RdDCSR (1)	/* Read DMA Control & Status Reg.  */
-					/* channel 1 (read)                */
-#define _DBSA1  	_DBSA (1)	/* DMA Buffer Start address reg. A */
-					/* channel 1                       */
-#define _DBTA1  	_DBTA (1)	/* DMA Buffer Transfer count       */
-					/* reg. A channel 1                */
-#define _DBSB1  	_DBSB (1)	/* DMA Buffer Start address reg. B */
-					/* channel 1                       */
-#define _DBTB1  	_DBTB (1)	/* DMA Buffer Transfer count       */
-					/* reg. B channel 1                */
-
-#define _DDAR2  	_DDAR (2)	/* DMA Device Address Reg.         */
-					/* channel 2                       */
+					/* channel 1 (read)		   */
+#define _DBSA1		_DBSA (1)	/* DMA Buffer Start address reg. A */
+					/* channel 1			   */
+#define _DBTA1		_DBTA (1)	/* DMA Buffer Transfer count	   */
+					/* reg. A channel 1		   */
+#define _DBSB1		_DBSB (1)	/* DMA Buffer Start address reg. B */
+					/* channel 1			   */
+#define _DBTB1		_DBTB (1)	/* DMA Buffer Transfer count	   */
+					/* reg. B channel 1		   */
+
+#define _DDAR2		_DDAR (2)	/* DMA Device Address Reg.	   */
+					/* channel 2			   */
 #define _SetDCSR2	_SetDCSR (2)	/* Set DMA Control & Status Reg.   */
-					/* channel 2 (write)               */
+					/* channel 2 (write)		   */
 #define _ClrDCSR2	_ClrDCSR (2)	/* Clear DMA Control & Status Reg. */
-					/* channel 2 (write)               */
+					/* channel 2 (write)		   */
 #define _RdDCSR2	_RdDCSR (2)	/* Read DMA Control & Status Reg.  */
-					/* channel 2 (read)                */
-#define _DBSA2  	_DBSA (2)	/* DMA Buffer Start address reg. A */
-					/* channel 2                       */
-#define _DBTA2  	_DBTA (2)	/* DMA Buffer Transfer count       */
-					/* reg. A channel 2                */
-#define _DBSB2  	_DBSB (2)	/* DMA Buffer Start address reg. B */
-					/* channel 2                       */
-#define _DBTB2  	_DBTB (2)	/* DMA Buffer Transfer count       */
-					/* reg. B channel 2                */
-
-#define _DDAR3  	_DDAR (3)	/* DMA Device Address Reg.         */
-					/* channel 3                       */
+					/* channel 2 (read)		   */
+#define _DBSA2		_DBSA (2)	/* DMA Buffer Start address reg. A */
+					/* channel 2			   */
+#define _DBTA2		_DBTA (2)	/* DMA Buffer Transfer count	   */
+					/* reg. A channel 2		   */
+#define _DBSB2		_DBSB (2)	/* DMA Buffer Start address reg. B */
+					/* channel 2			   */
+#define _DBTB2		_DBTB (2)	/* DMA Buffer Transfer count	   */
+					/* reg. B channel 2		   */
+
+#define _DDAR3		_DDAR (3)	/* DMA Device Address Reg.	   */
+					/* channel 3			   */
 #define _SetDCSR3	_SetDCSR (3)	/* Set DMA Control & Status Reg.   */
-					/* channel 3 (write)               */
+					/* channel 3 (write)		   */
 #define _ClrDCSR3	_ClrDCSR (3)	/* Clear DMA Control & Status Reg. */
-					/* channel 3 (write)               */
+					/* channel 3 (write)		   */
 #define _RdDCSR3	_RdDCSR (3)	/* Read DMA Control & Status Reg.  */
-					/* channel 3 (read)                */
-#define _DBSA3  	_DBSA (3)	/* DMA Buffer Start address reg. A */
-					/* channel 3                       */
-#define _DBTA3  	_DBTA (3)	/* DMA Buffer Transfer count       */
-					/* reg. A channel 3                */
-#define _DBSB3  	_DBSB (3)	/* DMA Buffer Start address reg. B */
-					/* channel 3                       */
-#define _DBTB3  	_DBTB (3)	/* DMA Buffer Transfer count       */
-					/* reg. B channel 3                */
-
-#define _DDAR4  	_DDAR (4)	/* DMA Device Address Reg.         */
-					/* channel 4                       */
+					/* channel 3 (read)		   */
+#define _DBSA3		_DBSA (3)	/* DMA Buffer Start address reg. A */
+					/* channel 3			   */
+#define _DBTA3		_DBTA (3)	/* DMA Buffer Transfer count	   */
+					/* reg. A channel 3		   */
+#define _DBSB3		_DBSB (3)	/* DMA Buffer Start address reg. B */
+					/* channel 3			   */
+#define _DBTB3		_DBTB (3)	/* DMA Buffer Transfer count	   */
+					/* reg. B channel 3		   */
+
+#define _DDAR4		_DDAR (4)	/* DMA Device Address Reg.	   */
+					/* channel 4			   */
 #define _SetDCSR4	_SetDCSR (4)	/* Set DMA Control & Status Reg.   */
-					/* channel 4 (write)               */
+					/* channel 4 (write)		   */
 #define _ClrDCSR4	_ClrDCSR (4)	/* Clear DMA Control & Status Reg. */
-					/* channel 4 (write)               */
+					/* channel 4 (write)		   */
 #define _RdDCSR4	_RdDCSR (4)	/* Read DMA Control & Status Reg.  */
-					/* channel 4 (read)                */
-#define _DBSA4  	_DBSA (4)	/* DMA Buffer Start address reg. A */
-					/* channel 4                       */
-#define _DBTA4  	_DBTA (4)	/* DMA Buffer Transfer count       */
-					/* reg. A channel 4                */
-#define _DBSB4  	_DBSB (4)	/* DMA Buffer Start address reg. B */
-					/* channel 4                       */
-#define _DBTB4  	_DBTB (4)	/* DMA Buffer Transfer count       */
-					/* reg. B channel 4                */
-
-#define _DDAR5  	_DDAR (5)	/* DMA Device Address Reg.         */
-					/* channel 5                       */
+					/* channel 4 (read)		   */
+#define _DBSA4		_DBSA (4)	/* DMA Buffer Start address reg. A */
+					/* channel 4			   */
+#define _DBTA4		_DBTA (4)	/* DMA Buffer Transfer count	   */
+					/* reg. A channel 4		   */
+#define _DBSB4		_DBSB (4)	/* DMA Buffer Start address reg. B */
+					/* channel 4			   */
+#define _DBTB4		_DBTB (4)	/* DMA Buffer Transfer count	   */
+					/* reg. B channel 4		   */
+
+#define _DDAR5		_DDAR (5)	/* DMA Device Address Reg.	   */
+					/* channel 5			   */
 #define _SetDCSR5	_SetDCSR (5)	/* Set DMA Control & Status Reg.   */
-					/* channel 5 (write)               */
+					/* channel 5 (write)		   */
 #define _ClrDCSR5	_ClrDCSR (5)	/* Clear DMA Control & Status Reg. */
-					/* channel 5 (write)               */
+					/* channel 5 (write)		   */
 #define _RdDCSR5	_RdDCSR (5)	/* Read DMA Control & Status Reg.  */
-					/* channel 5 (read)                */
-#define _DBSA5  	_DBSA (5)	/* DMA Buffer Start address reg. A */
-					/* channel 5                       */
-#define _DBTA5  	_DBTA (5)	/* DMA Buffer Transfer count       */
-					/* reg. A channel 5                */
-#define _DBSB5  	_DBSB (5)	/* DMA Buffer Start address reg. B */
-					/* channel 5                       */
-#define _DBTB5  	_DBTB (5)	/* DMA Buffer Transfer count       */
-					/* reg. B channel 5                */
+					/* channel 5 (read)		   */
+#define _DBSA5		_DBSA (5)	/* DMA Buffer Start address reg. A */
+					/* channel 5			   */
+#define _DBTA5		_DBTA (5)	/* DMA Buffer Transfer count	   */
+					/* reg. A channel 5		   */
+#define _DBSB5		_DBSB (5)	/* DMA Buffer Start address reg. B */
+					/* channel 5			   */
+#define _DBTB5		_DBTB (5)	/* DMA Buffer Transfer count	   */
+					/* reg. B channel 5		   */
 
 #if LANGUAGE == C
 
-#define DDAR0   	        	/* DMA Device Address Reg.         */ \
-					/* channel 0                       */ \
+#define DDAR0				/* DMA Device Address Reg.	   */ \
+					/* channel 0			   */ \
 			(*((volatile Word *) io_p2v (_DDAR0)))
-#define SetDCSR0	        	/* Set DMA Control & Status Reg.   */ \
-					/* channel 0 (write)               */ \
+#define SetDCSR0			/* Set DMA Control & Status Reg.   */ \
+					/* channel 0 (write)		   */ \
 			(*((volatile Word *) io_p2v (_SetDCSR0)))
-#define ClrDCSR0	        	/* Clear DMA Control & Status Reg. */ \
-					/* channel 0 (write)               */ \
+#define ClrDCSR0			/* Clear DMA Control & Status Reg. */ \
+					/* channel 0 (write)		   */ \
 			(*((volatile Word *) io_p2v (_ClrDCSR0)))
-#define RdDCSR0 	        	/* Read DMA Control & Status Reg.  */ \
-					/* channel 0 (read)                */ \
+#define RdDCSR0				/* Read DMA Control & Status Reg.  */ \
+					/* channel 0 (read)		   */ \
 			(*((volatile Word *) io_p2v (_RdDCSR0)))
-#define DBSA0   	        	/* DMA Buffer Start address reg. A */ \
-					/* channel 0                       */ \
+#define DBSA0				/* DMA Buffer Start address reg. A */ \
+					/* channel 0			   */ \
 			(*((volatile Address *) io_p2v (_DBSA0)))
-#define DBTA0   	        	/* DMA Buffer Transfer count       */ \
-					/* reg. A channel 0                */ \
+#define DBTA0				/* DMA Buffer Transfer count	   */ \
+					/* reg. A channel 0		   */ \
 			(*((volatile Word *) io_p2v (_DBTA0)))
-#define DBSB0   	        	/* DMA Buffer Start address reg. B */ \
-					/* channel 0                       */ \
+#define DBSB0				/* DMA Buffer Start address reg. B */ \
+					/* channel 0			   */ \
 			(*((volatile Address *) io_p2v (_DBSB0)))
-#define DBTB0   	        	/* DMA Buffer Transfer count       */ \
-					/* reg. B channel 0                */ \
+#define DBTB0				/* DMA Buffer Transfer count	   */ \
+					/* reg. B channel 0		   */ \
 			(*((volatile Word *) io_p2v (_DBTB0)))
 
-#define DDAR1   	        	/* DMA Device Address Reg.         */ \
-					/* channel 1                       */ \
+#define DDAR1				/* DMA Device Address Reg.	   */ \
+					/* channel 1			   */ \
 			(*((volatile Word *) io_p2v (_DDAR1)))
-#define SetDCSR1	        	/* Set DMA Control & Status Reg.   */ \
-					/* channel 1 (write)               */ \
+#define SetDCSR1			/* Set DMA Control & Status Reg.   */ \
+					/* channel 1 (write)		   */ \
 			(*((volatile Word *) io_p2v (_SetDCSR1)))
-#define ClrDCSR1	        	/* Clear DMA Control & Status Reg. */ \
-					/* channel 1 (write)               */ \
+#define ClrDCSR1			/* Clear DMA Control & Status Reg. */ \
+					/* channel 1 (write)		   */ \
 			(*((volatile Word *) io_p2v (_ClrDCSR1)))
-#define RdDCSR1 	        	/* Read DMA Control & Status Reg.  */ \
-					/* channel 1 (read)                */ \
+#define RdDCSR1				/* Read DMA Control & Status Reg.  */ \
+					/* channel 1 (read)		   */ \
 			(*((volatile Word *) io_p2v (_RdDCSR1)))
-#define DBSA1   	        	/* DMA Buffer Start address reg. A */ \
-					/* channel 1                       */ \
+#define DBSA1				/* DMA Buffer Start address reg. A */ \
+					/* channel 1			   */ \
 			(*((volatile Address *) io_p2v (_DBSA1)))
-#define DBTA1   	        	/* DMA Buffer Transfer count       */ \
-					/* reg. A channel 1                */ \
+#define DBTA1				/* DMA Buffer Transfer count	   */ \
+					/* reg. A channel 1		   */ \
 			(*((volatile Word *) io_p2v (_DBTA1)))
-#define DBSB1   	        	/* DMA Buffer Start address reg. B */ \
-					/* channel 1                       */ \
+#define DBSB1				/* DMA Buffer Start address reg. B */ \
+					/* channel 1			   */ \
 			(*((volatile Address *) io_p2v (_DBSB1)))
-#define DBTB1   	        	/* DMA Buffer Transfer count       */ \
-					/* reg. B channel 1                */ \
+#define DBTB1				/* DMA Buffer Transfer count	   */ \
+					/* reg. B channel 1		   */ \
 			(*((volatile Word *) io_p2v (_DBTB1)))
 
-#define DDAR2   	        	/* DMA Device Address Reg.         */ \
-					/* channel 2                       */ \
+#define DDAR2				/* DMA Device Address Reg.	   */ \
+					/* channel 2			   */ \
 			(*((volatile Word *) io_p2v (_DDAR2)))
-#define SetDCSR2	        	/* Set DMA Control & Status Reg.   */ \
-					/* channel 2 (write)               */ \
+#define SetDCSR2			/* Set DMA Control & Status Reg.   */ \
+					/* channel 2 (write)		   */ \
 			(*((volatile Word *) io_p2v (_SetDCSR2)))
-#define ClrDCSR2	        	/* Clear DMA Control & Status Reg. */ \
-					/* channel 2 (write)               */ \
+#define ClrDCSR2			/* Clear DMA Control & Status Reg. */ \
+					/* channel 2 (write)		   */ \
 			(*((volatile Word *) io_p2v (_ClrDCSR2)))
-#define RdDCSR2 	        	/* Read DMA Control & Status Reg.  */ \
-					/* channel 2 (read)                */ \
+#define RdDCSR2				/* Read DMA Control & Status Reg.  */ \
+					/* channel 2 (read)		   */ \
 			(*((volatile Word *) io_p2v (_RdDCSR2)))
-#define DBSA2   	        	/* DMA Buffer Start address reg. A */ \
-					/* channel 2                       */ \
+#define DBSA2				/* DMA Buffer Start address reg. A */ \
+					/* channel 2			   */ \
 			(*((volatile Address *) io_p2v (_DBSA2)))
-#define DBTA2   	        	/* DMA Buffer Transfer count       */ \
-					/* reg. A channel 2                */ \
+#define DBTA2				/* DMA Buffer Transfer count	   */ \
+					/* reg. A channel 2		   */ \
 			(*((volatile Word *) io_p2v (_DBTA2)))
-#define DBSB2   	        	/* DMA Buffer Start address reg. B */ \
-					/* channel 2                       */ \
+#define DBSB2				/* DMA Buffer Start address reg. B */ \
+					/* channel 2			   */ \
 			(*((volatile Address *) io_p2v (_DBSB2)))
-#define DBTB2   	        	/* DMA Buffer Transfer count       */ \
-					/* reg. B channel 2                */ \
+#define DBTB2				/* DMA Buffer Transfer count	   */ \
+					/* reg. B channel 2		   */ \
 			(*((volatile Word *) io_p2v (_DBTB2)))
 
-#define DDAR3   	        	/* DMA Device Address Reg.         */ \
-					/* channel 3                       */ \
+#define DDAR3				/* DMA Device Address Reg.	   */ \
+					/* channel 3			   */ \
 			(*((volatile Word *) io_p2v (_DDAR3)))
-#define SetDCSR3	        	/* Set DMA Control & Status Reg.   */ \
-					/* channel 3 (write)               */ \
+#define SetDCSR3			/* Set DMA Control & Status Reg.   */ \
+					/* channel 3 (write)		   */ \
 			(*((volatile Word *) io_p2v (_SetDCSR3)))
-#define ClrDCSR3	        	/* Clear DMA Control & Status Reg. */ \
-					/* channel 3 (write)               */ \
+#define ClrDCSR3			/* Clear DMA Control & Status Reg. */ \
+					/* channel 3 (write)		   */ \
 			(*((volatile Word *) io_p2v (_ClrDCSR3)))
-#define RdDCSR3 	        	/* Read DMA Control & Status Reg.  */ \
-					/* channel 3 (read)                */ \
+#define RdDCSR3				/* Read DMA Control & Status Reg.  */ \
+					/* channel 3 (read)		   */ \
 			(*((volatile Word *) io_p2v (_RdDCSR3)))
-#define DBSA3   	        	/* DMA Buffer Start address reg. A */ \
-					/* channel 3                       */ \
+#define DBSA3				/* DMA Buffer Start address reg. A */ \
+					/* channel 3			   */ \
 			(*((volatile Address *) io_p2v (_DBSA3)))
-#define DBTA3   	        	/* DMA Buffer Transfer count       */ \
-					/* reg. A channel 3                */ \
+#define DBTA3				/* DMA Buffer Transfer count	   */ \
+					/* reg. A channel 3		   */ \
 			(*((volatile Word *) io_p2v (_DBTA3)))
-#define DBSB3   	        	/* DMA Buffer Start address reg. B */ \
-					/* channel 3                       */ \
+#define DBSB3				/* DMA Buffer Start address reg. B */ \
+					/* channel 3			   */ \
 			(*((volatile Address *) io_p2v (_DBSB3)))
-#define DBTB3   	        	/* DMA Buffer Transfer count       */ \
-					/* reg. B channel 3                */ \
+#define DBTB3				/* DMA Buffer Transfer count	   */ \
+					/* reg. B channel 3		   */ \
 			(*((volatile Word *) io_p2v (_DBTB3)))
 
-#define DDAR4   	        	/* DMA Device Address Reg.         */ \
-					/* channel 4                       */ \
+#define DDAR4				/* DMA Device Address Reg.	   */ \
+					/* channel 4			   */ \
 			(*((volatile Word *) io_p2v (_DDAR4)))
-#define SetDCSR4	        	/* Set DMA Control & Status Reg.   */ \
-					/* channel 4 (write)               */ \
+#define SetDCSR4			/* Set DMA Control & Status Reg.   */ \
+					/* channel 4 (write)		   */ \
 			(*((volatile Word *) io_p2v (_SetDCSR4)))
-#define ClrDCSR4	        	/* Clear DMA Control & Status Reg. */ \
-					/* channel 4 (write)               */ \
+#define ClrDCSR4			/* Clear DMA Control & Status Reg. */ \
+					/* channel 4 (write)		   */ \
 			(*((volatile Word *) io_p2v (_ClrDCSR4)))
-#define RdDCSR4 	        	/* Read DMA Control & Status Reg.  */ \
-					/* channel 4 (read)                */ \
+#define RdDCSR4				/* Read DMA Control & Status Reg.  */ \
+					/* channel 4 (read)		   */ \
 			(*((volatile Word *) io_p2v (_RdDCSR4)))
-#define DBSA4   	        	/* DMA Buffer Start address reg. A */ \
-					/* channel 4                       */ \
+#define DBSA4				/* DMA Buffer Start address reg. A */ \
+					/* channel 4			   */ \
 			(*((volatile Address *) io_p2v (_DBSA4)))
-#define DBTA4   	        	/* DMA Buffer Transfer count       */ \
-					/* reg. A channel 4                */ \
+#define DBTA4				/* DMA Buffer Transfer count	   */ \
+					/* reg. A channel 4		   */ \
 			(*((volatile Word *) io_p2v (_DBTA4)))
-#define DBSB4   	        	/* DMA Buffer Start address reg. B */ \
-					/* channel 4                       */ \
+#define DBSB4				/* DMA Buffer Start address reg. B */ \
+					/* channel 4			   */ \
 			(*((volatile Address *) io_p2v (_DBSB4)))
-#define DBTB4   	        	/* DMA Buffer Transfer count       */ \
-					/* reg. B channel 4                */ \
+#define DBTB4				/* DMA Buffer Transfer count	   */ \
+					/* reg. B channel 4		   */ \
 			(*((volatile Word *) io_p2v (_DBTB4)))
 
-#define DDAR5   	        	/* DMA Device Address Reg.         */ \
-					/* channel 5                       */ \
+#define DDAR5				/* DMA Device Address Reg.	   */ \
+					/* channel 5			   */ \
 			(*((volatile Word *) io_p2v (_DDAR5)))
-#define SetDCSR5	        	/* Set DMA Control & Status Reg.   */ \
-					/* channel 5 (write)               */ \
+#define SetDCSR5			/* Set DMA Control & Status Reg.   */ \
+					/* channel 5 (write)		   */ \
 			(*((volatile Word *) io_p2v (_SetDCSR5)))
-#define ClrDCSR5	        	/* Clear DMA Control & Status Reg. */ \
-					/* channel 5 (write)               */ \
+#define ClrDCSR5			/* Clear DMA Control & Status Reg. */ \
+					/* channel 5 (write)		   */ \
 			(*((volatile Word *) io_p2v (_ClrDCSR5)))
-#define RdDCSR5 	        	/* Read DMA Control & Status Reg.  */ \
-					/* channel 5 (read)                */ \
+#define RdDCSR5				/* Read DMA Control & Status Reg.  */ \
+					/* channel 5 (read)		   */ \
 			(*((volatile Word *) io_p2v (_RdDCSR5)))
-#define DBSA5   	        	/* DMA Buffer Start address reg. A */ \
-					/* channel 5                       */ \
+#define DBSA5				/* DMA Buffer Start address reg. A */ \
+					/* channel 5			   */ \
 			(*((volatile Address *) io_p2v (_DBSA5)))
-#define DBTA5   	        	/* DMA Buffer Transfer count       */ \
-					/* reg. A channel 5                */ \
+#define DBTA5				/* DMA Buffer Transfer count	   */ \
+					/* reg. A channel 5		   */ \
 			(*((volatile Word *) io_p2v (_DBTA5)))
-#define DBSB5   	        	/* DMA Buffer Start address reg. B */ \
-					/* channel 5                       */ \
+#define DBSB5				/* DMA Buffer Start address reg. B */ \
+					/* channel 5			   */ \
 			(*((volatile Address *) io_p2v (_DBSB5)))
-#define DBTB5   	        	/* DMA Buffer Transfer count       */ \
-					/* reg. B channel 5                */ \
+#define DBTB5				/* DMA Buffer Transfer count	   */ \
+					/* reg. B channel 5		   */ \
 			(*((volatile Word *) io_p2v (_DBTB5)))
 
 #endif /* LANGUAGE == C */
 
-#define DDAR_RW 	0x00000001	/* device data Read/Write          */
-#define DDAR_DevWr	(DDAR_RW*0)	/*  Device data Write              */
-					/*  (memory -> device)             */
-#define DDAR_DevRd	(DDAR_RW*1)	/*  Device data Read               */
-					/*  (device -> memory)             */
-#define DDAR_E  	0x00000002	/* big/little Endian device        */
-#define DDAR_LtlEnd	(DDAR_E*0)	/*  Little Endian device           */
-#define DDAR_BigEnd	(DDAR_E*1)	/*  Big Endian device              */
-#define DDAR_BS 	0x00000004	/* device Burst Size               */
-#define DDAR_Brst4	(DDAR_BS*0)	/*  Burst-of-4 device              */
-#define DDAR_Brst8	(DDAR_BS*1)	/*  Burst-of-8 device              */
-#define DDAR_DW 	0x00000008	/* device Data Width               */
-#define DDAR_8BitDev	(DDAR_DW*0)	/*  8-Bit Device                   */
-#define DDAR_16BitDev	(DDAR_DW*1)	/*  16-Bit Device                  */
-#define DDAR_DS 	Fld (4, 4)	/* Device Select                   */
-#define DDAR_Ser0UDCTr	        	/*  Ser. port 0 UDC Transmit       */ \
+#define DDAR_RW		0x00000001	/* device data Read/Write	   */
+#define DDAR_DevWr	(DDAR_RW*0)	/*  Device data Write		   */
+					/*  (memory -> device)		   */
+#define DDAR_DevRd	(DDAR_RW*1)	/*  Device data Read		   */
+					/*  (device -> memory)		   */
+#define DDAR_E		0x00000002	/* big/little Endian device	   */
+#define DDAR_LtlEnd	(DDAR_E*0)	/*  Little Endian device	   */
+#define DDAR_BigEnd	(DDAR_E*1)	/*  Big Endian device		   */
+#define DDAR_BS		0x00000004	/* device Burst Size		   */
+#define DDAR_Brst4	(DDAR_BS*0)	/*  Burst-of-4 device		   */
+#define DDAR_Brst8	(DDAR_BS*1)	/*  Burst-of-8 device		   */
+#define DDAR_DW		0x00000008	/* device Data Width		   */
+#define DDAR_8BitDev	(DDAR_DW*0)	/*  8-Bit Device		   */
+#define DDAR_16BitDev	(DDAR_DW*1)	/*  16-Bit Device		   */
+#define DDAR_DS		Fld (4, 4)	/* Device Select		   */
+#define DDAR_Ser0UDCTr			/*  Ser. port 0 UDC Transmit	   */ \
 			(0x0 << FShft (DDAR_DS))
-#define DDAR_Ser0UDCRc	        	/*  Ser. port 0 UDC Receive        */ \
+#define DDAR_Ser0UDCRc			/*  Ser. port 0 UDC Receive	   */ \
 			(0x1 << FShft (DDAR_DS))
-#define DDAR_Ser1SDLCTr	        	/*  Ser. port 1 SDLC Transmit      */ \
+#define DDAR_Ser1SDLCTr			/*  Ser. port 1 SDLC Transmit	   */ \
 			(0x2 << FShft (DDAR_DS))
-#define DDAR_Ser1SDLCRc	        	/*  Ser. port 1 SDLC Receive       */ \
+#define DDAR_Ser1SDLCRc			/*  Ser. port 1 SDLC Receive	   */ \
 			(0x3 << FShft (DDAR_DS))
-#define DDAR_Ser1UARTTr	        	/*  Ser. port 1 UART Transmit      */ \
+#define DDAR_Ser1UARTTr			/*  Ser. port 1 UART Transmit	   */ \
 			(0x4 << FShft (DDAR_DS))
-#define DDAR_Ser1UARTRc	        	/*  Ser. port 1 UART Receive       */ \
+#define DDAR_Ser1UARTRc			/*  Ser. port 1 UART Receive	   */ \
 			(0x5 << FShft (DDAR_DS))
-#define DDAR_Ser2ICPTr	        	/*  Ser. port 2 ICP Transmit       */ \
+#define DDAR_Ser2ICPTr			/*  Ser. port 2 ICP Transmit	   */ \
 			(0x6 << FShft (DDAR_DS))
-#define DDAR_Ser2ICPRc	        	/*  Ser. port 2 ICP Receive        */ \
+#define DDAR_Ser2ICPRc			/*  Ser. port 2 ICP Receive	   */ \
 			(0x7 << FShft (DDAR_DS))
-#define DDAR_Ser3UARTTr	        	/*  Ser. port 3 UART Transmit      */ \
+#define DDAR_Ser3UARTTr			/*  Ser. port 3 UART Transmit	   */ \
 			(0x8 << FShft (DDAR_DS))
-#define DDAR_Ser3UARTRc	        	/*  Ser. port 3 UART Receive       */ \
+#define DDAR_Ser3UARTRc			/*  Ser. port 3 UART Receive	   */ \
 			(0x9 << FShft (DDAR_DS))
-#define DDAR_Ser4MCP0Tr	        	/*  Ser. port 4 MCP 0 Transmit     */ \
-					/*  (audio)                        */ \
+#define DDAR_Ser4MCP0Tr			/*  Ser. port 4 MCP 0 Transmit	   */ \
+					/*  (audio)			   */ \
 			(0xA << FShft (DDAR_DS))
-#define DDAR_Ser4MCP0Rc	        	/*  Ser. port 4 MCP 0 Receive      */ \
-					/*  (audio)                        */ \
+#define DDAR_Ser4MCP0Rc			/*  Ser. port 4 MCP 0 Receive	   */ \
+					/*  (audio)			   */ \
 			(0xB << FShft (DDAR_DS))
-#define DDAR_Ser4MCP1Tr	        	/*  Ser. port 4 MCP 1 Transmit     */ \
-					/*  (telecom)                      */ \
+#define DDAR_Ser4MCP1Tr			/*  Ser. port 4 MCP 1 Transmit	   */ \
+					/*  (telecom)			   */ \
 			(0xC << FShft (DDAR_DS))
-#define DDAR_Ser4MCP1Rc	        	/*  Ser. port 4 MCP 1 Receive      */ \
-					/*  (telecom)                      */ \
+#define DDAR_Ser4MCP1Rc			/*  Ser. port 4 MCP 1 Receive	   */ \
+					/*  (telecom)			   */ \
 			(0xD << FShft (DDAR_DS))
-#define DDAR_Ser4SSPTr	        	/*  Ser. port 4 SSP Transmit       */ \
+#define DDAR_Ser4SSPTr			/*  Ser. port 4 SSP Transmit	   */ \
 			(0xE << FShft (DDAR_DS))
-#define DDAR_Ser4SSPRc	        	/*  Ser. port 4 SSP Receive        */ \
+#define DDAR_Ser4SSPRc			/*  Ser. port 4 SSP Receive	   */ \
 			(0xF << FShft (DDAR_DS))
-#define DDAR_DA 	Fld (24, 8)	/* Device Address                  */
-#define DDAR_DevAdd(Add)        	/*  Device Address                 */ \
+#define DDAR_DA		Fld (24, 8)	/* Device Address		   */
+#define DDAR_DevAdd(Add)		/*  Device Address		   */ \
 			(((Add) & 0xF0000000) | \
 			 (((Add) & 0X003FFFFC) << (FShft (DDAR_DA) - 2)))
-#define DDAR_Ser0UDCWr	        	/* Ser. port 0 UDC Write           */ \
+#define DDAR_Ser0UDCWr			/* Ser. port 0 UDC Write	   */ \
 			(DDAR_DevWr + DDAR_Brst8 + DDAR_8BitDev + \
 			 DDAR_Ser0UDCTr + DDAR_DevAdd (_Ser0UDCDR))
-#define DDAR_Ser0UDCRd	        	/* Ser. port 0 UDC Read            */ \
+#define DDAR_Ser0UDCRd			/* Ser. port 0 UDC Read		   */ \
 			(DDAR_DevRd + DDAR_Brst8 + DDAR_8BitDev + \
 			 DDAR_Ser0UDCRc + DDAR_DevAdd (_Ser0UDCDR))
-#define DDAR_Ser1UARTWr	        	/* Ser. port 1 UART Write          */ \
+#define DDAR_Ser1UARTWr			/* Ser. port 1 UART Write	   */ \
 			(DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \
 			 DDAR_Ser1UARTTr + DDAR_DevAdd (_Ser1UTDR))
-#define DDAR_Ser1UARTRd	        	/* Ser. port 1 UART Read           */ \
+#define DDAR_Ser1UARTRd			/* Ser. port 1 UART Read	   */ \
 			(DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \
 			 DDAR_Ser1UARTRc + DDAR_DevAdd (_Ser1UTDR))
-#define DDAR_Ser1SDLCWr	        	/* Ser. port 1 SDLC Write          */ \
+#define DDAR_Ser1SDLCWr			/* Ser. port 1 SDLC Write	   */ \
 			(DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \
 			 DDAR_Ser1SDLCTr + DDAR_DevAdd (_Ser1SDDR))
-#define DDAR_Ser1SDLCRd	        	/* Ser. port 1 SDLC Read           */ \
+#define DDAR_Ser1SDLCRd			/* Ser. port 1 SDLC Read	   */ \
 			(DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \
 			 DDAR_Ser1SDLCRc + DDAR_DevAdd (_Ser1SDDR))
-#define DDAR_Ser2UARTWr	        	/* Ser. port 2 UART Write          */ \
+#define DDAR_Ser2UARTWr			/* Ser. port 2 UART Write	   */ \
 			(DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \
 			 DDAR_Ser2ICPTr + DDAR_DevAdd (_Ser2UTDR))
-#define DDAR_Ser2UARTRd	        	/* Ser. port 2 UART Read           */ \
+#define DDAR_Ser2UARTRd			/* Ser. port 2 UART Read	   */ \
 			(DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \
 			 DDAR_Ser2ICPRc + DDAR_DevAdd (_Ser2UTDR))
-#define DDAR_Ser2HSSPWr	        	/* Ser. port 2 HSSP Write          */ \
+#define DDAR_Ser2HSSPWr			/* Ser. port 2 HSSP Write	   */ \
 			(DDAR_DevWr + DDAR_Brst8 + DDAR_8BitDev + \
 			 DDAR_Ser2ICPTr + DDAR_DevAdd (_Ser2HSDR))
-#define DDAR_Ser2HSSPRd	        	/* Ser. port 2 HSSP Read           */ \
+#define DDAR_Ser2HSSPRd			/* Ser. port 2 HSSP Read	   */ \
 			(DDAR_DevRd + DDAR_Brst8 + DDAR_8BitDev + \
 			 DDAR_Ser2ICPRc + DDAR_DevAdd (_Ser2HSDR))
-#define DDAR_Ser3UARTWr	        	/* Ser. port 3 UART Write          */ \
+#define DDAR_Ser3UARTWr			/* Ser. port 3 UART Write	   */ \
 			(DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \
 			 DDAR_Ser3UARTTr + DDAR_DevAdd (_Ser3UTDR))
-#define DDAR_Ser3UARTRd	        	/* Ser. port 3 UART Read           */ \
+#define DDAR_Ser3UARTRd			/* Ser. port 3 UART Read	   */ \
 			(DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \
 			 DDAR_Ser3UARTRc + DDAR_DevAdd (_Ser3UTDR))
-#define DDAR_Ser4MCP0Wr	        	/* Ser. port 4 MCP 0 Write (audio) */ \
+#define DDAR_Ser4MCP0Wr			/* Ser. port 4 MCP 0 Write (audio) */ \
 			(DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \
 			 DDAR_Ser4MCP0Tr + DDAR_DevAdd (_Ser4MCDR0))
-#define DDAR_Ser4MCP0Rd	        	/* Ser. port 4 MCP 0 Read (audio)  */ \
+#define DDAR_Ser4MCP0Rd			/* Ser. port 4 MCP 0 Read (audio)  */ \
 			(DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \
 			 DDAR_Ser4MCP0Rc + DDAR_DevAdd (_Ser4MCDR0))
-#define DDAR_Ser4MCP1Wr	        	/* Ser. port 4 MCP 1 Write         */ \
-					/* (telecom)                       */ \
+#define DDAR_Ser4MCP1Wr			/* Ser. port 4 MCP 1 Write	   */ \
+					/* (telecom)			   */ \
 			(DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \
 			 DDAR_Ser4MCP1Tr + DDAR_DevAdd (_Ser4MCDR1))
-#define DDAR_Ser4MCP1Rd	        	/* Ser. port 4 MCP 1 Read          */ \
-					/* (telecom)                       */ \
+#define DDAR_Ser4MCP1Rd			/* Ser. port 4 MCP 1 Read	   */ \
+					/* (telecom)			   */ \
 			(DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \
 			 DDAR_Ser4MCP1Rc + DDAR_DevAdd (_Ser4MCDR1))
-#define DDAR_Ser4SSPWr	        	/* Ser. port 4 SSP Write (16 bits) */ \
+#define DDAR_Ser4SSPWr			/* Ser. port 4 SSP Write (16 bits) */ \
 			(DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \
 			 DDAR_Ser4SSPTr + DDAR_DevAdd (_Ser4SSDR))
-#define DDAR_Ser4SSPRd	        	/* Ser. port 4 SSP Read (16 bits)  */ \
+#define DDAR_Ser4SSPRd			/* Ser. port 4 SSP Read (16 bits)  */ \
 			(DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \
 			 DDAR_Ser4SSPRc + DDAR_DevAdd (_Ser4SSDR))
 
-#define DCSR_RUN	0x00000001	/* DMA RUNing                      */
-#define DCSR_IE 	0x00000002	/* DMA Interrupt Enable            */
-#define DCSR_ERROR	0x00000004	/* DMA ERROR                       */
-#define DCSR_DONEA	0x00000008	/* DONE DMA transfer buffer A      */
+#define DCSR_RUN	0x00000001	/* DMA RUNing			   */
+#define DCSR_IE		0x00000002	/* DMA Interrupt Enable		   */
+#define DCSR_ERROR	0x00000004	/* DMA ERROR			   */
+#define DCSR_DONEA	0x00000008	/* DONE DMA transfer buffer A	   */
 #define DCSR_STRTA	0x00000010	/* STaRTed DMA transfer buffer A   */
-#define DCSR_DONEB	0x00000020	/* DONE DMA transfer buffer B      */
+#define DCSR_DONEB	0x00000020	/* DONE DMA transfer buffer B	   */
 #define DCSR_STRTB	0x00000040	/* STaRTed DMA transfer buffer B   */
-#define DCSR_BIU	0x00000080	/* DMA Buffer In Use               */
-#define DCSR_BufA	(DCSR_BIU*0)	/*  DMA Buffer A in use            */
-#define DCSR_BufB	(DCSR_BIU*1)	/*  DMA Buffer B in use            */
+#define DCSR_BIU	0x00000080	/* DMA Buffer In Use		   */
+#define DCSR_BufA	(DCSR_BIU*0)	/*  DMA Buffer A in use		   */
+#define DCSR_BufB	(DCSR_BIU*1)	/*  DMA Buffer B in use		   */
 
-#define DBT_TC  	Fld (13, 0)	/* Transfer Count                  */
-#define DBTA_TCA	DBT_TC  	/* Transfer Count buffer A         */
-#define DBTB_TCB	DBT_TC  	/* Transfer Count buffer B         */
+#define DBT_TC		Fld (13, 0)	/* Transfer Count		   */
+#define DBTA_TCA	DBT_TC		/* Transfer Count buffer A	   */
+#define DBTB_TCB	DBT_TC		/* Transfer Count buffer B	   */
 
 
 /*
  * Liquid Crystal Display (LCD) control registers
  *
  * Registers
- *    LCCR0     	Liquid Crystal Display (LCD) Control Register 0
- *              	(read/write).
- *              	[Bits LDM, BAM, and ERM are only implemented in
- *              	versions 2.0 (rev. = 8) and higher of the StrongARM
- *              	SA-1100.]
- *    LCSR      	Liquid Crystal Display (LCD) Status Register
- *              	(read/write).
- *              	[Bit LDD can be only read in versions 1.0 (rev. = 1)
- *              	and 1.1 (rev. = 2) of the StrongARM SA-1100, it can be
- *              	read and written (cleared) in versions 2.0 (rev. = 8)
- *              	and higher.]
- *    DBAR1     	Liquid Crystal Display (LCD) Direct Memory Access
- *              	(DMA) Base Address Register channel 1 (read/write).
- *    DCAR1     	Liquid Crystal Display (LCD) Direct Memory Access
- *              	(DMA) Current Address Register channel 1 (read).
- *    DBAR2     	Liquid Crystal Display (LCD) Direct Memory Access
- *              	(DMA) Base Address Register channel 2 (read/write).
- *    DCAR2     	Liquid Crystal Display (LCD) Direct Memory Access
- *              	(DMA) Current Address Register channel 2 (read).
- *    LCCR1     	Liquid Crystal Display (LCD) Control Register 1
- *              	(read/write).
- *              	[The LCCR1 register can be only written in
- *              	versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the
- *              	StrongARM SA-1100, it can be written and read in
- *              	versions 2.0 (rev. = 8) and higher.]
- *    LCCR2     	Liquid Crystal Display (LCD) Control Register 2
- *              	(read/write).
- *              	[The LCCR1 register can be only written in
- *              	versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the
- *              	StrongARM SA-1100, it can be written and read in
- *              	versions 2.0 (rev. = 8) and higher.]
- *    LCCR3     	Liquid Crystal Display (LCD) Control Register 3
- *              	(read/write).
- *              	[The LCCR1 register can be only written in
- *              	versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the
- *              	StrongARM SA-1100, it can be written and read in
- *              	versions 2.0 (rev. = 8) and higher. Bit PCP is only
- *              	implemented in versions 2.0 (rev. = 8) and higher of
- *              	the StrongARM SA-1100.]
+ *    LCCR0		Liquid Crystal Display (LCD) Control Register 0
+ *			(read/write).
+ *			[Bits LDM, BAM, and ERM are only implemented in
+ *			versions 2.0 (rev. = 8) and higher of the StrongARM
+ *			SA-1100.]
+ *    LCSR		Liquid Crystal Display (LCD) Status Register
+ *			(read/write).
+ *			[Bit LDD can be only read in versions 1.0 (rev. = 1)
+ *			and 1.1 (rev. = 2) of the StrongARM SA-1100, it can be
+ *			read and written (cleared) in versions 2.0 (rev. = 8)
+ *			and higher.]
+ *    DBAR1		Liquid Crystal Display (LCD) Direct Memory Access
+ *			(DMA) Base Address Register channel 1 (read/write).
+ *    DCAR1		Liquid Crystal Display (LCD) Direct Memory Access
+ *			(DMA) Current Address Register channel 1 (read).
+ *    DBAR2		Liquid Crystal Display (LCD) Direct Memory Access
+ *			(DMA) Base Address Register channel 2 (read/write).
+ *    DCAR2		Liquid Crystal Display (LCD) Direct Memory Access
+ *			(DMA) Current Address Register channel 2 (read).
+ *    LCCR1		Liquid Crystal Display (LCD) Control Register 1
+ *			(read/write).
+ *			[The LCCR1 register can be only written in
+ *			versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the
+ *			StrongARM SA-1100, it can be written and read in
+ *			versions 2.0 (rev. = 8) and higher.]
+ *    LCCR2		Liquid Crystal Display (LCD) Control Register 2
+ *			(read/write).
+ *			[The LCCR1 register can be only written in
+ *			versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the
+ *			StrongARM SA-1100, it can be written and read in
+ *			versions 2.0 (rev. = 8) and higher.]
+ *    LCCR3		Liquid Crystal Display (LCD) Control Register 3
+ *			(read/write).
+ *			[The LCCR1 register can be only written in
+ *			versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the
+ *			StrongARM SA-1100, it can be written and read in
+ *			versions 2.0 (rev. = 8) and higher. Bit PCP is only
+ *			implemented in versions 2.0 (rev. = 8) and higher of
+ *			the StrongARM SA-1100.]
  *
  * Clocks
  *    fcpu, Tcpu	Frequency, period of the CPU core clock (CCLK).
  *    fmem, Tmem	Frequency, period of the memory clock (fmem = fcpu/2).
  *    fpix, Tpix	Frequency, period of the pixel clock.
- *    fln, Tln  	Frequency, period of the line clock.
- *    fac, Tac  	Frequency, period of the AC bias clock.
+ *    fln, Tln		Frequency, period of the line clock.
+ *    fac, Tac		Frequency, period of the AC bias clock.
  */
 
-#define LCD_PEntrySp	2       	/* LCD Palette Entry Space [byte]  */
-#define LCD_4BitPSp	        	/* LCD 4-Bit pixel Palette Space   */ \
-					/* [byte]                          */ \
+#define LCD_PEntrySp	2		/* LCD Palette Entry Space [byte]  */
+#define LCD_4BitPSp			/* LCD 4-Bit pixel Palette Space   */ \
+					/* [byte]			   */ \
 			(16*LCD_PEntrySp)
-#define LCD_8BitPSp	        	/* LCD 8-Bit pixel Palette Space   */ \
-					/* [byte]                          */ \
+#define LCD_8BitPSp			/* LCD 8-Bit pixel Palette Space   */ \
+					/* [byte]			   */ \
 			(256*LCD_PEntrySp)
-#define LCD_12_16BitPSp	        	/* LCD 12/16-Bit pixel             */ \
-					/* dummy-Palette Space [byte]      */ \
+#define LCD_12_16BitPSp			/* LCD 12/16-Bit pixel		   */ \
+					/* dummy-Palette Space [byte]	   */ \
 			(16*LCD_PEntrySp)
 
 #define LCD_PGrey	Fld (4, 0)	/* LCD Palette entry Grey value    */
 #define LCD_PBlue	Fld (4, 0)	/* LCD Palette entry Blue value    */
 #define LCD_PGreen	Fld (4, 4)	/* LCD Palette entry Green value   */
-#define LCD_PRed	Fld (4, 8)	/* LCD Palette entry Red value     */
-#define LCD_PBS 	Fld (2, 12)	/* LCD Pixel Bit Size              */
-#define LCD_4Bit	        	/*  LCD 4-Bit pixel mode           */ \
+#define LCD_PRed	Fld (4, 8)	/* LCD Palette entry Red value	   */
+#define LCD_PBS		Fld (2, 12)	/* LCD Pixel Bit Size		   */
+#define LCD_4Bit			/*  LCD 4-Bit pixel mode	   */ \
 			(0 << FShft (LCD_PBS))
-#define LCD_8Bit	        	/*  LCD 8-Bit pixel mode           */ \
+#define LCD_8Bit			/*  LCD 8-Bit pixel mode	   */ \
 			(1 << FShft (LCD_PBS))
-#define LCD_12_16Bit	        	/*  LCD 12/16-Bit pixel mode       */ \
+#define LCD_12_16Bit			/*  LCD 12/16-Bit pixel mode	   */ \
 			(2 << FShft (LCD_PBS))
 
-#define LCD_Int0_0	0x0     	/* LCD Intensity =   0.0% =  0     */
-#define LCD_Int11_1	0x1     	/* LCD Intensity =  11.1% =  1/9   */
-#define LCD_Int20_0	0x2     	/* LCD Intensity =  20.0% =  1/5   */
-#define LCD_Int26_7	0x3     	/* LCD Intensity =  26.7% =  4/15  */
-#define LCD_Int33_3	0x4     	/* LCD Intensity =  33.3% =  3/9   */
-#define LCD_Int40_0	0x5     	/* LCD Intensity =  40.0% =  2/5   */
-#define LCD_Int44_4	0x6     	/* LCD Intensity =  44.4% =  4/9   */
-#define LCD_Int50_0	0x7     	/* LCD Intensity =  50.0% =  1/2   */
-#define LCD_Int55_6	0x8     	/* LCD Intensity =  55.6% =  5/9   */
-#define LCD_Int60_0	0x9     	/* LCD Intensity =  60.0% =  3/5   */
-#define LCD_Int66_7	0xA     	/* LCD Intensity =  66.7% =  6/9   */
-#define LCD_Int73_3	0xB     	/* LCD Intensity =  73.3% = 11/15  */
-#define LCD_Int80_0	0xC     	/* LCD Intensity =  80.0% =  4/5   */
-#define LCD_Int88_9	0xD     	/* LCD Intensity =  88.9% =  8/9   */
-#define LCD_Int100_0	0xE     	/* LCD Intensity = 100.0% =  1     */
-#define LCD_Int100_0A	0xF     	/* LCD Intensity = 100.0% =  1     */
-					/* (Alternative)                   */
-
-#define _LCCR0  	0xB0100000	/* LCD Control Reg. 0              */
-#define _LCSR   	0xB0100004	/* LCD Status Reg.                 */
-#define _DBAR1  	0xB0100010	/* LCD DMA Base Address Reg.       */
-					/* channel 1                       */
-#define _DCAR1  	0xB0100014	/* LCD DMA Current Address Reg.    */
-					/* channel 1                       */
-#define _DBAR2  	0xB0100018	/* LCD DMA Base Address Reg.       */
-					/* channel 2                       */
-#define _DCAR2  	0xB010001C	/* LCD DMA Current Address Reg.    */
-					/* channel 2                       */
-#define _LCCR1  	0xB0100020	/* LCD Control Reg. 1              */
-#define _LCCR2  	0xB0100024	/* LCD Control Reg. 2              */
-#define _LCCR3  	0xB0100028	/* LCD Control Reg. 3              */
+#define LCD_Int0_0	0x0		/* LCD Intensity =   0.0% =  0	   */
+#define LCD_Int11_1	0x1		/* LCD Intensity =  11.1% =  1/9   */
+#define LCD_Int20_0	0x2		/* LCD Intensity =  20.0% =  1/5   */
+#define LCD_Int26_7	0x3		/* LCD Intensity =  26.7% =  4/15  */
+#define LCD_Int33_3	0x4		/* LCD Intensity =  33.3% =  3/9   */
+#define LCD_Int40_0	0x5		/* LCD Intensity =  40.0% =  2/5   */
+#define LCD_Int44_4	0x6		/* LCD Intensity =  44.4% =  4/9   */
+#define LCD_Int50_0	0x7		/* LCD Intensity =  50.0% =  1/2   */
+#define LCD_Int55_6	0x8		/* LCD Intensity =  55.6% =  5/9   */
+#define LCD_Int60_0	0x9		/* LCD Intensity =  60.0% =  3/5   */
+#define LCD_Int66_7	0xA		/* LCD Intensity =  66.7% =  6/9   */
+#define LCD_Int73_3	0xB		/* LCD Intensity =  73.3% = 11/15  */
+#define LCD_Int80_0	0xC		/* LCD Intensity =  80.0% =  4/5   */
+#define LCD_Int88_9	0xD		/* LCD Intensity =  88.9% =  8/9   */
+#define LCD_Int100_0	0xE		/* LCD Intensity = 100.0% =  1	   */
+#define LCD_Int100_0A	0xF		/* LCD Intensity = 100.0% =  1	   */
+					/* (Alternative)		   */
+
+#define _LCCR0		0xB0100000	/* LCD Control Reg. 0		   */
+#define _LCSR		0xB0100004	/* LCD Status Reg.		   */
+#define _DBAR1		0xB0100010	/* LCD DMA Base Address Reg.	   */
+					/* channel 1			   */
+#define _DCAR1		0xB0100014	/* LCD DMA Current Address Reg.    */
+					/* channel 1			   */
+#define _DBAR2		0xB0100018	/* LCD DMA Base Address Reg.	   */
+					/* channel 2			   */
+#define _DCAR2		0xB010001C	/* LCD DMA Current Address Reg.    */
+					/* channel 2			   */
+#define _LCCR1		0xB0100020	/* LCD Control Reg. 1		   */
+#define _LCCR2		0xB0100024	/* LCD Control Reg. 2		   */
+#define _LCCR3		0xB0100028	/* LCD Control Reg. 3		   */
 
 #if LANGUAGE == C
-#define LCCR0   	        	/* LCD Control Reg. 0              */ \
+#define LCCR0				/* LCD Control Reg. 0		   */ \
 			(*((volatile Word *) io_p2v (_LCCR0)))
-#define LCSR    	        	/* LCD Status Reg.                 */ \
+#define LCSR				/* LCD Status Reg.		   */ \
 			(*((volatile Word *) io_p2v (_LCSR)))
-#define DBAR1   	        	/* LCD DMA Base Address Reg.       */ \
-					/* channel 1                       */ \
+#define DBAR1				/* LCD DMA Base Address Reg.	   */ \
+					/* channel 1			   */ \
 			(*((volatile Address *) io_p2v (_DBAR1)))
-#define DCAR1   	        	/* LCD DMA Current Address Reg.    */ \
-					/* channel 1                       */ \
+#define DCAR1				/* LCD DMA Current Address Reg.    */ \
+					/* channel 1			   */ \
 			(*((volatile Address *) io_p2v (_DCAR1)))
-#define DBAR2   	        	/* LCD DMA Base Address Reg.       */ \
-					/* channel 2                       */ \
+#define DBAR2				/* LCD DMA Base Address Reg.	   */ \
+					/* channel 2			   */ \
 			(*((volatile Address *) io_p2v (_DBAR2)))
-#define DCAR2   	        	/* LCD DMA Current Address Reg.    */ \
-					/* channel 2                       */ \
+#define DCAR2				/* LCD DMA Current Address Reg.    */ \
+					/* channel 2			   */ \
 			(*((volatile Address *) io_p2v (_DCAR2)))
-#define LCCR1   	        	/* LCD Control Reg. 1              */ \
+#define LCCR1				/* LCD Control Reg. 1		   */ \
 			(*((volatile Word *) io_p2v (_LCCR1)))
-#define LCCR2   	        	/* LCD Control Reg. 2              */ \
+#define LCCR2				/* LCD Control Reg. 2		   */ \
 			(*((volatile Word *) io_p2v (_LCCR2)))
-#define LCCR3   	        	/* LCD Control Reg. 3              */ \
+#define LCCR3				/* LCD Control Reg. 3		   */ \
 			(*((volatile Word *) io_p2v (_LCCR3)))
 #endif /* LANGUAGE == C */
 
-#define LCCR0_LEN	0x00000001	/* LCD ENable                      */
+#define LCCR0_LEN	0x00000001	/* LCD ENable			   */
 #define LCCR0_CMS	0x00000002	/* Color/Monochrome display Select */
-#define LCCR0_Color	(LCCR0_CMS*0)	/*  Color display                  */
-#define LCCR0_Mono	(LCCR0_CMS*1)	/*  Monochrome display             */
-#define LCCR0_SDS	0x00000004	/* Single/Dual panel display       */
-					/* Select                          */
-#define LCCR0_Sngl	(LCCR0_SDS*0)	/*  Single panel display           */
-#define LCCR0_Dual	(LCCR0_SDS*1)	/*  Dual panel display             */
-#define LCCR0_LDM	0x00000008	/* LCD Disable done (LDD)          */
-					/* interrupt Mask (disable)        */
-#define LCCR0_BAM	0x00000010	/* Base Address update (BAU)       */
-					/* interrupt Mask (disable)        */
+#define LCCR0_Color	(LCCR0_CMS*0)	/*  Color display		   */
+#define LCCR0_Mono	(LCCR0_CMS*1)	/*  Monochrome display		   */
+#define LCCR0_SDS	0x00000004	/* Single/Dual panel display	   */
+					/* Select			   */
+#define LCCR0_Sngl	(LCCR0_SDS*0)	/*  Single panel display	   */
+#define LCCR0_Dual	(LCCR0_SDS*1)	/*  Dual panel display		   */
+#define LCCR0_LDM	0x00000008	/* LCD Disable done (LDD)	   */
+					/* interrupt Mask (disable)	   */
+#define LCCR0_BAM	0x00000010	/* Base Address update (BAU)	   */
+					/* interrupt Mask (disable)	   */
 #define LCCR0_ERM	0x00000020	/* LCD ERror (BER, IOL, IUL, IOU,  */
 					/* IUU, OOL, OUL, OOU, and OUU)    */
-					/* interrupt Mask (disable)        */
+					/* interrupt Mask (disable)	   */
 #define LCCR0_PAS	0x00000080	/* Passive/Active display Select   */
-#define LCCR0_Pas	(LCCR0_PAS*0)	/*  Passive display (STN)          */
-#define LCCR0_Act	(LCCR0_PAS*1)	/*  Active display (TFT)           */
-#define LCCR0_BLE	0x00000100	/* Big/Little Endian select        */
-#define LCCR0_LtlEnd	(LCCR0_BLE*0)	/*  Little Endian frame buffer     */
-#define LCCR0_BigEnd	(LCCR0_BLE*1)	/*  Big Endian frame buffer        */
+#define LCCR0_Pas	(LCCR0_PAS*0)	/*  Passive display (STN)	   */
+#define LCCR0_Act	(LCCR0_PAS*1)	/*  Active display (TFT)	   */
+#define LCCR0_BLE	0x00000100	/* Big/Little Endian select	   */
+#define LCCR0_LtlEnd	(LCCR0_BLE*0)	/*  Little Endian frame buffer	   */
+#define LCCR0_BigEnd	(LCCR0_BLE*1)	/*  Big Endian frame buffer	   */
 #define LCCR0_DPD	0x00000200	/* Double Pixel Data (monochrome   */
-					/* display mode)                   */
-#define LCCR0_4PixMono	(LCCR0_DPD*0)	/*  4-Pixel/clock Monochrome       */
-					/*  display                        */
-#define LCCR0_8PixMono	(LCCR0_DPD*1)	/*  8-Pixel/clock Monochrome       */
-					/*  display                        */
-#define LCCR0_PDD	Fld (8, 12)	/* Palette DMA request Delay       */
-					/* [Tmem]                          */
-#define LCCR0_DMADel(Tcpu)      	/*  palette DMA request Delay      */ \
-					/*  [0..510 Tcpu]                  */ \
+					/* display mode)		   */
+#define LCCR0_4PixMono	(LCCR0_DPD*0)	/*  4-Pixel/clock Monochrome	   */
+					/*  display			   */
+#define LCCR0_8PixMono	(LCCR0_DPD*1)	/*  8-Pixel/clock Monochrome	   */
+					/*  display			   */
+#define LCCR0_PDD	Fld (8, 12)	/* Palette DMA request Delay	   */
+					/* [Tmem]			   */
+#define LCCR0_DMADel(Tcpu)		/*  palette DMA request Delay	   */ \
+					/*  [0..510 Tcpu]		   */ \
 			((Tcpu)/2 << FShft (LCCR0_PDD))
 
-#define LCSR_LDD	0x00000001	/* LCD Disable Done                */
-#define LCSR_BAU	0x00000002	/* Base Address Update (read)      */
-#define LCSR_BER	0x00000004	/* Bus ERror                       */
-#define LCSR_ABC	0x00000008	/* AC Bias clock Count             */
-#define LCSR_IOL	0x00000010	/* Input FIFO Over-run Lower       */
-					/* panel                           */
-#define LCSR_IUL	0x00000020	/* Input FIFO Under-run Lower      */
-					/* panel                           */
-#define LCSR_IOU	0x00000040	/* Input FIFO Over-run Upper       */
-					/* panel                           */
-#define LCSR_IUU	0x00000080	/* Input FIFO Under-run Upper      */
-					/* panel                           */
-#define LCSR_OOL	0x00000100	/* Output FIFO Over-run Lower      */
-					/* panel                           */
-#define LCSR_OUL	0x00000200	/* Output FIFO Under-run Lower     */
-					/* panel                           */
-#define LCSR_OOU	0x00000400	/* Output FIFO Over-run Upper      */
-					/* panel                           */
-#define LCSR_OUU	0x00000800	/* Output FIFO Under-run Upper     */
-					/* panel                           */
-
-#define LCCR1_PPL	Fld (6, 4)	/* Pixels Per Line/16 - 1          */
-#define LCCR1_DisWdth(Pixel)    	/*  Display Width [16..1024 pix.]  */ \
+#define LCSR_LDD	0x00000001	/* LCD Disable Done		   */
+#define LCSR_BAU	0x00000002	/* Base Address Update (read)	   */
+#define LCSR_BER	0x00000004	/* Bus ERror			   */
+#define LCSR_ABC	0x00000008	/* AC Bias clock Count		   */
+#define LCSR_IOL	0x00000010	/* Input FIFO Over-run Lower	   */
+					/* panel			   */
+#define LCSR_IUL	0x00000020	/* Input FIFO Under-run Lower	   */
+					/* panel			   */
+#define LCSR_IOU	0x00000040	/* Input FIFO Over-run Upper	   */
+					/* panel			   */
+#define LCSR_IUU	0x00000080	/* Input FIFO Under-run Upper	   */
+					/* panel			   */
+#define LCSR_OOL	0x00000100	/* Output FIFO Over-run Lower	   */
+					/* panel			   */
+#define LCSR_OUL	0x00000200	/* Output FIFO Under-run Lower	   */
+					/* panel			   */
+#define LCSR_OOU	0x00000400	/* Output FIFO Over-run Upper	   */
+					/* panel			   */
+#define LCSR_OUU	0x00000800	/* Output FIFO Under-run Upper	   */
+					/* panel			   */
+
+#define LCCR1_PPL	Fld (6, 4)	/* Pixels Per Line/16 - 1	   */
+#define LCCR1_DisWdth(Pixel)		/*  Display Width [16..1024 pix.]  */ \
 			(((Pixel) - 16)/16 << FShft (LCCR1_PPL))
-#define LCCR1_HSW	Fld (6, 10)	/* Horizontal Synchronization      */
+#define LCCR1_HSW	Fld (6, 10)	/* Horizontal Synchronization	   */
 					/* pulse Width - 2 [Tpix] (L_LCLK) */
-#define LCCR1_HorSnchWdth(Tpix) 	/*  Horizontal Synchronization     */ \
-					/*  pulse Width [2..65 Tpix]       */ \
+#define LCCR1_HorSnchWdth(Tpix)		/*  Horizontal Synchronization	   */ \
+					/*  pulse Width [2..65 Tpix]	   */ \
 			(((Tpix) - 2) << FShft (LCCR1_HSW))
 #define LCCR1_ELW	Fld (8, 16)	/* End-of-Line pixel clock Wait    */
-					/* count - 1 [Tpix]                */
-#define LCCR1_EndLnDel(Tpix)    	/*  End-of-Line Delay              */ \
-					/*  [1..256 Tpix]                  */ \
+					/* count - 1 [Tpix]		   */
+#define LCCR1_EndLnDel(Tpix)		/*  End-of-Line Delay		   */ \
+					/*  [1..256 Tpix]		   */ \
 			(((Tpix) - 1) << FShft (LCCR1_ELW))
 #define LCCR1_BLW	Fld (8, 24)	/* Beginning-of-Line pixel clock   */
-					/* Wait count - 1 [Tpix]           */
-#define LCCR1_BegLnDel(Tpix)    	/*  Beginning-of-Line Delay        */ \
-					/*  [1..256 Tpix]                  */ \
+					/* Wait count - 1 [Tpix]	   */
+#define LCCR1_BegLnDel(Tpix)		/*  Beginning-of-Line Delay	   */ \
+					/*  [1..256 Tpix]		   */ \
 			(((Tpix) - 1) << FShft (LCCR1_BLW))
 
-#define LCCR2_LPP	Fld (10, 0)	/* Line Per Panel - 1              */
-#define LCCR2_DisHght(Line)     	/*  Display Height [1..1024 lines] */ \
+#define LCCR2_LPP	Fld (10, 0)	/* Line Per Panel - 1		   */
+#define LCCR2_DisHght(Line)		/*  Display Height [1..1024 lines] */ \
 			(((Line) - 1) << FShft (LCCR2_LPP))
 #define LCCR2_VSW	Fld (6, 10)	/* Vertical Synchronization pulse  */
-					/* Width - 1 [Tln] (L_FCLK)        */
-#define LCCR2_VrtSnchWdth(Tln)  	/*  Vertical Synchronization pulse */ \
-					/*  Width [1..64 Tln]              */ \
+					/* Width - 1 [Tln] (L_FCLK)	   */
+#define LCCR2_VrtSnchWdth(Tln)		/*  Vertical Synchronization pulse */ \
+					/*  Width [1..64 Tln]		   */ \
 			(((Tln) - 1) << FShft (LCCR2_VSW))
 #define LCCR2_EFW	Fld (8, 16)	/* End-of-Frame line clock Wait    */
-					/* count [Tln]                     */
-#define LCCR2_EndFrmDel(Tln)    	/*  End-of-Frame Delay             */ \
-					/*  [0..255 Tln]                   */ \
+					/* count [Tln]			   */
+#define LCCR2_EndFrmDel(Tln)		/*  End-of-Frame Delay		   */ \
+					/*  [0..255 Tln]		   */ \
 			((Tln) << FShft (LCCR2_EFW))
 #define LCCR2_BFW	Fld (8, 24)	/* Beginning-of-Frame line clock   */
-					/* Wait count [Tln]                */
-#define LCCR2_BegFrmDel(Tln)    	/*  Beginning-of-Frame Delay       */ \
-					/*  [0..255 Tln]                   */ \
+					/* Wait count [Tln]		   */
+#define LCCR2_BegFrmDel(Tln)		/*  Beginning-of-Frame Delay	   */ \
+					/*  [0..255 Tln]		   */ \
 			((Tln) << FShft (LCCR2_BFW))
 
-#define LCCR3_PCD	Fld (8, 0)	/* Pixel Clock Divisor/2 - 2       */
-					/* [1..255] (L_PCLK)               */
-					/* fpix = fcpu/(2*(PCD + 2))       */
-					/* Tpix = 2*(PCD + 2)*Tcpu         */
-#define LCCR3_PixClkDiv(Div)    	/*  Pixel Clock Divisor [6..514]   */ \
+#define LCCR3_PCD	Fld (8, 0)	/* Pixel Clock Divisor/2 - 2	   */
+					/* [1..255] (L_PCLK)		   */
+					/* fpix = fcpu/(2*(PCD + 2))	   */
+					/* Tpix = 2*(PCD + 2)*Tcpu	   */
+#define LCCR3_PixClkDiv(Div)		/*  Pixel Clock Divisor [6..514]   */ \
 			(((Div) - 4)/2 << FShft (LCCR3_PCD))
 					/*  fpix = fcpu/(2*Floor (Div/2))  */
 					/*  Tpix = 2*Floor (Div/2)*Tcpu    */
 #define LCCR3_CeilPixClkDiv(Div)	/*  Ceil. of PixClkDiv [6..514]    */ \
 			(((Div) - 3)/2 << FShft (LCCR3_PCD))
 					/*  fpix = fcpu/(2*Ceil (Div/2))   */
-					/*  Tpix = 2*Ceil (Div/2)*Tcpu     */
+					/*  Tpix = 2*Ceil (Div/2)*Tcpu	   */
 #define LCCR3_ACB	Fld (8, 8)	/* AC Bias clock half period - 1   */
-					/* [Tln] (L_BIAS)                  */
-#define LCCR3_ACBsDiv(Div)      	/*  AC Bias clock Divisor [2..512] */ \
+					/* [Tln] (L_BIAS)		   */
+#define LCCR3_ACBsDiv(Div)		/*  AC Bias clock Divisor [2..512] */ \
 			(((Div) - 2)/2 << FShft (LCCR3_ACB))
 					/*  fac = fln/(2*Floor (Div/2))    */
-					/*  Tac = 2*Floor (Div/2)*Tln      */
-#define LCCR3_CeilACBsDiv(Div)  	/*  Ceil. of ACBsDiv [2..512]      */ \
+					/*  Tac = 2*Floor (Div/2)*Tln	   */
+#define LCCR3_CeilACBsDiv(Div)		/*  Ceil. of ACBsDiv [2..512]	   */ \
 			(((Div) - 1)/2 << FShft (LCCR3_ACB))
-					/*  fac = fln/(2*Ceil (Div/2))     */
-					/*  Tac = 2*Ceil (Div/2)*Tln       */
-#define LCCR3_API	Fld (4, 16)	/* AC bias Pin transitions per     */
-					/* Interrupt                       */
-#define LCCR3_ACBsCntOff        	/*  AC Bias clock transition Count */ \
-					/*  Off                            */ \
+					/*  fac = fln/(2*Ceil (Div/2))	   */
+					/*  Tac = 2*Ceil (Div/2)*Tln	   */
+#define LCCR3_API	Fld (4, 16)	/* AC bias Pin transitions per	   */
+					/* Interrupt			   */
+#define LCCR3_ACBsCntOff		/*  AC Bias clock transition Count */ \
+					/*  Off				   */ \
 			(0 << FShft (LCCR3_API))
-#define LCCR3_ACBsCnt(Trans)    	/*  AC Bias clock transition Count */ \
-					/*  [1..15]                        */ \
+#define LCCR3_ACBsCnt(Trans)		/*  AC Bias clock transition Count */ \
+					/*  [1..15]			   */ \
 			((Trans) << FShft (LCCR3_API))
 #define LCCR3_VSP	0x00100000	/* Vertical Synchronization pulse  */
-					/* Polarity (L_FCLK)               */
+					/* Polarity (L_FCLK)		   */
 #define LCCR3_VrtSnchH	(LCCR3_VSP*0)	/*  Vertical Synchronization pulse */
-					/*  active High                    */
+					/*  active High			   */
 #define LCCR3_VrtSnchL	(LCCR3_VSP*1)	/*  Vertical Synchronization pulse */
-					/*  active Low                     */
-#define LCCR3_HSP	0x00200000	/* Horizontal Synchronization      */
-					/* pulse Polarity (L_LCLK)         */
-#define LCCR3_HorSnchH	(LCCR3_HSP*0)	/*  Horizontal Synchronization     */
-					/*  pulse active High              */
-#define LCCR3_HorSnchL	(LCCR3_HSP*1)	/*  Horizontal Synchronization     */
-					/*  pulse active Low               */
+					/*  active Low			   */
+#define LCCR3_HSP	0x00200000	/* Horizontal Synchronization	   */
+					/* pulse Polarity (L_LCLK)	   */
+#define LCCR3_HorSnchH	(LCCR3_HSP*0)	/*  Horizontal Synchronization	   */
+					/*  pulse active High		   */
+#define LCCR3_HorSnchL	(LCCR3_HSP*1)	/*  Horizontal Synchronization	   */
+					/*  pulse active Low		   */
 #define LCCR3_PCP	0x00400000	/* Pixel Clock Polarity (L_PCLK)   */
-#define LCCR3_PixRsEdg	(LCCR3_PCP*0)	/*  Pixel clock Rising-Edge        */
-#define LCCR3_PixFlEdg	(LCCR3_PCP*1)	/*  Pixel clock Falling-Edge       */
+#define LCCR3_PixRsEdg	(LCCR3_PCP*0)	/*  Pixel clock Rising-Edge	   */
+#define LCCR3_PixFlEdg	(LCCR3_PCP*1)	/*  Pixel clock Falling-Edge	   */
 #define LCCR3_OEP	0x00800000	/* Output Enable Polarity (L_BIAS, */
-					/* active display mode)            */
-#define LCCR3_OutEnH	(LCCR3_OEP*0)	/*  Output Enable active High      */
-#define LCCR3_OutEnL	(LCCR3_OEP*1)	/*  Output Enable active Low       */
+					/* active display mode)		   */
+#define LCCR3_OutEnH	(LCCR3_OEP*0)	/*  Output Enable active High	   */
+#define LCCR3_OutEnL	(LCCR3_OEP*1)	/*  Output Enable active Low	   */
 
 
 #undef C
diff --git a/include/ahci.h b/include/ahci.h
index 80701e298c..b363ee1969 100644
--- a/include/ahci.h
+++ b/include/ahci.h
@@ -91,12 +91,12 @@
 #define PORT_IRQ_PIOS_FIS	(1 << 1) /* PIO Setup FIS rx'd */
 #define PORT_IRQ_D2H_REG_FIS	(1 << 0) /* D2H Register FIS rx'd */
 
-#define PORT_IRQ_FATAL		PORT_IRQ_TF_ERR | PORT_IRQ_HBUS_ERR 	\
+#define PORT_IRQ_FATAL		PORT_IRQ_TF_ERR | PORT_IRQ_HBUS_ERR	\
 				| PORT_IRQ_HBUS_DATA_ERR | PORT_IRQ_IF_ERR
 
-#define DEF_PORT_IRQ		PORT_IRQ_FATAL | PORT_IRQ_PHYRDY 	\
-				| PORT_IRQ_CONNECT | PORT_IRQ_SG_DONE 	\
-				| PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_FIS 	\
+#define DEF_PORT_IRQ		PORT_IRQ_FATAL | PORT_IRQ_PHYRDY	\
+				| PORT_IRQ_CONNECT | PORT_IRQ_SG_DONE	\
+				| PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_FIS	\
 				| PORT_IRQ_DMAS_FIS | PORT_IRQ_PIOS_FIS	\
 				| PORT_IRQ_D2H_REG_FIS
 
@@ -172,7 +172,7 @@ struct ahci_ioports {
 };
 
 struct ahci_probe_ent {
-	pci_dev_t 	dev;
+	pci_dev_t	dev;
 	struct ahci_ioports	port[AHCI_MAX_PORTS];
 	u32	n_ports;
 	u32	hard_port_no;
diff --git a/include/armcoremodule.h b/include/armcoremodule.h
index 7dac6f8c9e..f1ded85fcf 100644
--- a/include/armcoremodule.h
+++ b/include/armcoremodule.h
@@ -28,20 +28,20 @@
 #ifndef __ARMCOREMODULE_H
 #define __ARMCOREMODULE_H
 
-#define CM_BASE		0x10000000
+#define CM_BASE			0x10000000
 
 /* CM registers common to all CMs */
 /* Note that observed values after reboot into the ARM Boot Monitor
    have been used as defaults, rather than the POR values */
-#define OS_CTRL     		0x0000000C
+#define OS_CTRL			0x0000000C
 #define CMMASK_REMAP		0x00000005	/* set remap & led           */
 #define CMMASK_RESET		0x00000008
-#define OS_LOCK             	0x00000014
-#define CMVAL_LOCK1	     	0x0000A000	/* locking value             */
+#define OS_LOCK			0x00000014
+#define CMVAL_LOCK1		0x0000A000	/* locking value             */
 #define CMVAL_LOCK2		0x0000005F	/* locking value             */
 #define CMVAL_UNLOCK		0x00000000	/* any value != CM_LOCKVAL   */
 #define OS_SDRAM		0x00000020
-#define OS_INIT     		0x00000024
+#define OS_INIT			0x00000024
 #define CMMASK_MAP_SIMPLE	0xFFFDFFFF	/* simple mapping */
 #define CMMASK_TCRAM_DISABLE	0xFFFEFFFF	/* TCRAM disabled */
 #define CMMASK_LOWVEC		0x00000000	/* vectors @ 0x00000000 */
diff --git a/include/asm-arm/arch-arm720t/netarm_mem_module.h b/include/asm-arm/arch-arm720t/netarm_mem_module.h
index f0529fd09b..c650c3b004 100644
--- a/include/asm-arm/arch-arm720t/netarm_mem_module.h
+++ b/include/asm-arm/arch-arm720t/netarm_mem_module.h
@@ -170,15 +170,15 @@
 /* Option B Registers (0xFFC0_00x8) */
 #define NETARM_MEM_OPTB_SYNC_1_STAGE	(0x00000001)
 #define NETARM_MEM_OPTB_SYNC_2_STAGE	(0x00000002)
-#define NETARM_MEM_OPTB_BCYC_PLUS0   	(0x00000000)
-#define NETARM_MEM_OPTB_BCYC_PLUS4   	(0x00000004)
-#define NETARM_MEM_OPTB_BCYC_PLUS8   	(0x00000008)
-#define NETARM_MEM_OPTB_BCYC_PLUS12  	(0x0000000C)
-
-#define NETARM_MEM_OPTB_WAIT_PLUS0   	(0x00000000)
-#define NETARM_MEM_OPTB_WAIT_PLUS16   	(0x00000010)
-#define NETARM_MEM_OPTB_WAIT_PLUS32   	(0x00000020)
-#define NETARM_MEM_OPTB_WAIT_PLUS48   	(0x00000030)
+#define NETARM_MEM_OPTB_BCYC_PLUS0	(0x00000000)
+#define NETARM_MEM_OPTB_BCYC_PLUS4	(0x00000004)
+#define NETARM_MEM_OPTB_BCYC_PLUS8	(0x00000008)
+#define NETARM_MEM_OPTB_BCYC_PLUS12	(0x0000000C)
+
+#define NETARM_MEM_OPTB_WAIT_PLUS0	(0x00000000)
+#define NETARM_MEM_OPTB_WAIT_PLUS16	(0x00000010)
+#define NETARM_MEM_OPTB_WAIT_PLUS32	(0x00000020)
+#define NETARM_MEM_OPTB_WAIT_PLUS48	(0x00000030)
 #endif
 
 #endif
diff --git a/include/asm-arm/arch-arm720t/netarm_ser_module.h b/include/asm-arm/arch-arm720t/netarm_ser_module.h
index fceabd173e..6fbae11c8d 100644
--- a/include/asm-arm/arch-arm720t/netarm_ser_module.h
+++ b/include/asm-arm/arch-arm720t/netarm_ser_module.h
@@ -284,21 +284,21 @@ typedef struct {
 /* from section 7.5.4 of HW Ref Guide */
 
 /* #ifdef CONFIG_NETARM_PLL_BYPASS */
-#define	NETARM_SER_BR_X16(x)	( NETARM_SER_BR_EN | 			\
-				  NETARM_SER_BR_RX_CLK_INT | 		\
-				  NETARM_SER_BR_TX_CLK_INT | 		\
-				  NETARM_SER_BR_CLK_EXT_5 | 		\
-				  ( ( ( ( NETARM_XTAL_FREQ / 		\
-				          ( x * 10 ) ) - 1 ) /	16 ) & 	\
+#define	NETARM_SER_BR_X16(x)	( NETARM_SER_BR_EN |			\
+				  NETARM_SER_BR_RX_CLK_INT |		\
+				  NETARM_SER_BR_TX_CLK_INT |		\
+				  NETARM_SER_BR_CLK_EXT_5 |		\
+				  ( ( ( ( NETARM_XTAL_FREQ /		\
+				          ( x * 10 ) ) - 1 ) /	16 ) &	\
 				    NETARM_SER_BR_MASK ) )
 /*
 #else
-#define	NETARM_SER_BR_X16(x)	( NETARM_SER_BR_EN | 			\
-				  NETARM_SER_BR_RX_CLK_INT | 		\
-				  NETARM_SER_BR_TX_CLK_INT | 		\
-				  NETARM_SER_BR_CLK_SYSTEM | 		\
-				  ( ( ( ( NETARM_PLLED_SYSCLK_FREQ / 		\
-				          ( x * 2 ) ) - 1 ) /	16 ) & 	\
+#define	NETARM_SER_BR_X16(x)	( NETARM_SER_BR_EN |			\
+				  NETARM_SER_BR_RX_CLK_INT |		\
+				  NETARM_SER_BR_TX_CLK_INT |		\
+				  NETARM_SER_BR_CLK_SYSTEM |		\
+				  ( ( ( ( NETARM_PLLED_SYSCLK_FREQ /		\
+				          ( x * 2 ) ) - 1 ) /	16 ) &	\
 				    NETARM_SER_BR_MASK ) )
 #endif
 */
@@ -313,13 +313,13 @@ typedef struct {
 /* #ifdef CONFIG_NETARM_PLL_BYPASS */
 #define	NETARM_SER_RXGAP(x)	( NETARM_SER_RX_GAP_TIMER_EN |		\
 				  ( ( ( ( 10 * NETARM_XTAL_FREQ ) /	\
-				        ( x * 5 * 512 ) ) - 1 ) & 	\
+				        ( x * 5 * 512 ) ) - 1 ) &	\
 			              NETARM_SER_RX_GAP_MASK ) )
 /*
 #else
 #define	NETARM_SER_RXGAP(x)	( NETARM_SER_RX_GAP_TIMER_EN |			\
 				  ( ( ( ( 2 * NETARM_PLLED_SYSCLK_FREQ ) /	\
-				        ( x * 512 ) ) - 1 ) & 			\
+				        ( x * 512 ) ) - 1 ) &			\
 			              NETARM_SER_RX_GAP_MASK ) )
 #endif
 */
@@ -327,11 +327,11 @@ typedef struct {
 #if 0
 #define	NETARM_SER_RXGAP(x)	( NETARM_SER_RX_GAP_TIMER_EN |		\
 				  ( ( ( ( 2 * NETARM_PLLED_SYSCLK_FREQ ) /	\
-				        ( x * 5 * 512 ) ) - 1 ) & 	\
+				        ( x * 5 * 512 ) ) - 1 ) &	\
 			              NETARM_SER_RX_GAP_MASK ) )
 #define	NETARM_SER_RXGAP(x)	( NETARM_SER_RX_GAP_TIMER_EN |		\
 				  ( ( ( ( 10 * NETARM_XTAL_FREQ ) /	\
-				        ( x * 512 ) ) - 1 ) & 	\
+				        ( x * 512 ) ) - 1 ) &	\
 			              NETARM_SER_RX_GAP_MASK ) )
 #endif
 
diff --git a/include/asm-arm/arch-arm720t/s3c4510b.h b/include/asm-arm/arch-arm720t/s3c4510b.h
index 73a3b6d856..6b8c8edd7a 100644
--- a/include/asm-arm/arch-arm720t/s3c4510b.h
+++ b/include/asm-arm/arch-arm720t/s3c4510b.h
@@ -35,7 +35,7 @@
 
 /* Special Register Start Address After System Reset */
 #define REG_BASE	(0x03ff0000)
-#define SPSTR      	(REG_BASE)
+#define SPSTR		(REG_BASE)
 
 /* *********************** */
 /* System Manager Register */
@@ -100,7 +100,7 @@
 #define REG_I2C_CON	(REG_BASE+0xf000)
 #define REG_I2C_BUF	(REG_BASE+0xf004)
 #define REG_I2C_PS	(REG_BASE+0xf008)
-#define REG_I2C_COUNT 	(REG_BASE+0xf00c)
+#define REG_I2C_COUNT	(REG_BASE+0xf00c)
 
 /********************/
 /*    GDMA 0        */
@@ -149,7 +149,7 @@
 /********************/
 /*  Timer Register  */
 /********************/
-#define REG_TMOD  	(REG_BASE+0x6000)
+#define REG_TMOD	(REG_BASE+0x6000)
 #define REG_TDATA0	(REG_BASE+0x6004)
 #define REG_TDATA1	(REG_BASE+0x6008)
 #define REG_TCNT0	(REG_BASE+0x600c)
@@ -159,8 +159,8 @@
 /* I/O Port Interface */
 /**********************/
 #define REG_IOPMODE	(REG_BASE+0x5000)
-#define REG_IOPCON  	(REG_BASE+0x5004)
-#define REG_IOPDATA 	(REG_BASE+0x5008)
+#define REG_IOPCON	(REG_BASE+0x5004)
+#define REG_IOPDATA	(REG_BASE+0x5008)
 
 /*********************************/
 /* Interrupt Controller Register */
diff --git a/include/asm-arm/arch-at91rm9200/AT91RM9200.h b/include/asm-arm/arch-at91rm9200/AT91RM9200.h
index 0e01005a91..2f7f71036b 100644
--- a/include/asm-arm/arch-at91rm9200/AT91RM9200.h
+++ b/include/asm-arm/arch-at91rm9200/AT91RM9200.h
@@ -32,17 +32,17 @@ typedef volatile unsigned int AT91_REG;		/* Hardware register definition */
 /*****************************************************************************/
 typedef struct _AT91S_TC
 {
-	AT91_REG	 TC_CCR; 	/* Channel Control Register */
-	AT91_REG	 TC_CMR; 	/* Channel Mode Register */
-	AT91_REG	 Reserved0[2]; 	/*  */
-	AT91_REG	 TC_CV; 	/* Counter Value */
-	AT91_REG	 TC_RA; 	/* Register A */
-	AT91_REG	 TC_RB; 	/* Register B */
-	AT91_REG	 TC_RC; 	/* Register C */
-	AT91_REG	 TC_SR; 	/* Status Register */
-	AT91_REG	 TC_IER; 	/* Interrupt Enable Register */
-	AT91_REG	 TC_IDR; 	/* Interrupt Disable Register */
-	AT91_REG	 TC_IMR; 	/* Interrupt Mask Register */
+	AT91_REG	 TC_CCR;	/* Channel Control Register */
+	AT91_REG	 TC_CMR;	/* Channel Mode Register */
+	AT91_REG	 Reserved0[2];	/*  */
+	AT91_REG	 TC_CV;		/* Counter Value */
+	AT91_REG	 TC_RA;		/* Register A */
+	AT91_REG	 TC_RB;		/* Register B */
+	AT91_REG	 TC_RC;		/* Register C */
+	AT91_REG	 TC_SR;		/* Status Register */
+	AT91_REG	 TC_IER;	/* Interrupt Enable Register */
+	AT91_REG	 TC_IDR;	/* Interrupt Disable Register */
+	AT91_REG	 TC_IMR;	/* Interrupt Mask Register */
 } AT91S_TC, *AT91PS_TC;
 
 #define AT91C_TC_TIMER_DIV1_CLOCK ((unsigned int) 0x0 <<  0) /* (TC) MCK/2 */
@@ -65,33 +65,33 @@ typedef struct _AT91S_TC
 /*****************************************************************************/
 typedef struct _AT91S_USART
 {
-	AT91_REG	 US_CR; 	/* Control Register */
-	AT91_REG	 US_MR; 	/* Mode Register */
-	AT91_REG	 US_IER; 	/* Interrupt Enable Register */
-	AT91_REG	 US_IDR; 	/* Interrupt Disable Register */
-	AT91_REG	 US_IMR; 	/* Interrupt Mask Register */
-	AT91_REG	 US_CSR; 	/* Channel Status Register */
-	AT91_REG	 US_RHR; 	/* Receiver Holding Register */
-	AT91_REG	 US_THR; 	/* Transmitter Holding Register */
-	AT91_REG	 US_BRGR; 	/* Baud Rate Generator Register */
-	AT91_REG	 US_RTOR; 	/* Receiver Time-out Register */
-	AT91_REG	 US_TTGR; 	/* Transmitter Time-guard Register */
-	AT91_REG	 Reserved0[5]; 	/*  */
-	AT91_REG	 US_FIDI; 	/* FI_DI_Ratio Register */
-	AT91_REG	 US_NER; 	/* Nb Errors Register */
-	AT91_REG	 US_XXR; 	/* XON_XOFF Register */
-	AT91_REG	 US_IF; 	/* IRDA_FILTER Register */
+	AT91_REG	 US_CR;		/* Control Register */
+	AT91_REG	 US_MR;		/* Mode Register */
+	AT91_REG	 US_IER;	/* Interrupt Enable Register */
+	AT91_REG	 US_IDR;	/* Interrupt Disable Register */
+	AT91_REG	 US_IMR;	/* Interrupt Mask Register */
+	AT91_REG	 US_CSR;	/* Channel Status Register */
+	AT91_REG	 US_RHR;	/* Receiver Holding Register */
+	AT91_REG	 US_THR;	/* Transmitter Holding Register */
+	AT91_REG	 US_BRGR;	/* Baud Rate Generator Register */
+	AT91_REG	 US_RTOR;	/* Receiver Time-out Register */
+	AT91_REG	 US_TTGR;	/* Transmitter Time-guard Register */
+	AT91_REG	 Reserved0[5];	/*  */
+	AT91_REG	 US_FIDI;	/* FI_DI_Ratio Register */
+	AT91_REG	 US_NER;	/* Nb Errors Register */
+	AT91_REG	 US_XXR;	/* XON_XOFF Register */
+	AT91_REG	 US_IF;		/* IRDA_FILTER Register */
 	AT91_REG	 Reserved1[44];	/*  */
-	AT91_REG	 US_RPR; 	/* Receive Pointer Register */
-	AT91_REG	 US_RCR; 	/* Receive Counter Register */
-	AT91_REG	 US_TPR; 	/* Transmit Pointer Register */
-	AT91_REG	 US_TCR; 	/* Transmit Counter Register */
-	AT91_REG	 US_RNPR; 	/* Receive Next Pointer Register */
-	AT91_REG	 US_RNCR; 	/* Receive Next Counter Register */
-	AT91_REG	 US_TNPR; 	/* Transmit Next Pointer Register */
-	AT91_REG	 US_TNCR; 	/* Transmit Next Counter Register */
-	AT91_REG	 US_PTCR; 	/* PDC Transfer Control Register */
-	AT91_REG	 US_PTSR; 	/* PDC Transfer Status Register */
+	AT91_REG	 US_RPR;	/* Receive Pointer Register */
+	AT91_REG	 US_RCR;	/* Receive Counter Register */
+	AT91_REG	 US_TPR;	/* Transmit Pointer Register */
+	AT91_REG	 US_TCR;	/* Transmit Counter Register */
+	AT91_REG	 US_RNPR;	/* Receive Next Pointer Register */
+	AT91_REG	 US_RNCR;	/* Receive Next Counter Register */
+	AT91_REG	 US_TNPR;	/* Transmit Next Pointer Register */
+	AT91_REG	 US_TNCR;	/* Transmit Next Counter Register */
+	AT91_REG	 US_PTCR;	/* PDC Transfer Control Register */
+	AT91_REG	 US_PTSR;	/* PDC Transfer Status Register */
 } AT91S_USART, *AT91PS_USART;
 
 /*****************************************************************************/
@@ -99,10 +99,10 @@ typedef struct _AT91S_USART
 /*****************************************************************************/
 typedef struct _AT91S_CKGR
 {
-	AT91_REG	 CKGR_MOR; 	/* Main Oscillator Register */
-	AT91_REG	 CKGR_MCFR; 	/* Main Clock  Frequency Register */
-	AT91_REG	 CKGR_PLLAR; 	/* PLL A Register */
-	AT91_REG	 CKGR_PLLBR; 	/* PLL B Register */
+	AT91_REG	 CKGR_MOR;	/* Main Oscillator Register */
+	AT91_REG	 CKGR_MCFR;	/* Main Clock  Frequency Register */
+	AT91_REG	 CKGR_PLLAR;	/* PLL A Register */
+	AT91_REG	 CKGR_PLLBR;	/* PLL B Register */
 } AT91S_CKGR, *AT91PS_CKGR;
 
 /* -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- */
@@ -146,41 +146,41 @@ typedef struct _AT91S_CKGR
 /*****************************************************************************/
 typedef struct _AT91S_PIO
 {
-	AT91_REG	 PIO_PER; 	/* PIO Enable Register */
-	AT91_REG	 PIO_PDR; 	/* PIO Disable Register */
-	AT91_REG	 PIO_PSR; 	/* PIO Status Register */
-	AT91_REG	 Reserved0[1]; 	/*  */
-	AT91_REG	 PIO_OER; 	/* Output Enable Register */
-	AT91_REG	 PIO_ODR; 	/* Output Disable Registerr */
-	AT91_REG	 PIO_OSR; 	/* Output Status Register */
-	AT91_REG	 Reserved1[1]; 	/*  */
-	AT91_REG	 PIO_IFER; 	/* Input Filter Enable Register */
-	AT91_REG	 PIO_IFDR; 	/* Input Filter Disable Register */
-	AT91_REG	 PIO_IFSR; 	/* Input Filter Status Register */
-	AT91_REG	 Reserved2[1]; 	/*  */
-	AT91_REG	 PIO_SODR; 	/* Set Output Data Register */
-	AT91_REG	 PIO_CODR; 	/* Clear Output Data Register */
-	AT91_REG	 PIO_ODSR; 	/* Output Data Status Register */
-	AT91_REG	 PIO_PDSR; 	/* Pin Data Status Register */
-	AT91_REG	 PIO_IER; 	/* Interrupt Enable Register */
-	AT91_REG	 PIO_IDR; 	/* Interrupt Disable Register */
-	AT91_REG	 PIO_IMR; 	/* Interrupt Mask Register */
-	AT91_REG	 PIO_ISR; 	/* Interrupt Status Register */
-	AT91_REG	 PIO_MDER; 	/* Multi-driver Enable Register */
-	AT91_REG	 PIO_MDDR; 	/* Multi-driver Disable Register */
-	AT91_REG	 PIO_MDSR; 	/* Multi-driver Status Register */
-	AT91_REG	 Reserved3[1]; 	/*  */
-	AT91_REG	 PIO_PPUDR; 	/* Pull-up Disable Register */
-	AT91_REG	 PIO_PPUER; 	/* Pull-up Enable Register */
-	AT91_REG	 PIO_PPUSR; 	/* Pad Pull-up Status Register */
-	AT91_REG	 Reserved4[1]; 	/*  */
-	AT91_REG	 PIO_ASR; 	/* Select A Register */
-	AT91_REG	 PIO_BSR; 	/* Select B Register */
-	AT91_REG	 PIO_ABSR; 	/* AB Select Status Register */
-	AT91_REG	 Reserved5[9]; 	/*  */
-	AT91_REG	 PIO_OWER; 	/* Output Write Enable Register */
-	AT91_REG	 PIO_OWDR; 	/* Output Write Disable Register */
-	AT91_REG	 PIO_OWSR; 	/* Output Write Status Register */
+	AT91_REG	 PIO_PER;	/* PIO Enable Register */
+	AT91_REG	 PIO_PDR;	/* PIO Disable Register */
+	AT91_REG	 PIO_PSR;	/* PIO Status Register */
+	AT91_REG	 Reserved0[1];	/*  */
+	AT91_REG	 PIO_OER;	/* Output Enable Register */
+	AT91_REG	 PIO_ODR;	/* Output Disable Registerr */
+	AT91_REG	 PIO_OSR;	/* Output Status Register */
+	AT91_REG	 Reserved1[1];	/*  */
+	AT91_REG	 PIO_IFER;	/* Input Filter Enable Register */
+	AT91_REG	 PIO_IFDR;	/* Input Filter Disable Register */
+	AT91_REG	 PIO_IFSR;	/* Input Filter Status Register */
+	AT91_REG	 Reserved2[1];	/*  */
+	AT91_REG	 PIO_SODR;	/* Set Output Data Register */
+	AT91_REG	 PIO_CODR;	/* Clear Output Data Register */
+	AT91_REG	 PIO_ODSR;	/* Output Data Status Register */
+	AT91_REG	 PIO_PDSR;	/* Pin Data Status Register */
+	AT91_REG	 PIO_IER;	/* Interrupt Enable Register */
+	AT91_REG	 PIO_IDR;	/* Interrupt Disable Register */
+	AT91_REG	 PIO_IMR;	/* Interrupt Mask Register */
+	AT91_REG	 PIO_ISR;	/* Interrupt Status Register */
+	AT91_REG	 PIO_MDER;	/* Multi-driver Enable Register */
+	AT91_REG	 PIO_MDDR;	/* Multi-driver Disable Register */
+	AT91_REG	 PIO_MDSR;	/* Multi-driver Status Register */
+	AT91_REG	 Reserved3[1];	/*  */
+	AT91_REG	 PIO_PPUDR;	/* Pull-up Disable Register */
+	AT91_REG	 PIO_PPUER;	/* Pull-up Enable Register */
+	AT91_REG	 PIO_PPUSR;	/* Pad Pull-up Status Register */
+	AT91_REG	 Reserved4[1];	/*  */
+	AT91_REG	 PIO_ASR;	/* Select A Register */
+	AT91_REG	 PIO_BSR;	/* Select B Register */
+	AT91_REG	 PIO_ABSR;	/* AB Select Status Register */
+	AT91_REG	 Reserved5[9];	/*  */
+	AT91_REG	 PIO_OWER;	/* Output Write Enable Register */
+	AT91_REG	 PIO_OWDR;	/* Output Write Disable Register */
+	AT91_REG	 PIO_OWSR;	/* Output Write Status Register */
 } AT91S_PIO, *AT91PS_PIO;
 
 
@@ -189,30 +189,30 @@ typedef struct _AT91S_PIO
 /*****************************************************************************/
 typedef struct _AT91S_DBGU
 {
-	AT91_REG	 DBGU_CR; 	/* Control Register */
-	AT91_REG	 DBGU_MR; 	/* Mode Register */
-	AT91_REG	 DBGU_IER; 	/* Interrupt Enable Register */
-	AT91_REG	 DBGU_IDR; 	/* Interrupt Disable Register */
-	AT91_REG	 DBGU_IMR; 	/* Interrupt Mask Register */
-	AT91_REG	 DBGU_CSR; 	/* Channel Status Register */
-	AT91_REG	 DBGU_RHR; 	/* Receiver Holding Register */
-	AT91_REG	 DBGU_THR; 	/* Transmitter Holding Register */
-	AT91_REG	 DBGU_BRGR; 	/* Baud Rate Generator Register */
-	AT91_REG	 Reserved0[7]; 	/*  */
-	AT91_REG	 DBGU_C1R; 	/* Chip ID1 Register */
-	AT91_REG	 DBGU_C2R; 	/* Chip ID2 Register */
-	AT91_REG	 DBGU_FNTR; 	/* Force NTRST Register */
-	AT91_REG	 Reserved1[45]; 	/*  */
-	AT91_REG	 DBGU_RPR; 	/* Receive Pointer Register */
-	AT91_REG	 DBGU_RCR; 	/* Receive Counter Register */
-	AT91_REG	 DBGU_TPR; 	/* Transmit Pointer Register */
-	AT91_REG	 DBGU_TCR; 	/* Transmit Counter Register */
-	AT91_REG	 DBGU_RNPR; 	/* Receive Next Pointer Register */
-	AT91_REG	 DBGU_RNCR; 	/* Receive Next Counter Register */
-	AT91_REG	 DBGU_TNPR; 	/* Transmit Next Pointer Register */
-	AT91_REG	 DBGU_TNCR; 	/* Transmit Next Counter Register */
-	AT91_REG	 DBGU_PTCR; 	/* PDC Transfer Control Register */
-	AT91_REG	 DBGU_PTSR; 	/* PDC Transfer Status Register */
+	AT91_REG	 DBGU_CR;	/* Control Register */
+	AT91_REG	 DBGU_MR;	/* Mode Register */
+	AT91_REG	 DBGU_IER;	/* Interrupt Enable Register */
+	AT91_REG	 DBGU_IDR;	/* Interrupt Disable Register */
+	AT91_REG	 DBGU_IMR;	/* Interrupt Mask Register */
+	AT91_REG	 DBGU_CSR;	/* Channel Status Register */
+	AT91_REG	 DBGU_RHR;	/* Receiver Holding Register */
+	AT91_REG	 DBGU_THR;	/* Transmitter Holding Register */
+	AT91_REG	 DBGU_BRGR;	/* Baud Rate Generator Register */
+	AT91_REG	 Reserved0[7];	/*  */
+	AT91_REG	 DBGU_C1R;	/* Chip ID1 Register */
+	AT91_REG	 DBGU_C2R;	/* Chip ID2 Register */
+	AT91_REG	 DBGU_FNTR;	/* Force NTRST Register */
+	AT91_REG	 Reserved1[45];	/*  */
+	AT91_REG	 DBGU_RPR;	/* Receive Pointer Register */
+	AT91_REG	 DBGU_RCR;	/* Receive Counter Register */
+	AT91_REG	 DBGU_TPR;	/* Transmit Pointer Register */
+	AT91_REG	 DBGU_TCR;	/* Transmit Counter Register */
+	AT91_REG	 DBGU_RNPR;	/* Receive Next Pointer Register */
+	AT91_REG	 DBGU_RNCR;	/* Receive Next Counter Register */
+	AT91_REG	 DBGU_TNPR;	/* Transmit Next Pointer Register */
+	AT91_REG	 DBGU_TNCR;	/* Transmit Next Counter Register */
+	AT91_REG	 DBGU_PTCR;	/* PDC Transfer Control Register */
+	AT91_REG	 DBGU_PTSR;	/* PDC Transfer Status Register */
 } AT91S_DBGU, *AT91PS_DBGU;
 
 /* -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register --------  */
@@ -247,7 +247,7 @@ typedef struct _AT91S_DBGU
 /*****************************************************************************/
 typedef struct _AT91S_SMC2
 {
-	AT91_REG	 SMC2_CSR[8]; 	/* SMC2 Chip Select Register */
+	AT91_REG	 SMC2_CSR[8];	/* SMC2 Chip Select Register */
 } AT91S_SMC2, *AT91PS_SMC2;
 
 /* -------- SMC2_CSR : (SMC2 Offset: 0x0) SMC2 Chip Select Register --------  */
@@ -272,21 +272,21 @@ typedef struct _AT91S_SMC2
 /*****************************************************************************/
 typedef struct _AT91S_PMC
 {
-	AT91_REG	 PMC_SCER; 	/* System Clock Enable Register */
-	AT91_REG	 PMC_SCDR; 	/* System Clock Disable Register */
-	AT91_REG	 PMC_SCSR; 	/* System Clock Status Register */
-	AT91_REG	 Reserved0[1]; 	/* */
-	AT91_REG	 PMC_PCER; 	/* Peripheral Clock Enable Register */
-	AT91_REG	 PMC_PCDR; 	/* Peripheral Clock Disable Register */
-	AT91_REG	 PMC_PCSR; 	/* Peripheral Clock Status Register */
-	AT91_REG	 Reserved1[5]; 	/* */
-	AT91_REG	 PMC_MCKR; 	/* Master Clock Register */
-	AT91_REG	 Reserved2[3]; 	/* */
-	AT91_REG	 PMC_PCKR[8]; 	/* Programmable Clock Register */
-	AT91_REG	 PMC_IER; 	/* Interrupt Enable Register */
-	AT91_REG	 PMC_IDR; 	/* Interrupt Disable Register */
-	AT91_REG	 PMC_SR; 	/* Status Register */
-	AT91_REG	 PMC_IMR; 	/* Interrupt Mask Register */
+	AT91_REG	 PMC_SCER;	/* System Clock Enable Register */
+	AT91_REG	 PMC_SCDR;	/* System Clock Disable Register */
+	AT91_REG	 PMC_SCSR;	/* System Clock Status Register */
+	AT91_REG	 Reserved0[1];	/* */
+	AT91_REG	 PMC_PCER;	/* Peripheral Clock Enable Register */
+	AT91_REG	 PMC_PCDR;	/* Peripheral Clock Disable Register */
+	AT91_REG	 PMC_PCSR;	/* Peripheral Clock Status Register */
+	AT91_REG	 Reserved1[5];	/* */
+	AT91_REG	 PMC_MCKR;	/* Master Clock Register */
+	AT91_REG	 Reserved2[3];	/* */
+	AT91_REG	 PMC_PCKR[8];	/* Programmable Clock Register */
+	AT91_REG	 PMC_IER;	/* Interrupt Enable Register */
+	AT91_REG	 PMC_IDR;	/* Interrupt Disable Register */
+	AT91_REG	 PMC_SR;	/* Status Register */
+	AT91_REG	 PMC_IMR;	/* Interrupt Mask Register */
 } AT91S_PMC, *AT91PS_PMC;
 
 /*------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------*/
@@ -346,49 +346,49 @@ typedef struct _AT91S_PMC
 /*****************************************************************************/
 typedef struct _AT91S_EMAC
 {
-	AT91_REG	 EMAC_CTL; 	/* Network Control Register */
-	AT91_REG	 EMAC_CFG; 	/* Network Configuration Register */
-	AT91_REG	 EMAC_SR; 	/* Network Status Register */
-	AT91_REG	 EMAC_TAR; 	/* Transmit Address Register */
-	AT91_REG	 EMAC_TCR; 	/* Transmit Control Register */
-	AT91_REG	 EMAC_TSR; 	/* Transmit Status Register */
-	AT91_REG	 EMAC_RBQP; 	/* Receive Buffer Queue Pointer */
-	AT91_REG	 Reserved0[1]; 	/*  */
-	AT91_REG	 EMAC_RSR; 	/* Receive Status Register */
-	AT91_REG	 EMAC_ISR; 	/* Interrupt Status Register */
-	AT91_REG	 EMAC_IER; 	/* Interrupt Enable Register */
-	AT91_REG	 EMAC_IDR; 	/* Interrupt Disable Register */
-	AT91_REG	 EMAC_IMR; 	/* Interrupt Mask Register */
-	AT91_REG	 EMAC_MAN; 	/* PHY Maintenance Register */
-	AT91_REG	 Reserved1[2]; 	/*  */
-	AT91_REG	 EMAC_FRA; 	/* Frames Transmitted OK Register */
-	AT91_REG	 EMAC_SCOL; 	/* Single Collision Frame Register */
-	AT91_REG	 EMAC_MCOL; 	/* Multiple Collision Frame Register */
-	AT91_REG	 EMAC_OK; 	/* Frames Received OK Register */
-	AT91_REG	 EMAC_SEQE; 	/* Frame Check Sequence Error Register */
-	AT91_REG	 EMAC_ALE; 	/* Alignment Error Register */
-	AT91_REG	 EMAC_DTE; 	/* Deferred Transmission Frame Register */
-	AT91_REG	 EMAC_LCOL; 	/* Late Collision Register */
-	AT91_REG	 EMAC_ECOL; 	/* Excessive Collision Register */
-	AT91_REG	 EMAC_CSE; 	/* Carrier Sense Error Register */
-	AT91_REG	 EMAC_TUE; 	/* Transmit Underrun Error Register */
-	AT91_REG	 EMAC_CDE; 	/* Code Error Register */
-	AT91_REG	 EMAC_ELR; 	/* Excessive Length Error Register */
-	AT91_REG	 EMAC_RJB; 	/* Receive Jabber Register */
-	AT91_REG	 EMAC_USF; 	/* Undersize Frame Register */
-	AT91_REG	 EMAC_SQEE; 	/* SQE Test Error Register */
-	AT91_REG	 EMAC_DRFC; 	/* Discarded RX Frame Register */
-	AT91_REG	 Reserved2[3]; 	/*  */
-	AT91_REG	 EMAC_HSH; 	/* Hash Address High[63:32] */
-	AT91_REG	 EMAC_HSL; 	/* Hash Address Low[31:0] */
-	AT91_REG	 EMAC_SA1L; 	/* Specific Address 1 Low, First 4 bytes */
-	AT91_REG	 EMAC_SA1H; 	/* Specific Address 1 High, Last 2 bytes */
-	AT91_REG	 EMAC_SA2L; 	/* Specific Address 2 Low, First 4 bytes */
-	AT91_REG	 EMAC_SA2H; 	/* Specific Address 2 High, Last 2 bytes */
-	AT91_REG	 EMAC_SA3L; 	/* Specific Address 3 Low, First 4 bytes */
-	AT91_REG	 EMAC_SA3H; 	/* Specific Address 3 High, Last 2 bytes */
-	AT91_REG	 EMAC_SA4L; 	/* Specific Address 4 Low, First 4 bytes */
-	AT91_REG	 EMAC_SA4H; 	/* Specific Address 4 High, Last 2 bytesr */
+	AT91_REG	 EMAC_CTL;	/* Network Control Register */
+	AT91_REG	 EMAC_CFG;	/* Network Configuration Register */
+	AT91_REG	 EMAC_SR;	/* Network Status Register */
+	AT91_REG	 EMAC_TAR;	/* Transmit Address Register */
+	AT91_REG	 EMAC_TCR;	/* Transmit Control Register */
+	AT91_REG	 EMAC_TSR;	/* Transmit Status Register */
+	AT91_REG	 EMAC_RBQP;	/* Receive Buffer Queue Pointer */
+	AT91_REG	 Reserved0[1];	/*  */
+	AT91_REG	 EMAC_RSR;	/* Receive Status Register */
+	AT91_REG	 EMAC_ISR;	/* Interrupt Status Register */
+	AT91_REG	 EMAC_IER;	/* Interrupt Enable Register */
+	AT91_REG	 EMAC_IDR;	/* Interrupt Disable Register */
+	AT91_REG	 EMAC_IMR;	/* Interrupt Mask Register */
+	AT91_REG	 EMAC_MAN;	/* PHY Maintenance Register */
+	AT91_REG	 Reserved1[2];	/*  */
+	AT91_REG	 EMAC_FRA;	/* Frames Transmitted OK Register */
+	AT91_REG	 EMAC_SCOL;	/* Single Collision Frame Register */
+	AT91_REG	 EMAC_MCOL;	/* Multiple Collision Frame Register */
+	AT91_REG	 EMAC_OK;	/* Frames Received OK Register */
+	AT91_REG	 EMAC_SEQE;	/* Frame Check Sequence Error Register */
+	AT91_REG	 EMAC_ALE;	/* Alignment Error Register */
+	AT91_REG	 EMAC_DTE;	/* Deferred Transmission Frame Register */
+	AT91_REG	 EMAC_LCOL;	/* Late Collision Register */
+	AT91_REG	 EMAC_ECOL;	/* Excessive Collision Register */
+	AT91_REG	 EMAC_CSE;	/* Carrier Sense Error Register */
+	AT91_REG	 EMAC_TUE;	/* Transmit Underrun Error Register */
+	AT91_REG	 EMAC_CDE;	/* Code Error Register */
+	AT91_REG	 EMAC_ELR;	/* Excessive Length Error Register */
+	AT91_REG	 EMAC_RJB;	/* Receive Jabber Register */
+	AT91_REG	 EMAC_USF;	/* Undersize Frame Register */
+	AT91_REG	 EMAC_SQEE;	/* SQE Test Error Register */
+	AT91_REG	 EMAC_DRFC;	/* Discarded RX Frame Register */
+	AT91_REG	 Reserved2[3];	/*  */
+	AT91_REG	 EMAC_HSH;	/* Hash Address High[63:32] */
+	AT91_REG	 EMAC_HSL;	/* Hash Address Low[31:0] */
+	AT91_REG	 EMAC_SA1L;	/* Specific Address 1 Low, First 4 bytes */
+	AT91_REG	 EMAC_SA1H;	/* Specific Address 1 High, Last 2 bytes */
+	AT91_REG	 EMAC_SA2L;	/* Specific Address 2 Low, First 4 bytes */
+	AT91_REG	 EMAC_SA2H;	/* Specific Address 2 High, Last 2 bytes */
+	AT91_REG	 EMAC_SA3L;	/* Specific Address 3 Low, First 4 bytes */
+	AT91_REG	 EMAC_SA3H;	/* Specific Address 3 High, Last 2 bytes */
+	AT91_REG	 EMAC_SA4L;	/* Specific Address 4 Low, First 4 bytes */
+	AT91_REG	 EMAC_SA4H;	/* Specific Address 4 High, Last 2 bytesr */
 } AT91S_EMAC, *AT91PS_EMAC;
 
 /* -------- EMAC_CTL : (EMAC Offset: 0x0)  --------  */
@@ -476,27 +476,27 @@ typedef struct _AT91S_EMAC
 /*****************************************************************************/
 typedef struct _AT91S_SPI
 {
-	AT91_REG	 SPI_CR; 	/* Control Register */
-	AT91_REG	 SPI_MR; 	/* Mode Register */
-	AT91_REG	 SPI_RDR; 	/* Receive Data Register */
-	AT91_REG	 SPI_TDR; 	/* Transmit Data Register */
-	AT91_REG	 SPI_SR; 	/* Status Register */
-	AT91_REG	 SPI_IER; 	/* Interrupt Enable Register */
-	AT91_REG	 SPI_IDR; 	/* Interrupt Disable Register */
-	AT91_REG	 SPI_IMR; 	/* Interrupt Mask Register */
-	AT91_REG	 Reserved0[4]; 	/* */
-	AT91_REG	 SPI_CSR[4]; 	/* Chip Select Register */
+	AT91_REG	 SPI_CR;	/* Control Register */
+	AT91_REG	 SPI_MR;	/* Mode Register */
+	AT91_REG	 SPI_RDR;	/* Receive Data Register */
+	AT91_REG	 SPI_TDR;	/* Transmit Data Register */
+	AT91_REG	 SPI_SR;	/* Status Register */
+	AT91_REG	 SPI_IER;	/* Interrupt Enable Register */
+	AT91_REG	 SPI_IDR;	/* Interrupt Disable Register */
+	AT91_REG	 SPI_IMR;	/* Interrupt Mask Register */
+	AT91_REG	 Reserved0[4];	/* */
+	AT91_REG	 SPI_CSR[4];	/* Chip Select Register */
 	AT91_REG	 Reserved1[48]; /* */
-	AT91_REG	 SPI_RPR; 	/* Receive Pointer Register */
-	AT91_REG	 SPI_RCR; 	/* Receive Counter Register */
-	AT91_REG	 SPI_TPR; 	/* Transmit Pointer Register */
-	AT91_REG	 SPI_TCR; 	/* Transmit Counter Register */
-	AT91_REG	 SPI_RNPR; 	/* Receive Next Pointer Register */
-	AT91_REG	 SPI_RNCR; 	/* Receive Next Counter Register */
-	AT91_REG	 SPI_TNPR; 	/* Transmit Next Pointer Register */
-	AT91_REG	 SPI_TNCR; 	/* Transmit Next Counter Register */
-	AT91_REG	 SPI_PTCR; 	/* PDC Transfer Control Register */
-	AT91_REG	 SPI_PTSR; 	/* PDC Transfer Status Register */
+	AT91_REG	 SPI_RPR;	/* Receive Pointer Register */
+	AT91_REG	 SPI_RCR;	/* Receive Counter Register */
+	AT91_REG	 SPI_TPR;	/* Transmit Pointer Register */
+	AT91_REG	 SPI_TCR;	/* Transmit Counter Register */
+	AT91_REG	 SPI_RNPR;	/* Receive Next Pointer Register */
+	AT91_REG	 SPI_RNCR;	/* Receive Next Counter Register */
+	AT91_REG	 SPI_TNPR;	/* Transmit Next Pointer Register */
+	AT91_REG	 SPI_TNCR;	/* Transmit Next Counter Register */
+	AT91_REG	 SPI_PTCR;	/* PDC Transfer Control Register */
+	AT91_REG	 SPI_PTSR;	/* PDC Transfer Status Register */
 } AT91S_SPI, *AT91PS_SPI;
 
 /* -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- */
@@ -560,16 +560,16 @@ typedef struct _AT91S_SPI
 /*****************************************************************************/
 typedef struct _AT91S_PDC
 {
-	AT91_REG	 PDC_RPR; 	/* Receive Pointer Register */
-	AT91_REG	 PDC_RCR; 	/* Receive Counter Register */
-	AT91_REG	 PDC_TPR; 	/* Transmit Pointer Register */
-	AT91_REG	 PDC_TCR; 	/* Transmit Counter Register */
-	AT91_REG	 PDC_RNPR; 	/* Receive Next Pointer Register */
-	AT91_REG	 PDC_RNCR; 	/* Receive Next Counter Register */
-	AT91_REG	 PDC_TNPR; 	/* Transmit Next Pointer Register */
-	AT91_REG	 PDC_TNCR; 	/* Transmit Next Counter Register */
-	AT91_REG	 PDC_PTCR; 	/* PDC Transfer Control Register */
-	AT91_REG	 PDC_PTSR; 	/* PDC Transfer Status Register */
+	AT91_REG	 PDC_RPR;	/* Receive Pointer Register */
+	AT91_REG	 PDC_RCR;	/* Receive Counter Register */
+	AT91_REG	 PDC_TPR;	/* Transmit Pointer Register */
+	AT91_REG	 PDC_TCR;	/* Transmit Counter Register */
+	AT91_REG	 PDC_RNPR;	/* Receive Next Pointer Register */
+	AT91_REG	 PDC_RNCR;	/* Receive Next Counter Register */
+	AT91_REG	 PDC_TNPR;	/* Transmit Next Pointer Register */
+	AT91_REG	 PDC_TNCR;	/* Transmit Next Counter Register */
+	AT91_REG	 PDC_PTCR;	/* PDC Transfer Control Register */
+	AT91_REG	 PDC_PTSR;	/* PDC Transfer Status Register */
 } AT91S_PDC, *AT91PS_PDC;
 
 /* -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- */
@@ -700,7 +700,7 @@ typedef struct _AT91S_PDC
 #define AT91C_PIO_PB5		((unsigned int) 1 <<  5)	/* Pin Controlled by PB5 */
 #define AT91C_PIO_PB6		((unsigned int) 1 <<  6)	/* Pin Controlled by PB6 */
 #define AT91C_PIO_PB7		((unsigned int) 1 <<  7)	/* Pin Controlled by PB7 */
-#define AT91C_PIO_PB22		((unsigned int) 1 << 22) 	/* Pin Controlled by PB22 */
+#define AT91C_PIO_PB22		((unsigned int) 1 << 22)	/* Pin Controlled by PB22 */
 #define AT91C_PIO_PB25		((unsigned int) 1 << 25)	/* Pin Controlled by PB25 */
 #define AT91C_PB25_DSR1		((unsigned int) AT91C_PIO_PB25)	/* USART 1 Data Set ready */
 #define AT91C_PB25_EF100	((unsigned int) AT91C_PIO_PB25)	/* Ethernet MAC Force 100 Mbits */
@@ -775,7 +775,7 @@ typedef struct _AT91S_PDC
 #define AT91C_TCB0_BCR		((AT91_REG *)	0xFFFA00C0) /* (TCB0) TC Block Control Register */
 #define AT91C_PIOC_PDR		((AT91_REG *)	0xFFFFF804) /* (PIOC) PIO Disable Register */
 #define AT91C_PIOC_PER		((AT91_REG *)	0xFFFFF800) /* (PIOC) PIO Enable Register */
-#define AT91C_PIOC_ODR  	((AT91_REG *)	0xFFFFF814) /* (PIOC) Output Disable Registerr */
+#define AT91C_PIOC_ODR		((AT91_REG *)	0xFFFFF814) /* (PIOC) Output Disable Registerr */
 #define AT91C_PIOB_PER		((AT91_REG *)	0xFFFFF600) /* (PIOB) PIO Enable Register */
 #define AT91C_PIOB_ODR		((AT91_REG *)	0xFFFFF614) /* (PIOB) Output Disable Registerr */
 #define AT91C_PIOB_PDSR		((AT91_REG *)	0xFFFFF63C) /* (PIOB) Pin Data Status Register */
diff --git a/include/asm-arm/arch-at91sam9/gpio.h b/include/asm-arm/arch-at91sam9/gpio.h
index c157e107e1..c4d7b971be 100644
--- a/include/asm-arm/arch-at91sam9/gpio.h
+++ b/include/asm-arm/arch-at91sam9/gpio.h
@@ -218,7 +218,7 @@ static inline unsigned pin_to_mask(unsigned pin)
  */
 static inline int at91_set_GPIO_periph(unsigned pin, int use_pullup)
 {
-	void 		*pio = pin_to_controller(pin);
+	void		*pio = pin_to_controller(pin);
 	unsigned	mask = pin_to_mask(pin);
 
 	__raw_writel(mask, pio + PIO_IDR);
@@ -232,7 +232,7 @@ static inline int at91_set_GPIO_periph(unsigned pin, int use_pullup)
  */
 static inline int at91_set_A_periph(unsigned pin, int use_pullup)
 {
-	void 		*pio = pin_to_controller(pin);
+	void		*pio = pin_to_controller(pin);
 	unsigned	mask = pin_to_mask(pin);
 
 	__raw_writel(mask, pio + PIO_IDR);
diff --git a/include/asm-arm/arch-ixp/ixp425.h b/include/asm-arm/arch-ixp/ixp425.h
index 11dc356a92..2114437dc7 100644
--- a/include/asm-arm/arch-ixp/ixp425.h
+++ b/include/asm-arm/arch-ixp/ixp425.h
@@ -53,13 +53,13 @@
  *
  * 0x6000000	0x00004000	    0x4000	0xFFFEB000	QMgr
  *
- * 0xC0000000	     0x100   	    0x1000	0xFFFDD000	PCI CFG
+ * 0xC0000000	     0x100	    0x1000	0xFFFDD000	PCI CFG
  *
  * 0xC4000000	     0x100          0x1000	0xFFFDE000	EXP CFG
  *
  * 0xC8000000	    0xC000          0xC000	0xFFFDF000	PERIPHERAL
  *
- * 0xCC000000	     0x100   	    0x1000	Not Mapped	SDRAM CFG
+ * 0xCC000000	     0x100	    0x1000	Not Mapped	SDRAM CFG
  */
 
 /*
@@ -171,17 +171,17 @@
 #define IXP425_SDR_REFRESH_OFFSET	0x04
 #define IXP425_SDR_IR_OFFSET		0x08
 
-#define IXP425_SDRAM_REG(x) 	(IXP425_SDRAM_CFG_BASE_PHYS+(x))
+#define IXP425_SDRAM_REG(x)	(IXP425_SDRAM_CFG_BASE_PHYS+(x))
 
 #define IXP425_SDR_CONFIG	IXP425_SDRAM_REG(IXP425_SDR_CONFIG_OFFSET)
-#define IXP425_SDR_REFRESH     	IXP425_SDRAM_REG(IXP425_SDR_REFRESH_OFFSET)
-#define IXP425_SDR_IR     	IXP425_SDRAM_REG(IXP425_SDR_IR_OFFSET)
+#define IXP425_SDR_REFRESH	IXP425_SDRAM_REG(IXP425_SDR_REFRESH_OFFSET)
+#define IXP425_SDR_IR		IXP425_SDRAM_REG(IXP425_SDR_IR_OFFSET)
 
 /*
  * UART registers
  */
-#define IXP425_UART1	0
-#define IXP425_UART2	0x1000
+#define IXP425_UART1		0
+#define IXP425_UART2		0x1000
 
 #define IXP425_UART_RBR_OFFSET	0x00
 #define IXP425_UART_THR_OFFSET	0x00
@@ -476,49 +476,49 @@
  */
 
 /* CSR bit definitions */
-#define PCI_CSR_HOST    	BIT(0)
-#define PCI_CSR_ARBEN   	BIT(1)
-#define PCI_CSR_ADS     	BIT(2)
-#define PCI_CSR_PDS     	BIT(3)
-#define PCI_CSR_ABE     	BIT(4)
-#define PCI_CSR_DBT     	BIT(5)
-#define PCI_CSR_ASE     	BIT(8)
-#define PCI_CSR_IC      	BIT(15)
+#define PCI_CSR_HOST		BIT(0)
+#define PCI_CSR_ARBEN		BIT(1)
+#define PCI_CSR_ADS		BIT(2)
+#define PCI_CSR_PDS		BIT(3)
+#define PCI_CSR_ABE		BIT(4)
+#define PCI_CSR_DBT		BIT(5)
+#define PCI_CSR_ASE		BIT(8)
+#define PCI_CSR_IC		BIT(15)
 
 /* ISR (Interrupt status) Register bit definitions */
-#define PCI_ISR_PSE     	BIT(0)
-#define PCI_ISR_PFE     	BIT(1)
-#define PCI_ISR_PPE     	BIT(2)
-#define PCI_ISR_AHBE    	BIT(3)
-#define PCI_ISR_APDC    	BIT(4)
-#define PCI_ISR_PADC    	BIT(5)
-#define PCI_ISR_ADB     	BIT(6)
-#define PCI_ISR_PDB     	BIT(7)
+#define PCI_ISR_PSE		BIT(0)
+#define PCI_ISR_PFE		BIT(1)
+#define PCI_ISR_PPE		BIT(2)
+#define PCI_ISR_AHBE		BIT(3)
+#define PCI_ISR_APDC		BIT(4)
+#define PCI_ISR_PADC		BIT(5)
+#define PCI_ISR_ADB		BIT(6)
+#define PCI_ISR_PDB		BIT(7)
 
 /* INTEN (Interrupt Enable) Register bit definitions */
-#define PCI_INTEN_PSE   	BIT(0)
-#define PCI_INTEN_PFE   	BIT(1)
-#define PCI_INTEN_PPE   	BIT(2)
-#define PCI_INTEN_AHBE  	BIT(3)
-#define PCI_INTEN_APDC  	BIT(4)
-#define PCI_INTEN_PADC  	BIT(5)
-#define PCI_INTEN_ADB   	BIT(6)
-#define PCI_INTEN_PDB   	BIT(7)
+#define PCI_INTEN_PSE		BIT(0)
+#define PCI_INTEN_PFE		BIT(1)
+#define PCI_INTEN_PPE		BIT(2)
+#define PCI_INTEN_AHBE		BIT(3)
+#define PCI_INTEN_APDC		BIT(4)
+#define PCI_INTEN_PADC		BIT(5)
+#define PCI_INTEN_ADB		BIT(6)
+#define PCI_INTEN_PDB		BIT(7)
 
 /*
  * Shift value for byte enable on NP cmd/byte enable register
  */
-#define IXP425_PCI_NP_CBE_BESL		4
+#define IXP425_PCI_NP_CBE_BESL	4
 
 /*
  * PCI commands supported by NP access unit
  */
-#define NP_CMD_IOREAD			0x2
-#define NP_CMD_IOWRITE			0x3
-#define NP_CMD_CONFIGREAD		0xa
-#define NP_CMD_CONFIGWRITE		0xb
-#define NP_CMD_MEMREAD			0x6
-#define	NP_CMD_MEMWRITE			0x7
+#define NP_CMD_IOREAD		0x2
+#define NP_CMD_IOWRITE		0x3
+#define NP_CMD_CONFIGREAD	0xa
+#define NP_CMD_CONFIGWRITE	0xb
+#define NP_CMD_MEMREAD		0x6
+#define	NP_CMD_MEMWRITE		0x7
 
 #if 0
 #ifndef __ASSEMBLY__
diff --git a/include/asm-arm/arch-omap24xx/clocks.h b/include/asm-arm/arch-omap24xx/clocks.h
index 2a95af1810..2e92569a9c 100644
--- a/include/asm-arm/arch-omap24xx/clocks.h
+++ b/include/asm-arm/arch-omap24xx/clocks.h
@@ -35,9 +35,9 @@
 ; PRCM Scheme II
 ;
 ; Enable clocks and DPLL for:
-;  DPLL=300, 	DPLLout=600   	M=1,N=50   CM_CLKSEL1_PLL[21:8]  12/2*50
-;  Core=600  	(core domain)   DPLLx2     CM_CLKSEL2_PLL[1:0]
-;  MPUF=300   	(mpu domain)    2          CM_CLKSEL_MPU[4:0]
+;  DPLL=300,	DPLLout=600	M=1,N=50   CM_CLKSEL1_PLL[21:8]  12/2*50
+;  Core=600	(core domain)   DPLLx2     CM_CLKSEL2_PLL[1:0]
+;  MPUF=300	(mpu domain)    2          CM_CLKSEL_MPU[4:0]
 ;  DSPF=200    (dsp domain)    3          CM_CLKSEL_DSP[4:0]
 ;  DSPI=100                    6          CM_CLKSEL_DSP[6:5]
 ;  DSP_S          bypass	               CM_CLKSEL_DSP[7]
@@ -64,9 +64,9 @@
 ; PRCM Scheme III
 ;
 ; Enable clocks and DPLL for:
-;  DPLL=266, 	DPLLout=532   	M=5+1,N=133 CM_CLKSEL1_PLL[21:8]  12/6*133=266
-;  Core=532  	(core domain)   DPLLx2      CM_CLKSEL2_PLL[1:0]
-;  MPUF=266   	(mpu domain)    /2          CM_CLKSEL_MPU[4:0]
+;  DPLL=266,	DPLLout=532	M=5+1,N=133 CM_CLKSEL1_PLL[21:8]  12/6*133=266
+;  Core=532	(core domain)   DPLLx2      CM_CLKSEL2_PLL[1:0]
+;  MPUF=266	(mpu domain)    /2          CM_CLKSEL_MPU[4:0]
 ;  DSPF=177.3     (dsp domain)  /3          CM_CLKSEL_DSP[4:0]
 ;  DSPI=88.67                   /6          CM_CLKSEL_DSP[6:5]
 ;  DSP_S         ACTIVATED	            CM_CLKSEL_DSP[7]
diff --git a/include/asm-arm/arch-pxa/bitfield.h b/include/asm-arm/arch-pxa/bitfield.h
index 2ac5ea21cf..104a21c2e4 100644
--- a/include/asm-arm/arch-pxa/bitfield.h
+++ b/include/asm-arm/arch-pxa/bitfield.h
@@ -1,13 +1,13 @@
 /*
- *	FILE    	bitfield.h
+ *	FILE		bitfield.h
  *
- *	Version 	1.1
- *	Author  	Copyright (c) Marc A. Viredaz, 1998
- *	        	DEC Western Research Laboratory, Palo Alto, CA
- *	Date    	April 1998 (April 1997)
- *	System  	Advanced RISC Machine (ARM)
+ *	Version		1.1
+ *	Author		Copyright (c) Marc A. Viredaz, 1998
+ *			DEC Western Research Laboratory, Palo Alto, CA
+ *	Date		April 1998 (April 1997)
+ *	System		Advanced RISC Machine (ARM)
  *	Language	C or ARM Assembly
- *	Purpose 	Definition of macros to operate on bit fields.
+ *	Purpose		Definition of macros to operate on bit fields.
  */
 
 
@@ -35,11 +35,11 @@
  *    line-size limit).
  *
  * Input
- *    Size      	Size of the bit field, in number of bits.
- *    Shft      	Shift value of the bit field with respect to bit 0.
+ *    Size		Size of the bit field, in number of bits.
+ *    Shft		Shift value of the bit field with respect to bit 0.
  *
  * Output
- *    Fld       	Encoded bit field.
+ *    Fld		Encoded bit field.
  */
 
 #define Fld(Size, Shft)	(((Size) << 16) + (Shft))
@@ -54,14 +54,14 @@
  *    bit field.
  *
  * Input
- *    Field     	Encoded bit field (using the macro "Fld").
+ *    Field		Encoded bit field (using the macro "Fld").
  *
  * Output
- *    FSize     	Size of the bit field, in number of bits.
- *    FShft     	Shift value of the bit field with respect to bit 0.
- *    FMsk      	Mask for the bit field.
- *    FAlnMsk   	Mask for the bit field, aligned on bit 0.
- *    F1stBit   	First bit of the bit field.
+ *    FSize		Size of the bit field, in number of bits.
+ *    FShft		Shift value of the bit field with respect to bit 0.
+ *    FMsk		Mask for the bit field.
+ *    FAlnMsk		Mask for the bit field, aligned on bit 0.
+ *    F1stBit		First bit of the bit field.
  */
 
 #define FSize(Field)	((Field) >> 16)
@@ -79,11 +79,11 @@
  *    former appropriately.
  *
  * Input
- *    Value     	Bit-field value.
- *    Field     	Encoded bit field (using the macro "Fld").
+ *    Value		Bit-field value.
+ *    Field		Encoded bit field (using the macro "Fld").
  *
  * Output
- *    FInsrt    	Bit-field value positioned appropriately.
+ *    FInsrt		Bit-field value positioned appropriately.
  */
 
 #define FInsrt(Value, Field) \
@@ -98,11 +98,11 @@
  *    shifting it appropriately.
  *
  * Input
- *    Data      	Data containing the bit-field to be extracted.
- *    Field     	Encoded bit field (using the macro "Fld").
+ *    Data		Data containing the bit-field to be extracted.
+ *    Field		Encoded bit field (using the macro "Fld").
  *
  * Output
- *    FExtr     	Bit-field value.
+ *    FExtr		Bit-field value.
  */
 
 #define FExtr(Data, Field) \
diff --git a/include/asm-arm/arch-pxa/mmc.h b/include/asm-arm/arch-pxa/mmc.h
index b9304b1bdc..9440d80b50 100644
--- a/include/asm-arm/arch-pxa/mmc.h
+++ b/include/asm-arm/arch-pxa/mmc.h
@@ -16,95 +16,95 @@
 /* PXA-250 MMC controller registers */
 
 /* MMC_STRPCL */
-#define MMC_STRPCL_STOP_CLK     	(0x0001UL)
+#define MMC_STRPCL_STOP_CLK		(0x0001UL)
 #define MMC_STRPCL_START_CLK		(0x0002UL)
 
 /* MMC_STAT */
 #define MMC_STAT_END_CMD_RES		(0x0001UL << 13)
-#define MMC_STAT_PRG_DONE       	(0x0001UL << 12)
-#define MMC_STAT_DATA_TRAN_DONE     	(0x0001UL << 11)
-#define MMC_STAT_CLK_EN	 		(0x0001UL << 8)
-#define MMC_STAT_RECV_FIFO_FULL     	(0x0001UL << 7)
-#define MMC_STAT_XMIT_FIFO_EMPTY    	(0x0001UL << 6)
-#define MMC_STAT_RES_CRC_ERROR      	(0x0001UL << 5)
+#define MMC_STAT_PRG_DONE		(0x0001UL << 12)
+#define MMC_STAT_DATA_TRAN_DONE		(0x0001UL << 11)
+#define MMC_STAT_CLK_EN			(0x0001UL << 8)
+#define MMC_STAT_RECV_FIFO_FULL		(0x0001UL << 7)
+#define MMC_STAT_XMIT_FIFO_EMPTY	(0x0001UL << 6)
+#define MMC_STAT_RES_CRC_ERROR		(0x0001UL << 5)
 #define MMC_STAT_SPI_READ_ERROR_TOKEN   (0x0001UL << 4)
-#define MMC_STAT_CRC_READ_ERROR     	(0x0001UL << 3)
-#define MMC_STAT_CRC_WRITE_ERROR    	(0x0001UL << 2)
-#define MMC_STAT_TIME_OUT_RESPONSE  	(0x0001UL << 1)
-#define MMC_STAT_READ_TIME_OUT      	(0x0001UL)
+#define MMC_STAT_CRC_READ_ERROR		(0x0001UL << 3)
+#define MMC_STAT_CRC_WRITE_ERROR	(0x0001UL << 2)
+#define MMC_STAT_TIME_OUT_RESPONSE	(0x0001UL << 1)
+#define MMC_STAT_READ_TIME_OUT		(0x0001UL)
 
 #define MMC_STAT_ERRORS (MMC_STAT_RES_CRC_ERROR|MMC_STAT_SPI_READ_ERROR_TOKEN\
 	|MMC_STAT_CRC_READ_ERROR|MMC_STAT_TIME_OUT_RESPONSE\
 	|MMC_STAT_READ_TIME_OUT|MMC_STAT_CRC_WRITE_ERROR)
 
 /* MMC_CLKRT */
-#define MMC_CLKRT_20MHZ	 		(0x0000UL)
-#define MMC_CLKRT_10MHZ	 		(0x0001UL)
-#define MMC_CLKRT_5MHZ	  		(0x0002UL)
+#define MMC_CLKRT_20MHZ			(0x0000UL)
+#define MMC_CLKRT_10MHZ			(0x0001UL)
+#define MMC_CLKRT_5MHZ			(0x0002UL)
 #define MMC_CLKRT_2_5MHZ		(0x0003UL)
-#define MMC_CLKRT_1_25MHZ       	(0x0004UL)
-#define MMC_CLKRT_0_625MHZ      	(0x0005UL)
-#define MMC_CLKRT_0_3125MHZ     	(0x0006UL)
+#define MMC_CLKRT_1_25MHZ		(0x0004UL)
+#define MMC_CLKRT_0_625MHZ		(0x0005UL)
+#define MMC_CLKRT_0_3125MHZ		(0x0006UL)
 
 /* MMC_SPI */
-#define MMC_SPI_DISABLE	 		(0x00UL)
-#define MMC_SPI_EN	  		(0x01UL)
-#define MMC_SPI_CS_EN	   		(0x01UL << 2)
-#define MMC_SPI_CS_ADDRESS      	(0x01UL << 3)
-#define MMC_SPI_CRC_ON	  		(0x01UL << 1)
+#define MMC_SPI_DISABLE			(0x00UL)
+#define MMC_SPI_EN			(0x01UL)
+#define MMC_SPI_CS_EN			(0x01UL << 2)
+#define MMC_SPI_CS_ADDRESS		(0x01UL << 3)
+#define MMC_SPI_CRC_ON			(0x01UL << 1)
 
 /* MMC_CMDAT */
 #define MMC_CMDAT_SD_4DAT		(0x0001UL << 8)
 #define MMC_CMDAT_MMC_DMA_EN		(0x0001UL << 7)
-#define MMC_CMDAT_INIT	  		(0x0001UL << 6)
-#define MMC_CMDAT_BUSY	  		(0x0001UL << 5)
-#define MMC_CMDAT_BCR	  		(0x0003UL << 5)
+#define MMC_CMDAT_INIT			(0x0001UL << 6)
+#define MMC_CMDAT_BUSY			(0x0001UL << 5)
+#define MMC_CMDAT_BCR			(0x0003UL << 5)
 #define MMC_CMDAT_STREAM		(0x0001UL << 4)
-#define MMC_CMDAT_BLOCK	 		(0x0000UL << 4)
-#define MMC_CMDAT_WRITE	 		(0x0001UL << 3)
-#define MMC_CMDAT_READ	  		(0x0000UL << 3)
-#define MMC_CMDAT_DATA_EN       	(0x0001UL << 2)
-#define MMC_CMDAT_R0	    		(0)
-#define MMC_CMDAT_R1	    		(0x0001UL)
-#define MMC_CMDAT_R2	    		(0x0002UL)
-#define MMC_CMDAT_R3	    		(0x0003UL)
+#define MMC_CMDAT_BLOCK			(0x0000UL << 4)
+#define MMC_CMDAT_WRITE			(0x0001UL << 3)
+#define MMC_CMDAT_READ			(0x0000UL << 3)
+#define MMC_CMDAT_DATA_EN		(0x0001UL << 2)
+#define MMC_CMDAT_R0			(0)
+#define MMC_CMDAT_R1			(0x0001UL)
+#define MMC_CMDAT_R2			(0x0002UL)
+#define MMC_CMDAT_R3			(0x0003UL)
 
 /* MMC_RESTO */
-#define MMC_RES_TO_MAX	  		(0x007fUL) /* [6:0] */
+#define MMC_RES_TO_MAX			(0x007fUL) /* [6:0] */
 
 /* MMC_RDTO */
-#define MMC_READ_TO_MAX	 		(0x0ffffUL) /* [15:0] */
+#define MMC_READ_TO_MAX			(0x0ffffUL) /* [15:0] */
 
 /* MMC_BLKLEN */
-#define MMC_BLK_LEN_MAX	 		(0x03ffUL) /* [9:0] */
+#define MMC_BLK_LEN_MAX			(0x03ffUL) /* [9:0] */
 
 /* MMC_PRTBUF */
-#define MMC_PRTBUF_BUF_PART_FULL       	(0x01UL)
+#define MMC_PRTBUF_BUF_PART_FULL	(0x01UL)
 #define MMC_PRTBUF_BUF_FULL		(0x00UL    )
 
 /* MMC_I_MASK */
 #define MMC_I_MASK_TXFIFO_WR_REQ	(0x01UL << 6)
 #define MMC_I_MASK_RXFIFO_RD_REQ	(0x01UL << 5)
-#define MMC_I_MASK_CLK_IS_OFF	   	(0x01UL << 4)
-#define MMC_I_MASK_STOP_CMD	 	(0x01UL << 3)
-#define MMC_I_MASK_END_CMD_RES	  	(0x01UL << 2)
-#define MMC_I_MASK_PRG_DONE	 	(0x01UL << 1)
+#define MMC_I_MASK_CLK_IS_OFF		(0x01UL << 4)
+#define MMC_I_MASK_STOP_CMD		(0x01UL << 3)
+#define MMC_I_MASK_END_CMD_RES		(0x01UL << 2)
+#define MMC_I_MASK_PRG_DONE		(0x01UL << 1)
 #define MMC_I_MASK_DATA_TRAN_DONE       (0x01UL)
-#define MMC_I_MASK_ALL	      		(0x07fUL)
+#define MMC_I_MASK_ALL			(0x07fUL)
 
 
 /* MMC_I_REG */
-#define MMC_I_REG_TXFIFO_WR_REQ     	(0x01UL << 6)
-#define MMC_I_REG_RXFIFO_RD_REQ     	(0x01UL << 5)
+#define MMC_I_REG_TXFIFO_WR_REQ		(0x01UL << 6)
+#define MMC_I_REG_RXFIFO_RD_REQ		(0x01UL << 5)
 #define MMC_I_REG_CLK_IS_OFF		(0x01UL << 4)
-#define MMC_I_REG_STOP_CMD      	(0x01UL << 3)
-#define MMC_I_REG_END_CMD_RES       	(0x01UL << 2)
-#define MMC_I_REG_PRG_DONE      	(0x01UL << 1)
-#define MMC_I_REG_DATA_TRAN_DONE    	(0x01UL)
-#define MMC_I_REG_ALL	   		(0x007fUL)
+#define MMC_I_REG_STOP_CMD		(0x01UL << 3)
+#define MMC_I_REG_END_CMD_RES		(0x01UL << 2)
+#define MMC_I_REG_PRG_DONE		(0x01UL << 1)
+#define MMC_I_REG_DATA_TRAN_DONE	(0x01UL)
+#define MMC_I_REG_ALL			(0x007fUL)
 
 /* MMC_CMD */
-#define MMC_CMD_INDEX_MAX       	(0x006fUL)  /* [5:0] */
+#define MMC_CMD_INDEX_MAX		(0x006fUL)  /* [5:0] */
 #define CMD(x)  (x)
 
 #define MMC_DEFAULT_RCA			1
@@ -112,11 +112,11 @@
 #define MMC_BLOCK_SIZE			512
 #define MMC_CMD_RESET			0
 #define MMC_CMD_SEND_OP_COND		1
-#define MMC_CMD_ALL_SEND_CID 		2
+#define MMC_CMD_ALL_SEND_CID		2
 #define MMC_CMD_SET_RCA			3
 #define MMC_CMD_SELECT_CARD		7
-#define MMC_CMD_SEND_CSD 		9
-#define MMC_CMD_SEND_CID 		10
+#define MMC_CMD_SEND_CSD		9
+#define MMC_CMD_SEND_CID		10
 #define MMC_CMD_SEND_STATUS		13
 #define MMC_CMD_SET_BLOCKLEN		16
 #define MMC_CMD_READ_BLOCK		17
@@ -203,5 +203,4 @@ typedef struct mmc_csd
 			ecc:2;
 } mmc_csd_t;
 
-
 #endif /* __MMC_PXA_P_H__ */
diff --git a/include/asm-arm/arch-s3c24x0/memory.h b/include/asm-arm/arch-s3c24x0/memory.h
index 333f218679..5e254d2356 100644
--- a/include/asm-arm/arch-s3c24x0/memory.h
+++ b/include/asm-arm/arch-s3c24x0/memory.h
@@ -103,10 +103,10 @@ extern unsigned long __phys_to_virt(unsigned long ppage);
  * The nodes are matched with the physical memory bank addresses which are
  * incidentally the same as virtual addresses.
  *
- * 	node 0:  0xc0000000 - 0xc7ffffff
- * 	node 1:  0xc8000000 - 0xcfffffff
- * 	node 2:  0xd0000000 - 0xd7ffffff
- * 	node 3:  0xd8000000 - 0xdfffffff
+ *	node 0:  0xc0000000 - 0xc7ffffff
+ *	node 1:  0xc8000000 - 0xcfffffff
+ *	node 2:  0xd0000000 - 0xd7ffffff
+ *	node 3:  0xd8000000 - 0xdfffffff
  */
 
 #define NR_NODES	4
diff --git a/include/asm-arm/arch-sa1100/bitfield.h b/include/asm-arm/arch-sa1100/bitfield.h
index 2ac5ea21cf..104a21c2e4 100644
--- a/include/asm-arm/arch-sa1100/bitfield.h
+++ b/include/asm-arm/arch-sa1100/bitfield.h
@@ -1,13 +1,13 @@
 /*
- *	FILE    	bitfield.h
+ *	FILE		bitfield.h
  *
- *	Version 	1.1
- *	Author  	Copyright (c) Marc A. Viredaz, 1998
- *	        	DEC Western Research Laboratory, Palo Alto, CA
- *	Date    	April 1998 (April 1997)
- *	System  	Advanced RISC Machine (ARM)
+ *	Version		1.1
+ *	Author		Copyright (c) Marc A. Viredaz, 1998
+ *			DEC Western Research Laboratory, Palo Alto, CA
+ *	Date		April 1998 (April 1997)
+ *	System		Advanced RISC Machine (ARM)
  *	Language	C or ARM Assembly
- *	Purpose 	Definition of macros to operate on bit fields.
+ *	Purpose		Definition of macros to operate on bit fields.
  */
 
 
@@ -35,11 +35,11 @@
  *    line-size limit).
  *
  * Input
- *    Size      	Size of the bit field, in number of bits.
- *    Shft      	Shift value of the bit field with respect to bit 0.
+ *    Size		Size of the bit field, in number of bits.
+ *    Shft		Shift value of the bit field with respect to bit 0.
  *
  * Output
- *    Fld       	Encoded bit field.
+ *    Fld		Encoded bit field.
  */
 
 #define Fld(Size, Shft)	(((Size) << 16) + (Shft))
@@ -54,14 +54,14 @@
  *    bit field.
  *
  * Input
- *    Field     	Encoded bit field (using the macro "Fld").
+ *    Field		Encoded bit field (using the macro "Fld").
  *
  * Output
- *    FSize     	Size of the bit field, in number of bits.
- *    FShft     	Shift value of the bit field with respect to bit 0.
- *    FMsk      	Mask for the bit field.
- *    FAlnMsk   	Mask for the bit field, aligned on bit 0.
- *    F1stBit   	First bit of the bit field.
+ *    FSize		Size of the bit field, in number of bits.
+ *    FShft		Shift value of the bit field with respect to bit 0.
+ *    FMsk		Mask for the bit field.
+ *    FAlnMsk		Mask for the bit field, aligned on bit 0.
+ *    F1stBit		First bit of the bit field.
  */
 
 #define FSize(Field)	((Field) >> 16)
@@ -79,11 +79,11 @@
  *    former appropriately.
  *
  * Input
- *    Value     	Bit-field value.
- *    Field     	Encoded bit field (using the macro "Fld").
+ *    Value		Bit-field value.
+ *    Field		Encoded bit field (using the macro "Fld").
  *
  * Output
- *    FInsrt    	Bit-field value positioned appropriately.
+ *    FInsrt		Bit-field value positioned appropriately.
  */
 
 #define FInsrt(Value, Field) \
@@ -98,11 +98,11 @@
  *    shifting it appropriately.
  *
  * Input
- *    Data      	Data containing the bit-field to be extracted.
- *    Field     	Encoded bit field (using the macro "Fld").
+ *    Data		Data containing the bit-field to be extracted.
+ *    Field		Encoded bit field (using the macro "Fld").
  *
  * Output
- *    FExtr     	Bit-field value.
+ *    FExtr		Bit-field value.
  */
 
 #define FExtr(Data, Field) \
diff --git a/include/asm-arm/global_data.h b/include/asm-arm/global_data.h
index 0410b5ef70..7564ff1469 100644
--- a/include/asm-arm/global_data.h
+++ b/include/asm-arm/global_data.h
@@ -61,6 +61,8 @@ typedef	struct	global_data {
 #define	GD_FLG_DEVINIT	0x00002		/* Devices have been initialized	*/
 #define	GD_FLG_SILENT	0x00004		/* Silent mode				*/
 #define	GD_FLG_POSTFAIL	0x00008		/* Critical POST test failed		*/
+#define	GD_FLG_POSTSTOP	0x00010		/* POST seqeunce aborted		*/
+#define	GD_FLG_LOGINIT	0x00020		/* Log Buffer has been initialized	*/
 
 #define DECLARE_GLOBAL_DATA_PTR     register volatile gd_t *gd asm ("r8")
 
diff --git a/include/asm-arm/u-boot.h b/include/asm-arm/u-boot.h
index c120312e0a..b11d5558f0 100644
--- a/include/asm-arm/u-boot.h
+++ b/include/asm-arm/u-boot.h
@@ -47,7 +47,7 @@ typedef struct bd_info {
     {
 	ulong start;
 	ulong size;
-    } 			bi_dram[CONFIG_NR_DRAM_BANKS];
+    }			bi_dram[CONFIG_NR_DRAM_BANKS];
 #ifdef CONFIG_HAS_ETH1
     /* second onboard ethernet port */
     unsigned char   bi_enet1addr[6];
diff --git a/include/asm-avr32/arch-at32ap700x/mmc.h b/include/asm-avr32/arch-at32ap700x/mmc.h
index fcfbbb3c6c..6a33fef5a8 100644
--- a/include/asm-avr32/arch-at32ap700x/mmc.h
+++ b/include/asm-avr32/arch-at32ap700x/mmc.h
@@ -74,13 +74,13 @@ struct mmc_csd
 /* MMC Command numbers */
 #define MMC_CMD_GO_IDLE_STATE		0
 #define MMC_CMD_SEND_OP_COND		1
-#define MMC_CMD_ALL_SEND_CID 		2
+#define MMC_CMD_ALL_SEND_CID		2
 #define MMC_CMD_SET_RELATIVE_ADDR	3
 #define MMC_CMD_SD_SEND_RELATIVE_ADDR	3
 #define MMC_CMD_SET_DSR			4
 #define MMC_CMD_SELECT_CARD		7
-#define MMC_CMD_SEND_CSD 		9
-#define MMC_CMD_SEND_CID 		10
+#define MMC_CMD_SEND_CSD		9
+#define MMC_CMD_SEND_CID		10
 #define MMC_CMD_SEND_STATUS		13
 #define MMC_CMD_SET_BLOCKLEN		16
 #define MMC_CMD_READ_SINGLE_BLOCK	17
diff --git a/include/asm-avr32/global_data.h b/include/asm-avr32/global_data.h
index daf64bc008..007cfe4e7e 100644
--- a/include/asm-avr32/global_data.h
+++ b/include/asm-avr32/global_data.h
@@ -52,6 +52,8 @@ typedef	struct	global_data {
 #define GD_FLG_DEVINIT	0x00002		/* Devices have been initialized */
 #define GD_FLG_SILENT	0x00004		/* Silent mode			 */
 #define GD_FLG_POSTFAIL	0x00008		/* Critical POST test failed	 */
+#define GD_FLG_POSTSTOP	0x00010		/* POST seqeunce aborted	 */
+#define GD_FLG_LOGINIT	0x00020		/* Log Buf has been initialized	 */
 
 #define DECLARE_GLOBAL_DATA_PTR register gd_t *gd asm("r5")
 
diff --git a/include/asm-blackfin/cplb.h b/include/asm-blackfin/cplb.h
index 7aa712fe0a..e36af2da3d 100644
--- a/include/asm-blackfin/cplb.h
+++ b/include/asm-blackfin/cplb.h
@@ -42,8 +42,8 @@
 #define CPLB_D_PAGE_MGMT	CPLB_LOCK | CPLB_ALL_ACCESS | CPLB_VALID
 #define CPLB_DNOCACHE		CPLB_ALL_ACCESS | CPLB_VALID
 #define CPLB_DDOCACHE		CPLB_DNOCACHE | CPLB_DEF_CACHE
-#define CPLB_INOCACHE   	CPLB_USER_RD | CPLB_VALID
-#define CPLB_IDOCACHE   	CPLB_INOCACHE | CPLB_L1_CHBL
+#define CPLB_INOCACHE		CPLB_USER_RD | CPLB_VALID
+#define CPLB_IDOCACHE		CPLB_INOCACHE | CPLB_L1_CHBL
 
 /* Data Attibutes*/
 
diff --git a/include/asm-blackfin/global_data.h b/include/asm-blackfin/global_data.h
index 6debfc7451..4c88639623 100644
--- a/include/asm-blackfin/global_data.h
+++ b/include/asm-blackfin/global_data.h
@@ -62,6 +62,8 @@ typedef struct global_data {
 #define	GD_FLG_DEVINIT	0x00002	/* Devices have been initialized */
 #define	GD_FLG_SILENT	0x00004	/* Silent mode                   */
 #define	GD_FLG_POSTFAIL	0x00008	/* Critical POST test failed     */
+#define	GD_FLG_POSTSTOP	0x00010	/* POST seqeunce aborted	 */
+#define	GD_FLG_LOGINIT	0x00020	/* Log Buf has been initialized	 */
 
 #define DECLARE_GLOBAL_DATA_PTR     register gd_t * volatile gd asm ("P5")
 
diff --git a/include/asm-blackfin/shared_resources.h b/include/asm-blackfin/shared_resources.h
index d280ffeeaa..2ac8990693 100644
--- a/include/asm-blackfin/shared_resources.h
+++ b/include/asm-blackfin/shared_resources.h
@@ -27,7 +27,7 @@
 
 void swap_to(int device_id);
 
-#define FLASH 	 0
+#define FLASH	 0
 #define ETHERNET 1
 
 #endif /* _SHARED_RESOURCES_H_ */
diff --git a/include/asm-i386/global_data.h b/include/asm-i386/global_data.h
index 68a9ad61ef..3235063995 100644
--- a/include/asm-i386/global_data.h
+++ b/include/asm-i386/global_data.h
@@ -55,6 +55,8 @@ typedef	struct {
 #define	GD_FLG_DEVINIT	0x00002		/* Devices have been initialized	*/
 #define	GD_FLG_SILENT	0x00004		/* Silent mode				*/
 #define	GD_FLG_POSTFAIL	0x00008		/* Critical POST test failed		*/
+#define	GD_FLG_POSTSTOP	0x00010		/* POST seqeunce aborted		*/
+#define	GD_FLG_LOGINIT	0x00020		/* Log Buffer has been initialized	*/
 
 extern gd_t *global_data;
 
diff --git a/include/asm-i386/ic/sc520.h b/include/asm-i386/ic/sc520.h
index d5abbbe52a..0f7e7a551e 100644
--- a/include/asm-i386/ic/sc520.h
+++ b/include/asm-i386/ic/sc520.h
@@ -25,209 +25,209 @@
 #define _ASM_IC_SC520_H_ 1
 
 /* Memory mapped configuration registers, MMCR */
-#define SC520_REVID		0x0000		/* ElanSC520 Microcontroller Revision ID Register */
-#define SC520_CPUCTL		0x0002		/* Am5x86 CPU Control Register */
-#define SC520_DRCCTL            0x0010          /* SDRAM Control Register */
-#define SC520_DRCTMCTL		0x0012		/* SDRAM Timing Control Register */
-#define SC520_DRCCFG		0x0014		/* SDRAM Bank Configuration Register*/
-#define SC520_DRCBENDADR	0x0018		/* SDRAM Bank 0-3 Ending Address Register*/
-#define SC520_ECCCTL		0x0020		/* ECC Control Register */
-#define SC520_ECCSTA		0x0021		/* ECC Status Register */
-#define SC520_ECCCKBPOS		0x0022		/* ECC Check Bit Position Register */
-#define SC520_ECCSBADD		0x0024		/* ECC Single-Bit Error Address Register */
-#define SC520_DBCTL		0x0040		/* SDRAM Buffer Control Register */
-#define SC520_BOOTCSCTL		0x0050		/* /BOOTCS Control Register */
-#define SC520_ROMCS1CTL		0x0054		/* /ROMCS1 Control Register */
-#define SC520_ROMCS2CTL		0x0056		/* /ROMCS2 Control Register */
-#define SC520_HBCTL		0x0060 		/* Host Bridge Control Register */
-#define SC520_HBTGTIRQCTL	0x0062		/* Host Bridge Target Interrupt Control Register */
-#define SC520_HBTGTIRQSTA	0x0064		/* Host Bridge Target Interrupt Status Register */
-#define SC520_HBMSTIRQCTL	0x0066		/* Host Bridge Target Interrupt Control Register */
-#define SC520_HBMSTIRQSTA	0x0068		/* Host Bridge Master Interrupt Status Register */
-#define SC520_MSTINTADD		0x006c		/* Host Bridge Master Interrupt Address Register */
-#define SC520_SYSARBCTL		0x0070		/* System Arbiter Control Register */
-#define SC520_PCIARBSTA		0x0071		/* PCI Bus Arbiter Status Register */
-#define SC520_SYSARBMENB	0x0072		/* System Arbiter Master Enable Register */
-#define SC520_ARBPRICTL		0x0074		/* Arbiter Priority Control Register */
-#define SC520_ADDDECCTL     	0x0080 		/* Address Decode Control Register */
-#define SC520_WPVSTA        	0x0082		/* Write-Protect Violation Status Register */
-#define SC520_PAR0          	0x0088		/* Programmable Address Region 0 Register */
-#define SC520_PAR1          	0x008c       	/* Programmable Address Region 1 Register */
-#define SC520_PAR2          	0x0090       	/* Programmable Address Region 2 Register */
-#define SC520_PAR3          	0x0094      	/* Programmable Address Region 3 Register */
-#define SC520_PAR4          	0x0098       	/* Programmable Address Region 4 Register */
-#define SC520_PAR5          	0x009c       	/* Programmable Address Region 5 Register */
-#define SC520_PAR6         	0x00a0      	/* Programmable Address Region 6 Register */
-#define SC520_PAR7          	0x00a4       	/* Programmable Address Region 7 Register */
-#define SC520_PAR8          	0x00a8       	/* Programmable Address Region 8 Register */
-#define SC520_PAR9          	0x00ac       	/* Programmable Address Region 9 Register */
-#define SC520_PAR10         	0x00b0       	/* Programmable Address Region 10 Register */
-#define SC520_PAR11         	0x00b4       	/* Programmable Address Region 11 Register */
-#define SC520_PAR12         	0x00b8       	/* Programmable Address Region 12 Register */
-#define SC520_PAR13         	0x00bc       	/* Programmable Address Region 13 Register */
-#define SC520_PAR14         	0x00c0       	/* Programmable Address Region 14 Register */
-#define SC520_PAR15		0x00c4		/* Programmable Address Region 15 Register */
-#define SC520_GPECHO		0x0c00		/* GP Echo Mode Register */
-#define SC520_GPCSDW		0x0c01		/* GP Chip Select Data Width Register */
-#define SC520_GPCSQUAL		0x0c02		/* GP Chip Select Qualification Register */
-#define SC520_GPCSRT		0x0c08		/* GP Chip Select Recovery Time Register */
-#define SC520_GPCSPW		0x0c09		/* GP Chip Select Pulse Width Register */
-#define SC520_GPCSOFF		0x0c0a		/* GP Chip Select Offset Register */
-#define SC520_GPRDW		0x0c0b		/* GP Read Pulse Width Register */
-#define SC520_GPRDOFF		0x0c0c		/* GP Read Offset Register */
-#define SC520_GPWRW		0x0c0d		/* GP Write Pulse Width Register */
-#define SC520_GPWROFF		0x0c0e		/* GP Write Offset Register */
-#define SC520_GPALEW		0x0c0f		/* GP ALE Pulse Width Register */
-#define SC520_GPALEOFF		0x0c10		/* GP ALE Offset Register */
-#define SC520_PIOPFS15_0	0x0c20		/* PIO15-PIO0 Pin Function Select */
-#define SC520_PIOPFS31_16	0x0c22		/* PIO31-PIO16 Pin Function Select */
-#define SC520_CSPFS		0x0c24		/* Chip Select Pin Function Select */
-#define SC520_CLKSEL		0x0c26		/* Clock Select */
-#define SC520_DSCTL		0x0c28		/* Drive Strength Control */
-#define SC520_PIODIR15_0	0x0c2a		/* PIO15-PIO0 Direction */
-#define SC520_PIODIR31_16	0x0c2c		/* PIO31-PIO16 Direction */
-#define SC520_PIODATA15_0	0x0c30		/* PIO15-PIO0 Data */
-#define SC520_PIODATA31_16	0x0c32		/* PIO31-PIO16 Data */
-#define SC520_PIOSET15_0	0x0c34		/* PIO15-PIO0 Set */
-#define SC520_PIOSET31_16	0x0c36		/* PIO31-PIO16 Set */
-#define SC520_PIOCLR15_0	0x0c38		/* PIO15-PIO0 Clear */
-#define SC520_PIOCLR31_16	0x0c3a		/* PIO31-PIO16 Clear */
-#define SC520_SWTMRMILLI 	0x0c60		/* Software Timer Millisecond Count */
-#define SC520_SWTMRMICRO 	0x0c62		/* Software Timer Microsecond Count */
-#define SC520_SWTMRCFG   	0x0c64		/* Software Timer Configuration */
-#define SC520_GPTMRSTA		0x0c70		/* GP Timers Status Register */
-#define SC520_GPTMR0CTL		0x0c72		/* GP Timer 0 Mode/Control Register */
-#define SC520_GPTMR0CNT		0x0c74		/* GP Timer 0 Count Register */
-#define SC520_GPTMR0MAXCMPA	0x0c76		/* GP Timer 0 Maxcount Compare A Register */
-#define SC520_GPTMR0MAXCMPB	0x0c78		/* GP Timer 0 Maxcount Compare B Register */
-#define SC520_GPTMR1CTL		0x0c7a		/* GP Timer 1 Mode/Control Register */
-#define SC520_GPTMR1CNT		0x0c7c		/* GP Timer 1 Count Register */
-#define SC520_GPTMR1MAXCMPA	0x0c7e		/* GP Timer 1 Maxcount Compare Register A */
-#define SC520_GPTMR1MAXCMPB	0x0c80		/* GP Timer 1 Maxcount Compare B Register */
-#define SC520_GPTMR2CTL		0x0c82		/* GP Timer 2 Mode/Control Register */
-#define SC520_GPTMR2CNT		0x0c84		/* GP Timer 2 Count Register */
-#define SC520_GPTMR2MAXCMPA	0x0c8e		/* GP Timer 2 Maxcount Compare A Register */
-#define SC520_WDTMRCTL		0x0cb0		/* Watchdog Timer Control Register */
-#define SC520_WDTMRCNTL		0x0cb2		/* Watchdog Timer Count Low Register */
-#define SC520_WDTMRCNTH		0x0cb4		/* Watchdog Timer Count High Register */
-#define SC520_UART1CTL		0x0cc0	        /* UART 1 General Control Register */
-#define SC520_UART1STA		0x0cc1	        /* UART 1 General Status Register */
-#define SC520_UART1FCRSHAD	0x0cc2	        /* UART 1 FIFO Control Shadow Register */
-#define SC520_UART2CTL		0x0cc4	        /* UART 2 General Control Register */
-#define SC520_UART2STA		0x0cc5	        /* UART 2 General Status Register */
-#define SC520_UART2FCRSHAD	0x0cc6	        /* UART 2 FIFO Control Shadow Register */
-#define SC520_SSICTL            0x0cd0          /* SSI Control */
-#define SC520_SSIXMIT           0x0cd1          /* SSI Transmit */
-#define SC520_SSICMD            0x0cd2          /* SSI Command */
-#define SC520_SSISTA            0x0cd3          /* SSI Status */
-#define SC520_SSIRCV            0x0cd4          /* SSI Receive */
-#define SC520_PICICR		0x0d00		/* Interrupt Control Register */
-#define SC520_MPICMODE		0x0d02		/* Master PIC Interrupt Mode Register */
-#define SC520_SL1PICMODE	0x0d03		/* Slave 1 PIC Interrupt Mode Register */
-#define SC520_SL2PICMODE	0x0d04		/* Slave 2 PIC Interrupt Mode Register */
-#define SC520_SWINT16_1		0x0d08		/* Software Interrupt 16-1 Control Register */
-#define SC520_SWINT22_17	0x0d0a		/* Software Interrupt 22-17/NMI Control Register */
-#define SC520_INTPINPOL		0x0d10		/* Interrupt Pin Polarity Register */
-#define SC520_PCIHOSTMAP	0x0d14		/* PCI Host Bridge Interrupt Mappin Register */
-#define SC520_ECCMAP		0x0d18		/* ECC Interrupt Mapping Register */
-#define SC520_GPTMR0MAP		0x0d1a		/* GP Timer 0 Interrupt Mapping Register */
-#define SC520_GPTMR1MAP		0x0d1b		/* GP Timer 1 Interrupt Mapping Register */
-#define SC520_GPTMR2MAP		0x0d1c		/* GP Timer 2 Interrupt Mapping Register */
-#define SC520_PIT0MAP		0x0d20		/* PIT0 Interrupt Mapping Register */
-#define SC520_PIT1MAP		0x0d21		/* PIT1 Interrupt Mapping Register */
-#define SC520_PIT2MAP		0x0d22		/* PIT2 Interrupt Mapping Register */
-#define SC520_UART1MAP		0x0d28		/* UART 1 Interrupt Mapping Register */
-#define SC520_UART2MAP		0x0d29		/* UART 2 Interrupt Mapping Register */
-#define SC520_PCIINTAMAP	0x0d30		/* PCI Interrupt A Mapping Register */
-#define SC520_PCIINTBMAP	0x0d31		/* PCI Interrupt B Mapping Register */
-#define SC520_PCIINTCMAP	0x0d32		/* PCI Interrupt C Mapping Register */
-#define SC520_PCIINTDMAP	0x0d33		/* PCI Interrupt D Mapping Register */
-#define SC520_DMABCINTMAP	0x0d40		/* DMA Buffer Chaining Interrupt Mapping Register */
-#define SC520_SSIMAP		0x0d41		/* SSI Interrupt Mapping Register */
-#define SC520_WDTMAP		0x0d42		/* Watchdog Timer Interrupt Mapping Register */
-#define SC520_RTCMAP		0x0d43		/* RTC Interrupt Mapping Register */
-#define SC520_WPVMAP		0x0d44		/* Write-Protect Interrupt Mapping Register */
-#define SC520_ICEMAP		0x0d45		/* AMDebug JTAG RX/TX Interrupt Mapping Register */
-#define SC520_FERRMAP		0x0d46		/* Floating Point Error Interrupt Mapping Register */
-#define SC520_GP0IMAP		0x0d50		/* GPIRQ0 Interrupt Mapping Register */
-#define SC520_GP1IMAP		0x0d51		/* GPIRQ1 Interrupt Mapping Register */
-#define SC520_GP2IMAP		0x0d52		/* GPIRQ2 Interrupt Mapping Register */
-#define SC520_GP3IMAP		0x0d53		/* GPIRQ3 Interrupt Mapping Register */
-#define SC520_GP4IMAP		0x0d54		/* GPIRQ4 Interrupt Mapping Register */
-#define SC520_GP5IMAP		0x0d55		/* GPIRQ5 Interrupt Mapping Register */
-#define SC520_GP6IMAP		0x0d56		/* GPIRQ6 Interrupt Mapping Register */
-#define SC520_GP7IMAP		0x0d57		/* GPIRQ7 Interrupt Mapping Register */
-#define SC520_GP8IMAP		0x0d58		/* GPIRQ8 Interrupt Mapping Register */
-#define SC520_GP9IMAP		0x0d59		/* GPIRQ9 Interrupt Mapping Register */
-#define SC520_GP10IMAP		0x0d5a		/* GPIRQ10 Interrupt Mapping Register */
-#define SC520_SYSINFO		0x0d70		/* System Board Information Register */
-#define SC520_RESCFG		0x0d72		/* Reset Configuration Register */
-#define SC520_RESSTA		0x0d74		/* Reset Status Register */
-#define SC520_GPDMAMMIO		0x0d81		/* GP-DMA Memory-Mapped I/O Register */
-#define SC520_GPDMAEXTCHMAPA	0x0d82		/* GP-DMA Resource Channel Map A */
-#define SC520_GPDMAEXTCHMAPB	0x0d84		/* GP-DMA Resource Channel Map B */
-#define SC520_GPDMAEXTPG0	0x0d86		/* GP-DMA Channel 0 Extended Page */
-#define SC520_GPDMAEXTPG1	0x0d87		/* GP-DMA Channel 1 Extended Page */
-#define SC520_GPDMAEXTPG2	0x0d88		/* GP-DMA Channel 2 Extended Page */
-#define SC520_GPDMAEXTPG3	0x0d89		/* GP-DMA Channel 3 Extended Page */
-#define SC520_GPDMAEXTPG5	0x0d8a		/* GP-DMA Channel 5 Extended Page */
-#define SC520_GPDMAEXTPG6	0x0d8b		/* GP-DMA Channel 6 Extended Page */
-#define SC520_GPDMAEXTPG7	0x0d8c		/* GP-DMA Channel 7 Extended Page */
-#define SC520_GPDMAEXTTC3	0x0d90		/* GP-DMA Channel 3 Extender Transfer count */
-#define SC520_GPDMAEXTTC5	0x0d91		/* GP-DMA Channel 5 Extender Transfer count */
-#define SC520_GPDMAEXTTC6	0x0d92		/* GP-DMA Channel 6 Extender Transfer count */
-#define SC520_GPDMAEXTTC7	0x0d93		/* GP-DMA Channel 7 Extender Transfer count */
-#define SC520_GPDMABCCTL	0x0d98		/* Buffer Chaining Control */
-#define SC520_GPDMABCSTA	0x0d99		/* Buffer Chaining Status */
-#define SC520_GPDMABSINTENB	0x0d9a		/* Buffer Chaining Interrupt Enable */
-#define SC520_GPDMABCVAL	0x0d9b		/* Buffer Chaining Valid */
-#define SC520_GPDMANXTADDL3	0x0da0		/* GP-DMA Channel 3 Next Address Low */
-#define SC520_GPDMANXTADDH3	0x0da2		/* GP-DMA Channel 3 Next Address High */
-#define SC520_GPDMANXTADDL5	0x0da4		/* GP-DMA Channel 5 Next Address Low */
-#define SC520_GPDMANXTADDH5	0x0da6		/* GP-DMA Channel 5 Next Address High */
-#define SC520_GPDMANXTADDL6	0x0da8		/* GP-DMA Channel 6 Next Address Low */
-#define SC520_GPDMANXTADDH6	0x0daa		/* GP-DMA Channel 6 Next Address High */
-#define SC520_GPDMANXTADDL7	0x0dac		/* GP-DMA Channel 7 Next Address Low */
-#define SC520_GPDMANXTADDH7	0x0dae		/* GP-DMA Channel 7 Next Address High */
-#define SC520_GPDMANXTTCL3	0x0db0		/* GP-DMA Channel 3 Next Transfer Count Low */
-#define SC520_GPDMANXTTCH3	0x0db2		/* GP-DMA Channel 3 Next Transfer Count High */
-#define SC520_GPDMANXTTCL5	0x0db4		/* GP-DMA Channel 5 Next Transfer Count Low */
-#define SC520_GPDMANXTTCH5	0x0db6		/* GP-DMA Channel 5 Next Transfer Count High */
-#define SC520_GPDMANXTTCL6	0x0db8		/* GP-DMA Channel 6 Next Transfer Count Low */
-#define SC520_GPDMANXTTCH6	0x0dba		/* GP-DMA Channel 6 Next Transfer Count High */
-#define SC520_GPDMANXTTCL7	0x0dbc		/* GP-DMA Channel 7 Next Transfer Count Low */
-#define SC520_GPDMANXTTCH7	0x0dbe		/* GP-DMA Channel 7 Next Transfer Count High */
+#define SC520_REVID		0x0000	/* ElanSC520 Microcontroller Revision ID Register */
+#define SC520_CPUCTL		0x0002	/* Am5x86 CPU Control Register */
+#define SC520_DRCCTL		0x0010	/* SDRAM Control Register */
+#define SC520_DRCTMCTL		0x0012	/* SDRAM Timing Control Register */
+#define SC520_DRCCFG		0x0014	/* SDRAM Bank Configuration Register*/
+#define SC520_DRCBENDADR	0x0018	/* SDRAM Bank 0-3 Ending Address Register*/
+#define SC520_ECCCTL		0x0020	/* ECC Control Register */
+#define SC520_ECCSTA		0x0021	/* ECC Status Register */
+#define SC520_ECCCKBPOS		0x0022	/* ECC Check Bit Position Register */
+#define SC520_ECCSBADD		0x0024	/* ECC Single-Bit Error Address Register */
+#define SC520_DBCTL		0x0040	/* SDRAM Buffer Control Register */
+#define SC520_BOOTCSCTL		0x0050	/* /BOOTCS Control Register */
+#define SC520_ROMCS1CTL		0x0054	/* /ROMCS1 Control Register */
+#define SC520_ROMCS2CTL		0x0056	/* /ROMCS2 Control Register */
+#define SC520_HBCTL		0x0060	/* Host Bridge Control Register */
+#define SC520_HBTGTIRQCTL	0x0062	/* Host Bridge Target Interrupt Control Register */
+#define SC520_HBTGTIRQSTA	0x0064	/* Host Bridge Target Interrupt Status Register */
+#define SC520_HBMSTIRQCTL	0x0066	/* Host Bridge Target Interrupt Control Register */
+#define SC520_HBMSTIRQSTA	0x0068	/* Host Bridge Master Interrupt Status Register */
+#define SC520_MSTINTADD		0x006c	/* Host Bridge Master Interrupt Address Register */
+#define SC520_SYSARBCTL		0x0070	/* System Arbiter Control Register */
+#define SC520_PCIARBSTA		0x0071	/* PCI Bus Arbiter Status Register */
+#define SC520_SYSARBMENB	0x0072	/* System Arbiter Master Enable Register */
+#define SC520_ARBPRICTL		0x0074	/* Arbiter Priority Control Register */
+#define SC520_ADDDECCTL		0x0080	/* Address Decode Control Register */
+#define SC520_WPVSTA		0x0082	/* Write-Protect Violation Status Register */
+#define SC520_PAR0		0x0088	/* Programmable Address Region 0 Register */
+#define SC520_PAR1		0x008c	/* Programmable Address Region 1 Register */
+#define SC520_PAR2		0x0090	/* Programmable Address Region 2 Register */
+#define SC520_PAR3		0x0094	/* Programmable Address Region 3 Register */
+#define SC520_PAR4		0x0098	/* Programmable Address Region 4 Register */
+#define SC520_PAR5		0x009c	/* Programmable Address Region 5 Register */
+#define SC520_PAR6		0x00a0	/* Programmable Address Region 6 Register */
+#define SC520_PAR7		0x00a4	/* Programmable Address Region 7 Register */
+#define SC520_PAR8		0x00a8	/* Programmable Address Region 8 Register */
+#define SC520_PAR9		0x00ac	/* Programmable Address Region 9 Register */
+#define SC520_PAR10		0x00b0	/* Programmable Address Region 10 Register */
+#define SC520_PAR11		0x00b4	/* Programmable Address Region 11 Register */
+#define SC520_PAR12		0x00b8	/* Programmable Address Region 12 Register */
+#define SC520_PAR13		0x00bc	/* Programmable Address Region 13 Register */
+#define SC520_PAR14		0x00c0	/* Programmable Address Region 14 Register */
+#define SC520_PAR15		0x00c4	/* Programmable Address Region 15 Register */
+#define SC520_GPECHO		0x0c00	/* GP Echo Mode Register */
+#define SC520_GPCSDW		0x0c01	/* GP Chip Select Data Width Register */
+#define SC520_GPCSQUAL		0x0c02	/* GP Chip Select Qualification Register */
+#define SC520_GPCSRT		0x0c08	/* GP Chip Select Recovery Time Register */
+#define SC520_GPCSPW		0x0c09	/* GP Chip Select Pulse Width Register */
+#define SC520_GPCSOFF		0x0c0a	/* GP Chip Select Offset Register */
+#define SC520_GPRDW		0x0c0b	/* GP Read Pulse Width Register */
+#define SC520_GPRDOFF		0x0c0c	/* GP Read Offset Register */
+#define SC520_GPWRW		0x0c0d	/* GP Write Pulse Width Register */
+#define SC520_GPWROFF		0x0c0e	/* GP Write Offset Register */
+#define SC520_GPALEW		0x0c0f	/* GP ALE Pulse Width Register */
+#define SC520_GPALEOFF		0x0c10	/* GP ALE Offset Register */
+#define SC520_PIOPFS15_0	0x0c20	/* PIO15-PIO0 Pin Function Select */
+#define SC520_PIOPFS31_16	0x0c22	/* PIO31-PIO16 Pin Function Select */
+#define SC520_CSPFS		0x0c24	/* Chip Select Pin Function Select */
+#define SC520_CLKSEL		0x0c26	/* Clock Select */
+#define SC520_DSCTL		0x0c28	/* Drive Strength Control */
+#define SC520_PIODIR15_0	0x0c2a	/* PIO15-PIO0 Direction */
+#define SC520_PIODIR31_16	0x0c2c	/* PIO31-PIO16 Direction */
+#define SC520_PIODATA15_0	0x0c30	/* PIO15-PIO0 Data */
+#define SC520_PIODATA31_16	0x0c32	/* PIO31-PIO16 Data */
+#define SC520_PIOSET15_0	0x0c34	/* PIO15-PIO0 Set */
+#define SC520_PIOSET31_16	0x0c36	/* PIO31-PIO16 Set */
+#define SC520_PIOCLR15_0	0x0c38	/* PIO15-PIO0 Clear */
+#define SC520_PIOCLR31_16	0x0c3a	/* PIO31-PIO16 Clear */
+#define SC520_SWTMRMILLI	0x0c60	/* Software Timer Millisecond Count */
+#define SC520_SWTMRMICRO	0x0c62	/* Software Timer Microsecond Count */
+#define SC520_SWTMRCFG		0x0c64	/* Software Timer Configuration */
+#define SC520_GPTMRSTA		0x0c70	/* GP Timers Status Register */
+#define SC520_GPTMR0CTL		0x0c72	/* GP Timer 0 Mode/Control Register */
+#define SC520_GPTMR0CNT		0x0c74	/* GP Timer 0 Count Register */
+#define SC520_GPTMR0MAXCMPA	0x0c76	/* GP Timer 0 Maxcount Compare A Register */
+#define SC520_GPTMR0MAXCMPB	0x0c78	/* GP Timer 0 Maxcount Compare B Register */
+#define SC520_GPTMR1CTL		0x0c7a	/* GP Timer 1 Mode/Control Register */
+#define SC520_GPTMR1CNT		0x0c7c	/* GP Timer 1 Count Register */
+#define SC520_GPTMR1MAXCMPA	0x0c7e	/* GP Timer 1 Maxcount Compare Register A */
+#define SC520_GPTMR1MAXCMPB	0x0c80	/* GP Timer 1 Maxcount Compare B Register */
+#define SC520_GPTMR2CTL		0x0c82	/* GP Timer 2 Mode/Control Register */
+#define SC520_GPTMR2CNT		0x0c84	/* GP Timer 2 Count Register */
+#define SC520_GPTMR2MAXCMPA	0x0c8e	/* GP Timer 2 Maxcount Compare A Register */
+#define SC520_WDTMRCTL		0x0cb0	/* Watchdog Timer Control Register */
+#define SC520_WDTMRCNTL		0x0cb2	/* Watchdog Timer Count Low Register */
+#define SC520_WDTMRCNTH		0x0cb4	/* Watchdog Timer Count High Register */
+#define SC520_UART1CTL		0x0cc0	/* UART 1 General Control Register */
+#define SC520_UART1STA		0x0cc1	/* UART 1 General Status Register */
+#define SC520_UART1FCRSHAD	0x0cc2	/* UART 1 FIFO Control Shadow Register */
+#define SC520_UART2CTL		0x0cc4	/* UART 2 General Control Register */
+#define SC520_UART2STA		0x0cc5	/* UART 2 General Status Register */
+#define SC520_UART2FCRSHAD	0x0cc6	/* UART 2 FIFO Control Shadow Register */
+#define SC520_SSICTL		0x0cd0	/* SSI Control */
+#define SC520_SSIXMIT		0x0cd1	/* SSI Transmit */
+#define SC520_SSICMD		0x0cd2	/* SSI Command */
+#define SC520_SSISTA		0x0cd3	/* SSI Status */
+#define SC520_SSIRCV		0x0cd4	/* SSI Receive */
+#define SC520_PICICR		0x0d00	/* Interrupt Control Register */
+#define SC520_MPICMODE		0x0d02	/* Master PIC Interrupt Mode Register */
+#define SC520_SL1PICMODE	0x0d03	/* Slave 1 PIC Interrupt Mode Register */
+#define SC520_SL2PICMODE	0x0d04	/* Slave 2 PIC Interrupt Mode Register */
+#define SC520_SWINT16_1		0x0d08	/* Software Interrupt 16-1 Control Register */
+#define SC520_SWINT22_17	0x0d0a	/* Software Interrupt 22-17/NMI Control Register */
+#define SC520_INTPINPOL		0x0d10	/* Interrupt Pin Polarity Register */
+#define SC520_PCIHOSTMAP	0x0d14	/* PCI Host Bridge Interrupt Mappin Register */
+#define SC520_ECCMAP		0x0d18	/* ECC Interrupt Mapping Register */
+#define SC520_GPTMR0MAP		0x0d1a	/* GP Timer 0 Interrupt Mapping Register */
+#define SC520_GPTMR1MAP		0x0d1b	/* GP Timer 1 Interrupt Mapping Register */
+#define SC520_GPTMR2MAP		0x0d1c	/* GP Timer 2 Interrupt Mapping Register */
+#define SC520_PIT0MAP		0x0d20	/* PIT0 Interrupt Mapping Register */
+#define SC520_PIT1MAP		0x0d21	/* PIT1 Interrupt Mapping Register */
+#define SC520_PIT2MAP		0x0d22	/* PIT2 Interrupt Mapping Register */
+#define SC520_UART1MAP		0x0d28	/* UART 1 Interrupt Mapping Register */
+#define SC520_UART2MAP		0x0d29	/* UART 2 Interrupt Mapping Register */
+#define SC520_PCIINTAMAP	0x0d30	/* PCI Interrupt A Mapping Register */
+#define SC520_PCIINTBMAP	0x0d31	/* PCI Interrupt B Mapping Register */
+#define SC520_PCIINTCMAP	0x0d32	/* PCI Interrupt C Mapping Register */
+#define SC520_PCIINTDMAP	0x0d33	/* PCI Interrupt D Mapping Register */
+#define SC520_DMABCINTMAP	0x0d40	/* DMA Buffer Chaining Interrupt Mapping Register */
+#define SC520_SSIMAP		0x0d41	/* SSI Interrupt Mapping Register */
+#define SC520_WDTMAP		0x0d42	/* Watchdog Timer Interrupt Mapping Register */
+#define SC520_RTCMAP		0x0d43	/* RTC Interrupt Mapping Register */
+#define SC520_WPVMAP		0x0d44	/* Write-Protect Interrupt Mapping Register */
+#define SC520_ICEMAP		0x0d45	/* AMDebug JTAG RX/TX Interrupt Mapping Register */
+#define SC520_FERRMAP		0x0d46	/* Floating Point Error Interrupt Mapping Register */
+#define SC520_GP0IMAP		0x0d50	/* GPIRQ0 Interrupt Mapping Register */
+#define SC520_GP1IMAP		0x0d51	/* GPIRQ1 Interrupt Mapping Register */
+#define SC520_GP2IMAP		0x0d52	/* GPIRQ2 Interrupt Mapping Register */
+#define SC520_GP3IMAP		0x0d53	/* GPIRQ3 Interrupt Mapping Register */
+#define SC520_GP4IMAP		0x0d54	/* GPIRQ4 Interrupt Mapping Register */
+#define SC520_GP5IMAP		0x0d55	/* GPIRQ5 Interrupt Mapping Register */
+#define SC520_GP6IMAP		0x0d56	/* GPIRQ6 Interrupt Mapping Register */
+#define SC520_GP7IMAP		0x0d57	/* GPIRQ7 Interrupt Mapping Register */
+#define SC520_GP8IMAP		0x0d58	/* GPIRQ8 Interrupt Mapping Register */
+#define SC520_GP9IMAP		0x0d59	/* GPIRQ9 Interrupt Mapping Register */
+#define SC520_GP10IMAP		0x0d5a	/* GPIRQ10 Interrupt Mapping Register */
+#define SC520_SYSINFO		0x0d70	/* System Board Information Register */
+#define SC520_RESCFG		0x0d72	/* Reset Configuration Register */
+#define SC520_RESSTA		0x0d74	/* Reset Status Register */
+#define SC520_GPDMAMMIO		0x0d81	/* GP-DMA Memory-Mapped I/O Register */
+#define SC520_GPDMAEXTCHMAPA	0x0d82	/* GP-DMA Resource Channel Map A */
+#define SC520_GPDMAEXTCHMAPB	0x0d84	/* GP-DMA Resource Channel Map B */
+#define SC520_GPDMAEXTPG0	0x0d86	/* GP-DMA Channel 0 Extended Page */
+#define SC520_GPDMAEXTPG1	0x0d87	/* GP-DMA Channel 1 Extended Page */
+#define SC520_GPDMAEXTPG2	0x0d88	/* GP-DMA Channel 2 Extended Page */
+#define SC520_GPDMAEXTPG3	0x0d89	/* GP-DMA Channel 3 Extended Page */
+#define SC520_GPDMAEXTPG5	0x0d8a	/* GP-DMA Channel 5 Extended Page */
+#define SC520_GPDMAEXTPG6	0x0d8b	/* GP-DMA Channel 6 Extended Page */
+#define SC520_GPDMAEXTPG7	0x0d8c	/* GP-DMA Channel 7 Extended Page */
+#define SC520_GPDMAEXTTC3	0x0d90	/* GP-DMA Channel 3 Extender Transfer count */
+#define SC520_GPDMAEXTTC5	0x0d91	/* GP-DMA Channel 5 Extender Transfer count */
+#define SC520_GPDMAEXTTC6	0x0d92	/* GP-DMA Channel 6 Extender Transfer count */
+#define SC520_GPDMAEXTTC7	0x0d93	/* GP-DMA Channel 7 Extender Transfer count */
+#define SC520_GPDMABCCTL	0x0d98	/* Buffer Chaining Control */
+#define SC520_GPDMABCSTA	0x0d99	/* Buffer Chaining Status */
+#define SC520_GPDMABSINTENB	0x0d9a	/* Buffer Chaining Interrupt Enable */
+#define SC520_GPDMABCVAL	0x0d9b	/* Buffer Chaining Valid */
+#define SC520_GPDMANXTADDL3	0x0da0	/* GP-DMA Channel 3 Next Address Low */
+#define SC520_GPDMANXTADDH3	0x0da2	/* GP-DMA Channel 3 Next Address High */
+#define SC520_GPDMANXTADDL5	0x0da4	/* GP-DMA Channel 5 Next Address Low */
+#define SC520_GPDMANXTADDH5	0x0da6	/* GP-DMA Channel 5 Next Address High */
+#define SC520_GPDMANXTADDL6	0x0da8	/* GP-DMA Channel 6 Next Address Low */
+#define SC520_GPDMANXTADDH6	0x0daa	/* GP-DMA Channel 6 Next Address High */
+#define SC520_GPDMANXTADDL7	0x0dac	/* GP-DMA Channel 7 Next Address Low */
+#define SC520_GPDMANXTADDH7	0x0dae	/* GP-DMA Channel 7 Next Address High */
+#define SC520_GPDMANXTTCL3	0x0db0	/* GP-DMA Channel 3 Next Transfer Count Low */
+#define SC520_GPDMANXTTCH3	0x0db2	/* GP-DMA Channel 3 Next Transfer Count High */
+#define SC520_GPDMANXTTCL5	0x0db4	/* GP-DMA Channel 5 Next Transfer Count Low */
+#define SC520_GPDMANXTTCH5	0x0db6	/* GP-DMA Channel 5 Next Transfer Count High */
+#define SC520_GPDMANXTTCL6	0x0db8	/* GP-DMA Channel 6 Next Transfer Count Low */
+#define SC520_GPDMANXTTCH6	0x0dba	/* GP-DMA Channel 6 Next Transfer Count High */
+#define SC520_GPDMANXTTCL7	0x0dbc	/* GP-DMA Channel 7 Next Transfer Count Low */
+#define SC520_GPDMANXTTCH7	0x0dbe	/* GP-DMA Channel 7 Next Transfer Count High */
 
 /* MMCR Register bits (not all of them :) ) */
 
 /* SSI Stuff */
-#define CTL_CLK_SEL_4           0x00           /* Nominal Bit Rate = 8 MHz    */
-#define CTL_CLK_SEL_8           0x10           /* Nominal Bit Rate = 4 MHz    */
-#define CTL_CLK_SEL_16          0x20           /* Nominal Bit Rate = 2 MHz    */
-#define CTL_CLK_SEL_32          0x30           /* Nominal Bit Rate = 1 MHz    */
-#define CTL_CLK_SEL_64          0x40           /* Nominal Bit Rate = 512 KHz  */
-#define CTL_CLK_SEL_128         0x50           /* Nominal Bit Rate = 256 KHz  */
-#define CTL_CLK_SEL_256         0x60           /* Nominal Bit Rate = 128 KHz  */
-#define CTL_CLK_SEL_512         0x70           /* Nominal Bit Rate = 64 KHz   */
+#define CTL_CLK_SEL_4		0x00	/* Nominal Bit Rate = 8 MHz    */
+#define CTL_CLK_SEL_8		0x10	/* Nominal Bit Rate = 4 MHz    */
+#define CTL_CLK_SEL_16		0x20	/* Nominal Bit Rate = 2 MHz    */
+#define CTL_CLK_SEL_32		0x30	/* Nominal Bit Rate = 1 MHz    */
+#define CTL_CLK_SEL_64		0x40	/* Nominal Bit Rate = 512 KHz  */
+#define CTL_CLK_SEL_128		0x50	/* Nominal Bit Rate = 256 KHz  */
+#define CTL_CLK_SEL_256		0x60	/* Nominal Bit Rate = 128 KHz  */
+#define CTL_CLK_SEL_512		0x70	/* Nominal Bit Rate = 64 KHz   */
 
-#define TC_INT_ENB              0x08           /* Transaction Complete Interrupt Enable */
-#define PHS_INV_ENB             0x04           /* SSI Inverted Phase Mode Enable */
-#define CLK_INV_ENB    	        0x02           /* SSI Inverted Clock Mode Enable */
-#define MSBF_ENB      	        0x01           /* SSI Most Significant Bit First Mode Enable */
+#define TC_INT_ENB		0x08	/* Transaction Complete Interrupt Enable */
+#define PHS_INV_ENB		0x04	/* SSI Inverted Phase Mode Enable */
+#define CLK_INV_ENB		0x02	/* SSI Inverted Clock Mode Enable */
+#define MSBF_ENB		0x01	/* SSI Most Significant Bit First Mode Enable */
 
-#define SSICMD_CMD_SEL_XMITRCV  0x03           /* Simultaneous Transmit / Receive Transaction */
-#define SSICMD_CMD_SEL_RCV      0x02           /* Receive Transaction */
-#define SSICMD_CMD_SEL_XMIT     0x01           /* Transmit Transaction */
-#define SSISTA_BSY              0x02           /* SSI Busy */
-#define SSISTA_TC_INT           0x01           /* SSI Transaction Complete Interrupt */
+#define SSICMD_CMD_SEL_XMITRCV	0x03	/* Simultaneous Transmit / Receive Transaction */
+#define SSICMD_CMD_SEL_RCV	0x02	/* Receive Transaction */
+#define SSICMD_CMD_SEL_XMIT	0x01	/* Transmit Transaction */
+#define SSISTA_BSY		0x02	/* SSI Busy */
+#define SSISTA_TC_INT		0x01	/* SSI Transaction Complete Interrupt */
 
 
 /* BITS for SC520_ADDDECCTL: */
-#define WPV_INT_ENB		0x80		/* Write-Protect Violation Interrupt Enable */
-#define IO_HOLE_DEST_PCI	0x10		/* I/O Hole Access Destination */
-#define RTC_DIS			0x04		/* RTC Disable */
-#define UART2_DIS		0x02		/* UART2 Disable */
-#define UART1_DIS		0x01		/* UART1 Disable */
+#define WPV_INT_ENB		0x80	/* Write-Protect Violation Interrupt Enable */
+#define IO_HOLE_DEST_PCI	0x10	/* I/O Hole Access Destination */
+#define RTC_DIS			0x04	/* RTC Disable */
+#define UART2_DIS		0x02	/* UART2 Disable */
+#define UART1_DIS		0x01	/* UART1 Disable */
 
 /* bus mapping constants (used for PCI core initialization) */																																																 /* bus mapping constants */
 #define SC520_REG_ADDR		0x00000cf8
@@ -256,7 +256,7 @@
 /* PCI bus memory from 0x10000000 to 0x26ffffff
  * (make 0x27000000 - 0x27ffffff available for stuff like PCCard boot) */
 #define SC520_PCI_MEM_PHYS	0x10000000
-#define SC520_PCI_MEM_BUS       0x10000000
+#define SC520_PCI_MEM_BUS	0x10000000
 #define SC520_PCI_MEM_SIZE	0x17000000
 
 /* 0x28000000 - 0x3fffffff is used by the flash banks */
diff --git a/include/asm-m68k/global_data.h b/include/asm-m68k/global_data.h
index c897f2b2a8..7377d313db 100644
--- a/include/asm-m68k/global_data.h
+++ b/include/asm-m68k/global_data.h
@@ -73,6 +73,8 @@ typedef	struct	global_data {
 #define	GD_FLG_DEVINIT	0x00002		/* Devices have been initialized	*/
 #define	GD_FLG_SILENT	0x00004		/* Silent mode				*/
 #define	GD_FLG_POSTFAIL	0x00008		/* Critical POST test failed		*/
+#define	GD_FLG_POSTSTOP	0x00010		/* POST seqeunce aborted		*/
+#define	GD_FLG_LOGINIT	0x00020		/* Log Buffer has been initialized	*/
 
 #if 0
 extern gd_t *global_data;
diff --git a/include/asm-m68k/m5249.h b/include/asm-m68k/m5249.h
index 5ed3cbc056..facf0c9090 100644
--- a/include/asm-m68k/m5249.h
+++ b/include/asm-m68k/m5249.h
@@ -58,7 +58,7 @@
 #define	MCFSIM_SYPCR		0x01	/* System Protection reg (r/w) */
 #define	MCFSIM_SWIVR		0x02	/* SW Watchdog intr reg (r/w) */
 #define	MCFSIM_SWSR		0x03	/* SW Watchdog service (r/w) */
-#define MCFSIM_MPARK  		0x0c	/* Bus master park register (r/w) */
+#define MCFSIM_MPARK		0x0c	/* Bus master park register (r/w) */
 
 #define	MCFSIM_SIMR		0x00	/* SIM Config reg (r/w) */
 #define	MCFSIM_ICR0		0x4c	/* Intr Ctrl reg 0 (r/w) */
diff --git a/include/asm-m68k/m5282.h b/include/asm-m68k/m5282.h
index 7473bb9be6..f6a6b0408f 100644
--- a/include/asm-m68k/m5282.h
+++ b/include/asm-m68k/m5282.h
@@ -382,15 +382,15 @@
 #define MCFCCM_CIR		(*(vu_short *)(CFG_MBAR+0x0011000A))
 
 /* Bit level definitions and macros */
-#define MCFCCM_CCR_LOAD			(0x8000)
-#define MCFCCM_CCR_MODE(x) 		(((x)&0x0007)<<8)
-#define MCFCCM_CCR_SZEN  		(0x0040)
-#define MCFCCM_CCR_PSTEN 		(0x0020)
-#define MCFCCM_CCR_BME			(0x0008)
-#define MCFCCM_CCR_BMT(x)		(((x)&0x0007))
+#define MCFCCM_CCR_LOAD		(0x8000)
+#define MCFCCM_CCR_MODE(x)	(((x)&0x0007)<<8)
+#define MCFCCM_CCR_SZEN		(0x0040)
+#define MCFCCM_CCR_PSTEN	(0x0020)
+#define MCFCCM_CCR_BME		(0x0008)
+#define MCFCCM_CCR_BMT(x)	(((x)&0x0007))
 
-#define MCFCCM_CIR_PIN_MASK		(0xFF00)
-#define MCFCCM_CIR_PRN_MASK		(0x00FF)
+#define MCFCCM_CIR_PIN_MASK	(0xFF00)
+#define MCFCCM_CIR_PRN_MASK	(0x00FF)
 
 /* Clock Module */
 
@@ -554,7 +554,7 @@
 #define MCFGPT_GPTIE_C1I		(0x02)
 #define MCFGPT_GPTIE_C0I		(0x01)
 
-#define MCFGPT_GPTSCR2_TOI 		(0x80)
+#define MCFGPT_GPTSCR2_TOI		(0x80)
 #define MCFGPT_GPTSCR2_PUPT		(0x20)
 #define MCFGPT_GPTSCR2_RDPT		(0x10)
 #define MCFGPT_GPTSCR2_TCRE		(0x08)
diff --git a/include/asm-microblaze/asm.h b/include/asm-microblaze/asm.h
index f10f89c941..deb23e094a 100644
--- a/include/asm-microblaze/asm.h
+++ b/include/asm-microblaze/asm.h
@@ -74,7 +74,7 @@
 {								\
 	register unsigned tmp;					\
 	__asm__ __volatile__ ("					\
-			mfs 	%0, rmsr;			\
+			mfs	%0, rmsr;			\
 			ori	%0, %0, "#val";			\
 			mts	rmsr, %0;			\
 			nop;"					\
@@ -87,7 +87,7 @@
 {								\
 	register unsigned tmp;					\
 	__asm__ __volatile__ ("					\
-			mfs 	%0, rmsr;			\
+			mfs	%0, rmsr;			\
 			andi	%0, %0, ~"#val";		\
 			mts	rmsr, %0;			\
 			nop;"					\
diff --git a/include/asm-microblaze/global_data.h b/include/asm-microblaze/global_data.h
index 91243b22c0..376786fca9 100644
--- a/include/asm-microblaze/global_data.h
+++ b/include/asm-microblaze/global_data.h
@@ -53,6 +53,8 @@ typedef	struct	global_data {
 #define	GD_FLG_DEVINIT	0x00002		/* Devices have been initialized	*/
 #define	GD_FLG_SILENT	0x00004		/* Silent mode				*/
 #define	GD_FLG_POSTFAIL	0x00008		/* Critical POST test failed		*/
+#define	GD_FLG_POSTSTOP	0x00010		/* POST seqeunce aborted		*/
+#define	GD_FLG_LOGINIT	0x00020		/* Log Buffer has been initialized	*/
 
 #define DECLARE_GLOBAL_DATA_PTR     register volatile gd_t *gd asm ("r31")
 
diff --git a/include/asm-mips/au1x00.h b/include/asm-mips/au1x00.h
index a4e9947d93..6a33197f6c 100644
--- a/include/asm-mips/au1x00.h
+++ b/include/asm-mips/au1x00.h
@@ -5,7 +5,7 @@
  *
  * Copyright 2000,2001 MontaVista Software Inc.
  * Author: MontaVista Software, Inc.
- *         	ppopov@mvista.com or source@mvista.com
+ *	   ppopov@mvista.com or source@mvista.com
  *
  *  This program is free software; you can redistribute  it and/or modify it
  *  under  the terms of  the GNU General  Public License as published by the
diff --git a/include/asm-mips/cacheops.h b/include/asm-mips/cacheops.h
index 256ad2cc6e..70bcad7694 100644
--- a/include/asm-mips/cacheops.h
+++ b/include/asm-mips/cacheops.h
@@ -21,7 +21,7 @@
 #define Index_Store_Tag_I	0x08
 #define Index_Store_Tag_D	0x09
 #if defined(CONFIG_CPU_LOONGSON2)
-#define Hit_Invalidate_I    	0x00
+#define Hit_Invalidate_I	0x00
 #else
 #define Hit_Invalidate_I	0x10
 #endif
diff --git a/include/asm-mips/global_data.h b/include/asm-mips/global_data.h
index bd9e4dd862..0c0ba50f42 100644
--- a/include/asm-mips/global_data.h
+++ b/include/asm-mips/global_data.h
@@ -55,6 +55,8 @@ typedef	struct	global_data {
 #define	GD_FLG_DEVINIT	0x00002		/* Devices have been initialized */
 #define	GD_FLG_SILENT	0x00004		/* Silent mode			 */
 #define	GD_FLG_POSTFAIL	0x00008		/* Critical POST test failed	 */
+#define	GD_FLG_POSTSTOP	0x00010		/* POST seqeunce aborted	 */
+#define	GD_FLG_LOGINIT	0x00020		/* Log Buf has been initialized	 */
 
 #define DECLARE_GLOBAL_DATA_PTR     register volatile gd_t *gd asm ("k0")
 
diff --git a/include/asm-mips/mipsregs.h b/include/asm-mips/mipsregs.h
index 0586c53d3b..61a0dac1ce 100644
--- a/include/asm-mips/mipsregs.h
+++ b/include/asm-mips/mipsregs.h
@@ -283,7 +283,7 @@ set_cp0_##name(unsigned int set)				\
 								\
 	res = read_32bit_cp0_register(register);                \
 	res |= set;						\
-	write_32bit_cp0_register(register, res);        	\
+	write_32bit_cp0_register(register, res);		\
 								\
 	return res;                                             \
 }								\
@@ -332,7 +332,7 @@ __BUILD_SET_CP0(config,CP0_CONFIG)
 #  define KSU_KERNEL		0x00000000
 #define ST0_UX			0x00000020
 #define ST0_SX			0x00000040
-#define ST0_KX 			0x00000080
+#define ST0_KX			0x00000080
 #define ST0_DE			0x00010000
 #define ST0_CE			0x00020000
 
@@ -362,22 +362,22 @@ __BUILD_SET_CP0(config,CP0_CONFIG)
  */
 #define TX39_CONF_ICS_SHIFT	19
 #define TX39_CONF_ICS_MASK	0x00380000
-#define TX39_CONF_ICS_1KB 	0x00000000
-#define TX39_CONF_ICS_2KB 	0x00080000
-#define TX39_CONF_ICS_4KB 	0x00100000
-#define TX39_CONF_ICS_8KB 	0x00180000
-#define TX39_CONF_ICS_16KB 	0x00200000
+#define TX39_CONF_ICS_1KB	0x00000000
+#define TX39_CONF_ICS_2KB	0x00080000
+#define TX39_CONF_ICS_4KB	0x00100000
+#define TX39_CONF_ICS_8KB	0x00180000
+#define TX39_CONF_ICS_16KB	0x00200000
 
 #define TX39_CONF_DCS_SHIFT	16
 #define TX39_CONF_DCS_MASK	0x00070000
-#define TX39_CONF_DCS_1KB 	0x00000000
-#define TX39_CONF_DCS_2KB 	0x00010000
-#define TX39_CONF_DCS_4KB 	0x00020000
-#define TX39_CONF_DCS_8KB 	0x00030000
-#define TX39_CONF_DCS_16KB 	0x00040000
-
-#define TX39_CONF_CWFON 	0x00004000
-#define TX39_CONF_WBON  	0x00002000
+#define TX39_CONF_DCS_1KB	0x00000000
+#define TX39_CONF_DCS_2KB	0x00010000
+#define TX39_CONF_DCS_4KB	0x00020000
+#define TX39_CONF_DCS_8KB	0x00030000
+#define TX39_CONF_DCS_16KB	0x00040000
+
+#define TX39_CONF_CWFON		0x00004000
+#define TX39_CONF_WBON		0x00002000
 #define TX39_CONF_RF_SHIFT	10
 #define TX39_CONF_RF_MASK	0x00000c00
 #define TX39_CONF_DOZE		0x00000200
diff --git a/include/asm-nios/global_data.h b/include/asm-nios/global_data.h
index ddd66cfd40..a8cc987893 100644
--- a/include/asm-nios/global_data.h
+++ b/include/asm-nios/global_data.h
@@ -46,6 +46,8 @@ typedef	struct	global_data {
 #define	GD_FLG_DEVINIT	0x00002		/* Devices have been initialized	*/
 #define	GD_FLG_SILENT	0x00004		/* Silent mode				*/
 #define	GD_FLG_POSTFAIL	0x00008		/* Critical POST test failed		*/
+#define	GD_FLG_POSTSTOP	0x00010		/* POST seqeunce aborted		*/
+#define	GD_FLG_LOGINIT	0x00020		/* Log Buffer has been initialized	*/
 
 #define DECLARE_GLOBAL_DATA_PTR     register gd_t *gd asm ("%g7")
 
diff --git a/include/asm-nios/io.h b/include/asm-nios/io.h
index 12a0bd9152..8b788068b3 100644
--- a/include/asm-nios/io.h
+++ b/include/asm-nios/io.h
@@ -34,21 +34,21 @@
 #define readb(addr)\
 	({unsigned char val;\
 	 asm volatile(  "	pfxio	0		\n"\
-		 	"	ld	%0, [%1]	\n"\
+			"	ld	%0, [%1]	\n"\
 			"	ext8d	%0, %1		\n"\
 			:"=r"(val) : "r" (addr)); val;})
 
 #define readw(addr)\
 	({unsigned short val;\
 	 asm volatile(  "	pfxio	0		\n"\
-		 	"	ld	%0, [%1]	\n"\
+			"	ld	%0, [%1]	\n"\
 			"	ext16d	%0, %1		\n"\
 			:"=r"(val) : "r" (addr)); val;})
 
 #define readl(addr)\
 	({unsigned long val;\
 	 asm volatile(  "	pfxio	0		\n"\
-		 	"	ld	%0, [%1]	\n"\
+			"	ld	%0, [%1]	\n"\
 			:"=r"(val) : "r" (addr)); val;})
 
 #define writeb(addr,val)\
diff --git a/include/asm-nios2/global_data.h b/include/asm-nios2/global_data.h
index ae5f61700e..729048917b 100644
--- a/include/asm-nios2/global_data.h
+++ b/include/asm-nios2/global_data.h
@@ -45,6 +45,8 @@ typedef	struct	global_data {
 #define	GD_FLG_DEVINIT	0x00002		/* Devices have been initialized	*/
 #define	GD_FLG_SILENT	0x00004		/* Silent mode				*/
 #define	GD_FLG_POSTFAIL	0x00008		/* Critical POST test failed		*/
+#define	GD_FLG_POSTSTOP	0x00010		/* POST seqeunce aborted		*/
+#define	GD_FLG_LOGINIT	0x00020		/* Log Buffer has been initialized	*/
 
 #define DECLARE_GLOBAL_DATA_PTR     register gd_t *gd asm ("r15")
 
diff --git a/include/asm-ppc/4xx_pci.h b/include/asm-ppc/4xx_pci.h
index 3c1adec19c..30125a19ef 100644
--- a/include/asm-ppc/4xx_pci.h
+++ b/include/asm-ppc/4xx_pci.h
@@ -47,6 +47,6 @@
 #define PTM2MS          0xEF400038
 #define PTM2LA          0xEF40003C
 
-#define PCIDEVID_405GP 	0x0
+#define PCIDEVID_405GP	0x0
 
 #endif
diff --git a/include/asm-ppc/5xx_immap.h b/include/asm-ppc/5xx_immap.h
index 8e570573b6..72cbab43e4 100644
--- a/include/asm-ppc/5xx_immap.h
+++ b/include/asm-ppc/5xx_immap.h
@@ -408,31 +408,31 @@ typedef struct uimb {
 /* Internal Memory Map MPC555
 */
 typedef struct immap {
-	char               res1[262144];       	/* CMF Flash A 256 Kbytes */
-	char               res2[196608];       	/* CMF Flash B 192 Kbytes */
-	char               res3[2670592];      	/* Reserved for Flash */
-	sysconf5xx_t       im_siu_conf;        	/* SIU Configuration */
+	char               res1[262144];	/* CMF Flash A 256 Kbytes */
+	char               res2[196608];	/* CMF Flash B 192 Kbytes */
+	char               res3[2670592];	/* Reserved for Flash */
+	sysconf5xx_t       im_siu_conf;		/* SIU Configuration */
 	memctl5xx_t	   im_memctl;		/* Memory Controller */
 	sit5xx_t           im_sit;		/* System Integration Timers */
 	car5xx_t	   im_clkrst;		/* Clocks and Reset */
-	sitk5xx_t          im_sitk;            	/* System Integration Timer Keys*/
-	cark8xx_t          im_clkrstk;         	/* Clocks and Resert Keys */
+	sitk5xx_t          im_sitk;		/* System Integration Timer Keys*/
+	cark8xx_t          im_clkrstk;		/* Clocks and Resert Keys */
 	fl5xx_t	           im_fla;	        /* Flash Module A */
 	fl5xx_t	           im_flb;	        /* Flash Module B */
-	char               res4[14208];        	/* Reserved for SIU */
-	dprc5xx_t	   im_dprc;            	/* Dpram Control Register */
-	char               res5[8180];         	/* Reserved */
-	char               dptram[6144];       	/* Dptram */
-	char               res6[2048];         	/* Reserved */
+	char               res4[14208];		/* Reserved for SIU */
+	dprc5xx_t	   im_dprc;		/* Dpram Control Register */
+	char               res5[8180];		/* Reserved */
+	char               dptram[6144];	/* Dptram */
+	char               res6[2048];		/* Reserved */
 	tpu5xx_t	   im_tpua;		/* Time Proessing Unit A */
-	tpu5xx_t	   im_tpub;  	      	/* Time Processing Unit B */
-	qadc5xx_t	   im_qadca;           	/* QADC A */
-	qadc5xx_t	   im_qadcb;           	/* QADC B */
+	tpu5xx_t	   im_tpub;		/* Time Processing Unit B */
+	qadc5xx_t	   im_qadca;		/* QADC A */
+	qadc5xx_t	   im_qadcb;		/* QADC B */
 	qsmcm5xx_t	   im_qsmcm;		/* SCI and SPI */
-	mios5xx_t      	   im_mios;		/* MIOS */
-	tcan5xx_t          im_tcana;           	/* Toucan A */
-	tcan5xx_t          im_tcanb;	       	/* Toucan B */
-	char               res7[1792];         	/* Reserved */
+	mios5xx_t	   im_mios;		/* MIOS */
+	tcan5xx_t          im_tcana;		/* Toucan A */
+	tcan5xx_t          im_tcanb;		/* Toucan B */
+	char               res7[1792];		/* Reserved */
 	uimb5xx_t          im_uimb;	        /* UIMB */
 } immap_t;
 
diff --git a/include/asm-ppc/e300.h b/include/asm-ppc/e300.h
index de8239965a..05db0de8f8 100644
--- a/include/asm-ppc/e300.h
+++ b/include/asm-ppc/e300.h
@@ -16,59 +16,59 @@
  */
 
 /* #define HID0 1008 already defined in processor.h */
-#define HID0_MASK_MACHINE_CHECK              0x00000000
-#define HID0_ENABLE_MACHINE_CHECK            0x80000000
+#define HID0_MASK_MACHINE_CHECK		     0x00000000
+#define HID0_ENABLE_MACHINE_CHECK	     0x80000000
 
-#define HID0_DISABLE_CACHE_PARITY            0x00000000
-#define HID0_ENABLE_CACHE_PARITY             0x40000000
+#define HID0_DISABLE_CACHE_PARITY	     0x00000000
+#define HID0_ENABLE_CACHE_PARITY	     0x40000000
 
-#define HID0_DISABLE_ADDRESS_PARITY          0x00000000 /* on mpc8349ads must be disabled */
-#define HID0_ENABLE_ADDRESS_PARITY           0x20000000
+#define HID0_DISABLE_ADDRESS_PARITY	     0x00000000 /* on mpc8349ads must be disabled */
+#define HID0_ENABLE_ADDRESS_PARITY	     0x20000000
 
-#define HID0_DISABLE_DATA_PARITY             0x00000000 /* on mpc8349ads must be disabled */
-#define HID0_ENABLE_DATE_PARITY              0x10000000
+#define HID0_DISABLE_DATA_PARITY	     0x00000000 /* on mpc8349ads must be disabled */
+#define HID0_ENABLE_DATE_PARITY		     0x10000000
 
-#define HID0_CORE_CLK_OUT                    0x00000000
-#define HID0_CORE_CLK_OUT_DIV_2              0x08000000
+#define HID0_CORE_CLK_OUT		     0x00000000
+#define HID0_CORE_CLK_OUT_DIV_2		     0x08000000
 
 #define HID0_ENABLE_ARTRY_OUT_PRECHARGE      0x00000000 /* on mpc8349ads must be enabled */
 #define HID0_DISABLE_ARTRY_OUT_PRECHARGE     0x01000000
 
-#define HID0_DISABLE_DOSE_MODE               0x00000000
-#define HID0_ENABLE_DOSE_MODE                0x00800000
+#define HID0_DISABLE_DOSE_MODE		     0x00000000
+#define HID0_ENABLE_DOSE_MODE		     0x00800000
 
-#define HID0_DISABLE_NAP_MODE                0x00000000
-#define HID0_ENABLE_NAP_MODE                 0x00400000
+#define HID0_DISABLE_NAP_MODE		     0x00000000
+#define HID0_ENABLE_NAP_MODE		     0x00400000
 
-#define HID0_DISABLE_SLEEP_MODE              0x00000000
-#define HID0_ENABLE_SLEEP_MODE               0x00200000
+#define HID0_DISABLE_SLEEP_MODE		     0x00000000
+#define HID0_ENABLE_SLEEP_MODE		     0x00200000
 
 #define HID0_DISABLE_DYNAMIC_POWER_MANAGMENT 0x00000000
 #define HID0_ENABLE_DYNAMIC_POWER_MANAGMENT  0x00100000
 
-#define HID0_SOFT_RESET                      0x00010000
+#define HID0_SOFT_RESET			     0x00010000
 
-#define HID0_DISABLE_INSTRUCTION_CACHE       0x00000000
-#define HID0_ENABLE_INSTRUCTION_CACHE        0x00008000
+#define HID0_DISABLE_INSTRUCTION_CACHE	     0x00000000
+#define HID0_ENABLE_INSTRUCTION_CACHE	     0x00008000
 
-#define HID0_DISABLE_DATA_CACHE              0x00000000
-#define HID0_ENABLE_DATA_CACHE               0x00004000
+#define HID0_DISABLE_DATA_CACHE		     0x00000000
+#define HID0_ENABLE_DATA_CACHE		     0x00004000
 
-#define HID0_LOCK_INSTRUCTION_CACHE          0x00002000
+#define HID0_LOCK_INSTRUCTION_CACHE	     0x00002000
 
-#define HID0_LOCK_DATA_CACHE                 0x00001000
+#define HID0_LOCK_DATA_CACHE		     0x00001000
 
 #define HID0_INVALIDATE_INSTRUCTION_CACHE    0x00000800
 
-#define HID0_INVALIDATE_DATA_CACHE           0x00000400
+#define HID0_INVALIDATE_DATA_CACHE	     0x00000400
 
-#define HID0_DISABLE_M_BIT                   0x00000000
-#define HID0_ENABLE_M_BIT                    0x00000080
+#define HID0_DISABLE_M_BIT		     0x00000000
+#define HID0_ENABLE_M_BIT		     0x00000080
 
-#define HID0_FBIOB                           0x00000010
+#define HID0_FBIOB			     0x00000010
 
-#define HID0_DISABLE_ADDRESS_BROADCAST       0x00000000
-#define HID0_ENABLE_ADDRESS_BROADCAST        0x00000008
+#define HID0_DISABLE_ADDRESS_BROADCAST	     0x00000000
+#define HID0_ENABLE_ADDRESS_BROADCAST	     0x00000008
 
 #define HID0_ENABLE_NOOP_DCACHE_INSTRUCTION  0x00000000
 #define HID0_DISABLE_NOOP_DCACHE_INSTRUCTION 0x00000001
@@ -90,37 +90,37 @@
 
 
 /* BAT (block address translation */
-#define BATU_BEPI_MSK	    0xfffe0000
-#define BATU_BL_MSK         0x00001ffc
-
-#define BATU_BL_128K        0x00000000
-#define BATU_BL_256K        0x00000004
-#define BATU_BL_512K        0x0000000c
-#define BATU_BL_1M          0x0000001c
-#define BATU_BL_2M          0x0000003c
-#define BATU_BL_4M          0x0000007c
-#define BATU_BL_8M          0x000000fc
-#define BATU_BL_16M         0x000001fc
-#define BATU_BL_32M         0x000003fc
-#define BATU_BL_64M         0x000007fc
-#define BATU_BL_128M        0x00000ffc
-#define BATU_BL_256M        0x00001ffc
-
-#define BATU_VS             0x00000002
-#define BATU_VP             0x00000001
-
-#define BATL_BRPN_MSK       0xfffe0000
-#define BATL_WIMG_MSK       0x00000078
-
-#define BATL_WRITETHROUGH   0x00000040
-#define BATL_CACHEINHIBIT   0x00000020
-#define BATL_MEMCOHERENCE   0x00000010
-#define BATL_GUARDEDSTORAGE 0x00000008
-
-#define BATL_PP_MSK         0x00000003
-#define BATL_PP_00          0x00000000 /* No access */
-#define BATL_PP_01          0x00000001 /* Read-only */
-#define BATL_PP_10          0x00000002 /* Read-write */
-#define BATL_PP_11        	0x00000003
+#define BATU_BEPI_MSK		0xfffe0000
+#define BATU_BL_MSK		0x00001ffc
+
+#define BATU_BL_128K		0x00000000
+#define BATU_BL_256K		0x00000004
+#define BATU_BL_512K		0x0000000c
+#define BATU_BL_1M		0x0000001c
+#define BATU_BL_2M		0x0000003c
+#define BATU_BL_4M		0x0000007c
+#define BATU_BL_8M		0x000000fc
+#define BATU_BL_16M		0x000001fc
+#define BATU_BL_32M		0x000003fc
+#define BATU_BL_64M		0x000007fc
+#define BATU_BL_128M		0x00000ffc
+#define BATU_BL_256M		0x00001ffc
+
+#define BATU_VS			0x00000002
+#define BATU_VP			0x00000001
+
+#define BATL_BRPN_MSK		0xfffe0000
+#define BATL_WIMG_MSK		0x00000078
+
+#define BATL_WRITETHROUGH	0x00000040
+#define BATL_CACHEINHIBIT	0x00000020
+#define BATL_MEMCOHERENCE	0x00000010
+#define BATL_GUARDEDSTORAGE	0x00000008
+
+#define BATL_PP_MSK		0x00000003
+#define BATL_PP_00		0x00000000 /* No access */
+#define BATL_PP_01		0x00000001 /* Read-only */
+#define BATL_PP_10		0x00000002 /* Read-write */
+#define BATL_PP_11		0x00000003
 
 #endif	/* __E300_H__ */
diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h
index 202c8441c2..ea702662f8 100644
--- a/include/asm-ppc/global_data.h
+++ b/include/asm-ppc/global_data.h
@@ -168,6 +168,8 @@ typedef	struct	global_data {
 #define	GD_FLG_DEVINIT	0x00002		/* Devices have been initialized	*/
 #define	GD_FLG_SILENT	0x00004		/* Silent mode				*/
 #define	GD_FLG_POSTFAIL	0x00008		/* Critical POST test failed		*/
+#define	GD_FLG_POSTSTOP	0x00010		/* POST seqeunce aborted		*/
+#define	GD_FLG_LOGINIT	0x00020		/* Log Buffer has been initialized	*/
 
 #if 1
 #define DECLARE_GLOBAL_DATA_PTR     register volatile gd_t *gd asm ("r2")
diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h
index 2d07625464..113ba482da 100644
--- a/include/asm-ppc/immap_85xx.h
+++ b/include/asm-ppc/immap_85xx.h
@@ -1054,7 +1054,7 @@ typedef struct ccsr_cpm {
  * 0x9000-0x90bff: General SIU
  */
 typedef struct ccsr_cpm_siu {
-	char 	res1[80];
+	char	res1[80];
 	uint	smaer;
 	uint	smser;
 	uint	smevr;
@@ -1143,9 +1143,9 @@ typedef struct ccsr_cpm_timer {
 /* 0x91018-0x912ff: SDMA */
 typedef struct ccsr_cpm_sdma {
 	uchar	sdsr;
-	char 	res1[3];
-	uchar 	sdmr;
-	char 	res2[739];
+	char	res1[3];
+	uchar	sdmr;
+	char	res2[739];
 } ccsr_cpm_sdma_t;
 
 /* 0x91300-0x9131f: FCC1 */
@@ -1228,7 +1228,7 @@ typedef struct ccsr_cpm_fcc3_ext {
 
 /* 0x91400-0x915ef: TC layers */
 typedef struct ccsr_cpm_tmp1 {
-	char 	res[496];
+	char	res[496];
 } ccsr_cpm_tmp1_t;
 
 /* 0x915f0-0x9185f: BRGs:5,6,7,8 */
@@ -1296,7 +1296,7 @@ typedef struct ccsr_cpm_scc {
 
 /* 0x91a80-0x91a9f */
 typedef struct ccsr_cpm_tmp2 {
-	char 	res[32];
+	char	res[32];
 } ccsr_cpm_tmp2_t;
 
 /* 0x91aa0-0x91aff: SPI */
@@ -1338,16 +1338,16 @@ typedef struct ccsr_cpm {
 	/* Some references are into the unique and known dpram spaces,
 	 * others are from the generic base.
 	 */
-#define im_dprambase    	im_dpram1
-	u_char          	im_dpram1[16*1024];
-	char            	res1[16*1024];
-	u_char          	im_dpram2[16*1024];
-	char            	res2[16*1024];
-	ccsr_cpm_siu_t  	im_cpm_siu;     /* SIU Configuration */
-	ccsr_cpm_intctl_t    	im_cpm_intctl;  /* Interrupt Controller */
-	ccsr_cpm_iop_t       	im_cpm_iop;     /* IO Port control/status */
-	ccsr_cpm_timer_t  	im_cpm_timer;   /* CPM timers */
-	ccsr_cpm_sdma_t      	im_cpm_sdma;    /* SDMA control/status */
+#define im_dprambase		im_dpram1
+	u_char			im_dpram1[16*1024];
+	char			res1[16*1024];
+	u_char			im_dpram2[16*1024];
+	char			res2[16*1024];
+	ccsr_cpm_siu_t		im_cpm_siu;     /* SIU Configuration */
+	ccsr_cpm_intctl_t	im_cpm_intctl;  /* Interrupt Controller */
+	ccsr_cpm_iop_t		im_cpm_iop;     /* IO Port control/status */
+	ccsr_cpm_timer_t	im_cpm_timer;   /* CPM timers */
+	ccsr_cpm_sdma_t		im_cpm_sdma;    /* SDMA control/status */
 	ccsr_cpm_fcc1_t		im_cpm_fcc1;
 	ccsr_cpm_fcc2_t		im_cpm_fcc2;
 	ccsr_cpm_fcc3_t		im_cpm_fcc3;
@@ -1553,7 +1553,7 @@ typedef struct par_io {
 typedef struct ccsr_gur {
 	uint	porpllsr;	/* 0xe0000 - POR PLL ratio status register */
 	uint	porbmsr;	/* 0xe0004 - POR boot mode status register */
-#define MPC85xx_PORBMSR_HA 		0x00070000
+#define MPC85xx_PORBMSR_HA		0x00070000
 	uint	porimpscr;	/* 0xe0008 - POR I/O impedance status and control register */
 	uint	pordevsr;	/* 0xe000c - POR I/O device status regsiter */
 #define MPC85xx_PORDEVSR_SGMII1_DIS	0x20000000
@@ -1561,13 +1561,13 @@ typedef struct ccsr_gur {
 #define MPC85xx_PORDEVSR_SGMII3_DIS	0x08000000
 #define MPC85xx_PORDEVSR_SGMII4_DIS	0x04000000
 #define MPC85xx_PORDEVSR_IO_SEL		0x00380000
-#define MPC85xx_PORDEVSR_PCI2_ARB 	0x00040000
-#define MPC85xx_PORDEVSR_PCI1_ARB 	0x00020000
-#define MPC85xx_PORDEVSR_PCI1_PCI32 	0x00010000
-#define MPC85xx_PORDEVSR_PCI1_SPD 	0x00008000
-#define MPC85xx_PORDEVSR_PCI2_SPD 	0x00004000
+#define MPC85xx_PORDEVSR_PCI2_ARB	0x00040000
+#define MPC85xx_PORDEVSR_PCI1_ARB	0x00020000
+#define MPC85xx_PORDEVSR_PCI1_PCI32	0x00010000
+#define MPC85xx_PORDEVSR_PCI1_SPD	0x00008000
+#define MPC85xx_PORDEVSR_PCI2_SPD	0x00004000
 #define MPC85xx_PORDEVSR_DRAM_RTYPE	0x00000060
-#define MPC85xx_PORDEVSR_RIO_CTLS 	0x00000008
+#define MPC85xx_PORDEVSR_RIO_CTLS	0x00000008
 #define MPC85xx_PORDEVSR_RIO_DEV_ID	0x00000007
 	uint	pordbgmsr;	/* 0xe0010 - POR debug mode status register */
 	uint	pordevsr2;	/* 0xe0014 - POR I/O device status regsiter 2 */
@@ -1593,13 +1593,13 @@ typedef struct ccsr_gur {
 #define MPC85xx_DEVDISR_SEC		0x01000000
 #define MPC85xx_DEVDISR_SRIO		0x00080000
 #define MPC85xx_DEVDISR_RMSG		0x00040000
-#define MPC85xx_DEVDISR_DDR 		0x00010000
-#define MPC85xx_DEVDISR_CPU 		0x00008000
-#define MPC85xx_DEVDISR_CPU0 		MPC85xx_DEVDISR_CPU
-#define MPC85xx_DEVDISR_TB 		0x00004000
-#define MPC85xx_DEVDISR_TB0 		MPC85xx_DEVDISR_TB
-#define MPC85xx_DEVDISR_CPU1 		0x00002000
-#define MPC85xx_DEVDISR_TB1 		0x00001000
+#define MPC85xx_DEVDISR_DDR		0x00010000
+#define MPC85xx_DEVDISR_CPU		0x00008000
+#define MPC85xx_DEVDISR_CPU0		MPC85xx_DEVDISR_CPU
+#define MPC85xx_DEVDISR_TB		0x00004000
+#define MPC85xx_DEVDISR_TB0		MPC85xx_DEVDISR_TB
+#define MPC85xx_DEVDISR_CPU1		0x00002000
+#define MPC85xx_DEVDISR_TB1		0x00001000
 #define MPC85xx_DEVDISR_DMA		0x00000400
 #define MPC85xx_DEVDISR_TSEC1		0x00000080
 #define MPC85xx_DEVDISR_TSEC2		0x00000040
diff --git a/include/asm-ppc/immap_86xx.h b/include/asm-ppc/immap_86xx.h
index 0b78c94f7c..c03b4b8157 100644
--- a/include/asm-ppc/immap_86xx.h
+++ b/include/asm-ppc/immap_86xx.h
@@ -119,7 +119,7 @@ typedef struct ccsr_ddr {
 	uint    sdram_mode_2;		/* 0x211c - DDR SDRAM Mode Configuration 2 */
 	uint    sdram_mode_cntl;        /* 0x2120 - DDR SDRAM Mode Control */
 	uint	sdram_interval;		/* 0x2124 - DDR SDRAM Interval Configuration */
-	uint    sdram_data_init; 	/* 0x2128 - DDR SDRAM Data Initialization */
+	uint    sdram_data_init;	/* 0x2128 - DDR SDRAM Data Initialization */
 	char	res8[4];
 	uint	sdram_clk_cntl;		/* 0x2130 - DDR SDRAM Clock Control */
 	char    res9[12];
@@ -464,7 +464,7 @@ typedef struct ccsr_dma {
 
 /* tsec1-4: 24000-28000 */
 typedef struct ccsr_tsec {
-	uint    id; 		/* 0x24000 - Controller ID Register */
+	uint    id;		/* 0x24000 - Controller ID Register */
 	char	res1[12];
 	uint	ievent;		/* 0x24010 - Interrupt Event Register */
 	uint	imask;		/* 0x24014 - Interrupt Mask Register */
@@ -538,7 +538,7 @@ typedef struct ccsr_tsec {
 	uint    rbifx;		/* 0x24330 - Receive bit field extract control Register */
 	uint    rqfar;		/* 0x24334 - Receive queue filing table address Register */
 	uint    rqfcr;		/* 0x24338 - Receive queue filing table control Register */
-	uint    rqfpr;      	/* 0x2433c - Receive queue filing table property Register */
+	uint    rqfpr;		/* 0x2433c - Receive queue filing table property Register */
 	uint	mrblr;		/* 0x24340 - Maximum Receive Buffer Length Register */
 	char	res28[56];
 	uint    rbdbph;		/* 0x2437C - Receive Data Buffer Pointer High */
diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h
index 49d6860fc7..4f78ca7a94 100644
--- a/include/asm-ppc/mmu.h
+++ b/include/asm-ppc/mmu.h
@@ -343,7 +343,7 @@ extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower);
 #define MAS0_ESEL(x)	((x << 16) & 0x0FFF0000)
 #define MAS0_NV(x)	((x) & 0x00000FFF)
 
-#define MAS1_VALID 	0x80000000
+#define MAS1_VALID	0x80000000
 #define MAS1_IPROT	0x40000000
 #define MAS1_TID(x)	((x << 16) & 0x3FFF0000)
 #define MAS1_TS		0x00001000
@@ -685,7 +685,7 @@ extern int num_tlb_entries;
 #define MSYNC				.long 0x7c000000|\
 					(598<<1)
 
-#define MBAR_INST 				.long 0x7c000000|\
+#define MBAR_INST				.long 0x7c000000|\
 					(854<<1)
 
 #ifndef __ASSEMBLY__
diff --git a/include/asm-ppc/ppc4xx-intvec.h b/include/asm-ppc/ppc4xx-intvec.h
index e2181190e3..5b45de4335 100644
--- a/include/asm-ppc/ppc4xx-intvec.h
+++ b/include/asm-ppc/ppc4xx-intvec.h
@@ -323,9 +323,9 @@
 #define VECNUM_EWU0		17	/* Ethernet wakeup sequence detected */
 
 #define VECNUM_MADMAL		18	/* Logical OR of following MadMAL int */
-#define VECNUM_MS		18	/*	MAL_SERR_INT 		*/
-#define VECNUM_TXDE		18	/* 	MAL_TXDE_INT 		*/
-#define VECNUM_RXDE		18	/*	MAL_RXDE_INT 		*/
+#define VECNUM_MS		18	/*	MAL_SERR_INT		*/
+#define VECNUM_TXDE		18	/*	MAL_TXDE_INT		*/
+#define VECNUM_RXDE		18	/*	MAL_RXDE_INT		*/
 
 #define VECNUM_MTE		19	/* MAL TXEOB			*/
 #define VECNUM_MTE1		20	/* MAL TXEOB1			*/
diff --git a/include/asm-ppc/ptrace.h b/include/asm-ppc/ptrace.h
index 3c2f4e605a..196613b9f1 100644
--- a/include/asm-ppc/ptrace.h
+++ b/include/asm-ppc/ptrace.h
@@ -39,7 +39,7 @@ struct pt_regs {
 	PPC_REG trap;		/* Reason for being here */
 	PPC_REG dar;		/* Fault registers */
 	PPC_REG dsisr;
-	PPC_REG result; 	/* Result of a system call */
+	PPC_REG result;		/* Result of a system call */
 };
 #endif
 
diff --git a/include/asm-ppc/sigcontext.h b/include/asm-ppc/sigcontext.h
index 4bd66a707d..715c868ab6 100644
--- a/include/asm-ppc/sigcontext.h
+++ b/include/asm-ppc/sigcontext.h
@@ -9,7 +9,7 @@ struct sigcontext_struct {
 	int		signal;
 	unsigned long	handler;
 	unsigned long	oldmask;
-	struct pt_regs 	*regs;
+	struct pt_regs	*regs;
 };
 
 #endif
diff --git a/include/asm-ppc/u-boot.h b/include/asm-ppc/u-boot.h
index 786ba030ea..83af2f584e 100644
--- a/include/asm-ppc/u-boot.h
+++ b/include/asm-ppc/u-boot.h
@@ -126,14 +126,14 @@ typedef struct bd_info {
 #if defined(CONFIG_4xx)
 #if defined(CONFIG_440GX) || \
     defined(CONFIG_460EX) || defined(CONFIG_460GT)
-	int 		bi_phynum[4];           /* Determines phy mapping */
-	int 		bi_phymode[4];          /* Determines phy mode */
+	int		bi_phynum[4];           /* Determines phy mapping */
+	int		bi_phymode[4];          /* Determines phy mode */
 #elif defined(CONFIG_405EP) || defined(CONFIG_440)
-	int 		bi_phynum[2];           /* Determines phy mapping */
-	int 		bi_phymode[2];          /* Determines phy mode */
+	int		bi_phynum[2];           /* Determines phy mapping */
+	int		bi_phymode[2];          /* Determines phy mode */
 #else
-	int 		bi_phynum[1];           /* Determines phy mapping */
-	int 		bi_phymode[1];          /* Determines phy mode */
+	int		bi_phynum[1];           /* Determines phy mapping */
+	int		bi_phymode[1];          /* Determines phy mode */
 #endif
 #endif /* defined(CONFIG_4xx) */
 } bd_t;
diff --git a/include/asm-sh/cpu_sh7750.h b/include/asm-sh/cpu_sh7750.h
index 3c3c30980a..4e43a465e6 100644
--- a/include/asm-sh/cpu_sh7750.h
+++ b/include/asm-sh/cpu_sh7750.h
@@ -32,108 +32,108 @@
 #endif
 
 /*      OCN     */
-#define PTEH 	0xFF000000
-#define PTEL 	0xFF000004
-#define TTB 	0xFF000008
-#define TEA 	0xFF00000C
-#define MMUCR 	0xFF000010
-#define BASRA 	0xFF000014
+#define PTEH	0xFF000000
+#define PTEL	0xFF000004
+#define TTB	0xFF000008
+#define TEA	0xFF00000C
+#define MMUCR	0xFF000010
+#define BASRA	0xFF000014
 #define BASRB	0xFF000018
 #define CCR	0xFF00001C
-#define TRA 	0xFF000020
-#define EXPEVT 	0xFF000024
-#define INTEVT 	0xFF000028
-#define PTEA 	0xFF000034
-#define QACR0 	0xFF000038
-#define QACR1 	0xFF00003C
+#define TRA	0xFF000020
+#define EXPEVT	0xFF000024
+#define INTEVT	0xFF000028
+#define PTEA	0xFF000034
+#define QACR0	0xFF000038
+#define QACR1	0xFF00003C
 
 /*      UBC     */
-#define BARA 	0xFF200000
-#define BAMRA 	0xFF200004
-#define BBRA 	0xFF200008
-#define BARB 	0xFF20000C
-#define BAMRB 	0xFF200010
-#define BBRB 	0xFF200014
-#define BDRB 	0xFF200018
-#define BDMRB 	0xFF20001C
-#define BRCR 	0xFF200020
+#define BARA	0xFF200000
+#define BAMRA	0xFF200004
+#define BBRA	0xFF200008
+#define BARB	0xFF20000C
+#define BAMRB	0xFF200010
+#define BBRB	0xFF200014
+#define BDRB	0xFF200018
+#define BDMRB	0xFF20001C
+#define BRCR	0xFF200020
 
 /*      BSC     */
 #define BCR1	0xFF800000
 #define BCR2	0xFF800004
-#define BCR3 	0xFF800050
+#define BCR3	0xFF800050
 #define BCR4	0xFE0A00F0
-#define WCR1 	0xFF800008
-#define WCR2 	0xFF80000C
-#define WCR3 	0xFF800010
-#define MCR 	0xFF800014
-#define PCR 	0xFF800018
-#define RTCSR 	0xFF80001C
-#define RTCNT 	0xFF800020
-#define RTCOR 	0xFF800024
-#define RFCR 	0xFF800028
-#define PCTRA 	0xFF80002C
-#define PDTRA 	0xFF800030
-#define PCTRB 	0xFF800040
-#define PDTRB 	0xFF800044
-#define GPIOIC 	0xFF800048
+#define WCR1	0xFF800008
+#define WCR2	0xFF80000C
+#define WCR3	0xFF800010
+#define MCR	0xFF800014
+#define PCR	0xFF800018
+#define RTCSR	0xFF80001C
+#define RTCNT	0xFF800020
+#define RTCOR	0xFF800024
+#define RFCR	0xFF800028
+#define PCTRA	0xFF80002C
+#define PDTRA	0xFF800030
+#define PCTRB	0xFF800040
+#define PDTRB	0xFF800044
+#define GPIOIC	0xFF800048
 
 /*      DMAC    */
-#define SAR0 	0xFFA00000
-#define DAR0 	0xFFA00004
+#define SAR0	0xFFA00000
+#define DAR0	0xFFA00004
 #define DMATCR0 0xFFA00008
 #define CHCR0	0xFFA0000C
-#define SAR1 	0xFFA00010
-#define DAR1 	0xFFA00014
+#define SAR1	0xFFA00010
+#define DAR1	0xFFA00014
 #define DMATCR1 0xFFA00018
-#define CHCR1 	0xFFA0001C
-#define SAR2 	0xFFA00020
-#define DAR2 	0xFFA00024
+#define CHCR1	0xFFA0001C
+#define SAR2	0xFFA00020
+#define DAR2	0xFFA00024
 #define DMATCR2 0xFFA00028
-#define CHCR2 	0xFFA0002C
-#define SAR3 	0xFFA00030
-#define DAR3 	0xFFA00034
+#define CHCR2	0xFFA0002C
+#define SAR3	0xFFA00030
+#define DAR3	0xFFA00034
 #define DMATCR3 0xFFA00038
-#define CHCR3 	0xFFA0003C
-#define DMAOR 	0xFFA00040
+#define CHCR3	0xFFA0003C
+#define DMAOR	0xFFA00040
 #define SAR4	0xFFA00050
-#define DAR4 	0xFFA00054
+#define DAR4	0xFFA00054
 #define DMATCR4 0xFFA00058
 
 /*      CPG     */
-#define FRQCR 	0xFFC00000
-#define STBCR 	0xFFC00004
-#define WTCNT 	0xFFC00008
-#define WTCSR 	0xFFC0000C
-#define STBCR2 	0xFFC00010
+#define FRQCR	0xFFC00000
+#define STBCR	0xFFC00004
+#define WTCNT	0xFFC00008
+#define WTCSR	0xFFC0000C
+#define STBCR2	0xFFC00010
 
 /*      RTC     */
 #define R64CNT	0xFFC80000
 #define RSECCNT 0xFFC80004
 #define RMINCNT 0xFFC80008
-#define RHRCNT 	0xFFC8000C
-#define RWKCNT 	0xFFC80010
+#define RHRCNT	0xFFC8000C
+#define RWKCNT	0xFFC80010
 #define RDAYCNT 0xFFC80014
 #define RMONCNT 0xFFC80018
-#define RYRCNT 	0xFFC8001C
-#define RSECAR 	0xFFC80020
-#define RMINAR 	0xFFC80024
-#define RHRAR 	0xFFC80028
-#define RWKAR 	0xFFC8002C
-#define RDAYAR 	0xFFC80030
-#define RMONAR 	0xFFC80034
-#define RCR1 	0xFFC80038
-#define RCR2 	0xFFC8003C
-#define RCR3 	0xFFC80050
-#define RYRAR 	0xFFC80054
+#define RYRCNT	0xFFC8001C
+#define RSECAR	0xFFC80020
+#define RMINAR	0xFFC80024
+#define RHRAR	0xFFC80028
+#define RWKAR	0xFFC8002C
+#define RDAYAR	0xFFC80030
+#define RMONAR	0xFFC80034
+#define RCR1	0xFFC80038
+#define RCR2	0xFFC8003C
+#define RCR3	0xFFC80050
+#define RYRAR	0xFFC80054
 
 /*      ICR     */
-#define ICR 	0xFFD00000
-#define IPRA 	0xFFD00004
-#define IPRB 	0xFFD00008
+#define ICR	0xFFD00000
+#define IPRA	0xFFD00004
+#define IPRB	0xFFD00008
 #define IPRC	0xFFD0000C
-#define IPRD 	0xFFD00010
-#define INTPRI 	0xFE080000
+#define IPRD	0xFFD00010
+#define INTPRI	0xFE080000
 #define INTREQ	0xFE080020
 #define INTMSK	0xFE080040
 #define INTMSKCL	0xFE080060
@@ -143,54 +143,54 @@
 #define CLKSTPCLR	0xFE0A0008
 
 /*      TMU     */
-#define TSTR2 	0xFE100004
-#define TCOR3 	0xFE100008
-#define TCNT3 	0xFE10000C
-#define TCR3 	0xFE100010
-#define TCOR4 	0xFE100014
-#define TCNT4 	0xFE100018
-#define TCR4 	0xFE10001C
-#define TOCR 	0xFFD80000
-#define TSTR0 	0xFFD80004
+#define TSTR2	0xFE100004
+#define TCOR3	0xFE100008
+#define TCNT3	0xFE10000C
+#define TCR3	0xFE100010
+#define TCOR4	0xFE100014
+#define TCNT4	0xFE100018
+#define TCR4	0xFE10001C
+#define TOCR	0xFFD80000
+#define TSTR0	0xFFD80004
 #define TCOR0	0xFFD80008
-#define TCNT0 	0xFFD8000C
-#define TCR0 	0xFFD80010
-#define TCOR1 	0xFFD80014
-#define TCNT1 	0xFFD80018
-#define TCR1 	0xFFD8001C
-#define TCOR2 	0xFFD80020
-#define TCNT2 	0xFFD80024
-#define TCR2 	0xFFD80028
-#define TCPR2 	0xFFD8002C
+#define TCNT0	0xFFD8000C
+#define TCR0	0xFFD80010
+#define TCOR1	0xFFD80014
+#define TCNT1	0xFFD80018
+#define TCR1	0xFFD8001C
+#define TCOR2	0xFFD80020
+#define TCNT2	0xFFD80024
+#define TCR2	0xFFD80028
+#define TCPR2	0xFFD8002C
 #define TSTR	TSTR0
 
 /*      SCI     */
-#define SCSMR1 	0xFFE00000
-#define SCBRR1 	0xFFE00004
-#define SCSCR1 	0xFFE00008
-#define SCTDR1 	0xFFE0000C
-#define SCSSR1 	0xFFE00010
-#define SCRDR1 	0xFFE00014
+#define SCSMR1	0xFFE00000
+#define SCBRR1	0xFFE00004
+#define SCSCR1	0xFFE00008
+#define SCTDR1	0xFFE0000C
+#define SCSSR1	0xFFE00010
+#define SCRDR1	0xFFE00014
 #define SCSCMR1 0xFFE00018
 #define SCSPTR1 0xFFE0001C
 #define SCF0_BASE	SCSMR1
 
 /*      SCIF    */
-#define SCSMR2 	0xFFE80000
-#define SCBRR2 	0xFFE80004
-#define SCSCR2 	0xFFE80008
+#define SCSMR2	0xFFE80000
+#define SCBRR2	0xFFE80004
+#define SCSCR2	0xFFE80008
 #define SCFTDR2 0xFFE8000C
-#define SCFSR2 	0xFFE80010
+#define SCFSR2	0xFFE80010
 #define SCFRDR2	0xFFE80014
-#define SCFCR2 	0xFFE80018
-#define SCFDR2 	0xFFE8001C
+#define SCFCR2	0xFFE80018
+#define SCFDR2	0xFFE8001C
 #define SCSPTR2	0xFFE80020
-#define SCLSR2 	0xFFE80024
+#define SCLSR2	0xFFE80024
 #define SCIF1_BASE	SCSMR2
 
 /*      H-UDI   */
-#define SDIR 	0xFFF00000
-#define SDDR 	0xFFF00008
-#define SDINT 	0xFFF00014
+#define SDIR	0xFFF00000
+#define SDDR	0xFFF00008
+#define SDINT	0xFFF00014
 
 #endif	/* _ASM_CPU_SH7750_H_ */
diff --git a/include/asm-sh/global_data.h b/include/asm-sh/global_data.h
index 521a66ffc3..69af24a770 100644
--- a/include/asm-sh/global_data.h
+++ b/include/asm-sh/global_data.h
@@ -45,6 +45,8 @@ typedef	struct global_data
 #define	GD_FLG_DEVINIT	0x00002		/* Devices have been initialized	*/
 #define	GD_FLG_SILENT	0x00004		/* Silent mode				*/
 #define	GD_FLG_POSTFAIL	0x00008		/* Critical POST test failed		*/
+#define	GD_FLG_POSTSTOP	0x00010		/* POST seqeunce aborted		*/
+#define	GD_FLG_LOGINIT	0x00020		/* Log Buffer has been initialized	*/
 
 #define DECLARE_GLOBAL_DATA_PTR	register gd_t *gd asm ("r13")
 
diff --git a/include/asm-sh/ptrace.h b/include/asm-sh/ptrace.h
index 14cc1aca63..16252cc25b 100644
--- a/include/asm-sh/ptrace.h
+++ b/include/asm-sh/ptrace.h
@@ -28,7 +28,7 @@
 
 #define REG_PR		17
 #define REG_SR		18
-#define REG_GBR      	19
+#define REG_GBR		19
 #define REG_MACH	20
 #define REG_MACL	21
 
diff --git a/include/asm-sh/system.h b/include/asm-sh/system.h
index b353bc5c3b..a62c42261d 100644
--- a/include/asm-sh/system.h
+++ b/include/asm-sh/system.h
@@ -23,21 +23,21 @@
  register unsigned long *__ts5 __asm__ ("r5") = (unsigned long *)next;	\
  register unsigned long *__ts6 __asm__ ("r6") = &next->thread.sp;	\
  register unsigned long __ts7 __asm__ ("r7") = next->thread.pc;		\
- __asm__ __volatile__ (".balign 4\n\t" 					\
-		       "stc.l	gbr, @-r15\n\t" 			\
-		       "sts.l	pr, @-r15\n\t" 				\
-		       "mov.l	r8, @-r15\n\t" 				\
-		       "mov.l	r9, @-r15\n\t" 				\
-		       "mov.l	r10, @-r15\n\t" 			\
-		       "mov.l	r11, @-r15\n\t" 			\
-		       "mov.l	r12, @-r15\n\t" 			\
-		       "mov.l	r13, @-r15\n\t" 			\
-		       "mov.l	r14, @-r15\n\t" 			\
+ __asm__ __volatile__ (".balign 4\n\t"					\
+		       "stc.l	gbr, @-r15\n\t"				\
+		       "sts.l	pr, @-r15\n\t"				\
+		       "mov.l	r8, @-r15\n\t"				\
+		       "mov.l	r9, @-r15\n\t"				\
+		       "mov.l	r10, @-r15\n\t"				\
+		       "mov.l	r11, @-r15\n\t"				\
+		       "mov.l	r12, @-r15\n\t"				\
+		       "mov.l	r13, @-r15\n\t"				\
+		       "mov.l	r14, @-r15\n\t"				\
 		       "mov.l	r15, @r1	! save SP\n\t"		\
 		       "mov.l	@r6, r15	! change to new stack\n\t" \
-		       "mova	1f, %0\n\t" 				\
-		       "mov.l	%0, @r2		! save PC\n\t" 		\
-		       "mov.l	2f, %0\n\t" 				\
+		       "mova	1f, %0\n\t"				\
+		       "mov.l	%0, @r2		! save PC\n\t"		\
+		       "mov.l	2f, %0\n\t"				\
 		       "jmp	@%0		! call __switch_to\n\t" \
 		       " lds	r7, pr		!  with return to new PC\n\t" \
 		       ".balign	4\n"					\
@@ -54,8 +54,8 @@
 		       "lds.l	@r15+, pr\n\t"				\
 		       "ldc.l	@r15+, gbr\n\t"				\
 		       : "=z" (__last)					\
-		       : "r" (__ts1), "r" (__ts2), "r" (__ts4), 	\
-			 "r" (__ts5), "r" (__ts6), "r" (__ts7) 		\
+		       : "r" (__ts1), "r" (__ts2), "r" (__ts4),		\
+			 "r" (__ts5), "r" (__ts6), "r" (__ts7)		\
 		       : "r3", "t");					\
 	last = __last;							\
 } while (0)
@@ -145,7 +145,7 @@ do {					\
 		"mov.l	1f, %0\n\t"	\
 		"or	%1, %0\n\t"	\
 		"jmp	@%0\n\t"	\
-		" nop\n\t" 		\
+		" nop\n\t"		\
 		".balign 4\n"		\
 		"1:	.long 2f\n"	\
 		"2:"			\
diff --git a/include/asm-sparc/global_data.h b/include/asm-sparc/global_data.h
index 7c29fc6840..de2c84b22b 100644
--- a/include/asm-sparc/global_data.h
+++ b/include/asm-sparc/global_data.h
@@ -79,6 +79,9 @@ typedef struct global_data {
 #define	GD_FLG_RELOC	0x00001	/* Code was relocated to RAM            */
 #define	GD_FLG_DEVINIT	0x00002	/* Devices have been initialized        */
 #define	GD_FLG_SILENT	0x00004	/* Silent mode                          */
+#define	GD_FLG_POSTFAIL	0x00008	/* Critical POST test failed		*/
+#define	GD_FLG_POSTSTOP	0x00010	/* POST seqeunce aborted		*/
+#define	GD_FLG_LOGINIT	0x00020	/* Log Buffer has been initialized	*/
 
 #define DECLARE_GLOBAL_DATA_PTR     register volatile gd_t *gd asm ("%g7")
 
diff --git a/include/bcm5221.h b/include/bcm5221.h
index 6fb94aaef5..61424b1276 100644
--- a/include/bcm5221.h
+++ b/include/bcm5221.h
@@ -23,7 +23,7 @@
  * MA 02111-1307 USA
  */
 
-#define	BCM5221_BMCR 		0	/* Basic Mode Control Register */
+#define	BCM5221_BMCR		0	/* Basic Mode Control Register */
 #define BCM5221_BMSR		1	/* Basic Mode Status Register */
 #define BCM5221_PHYID1		2	/* PHY Identifier Register 1 */
 #define BCM5221_PHYID2		3	/* PHY Identifier Register 2 */
diff --git a/include/bedbug/ppc.h b/include/bedbug/ppc.h
index 9cc8f9fa38..46bf8db1a7 100644
--- a/include/bedbug/ppc.h
+++ b/include/bedbug/ppc.h
@@ -321,7 +321,7 @@ struct opcode {
 				   array are the operand identifiers */
 
   int (*hfunc)(struct ppc_ctx *);
-  				/* Address of a function to handle the given
+				/* Address of a function to handle the given
 				   mnemonic */
 
   char *	name;		/* The symbolic name of this opcode */
diff --git a/include/bedbug/tables.h b/include/bedbug/tables.h
index 66cf8eaea3..e675de3209 100644
--- a/include/bedbug/tables.h
+++ b/include/bedbug/tables.h
@@ -12,43 +12,43 @@
  */
 
 struct operand operands[] = {
-  /*Field    Name     Bits  Shift  Hint 		   Position	*/
-  /*-----    ------   ----- -----  ---- 	           ------------ */
-  { O_AA,    "O_AA",    1,     1,  OH_SILENT },		/*   30 	*/
+  /*Field    Name     Bits  Shift  Hint			   Position	*/
+  /*-----    ------   ----- -----  ----			   ------------ */
+  { O_AA,    "O_AA",	1,     1,  OH_SILENT },		/*   30		*/
   { O_BD,    "O_BD",   14,     2,  OH_ADDR },		/* 16-29	*/
-  { O_BI,    "O_BI",    5,    16,  0 },			/* 11-15	*/
-  { O_BO,    "O_BO",    5,    21,  0 },			/*  6-10	*/
-  { O_crbD,  "O_crbD",  5,    21,  0 },			/*  6-10	*/
-  { O_crbA,  "O_crbA",  5,    16,  0 },			/* 11-15	*/
-  { O_crbB,  "O_crbB",  5,    11,  0 },			/* 16-20	*/
-  { O_CRM,   "O_CRM",   8,    12,  0 },			/* 12-19	*/
+  { O_BI,    "O_BI",	5,    16,  0 },			/* 11-15	*/
+  { O_BO,    "O_BO",	5,    21,  0 },			/*  6-10	*/
+  { O_crbD,  "O_crbD",	5,    21,  0 },			/*  6-10	*/
+  { O_crbA,  "O_crbA",	5,    16,  0 },			/* 11-15	*/
+  { O_crbB,  "O_crbB",	5,    11,  0 },			/* 16-20	*/
+  { O_CRM,   "O_CRM",	8,    12,  0 },			/* 12-19	*/
   { O_d,     "O_d",    15,     0,  OH_OFFSET },		/* 16-31	*/
-  { O_frC,   "O_frC",   5,     6,  0 },			/* 21-25	*/
-  { O_frD,   "O_frD",   5,    21,  0 },			/*  6-10	*/
-  { O_frS,   "O_frS",   5,    21,  0 },			/*  6-10	*/
-  { O_IMM,   "O_IMM",   4,    12,  0 },			/* 16-19	*/
+  { O_frC,   "O_frC",	5,     6,  0 },			/* 21-25	*/
+  { O_frD,   "O_frD",	5,    21,  0 },			/*  6-10	*/
+  { O_frS,   "O_frS",	5,    21,  0 },			/*  6-10	*/
+  { O_IMM,   "O_IMM",	4,    12,  0 },			/* 16-19	*/
   { O_LI,    "O_LI",   24,     2,  OH_ADDR },		/*  6-29	*/
-  { O_LK,    "O_LK",    1,     0,  OH_SILENT },		/*   31		*/
-  { O_MB,    "O_MB",    5,     6,  0 },			/* 21-25	*/
-  { O_ME,    "O_ME",    5,     1,  0 },			/* 26-30	*/
-  { O_NB,    "O_NB",    5,    11,  0 },			/* 16-20	*/
-  { O_OE,    "O_OE",    1,    10,  OH_SILENT },		/*   21		*/
-  { O_rA,    "O_rA",    5,    16,  OH_REG },		/* 11-15	*/
-  { O_rB,    "O_rB",    5,    11,  OH_REG },		/* 16-20	*/
-  { O_Rc,    "O_Rc",    1,     0,  OH_SILENT },		/*   31		*/
-  { O_rD,    "O_rD",    5,    21,  OH_REG },		/*  6-10	*/
-  { O_rS,    "O_rS",    5,    21,  OH_REG },		/*  6-10	*/
-  { O_SH,    "O_SH",    5,    11,  0 },			/* 16-20	*/
+  { O_LK,    "O_LK",	1,     0,  OH_SILENT },		/*   31		*/
+  { O_MB,    "O_MB",	5,     6,  0 },			/* 21-25	*/
+  { O_ME,    "O_ME",	5,     1,  0 },			/* 26-30	*/
+  { O_NB,    "O_NB",	5,    11,  0 },			/* 16-20	*/
+  { O_OE,    "O_OE",	1,    10,  OH_SILENT },		/*   21		*/
+  { O_rA,    "O_rA",	5,    16,  OH_REG },		/* 11-15	*/
+  { O_rB,    "O_rB",	5,    11,  OH_REG },		/* 16-20	*/
+  { O_Rc,    "O_Rc",	1,     0,  OH_SILENT },		/*   31		*/
+  { O_rD,    "O_rD",	5,    21,  OH_REG },		/*  6-10	*/
+  { O_rS,    "O_rS",	5,    21,  OH_REG },		/*  6-10	*/
+  { O_SH,    "O_SH",	5,    11,  0 },			/* 16-20	*/
   { O_SIMM,  "O_SIMM", 16,     0,  0 },			/* 16-31	*/
-  { O_SR,    "O_SR",    4,    16,  0 },			/* 12-15	*/
-  { O_TO,    "O_TO",    5,    21,  0 },			/*  6-10	*/
+  { O_SR,    "O_SR",	4,    16,  0 },			/* 12-15	*/
+  { O_TO,    "O_TO",	5,    21,  0 },			/*  6-10	*/
   { O_UIMM,  "O_UIMM", 16,     0,  0 },			/* 16-31	*/
-  { O_crfD,  "O_crfD",  3,    23,  0 },			/*  6- 8	*/
-  { O_crfS,  "O_crfS",  3,    18,  0 },			/* 11-13	*/
-  { O_L,     "O_L",     1,    21,  0 },			/*   10		*/
+  { O_crfD,  "O_crfD",	3,    23,  0 },			/*  6- 8	*/
+  { O_crfS,  "O_crfS",	3,    18,  0 },			/* 11-13	*/
+  { O_L,     "O_L",	1,    21,  0 },			/*   10		*/
   { O_spr,   "O_spr",  10,    11,  OH_SPR },		/* 11-20	*/
   { O_tbr,   "O_tbr",  10,    11,  OH_TBR },		/* 11-20	*/
-  { O_cr2,   "O_cr2",   0,     0,  OH_LITERAL },        /* "cr2"        */
+  { O_cr2,   "O_cr2",	0,     0,  OH_LITERAL },	/* "cr2"	*/
 };
 
 const unsigned int n_operands = sizeof(operands) / sizeof(operands[0]);
@@ -64,418 +64,418 @@ const unsigned int n_operands = sizeof(operands) / sizeof(operands[0]);
    bit locations */
 
 struct opcode opcodes[] = {
-  { D_OPCODE(3),           D_MASK,   {O_TO, O_rA, O_SIMM, 0},
-    0,               "twi",          0 },
-  { D_OPCODE(7),           D_MASK,   {O_rD, O_rA, O_SIMM, 0},
-    0,               "mulli",        0 },
-  { D_OPCODE(8),           D_MASK,   {O_rD, O_rA, O_SIMM, 0},
-    0,               "subfic",       0 },
-  { D_OPCODE(10),          D_MASK,   {O_crfD, O_L, O_rA, O_UIMM, 0},
-    0,               "cmpli",        0 },
-  { D_OPCODE(11),          D_MASK,   {O_crfD, O_L, O_rA, O_SIMM, 0},
-    0,               "cmpi",         0 },
-  { D_OPCODE(12),          D_MASK,   {O_rD, O_rA, O_SIMM, 0},
-    0,               "addic",        0 },
-  { D_OPCODE(13),          D_MASK,   {O_rD, O_rA, O_SIMM, 0},
-    0,               "addic.",       0 },
-  { D_OPCODE(14),          D_MASK,   {O_rD, O_rA, O_SIMM, 0},
-    0,               "addi",         H_RA0_IS_0 },
-  { D_OPCODE(15),          D_MASK,   {O_rD, O_rA, O_SIMM, 0},
-    0,               "addis",        H_RA0_IS_0|H_IMM_HIGH },
-  { B_OPCODE(16,0,0),      B_MASK,   {O_BO, O_BI, O_BD, O_AA, O_LK, 0},
-    handle_bc,       "bc",           H_RELATIVE },
-  { B_OPCODE(16,0,1),      B_MASK,   {O_BO, O_BI, O_BD, O_AA, O_LK, 0},
-    0,               "bcl",          H_RELATIVE },
-  { B_OPCODE(16,1,0),      B_MASK,   {O_BO, O_BI, O_BD, O_AA, O_LK, 0},
-    0,               "bca",          0 },
-  { B_OPCODE(16,1,1),      B_MASK,   {O_BO, O_BI, O_BD, O_AA, O_LK, 0},
-    0,               "bcla",         0 },
-  { SC_OPCODE(17),         SC_MASK,  {0},
-    0,               "sc",           0 },
-  { I_OPCODE(18,0,0),      I_MASK,   {O_LI, O_AA, O_LK, 0},
-    0,               "b",            H_RELATIVE },
-  { I_OPCODE(18,0,1),      I_MASK,   {O_LI, O_AA, O_LK, 0},
-    0,               "bl",           H_RELATIVE },
-  { I_OPCODE(18,1,0),      I_MASK,   {O_LI, O_AA, O_LK, 0},
-    0,               "ba",           0 },
-  { I_OPCODE(18,1,1),      I_MASK,   {O_LI, O_AA, O_LK, 0},
-    0,               "bla",          0 },
-  { XL_OPCODE(19,0,0),     XL_MASK,  {O_crfD, O_crfS},
-    0,               "mcrf",         0 },
+  { D_OPCODE(3),	   D_MASK,   {O_TO, O_rA, O_SIMM, 0},
+    0,		     "twi",	     0 },
+  { D_OPCODE(7),	   D_MASK,   {O_rD, O_rA, O_SIMM, 0},
+    0,		     "mulli",	     0 },
+  { D_OPCODE(8),	   D_MASK,   {O_rD, O_rA, O_SIMM, 0},
+    0,		     "subfic",	     0 },
+  { D_OPCODE(10),	   D_MASK,   {O_crfD, O_L, O_rA, O_UIMM, 0},
+    0,		     "cmpli",	     0 },
+  { D_OPCODE(11),	   D_MASK,   {O_crfD, O_L, O_rA, O_SIMM, 0},
+    0,		     "cmpi",	     0 },
+  { D_OPCODE(12),	   D_MASK,   {O_rD, O_rA, O_SIMM, 0},
+    0,		     "addic",	     0 },
+  { D_OPCODE(13),	   D_MASK,   {O_rD, O_rA, O_SIMM, 0},
+    0,		     "addic.",	     0 },
+  { D_OPCODE(14),	   D_MASK,   {O_rD, O_rA, O_SIMM, 0},
+    0,		     "addi",	     H_RA0_IS_0 },
+  { D_OPCODE(15),	   D_MASK,   {O_rD, O_rA, O_SIMM, 0},
+    0,		     "addis",	     H_RA0_IS_0|H_IMM_HIGH },
+  { B_OPCODE(16,0,0),	   B_MASK,   {O_BO, O_BI, O_BD, O_AA, O_LK, 0},
+    handle_bc,	     "bc",	     H_RELATIVE },
+  { B_OPCODE(16,0,1),	   B_MASK,   {O_BO, O_BI, O_BD, O_AA, O_LK, 0},
+    0,		     "bcl",	     H_RELATIVE },
+  { B_OPCODE(16,1,0),	   B_MASK,   {O_BO, O_BI, O_BD, O_AA, O_LK, 0},
+    0,		     "bca",	     0 },
+  { B_OPCODE(16,1,1),	   B_MASK,   {O_BO, O_BI, O_BD, O_AA, O_LK, 0},
+    0,		     "bcla",	     0 },
+  { SC_OPCODE(17),	   SC_MASK,  {0},
+    0,		     "sc",	     0 },
+  { I_OPCODE(18,0,0),	   I_MASK,   {O_LI, O_AA, O_LK, 0},
+    0,		     "b",	     H_RELATIVE },
+  { I_OPCODE(18,0,1),	   I_MASK,   {O_LI, O_AA, O_LK, 0},
+    0,		     "bl",	     H_RELATIVE },
+  { I_OPCODE(18,1,0),	   I_MASK,   {O_LI, O_AA, O_LK, 0},
+    0,		     "ba",	     0 },
+  { I_OPCODE(18,1,1),	   I_MASK,   {O_LI, O_AA, O_LK, 0},
+    0,		     "bla",	     0 },
+  { XL_OPCODE(19,0,0),	   XL_MASK,  {O_crfD, O_crfS},
+    0,		     "mcrf",	     0 },
   { XL_OPCODE(19,16,0),    XL_MASK,  {O_BO, O_BI, O_LK, 0},
-    0,               "bclr",         0 },
+    0,		     "bclr",	     0 },
   { XL_OPCODE(19,16,1),    XL_MASK,  {O_BO, O_BI, O_LK, 0},
-    0,               "bclrl",        0 },
+    0,		     "bclrl",	     0 },
   { XL_OPCODE(19,33,0),    XL_MASK,  {O_crbD, O_crbA, O_crbB, 0},
-    0,               "crnor",        0 },
+    0,		     "crnor",	     0 },
   { XL_OPCODE(19,50,0),    XL_MASK,  {0},
-    0,               "rfi",          0 },
+    0,		     "rfi",	     0 },
   { XL_OPCODE(19,129,0),   XL_MASK,  {O_crbD, O_crbA, O_crbB, 0},
-    0,               "crandc",       0 },
+    0,		     "crandc",	     0 },
   { XL_OPCODE(19,150,0),   XL_MASK,  {0},
-    0,               "isync",        0 },
+    0,		     "isync",	     0 },
   { XL_OPCODE(19,193,0),   XL_MASK,  {O_crbD, O_crbA, O_crbB, 0},
-    0,               "crxor",        0 },
+    0,		     "crxor",	     0 },
   { XL_OPCODE(19,225,0),   XL_MASK,  {O_crbD, O_crbA, O_crbB, 0},
-    0,               "crnand",       0 },
+    0,		     "crnand",	     0 },
   { XL_OPCODE(19,257,0),   XL_MASK,  {O_crbD, O_crbA, O_crbB, 0},
-    0,               "crand",        0 },
+    0,		     "crand",	     0 },
   { XL_OPCODE(19,289,0),   XL_MASK,  {O_crbD, O_crbA, O_crbB, 0},
-    0,               "creqv",        0 },
+    0,		     "creqv",	     0 },
   { XL_OPCODE(19,417,0),   XL_MASK,  {O_crbD, O_crbA, O_crbB, 0},
-    0,               "crorc",        0 },
+    0,		     "crorc",	     0 },
   { XL_OPCODE(19,449,0),   XL_MASK,  {O_crbD, O_crbA, O_crbB, 0},
-    0,               "cror",         0 },
+    0,		     "cror",	     0 },
   { XL_OPCODE(19,528,0),   XL_MASK,  {O_BO, O_BI, O_LK, 0},
-    0,               "bcctr",        0 },
+    0,		     "bcctr",	     0 },
   { XL_OPCODE(19,528,1),   XL_MASK,  {O_BO, O_BI, O_LK, 0},
-    0,               "bcctrl",       0 },
-  { M_OPCODE(20,0),        M_MASK,   {O_rA, O_rS, O_SH, O_MB, O_ME, O_Rc, 0},
-    0,               "rlwimi",       0 },
-  { M_OPCODE(20,1),        M_MASK,   {O_rA, O_rS, O_SH, O_MB, O_ME, O_Rc, 0},
-    0,               "rlwimi.",      0 },
-  { M_OPCODE(21,0),        M_MASK,   {O_rA, O_rS, O_SH, O_MB, O_ME, O_Rc, 0},
-    0,               "rlwinm",       0 },
-  { M_OPCODE(21,1),        M_MASK,   {O_rA, O_rS, O_SH, O_MB, O_ME, O_Rc, 0},
-    0,               "rlwinm.",      0 },
-  { M_OPCODE(23,0),        M_MASK,   {O_rA, O_rS, O_rB, O_MB, O_ME, O_Rc, 0},
-    0,               "rlwnm",        0 },
-  { M_OPCODE(23,1),        M_MASK,   {O_rA, O_rS, O_rB, O_MB, O_ME, O_Rc, 0},
-    0,               "rlwnm.",       0 },
-  { D_OPCODE(24),          D_MASK,   {O_rA, O_rS, O_UIMM, 0},
-    0,               "ori",          0 },
-  { D_OPCODE(25),          D_MASK,   {O_rA, O_rS, O_UIMM, 0},
-    0,               "oris",         H_IMM_HIGH },
-  { D_OPCODE(26),          D_MASK,   {O_rA, O_rS, O_UIMM, 0},
-    0,               "xori",         0 },
-  { D_OPCODE(27),          D_MASK,   {O_rA, O_rS, O_UIMM, 0},
-    0,               "xoris",        H_IMM_HIGH },
-  { D_OPCODE(28),          D_MASK,   {O_rA, O_rS, O_UIMM, 0},
-    0,               "andi.",        0 },
-  { D_OPCODE(29),          D_MASK,   {O_rA, O_rS, O_UIMM, 0},
-    0,               "andis.",       H_IMM_HIGH },
-  { X_OPCODE(31,0,0),      X_MASK,   {O_crfD, O_L, O_rA, O_rB, 0},
-    0,               "cmp",          0 },
-  { X_OPCODE(31,4,0),      X_MASK,   {O_TO, O_rA, O_rB, 0},
-    0,               "tw",           0 },
+    0,		     "bcctrl",	     0 },
+  { M_OPCODE(20,0),	   M_MASK,   {O_rA, O_rS, O_SH, O_MB, O_ME, O_Rc, 0},
+    0,		     "rlwimi",	     0 },
+  { M_OPCODE(20,1),	   M_MASK,   {O_rA, O_rS, O_SH, O_MB, O_ME, O_Rc, 0},
+    0,		     "rlwimi.",      0 },
+  { M_OPCODE(21,0),	   M_MASK,   {O_rA, O_rS, O_SH, O_MB, O_ME, O_Rc, 0},
+    0,		     "rlwinm",	     0 },
+  { M_OPCODE(21,1),	   M_MASK,   {O_rA, O_rS, O_SH, O_MB, O_ME, O_Rc, 0},
+    0,		     "rlwinm.",      0 },
+  { M_OPCODE(23,0),	   M_MASK,   {O_rA, O_rS, O_rB, O_MB, O_ME, O_Rc, 0},
+    0,		     "rlwnm",	     0 },
+  { M_OPCODE(23,1),	   M_MASK,   {O_rA, O_rS, O_rB, O_MB, O_ME, O_Rc, 0},
+    0,		     "rlwnm.",	     0 },
+  { D_OPCODE(24),	   D_MASK,   {O_rA, O_rS, O_UIMM, 0},
+    0,		     "ori",	     0 },
+  { D_OPCODE(25),	   D_MASK,   {O_rA, O_rS, O_UIMM, 0},
+    0,		     "oris",	     H_IMM_HIGH },
+  { D_OPCODE(26),	   D_MASK,   {O_rA, O_rS, O_UIMM, 0},
+    0,		     "xori",	     0 },
+  { D_OPCODE(27),	   D_MASK,   {O_rA, O_rS, O_UIMM, 0},
+    0,		     "xoris",	     H_IMM_HIGH },
+  { D_OPCODE(28),	   D_MASK,   {O_rA, O_rS, O_UIMM, 0},
+    0,		     "andi.",	     0 },
+  { D_OPCODE(29),	   D_MASK,   {O_rA, O_rS, O_UIMM, 0},
+    0,		     "andis.",	     H_IMM_HIGH },
+  { X_OPCODE(31,0,0),	   X_MASK,   {O_crfD, O_L, O_rA, O_rB, 0},
+    0,		     "cmp",	     0 },
+  { X_OPCODE(31,4,0),	   X_MASK,   {O_TO, O_rA, O_rB, 0},
+    0,		     "tw",	     0 },
   { XO_OPCODE(31,8,0,0),   XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
-    0,               "subfc",        0 },
+    0,		     "subfc",	     0 },
   { XO_OPCODE(31,8,0,1),   XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
-    0,               "subfc.",       0 },
+    0,		     "subfc.",	     0 },
   { XO_OPCODE(31,10,0,0),  XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
-    0,               "addc",         0 },
+    0,		     "addc",	     0 },
   { XO_OPCODE(31,10,0,1),  XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
-    0,               "addc.",        0 },
+    0,		     "addc.",	     0 },
   { XO_OPCODE(31,11,0,0),  XO_MASK,  {O_rD, O_rA, O_rB, O_Rc, 0},
-    0,               "mulhwu",       0 },
+    0,		     "mulhwu",	     0 },
   { XO_OPCODE(31,11,0,1),  XO_MASK,  {O_rD, O_rA, O_rB, O_Rc, 0},
-    0,               "mulhwu.",      0 },
-  { X_OPCODE(31,19,0),     X_MASK,   {O_rD, 0},
-    0,               "mfcr",         0 },
-  { X_OPCODE(31,20,0),     X_MASK,   {O_rD, O_rA, O_rB, 0},
-    0,               "lwarx",        H_RA0_IS_0 },
-  { X_OPCODE(31,23,0),     X_MASK,   {O_rD, O_rA, O_rB, 0},
-    0,               "lwzx",         H_RA0_IS_0 },
-  { X_OPCODE(31,24,0),     X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
-    0,               "slw",          0 },
-  { X_OPCODE(31,24,1),     X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
-    0,               "slw.",         0 },
-  { X_OPCODE(31,26,0),     X_MASK,   {O_rA, O_rS, O_Rc, 0 },
-    0,               "cntlzw",       0 },
-  { X_OPCODE(31,26,1),     X_MASK,   {O_rA, O_rS, O_Rc, 0},
-    0,               "cntlzw.",      0 },
-  { X_OPCODE(31,28,0),     X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
-    0,               "and",          0 },
-  { X_OPCODE(31,28,1),     X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
-    0,               "and.",         0 },
-  { X_OPCODE(31,32,0),     X_MASK,   {O_crfD, O_L, O_rA, O_rB, 0},
-    0,               "cmpl",         0 },
+    0,		     "mulhwu.",      0 },
+  { X_OPCODE(31,19,0),	   X_MASK,   {O_rD, 0},
+    0,		     "mfcr",	     0 },
+  { X_OPCODE(31,20,0),	   X_MASK,   {O_rD, O_rA, O_rB, 0},
+    0,		     "lwarx",	     H_RA0_IS_0 },
+  { X_OPCODE(31,23,0),	   X_MASK,   {O_rD, O_rA, O_rB, 0},
+    0,		     "lwzx",	     H_RA0_IS_0 },
+  { X_OPCODE(31,24,0),	   X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
+    0,		     "slw",	     0 },
+  { X_OPCODE(31,24,1),	   X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
+    0,		     "slw.",	     0 },
+  { X_OPCODE(31,26,0),	   X_MASK,   {O_rA, O_rS, O_Rc, 0 },
+    0,		     "cntlzw",	     0 },
+  { X_OPCODE(31,26,1),	   X_MASK,   {O_rA, O_rS, O_Rc, 0},
+    0,		     "cntlzw.",      0 },
+  { X_OPCODE(31,28,0),	   X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
+    0,		     "and",	     0 },
+  { X_OPCODE(31,28,1),	   X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
+    0,		     "and.",	     0 },
+  { X_OPCODE(31,32,0),	   X_MASK,   {O_crfD, O_L, O_rA, O_rB, 0},
+    0,		     "cmpl",	     0 },
   { XO_OPCODE(31,40,0,0),  XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
-    0,               "subf",         0 },
+    0,		     "subf",	     0 },
   { XO_OPCODE(31,40,0,1),  XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
-    0,               "subf.",        0 },
-  { X_OPCODE(31,54,0),     X_MASK,   {O_rA, O_rB, 0},
-    0,               "dcbst",        H_RA0_IS_0 },
-  { X_OPCODE(31,55,0),     X_MASK,   {O_rD, O_rA, O_rB, 0},
-    0,               "lwzux",        0 },
-  { X_OPCODE(31,60,0),     X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
-    0,               "andc",         0 },
-  { X_OPCODE(31,60,1),     X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
-    0,               "andc.",        0 },
+    0,		     "subf.",	     0 },
+  { X_OPCODE(31,54,0),	   X_MASK,   {O_rA, O_rB, 0},
+    0,		     "dcbst",	     H_RA0_IS_0 },
+  { X_OPCODE(31,55,0),	   X_MASK,   {O_rD, O_rA, O_rB, 0},
+    0,		     "lwzux",	     0 },
+  { X_OPCODE(31,60,0),	   X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
+    0,		     "andc",	     0 },
+  { X_OPCODE(31,60,1),	   X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
+    0,		     "andc.",	     0 },
   { XO_OPCODE(31,75,0,0),  XO_MASK,  {O_rD, O_rA, O_rB, O_Rc, 0},
-    0,               "mulhw",        0 },
+    0,		     "mulhw",	     0 },
   { XO_OPCODE(31,75,0,1),  XO_MASK,  {O_rD, O_rA, O_rB, O_Rc, 0},
-    0,               "mulhw.",       0 },
-  { X_OPCODE(31,83,0),     X_MASK,   {O_rD, 0},
-    0,               "mfmsr",        0 },
-  { X_OPCODE(31,86,0),     X_MASK,   {O_rA, O_rB, 0},
-    0,               "dcbf",         H_RA0_IS_0 },
-  { X_OPCODE(31,87,0),     X_MASK,   {O_rD, O_rA, O_rB, 0},
-    0,               "lbzx",         H_RA0_IS_0 },
+    0,		     "mulhw.",	     0 },
+  { X_OPCODE(31,83,0),	   X_MASK,   {O_rD, 0},
+    0,		     "mfmsr",	     0 },
+  { X_OPCODE(31,86,0),	   X_MASK,   {O_rA, O_rB, 0},
+    0,		     "dcbf",	     H_RA0_IS_0 },
+  { X_OPCODE(31,87,0),	   X_MASK,   {O_rD, O_rA, O_rB, 0},
+    0,		     "lbzx",	     H_RA0_IS_0 },
   { XO_OPCODE(31,104,0,0), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
-    0,               "neg",          0 },
+    0,		     "neg",	     0 },
   { XO_OPCODE(31,104,0,1), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
-    0,               "neg.",         0 },
+    0,		     "neg.",	     0 },
   { X_OPCODE(31,119,0),    X_MASK,   {O_rD, O_rA, O_rB, 0},
-    0,               "lbzux",        0 },
+    0,		     "lbzux",	     0 },
   { X_OPCODE(31,124,0),    X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
-    0,               "nor",          0 },
+    0,		     "nor",	     0 },
   { X_OPCODE(31,124,1),    X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
-    0,               "nor.",         0 },
+    0,		     "nor.",	     0 },
   { XO_OPCODE(31,136,0,0), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
-    0,               "subfe",        0 },
+    0,		     "subfe",	     0 },
   { XO_OPCODE(31,136,0,1), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
-    0,               "subfe.",       0 },
+    0,		     "subfe.",	     0 },
   { XO_OPCODE(31,138,0,0), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
-    0,               "adde",         0 },
+    0,		     "adde",	     0 },
   { XO_OPCODE(31,138,0,1), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
-    0,               "adde.",        0 },
+    0,		     "adde.",	     0 },
   { XFX_OPCODE(31,144,0),  XFX_MASK, {O_CRM, O_rS, 0},
-    0,               "mtcrf",        0 },
+    0,		     "mtcrf",	     0 },
   { X_OPCODE(31,146,0),    X_MASK,   {O_rS, 0},
-    0,               "mtmsr",        0 },
+    0,		     "mtmsr",	     0 },
   { X_OPCODE(31,150,1),    X_MASK,   {O_rS, O_rA, O_rB, 0},
-    0,               "stwcx.",       0 },
+    0,		     "stwcx.",	     0 },
   { X_OPCODE(31,151,0),    X_MASK,   {O_rS, O_rA, O_rB, 0},
-    0,               "stwx",         0 },
+    0,		     "stwx",	     0 },
   { X_OPCODE(31,183,0),    X_MASK,   {O_rS, O_rA, O_rB, 0},
-    0,               "stwux",        0 },
+    0,		     "stwux",	     0 },
   { XO_OPCODE(31,200,0,0), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
-    0,               "subfze",       0 },
+    0,		     "subfze",	     0 },
   { XO_OPCODE(31,200,0,1), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
-    0,               "subfze.",      0 },
+    0,		     "subfze.",      0 },
   { XO_OPCODE(31,202,0,0), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
-    0,               "addze",        0 },
+    0,		     "addze",	     0 },
   { XO_OPCODE(31,202,0,1), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
-    0,               "addze.",       0 },
+    0,		     "addze.",	     0 },
   { X_OPCODE(31,210,0),    X_MASK,   {O_SR, O_rS, 0},
-    0,               "mtsr",         0 },
+    0,		     "mtsr",	     0 },
   { X_OPCODE(31,215,0),    X_MASK,   {O_rS, O_rA, O_rB, 0},
-    0,               "stbx",         H_RA0_IS_0 },
+    0,		     "stbx",	     H_RA0_IS_0 },
   { XO_OPCODE(31,232,0,0), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
-    0,               "subfme",       0 },
+    0,		     "subfme",	     0 },
   { XO_OPCODE(31,232,0,1), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
-    0,               "subfme.",      0 },
+    0,		     "subfme.",      0 },
   { XO_OPCODE(31,234,0,0), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
-    0,               "addme",        0 },
+    0,		     "addme",	     0 },
   { XO_OPCODE(31,234,0,1), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
-    0,               "addme.",       0 },
+    0,		     "addme.",	     0 },
   { XO_OPCODE(31,235,0,0), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
-    0,               "mullw",        0 },
+    0,		     "mullw",	     0 },
   { XO_OPCODE(31,235,0,1), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
-    0,               "mullw.",       0 },
+    0,		     "mullw.",	     0 },
   { X_OPCODE(31,242,0),    X_MASK,   {O_rS, O_rB, 0},
-    0,               "mtsrin",       0 },
+    0,		     "mtsrin",	     0 },
   { X_OPCODE(31,246,0),    X_MASK,   {O_rA, O_rB, 0},
-    0,               "dcbtst",       H_RA0_IS_0 },
+    0,		     "dcbtst",	     H_RA0_IS_0 },
   { X_OPCODE(31,247,0),    X_MASK,   {O_rS, O_rA, O_rB, 0},
-    0,               "stbux",        0 },
+    0,		     "stbux",	     0 },
   { XO_OPCODE(31,266,0,0), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
-    0,               "add",          0 },
+    0,		     "add",	     0 },
   { XO_OPCODE(31,266,0,1), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
-    0,               "add.",         0 },
+    0,		     "add.",	     0 },
   { X_OPCODE(31,278,0),    X_MASK,   {O_rA, O_rB, 0},
-    0,               "dcbt",         H_RA0_IS_0 },
+    0,		     "dcbt",	     H_RA0_IS_0 },
   { X_OPCODE(31,279,0),    X_MASK,   {O_rD, O_rA, O_rB, 0},
-    0,               "lhzx",         H_RA0_IS_0 },
+    0,		     "lhzx",	     H_RA0_IS_0 },
   { X_OPCODE(31,284,0),    X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
-    0,               "eqv",          0 },
+    0,		     "eqv",	     0 },
   { X_OPCODE(31,284,1),    X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
-    0,               "eqv.",         0 },
+    0,		     "eqv.",	     0 },
   { X_OPCODE(31,306,0),    X_MASK,   {O_rB, 0},
-    0,               "tlbie",        0 },
+    0,		     "tlbie",	     0 },
   { X_OPCODE(31,310,0),    X_MASK,   {O_rD, O_rA, O_rB, 0},
-    0,               "eciwx",        H_RA0_IS_0 },
+    0,		     "eciwx",	     H_RA0_IS_0 },
   { X_OPCODE(31,311,0),    X_MASK,   {O_rD, O_rA, O_rB, 0},
-    0,               "lhzux",        0 },
+    0,		     "lhzux",	     0 },
   { X_OPCODE(31,316,0),    X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
-    0,               "xor",          0 },
+    0,		     "xor",	     0 },
   { X_OPCODE(31,316,1),    X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
-    0,               "xor.",         0 },
+    0,		     "xor.",	     0 },
   { XFX_OPCODE(31,339,0),  XFX_MASK, {O_rD, O_spr, 0},
-    0,               "mfspr",        0 },
+    0,		     "mfspr",	     0 },
   { X_OPCODE(31,343,0),    X_MASK,   {O_rD, O_rA, O_rB, 0},
-    0,               "lhax",         H_RA0_IS_0 },
+    0,		     "lhax",	     H_RA0_IS_0 },
   { X_OPCODE(31,370,0),    X_MASK,   {0},
-    0,               "tlbia",        0 },
+    0,		     "tlbia",	     0 },
   { XFX_OPCODE(31,371,0),  XFX_MASK, {O_rD, O_tbr, 0},
-    0,               "mftb",         0 },
+    0,		     "mftb",	     0 },
   { X_OPCODE(31,375,0),    X_MASK,   {O_rD, O_rA, O_rB, 0},
-    0,               "lhaux",        0 },
+    0,		     "lhaux",	     0 },
   { X_OPCODE(31,407,0),    X_MASK,   {O_rS, O_rA, O_rB, 0},
-    0,               "sthx",         H_RA0_IS_0 },
+    0,		     "sthx",	     H_RA0_IS_0 },
   { X_OPCODE(31,412,0),    X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
-    0,               "orc",          0 },
+    0,		     "orc",	     0 },
   { X_OPCODE(31,412,1),    X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
-    0,               "orc.",         0 },
+    0,		     "orc.",	     0 },
   { X_OPCODE(31,438,0),    X_MASK,   {O_rS, O_rA, O_rB, 0},
-    0,               "ecowx",        H_RA0_IS_0 },
+    0,		     "ecowx",	     H_RA0_IS_0 },
   { X_OPCODE(31,439,0),    X_MASK,   {O_rS, O_rA, O_rB, 0},
-    0,               "sthux",        0 },
+    0,		     "sthux",	     0 },
   { X_OPCODE(31,444,0),    X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
-    0,               "or",           0 },
+    0,		     "or",	     0 },
   { X_OPCODE(31,444,1),    X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
-    0,               "or.",          0 },
+    0,		     "or.",	     0 },
   { XO_OPCODE(31,459,0,0), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
-    0,               "divwu",        0 },
+    0,		     "divwu",	     0 },
   { XO_OPCODE(31,459,0,1), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
-    0,               "divwu.",       0 },
+    0,		     "divwu.",	     0 },
   { XFX_OPCODE(31,467,0),  XFX_MASK, {O_spr, O_rS, 0},
-    0,               "mtspr",        0 },
+    0,		     "mtspr",	     0 },
   { X_OPCODE(31,470,0),    X_MASK,   {O_rA, O_rB, 0},
-    0,               "dcbi",         H_RA0_IS_0 },
+    0,		     "dcbi",	     H_RA0_IS_0 },
   { X_OPCODE(31,476,0),    X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
-    0,               "nand",         0 },
+    0,		     "nand",	     0 },
   { X_OPCODE(31,476,1),    X_MASK,   {O_rA, O_rS, O_rB, O_Rc,0},
-    0,               "nand.",        0 },
+    0,		     "nand.",	     0 },
   { XO_OPCODE(31,491,0,0), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
-    0,               "divw",         0 },
+    0,		     "divw",	     0 },
   { XO_OPCODE(31,491,0,1), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
-    0,               "divw.",        0 },
+    0,		     "divw.",	     0 },
   { X_OPCODE(31,512,0),    X_MASK,   {O_crfD, 0},
-    0,               "mcrxr",        0 },
+    0,		     "mcrxr",	     0 },
   { XO_OPCODE(31,8,1,0),   XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
-    0,               "subfco",       0 },
+    0,		     "subfco",	     0 },
   { XO_OPCODE(31,8,1,1),   XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
-    0,               "subfco.",      0 },
+    0,		     "subfco.",      0 },
   { XO_OPCODE(31,10,1,0),  XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
-    0,               "addco",        0 },
+    0,		     "addco",	     0 },
   { XO_OPCODE(31,10,1,1),  XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
-    0,               "addco.",       0 },
+    0,		     "addco.",	     0 },
   { X_OPCODE(31,533,0),    X_MASK,   {O_rD, O_rA, O_rB, 0},
-    0,               "lswx",         H_RA0_IS_0 },
+    0,		     "lswx",	     H_RA0_IS_0 },
   { X_OPCODE(31,534,0),    X_MASK,   {O_rD, O_rA, O_rB, 0},
-    0,               "lwbrx",        H_RA0_IS_0 },
+    0,		     "lwbrx",	     H_RA0_IS_0 },
   { X_OPCODE(31,536,0),    X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
-    0,               "srw",          0 },
+    0,		     "srw",	     0 },
   { X_OPCODE(31,536,1),    X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
-    0,               "srw.",         0 },
+    0,		     "srw.",	     0 },
   { XO_OPCODE(31,40,1,0),  XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
-    0,               "subfo",        0 },
+    0,		     "subfo",	     0 },
   { XO_OPCODE(31,40,1,1),  XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
-    0,               "subfo.",       0 },
+    0,		     "subfo.",	     0 },
   { X_OPCODE(31,566,0),    X_MASK,   {0},
-    0,               "tlbsync",      0 },
+    0,		     "tlbsync",      0 },
   { X_OPCODE(31,595,0),    X_MASK,   {O_rD, O_SR, 0},
-    0,               "mfsr",         0 },
+    0,		     "mfsr",	     0 },
   { X_OPCODE(31,597,0),    X_MASK,   {O_rD, O_rA, O_NB, 0},
-    0,               "lswi",         H_RA0_IS_0 },
+    0,		     "lswi",	     H_RA0_IS_0 },
   { X_OPCODE(31,598,0),    X_MASK,   {0},
-    0,               "sync",         0 },
+    0,		     "sync",	     0 },
   { XO_OPCODE(31,104,1,0), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
-    0,               "nego",         0 },
+    0,		     "nego",	     0 },
   { XO_OPCODE(31,104,1,1), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
-    0,               "nego.",        0 },
+    0,		     "nego.",	     0 },
   { XO_OPCODE(31,136,1,0), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
-    0,               "subfeo",       0 },
+    0,		     "subfeo",	     0 },
   { XO_OPCODE(31,136,1,1), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
-    0,               "subfeo.",      0 },
+    0,		     "subfeo.",      0 },
   { XO_OPCODE(31,138,1,0), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
-    0,               "addeo",        0 },
+    0,		     "addeo",	     0 },
   { XO_OPCODE(31,138,1,1), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
-    0,               "addeo.",       0 },
+    0,		     "addeo.",	     0 },
   { X_OPCODE(31,659,0),    X_MASK,   {O_rD, O_rB, 0},
-    0,               "mfsrin",       0 },
+    0,		     "mfsrin",	     0 },
   { X_OPCODE(31,661,0),    X_MASK,   {O_rS, O_rA, O_rB, 0},
-    0,               "stswx",        H_RA0_IS_0 },
+    0,		     "stswx",	     H_RA0_IS_0 },
   { X_OPCODE(31,662,0),    X_MASK,   {O_rS, O_rA, O_rB, 0},
-    0,               "stwbrx",       H_RA0_IS_0 },
+    0,		     "stwbrx",	     H_RA0_IS_0 },
   { XO_OPCODE(31,200,1,0), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
-    0,               "subfzeo",      0 },
+    0,		     "subfzeo",      0 },
   { XO_OPCODE(31,200,1,1), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
-    0,               "subfzeo.",     0 },
+    0,		     "subfzeo.",     0 },
   { XO_OPCODE(31,202,1,0), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
-    0,               "addzeo",       0 },
+    0,		     "addzeo",	     0 },
   { XO_OPCODE(31,202,1,1), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
-    0,               "addzeo.",      0 },
+    0,		     "addzeo.",      0 },
   { X_OPCODE(31,725,0),    X_MASK,   {O_rS, O_rA, O_NB, 0},
-    0,               "stswi",        H_RA0_IS_0 },
+    0,		     "stswi",	     H_RA0_IS_0 },
   { XO_OPCODE(31,232,1,0), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
-    0,               "subfmeo",      0 },
+    0,		     "subfmeo",      0 },
   { XO_OPCODE(31,232,1,1), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
-    0,               "subfmeo.",     0 },
+    0,		     "subfmeo.",     0 },
   { XO_OPCODE(31,234,1,0), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
-    0,               "addmeo",       0 },
+    0,		     "addmeo",	     0 },
   { XO_OPCODE(31,234,1,1), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
-    0,               "addmeo.",      0 },
+    0,		     "addmeo.",      0 },
   { XO_OPCODE(31,235,1,0), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
-    0,               "mullwo",       0 },
+    0,		     "mullwo",	     0 },
   { XO_OPCODE(31,235,1,1), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
-    0,               "mullwo.",      0 },
+    0,		     "mullwo.",      0 },
   { XO_OPCODE(31,266,1,0), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
-    0,               "addo",         0 },
+    0,		     "addo",	     0 },
   { XO_OPCODE(31,266,1,1), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
-    0,               "addo.",        0 },
+    0,		     "addo.",	     0 },
   { X_OPCODE(31,790,0),    X_MASK,   {O_rD, O_rA, O_rB, 0},
-    0,               "lhbrx",        H_RA0_IS_0 },
+    0,		     "lhbrx",	     H_RA0_IS_0 },
   { X_OPCODE(31,792,0),    X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
-    0,               "sraw",         0 },
+    0,		     "sraw",	     0 },
   { X_OPCODE(31,792,1),    X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
-    0,               "sraw.",        0 },
+    0,		     "sraw.",	     0 },
   { X_OPCODE(31,824,0),    X_MASK,   {O_rA, O_rS, O_SH, O_Rc, 0},
-    0,               "srawi",        0 },
+    0,		     "srawi",	     0 },
   { X_OPCODE(31,824,1),    X_MASK,   {O_rA, O_rS, O_SH, O_Rc, 0},
-    0,               "srawi.",       0 },
+    0,		     "srawi.",	     0 },
   { X_OPCODE(31,854,0),    X_MASK,   {0},
-    0,               "eieio",        0 },
+    0,		     "eieio",	     0 },
   { X_OPCODE(31,918,0),    X_MASK,   {O_rS, O_rA, O_rB, 0},
-    0,               "sthbrx",       H_RA0_IS_0 },
+    0,		     "sthbrx",	     H_RA0_IS_0 },
   { X_OPCODE(31,922,0),    X_MASK,   {O_rA, O_rS, O_Rc, 0},
-    0,               "extsh",        0 },
+    0,		     "extsh",	     0 },
   { X_OPCODE(31,922,1),    X_MASK,   {O_rA, O_rS, O_Rc, 0},
-    0,               "extsh.",       0 },
+    0,		     "extsh.",	     0 },
   { X_OPCODE(31,954,0),    X_MASK,   {O_rA, O_rS, O_Rc, 0},
-    0,               "extsb",        0 },
+    0,		     "extsb",	     0 },
   { X_OPCODE(31,954,1),    X_MASK,   {O_rA, O_rS, O_Rc, 0},
-    0,               "extsb.",       0 },
+    0,		     "extsb.",	     0 },
   { XO_OPCODE(31,459,1,0), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
-    0,               "divwuo",       0 },
+    0,		     "divwuo",	     0 },
   { XO_OPCODE(31,459,1,1), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
-    0,               "divwuo.",      0 },
+    0,		     "divwuo.",      0 },
   { X_OPCODE(31,978,0),    X_MASK,   {O_rB, 0},
-    0,               "tlbld",        0 },
+    0,		     "tlbld",	     0 },
   { X_OPCODE(31,982,0),    X_MASK,   {O_rA, O_rB, 0},
-    0,               "icbi",         H_RA0_IS_0 },
+    0,		     "icbi",	     H_RA0_IS_0 },
   { XO_OPCODE(31,491,1,0), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
-    0,               "divwo",        0 },
+    0,		     "divwo",	     0 },
   { XO_OPCODE(31,491,1,1), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
-    0,               "divwo.",       0 },
+    0,		     "divwo.",	     0 },
   { X_OPCODE(31,1010,0),   X_MASK,   {O_rB, 0},
-    0,               "tlbli",        0 },
+    0,		     "tlbli",	     0 },
   { X_OPCODE(31,1014,0),   X_MASK,   {O_rA, O_rB, 0},
-    0,               "dcbz",         H_RA0_IS_0 },
-  { D_OPCODE(32),          D_MASK,   {O_rD, O_d, O_rA, 0},
-    0,               "lwz",          H_RA0_IS_0 },
-  { D_OPCODE(33),          D_MASK,   {O_rD, O_d, O_rA, 0},
-    0,               "lwzu",         0 },
-  { D_OPCODE(34),          D_MASK,   {O_rD, O_d, O_rA, 0},
-    0,               "lbz",          H_RA0_IS_0 },
-  { D_OPCODE(35),          D_MASK,   {O_rD, O_d, O_rA, 0},
-    0,               "lbzu",         0 },
-  { D_OPCODE(36),          D_MASK,   {O_rS, O_d, O_rA, 0},
-    0,               "stw",          H_RA0_IS_0 },
-  { D_OPCODE(37),          D_MASK,   {O_rS, O_d, O_rA, 0},
-    0,               "stwu",         0 },
-  { D_OPCODE(38),          D_MASK,   {O_rS, O_d, O_rA, 0},
-    0,               "stb",          H_RA0_IS_0 },
-  { D_OPCODE(39),          D_MASK,   {O_rS, O_d, O_rA, 0},
-    0,               "stbu",         0 },
-  { D_OPCODE(40),          D_MASK,   {O_rD, O_d, O_rA, 0},
-    0,               "lhz",          H_RA0_IS_0 },
-  { D_OPCODE(41),          D_MASK,   {O_rD, O_d, O_rA, 0},
-    0,               "lhzu",         0 },
-  { D_OPCODE(42),          D_MASK,   {O_rD, O_d, O_rA, 0},
-    0,               "lha",          H_RA0_IS_0 },
-  { D_OPCODE(43),          D_MASK,   {O_rD, O_d, O_rA, 0},
-    0,               "lhau",         0 },
-  { D_OPCODE(44),          D_MASK,   {O_rS, O_d, O_rA, 0},
-    0,               "sth",          H_RA0_IS_0 },
-  { D_OPCODE(45),          D_MASK,   {O_rS, O_d, O_rA, 0},
-    0,               "sthu",         0 },
-  { D_OPCODE(46),          D_MASK,   {O_rD, O_d, O_rA, 0},
-    0,               "lmw",          H_RA0_IS_0 },
-  { D_OPCODE(47),          D_MASK,   {O_rS, O_d, O_rA, 0},
-    0,               "stmw",         H_RA0_IS_0 },
+    0,		     "dcbz",	     H_RA0_IS_0 },
+  { D_OPCODE(32),	   D_MASK,   {O_rD, O_d, O_rA, 0},
+    0,		     "lwz",	     H_RA0_IS_0 },
+  { D_OPCODE(33),	   D_MASK,   {O_rD, O_d, O_rA, 0},
+    0,		     "lwzu",	     0 },
+  { D_OPCODE(34),	   D_MASK,   {O_rD, O_d, O_rA, 0},
+    0,		     "lbz",	     H_RA0_IS_0 },
+  { D_OPCODE(35),	   D_MASK,   {O_rD, O_d, O_rA, 0},
+    0,		     "lbzu",	     0 },
+  { D_OPCODE(36),	   D_MASK,   {O_rS, O_d, O_rA, 0},
+    0,		     "stw",	     H_RA0_IS_0 },
+  { D_OPCODE(37),	   D_MASK,   {O_rS, O_d, O_rA, 0},
+    0,		     "stwu",	     0 },
+  { D_OPCODE(38),	   D_MASK,   {O_rS, O_d, O_rA, 0},
+    0,		     "stb",	     H_RA0_IS_0 },
+  { D_OPCODE(39),	   D_MASK,   {O_rS, O_d, O_rA, 0},
+    0,		     "stbu",	     0 },
+  { D_OPCODE(40),	   D_MASK,   {O_rD, O_d, O_rA, 0},
+    0,		     "lhz",	     H_RA0_IS_0 },
+  { D_OPCODE(41),	   D_MASK,   {O_rD, O_d, O_rA, 0},
+    0,		     "lhzu",	     0 },
+  { D_OPCODE(42),	   D_MASK,   {O_rD, O_d, O_rA, 0},
+    0,		     "lha",	     H_RA0_IS_0 },
+  { D_OPCODE(43),	   D_MASK,   {O_rD, O_d, O_rA, 0},
+    0,		     "lhau",	     0 },
+  { D_OPCODE(44),	   D_MASK,   {O_rS, O_d, O_rA, 0},
+    0,		     "sth",	     H_RA0_IS_0 },
+  { D_OPCODE(45),	   D_MASK,   {O_rS, O_d, O_rA, 0},
+    0,		     "sthu",	     0 },
+  { D_OPCODE(46),	   D_MASK,   {O_rD, O_d, O_rA, 0},
+    0,		     "lmw",	     H_RA0_IS_0 },
+  { D_OPCODE(47),	   D_MASK,   {O_rS, O_d, O_rA, 0},
+    0,		     "stmw",	     H_RA0_IS_0 },
 };
 
 const unsigned int n_opcodes = sizeof(opcodes) / sizeof(opcodes[0]);
diff --git a/include/clps7111.h b/include/clps7111.h
index d122d847ad..baf600773b 100644
--- a/include/clps7111.h
+++ b/include/clps7111.h
@@ -231,7 +231,7 @@
 #define IO_RTCDR	IO_WORD(RTCDR)
 #define IO_RTCMR	IO_WORD(RTCMR)
 #define IO_PMPCON	IO_WORD(PMPCON)
-#define IO_CODR 	IO_BYTE(CODR)
+#define IO_CODR		IO_BYTE(CODR)
 #define IO_UARTDR	IO_WORD(UARTDR)
 #define IO_UBRLCR	IO_WORD(UBRLCR)
 #define IO_SYNCIO	IO_WORD(SYNCIO)
diff --git a/include/command.h b/include/command.h
index 0597c10daf..c3ef51d8c4 100644
--- a/include/command.h
+++ b/include/command.h
@@ -74,7 +74,7 @@ extern int cmd_auto_complete(const char *const prompt, char *buf, int *np, int *
  * void function (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
  */
 
-typedef	void 	command_t (cmd_tbl_t *, int, int, char *[]);
+typedef	void	command_t (cmd_tbl_t *, int, int, char *[]);
 
 #endif	/* __ASSEMBLY__ */
 
diff --git a/include/commproc.h b/include/commproc.h
index 32a3e1c82a..0a4e817fa6 100644
--- a/include/commproc.h
+++ b/include/commproc.h
@@ -786,19 +786,19 @@ typedef struct scc_enet {
 #undef	SCC_ENET
 #define	FEC_ENET
 
-#define PD_MII_TXD1	((ushort)0x1000)	/* PD  3 	*/
-#define PD_MII_TXD2	((ushort)0x0800)	/* PD  4 	*/
-#define PD_MII_TXD3	((ushort)0x0400)	/* PD  5 	*/
-#define PD_MII_RX_DV	((ushort)0x0200)	/* PD  6 	*/
-#define PD_MII_RX_ERR	((ushort)0x0100)	/* PD  7 	*/
-#define PD_MII_RX_CLK	((ushort)0x0080)	/* PD  8 	*/
-#define PD_MII_TXD0	((ushort)0x0040)	/* PD  9 	*/
-#define PD_MII_RXD0	((ushort)0x0020)	/* PD 10 	*/
-#define PD_MII_TX_ERR	((ushort)0x0010)	/* PD 11 	*/
-#define PD_MII_MDC	((ushort)0x0008)	/* PD 12 	*/
-#define PD_MII_RXD1	((ushort)0x0004)	/* PD 13 	*/
-#define PD_MII_RXD2	((ushort)0x0002)	/* PD 14 	*/
-#define PD_MII_RXD3	((ushort)0x0001)	/* PD 15 	*/
+#define PD_MII_TXD1	((ushort)0x1000)	/* PD  3	*/
+#define PD_MII_TXD2	((ushort)0x0800)	/* PD  4	*/
+#define PD_MII_TXD3	((ushort)0x0400)	/* PD  5	*/
+#define PD_MII_RX_DV	((ushort)0x0200)	/* PD  6	*/
+#define PD_MII_RX_ERR	((ushort)0x0100)	/* PD  7	*/
+#define PD_MII_RX_CLK	((ushort)0x0080)	/* PD  8	*/
+#define PD_MII_TXD0	((ushort)0x0040)	/* PD  9	*/
+#define PD_MII_RXD0	((ushort)0x0020)	/* PD 10	*/
+#define PD_MII_TX_ERR	((ushort)0x0010)	/* PD 11	*/
+#define PD_MII_MDC	((ushort)0x0008)	/* PD 12	*/
+#define PD_MII_RXD1	((ushort)0x0004)	/* PD 13	*/
+#define PD_MII_RXD2	((ushort)0x0002)	/* PD 14	*/
+#define PD_MII_RXD3	((ushort)0x0001)	/* PD 15	*/
 #define PD_MII_MASK	((ushort)0x1FFF)	/* PD 3-15	*/
 #endif	/* CONFIG_GEN860T */
 
diff --git a/include/config_cmd_all.h b/include/config_cmd_all.h
index d1b5ffb897..c2bb094e2a 100644
--- a/include/config_cmd_all.h
+++ b/include/config_cmd_all.h
@@ -16,13 +16,13 @@
 #define CONFIG_CMD_AMBAPP	/* AMBA Plug & Play Bus print utility */
 #define CONFIG_CMD_ASKENV	/* ask for env variable		*/
 #define CONFIG_CMD_AUTOSCRIPT	/* Autoscript Support		*/
-#define CONFIG_CMD_BDI	       	/* bdinfo			*/
+#define CONFIG_CMD_BDI		/* bdinfo			*/
 #define CONFIG_CMD_BEDBUG	/* Include BedBug Debugger	*/
 #define CONFIG_CMD_BMP		/* BMP support			*/
 #define CONFIG_CMD_BOOTD	/* bootd			*/
 #define CONFIG_CMD_BSP		/* Board Specific functions	*/
 #define CONFIG_CMD_CACHE	/* icache, dcache		*/
-#define CONFIG_CMD_CDP		/* Cisco Discovery Protocol 	*/
+#define CONFIG_CMD_CDP		/* Cisco Discovery Protocol	*/
 #define CONFIG_CMD_CONSOLE	/* coninfo			*/
 #define CONFIG_CMD_DATE		/* support for RTC, date/time...*/
 #define CONFIG_CMD_DHCP		/* DHCP Support			*/
@@ -71,7 +71,7 @@
 #define CONFIG_CMD_SAVES	/* save S record dump		*/
 #define CONFIG_CMD_SCSI		/* SCSI Support			*/
 #define CONFIG_CMD_SDRAM	/* SDRAM DIMM SPD info printout */
-#define CONFIG_CMD_SETEXPR	/* setexpr support 		*/
+#define CONFIG_CMD_SETEXPR	/* setexpr support		*/
 #define CONFIG_CMD_SETGETDCR	/* DCR support on 4xx		*/
 #define CONFIG_CMD_SNTP		/* SNTP support			*/
 #define CONFIG_CMD_SPI		/* SPI utility			*/
diff --git a/include/config_cmd_default.h b/include/config_cmd_default.h
index f61cfc9368..b556706c73 100644
--- a/include/config_cmd_default.h
+++ b/include/config_cmd_default.h
@@ -17,7 +17,7 @@
  */
 
 #define CONFIG_CMD_AUTOSCRIPT	/* Autoscript Support		*/
-#define CONFIG_CMD_BDI	       	/* bdinfo			*/
+#define CONFIG_CMD_BDI		/* bdinfo			*/
 #define CONFIG_CMD_BOOTD	/* bootd			*/
 #define CONFIG_CMD_CONSOLE	/* coninfo			*/
 #define CONFIG_CMD_ECHO		/* echo arguments		*/
diff --git a/include/configs/A3000.h b/include/configs/A3000.h
index 0a9a1ff90c..dba1bf727d 100644
--- a/include/configs/A3000.h
+++ b/include/configs/A3000.h
@@ -87,7 +87,7 @@
  *-----------------------------------------------------------------------
  */
 #define CONFIG_HARD_I2C		1		/* To enable I2C support	*/
-#undef  CONFIG_SOFT_I2C				/* I2C bit-banged		*/
+#undef	CONFIG_SOFT_I2C				/* I2C bit-banged		*/
 #define CFG_I2C_SPEED		400000		/* I2C speed and slave address	*/
 #define CFG_I2C_SLAVE		0x7F
 
@@ -95,9 +95,9 @@
  * PCI stuff
  *-----------------------------------------------------------------------
  */
-#define CONFIG_PCI      		/* include pci support          */
-#undef CONFIG_PCI_PNP
-#define CONFIG_PCI_SCAN_SHOW    /* print pci devices @ startup  */
+#define CONFIG_PCI			/* include pci support		*/
+#undef	CONFIG_PCI_PNP
+#define CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/
 
 #define CONFIG_NET_MULTI		/* Multi ethernet cards support */
 
@@ -120,11 +120,11 @@
  * (Set up by the startup code)
  * Please note that CFG_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE	    0x00000000
+#define CFG_SDRAM_BASE			0x00000000
 
-#define CFG_FLASH_BASE0_PRELIM      0xFF000000      /* FLASH bank on RCS#0 */
-#define CFG_FLASH_BASE1_PRELIM      0xFF000000      /* FLASH bank on RCS#1 */
-#define CFG_FLASH_BASE  			CFG_FLASH_BASE0_PRELIM
+#define CFG_FLASH_BASE0_PRELIM		0xFF000000	/* FLASH bank on RCS#0 */
+#define CFG_FLASH_BASE1_PRELIM		0xFF000000	/* FLASH bank on RCS#1 */
+#define CFG_FLASH_BASE			CFG_FLASH_BASE0_PRELIM
 #define CFG_FLASH_BANKS			{ CFG_FLASH_BASE0_PRELIM }
 
 /* even though FLASHP_BASE is FF800000, with 4MB is RCS0, the
@@ -170,7 +170,7 @@
  * Definitions for initial stack pointer and data area
  */
 
-/* #define CFG_MONITOR_BASE        TEXT_BASE */
+/* #define CFG_MONITOR_BASE	   TEXT_BASE */
 /*#define CFG_GBL_DATA_SIZE    256*/
 #define CFG_GBL_DATA_SIZE      128
 #define CFG_INIT_RAM_ADDR     0x40000000
@@ -192,7 +192,7 @@
 	 */
 #define CFG_ROMNAL	    7
 #define CFG_ROMFAL	    11
-#define CFG_DBUS_SIZE       0x3
+#define CFG_DBUS_SIZE	    0x3
 
 	/* Bit-field values for MCCR2.
 	 */
@@ -218,7 +218,7 @@
 #define CFG_EXTROM	    1
 #define CFG_REGDIMM	    0
 
-#define CFG_PGMAX           0x32 /* how long the 8240 reatins the currently accessed page in memory FIXME: was 0x32*/
+#define CFG_PGMAX	    0x32 /* how long the 8240 reatins the currently accessed page in memory FIXME: was 0x32*/
 
 #define CFG_SDRAM_DSCD	0x20	/* SDRAM data in sample clock delay - note bottom 3 bits MUST be 0 */
 
diff --git a/include/configs/ADNPESC1.h b/include/configs/ADNPESC1.h
index c45c39554e..01ee72b8bc 100644
--- a/include/configs/ADNPESC1.h
+++ b/include/configs/ADNPESC1.h
@@ -81,9 +81,9 @@
  * appropriately -- this is very important if you plan to move your
  * memory to another place as configured at this time !!!).
  *
- * 	-The heap is placed below the monitor.
- * 	-Global data is placed below the heap.
- * 	-The stack is placed below global data (&grows down).
+ *	-The heap is placed below the monitor.
+ *	-Global data is placed below the heap.
+ *	-The stack is placed below global data (&grows down).
  *----------------------------------------------------------------------*/
 #define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256k		*/
 #define CFG_GBL_DATA_SIZE	128		/* Global data size rsvd*/
diff --git a/include/configs/ADNPESC1_base_32.h b/include/configs/ADNPESC1_base_32.h
index 55210ebd3a..c8428b4e79 100644
--- a/include/configs/ADNPESC1_base_32.h
+++ b/include/configs/ADNPESC1_base_32.h
@@ -370,10 +370,10 @@
 #define	CFG_NIOS_CPU_IDE_NUMS	2		/* number of IDE contr.	*/
 
 #define	CFG_NIOS_CPU_IDE0	0x00001000	/* IDE0		addr	*/
-#define	CFG_NIOS_CPU_IDE0_IRQ	36		/* 		IRQ	*/
+#define	CFG_NIOS_CPU_IDE0_IRQ	36		/*		IRQ	*/
 
 #define	CFG_NIOS_CPU_IDE1	0x00001020	/* IDE1		addr	*/
-#define	CFG_NIOS_CPU_IDE1_IRQ	37		/* 		IRQ	*/
+#define	CFG_NIOS_CPU_IDE1_IRQ	37		/*		IRQ	*/
 
 /* memory accessibility */
 #undef	CFG_NIOS_CPU_SRAM_BASE			/* board SRAM	addr	*/
diff --git a/include/configs/AMX860.h b/include/configs/AMX860.h
index 6f64038073..035ebc6935 100644
--- a/include/configs/AMX860.h
+++ b/include/configs/AMX860.h
@@ -115,7 +115,7 @@
 #define CFG_MEMTEST_START	0x0100000	/* memtest works on	*/
 #define CFG_MEMTEST_END		0x0200000	/* 1 ... 4 MB in DRAM	*/
 
-#define CFG_LOAD_ADDR	 	0x00100000
+#define CFG_LOAD_ADDR		0x00100000
 
 #define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
 
diff --git a/include/configs/APC405.h b/include/configs/APC405.h
index 8ad33f11d5..02f0c76e07 100644
--- a/include/configs/APC405.h
+++ b/include/configs/APC405.h
@@ -36,7 +36,7 @@
  */
 #define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
 #define CONFIG_4xx		1	/* ...member of PPC4xx family   */
-#define CONFIG_APCG405		1	/* ...on a APC405 board 	*/
+#define CONFIG_APCG405		1	/* ...on a APC405 board		*/
 
 #define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
 #define CONFIG_BOARD_EARLY_INIT_R 1
diff --git a/include/configs/AR405.h b/include/configs/AR405.h
index 50f09b03f3..06023819f9 100644
--- a/include/configs/AR405.h
+++ b/include/configs/AR405.h
@@ -208,7 +208,7 @@
 #define CFG_ENV_IS_IN_FLASH	1
 #define CFG_ENV_ADDR		0xFFFB0000	/* Address of Environment Sector*/
 #define CFG_ENV_SECT_SIZE	0x10000 /* see README - env sector total size	*/
-#define CFG_ENV_SIZE		0x04000	        /* Size of Environment 	        */
+#define CFG_ENV_SIZE		0x04000	        /* Size of Environment	        */
 
 #define CFG_ENV_ADDR_REDUND     0xFFFA0000
 #define CFG_ENV_SIZE_REDUND	CFG_ENV_SIZE
diff --git a/include/configs/ATUM8548.h b/include/configs/ATUM8548.h
index 0d644da7ae..f05c1d592b 100644
--- a/include/configs/ATUM8548.h
+++ b/include/configs/ATUM8548.h
@@ -55,7 +55,7 @@
 
 #define CONFIG_TSEC_ENET	1	/* tsec ethernet support */
 #define CONFIG_ENV_OVERWRITE
-#define CONFIG_SPD_EEPROM	1 	/* Use SPD EEPROM for DDR setup*/
+#define CONFIG_SPD_EEPROM	1	/* Use SPD EEPROM for DDR setup*/
 #undef CONFIG_DDR_2T_TIMING		/* Sets the 2T timing bit */
 
 #define CONFIG_DDR_ECC			/* only for ECC DDR module */
@@ -84,7 +84,7 @@
 
 #define CONFIG_BOARD_EARLY_INIT_F	1	/* Call board_pre_init */
 
-#define CONFIG_CMD_SDRAM 		1	/* SDRAM DIMM SPD info printout */
+#define CONFIG_CMD_SDRAM		1	/* SDRAM DIMM SPD info printout */
 #define CONFIG_ENABLE_36BIT_PHYS	1
 #undef	CFG_DRAM_TEST
 #define CFG_MEMTEST_START	0x00200000	/* memtest works on */
@@ -276,7 +276,7 @@
 #if !defined(CONFIG_PCI_PNP)
     #define PCI_ENET0_IOADDR	0xe0000000
     #define PCI_ENET0_MEMADDR	0xe0000000
-    #define PCI_IDSEL_NUMBER	0x0c 	/* slot0->3(IDSEL)=12->15 */
+    #define PCI_IDSEL_NUMBER	0x0c	/* slot0->3(IDSEL)=12->15 */
 #endif
 
 #if defined(CONFIG_PCI)
diff --git a/include/configs/Adder.h b/include/configs/Adder.h
index 8a76c264ca..7389c38b9e 100644
--- a/include/configs/Adder.h
+++ b/include/configs/Adder.h
@@ -149,7 +149,7 @@
 
 /* Environment is in flash */
 #define CFG_ENV_IS_IN_FLASH
-#define CFG_ENV_SECT_SIZE	0x10000 	/* We use one complete sector	*/
+#define CFG_ENV_SECT_SIZE	0x10000		/* We use one complete sector	*/
 #define CFG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
 
 #define CONFIG_ENV_OVERWRITE
@@ -191,16 +191,16 @@
 #define CFG_TBSCR		(TBSCR_TBF | TBSCR_TBE)
 
 /* PISCR - Periodic Interrupt Status and Control */
-#define CFG_PISCR       	(PISCR_PS | PISCR_PITF)
+#define CFG_PISCR		(PISCR_PS | PISCR_PITF)
 
 /* PLPRCR - PLL, Low-Power, and Reset Control Register */
-/* #define CFG_PLPRCR      	PLPRCR_TEXPS */
+/* #define CFG_PLPRCR		PLPRCR_TEXPS */
 
 /* SCCR - System Clock and reset Control Register */
-#define SCCR_MASK       	SCCR_EBDF11
+#define SCCR_MASK		SCCR_EBDF11
 #define CFG_SCCR		SCCR_RTSEL
 
-#define CFG_DER         	0
+#define CFG_DER			0
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
diff --git a/include/configs/B2.h b/include/configs/B2.h
index f1411db66c..d6ab1adeb9 100644
--- a/include/configs/B2.h
+++ b/include/configs/B2.h
@@ -37,7 +37,7 @@
 #define CONFIG_ARM7			1	/* This is a ARM7 CPU	*/
 #define CONFIG_B2			1	/* on an B2 Board      */
 #define CONFIG_ARM_THUMB	1	/* this is an ARM7TDMI */
-#undef  CONFIG_ARM7_REVD	 	/* disable ARM720 REV.D Workarounds */
+#undef  CONFIG_ARM7_REVD		/* disable ARM720 REV.D Workarounds */
 
 #define CONFIG_S3C44B0_CLOCK_SPEED	75 /* we have a 75Mhz S3C44B0*/
 
diff --git a/include/configs/CCM.h b/include/configs/CCM.h
index 9f06957d2f..6194c5c6e2 100644
--- a/include/configs/CCM.h
+++ b/include/configs/CCM.h
@@ -137,7 +137,7 @@
 #define	CFG_LOAD_ADDR		0x00100000	/* default load address	*/
 
 /* Ethernet hardware configuration done using port pins */
-#define CFG_PA_ETH_RESET 	0x0200		/* PA  6	*/
+#define CFG_PA_ETH_RESET	0x0200		/* PA  6	*/
 #define CFG_PA_ETH_MDDIS	0x4000		/* PA  1	*/
 #define CFG_PB_ETH_POWERDOWN	0x00000800	/* PB 20	*/
 #define CFG_PB_ETH_CFG1		0x00000400	/* PB 21	*/
diff --git a/include/configs/CPU86.h b/include/configs/CPU86.h
index 9763e64295..10cebc99c2 100644
--- a/include/configs/CPU86.h
+++ b/include/configs/CPU86.h
@@ -115,9 +115,9 @@
 
 #undef	CONFIG_BOOTARGS
 #define CONFIG_BOOTCOMMAND							\
-	"bootp; " 								\
-	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " 	\
-	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " 	\
+	"bootp; "								\
+	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "	\
 	"bootm"
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/CRAYL1.h b/include/configs/CRAYL1.h
index 2356858d8c..604779a691 100644
--- a/include/configs/CRAYL1.h
+++ b/include/configs/CRAYL1.h
@@ -130,16 +130,16 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_PROMPT	"=> "			/* Monitor Command Prompt	*/
+#define CFG_PROMPT	"=> "				/* Monitor Command Prompt	*/
 #define	CFG_CBSIZE	256				/* Console I/O Buffer Size	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_BARGSIZE	CFG_CBSIZE			/* Boot Argument Buffer Size	*/
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
 #define CFG_MAXARGS	16				/* max number of command args	*/
 
 
-#define CFG_LOAD_ADDR   	0x100000/* where to load what we get from TFTP */
+#define CFG_LOAD_ADDR		0x100000	/* where to load what we get from TFTP */
 #define CFG_TFTP_LOADADDR	CFG_LOAD_ADDR
-#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */
+#define CFG_EXTBDINFO		1		/* To use extended board_into (bd_t) */
 #define CFG_DRAM_TEST		1
 
 /*-----------------------------------------------------------------------
@@ -218,7 +218,7 @@
 #else
 #define CFG_OCM_DATA_ADDR	0xF0000000
 #define CFG_OCM_DATA_SIZE	0x1000
-#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR 	/* inside of On Chip SRAM    */
+#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR	/* inside of On Chip SRAM    */
 #define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE	/* End of On Chip SRAM	     */
 #define CFG_GBL_DATA_SIZE	64	/* size in bytes reserved for initial data */
 #define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
diff --git a/include/configs/CU824.h b/include/configs/CU824.h
index 8b50087f40..f36d8dacc0 100644
--- a/include/configs/CU824.h
+++ b/include/configs/CU824.h
@@ -305,7 +305,7 @@
 #define CONFIG_PCI			/* include pci support			*/
 #undef CONFIG_PCI_PNP
 
-#define CONFIG_NET_MULTI		/* Multi ethernet cards support 	*/
+#define CONFIG_NET_MULTI		/* Multi ethernet cards support		*/
 
 #define CONFIG_TULIP
 #define CONFIG_TULIP_USE_IO
diff --git a/include/configs/DK1C20.h b/include/configs/DK1C20.h
index eb78080208..fb06689074 100644
--- a/include/configs/DK1C20.h
+++ b/include/configs/DK1C20.h
@@ -76,9 +76,9 @@
  * a memory resource (so you must make sure TEXT_BASE is chosen
  * appropriately).
  *
- * 	-The heap is placed below the monitor.
- * 	-Global data is placed below the heap.
- * 	-The stack is placed below global data (&grows down).
+ *	-The heap is placed below the monitor.
+ *	-Global data is placed below the heap.
+ *	-The stack is placed below global data (&grows down).
  *----------------------------------------------------------------------*/
 #define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256k		*/
 #define CFG_GBL_DATA_SIZE	128		/* Global data size rsvd*/
diff --git a/include/configs/DK1S10.h b/include/configs/DK1S10.h
index bd360717a7..7a9ef79adc 100644
--- a/include/configs/DK1S10.h
+++ b/include/configs/DK1S10.h
@@ -84,9 +84,9 @@
  * a memory resource (so you must make sure TEXT_BASE is chosen
  * appropriately).
  *
- * 	-The heap is placed below the monitor.
- * 	-Global data is placed below the heap.
- * 	-The stack is placed below global data (&grows down).
+ *	-The heap is placed below the monitor.
+ *	-Global data is placed below the heap.
+ *	-The stack is placed below global data (&grows down).
  *----------------------------------------------------------------------*/
 #define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256k		*/
 #define CFG_GBL_DATA_SIZE	128		/* Global data size rsvd*/
diff --git a/include/configs/DK1S10_mtx_ldk_20.h b/include/configs/DK1S10_mtx_ldk_20.h
index 4eb96290bb..0115699416 100644
--- a/include/configs/DK1S10_mtx_ldk_20.h
+++ b/include/configs/DK1S10_mtx_ldk_20.h
@@ -147,7 +147,7 @@
 /* IDE i/f */
 #define	CFG_NIOS_CPU_IDE_NUMS	1		/* number of IDE contr.	*/
 #define	CFG_NIOS_CPU_IDE0	0x00000900	/* IDE0		addr	*/
-#define	CFG_NIOS_CPU_IDE0_IRQ	25		/* 		IRQ	*/
+#define	CFG_NIOS_CPU_IDE0_IRQ	25		/*		IRQ	*/
 
 /* memory accessibility */
 #undef	CFG_NIOS_CPU_SRAM_BASE			/* board SRAM	addr	*/
diff --git a/include/configs/DU440.h b/include/configs/DU440.h
index d54da9717b..0f5f85c22a 100644
--- a/include/configs/DU440.h
+++ b/include/configs/DU440.h
@@ -375,11 +375,11 @@ int du440_phy_addr(int devnum);
 #define CFG_FLASH		CFG_FLASH_BASE
 
 #define CFG_CPLD_BASE		0xC0000000
-#define CFG_CPLD_RANGE 	        0x00000010
+#define CFG_CPLD_RANGE	        0x00000010
 #define CFG_DUMEM_BASE		0xC0100000
-#define CFG_DUMEM_RANGE 	0x00100000
+#define CFG_DUMEM_RANGE		0x00100000
 #define CFG_DUIO_BASE		0xC0200000
-#define CFG_DUIO_RANGE 	        0x00010000
+#define CFG_DUIO_RANGE	        0x00010000
 
 #define CFG_NAND0_CS		2		/* NAND chip connected to CSx */
 #define CFG_NAND1_CS		3		/* NAND chip connected to CSx */
diff --git a/include/configs/EB+MCF-EV123.h b/include/configs/EB+MCF-EV123.h
index 5ba7585bce..417099e037 100644
--- a/include/configs/EB+MCF-EV123.h
+++ b/include/configs/EB+MCF-EV123.h
@@ -95,7 +95,7 @@
 
 #	define CFG_FEC0_PINMUX		0
 #	define CFG_FEC0_MIIBASE		CFG_FEC0_IOBASE
-#	define MCFFEC_TOUT_LOOP 	50000
+#	define MCFFEC_TOUT_LOOP		50000
 /* If CFG_DISCOVER_PHY is not defined - hardcoded */
 #	ifndef CFG_DISCOVER_PHY
 #		define FECDUPLEX	FULL
@@ -157,7 +157,7 @@
  */
 #define CFG_INIT_RAM_ADDR       0x20000000
 #define CFG_INIT_RAM_END	0x10000		/* End of used area in internal SRAM	*/
-#define CFG_GBL_DATA_SIZE	64      	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_SIZE	64		/* size in bytes reserved for initial data */
 #define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 #define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
 
@@ -219,13 +219,13 @@
 #define CFG_CS0_BASE		CFG_FLASH_BASE
 #define CFG_CS0_SIZE		2*1024*1024
 #define CFG_CS0_WIDTH		16
-#define CFG_CS0_RO 		0
+#define CFG_CS0_RO		0
 #define CFG_CS0_WS		6
 
 #define CFG_CS3_BASE		0xE0000000
 #define CFG_CS3_SIZE		1*1024*1024
 #define CFG_CS3_WIDTH		16
-#define CFG_CS3_RO 		0
+#define CFG_CS3_RO		0
 #define CFG_CS3_WS		6
 
 /*-----------------------------------------------------------------------
@@ -250,7 +250,7 @@
 #define CFG_PEHLPAR		0xC0
 #define CFG_PUAPAR		0x0F		/* UA0..UA3 = Uart 0 +1 */
 #define CFG_DDRUA		0x05
-#define CFG_PJPAR 		0xFF;
+#define CFG_PJPAR		0xFF;
 
 /*-----------------------------------------------------------------------
  * CCM configuration
diff --git a/include/configs/EP88x.h b/include/configs/EP88x.h
index c2ab18a79e..7824b900ad 100644
--- a/include/configs/EP88x.h
+++ b/include/configs/EP88x.h
@@ -144,7 +144,7 @@
 
 /* Environment is in flash */
 #define CFG_ENV_IS_IN_FLASH
-#define CFG_ENV_SECT_SIZE	0x20000 	/* We use one complete sector	*/
+#define CFG_ENV_SECT_SIZE	0x20000		/* We use one complete sector	*/
 #define CFG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
 
 #define CFG_OR0_PRELIM		0xFC000160
@@ -192,13 +192,13 @@
 #define CFG_TBSCR		(TBSCR_TBF | TBSCR_TBE)
 
 /* PISCR - Periodic Interrupt Status and Control */
-#define CFG_PISCR       	PISCR_PS
+#define CFG_PISCR		PISCR_PS
 
 /* SCCR - System Clock and reset Control Register */
-#define SCCR_MASK       	SCCR_EBDF11
+#define SCCR_MASK		SCCR_EBDF11
 #define CFG_SCCR		SCCR_RTSEL
 
-#define CFG_DER         	0
+#define CFG_DER			0
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
diff --git a/include/configs/ERIC.h b/include/configs/ERIC.h
index dc15b0c349..bfdcf6a554 100644
--- a/include/configs/ERIC.h
+++ b/include/configs/ERIC.h
@@ -330,7 +330,7 @@
  * BR0/1 and OR0/1 (FLASH)
  */
 
-#define FLASH_BASE0_PRELIM	0xFF800000	/* FLASH bank #0 8MB 	*/
+#define FLASH_BASE0_PRELIM	0xFF800000	/* FLASH bank #0 8MB	*/
 #define FLASH_BASE1_PRELIM	0		/* FLASH bank #1	*/
 
 
diff --git a/include/configs/ETX094.h b/include/configs/ETX094.h
index ed439b1922..525051fb57 100644
--- a/include/configs/ETX094.h
+++ b/include/configs/ETX094.h
@@ -51,7 +51,7 @@
 #define CONFIG_BOARD_TYPES	1	/* support board types		*/
 
 #define	CONFIG_FLASH_16BIT		/* for board with 16bit wide flash	*/
-#undef	SB_ETX094			/* only for SB-Board with 16MB SDRAM 	*/
+#undef	SB_ETX094			/* only for SB-Board with 16MB SDRAM	*/
 #define	CONFIG_BOOTP_RANDOM_DELAY	/* graceful BOOTP recovery mode		*/
 
 #define CONFIG_ETHADDR 08:00:06:00:00:00
diff --git a/include/configs/EVB64260.h b/include/configs/EVB64260.h
index 1c44a0c6d7..c9d8c271ba 100644
--- a/include/configs/EVB64260.h
+++ b/include/configs/EVB64260.h
@@ -42,7 +42,7 @@
 #define CONFIG_EVB64260		1	/* this is an EVB64260 board	*/
 #define CFG_GT_6426x        GT_64260 /* with a 64260 system controller */
 
-#define CONFIG_BAUDRATE		38400 	/* console baudrate = 38400	*/
+#define CONFIG_BAUDRATE		38400	/* console baudrate = 38400	*/
 
 #undef	CONFIG_ECC			/* enable ECC support */
 /* #define CONFIG_EVB64260_750CX  1 */      /* Support the EVB-64260-750CX Board */
@@ -91,7 +91,7 @@
 
 #undef	CONFIG_BOOTARGS
 #define CONFIG_BOOTCOMMAND						     \
-	"bootp && " 						     \
+	"bootp && "						     \
 	"setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath " \
 	"ip=$ipaddr:$serverip:$gatewayip:" \
 	"$netmask:$hostname:eth0:none; && " \
@@ -412,10 +412,10 @@
 #define CFG_L2
 
 #ifdef CONFIG_750CX
-#define L2_INIT 0
+#define L2_INIT		0
 #else
-#define L2_INIT  	(L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
-			L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
+#define L2_INIT		(L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
+			 L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
 #endif
 
 #define L2_ENABLE	(L2_INIT | L2CR_L2E)
diff --git a/include/configs/EXBITGEN.h b/include/configs/EXBITGEN.h
index 251227c7ff..99d1cf255c 100644
--- a/include/configs/EXBITGEN.h
+++ b/include/configs/EXBITGEN.h
@@ -33,7 +33,7 @@
  * (easy to change)
  */
 
-#define CONFIG_405GP		1	/* This is a PPC405GP CPU     	*/
+#define CONFIG_405GP		1	/* This is a PPC405GP CPU	*/
 #define CONFIG_4xx		1	/* ...member of PPC4xx family   */
 #define CONFIG_EXBITGEN		1	/* on a Exbit Generic board     */
 
diff --git a/include/configs/FADS823.h b/include/configs/FADS823.h
index 86cbe5872a..6f3e6a75b8 100644
--- a/include/configs/FADS823.h
+++ b/include/configs/FADS823.h
@@ -93,10 +93,10 @@
 #define CONFIG_LOADS_ECHO	0	/* Dont echoes received characters */
 #define CONFIG_BOOTARGS		""
 #define CONFIG_BOOTCOMMAND							\
-"bootp ;" 									\
-"setenv bootargs console=tty0 console=ttyS0 " 					\
-"root=/dev/nfs nfsroot=${serverip}:${rootpath} " 				\
-"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:eth0:off ;" 	\
+"bootp ;"									\
+"setenv bootargs console=tty0 console=ttyS0 "					\
+"root=/dev/nfs nfsroot=${serverip}:${rootpath} "				\
+"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:eth0:off ;"	\
 "bootm"
 #else
 #define CONFIG_BOOTDELAY	0	/* autoboot disabled		*/
diff --git a/include/configs/GEN860T.h b/include/configs/GEN860T.h
index c8b5a6d8a5..037b115c13 100644
--- a/include/configs/GEN860T.h
+++ b/include/configs/GEN860T.h
@@ -39,9 +39,9 @@
  * Identify the board
  */
 #if !defined(CONFIG_SC)
-#define CONFIG_IDENT_STRING				" B2"
+#define CONFIG_IDENT_STRING		" B2"
 #else
-#define CONFIG_IDENT_STRING				" SC"
+#define CONFIG_IDENT_STRING		" SC"
 #endif
 
 /*
@@ -50,26 +50,26 @@
  * generated by the DS1337 - and the DS1337 clock can be turned off.
  */
 #if !defined(CONFIG_SC)
-#define	CONFIG_8xx_GCLK_FREQ			66600000
+#define	CONFIG_8xx_GCLK_FREQ		66600000
 #else
-#define	CONFIG_8xx_GCLK_FREQ			48000000
+#define	CONFIG_8xx_GCLK_FREQ		48000000
 #endif
 
 /*
  * The RS-232 console port is on SMC1
  */
 #define	CONFIG_8xx_CONS_SMC1
-#define CONFIG_BAUDRATE					38400
+#define CONFIG_BAUDRATE			38400
 
 /*
  * Set allowable console baud rates
  */
-#define CFG_BAUDRATE_TABLE				{ 9600,		\
-							 		 	  19200,	\
-							 		 	  38400,	\
-									 	  57600,	\
-									 	  115200,	\
-										}
+#define CFG_BAUDRATE_TABLE		{ 9600,		\
+					  19200,	\
+					  38400,	\
+					  57600,	\
+					  115200,	\
+					}
 
 /*
  * Print console information
@@ -148,7 +148,7 @@
 #define CFG_DISCOVER_PHY
 #define CONFIG_MII
 #define CONFIG_MII_INIT			1
-#define CONFIG_PHY_ADDR         		0
+#define CONFIG_PHY_ADDR			0
 
 /*
  * Set default IP stuff just to get bootstrap entries into the
@@ -172,7 +172,7 @@
  * Enable I2C and select the hardware/software driver
  */
 #define CONFIG_HARD_I2C		1				/* CPM based I2C			*/
-#undef	CONFIG_SOFT_I2C        				/* Bit-banged I2C			*/
+#undef	CONFIG_SOFT_I2C						/* Bit-banged I2C			*/
 
 #ifdef CONFIG_HARD_I2C
 #define	CFG_I2C_SPEED		100000			/* clock speed in Hz		*/
@@ -181,7 +181,7 @@
 
 #ifdef CONFIG_SOFT_I2C
 #define PB_SCL				0x00000020		/* PB 26					*/
-#define PB_SDA				0x00000010		/* PB 27 					*/
+#define PB_SDA				0x00000010		/* PB 27					*/
 #define I2C_INIT			(immr->im_cpm.cp_pbdir |=  PB_SCL)
 #define I2C_ACTIVE			(immr->im_cpm.cp_pbdir |=  PB_SDA)
 #define I2C_TRISTATE		(immr->im_cpm.cp_pbdir &= ~PB_SDA)
@@ -388,7 +388,7 @@
  */
 #define CFG_INIT_RAM_ADDR		CFG_IMMR
 #define	CFG_INIT_RAM_END		0x2F00	/* End of used area in DPRAM		*/
-#define	CFG_INIT_DATA_SIZE		64  	/* # bytes reserved for initial data*/
+#define	CFG_INIT_DATA_SIZE		64	/* # bytes reserved for initial data*/
 #define CFG_GBL_DATA_OFFSET		(CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE)
 #define	CFG_INIT_SP_OFFSET		CFG_GBL_DATA_OFFSET
 
@@ -480,18 +480,18 @@
  */
 #if defined(CONFIG_WATCHDOG)
 #define CFG_SYPCR	( SYPCR_SWTC	| \
-					  SYPCR_BMT 	| \
-					  SYPCR_BME 	| \
-					  SYPCR_SWF 	| \
-					  SYPCR_SWE 	| \
+					  SYPCR_BMT	| \
+					  SYPCR_BME	| \
+					  SYPCR_SWF	| \
+					  SYPCR_SWE	| \
 					  SYPCR_SWRI	| \
 					  SYPCR_SWP		  \
 					)
 #else
 #define CFG_SYPCR	( SYPCR_SWTC	| \
-					  SYPCR_BMT 	| \
-					  SYPCR_BME 	| \
-					  SYPCR_SWF 	| \
+					  SYPCR_BMT	| \
+					  SYPCR_BME	| \
+					  SYPCR_SWF	| \
 					  SYPCR_SWP		  \
 					)
 #endif
@@ -557,18 +557,18 @@
 #define SCCR_MASK   SCCR_EBDF11
 
 #if !defined(CONFIG_SC)
-#define CFG_SCCR	( SCCR_TBS			| 	/* timebase = GCLK/2	*/ \
-					  SCCR_COM00   		| 	/* full strength CLKOUT	*/ \
-					  SCCR_DFSYNC00 	| 	/* SYNCLK / 1 (normal)	*/ \
-					  SCCR_DFBRG00		| 	/* BRGCLK / 1 (normal)	*/ \
+#define CFG_SCCR	( SCCR_TBS			|	/* timebase = GCLK/2	*/ \
+					  SCCR_COM00		|	/* full strength CLKOUT	*/ \
+					  SCCR_DFSYNC00	|	/* SYNCLK / 1 (normal)	*/ \
+					  SCCR_DFBRG00		|	/* BRGCLK / 1 (normal)	*/ \
 					  SCCR_DFNL000		| \
 					  SCCR_DFNH000		  \
 					)
 #else
-#define CFG_SCCR	( SCCR_TBS			| 	/* timebase = GCLK/2	*/ \
-					  SCCR_COM00   		| 	/* full strength CLKOUT	*/ \
-					  SCCR_DFSYNC00 	| 	/* SYNCLK / 1 (normal)	*/ \
-					  SCCR_DFBRG00		| 	/* BRGCLK / 1 (normal)	*/ \
+#define CFG_SCCR	( SCCR_TBS			|	/* timebase = GCLK/2	*/ \
+					  SCCR_COM00		|	/* full strength CLKOUT	*/ \
+					  SCCR_DFSYNC00	|	/* SYNCLK / 1 (normal)	*/ \
+					  SCCR_DFBRG00		|	/* BRGCLK / 1 (normal)	*/ \
 					  SCCR_DFNL000		| \
 					  SCCR_DFNH000		| \
 					  SCCR_RTDIV		| \
@@ -614,7 +614,7 @@
 #define CFG_BR0_PRELIM	( (FLASH_BASE0_PRELIM & BR_BA_MSK)	| \
 						  BR_MS_GPCM						| \
 						  BR_PS_8							| \
-						  BR_V 								  \
+						  BR_V								  \
 						)
 
 /*
@@ -626,9 +626,9 @@
 					)
 
 #define CFG_BR1		( (SDRAM_BASE & BR_BA_MSK)	| \
-					  BR_MS_UPMA 				| \
-					  BR_PS_32	 				| \
-					  BR_V 						  \
+					  BR_MS_UPMA				| \
+					  BR_PS_32					| \
+					  BR_V						  \
 					)
 
 /*
@@ -646,9 +646,9 @@
  * MAMR settings for SDRAM
  */
 #define CFG_MAMR_8COL	( (CFG_MAMR_PTA << MAMR_PTA_SHIFT)	| \
-						  MAMR_PTAE	    			| \
+						  MAMR_PTAE				| \
 						  MAMR_AMA_TYPE_1			| \
-						  MAMR_DSA_1_CYCL 			| \
+						  MAMR_DSA_1_CYCL			| \
 						  MAMR_G0CLA_A10			| \
 						  MAMR_RLFA_1X				| \
 						  MAMR_WLFA_1X				| \
@@ -660,7 +660,7 @@
  * 33 MHz bus with TRLX=1, ACS=11, CSNT=1, EBDF=1, SCY=2, EHTR=1,
  * no burst.
  */
-#define CFG_OR2_PRELIM 	( (0xffff0000 & OR_AM_MSK)	| \
+#define CFG_OR2_PRELIM	( (0xffff0000 & OR_AM_MSK)	| \
 						  OR_CSNT_SAM				| \
 						  OR_ACS_DIV2				| \
 						  OR_BI						| \
@@ -685,20 +685,20 @@
  */
 #define CFG_OR3_PRELIM	( (0xfc000000 & OR_AM_MSK)  | \
 						  OR_SCY_15_CLK				| \
-						  OR_BI 					  \
+						  OR_BI					  \
 						)
 
 #define CFG_BR3_PRELIM	( (FPGA_BASE & BR_BA_MSK)	| \
 						  BR_PS_32					| \
 						  BR_MS_GPCM				| \
-						  BR_V		  				  \
+						  BR_V						  \
 						)
 /*
  * CS4* configuration for FPGA SelectMap configuration interface.
  * 33 MHz bus, UPMB, no burst. Do not assert GPLB5 on falling edge
  * of GCLK1_50
  */
-#define CFG_OR4_PRELIM	( (0xffff0000 & OR_AM_MSK)  	| \
+#define CFG_OR4_PRELIM	( (0xffff0000 & OR_AM_MSK)	| \
 						  OR_G5LS						| \
 						  OR_BI							  \
 						)
@@ -706,7 +706,7 @@
 #define CFG_BR4_PRELIM	( (SELECTMAP_BASE & BR_BA_MSK)	| \
 						  BR_PS_8						| \
 						  BR_MS_UPMB					| \
-						  BR_V			  				  \
+						  BR_V							  \
 						)
 
 /*
@@ -728,7 +728,7 @@
 #define CFG_BR5_PRELIM	( (M1553_BASE & BR_BA_MSK)	| \
 						  BR_PS_16					| \
 						  BR_MS_GPCM				| \
-						  BR_V			  			  \
+						  BR_V						  \
 						)
 
 /*
@@ -760,5 +760,3 @@
 #endif
 
 #endif	/* __CONFIG_GEN860T_H */
-
-/* vim: set ts=4 tw=78 ai shiftwidth=4: */
diff --git a/include/configs/GENIETV.h b/include/configs/GENIETV.h
index 3a660edae2..f6d6ae0ce5 100644
--- a/include/configs/GENIETV.h
+++ b/include/configs/GENIETV.h
@@ -80,10 +80,10 @@
 #undef	CONFIG_8xx_CONS_NONE
 #define CONFIG_BAUDRATE		9600
 
-#define MPC8XX_FACT	12 			/* Multiply by 12	*/
-#define MPC8XX_XIN	5000000			/* 4 MHz clock 		*/
+#define MPC8XX_FACT	12			/* Multiply by 12	*/
+#define MPC8XX_XIN	5000000			/* 4 MHz clock		*/
 
-#define MPC8XX_HZ 	((MPC8XX_XIN) * (MPC8XX_FACT))
+#define MPC8XX_HZ	((MPC8XX_XIN) * (MPC8XX_FACT))
 #define CFG_PLPRCR_MF	((MPC8XX_FACT-1) << 20)
 #define CONFIG_8xx_GCLK_FREQ	MPC8XX_HZ	/* Force it - dont measure it */
 
@@ -95,9 +95,9 @@
 #define CONFIG_BOOTARGS		""
 #define CONFIG_BOOTCOMMAND							\
 "bootp; tftp; "									\
-"setenv bootargs console=tty0 console=ttyS0 " 					\
-"root=/dev/nfs nfsroot=${serverip}:${rootpath} " 				\
-"ip=${ipaddr}:${serverip}:${gatewayip}:${subnetmask}:${hostname}:eth0:off ;" 	\
+"setenv bootargs console=tty0 console=ttyS0 "					\
+"root=/dev/nfs nfsroot=${serverip}:${rootpath} "				\
+"ip=${ipaddr}:${serverip}:${gatewayip}:${subnetmask}:${hostname}:eth0:off ;"	\
 "bootm "
 #else
 #define CONFIG_BOOTDELAY	0	/* autoboot disabled		*/
@@ -197,7 +197,7 @@
 #define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
 #define	CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_OFFSET		0x10000	/* Offset of Environment Sector 	*/
+#define CFG_ENV_OFFSET		0x10000	/* Offset of Environment Sector		*/
 #define	CFG_ENV_SIZE		0x10000	/* Total Size of Environment Sector (64k)*/
 
 /* values according to the manual */
@@ -291,15 +291,15 @@
 
 #define FLASH_BASE0_PRELIM	0x02800000	/* FLASH bank #0		*/
 
-#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask 	*/
+#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask		*/
 #define CFG_PRELIM_OR_AM	0xFF800000	/* OR addr mask (512Kb) */
 
 /* FLASH timing */
-#define CFG_OR_TIMING_FLASH 	(OR_CSNT_SAM  | OR_ACS_DIV2 | OR_BI | \
+#define CFG_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_DIV2 | OR_BI | \
 				OR_SCY_15_CLK | OR_TRLX )
 
 /*#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH) */
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) 		/* 0xfff80ff4 */
+#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)		/* 0xfff80ff4 */
 #define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_8)	/* 0x02800401 */
 
 /*
diff --git a/include/configs/GTH.h b/include/configs/GTH.h
index 79f5714e6f..00e09f703c 100644
--- a/include/configs/GTH.h
+++ b/include/configs/GTH.h
@@ -135,7 +135,7 @@
 #define CFG_MEMTEST_END		0x0400000	/* 1 ... 4 MB in DRAM	*/
 
 /* Default location to load data from net */
-#define CFG_LOAD_ADDR	 	0x100000
+#define CFG_LOAD_ADDR		0x100000
 
 #define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
 
@@ -196,7 +196,7 @@
 #define	CFG_ENV_IS_IN_FLASH 1
 #undef CFG_ENV_IS_IN_EEPROM
 #define CFG_ENV_OFFSET		0x000E0000
-#define	CFG_ENV_SIZE		 0x4000 	/* Total Size of Environment Sector	*/
+#define	CFG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
 
 #define CFG_ENV_SECT_SIZE	0x50000	/* see README - env sector total size	*/
 
diff --git a/include/configs/HH405.h b/include/configs/HH405.h
index 18e5b3c288..8ea1ac37d1 100644
--- a/include/configs/HH405.h
+++ b/include/configs/HH405.h
@@ -41,7 +41,7 @@
 
 #define CONFIG_405EP		1	/* This is a PPC405 CPU		*/
 #define CONFIG_4xx		1	/* ...member of PPC4xx family   */
-#define CONFIG_HH405		1	/* ...on a HH405 board 	        */
+#define CONFIG_HH405		1	/* ...on a HH405 board	        */
 
 #define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
 #define CONFIG_MISC_INIT_R      1       /* call misc_init_r()           */
diff --git a/include/configs/IAD210.h b/include/configs/IAD210.h
index 7f3f16dbb1..87827ead1c 100644
--- a/include/configs/IAD210.h
+++ b/include/configs/IAD210.h
@@ -70,15 +70,15 @@
 
 #undef	CONFIG_BOOTARGS
 /* #define CONFIG_BOOTCOMMAND							\
- 	"bootp;" 								\
- 	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " 	\
- 	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" 	\
- 	"bootm"
+	"bootp;"								\
+	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;"	\
+	"bootm"
 */
 
 #define CONFIG_BOOTCOMMAND	\
-	"setenv bootargs root=/dev/nfs" 	\
-	"ip=192.168.28.129:139.10.137.138:192.168.28.1:255.255.255.0:iadlinux002::off; " 	\
+	"setenv bootargs root=/dev/nfs"	\
+	"ip=192.168.28.129:139.10.137.138:192.168.28.1:255.255.255.0:iadlinux002::off; "	\
 
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
@@ -159,7 +159,7 @@
 #define CFG_MEMTEST_START	0x0100000	/* memtest works on	*/
 #define CFG_MEMTEST_END		0x0400000	/* 1 ... 4 MB in DRAM	*/
 
-#define CFG_LOAD_ADDR	 	0x00100000
+#define CFG_LOAD_ADDR		0x00100000
 
 #define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
 
diff --git a/include/configs/ICU862.h b/include/configs/ICU862.h
index 9c88d7c417..f693956d42 100644
--- a/include/configs/ICU862.h
+++ b/include/configs/ICU862.h
@@ -72,9 +72,9 @@
 
 #undef	CONFIG_BOOTARGS
 #define CONFIG_BOOTCOMMAND							\
-	"bootp;" 								\
-	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " 	\
-	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" 	\
+	"bootp;"								\
+	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;"	\
 	"bootm"
 
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
@@ -164,7 +164,7 @@
 #define CFG_MEMTEST_START	0x0100000	/* memtest works on	*/
 #define CFG_MEMTEST_END		0x0400000	/* 1 ... 4 MB in DRAM	*/
 
-#define CFG_LOAD_ADDR	 	0x00100000
+#define CFG_LOAD_ADDR		0x00100000
 
 #define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
 
diff --git a/include/configs/IPHASE4539.h b/include/configs/IPHASE4539.h
index bb2c96ac94..7d564a0957 100644
--- a/include/configs/IPHASE4539.h
+++ b/include/configs/IPHASE4539.h
@@ -274,7 +274,7 @@
  * HID1 has only read-only information - nothing to set.
  */
 #define CFG_HID0_INIT	(HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
- 			 HID0_IFEM|HID0_ABE)
+			 HID0_IFEM|HID0_ABE)
 #define CFG_HID0_FINAL	(HID0_IFEM|HID0_ABE)
 #define CFG_HID2	0
 
diff --git a/include/configs/ISPAN.h b/include/configs/ISPAN.h
index 965b515f0e..760f7cca6e 100644
--- a/include/configs/ISPAN.h
+++ b/include/configs/ISPAN.h
@@ -186,7 +186,7 @@
 
 /* Environment is in flash, there is little space left in Serial EEPROM */
 #define CFG_ENV_IS_IN_FLASH
-#define CFG_ENV_SECT_SIZE	0x10000 	/* We use one complete sector	*/
+#define CFG_ENV_SECT_SIZE	0x10000		/* We use one complete sector	*/
 #define CFG_ENV_SIZE		(CFG_ENV_SECT_SIZE)
 #define CFG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
 #define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
diff --git a/include/configs/IVML24.h b/include/configs/IVML24.h
index 1142f2afac..0ffdfac07c 100644
--- a/include/configs/IVML24.h
+++ b/include/configs/IVML24.h
@@ -205,7 +205,7 @@
 
 # if defined (CONFIG_IVML24_16M)
 #  define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
- 			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 # elif defined (CONFIG_IVML24_32M)
 #  define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 			 SYPCR_SWE  | SYPCR_SWP)
@@ -265,7 +265,7 @@
 /* 0x01800014 */
 #define CFG_SCCR	(SCCR_COM01	| /*SCCR_TBS|*/		\
 			 SCCR_RTDIV	|   SCCR_RTSEL	  |	\
-			 /*SCCR_CRQEN|*/  /*SCCR_PRQEN|*/ 	\
+			 /*SCCR_CRQEN|*/  /*SCCR_PRQEN|*/	\
 			 SCCR_EBDF00	|   SCCR_DFSYNC00 |	\
 			 SCCR_DFBRG00	|   SCCR_DFNL000  |	\
 			 SCCR_DFNH000	|   SCCR_DFLCD101 |	\
@@ -458,8 +458,8 @@
 #if defined (CONFIG_IVML24_16M)
  /* 8 column SDRAM */
 # define CFG_MBMR_8COL	((CFG_MBMR_PTB << MBMR_PTB_SHIFT)  | \
- 			 MBMR_AMB_TYPE_0 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A11 |	\
- 			 MBMR_RLFB_1X	 | MBMR_WLFB_1X	   | MBMR_TLFB_4X)
+			 MBMR_AMB_TYPE_0 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A11 |	\
+			 MBMR_RLFB_1X	 | MBMR_WLFB_1X	   | MBMR_TLFB_4X)
 #elif defined (CONFIG_IVML24_32M)
 /* 128 MBit SDRAM */
 # define CFG_MBMR_8COL	((CFG_MBMR_PTB << MBMR_PTB_SHIFT)  | \
diff --git a/include/configs/IVMS8.h b/include/configs/IVMS8.h
index bd19dad1ff..ea3ffe0a10 100644
--- a/include/configs/IVMS8.h
+++ b/include/configs/IVMS8.h
@@ -200,7 +200,7 @@
 #if defined(CONFIG_WATCHDOG)
 # if defined (CONFIG_IVMS8_16M)
 #   define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
- 			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 #  elif defined (CONFIG_IVMS8_32M)
 #   define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 			 SYPCR_SWE  | SYPCR_SWP)
@@ -259,7 +259,7 @@
 /* 0x01800014 */
 #define CFG_SCCR	(SCCR_COM01	| /*SCCR_TBS|*/		\
 			 SCCR_RTDIV	|   SCCR_RTSEL	  |	\
-			 /*SCCR_CRQEN|*/  /*SCCR_PRQEN|*/ 	\
+			 /*SCCR_CRQEN|*/  /*SCCR_PRQEN|*/	\
 			 SCCR_EBDF00	|   SCCR_DFSYNC00 |	\
 			 SCCR_DFBRG00	|   SCCR_DFNL000  |	\
 			 SCCR_DFNH000	|   SCCR_DFLCD101 |	\
@@ -440,8 +440,8 @@
 #if defined (CONFIG_IVMS8_16M)
  /* 8 column SDRAM */
 # define CFG_MBMR_8COL	((CFG_MBMR_PTB << MBMR_PTB_SHIFT)  | \
- 			 MBMR_AMB_TYPE_0 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A11 |	\
- 			 MBMR_RLFB_1X	 | MBMR_WLFB_1X	   | MBMR_TLFB_4X)
+			 MBMR_AMB_TYPE_0 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A11 |	\
+			 MBMR_RLFB_1X	 | MBMR_WLFB_1X	   | MBMR_TLFB_4X)
 #elif defined (CONFIG_IVMS8_32M)
 /* 128 MBit SDRAM */
 #define CFG_MBMR_8COL	((CFG_MBMR_PTB << MBMR_PTB_SHIFT)  | \
diff --git a/include/configs/IceCube.h b/include/configs/IceCube.h
index 38a022611a..f85cff7abf 100644
--- a/include/configs/IceCube.h
+++ b/include/configs/IceCube.h
@@ -172,9 +172,9 @@
  * IPB Bus clocking configuration.
  */
 #if defined(CONFIG_LITE5200B)
-#define CFG_IPBCLK_EQUALS_XLBCLK 	/* define for 133MHz speed */
+#define CFG_IPBCLK_EQUALS_XLBCLK	/* define for 133MHz speed */
 #else
-#undef CFG_IPBCLK_EQUALS_XLBCLK   	/* define for 133MHz speed */
+#undef CFG_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
 #endif
 #endif /* CONFIG_MPC5200 */
 
diff --git a/include/configs/M5235EVB.h b/include/configs/M5235EVB.h
index 3ee2b395a4..8af1c52abf 100644
--- a/include/configs/M5235EVB.h
+++ b/include/configs/M5235EVB.h
@@ -84,7 +84,7 @@
 
 #	define CFG_FEC0_PINMUX		0
 #	define CFG_FEC0_MIIBASE		CFG_FEC0_IOBASE
-#	define MCFFEC_TOUT_LOOP 	50000
+#	define MCFFEC_TOUT_LOOP		50000
 /* If CFG_DISCOVER_PHY is not defined - hardcoded */
 #	ifndef CFG_DISCOVER_PHY
 #		define FECDUPLEX	FULL
diff --git a/include/configs/M5271EVB.h b/include/configs/M5271EVB.h
index e1cc720e77..a6fac4cbf6 100644
--- a/include/configs/M5271EVB.h
+++ b/include/configs/M5271EVB.h
@@ -95,7 +95,7 @@
 
 #	define CFG_FEC0_PINMUX		0
 #	define CFG_FEC0_MIIBASE		CFG_FEC0_IOBASE
-#	define MCFFEC_TOUT_LOOP 	50000
+#	define MCFFEC_TOUT_LOOP		50000
 /* If CFG_DISCOVER_PHY is not defined - hardcoded */
 #	ifndef CFG_DISCOVER_PHY
 #		define FECDUPLEX	FULL
diff --git a/include/configs/M5272C3.h b/include/configs/M5272C3.h
index 2b8734b4c6..7edd322bdd 100644
--- a/include/configs/M5272C3.h
+++ b/include/configs/M5272C3.h
@@ -97,7 +97,7 @@
 
 #	define CFG_FEC0_PINMUX		0
 #	define CFG_FEC0_MIIBASE		CFG_FEC0_IOBASE
-#	define MCFFEC_TOUT_LOOP 	50000
+#	define MCFFEC_TOUT_LOOP		50000
 /* If CFG_DISCOVER_PHY is not defined - hardcoded */
 #	ifndef CFG_DISCOVER_PHY
 #		define FECDUPLEX	FULL
diff --git a/include/configs/M5282EVB.h b/include/configs/M5282EVB.h
index 826778c35a..df46ee4438 100644
--- a/include/configs/M5282EVB.h
+++ b/include/configs/M5282EVB.h
@@ -82,7 +82,7 @@
 
 #	define CFG_FEC0_PINMUX		0
 #	define CFG_FEC0_MIIBASE		CFG_FEC0_IOBASE
-#	define MCFFEC_TOUT_LOOP 	50000
+#	define MCFFEC_TOUT_LOOP		50000
 /* If CFG_DISCOVER_PHY is not defined - hardcoded */
 #	ifndef CFG_DISCOVER_PHY
 #		define FECDUPLEX	FULL
@@ -215,13 +215,13 @@
 #define CFG_CS0_BASE		CFG_FLASH_BASE
 #define CFG_CS0_SIZE		2*1024*1024
 #define CFG_CS0_WIDTH		16
-#define CFG_CS0_RO 		0
+#define CFG_CS0_RO		0
 #define CFG_CS0_WS		6
 /*
 #define CFG_CS3_BASE		0xE0000000
 #define CFG_CS3_SIZE		1*1024*1024
 #define CFG_CS3_WIDTH		16
-#define CFG_CS3_RO 		0
+#define CFG_CS3_RO		0
 #define CFG_CS3_WS		6
 */
 /*-----------------------------------------------------------------------
@@ -246,6 +246,6 @@
 #define CFG_PEHLPAR		0xC0
 #define CFG_PUAPAR		0x0F	/* UA0..UA3 = Uart 0 +1 */
 #define CFG_DDRUA		0x05
-#define CFG_PJPAR 		0xFF;
+#define CFG_PJPAR		0xFF;
 
 #endif				/* _CONFIG_M5282EVB_H */
diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h
index 42692d69fa..b30d99c92e 100644
--- a/include/configs/M5329EVB.h
+++ b/include/configs/M5329EVB.h
@@ -77,7 +77,7 @@
 
 #	define CFG_FEC0_PINMUX		0
 #	define CFG_FEC0_MIIBASE		CFG_FEC0_IOBASE
-#	define MCFFEC_TOUT_LOOP 	50000
+#	define MCFFEC_TOUT_LOOP		50000
 /* If CFG_DISCOVER_PHY is not defined - hardcoded */
 #	ifndef CFG_DISCOVER_PHY
 #		define FECDUPLEX	FULL
diff --git a/include/configs/M5373EVB.h b/include/configs/M5373EVB.h
index 3b9da17e40..a710c6d9f8 100644
--- a/include/configs/M5373EVB.h
+++ b/include/configs/M5373EVB.h
@@ -77,7 +77,7 @@
 
 #	define CFG_FEC0_PINMUX		0
 #	define CFG_FEC0_MIIBASE		CFG_FEC0_IOBASE
-#	define MCFFEC_TOUT_LOOP 	50000
+#	define MCFFEC_TOUT_LOOP		50000
 /* If CFG_DISCOVER_PHY is not defined - hardcoded */
 #	ifndef CFG_DISCOVER_PHY
 #		define FECDUPLEX	FULL
diff --git a/include/configs/M5475EVB.h b/include/configs/M5475EVB.h
index fea7551cf1..a19c342270 100644
--- a/include/configs/M5475EVB.h
+++ b/include/configs/M5475EVB.h
@@ -83,7 +83,7 @@
 #	define CFG_FEC1_PINMUX		0
 #	define CFG_FEC1_MIIBASE		CFG_FEC0_IOBASE
 
-#	define MCFFEC_TOUT_LOOP 	50000
+#	define MCFFEC_TOUT_LOOP		50000
 /* If CFG_DISCOVER_PHY is not defined - hardcoded */
 #	ifndef CFG_DISCOVER_PHY
 #		define FECDUPLEX	FULL
diff --git a/include/configs/M5485EVB.h b/include/configs/M5485EVB.h
index 454d0a28dc..b73e2e006d 100644
--- a/include/configs/M5485EVB.h
+++ b/include/configs/M5485EVB.h
@@ -83,7 +83,7 @@
 #	define CFG_FEC1_PINMUX		0
 #	define CFG_FEC1_MIIBASE		CFG_FEC0_IOBASE
 
-#	define MCFFEC_TOUT_LOOP 	50000
+#	define MCFFEC_TOUT_LOOP		50000
 /* If CFG_DISCOVER_PHY is not defined - hardcoded */
 #	ifndef CFG_DISCOVER_PHY
 #		define FECDUPLEX	FULL
diff --git a/include/configs/MIP405.h b/include/configs/MIP405.h
index 9ddf82b3e0..d683b87ae0 100644
--- a/include/configs/MIP405.h
+++ b/include/configs/MIP405.h
@@ -123,7 +123,7 @@
  * (to get SDRAM settings)
  ***************************************************************/
 /*#define SDRAM_EEPROM_WRITE_ADDRESS	0xA0
-#define SDRAM_EEPROM_READ_ADDRESS 	0xA1
+#define SDRAM_EEPROM_READ_ADDRESS	0xA1
 */
 /**************************************************************
  * Environment definitions
@@ -132,7 +132,7 @@
 #define CONFIG_BOOTDELAY	5
 /* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
 /* #define CONFIG_BOOT_RETRY_TIME	-10	/XXX* feature is available but not enabled */
-#define CONFIG_ZERO_BOOTDELAY_CHECK  	/* check console even if bootdelay = 0 */
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check console even if bootdelay = 0 */
 
 #define CONFIG_BOOTCOMMAND	"diskboot 400000 0:1; bootm" /* autoboot command		*/
 #define CONFIG_BOOTARGS		"console=ttyS0,9600 root=/dev/hda5" /* boot arguments */
@@ -260,7 +260,7 @@
 /*-----------------------------------------------------------------------
  * Logbuffer Configuration
  */
-#undef CONFIG_LOGBUFFER 	/* supported but not enabled */
+#undef CONFIG_LOGBUFFER		/* supported but not enabled */
 /*-----------------------------------------------------------------------
  * Bootcountlimit Configuration
  */
@@ -271,8 +271,8 @@
  */
 #if 0 /* enable this if POST is desired (is supported but not enabled) */
 #define CONFIG_POST		(CFG_POST_MEMORY	| \
-				 CFG_POST_CPU 		| \
-				 CFG_POST_RTC 		| \
+				 CFG_POST_CPU		| \
+				 CFG_POST_RTC		| \
 				 CFG_POST_I2C)
 
 #endif
@@ -292,7 +292,7 @@
 #define PER_UART1_ADDR		0xF4200000 /* smallest window is 1MByte 0x10 0000*/
 
 #define MULTI_PURPOSE_SOCKET_ADDR 0xF8000000
-#define CONFIG_PORT_ADDR 	PER_PLD_ADDR + 5
+#define CONFIG_PORT_ADDR	PER_PLD_ADDR + 5
 
 
 /*-----------------------------------------------------------------------
@@ -301,7 +301,7 @@
 #define CFG_TEMP_STACK_OCM      1
 #define CFG_OCM_DATA_ADDR	0xF0000000
 #define CFG_OCM_DATA_SIZE	0x1000
-#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR 	/* inside of On Chip SRAM    */
+#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR	/* inside of On Chip SRAM    */
 #define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE	/* End of On Chip SRAM	       */
 #define CFG_GBL_DATA_SIZE	64		/* size in bytes reserved for initial data */
 #define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
@@ -362,7 +362,7 @@
 #define CFG_ATA_IDE0_OFFSET	0x01F0		/* ide0 offste */
 #define CFG_ATA_IDE1_OFFSET	0x0170		/* ide1 offset */
 #define CFG_ATA_DATA_OFFSET	0		/* data reg offset	*/
-#define CFG_ATA_REG_OFFSET 	0		/* reg offset */
+#define CFG_ATA_REG_OFFSET	0		/* reg offset */
 #define CFG_ATA_ALT_OFFSET	0x200		/* alternate register offset */
 
 #undef	CONFIG_IDE_8xx_DIRECT      /* no pcmcia interface required */
diff --git a/include/configs/MOUSSE.h b/include/configs/MOUSSE.h
index 9370c24c50..021729b582 100644
--- a/include/configs/MOUSSE.h
+++ b/include/configs/MOUSSE.h
@@ -265,18 +265,18 @@
 #else
 #define CFG_IBAT1L      (PORTX_DEV_BASE | BATL_PP_10 |BATL_CACHEINHIBIT)
 #endif
-#define CFG_DBAT1U  	CFG_IBAT1U
-#define CFG_DBAT1L  	CFG_IBAT1L
+#define CFG_DBAT1U	CFG_IBAT1U
+#define CFG_DBAT1L	CFG_IBAT1L
 
 /* PCI Memory region 1: 0x8XXX_XXXX PCI Mem space: EUMBAR, etc - 16MB */
-#define CFG_IBAT2U  	(PCI_MEM_SPACE1_START|BATU_BL_16M | BATU_VS | BATU_VP)
-#define CFG_IBAT2L 	(PCI_MEM_SPACE1_START|BATL_PP_10 | BATL_GUARDEDSTORAGE|BATL_CACHEINHIBIT)
+#define CFG_IBAT2U	(PCI_MEM_SPACE1_START|BATU_BL_16M | BATU_VS | BATU_VP)
+#define CFG_IBAT2L	(PCI_MEM_SPACE1_START|BATL_PP_10 | BATL_GUARDEDSTORAGE|BATL_CACHEINHIBIT)
 #define CFG_DBAT2U      CFG_IBAT2U
 #define CFG_DBAT2L      CFG_IBAT2L
 
 /* PCI Memory region 2: PCI Devices in 0xFD space */
-#define CFG_IBAT3U  	(PCI_MEM_SPACE2_START|BATU_BL_16M | BATU_VS | BATU_VP)
-#define CFG_IBAT3L 	(PCI_MEM_SPACE2_START|BATL_PP_10 | BATL_GUARDEDSTORAGE | BATL_CACHEINHIBIT)
+#define CFG_IBAT3U	(PCI_MEM_SPACE2_START|BATU_BL_16M | BATU_VS | BATU_VP)
+#define CFG_IBAT3L	(PCI_MEM_SPACE2_START|BATL_PP_10 | BATL_GUARDEDSTORAGE | BATL_CACHEINHIBIT)
 #define CFG_DBAT3U      CFG_IBAT3U
 #define CFG_DBAT3L      CFG_IBAT3L
 
@@ -299,7 +299,7 @@
 
 #if 0
 #define	CFG_ENV_IS_IN_FLASH	    1
-#define CFG_ENV_OFFSET          0x8000  /* Offset of the Environment Sector	 */
+#define CFG_ENV_OFFSET          0x8000  /* Offset of the Environment Sector	*/
 #define CFG_ENV_SIZE            0x4000  /* Size of the Environment Sector    */
 #else
 #define CFG_ENV_IS_IN_NVRAM          1
@@ -339,7 +339,7 @@
 #define CONFIG_PCI			/* include pci support			*/
 #undef CONFIG_PCI_PNP
 
-#define CONFIG_NET_MULTI		/* Multi ethernet cards support 	*/
+#define CONFIG_NET_MULTI		/* Multi ethernet cards support		*/
 
 #define CONFIG_TULIP
 
diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h
index f9fa535ff7..610151f586 100644
--- a/include/configs/MPC8313ERDB.h
+++ b/include/configs/MPC8313ERDB.h
@@ -217,7 +217,7 @@
 			| (0xFF << LBCR_BMT_SHIFT) \
 			| 0xF )	/* 0x0004ff0f */
 
-#define CFG_LBC_MRTPR	0x20000000  /*TODO */ 	/* LB refresh timer prescal, 266MHz/32 */
+#define CFG_LBC_MRTPR	0x20000000  /*TODO */	/* LB refresh timer prescal, 266MHz/32 */
 
 /* drivers/mtd/nand/nand.c */
 #define CFG_NAND_BASE		0xE2800000	/* 0xF0000000 */
@@ -549,28 +549,28 @@
 #define MK_STR(x)	XMK_STR(x)
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
-	"netdev=" MK_STR(CONFIG_NETDEV) "\0" 				\
+	"netdev=" MK_STR(CONFIG_NETDEV) "\0"				\
 	"ethprime=TSEC1\0"						\
-	"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" 				\
-	"tftpflash=tftpboot $loadaddr $uboot; " 			\
-		"protect off " MK_STR(TEXT_BASE) " +$filesize; " 	\
-		"erase " MK_STR(TEXT_BASE) " +$filesize; " 		\
-		"cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " 	\
-		"protect on " MK_STR(TEXT_BASE) " +$filesize; " 	\
-		"cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" 	\
+	"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"				\
+	"tftpflash=tftpboot $loadaddr $uboot; "				\
+		"protect off " MK_STR(TEXT_BASE) " +$filesize; "	\
+		"erase " MK_STR(TEXT_BASE) " +$filesize; "		\
+		"cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; "	\
+		"protect on " MK_STR(TEXT_BASE) " +$filesize; "		\
+		"cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0"	\
 	"fdtaddr=400000\0"						\
 	"fdtfile=" MK_STR(CONFIG_FDTFILE) "\0"				\
 	"console=ttyS0\0"						\
 	"setbootargs=setenv bootargs "					\
 		"root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
-	"setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
+	"setipargs=setenv bootargs nfsroot=$serverip:$rootpath "	 \
 		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 		"root=$rootdev rw console=$console,$baudrate $othbootargs\0"
 
 #define CONFIG_NFSBOOTCOMMAND						\
 	"setenv rootdev /dev/nfs;"					\
-	"run setbootargs;"							\
-	"run setipargs;"							\
+	"run setbootargs;"						\
+	"run setipargs;"						\
 	"tftp $loadaddr $bootfile;"					\
 	"tftp $fdtaddr $fdtfile;"					\
 	"bootm $loadaddr - $fdtaddr"
diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h
index ddefa5e919..1276a124c9 100644
--- a/include/configs/MPC832XEMDS.h
+++ b/include/configs/MPC832XEMDS.h
@@ -574,7 +574,7 @@
 
 #define CONFIG_LOADADDR	500000	/* default location for tftp and bootm */
 
-#define CONFIG_BOOTDELAY 6 	/* -1 disables auto-boot */
+#define CONFIG_BOOTDELAY 6	/* -1 disables auto-boot */
 #undef  CONFIG_BOOTARGS		/* the boot command will set bootargs */
 
 #define CONFIG_EXTRA_ENV_SETTINGS					\
diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
index cf552c2487..119e7ac7c6 100644
--- a/include/configs/MPC8349EMDS.h
+++ b/include/configs/MPC8349EMDS.h
@@ -39,7 +39,7 @@
 #define CONFIG_MPC8349EMDS	1	/* MPC8349EMDS board specific */
 
 #undef CONFIG_PCI
-#undef CONFIG_MPC83XX_PCI2 		/* support for 2nd PCI controller */
+#undef CONFIG_MPC83XX_PCI2		/* support for 2nd PCI controller */
 
 #define PCI_66M
 #ifdef PCI_66M
@@ -414,7 +414,7 @@
 #if !defined(CONFIG_PCI_PNP)
 	#define PCI_ENET0_IOADDR	0xFIXME
 	#define PCI_ENET0_MEMADDR	0xFIXME
-	#define PCI_IDSEL_NUMBER	0x0c 	/* slot0->3(IDSEL)=12->15 */
+	#define PCI_IDSEL_NUMBER	0x0c	/* slot0->3(IDSEL)=12->15 */
 #endif
 
 #undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h
index be8850a7e7..c72de03c01 100644
--- a/include/configs/MPC8349ITX.h
+++ b/include/configs/MPC8349ITX.h
@@ -149,8 +149,8 @@
  * DDR Setup
  */
 #define CFG_DDR_BASE		0x00000000	/* DDR is system memory*/
-#define CFG_SDRAM_BASE 		CFG_DDR_BASE
-#define CFG_DDR_SDRAM_BASE 	CFG_DDR_BASE
+#define CFG_SDRAM_BASE		CFG_DDR_BASE
+#define CFG_DDR_SDRAM_BASE	CFG_DDR_BASE
 #define CFG_83XX_DDR_USES_CS0
 #define CFG_MEMTEST_START	0x1000		/* memtest region */
 #define CFG_MEMTEST_END		0x2000
@@ -187,7 +187,7 @@
 boards, we say we have two, but don't display a message if we find only one. */
 #define CFG_FLASH_QUIET_TEST
 #define CFG_MAX_FLASH_BANKS	2		/* number of banks */
-#define CFG_FLASH_BANKS_LIST 	{CFG_FLASH_BASE, CFG_FLASH_BASE + 0x800000}
+#define CFG_FLASH_BANKS_LIST	{CFG_FLASH_BASE, CFG_FLASH_BASE + 0x800000}
 #define CFG_FLASH_SIZE		16		/* FLASH size in MB */
 #define CFG_FLASH_SIZE_SHIFT	4		/* log2 of the above value */
 
@@ -671,21 +671,21 @@ boards, we say we have two, but don't display a message if we find only one. */
 #define CONFIG_BOOTARGS \
 	"root=/dev/nfs rw" \
 	" nfsroot=" MK_STR(CONFIG_SERVERIP) ":" MK_STR(CONFIG_ROOTPATH) \
-	" ip=" MK_STR(CONFIG_IPADDR) ":" MK_STR(CONFIG_SERVERIP) ":" 	\
+	" ip=" MK_STR(CONFIG_IPADDR) ":" MK_STR(CONFIG_SERVERIP) ":"	\
 		MK_STR(CONFIG_GATEWAYIP) ":" MK_STR(CONFIG_NETMASK) ":" \
 		MK_STR(CONFIG_HOSTNAME) ":" MK_STR(CONFIG_NETDEV) ":off" \
 	" console=" MK_STR(CONFIG_CONSOLE) "," MK_STR(CONFIG_BAUDRATE)
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
-	"console=" MK_STR(CONFIG_CONSOLE) "\0" 				\
-	"netdev=" MK_STR(CONFIG_NETDEV) "\0" 				\
-	"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" 				\
-	"tftpflash=tftpboot $loadaddr $uboot; " 			\
-		"protect off " MK_STR(TEXT_BASE) " +$filesize; " 	\
-		"erase " MK_STR(TEXT_BASE) " +$filesize; " 		\
-		"cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " 	\
-		"protect on " MK_STR(TEXT_BASE) " +$filesize; " 	\
-		"cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" 	\
+	"console=" MK_STR(CONFIG_CONSOLE) "\0"				\
+	"netdev=" MK_STR(CONFIG_NETDEV) "\0"				\
+	"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"				\
+	"tftpflash=tftpboot $loadaddr $uboot; "				\
+		"protect off " MK_STR(TEXT_BASE) " +$filesize; "	\
+		"erase " MK_STR(TEXT_BASE) " +$filesize; "		\
+		"cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; "	\
+		"protect on " MK_STR(TEXT_BASE) " +$filesize; "		\
+		"cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0"	\
 	"fdtaddr=400000\0"						\
 	"fdtfile=" MK_STR(CONFIG_FDTFILE) "\0"
 
diff --git a/include/configs/MPC8360ERDK.h b/include/configs/MPC8360ERDK.h
index a4f6af6733..7b7d6f50c0 100644
--- a/include/configs/MPC8360ERDK.h
+++ b/include/configs/MPC8360ERDK.h
@@ -535,11 +535,11 @@
    "ubootfile=u-boot.bin\0"\
    "mtdparts=mtdparts=60000000.nand-flash:4096k(kernel),128k(dtb),-(rootfs)\0"\
    "setbootargs=setenv bootargs console=$consoledev,$baudrate "\
-   		"$mtdparts panic=1\0"\
+		"$mtdparts panic=1\0"\
    "adddhcpargs=setenv bootargs $bootargs ip=on\0"\
    "addnfsargs=setenv bootargs $bootargs ip=$ipaddr:$serverip:"\
-   		"$gatewayip:$netmask:$hostname:$netdev:off "\
-   		"root=/dev/nfs rw nfsroot=$serverip:$rootpath\0"\
+		"$gatewayip:$netmask:$hostname:$netdev:off "\
+		"root=/dev/nfs rw nfsroot=$serverip:$rootpath\0"\
    "addnandargs=setenv bootargs $bootargs root=/dev/mtdblock3 "\
 		"rootfstype=jffs2 rw\0"\
    "tftp_get_uboot=tftp 100000 $ubootfile\0"\
@@ -555,7 +555,7 @@
    "nand_read_kernel=nand read.jffs2 $loadaddr 0 400000\0"\
    "nand_read_dtb=nand read.jffs2 $fdtaddr 400000 20000\0"\
    "nor_reflash=protect off ff800000 ff87ffff ; erase ff800000 ff87ffff ; "\
-   		"cp.b 100000 ff800000 $filesize\0"\
+		"cp.b 100000 ff800000 $filesize\0"\
    "nand_reflash_kernel=run tftp_get_kernel nand_erase_kernel "\
 		"nand_write_kernel\0"\
    "nand_reflash_dtb=run tftp_get_dtb nand_erase_dtb nand_write_dtb\0"\
diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h
index 85934d718d..5719759808 100644
--- a/include/configs/MPC8540ADS.h
+++ b/include/configs/MPC8540ADS.h
@@ -46,7 +46,7 @@
 #endif
 
 #define CONFIG_PCI
-#define CONFIG_TSEC_ENET 		/* tsec ethernet support */
+#define CONFIG_TSEC_ENET		/* tsec ethernet support */
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
 #define CONFIG_DDR_DLL			/* possible DLL fix needed */
@@ -98,7 +98,7 @@
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  */
-#define CFG_CCSRBAR_DEFAULT 	0xff700000	/* CCSRBAR Default */
+#define CFG_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
 #define CFG_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
 #define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */
@@ -147,7 +147,7 @@
 #define CFG_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
 #define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
 
-#define CFG_MONITOR_BASE    	TEXT_BASE	/* start of monitor */
+#define CFG_MONITOR_BASE	TEXT_BASE	/* start of monitor */
 
 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
 #define CFG_RAMBOOT
@@ -268,16 +268,16 @@
 #define CFG_BCSR		(CFG_BR4_PRELIM & 0xffff8000)
 
 #define CONFIG_L1_INIT_RAM
-#define CFG_INIT_RAM_LOCK 	1
+#define CFG_INIT_RAM_LOCK	1
 #define CFG_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
-#define CFG_INIT_RAM_END    	0x4000	    	/* End of used area in RAM */
+#define CFG_INIT_RAM_END	0x4000		/* End of used area in RAM */
 
-#define CFG_GBL_DATA_SIZE  	128		/* num bytes initial data */
+#define CFG_GBL_DATA_SIZE	128		/* num bytes initial data */
 #define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 #define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
 
-#define CFG_MONITOR_LEN	    	(256 * 1024)    /* Reserve 256 kB for Mon */
-#define CFG_MALLOC_LEN	    	(128 * 1024)    /* Reserved for malloc */
+#define CFG_MONITOR_LEN		(256 * 1024)    /* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN		(128 * 1024)    /* Reserved for malloc */
 
 /* Serial Port */
 #define CONFIG_CONS_INDEX     1
@@ -337,7 +337,7 @@
 #if defined(CONFIG_PCI)
 
 #define CONFIG_NET_MULTI
-#define CONFIG_PCI_PNP	               	/* do pci plug-and-play */
+#define CONFIG_PCI_PNP			/* do pci plug-and-play */
 
 #undef CONFIG_EEPRO100
 #undef CONFIG_TULIP
@@ -345,7 +345,7 @@
 #if !defined(CONFIG_PCI_PNP)
     #define PCI_ENET0_IOADDR	0xe0000000
     #define PCI_ENET0_MEMADDR	0xe0000000
-    #define PCI_IDSEL_NUMBER	0x0c 	/* slot0->3(IDSEL)=12->15 */
+    #define PCI_IDSEL_NUMBER	0x0c	/* slot0->3(IDSEL)=12->15 */
 #endif
 
 #undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
@@ -357,7 +357,7 @@
 #if defined(CONFIG_TSEC_ENET)
 
 #ifndef CONFIG_NET_MULTI
-#define CONFIG_NET_MULTI 	1
+#define CONFIG_NET_MULTI	1
 #endif
 
 #define CONFIG_MII		1	/* MII PHY management */
diff --git a/include/configs/MPC8540EVAL.h b/include/configs/MPC8540EVAL.h
index 77eea73787..b13c81c2e2 100644
--- a/include/configs/MPC8540EVAL.h
+++ b/include/configs/MPC8540EVAL.h
@@ -30,14 +30,14 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 /* High Level Configuration Options */
-#define CONFIG_BOOKE		1	    /* BOOKE 			*/
+#define CONFIG_BOOKE		1	    /* BOOKE			*/
 #define CONFIG_E500		1	    /* BOOKE e500 family	*/
 #define CONFIG_MPC85xx		1	    /* MPC8540/MPC8560		*/
 #define CONFIG_MPC8540		1	    /* MPC8540 specific	        */
 #define CONFIG_MPC8540EVAL	1	    /* MPC8540EVAL board specific */
 
-#undef  CONFIG_PCI	         	    /* pci ethernet support	*/
-#define CONFIG_TSEC_ENET 		    /* tsec ethernet support  */
+#undef  CONFIG_PCI			    /* pci ethernet support	*/
+#define CONFIG_TSEC_ENET		    /* tsec ethernet support  */
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_SPD_EEPROM                   /* Use SPD EEPROM for DDR setup */
 #undef  CONFIG_DDR_ECC			    /* only for ECC DDR module */
@@ -63,7 +63,7 @@
 #endif
 
 /* below can be toggled for performance analysis. otherwise use default */
-#define CONFIG_L2_CACHE		    	    /* toggle L2 cache 	*/
+#define CONFIG_L2_CACHE			    /* toggle L2 cache	*/
 #undef  CONFIG_BTB			    /* toggle branch predition */
 #undef  CONFIG_ADDR_STREAMING		    /* toggle addr streaming   */
 
@@ -81,8 +81,8 @@
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  */
-#define CFG_CCSRBAR_DEFAULT 	0xff700000	/* CCSRBAR Default	*/
-#define CFG_CCSRBAR		0xe0000000	/* relocated CCSRBAR 	*/
+#define CFG_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default	*/
+#define CFG_CCSRBAR		0xe0000000	/* relocated CCSRBAR	*/
 #define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR	*/
 
@@ -113,7 +113,7 @@
 #define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)*/
 #define CFG_FLASH_CFI		1
 
-#define CFG_MONITOR_BASE    	TEXT_BASE	/* start of monitor */
+#define CFG_MONITOR_BASE	TEXT_BASE	/* start of monitor */
 
 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
 #define CFG_RAMBOOT
@@ -150,16 +150,16 @@
 #define CFG_BCSR                (CFG_BR4_PRELIM & 0xffff8000)
 
 #define CONFIG_L1_INIT_RAM
-#define CFG_INIT_RAM_LOCK 	1
-#define CFG_INIT_RAM_ADDR   	0x40000000 	/* Initial RAM address	*/
-#define CFG_INIT_RAM_END    	0x4000	    	/* End of used area in RAM */
+#define CFG_INIT_RAM_LOCK	1
+#define CFG_INIT_RAM_ADDR	0x40000000	/* Initial RAM address	*/
+#define CFG_INIT_RAM_END	0x4000		/* End of used area in RAM */
 
-#define CFG_GBL_DATA_SIZE  	128		/* num bytes initial data */
+#define CFG_GBL_DATA_SIZE	128		/* num bytes initial data */
 #define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 #define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
 
-#define CFG_MONITOR_LEN	    	(256 * 1024)    /* Reserve 256 kB for Mon */
-#define CFG_MALLOC_LEN	    	(128 * 1024)    /* Reserved for malloc */
+#define CFG_MONITOR_LEN		(256 * 1024)    /* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN		(128 * 1024)    /* Reserved for malloc */
 
 /* Serial Port */
 #define CONFIG_CONS_INDEX     1
@@ -168,7 +168,7 @@
 #define CFG_NS16550_SERIAL
 #define CFG_NS16550_REG_SIZE    1
 #define CFG_NS16550_CLK		get_bus_freq(0)
-#define CONFIG_BAUDRATE	 	115200
+#define CONFIG_BAUDRATE		115200
 
 #define CFG_BAUDRATE_TABLE  \
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
@@ -203,17 +203,17 @@
 #define CONFIG_NET_MULTI
 #undef CONFIG_EEPRO100
 #define CONFIG_TULIP
-#define CONFIG_PCI_PNP	               	/* do pci plug-and-play */
+#define CONFIG_PCI_PNP			/* do pci plug-and-play */
 #if !defined(CONFIG_PCI_PNP)
 #define PCI_ENET0_IOADDR      0xe0000000
 #define PCI_ENET0_MEMADDR     0xe0000000
-#define PCI_IDSEL_NUMBER      0x0c 	/*slot0->3(IDSEL)=12->15*/
+#define PCI_IDSEL_NUMBER      0x0c	/*slot0->3(IDSEL)=12->15*/
 #endif
 #define CONFIG_PCI_SCAN_SHOW    1       /* show pci devices on startup  */
 #define CFG_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
 #define CFG_PCI_SUBSYS_DEVICEID 0x0008
 #elif defined(CONFIG_TSEC_ENET)
-#define CONFIG_NET_MULTI 	1
+#define CONFIG_NET_MULTI	1
 #define CONFIG_MII		1	/* MII PHY management	*/
 #define CONFIG_TSEC1    1
 #define CONFIG_HAS_ETH0
@@ -262,7 +262,7 @@
 
 #define CONFIG_BOOTARGS	"root=/dev/ram rw console=ttyS0,115200"
 #define CONFIG_BOOTCOMMAND	"bootm 0xff800000 0xffa00000"
-#define CONFIG_BOOTDELAY	3 	/* -1 disable autoboot */
+#define CONFIG_BOOTDELAY	3	/* -1 disable autoboot */
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
 #define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
@@ -318,7 +318,7 @@
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ	(8 << 20) 	/* Initial Memory map for Linux */
+#define CFG_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux */
 
 /*
  * Internal Definitions
diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h
index 3f3f741ade..5b3ea05e63 100644
--- a/include/configs/MPC8541CDS.h
+++ b/include/configs/MPC8541CDS.h
@@ -38,7 +38,7 @@
 #define CONFIG_MPC8541CDS	1	/* MPC8541CDS board specific */
 
 #define CONFIG_PCI
-#define CONFIG_TSEC_ENET 		/* tsec ethernet support */
+#define CONFIG_TSEC_ENET		/* tsec ethernet support */
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
 #define CONFIG_DDR_DLL			/* possible DLL fix needed */
@@ -69,7 +69,7 @@ extern unsigned long get_clock_freq(void);
 /*
  * These can be toggled for performance analysis, otherwise use default.
  */
-#define CONFIG_L2_CACHE		    	    /* toggle L2 cache 	*/
+#define CONFIG_L2_CACHE			    /* toggle L2 cache	*/
 #define CONFIG_BTB			    /* toggle branch predition */
 #define CONFIG_ADDR_STREAMING		    /* toggle addr streaming   */
 
@@ -83,7 +83,7 @@ extern unsigned long get_clock_freq(void);
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  */
-#define CFG_CCSRBAR_DEFAULT 	0xff700000	/* CCSRBAR Default */
+#define CFG_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
 #define CFG_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
 #define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */
@@ -155,7 +155,7 @@ extern unsigned long get_clock_freq(void);
 #define CFG_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
 #define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
 
-#define CFG_MONITOR_BASE    	TEXT_BASE	/* start of monitor */
+#define CFG_MONITOR_BASE	TEXT_BASE	/* start of monitor */
 
 #define CFG_FLASH_CFI_DRIVER
 #define CFG_FLASH_CFI
@@ -284,16 +284,16 @@ extern unsigned long get_clock_freq(void);
 #define CFG_OR3_PRELIM   0xfff00ff7
 
 #define CONFIG_L1_INIT_RAM
-#define CFG_INIT_RAM_LOCK 	1
+#define CFG_INIT_RAM_LOCK	1
 #define CFG_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
-#define CFG_INIT_RAM_END    	0x4000	    /* End of used area in RAM */
+#define CFG_INIT_RAM_END	0x4000	    /* End of used area in RAM */
 
-#define CFG_GBL_DATA_SIZE  	128	    /* num bytes initial data */
+#define CFG_GBL_DATA_SIZE	128	    /* num bytes initial data */
 #define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 #define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
 
-#define CFG_MONITOR_LEN	    	(256 * 1024) /* Reserve 256 kB for Mon */
-#define CFG_MALLOC_LEN	    	(128 * 1024)	/* Reserved for malloc */
+#define CFG_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserved for malloc */
 
 /* Serial Port */
 #define CONFIG_CONS_INDEX     2
@@ -362,7 +362,7 @@ extern unsigned long get_clock_freq(void);
 
 #define CONFIG_MPC85XX_PCI2
 #define CONFIG_NET_MULTI
-#define CONFIG_PCI_PNP	               	/* do pci plug-and-play */
+#define CONFIG_PCI_PNP			/* do pci plug-and-play */
 
 #undef CONFIG_EEPRO100
 #undef CONFIG_TULIP
@@ -376,7 +376,7 @@ extern unsigned long get_clock_freq(void);
 #if defined(CONFIG_TSEC_ENET)
 
 #ifndef CONFIG_NET_MULTI
-#define CONFIG_NET_MULTI 	1
+#define CONFIG_NET_MULTI	1
 #endif
 
 #define CONFIG_MII		1	/* MII PHY management */
@@ -455,7 +455,7 @@ extern unsigned long get_clock_freq(void);
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ	(8 << 20) 	/* Initial Memory map for Linux*/
+#define CFG_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
 
 /*
  * Internal Definitions
diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h
index 500b57cece..e8383455c4 100644
--- a/include/configs/MPC8555CDS.h
+++ b/include/configs/MPC8555CDS.h
@@ -38,7 +38,7 @@
 #define CONFIG_MPC8555CDS	1	/* MPC8555CDS board specific */
 
 #define CONFIG_PCI
-#define CONFIG_TSEC_ENET 		/* tsec ethernet support */
+#define CONFIG_TSEC_ENET		/* tsec ethernet support */
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
 #define CONFIG_DDR_DLL			/* possible DLL fix needed */
@@ -69,7 +69,7 @@ extern unsigned long get_clock_freq(void);
 /*
  * These can be toggled for performance analysis, otherwise use default.
  */
-#define CONFIG_L2_CACHE		    	    /* toggle L2 cache 	*/
+#define CONFIG_L2_CACHE			    /* toggle L2 cache	*/
 #define CONFIG_BTB			    /* toggle branch predition */
 #define CONFIG_ADDR_STREAMING		    /* toggle addr streaming   */
 
@@ -83,7 +83,7 @@ extern unsigned long get_clock_freq(void);
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  */
-#define CFG_CCSRBAR_DEFAULT 	0xff700000	/* CCSRBAR Default */
+#define CFG_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
 #define CFG_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
 #define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */
@@ -155,7 +155,7 @@ extern unsigned long get_clock_freq(void);
 #define CFG_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
 #define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
 
-#define CFG_MONITOR_BASE    	TEXT_BASE	/* start of monitor */
+#define CFG_MONITOR_BASE	TEXT_BASE	/* start of monitor */
 
 #define CFG_FLASH_CFI_DRIVER
 #define CFG_FLASH_CFI
@@ -284,16 +284,16 @@ extern unsigned long get_clock_freq(void);
 #define CFG_OR3_PRELIM   0xfff00ff7
 
 #define CONFIG_L1_INIT_RAM
-#define CFG_INIT_RAM_LOCK 	1
+#define CFG_INIT_RAM_LOCK	1
 #define CFG_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
-#define CFG_INIT_RAM_END    	0x4000	    /* End of used area in RAM */
+#define CFG_INIT_RAM_END	0x4000	    /* End of used area in RAM */
 
-#define CFG_GBL_DATA_SIZE  	128	    /* num bytes initial data */
+#define CFG_GBL_DATA_SIZE	128	    /* num bytes initial data */
 #define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 #define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
 
-#define CFG_MONITOR_LEN	    	(256 * 1024) /* Reserve 256 kB for Mon */
-#define CFG_MALLOC_LEN	    	(128 * 1024)	/* Reserved for malloc */
+#define CFG_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserved for malloc */
 
 /* Serial Port */
 #define CONFIG_CONS_INDEX     2
@@ -361,7 +361,7 @@ extern unsigned long get_clock_freq(void);
 #if defined(CONFIG_PCI)
 
 #define CONFIG_NET_MULTI
-#define CONFIG_PCI_PNP	               	/* do pci plug-and-play */
+#define CONFIG_PCI_PNP			/* do pci plug-and-play */
 #define CONFIG_MPC85XX_PCI2
 
 #undef CONFIG_EEPRO100
@@ -376,7 +376,7 @@ extern unsigned long get_clock_freq(void);
 #if defined(CONFIG_TSEC_ENET)
 
 #ifndef CONFIG_NET_MULTI
-#define CONFIG_NET_MULTI 	1
+#define CONFIG_NET_MULTI	1
 #endif
 
 #define CONFIG_MII		1	/* MII PHY management */
@@ -455,7 +455,7 @@ extern unsigned long get_clock_freq(void);
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ	(8 << 20) 	/* Initial Memory map for Linux*/
+#define CFG_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
 
 /*
  * Internal Definitions
diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h
index e30302c5d4..9c95cc6567 100644
--- a/include/configs/MPC8560ADS.h
+++ b/include/configs/MPC8560ADS.h
@@ -42,7 +42,7 @@
 #define CONFIG_MPC8560ADS	1	/* MPC8560ADS board specific */
 
 #define CONFIG_PCI
-#define CONFIG_TSEC_ENET 		/* tsec ethernet support */
+#define CONFIG_TSEC_ENET		/* tsec ethernet support */
 #undef CONFIG_ETHER_ON_FCC             /* cpm FCC ethernet support */
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
@@ -93,7 +93,7 @@
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  */
-#define CFG_CCSRBAR_DEFAULT 	0xff700000	/* CCSRBAR Default */
+#define CFG_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
 #define CFG_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
 #define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */
@@ -142,7 +142,7 @@
 #define CFG_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
 #define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
 
-#define CFG_MONITOR_BASE    	TEXT_BASE	/* start of monitor */
+#define CFG_MONITOR_BASE	TEXT_BASE	/* start of monitor */
 
 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
 #define CFG_RAMBOOT
@@ -263,23 +263,23 @@
 #define CFG_BCSR		(CFG_BR4_PRELIM & 0xffff8000)
 
 #define CONFIG_L1_INIT_RAM
-#define CFG_INIT_RAM_LOCK 	1
+#define CFG_INIT_RAM_LOCK	1
 #define CFG_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
-#define CFG_INIT_RAM_END    	0x4000	    	/* End of used area in RAM */
+#define CFG_INIT_RAM_END	0x4000		/* End of used area in RAM */
 
-#define CFG_GBL_DATA_SIZE  	128		/* num bytes initial data */
+#define CFG_GBL_DATA_SIZE	128		/* num bytes initial data */
 #define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 #define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
 
-#define CFG_MONITOR_LEN	    	(256 * 1024)    /* Reserve 256 kB for Mon */
-#define CFG_MALLOC_LEN	    	(128 * 1024)    /* Reserved for malloc */
+#define CFG_MONITOR_LEN		(256 * 1024)    /* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN		(128 * 1024)    /* Reserved for malloc */
 
 /* Serial Port */
 #define CONFIG_CONS_ON_SCC	/* define if console on SCC */
 #undef  CONFIG_CONS_NONE	/* define if console on something else */
 #define CONFIG_CONS_INDEX       1  /* which serial channel for console */
 
-#define CONFIG_BAUDRATE	 	115200
+#define CONFIG_BAUDRATE		115200
 
 #define CFG_BAUDRATE_TABLE  \
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
@@ -325,7 +325,7 @@
 #if defined(CONFIG_PCI)
 
 #define CONFIG_NET_MULTI
-#define CONFIG_PCI_PNP	               	/* do pci plug-and-play */
+#define CONFIG_PCI_PNP			/* do pci plug-and-play */
 
 #undef CONFIG_EEPRO100
 #undef CONFIG_TULIP
@@ -333,7 +333,7 @@
 #if !defined(CONFIG_PCI_PNP)
     #define PCI_ENET0_IOADDR	0xe0000000
     #define PCI_ENET0_MEMADDR	0xe0000000
-    #define PCI_IDSEL_NUMBER	0x0c 	/* slot0->3(IDSEL)=12->15 */
+    #define PCI_IDSEL_NUMBER	0x0c	/* slot0->3(IDSEL)=12->15 */
 #endif
 
 #undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
@@ -345,7 +345,7 @@
 #ifdef CONFIG_TSEC_ENET
 
 #ifndef CONFIG_NET_MULTI
-#define CONFIG_NET_MULTI 	1
+#define CONFIG_NET_MULTI	1
 #endif
 
 #ifndef CONFIG_MII
@@ -367,9 +367,9 @@
 
 #endif /* CONFIG_TSEC_ENET */
 
-#ifdef CONFIG_ETHER_ON_FCC	/* CPM FCC Ethernet */
+#ifdef CONFIG_ETHER_ON_FCC		/* CPM FCC Ethernet */
 
-#undef  CONFIG_ETHER_NONE	/* define if ether on something else */
+#undef  CONFIG_ETHER_NONE		/* define if ether on something else */
 #define CONFIG_ETHER_INDEX      2       /* which channel for ether */
 
 #if (CONFIG_ETHER_INDEX == 2)
@@ -387,7 +387,7 @@
 #elif (CONFIG_ETHER_INDEX == 3)
   /* need more definitions here for FE3 */
   #define FETH3_RST		0x80
-#endif  				/* CONFIG_ETHER_INDEX */
+#endif					/* CONFIG_ETHER_INDEX */
 
 #ifndef CONFIG_MII
 #define CONFIG_MII		1	/* MII PHY management */
diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h
index 7bb20e58ca..a7c69d293c 100644
--- a/include/configs/MPC8568MDS.h
+++ b/include/configs/MPC8568MDS.h
@@ -38,7 +38,7 @@
 #define CONFIG_PCIE1		1	/* PCIE controller */
 #define CONFIG_FSL_PCI_INIT	1	/* use common fsl pci init code */
 #define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata */
-#define CONFIG_TSEC_ENET 		/* tsec ethernet support */
+#define CONFIG_TSEC_ENET		/* tsec ethernet support */
 #define CONFIG_QE			/* Enable QE */
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
@@ -68,7 +68,7 @@ extern unsigned long get_clock_freq(void);
 /*
  * These can be toggled for performance analysis, otherwise use default.
  */
-#define CONFIG_L2_CACHE				/* toggle L2 cache 	*/
+#define CONFIG_L2_CACHE				/* toggle L2 cache	*/
 #define CONFIG_BTB				/* toggle branch predition */
 #define CONFIG_ADDR_STREAMING			/* toggle addr streaming   */
 
@@ -88,7 +88,7 @@ extern unsigned long get_clock_freq(void);
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  */
-#define CFG_CCSRBAR_DEFAULT 	0xff700000	/* CCSRBAR Default */
+#define CFG_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
 #define CFG_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
 #define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */
@@ -166,7 +166,7 @@ extern unsigned long get_clock_freq(void);
 #define CFG_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
 #define CFG_FLASH_WRITE_TOUT	500		/* Flash Write Timeout (ms) */
 
-#define CFG_MONITOR_BASE    	TEXT_BASE	/* start of monitor */
+#define CFG_MONITOR_BASE	TEXT_BASE	/* start of monitor */
 
 #define CFG_FLASH_CFI_DRIVER
 #define CFG_FLASH_CFI
@@ -184,10 +184,10 @@ extern unsigned long get_clock_freq(void);
 #define CFG_BR2_PRELIM      0xf0001861
 #define CFG_OR2_PRELIM		0xfc006901
 
-#define CFG_LBC_LCRR		0x00030004    	/* LB clock ratio reg */
-#define CFG_LBC_LBCR		0x00000000    	/* LB config reg */
-#define CFG_LBC_LSRT		0x20000000  	/* LB sdram refresh timer */
-#define CFG_LBC_MRTPR		0x00000000  	/* LB refresh timer prescal*/
+#define CFG_LBC_LCRR		0x00030004	/* LB clock ratio reg */
+#define CFG_LBC_LBCR		0x00000000	/* LB config reg */
+#define CFG_LBC_LSRT		0x20000000	/* LB sdram refresh timer */
+#define CFG_LBC_MRTPR		0x00000000	/* LB refresh timer prescal*/
 
 /*
  * LSDMR masks
@@ -267,16 +267,16 @@ extern unsigned long get_clock_freq(void);
 #define CFG_OR5_PRELIM	 0xffff69f7
 
 #define CONFIG_L1_INIT_RAM
-#define CFG_INIT_RAM_LOCK 	1
+#define CFG_INIT_RAM_LOCK	1
 #define CFG_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
-#define CFG_INIT_RAM_END    	0x4000	    /* End of used area in RAM */
+#define CFG_INIT_RAM_END	0x4000	    /* End of used area in RAM */
 
-#define CFG_GBL_DATA_SIZE  	128	    /* num bytes initial data */
+#define CFG_GBL_DATA_SIZE	128	    /* num bytes initial data */
 #define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 #define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
 
-#define CFG_MONITOR_LEN	    	(256 * 1024) /* Reserve 256 kB for Mon */
-#define CFG_MALLOC_LEN	    	(128 * 1024)	/* Reserved for malloc */
+#define CFG_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserved for malloc */
 
 /* Serial Port */
 #define CONFIG_CONS_INDEX		1
@@ -350,7 +350,7 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_eTSEC_MDIO_BUS
 
 #ifdef CONFIG_eTSEC_MDIO_BUS
-#define CONFIG_MIIM_ADDRESS 	0xE0024520
+#define CONFIG_MIIM_ADDRESS	0xE0024520
 #endif
 
 #define CONFIG_UEC_ETH1         /* GETH1 */
@@ -379,7 +379,7 @@ extern unsigned long get_clock_freq(void);
 #if defined(CONFIG_PCI)
 
 #define CONFIG_NET_MULTI
-#define CONFIG_PCI_PNP	               	/* do pci plug-and-play */
+#define CONFIG_PCI_PNP			/* do pci plug-and-play */
 
 #undef CONFIG_EEPRO100
 #undef CONFIG_TULIP
@@ -395,7 +395,7 @@ extern unsigned long get_clock_freq(void);
 #endif	/* CONFIG_PCI */
 
 #ifndef CONFIG_NET_MULTI
-#define CONFIG_NET_MULTI 	1
+#define CONFIG_NET_MULTI	1
 #endif
 
 #if defined(CONFIG_TSEC_ENET)
@@ -480,7 +480,7 @@ extern unsigned long get_clock_freq(void);
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ	(8 << 20) 	/* Initial Memory map for Linux*/
+#define CFG_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
 
 /*
  * Internal Definitions
diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h
index 585411c4e2..15ff0eacf2 100644
--- a/include/configs/MPC8610HPCD.h
+++ b/include/configs/MPC8610HPCD.h
@@ -330,7 +330,7 @@
 #define CONFIG_USB_KEYBOARD	1
 #define CFG_DEVICE_DEREGISTER
 #define CFG_USB_EVENT_POLL	1
-#define CFG_USB_OHCI_SLOT_NAME 	"ohci_pci"
+#define CFG_USB_OHCI_SLOT_NAME	"ohci_pci"
 #define CFG_USB_OHCI_MAX_ROOT_PORTS 15
 #define CFG_OHCI_SWAP_REG_ACCESS	1
 
diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index a8d0077ca3..9acc3da54a 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -36,11 +36,11 @@
 #define CONFIG_MPC86xx		1	/* MPC86xx */
 #define CONFIG_MPC8641		1	/* MPC8641 specific */
 #define CONFIG_MPC8641HPCN	1	/* MPC8641HPCN board specific */
-#define CONFIG_NUM_CPUS         2       /* Number of CPUs in the system */
-#define CONFIG_LINUX_RESET_VEC  0x100   /* Reset vector used by Linux */
+#define CONFIG_NUM_CPUS		2	/* Number of CPUs in the system */
+#define CONFIG_LINUX_RESET_VEC	0x100	/* Reset vector used by Linux */
 
 #ifdef RUN_DIAG
-#define CFG_DIAG_ADDR        0xff800000
+#define CFG_DIAG_ADDR	     0xff800000
 #endif
 
 #define CFG_RESET_ADDRESS    0xfff00100
@@ -51,7 +51,7 @@
 #define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
 #define CONFIG_FSL_LAW		1	/* Use common FSL law init code */
 
-#define CONFIG_TSEC_ENET 		/* tsec ethernet support */
+#define CONFIG_TSEC_ENET		/* tsec ethernet support */
 #define CONFIG_ENV_OVERWRITE
 
 #define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
@@ -61,14 +61,14 @@
 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
 #define CONFIG_MEM_INIT_VALUE		0xDeadBeef
 #define CONFIG_NUM_DDR_CONTROLLERS     2
-/* #define CONFIG_DDR_INTERLEAVE               1 */
+/* #define CONFIG_DDR_INTERLEAVE	       1 */
 #define CACHE_LINE_INTERLEAVING		0x20000000
 #define PAGE_INTERLEAVING		0x21000000
 #define BANK_INTERLEAVING		0x22000000
 #define SUPER_BANK_INTERLEAVING		0x23000000
 
 
-#define CONFIG_ALTIVEC          1
+#define CONFIG_ALTIVEC		1
 
 /*
  * L2CR setup -- make sure this is right for your board!
@@ -81,7 +81,7 @@
 #ifndef __ASSEMBLY__
 extern unsigned long get_board_sys_clk(unsigned long dummy);
 #endif
-#define CONFIG_SYS_CLK_FREQ     get_board_sys_clk(0)
+#define CONFIG_SYS_CLK_FREQ	get_board_sys_clk(0)
 #endif
 
 #define CONFIG_BOARD_EARLY_INIT_F	1	/* Call board_pre_init */
@@ -94,7 +94,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  */
-#define CFG_CCSRBAR_DEFAULT 	0xff700000	/* CCSRBAR Default */
+#define CFG_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
 #define CFG_CCSRBAR		0xf8000000	/* relocated CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */
 
@@ -127,18 +127,18 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
     #define CFG_SDRAM_SIZE	256		/* DDR is 256MB */
 
     #define CFG_DDR_CS0_BNDS	0x0000000F
-    #define CFG_DDR_CS0_CONFIG	0x80010102      /* Enable, no interleaving */
+    #define CFG_DDR_CS0_CONFIG	0x80010102	/* Enable, no interleaving */
     #define CFG_DDR_EXT_REFRESH 0x00000000
-    #define CFG_DDR_TIMING_0    0x00260802
+    #define CFG_DDR_TIMING_0	0x00260802
     #define CFG_DDR_TIMING_1	0x39357322
     #define CFG_DDR_TIMING_2	0x14904cc8
     #define CFG_DDR_MODE_1	0x00480432
     #define CFG_DDR_MODE_2	0x00000000
     #define CFG_DDR_INTERVAL	0x06090100
-    #define CFG_DDR_DATA_INIT   0xdeadbeef
-    #define CFG_DDR_CLK_CTRL    0x03800000
-    #define CFG_DDR_OCD_CTRL    0x00000000
-    #define CFG_DDR_OCD_STATUS  0x00000000
+    #define CFG_DDR_DATA_INIT	0xdeadbeef
+    #define CFG_DDR_CLK_CTRL	0x03800000
+    #define CFG_DDR_OCD_CTRL	0x00000000
+    #define CFG_DDR_OCD_STATUS	0x00000000
     #define CFG_DDR_CONTROL	0xe3008000	/* Type = DDR2 */
     #define CFG_DDR_CONTROL2	0x04400000
 
@@ -170,7 +170,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
  *
  * Note that, on switching the boot location, fef00000 becomes fff00000.
  */
-#define CFG_FLASH_BASE          0xfe800000     /* start of FLASH 32M */
+#define CFG_FLASH_BASE		0xfe800000     /* start of FLASH 32M */
 #define CFG_FLASH_BASE2		0xff800000
 
 #define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE2}
@@ -189,7 +189,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 
 
 #define CONFIG_FSL_PIXIS	1	/* use common PIXIS code */
-#define PIXIS_BASE	0xf8100000      /* PIXIS registers */
+#define PIXIS_BASE	0xf8100000	/* PIXIS registers */
 #define PIXIS_ID		0x0	/* Board ID at offset 0 */
 #define PIXIS_VER		0x1	/* Board version at offset 1 */
 #define PIXIS_PVER		0x2	/* PIXIS FPGA version at offset 2 */
@@ -204,7 +204,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define PIXIS_VSPEED1		0x18	/* VELA VSpeed 1 */
 #define PIXIS_VCLKH		0x19	/* VELA VCLKH register */
 #define PIXIS_VCLKL		0x1A	/* VELA VCLKL register */
-#define CFG_PIXIS_VBOOT_MASK	0x40    /* Reset altbank mask*/
+#define CFG_PIXIS_VBOOT_MASK	0x40	/* Reset altbank mask*/
 
 #define CFG_MAX_FLASH_BANKS	2		/* number of banks */
 #define CFG_MAX_FLASH_SECT	128		/* sectors per device */
@@ -212,7 +212,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #undef	CFG_FLASH_CHECKSUM
 #define CFG_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
 #define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
-#define CFG_MONITOR_BASE    	TEXT_BASE	/* start of monitor */
+#define CFG_MONITOR_BASE	TEXT_BASE	/* start of monitor */
 
 #define CFG_FLASH_CFI_DRIVER
 #define CFG_FLASH_CFI
@@ -221,7 +221,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
 #define CFG_RAMBOOT
 #else
-#undef  CFG_RAMBOOT
+#undef	CFG_RAMBOOT
 #endif
 
 #if defined(CFG_RAMBOOT)
@@ -238,32 +238,32 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #else
 #define CFG_INIT_RAM_ADDR	0xf8400000	/* Initial RAM address */
 #endif
-#define CFG_INIT_RAM_END    	0x4000	    	/* End of used area in RAM */
+#define CFG_INIT_RAM_END	0x4000		/* End of used area in RAM */
 
-#define CFG_GBL_DATA_SIZE  	128		/* num bytes initial data */
+#define CFG_GBL_DATA_SIZE	128		/* num bytes initial data */
 #define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 #define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
 
-#define CFG_MONITOR_LEN	    	(256 * 1024)    /* Reserve 256 kB for Mon */
-#define CFG_MALLOC_LEN	    	(1024 * 1024)    /* Reserved for malloc */
+#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN		(1024 * 1024)	 /* Reserved for malloc */
 
 /* Serial Port */
 #define CONFIG_CONS_INDEX     1
 #undef	CONFIG_SERIAL_SOFTWARE_FIFO
 #define CFG_NS16550
 #define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE    1
+#define CFG_NS16550_REG_SIZE	1
 #define CFG_NS16550_CLK		get_bus_freq(0)
 
 #define CFG_BAUDRATE_TABLE  \
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 
-#define CFG_NS16550_COM1        (CFG_CCSRBAR+0x4500)
-#define CFG_NS16550_COM2        (CFG_CCSRBAR+0x4600)
+#define CFG_NS16550_COM1	(CFG_CCSRBAR+0x4500)
+#define CFG_NS16550_COM2	(CFG_CCSRBAR+0x4600)
 
 /* Use the HUSH parser */
 #define CFG_HUSH_PARSER
-#ifdef  CFG_HUSH_PARSER
+#ifdef	CFG_HUSH_PARSER
 #define CFG_PROMPT_HUSH_PS2 "> "
 #endif
 
@@ -286,7 +286,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #undef	CONFIG_SOFT_I2C			/* I2C bit-banged */
 #define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
 #define CFG_I2C_SLAVE		0x7F
-#define CFG_I2C_NOPROBES        {0x69}	/* Don't probe these addrs */
+#define CFG_I2C_NOPROBES	{0x69}	/* Don't probe these addrs */
 #define CFG_I2C_OFFSET		0x3100
 
 /*
@@ -308,13 +308,13 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CFG_PCI1_IO_SIZE	0x00100000	/* 1M */
 
 /* PCI view of System Memory */
-#define CFG_PCI_MEMORY_BUS      0x00000000
-#define CFG_PCI_MEMORY_PHYS     0x00000000
-#define CFG_PCI_MEMORY_SIZE     0x80000000
+#define CFG_PCI_MEMORY_BUS	0x00000000
+#define CFG_PCI_MEMORY_PHYS	0x00000000
+#define CFG_PCI_MEMORY_SIZE	0x80000000
 
 /* For RTL8139 */
 #define KSEG1ADDR(x)		({u32 _x=le32_to_cpu(*(u32 *)(x)); (&_x);})
-#define _IO_BASE                0x00000000
+#define _IO_BASE		0x00000000
 
 #define CFG_PCI2_MEM_BASE	0xa0000000
 #define CFG_PCI2_MEM_PHYS	CFG_PCI2_MEM_BASE
@@ -325,12 +325,12 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 
 #if defined(CONFIG_PCI)
 
-#define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
 
 #undef CFG_SCSI_SCAN_BUS_REVERSE
 
 #define CONFIG_NET_MULTI
-#define CONFIG_PCI_PNP	               	/* do pci plug-and-play */
+#define CONFIG_PCI_PNP			/* do pci plug-and-play */
 
 #define CONFIG_RTL8139
 
@@ -340,19 +340,19 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 /************************************************************
  * USB support
  ************************************************************/
-#define CONFIG_PCI_OHCI		1
+#define CONFIG_PCI_OHCI			1
 #define CONFIG_USB_OHCI_NEW		1
-#define CONFIG_USB_KEYBOARD	1
+#define CONFIG_USB_KEYBOARD		1
 #define CFG_DEVICE_DEREGISTER
-#define CFG_USB_EVENT_POLL	1
-#define CFG_USB_OHCI_SLOT_NAME 	"ohci_pci"
-#define CFG_USB_OHCI_MAX_ROOT_PORTS 15
+#define CFG_USB_EVENT_POLL		1
+#define CFG_USB_OHCI_SLOT_NAME		"ohci_pci"
+#define CFG_USB_OHCI_MAX_ROOT_PORTS	15
 #define CFG_OHCI_SWAP_REG_ACCESS	1
 
 #if !defined(CONFIG_PCI_PNP)
     #define PCI_ENET0_IOADDR	0xe0000000
     #define PCI_ENET0_MEMADDR	0xe0000000
-    #define PCI_IDSEL_NUMBER	0x0c 	/* slot0->3(IDSEL)=12->15 */
+    #define PCI_IDSEL_NUMBER	0x0c	/* slot0->3(IDSEL)=12->15 */
 #endif
 
 /*PCIE video card used*/
@@ -384,7 +384,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SATA_ULI5288
 #define CFG_SCSI_MAX_SCSI_ID	4
 #define CFG_SCSI_MAX_LUN	1
-#define CFG_SCSI_MAX_DEVICE 	(CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN)
+#define CFG_SCSI_MAX_DEVICE	(CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN)
 #define CFG_SCSI_MAXDEVICE	CFG_SCSI_MAX_DEVICE
 #endif
 
@@ -395,19 +395,19 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #if defined(CONFIG_TSEC_ENET)
 
 #ifndef CONFIG_NET_MULTI
-#define CONFIG_NET_MULTI 	1
+#define CONFIG_NET_MULTI	1
 #endif
 
 #define CONFIG_MII		1	/* MII PHY management */
 
-#define CONFIG_TSEC1    1
-#define CONFIG_TSEC1_NAME       "eTSEC1"
-#define CONFIG_TSEC2    1
-#define CONFIG_TSEC2_NAME       "eTSEC2"
-#define CONFIG_TSEC3    1
-#define CONFIG_TSEC3_NAME       "eTSEC3"
-#define CONFIG_TSEC4    1
-#define CONFIG_TSEC4_NAME       "eTSEC4"
+#define CONFIG_TSEC1		1
+#define CONFIG_TSEC1_NAME	"eTSEC1"
+#define CONFIG_TSEC2		1
+#define CONFIG_TSEC2_NAME	"eTSEC2"
+#define CONFIG_TSEC3		1
+#define CONFIG_TSEC3_NAME	"eTSEC3"
+#define CONFIG_TSEC4		1
+#define CONFIG_TSEC4_NAME	"eTSEC4"
 
 #define TSEC1_PHY_ADDR		0
 #define TSEC2_PHY_ADDR		1
@@ -427,76 +427,76 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #endif	/* CONFIG_TSEC_ENET */
 
 /*
- * BAT0         2G     Cacheable, non-guarded
- * 0x0000_0000  2G     DDR
+ * BAT0		2G     Cacheable, non-guarded
+ * 0x0000_0000	2G     DDR
  */
-#define CFG_DBAT0L      (BATL_PP_RW | BATL_MEMCOHERENCE)
-#define CFG_DBAT0U      (BATU_BL_2G | BATU_VS | BATU_VP)
-#define CFG_IBAT0L      (BATL_PP_RW | BATL_MEMCOHERENCE )
-#define CFG_IBAT0U      CFG_DBAT0U
+#define CFG_DBAT0L	(BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CFG_DBAT0U	(BATU_BL_2G | BATU_VS | BATU_VP)
+#define CFG_IBAT0L	(BATL_PP_RW | BATL_MEMCOHERENCE )
+#define CFG_IBAT0U	CFG_DBAT0U
 
 /*
- * BAT1         1G     Cache-inhibited, guarded
- * 0x8000_0000  512M   PCI-Express 1 Memory
- * 0xa000_0000  512M   PCI-Express 2 Memory
+ * BAT1		1G     Cache-inhibited, guarded
+ * 0x8000_0000	512M   PCI-Express 1 Memory
+ * 0xa000_0000	512M   PCI-Express 2 Memory
  *	Changed it for operating from 0xd0000000
  */
-#define CFG_DBAT1L      ( CFG_PCI1_MEM_PHYS | BATL_PP_RW \
+#define CFG_DBAT1L	( CFG_PCI1_MEM_PHYS | BATL_PP_RW \
 			| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 #define CFG_DBAT1U	(CFG_PCI1_MEM_PHYS | BATU_BL_1G | BATU_VS | BATU_VP)
 #define CFG_IBAT1L	(CFG_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CFG_IBAT1U      CFG_DBAT1U
+#define CFG_IBAT1U	CFG_DBAT1U
 
 /*
- * BAT2         512M   Cache-inhibited, guarded
- * 0xc000_0000  512M   RapidIO Memory
+ * BAT2		512M   Cache-inhibited, guarded
+ * 0xc000_0000	512M   RapidIO Memory
  */
-#define CFG_DBAT2L      (CFG_RIO_MEM_PHYS | BATL_PP_RW \
+#define CFG_DBAT2L	(CFG_RIO_MEM_PHYS | BATL_PP_RW \
 			| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 #define CFG_DBAT2U	(CFG_RIO_MEM_PHYS | BATU_BL_512M | BATU_VS | BATU_VP)
 #define CFG_IBAT2L	(CFG_RIO_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CFG_IBAT2U      CFG_DBAT2U
+#define CFG_IBAT2U	CFG_DBAT2U
 
 /*
- * BAT3         4M     Cache-inhibited, guarded
- * 0xf800_0000  4M     CCSR
+ * BAT3		4M     Cache-inhibited, guarded
+ * 0xf800_0000	4M     CCSR
  */
-#define CFG_DBAT3L      ( CFG_CCSRBAR | BATL_PP_RW \
+#define CFG_DBAT3L	( CFG_CCSRBAR | BATL_PP_RW \
 			| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_DBAT3U      (CFG_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP)
-#define CFG_IBAT3L      (CFG_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CFG_IBAT3U      CFG_DBAT3U
+#define CFG_DBAT3U	(CFG_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP)
+#define CFG_IBAT3L	(CFG_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CFG_IBAT3U	CFG_DBAT3U
 
 /*
- * BAT4         32M    Cache-inhibited, guarded
- * 0xe200_0000  16M    PCI-Express 1 I/O
- * 0xe300_0000  16M    PCI-Express 2 I/0
+ * BAT4		32M    Cache-inhibited, guarded
+ * 0xe200_0000	16M    PCI-Express 1 I/O
+ * 0xe300_0000	16M    PCI-Express 2 I/0
  *    Note that this is at 0xe0000000
  */
-#define CFG_DBAT4L      ( CFG_PCI1_IO_PHYS | BATL_PP_RW \
+#define CFG_DBAT4L	( CFG_PCI1_IO_PHYS | BATL_PP_RW \
 			| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 #define CFG_DBAT4U	(CFG_PCI1_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP)
 #define CFG_IBAT4L	(CFG_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CFG_IBAT4U      CFG_DBAT4U
+#define CFG_IBAT4U	CFG_DBAT4U
 
 /*
- * BAT5         128K   Cacheable, non-guarded
- * 0xe401_0000  128K   Init RAM for stack in the CPU DCache (no backing memory)
+ * BAT5		128K   Cacheable, non-guarded
+ * 0xe401_0000	128K   Init RAM for stack in the CPU DCache (no backing memory)
  */
-#define CFG_DBAT5L      (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
-#define CFG_DBAT5U      (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
-#define CFG_IBAT5L      CFG_DBAT5L
-#define CFG_IBAT5U      CFG_DBAT5U
+#define CFG_DBAT5L	(CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CFG_DBAT5U	(CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+#define CFG_IBAT5L	CFG_DBAT5L
+#define CFG_IBAT5U	CFG_DBAT5U
 
 /*
- * BAT6         32M    Cache-inhibited, guarded
- * 0xfe00_0000  32M    FLASH
+ * BAT6		32M    Cache-inhibited, guarded
+ * 0xfe00_0000	32M    FLASH
  */
-#define CFG_DBAT6L      ((CFG_FLASH_BASE & 0xfe000000) | BATL_PP_RW \
+#define CFG_DBAT6L	((CFG_FLASH_BASE & 0xfe000000) | BATL_PP_RW \
 			| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_DBAT6U      ((CFG_FLASH_BASE & 0xfe000000) | BATU_BL_32M | BATU_VS | BATU_VP)
-#define CFG_IBAT6L      ((CFG_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE)
-#define CFG_IBAT6U      CFG_DBAT6U
+#define CFG_DBAT6U	((CFG_FLASH_BASE & 0xfe000000) | BATU_BL_32M | BATU_VS | BATU_VP)
+#define CFG_IBAT6L	((CFG_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CFG_IBAT6U	CFG_DBAT6U
 
 #define CFG_DBAT7L 0x00000000
 #define CFG_DBAT7U 0x00000000
@@ -557,7 +557,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
  * Miscellaneous configurable options
  */
 #define CFG_LONGHELP			/* undef to save memory	*/
-#define CONFIG_CMDLINE_EDITING          /* Command-line editing */
+#define CONFIG_CMDLINE_EDITING		/* Command-line editing */
 #define CFG_LOAD_ADDR	0x2000000	/* default load address */
 #define CFG_PROMPT	"=> "		/* Monitor Command Prompt */
 
@@ -598,7 +598,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 
 /* The mac addresses for all ethernet interface */
 #if defined(CONFIG_TSEC_ENET)
-#define CONFIG_ETHADDR   00:E0:0C:00:00:01
+#define CONFIG_ETHADDR	 00:E0:0C:00:00:01
 #define CONFIG_ETH1ADDR  00:E0:0C:00:01:FD
 #define CONFIG_ETH2ADDR  00:E0:0C:00:02:FD
 #define CONFIG_ETH3ADDR  00:E0:0C:00:03:FD
@@ -624,45 +624,45 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_LOADADDR		1000000
 
 #define CONFIG_BOOTDELAY 10	/* -1 disables auto-boot */
-#undef  CONFIG_BOOTARGS		/* the boot command will set bootargs */
+#undef	CONFIG_BOOTARGS		/* the boot command will set bootargs */
 
 #define CONFIG_BAUDRATE	115200
 
-#define	CONFIG_EXTRA_ENV_SETTINGS				        \
-   "netdev=eth0\0"                                                      \
-   "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" 				\
-   "tftpflash=tftpboot $loadaddr $uboot; " 			\
-	"protect off " MK_STR(TEXT_BASE) " +$filesize; " 	\
-	"erase " MK_STR(TEXT_BASE) " +$filesize; " 		\
-	"cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " 	\
-	"protect on " MK_STR(TEXT_BASE) " +$filesize; " 	\
-	"cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" 	\
-   "consoledev=ttyS0\0"                                                 \
-   "ramdiskaddr=2000000\0"						\
-   "ramdiskfile=your.ramdisk.u-boot\0"                                  \
-   "fdtaddr=c00000\0"						\
-   "fdtfile=mpc8641_hpcn.dtb\0"                                  \
-   "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \
-   "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \
-   "maxcpus=2"
-
-
-#define CONFIG_NFSBOOTCOMMAND	                                        \
-   "setenv bootargs root=/dev/nfs rw "                                  \
-      "nfsroot=$serverip:$rootpath "                                    \
-      "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
-      "console=$consoledev,$baudrate $othbootargs;"                     \
-   "tftp $loadaddr $bootfile;"                                          \
-   "tftp $fdtaddr $fdtfile;"                                          \
-   "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND \
-   "setenv bootargs root=/dev/ram rw "                                  \
-      "console=$consoledev,$baudrate $othbootargs;"                     \
-   "tftp $ramdiskaddr $ramdiskfile;"                                    \
-   "tftp $loadaddr $bootfile;"                                          \
-   "tftp $fdtaddr $fdtfile;"                                          \
-   "bootm $loadaddr $ramdiskaddr $fdtaddr"
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"				\
+	"tftpflash=tftpboot $loadaddr $uboot; "				\
+		"protect off " MK_STR(TEXT_BASE) " +$filesize; "	\
+		"erase " MK_STR(TEXT_BASE) " +$filesize; "		\
+		"cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; "	\
+		"protect on " MK_STR(TEXT_BASE) " +$filesize; "		\
+		"cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0"	\
+	"consoledev=ttyS0\0"						\
+	"ramdiskaddr=2000000\0"						\
+	"ramdiskfile=your.ramdisk.u-boot\0"				\
+	"fdtaddr=c00000\0"						\
+	"fdtfile=mpc8641_hpcn.dtb\0"					\
+	"en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \
+	"dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \
+	"maxcpus=2"
+
+
+#define CONFIG_NFSBOOTCOMMAND						\
+	"setenv bootargs root=/dev/nfs rw "				\
+	      "nfsroot=$serverip:$rootpath "				\
+	      "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+	      "console=$consoledev,$baudrate $othbootargs;"		\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND						\
+	"setenv bootargs root=/dev/ram rw "				\
+	      "console=$consoledev,$baudrate $othbootargs;"		\
+	"tftp $ramdiskaddr $ramdiskfile;"				\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
 
 #define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
 
diff --git a/include/configs/MPC86xADS.h b/include/configs/MPC86xADS.h
index 831cc5ecd3..e0e8554811 100644
--- a/include/configs/MPC86xADS.h
+++ b/include/configs/MPC86xADS.h
@@ -22,7 +22,7 @@
 #define CONFIG_FADS		1       /* We are FADS compatible (more or less) */
 
 /* CPU type - pick one of these */
-#define CONFIG_MPC866T 		1
+#define CONFIG_MPC866T		1
 #undef CONFIG_MPC866P
 #undef CONFIG_MPC859T
 #undef CONFIG_MPC859DSL
diff --git a/include/configs/MUSENKI.h b/include/configs/MUSENKI.h
index f8cf01e5d3..4319e6c04c 100644
--- a/include/configs/MUSENKI.h
+++ b/include/configs/MUSENKI.h
@@ -86,7 +86,7 @@
  * PCI stuff
  *-----------------------------------------------------------------------
  */
-#define CONFIG_PCI      		/* include pci support          */
+#define CONFIG_PCI			/* include pci support          */
 #undef CONFIG_PCI_PNP
 
 #define CONFIG_NET_MULTI		/* Multi ethernet cards support */
diff --git a/include/configs/MVBLUE.h b/include/configs/MVBLUE.h
index d799f54f6a..d08d79520c 100644
--- a/include/configs/MVBLUE.h
+++ b/include/configs/MVBLUE.h
@@ -28,16 +28,16 @@
 #define MV_VERSION	"v0.2.0"
 
 /* LED0 = Power , LED1 = Error , LED2-5 = error code, LED6-7=00 -->PPCBoot error */
-#define ERR_NONE			0
-#define ERR_ENV 			1
-#define ERR_BOOTM_BADMAGIC 	2
-#define ERR_BOOTM_BADCRC   	3
-#define ERR_BOOTM_GUNZIP   	4
+#define ERR_NONE		0
+#define ERR_ENV			1
+#define ERR_BOOTM_BADMAGIC	2
+#define ERR_BOOTM_BADCRC	3
+#define ERR_BOOTM_GUNZIP	4
 #define ERR_BOOTP_TIMEOUT	5
-#define ERR_DHCP			6
-#define ERR_TFTP			7
-#define ERR_NOLAN 			8
-#define ERR_LANDRV 			9
+#define ERR_DHCP		6
+#define ERR_TFTP		7
+#define ERR_NOLAN		8
+#define ERR_LANDRV		9
 
 #define CONFIG_BOARD_TYPES	1
 #define MVBLUE_BOARD_BOX	1
@@ -45,10 +45,10 @@
 
 #if 0
 #define ERR_LED(code)	do { if (code) \
-								*(volatile char *)(0xff000003) = ( 3 | (code<<4) ) & 0xf3; \
-							 else \
-								*(volatile char *)(0xff000003) = ( 1 ); \
-						} while(0)
+		*(volatile char *)(0xff000003) = ( 3 | (code<<4) ) & 0xf3; \
+	else \
+		*(volatile char *)(0xff000003) = ( 1 ); \
+} while(0)
 #else
 #define ERR_LED(code)
 #endif
@@ -116,19 +116,19 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP		/* undef to save memory		*/
-#define CFG_PROMPT	"=> "	/* Monitor Command Prompt	*/
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
 
-#define CFG_PBSIZE		(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
-#define CFG_MAXARGS		16			/* Max number of command args	*/
+#define CFG_PBSIZE	(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
+#define CFG_MAXARGS	16		/* Max number of command args	*/
 #define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
 #define CFG_LOAD_ADDR	0x00100000	/* Default load address			*/
 
-#define CONFIG_BOOTCOMMAND  	"run nfsboot"
+#define CONFIG_BOOTCOMMAND	"run nfsboot"
 #define CONFIG_BOOTARGS			"root=/dev/mtdblock5 ro rootfstype=jffs2"
 
-#define CONFIG_NFSBOOTCOMMAND  	"bootp; run nfsargs addcons;bootm"
+#define CONFIG_NFSBOOTCOMMAND	"bootp; run nfsargs addcons;bootm"
 
 #define CONFIG_EXTRA_ENV_SETTINGS			\
 	"console_nr=0\0"				\
@@ -156,11 +156,11 @@
 #define CONFIG_PCI_SCAN_SHOW
 
 #define CONFIG_NET_MULTI
-#define CONFIG_NET_RETRY_COUNT 5
+#define CONFIG_NET_RETRY_COUNT		5
 
 #define CONFIG_TULIP
 #define CONFIG_TULIP_FIX_DAVICOM	1
-#define CONFIG_ETHADDR      		b6:b4:45:eb:fb:c0
+#define CONFIG_ETHADDR			b6:b4:45:eb:fb:c0
 
 #define CONFIG_HW_WATCHDOG
 
@@ -224,7 +224,7 @@
  */
 
 #define CONFIG_SYS_CLK_FREQ  33000000
-#define CFG_HZ		     	 10000
+#define CFG_HZ			 10000
 
 /* Bit-field values for MCCR1.  */
 #define CFG_ROMNAL      7
diff --git a/include/configs/MVS1.h b/include/configs/MVS1.h
index 75efd1e0e4..87458e3624 100644
--- a/include/configs/MVS1.h
+++ b/include/configs/MVS1.h
@@ -43,16 +43,19 @@
 #undef	CONFIG_8xx_CONS_SMC1		/* Console is *NOT* on SMC1	*/
 #define	CONFIG_8xx_CONS_SMC2	1	/* Console is on SMC2		*/
 #undef	CONFIG_8xx_CONS_NONE
-#define CONFIG_BAUDRATE		115200	/* console baudrate 		*/
+#define CONFIG_BAUDRATE		115200	/* console baudrate		*/
 #define CONFIG_BOOTDELAY	5	/* autoboot after this many seconds	*/
 
-#define CONFIG_PREBOOT		"echo;echo To mount root over NFS use \"run bootnet\";echo To mount root from FLASH use  \"run bootflash\";echo"
+#define CONFIG_PREBOOT		"echo;" \
+				"echo To mount root over NFS use \"run bootnet\";" \
+				"echo To mount root from FLASH use  \"run bootflash\";" \
+				"echo"
 #define	CONFIG_BOOTARGS		"root=/dev/mtdblock2 rw"
-#define CONFIG_BOOTCOMMAND						\
-    "bootp; "                               				\
-    "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
-    "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "   \
-    "bootm"
+#define CONFIG_BOOTCOMMAND							\
+	"bootp; "								\
+	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "	\
+	"bootm"
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
 #undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
@@ -61,7 +64,7 @@
 
 #undef	CONFIG_STATUS_LED		/* Status LED disabled/enabled	*/
 
-#undef  CONFIG_CAN_DRIVER       /* CAN Driver support disabled  */
+#undef	CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/
 
 
 /*
@@ -100,9 +103,9 @@
 #undef	CFG_LONGHELP			/* undef to save memory		*/
 #define	CFG_PROMPT		"=> "	/* Monitor Command Prompt	*/
 
-#undef  CFG_HUSH_PARSER			/* Hush parse for U-Boot ?? */
-#ifdef  CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2     "> "
+#undef	CFG_HUSH_PARSER			/* Hush parse for U-Boot ?? */
+#ifdef	CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2	"> "
 #endif
 
 #if defined(CONFIG_CMD_KGDB)
@@ -193,7 +196,7 @@
  */
 #if defined(CONFIG_WATCHDOG)
 #define CFG_SYPCR   (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
-	     SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+	     SYPCR_SWE	| SYPCR_SWRI| SYPCR_SWP)
 #else
 #define CFG_SYPCR   (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 #endif
@@ -267,8 +270,8 @@
 
 #define	CONFIG_IDE_PCCARD	0	/* **DON'T** Use IDE with PC Card Adapter	*/
 
-#undef	CONFIG_IDE_PCMCIA		/* Direct IDE    not supported	*/
-#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
+#undef	CONFIG_IDE_PCMCIA		/* Direct IDE	 not supported	*/
+#undef	CONFIG_IDE_LED			/* LED	 for ide not supported	*/
 #undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
 
 #define CFG_IDE_MAXBUS		0	/* max. no. of IDE buses			*/
diff --git a/include/configs/NC650.h b/include/configs/NC650.h
index 5346545d32..0b094827d7 100644
--- a/include/configs/NC650.h
+++ b/include/configs/NC650.h
@@ -76,12 +76,12 @@
 
 #undef	CONFIG_BOOTARGS
 #define CONFIG_BOOTCOMMAND							\
-	"bootp;" 								\
-	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " 	\
-	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" 	\
+	"bootp;"								\
+	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;"	\
 	"bootm"
 
-#define CONFIG_WATCHDOG			/* watchdog enabled 		*/
+#define CONFIG_WATCHDOG			/* watchdog enabled		*/
 
 #undef	CONFIG_STATUS_LED		/* Status LED disabled		*/
 
@@ -175,7 +175,7 @@
 #define CFG_MEMTEST_START	0x0100000	/* memtest works on	*/
 #define CFG_MEMTEST_END		0x0400000	/* 1 ... 4 MB in DRAM	*/
 
-#define CFG_LOAD_ADDR	 	0x00100000
+#define CFG_LOAD_ADDR		0x00100000
 
 #define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
 
diff --git a/include/configs/NETPHONE.h b/include/configs/NETPHONE.h
index e3c6fd333b..27e7ab9bce 100644
--- a/include/configs/NETPHONE.h
+++ b/include/configs/NETPHONE.h
@@ -66,7 +66,7 @@
 
 #undef	CONFIG_BOOTARGS
 #define CONFIG_BOOTCOMMAND							\
-	"tftpboot; " 								\
+	"tftpboot; "								\
 	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
 	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;"	\
 	"bootm"
@@ -97,7 +97,7 @@
 
 #define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
 
-#define	CONFIG_NET_MULTI	1 	/* the only way to get the FEC in */
+#define	CONFIG_NET_MULTI	1	/* the only way to get the FEC in */
 #define	FEC_ENET		1	/* eth.c needs it that way... */
 #undef CFG_DISCOVER_PHY
 #define CONFIG_MII		1
@@ -105,7 +105,7 @@
 #define CONFIG_RMII		1	/* use RMII interface */
 
 #define CONFIG_ETHER_ON_FEC1	1
-#define CONFIG_FEC1_PHY		8 	/* phy address of FEC */
+#define CONFIG_FEC1_PHY		8	/* phy address of FEC */
 #define CONFIG_FEC1_PHY_NORXERR 1
 
 #define CONFIG_ETHER_ON_FEC2	1
@@ -292,27 +292,27 @@
 #if MPC8XX_HZ == 120000000
 #define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
 			 (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
-		 	 PLPRCR_TEXPS)
+			 PLPRCR_TEXPS)
 #elif MPC8XX_HZ == 100000000
 #define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
 			 (0 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
-		 	 PLPRCR_TEXPS)
+			 PLPRCR_TEXPS)
 #elif MPC8XX_HZ == 50000000
 #define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
 			 (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \
-		 	 PLPRCR_TEXPS)
+			 PLPRCR_TEXPS)
 #elif MPC8XX_HZ == 25000000
 #define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
 			 (2 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \
-		 	 PLPRCR_TEXPS)
+			 PLPRCR_TEXPS)
 #elif MPC8XX_HZ == 40000000
 #define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
 			 (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
-		 	 PLPRCR_TEXPS)
+			 PLPRCR_TEXPS)
 #elif MPC8XX_HZ == 75000000
 #define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
 			 (1 << PLPRCR_S_SHIFT) | (15 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
-		 	 PLPRCR_TEXPS)
+			 PLPRCR_TEXPS)
 #else
 #error unsupported CPU freq for XIN = 10MHz
 #endif
@@ -322,15 +322,15 @@
 #if MPC8XX_HZ == 120000000
 #define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
 			 (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
-		 	 PLPRCR_TEXPS)
+			 PLPRCR_TEXPS)
 #elif MPC8XX_HZ == 100000000
 #define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
 			 (0 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \
-		 	 PLPRCR_TEXPS)
+			 PLPRCR_TEXPS)
 #elif MPC8XX_HZ ==  66666666
 #define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
 			 (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \
-		 	 PLPRCR_TEXPS)
+			 PLPRCR_TEXPS)
 #else
 #error unsupported CPU freq for XIN = 50MHz
 #endif
@@ -514,7 +514,7 @@
 #define ADDR_COLUMN		1
 #define ADDR_PAGE		2
 #define ADDR_COLUMN_PAGE	3
-#define NAND_ChipID_UNKNOWN 	0x00
+#define NAND_ChipID_UNKNOWN	0x00
 #define NAND_MAX_FLOORS		1
 #define NAND_MAX_CHIPS		1
 
diff --git a/include/configs/NETTA.h b/include/configs/NETTA.h
index 20404a394f..56c76d3258 100644
--- a/include/configs/NETTA.h
+++ b/include/configs/NETTA.h
@@ -64,7 +64,7 @@
 
 #undef	CONFIG_BOOTARGS
 #define CONFIG_BOOTCOMMAND							\
-	"tftpboot; " 								\
+	"tftpboot; "								\
 	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
 	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;"	\
 	"bootm"
@@ -93,7 +93,7 @@
 
 #define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
 
-#define	CONFIG_NET_MULTI	1 	/* the only way to get the FEC in */
+#define	CONFIG_NET_MULTI	1	/* the only way to get the FEC in */
 #define	FEC_ENET		1	/* eth.c needs it that way... */
 #undef  CFG_DISCOVER_PHY		/* do not discover phys */
 #define CONFIG_MII		1
@@ -102,15 +102,15 @@
 
 #if defined(CONFIG_NETTA_ISDN)
 #define CONFIG_ETHER_ON_FEC1	1
-#define CONFIG_FEC1_PHY		1   	/* phy address of FEC1 */
+#define CONFIG_FEC1_PHY		1	/* phy address of FEC1 */
 #define CONFIG_FEC1_PHY_NORXERR 1
 #undef  CONFIG_ETHER_ON_FEC2
 #else
 #define CONFIG_ETHER_ON_FEC1	1
-#define CONFIG_FEC1_PHY		8  	/* phy address of FEC1 */
+#define CONFIG_FEC1_PHY		8	/* phy address of FEC1 */
 #define CONFIG_FEC1_PHY_NORXERR 1
 #define CONFIG_ETHER_ON_FEC2	1
-#define CONFIG_FEC2_PHY		1   	/* phy address of FEC2 */
+#define CONFIG_FEC2_PHY		1	/* phy address of FEC2 */
 #define CONFIG_FEC2_PHY_NORXERR 1
 #endif
 
@@ -296,27 +296,27 @@
 #if MPC8XX_HZ == 120000000
 #define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
 			 (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
-		 	 PLPRCR_TEXPS)
+			 PLPRCR_TEXPS)
 #elif MPC8XX_HZ == 100000000
 #define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
 			 (0 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
-		 	 PLPRCR_TEXPS)
+			 PLPRCR_TEXPS)
 #elif MPC8XX_HZ == 50000000
 #define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
 			 (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \
-		 	 PLPRCR_TEXPS)
+			 PLPRCR_TEXPS)
 #elif MPC8XX_HZ == 25000000
 #define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
 			 (2 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \
-		 	 PLPRCR_TEXPS)
+			 PLPRCR_TEXPS)
 #elif MPC8XX_HZ == 40000000
 #define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
 			 (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
-		 	 PLPRCR_TEXPS)
+			 PLPRCR_TEXPS)
 #elif MPC8XX_HZ == 75000000
 #define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
 			 (1 << PLPRCR_S_SHIFT) | (15 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
-		 	 PLPRCR_TEXPS)
+			 PLPRCR_TEXPS)
 #else
 #error unsupported CPU freq for XIN = 10MHz
 #endif
@@ -326,19 +326,19 @@
 #if MPC8XX_HZ == 120000000
 #define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
 			 (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
-		 	 PLPRCR_TEXPS)
+			 PLPRCR_TEXPS)
 #elif MPC8XX_HZ == 100000000
 #define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
 			 (0 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \
-		 	 PLPRCR_TEXPS)
+			 PLPRCR_TEXPS)
 #elif MPC8XX_HZ ==  80000000
 #define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
 			 (0 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
-		 	 PLPRCR_TEXPS)
+			 PLPRCR_TEXPS)
 #elif MPC8XX_HZ ==  50000000
 #define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
 			 (1 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \
-		 	 PLPRCR_TEXPS)
+			 PLPRCR_TEXPS)
 #else
 #error unsupported CPU freq for XIN = 50MHz
 #endif
@@ -633,7 +633,7 @@
 #define ADDR_COLUMN		1
 #define ADDR_PAGE		2
 #define ADDR_COLUMN_PAGE	3
-#define NAND_ChipID_UNKNOWN 	0x00
+#define NAND_ChipID_UNKNOWN	0x00
 #define NAND_MAX_FLOORS		1
 #define NAND_MAX_CHIPS		1
 
diff --git a/include/configs/NETTA2.h b/include/configs/NETTA2.h
index cf66e04702..b8c48482ac 100644
--- a/include/configs/NETTA2.h
+++ b/include/configs/NETTA2.h
@@ -66,9 +66,9 @@
 
 #undef	CONFIG_BOOTARGS
 #define CONFIG_BOOTCOMMAND							\
-	"tftpboot; " 								\
-	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " 	\
-	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " 	\
+	"tftpboot; "								\
+	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "	\
 	"bootm"
 
 #define CONFIG_AUTOSCRIPT
@@ -98,7 +98,7 @@
 
 #define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
 
-#define	CONFIG_NET_MULTI	1 	/* the only way to get the FEC in */
+#define	CONFIG_NET_MULTI	1	/* the only way to get the FEC in */
 #define	FEC_ENET		1	/* eth.c needs it that way... */
 #undef CFG_DISCOVER_PHY
 #define CONFIG_MII		1
@@ -106,7 +106,7 @@
 #define CONFIG_RMII		1	/* use RMII interface */
 
 #define CONFIG_ETHER_ON_FEC1	1
-#define CONFIG_FEC1_PHY		8 	/* phy address of FEC */
+#define CONFIG_FEC1_PHY		8	/* phy address of FEC */
 #define CONFIG_FEC1_PHY_NORXERR 1
 
 #define CONFIG_ETHER_ON_FEC2	1
@@ -293,27 +293,27 @@
 #if MPC8XX_HZ == 120000000
 #define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
 			 (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
-		 	 PLPRCR_TEXPS)
+			 PLPRCR_TEXPS)
 #elif MPC8XX_HZ == 100000000
 #define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
 			 (0 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
-		 	 PLPRCR_TEXPS)
+			 PLPRCR_TEXPS)
 #elif MPC8XX_HZ == 50000000
 #define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
 			 (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \
-		 	 PLPRCR_TEXPS)
+			 PLPRCR_TEXPS)
 #elif MPC8XX_HZ == 25000000
 #define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
 			 (2 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \
-		 	 PLPRCR_TEXPS)
+			 PLPRCR_TEXPS)
 #elif MPC8XX_HZ == 40000000
 #define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
 			 (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
-		 	 PLPRCR_TEXPS)
+			 PLPRCR_TEXPS)
 #elif MPC8XX_HZ == 75000000
 #define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
 			 (1 << PLPRCR_S_SHIFT) | (15 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
-		 	 PLPRCR_TEXPS)
+			 PLPRCR_TEXPS)
 #else
 #error unsupported CPU freq for XIN = 10MHz
 #endif
@@ -323,15 +323,15 @@
 #if MPC8XX_HZ == 120000000
 #define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
 			 (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
-		 	 PLPRCR_TEXPS)
+			 PLPRCR_TEXPS)
 #elif MPC8XX_HZ == 100000000
 #define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
 			 (0 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \
-		 	 PLPRCR_TEXPS)
+			 PLPRCR_TEXPS)
 #elif MPC8XX_HZ ==  66666666
 #define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
 			 (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \
-		 	 PLPRCR_TEXPS)
+			 PLPRCR_TEXPS)
 #else
 #error unsupported CPU freq for XIN = 50MHz
 #endif
@@ -515,7 +515,7 @@
 #define ADDR_COLUMN		1
 #define ADDR_PAGE		2
 #define ADDR_COLUMN_PAGE	3
-#define NAND_ChipID_UNKNOWN 	0x00
+#define NAND_ChipID_UNKNOWN	0x00
 #define NAND_MAX_FLOORS		1
 #define NAND_MAX_CHIPS		1
 
diff --git a/include/configs/NETVIA.h b/include/configs/NETVIA.h
index af5339ee00..1293fb0e2b 100644
--- a/include/configs/NETVIA.h
+++ b/include/configs/NETVIA.h
@@ -63,9 +63,9 @@
 
 #undef	CONFIG_BOOTARGS
 #define CONFIG_BOOTCOMMAND							\
-	"tftpboot; " 								\
-	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " 	\
-	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " 	\
+	"tftpboot; "								\
+	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "	\
 	"bootm"
 
 #define CONFIG_LOADS_ECHO	0	/* echo off for serial download	*/
@@ -411,7 +411,7 @@
 #define ADDR_COLUMN		1
 #define ADDR_PAGE		2
 #define ADDR_COLUMN_PAGE	3
-#define NAND_ChipID_UNKNOWN 	0x00
+#define NAND_ChipID_UNKNOWN	0x00
 #define NAND_MAX_FLOORS		1
 #define NAND_MAX_CHIPS		1
 
diff --git a/include/configs/NSCU.h b/include/configs/NSCU.h
index 3929a846bc..11e5c63ed3 100644
--- a/include/configs/NSCU.h
+++ b/include/configs/NSCU.h
@@ -295,8 +295,8 @@
 #define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
 #define CFG_PCMCIA_IO_ADDR	(0xEC000000)
 #define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
-#define PCMCIA_MEM_WIN_NO 	8 /* override default 4 in pcmcia.h */
-#define	PCMCIA_SOCKETS_NO 	2 /* we have two sockets */
+#define PCMCIA_MEM_WIN_NO	8 /* override default 4 in pcmcia.h */
+#define	PCMCIA_SOCKETS_NO	2 /* we have two sockets */
 #undef	NSCU_OE_INV		/* PCMCIA_GCRX_CXOE was inverted on early boards */
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/NX823.h b/include/configs/NX823.h
index da1c173a43..2a4bd4724c 100644
--- a/include/configs/NX823.h
+++ b/include/configs/NX823.h
@@ -127,7 +127,7 @@
  */
 #define CFG_SDRAM_BASE		0x00000000
 #define CFG_FLASH_BASE		0x40000000
-#define CFG_MONITOR_LEN 	(128 << 10)	/* Reserve 128 kB for Monitor	*/
+#define CFG_MONITOR_LEN		(128 << 10)	/* Reserve 128 kB for Monitor	*/
 #define CFG_MONITOR_BASE	CFG_FLASH_BASE
 #define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
 
diff --git a/include/configs/P3G4.h b/include/configs/P3G4.h
index e85e1b91fc..5a2d157705 100644
--- a/include/configs/P3G4.h
+++ b/include/configs/P3G4.h
@@ -42,7 +42,7 @@
 #define CONFIG_P3G4		1	/* this is a P3G4  board	*/
 #define CFG_GT_6426x        GT_64260 /* with a 64260 system controller */
 
-#define CONFIG_BAUDRATE		115200 	/* console baudrate = 115200	*/
+#define CONFIG_BAUDRATE		115200	/* console baudrate = 115200	*/
 
 #undef	CONFIG_ECC			/* enable ECC support */
 /* #define CONFIG_EVB64260_750CX  1 */      /* Support the EVB-64260-750CX Board */
@@ -417,8 +417,8 @@
 
 #define CFG_L2
 
-#define L2_INIT  	(L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
-			L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
+#define L2_INIT		(L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
+			 L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
 
 #define L2_ENABLE	(L2_INIT | L2CR_L2E)
 
diff --git a/include/configs/PATI.h b/include/configs/PATI.h
index 0de7591da6..4b37eca7ce 100644
--- a/include/configs/PATI.h
+++ b/include/configs/PATI.h
@@ -32,7 +32,7 @@
  */
 
 #define CONFIG_MPC555		1		/* This is an MPC555 CPU		*/
-#define CONFIG_PATI		1		/* ...On a PATI board 	*/
+#define CONFIG_PATI		1		/* ...On a PATI board	*/
 /* Serial Console Configuration */
 #define	CONFIG_5xx_CONS_SCI1
 #undef	CONFIG_5xx_CONS_SCI2
@@ -74,11 +74,11 @@
 #else
 #define CONFIG_BOOTDELAY	5		/* autoboot after 5 seconds		*/
 #endif
-#define CONFIG_BOOTCOMMAND	"" 	/* autoboot command			*/
+#define CONFIG_BOOTCOMMAND	""	/* autoboot command			*/
 
 #define CONFIG_BOOTARGS		""		/* */
 
-#define CONFIG_WATCHDOG				/* turn on platform specific watchdog 	*/
+#define CONFIG_WATCHDOG				/* turn on platform specific watchdog	*/
 
 /*#define CONFIG_STATUS_LED	1		*/ /* Enable status led */
 
@@ -123,30 +123,30 @@
 /*
  * Internal Memory Mapped (This is not the IMMR content)
  */
-#define CFG_IMMR		0x01C00000				/* Physical start adress of internal memory map */
+#define CFG_IMMR		0x01C00000		/* Physical start adress of internal memory map */
 
 /*
  * Definitions for initial stack pointer and data area
  */
-#define CFG_INIT_RAM_ADDR	(CFG_IMMR + 0x003f9800)      		/* Physical start adress of internal MPC555 writable RAM */
-#define	CFG_INIT_RAM_END	(CFG_IMMR + 0x003fffff)       		/* Physical end adress of internal MPC555 used RAM area	*/
-#define	CFG_GBL_DATA_SIZE	128					/* Size in bytes reserved for initial global data */
+#define CFG_INIT_RAM_ADDR	(CFG_IMMR + 0x003f9800)	/* Physical start adress of internal MPC555 writable RAM */
+#define	CFG_INIT_RAM_END	(CFG_IMMR + 0x003fffff)	/* Physical end adress of internal MPC555 used RAM area	*/
+#define	CFG_GBL_DATA_SIZE	128			/* Size in bytes reserved for initial global data */
 #define CFG_GBL_DATA_OFFSET	((CFG_INIT_RAM_END - CFG_INIT_RAM_ADDR) - CFG_GBL_DATA_SIZE) /* Offset from the beginning of ram */
-#define	CFG_INIT_SP_ADDR	(CFG_IMMR + 0x03fa000)			/* Physical start adress of inital stack */
+#define	CFG_INIT_SP_ADDR	(CFG_IMMR + 0x03fa000)	/* Physical start adress of inital stack */
 /*
  * Start addresses for the final memory configuration
  * Please note that CFG_SDRAM_BASE _must_ start at 0
  */
-#define	CFG_SDRAM_BASE		0x00000000	/* Monitor won't change memory map 			*/
+#define	CFG_SDRAM_BASE		0x00000000	/* Monitor won't change memory map			*/
 #define CFG_FLASH_BASE		0xffC00000	/* External flash */
 #define PCI_BASE		0x03000000	/* PCI Base (CS2) */
 #define PCI_CONFIG_BASE		0x04000000	/* PCI & PLD  (CS3) */
 #define PLD_CONFIG_BASE		0x04001000	/* PLD  (CS3) */
 
 #define	CFG_MONITOR_BASE	0xFFF00000
-/* CFG_FLASH_BASE	*/ /* TEXT_BASE is defined in the board config.mk file. 	*/
-						/* This adress is given to the linker with -Ttext to 	*/
-						/* locate the text section at this adress. 		*/
+/* CFG_FLASH_BASE	*/ /* TEXT_BASE is defined in the board config.mk file.	*/
+						/* This adress is given to the linker with -Ttext to	*/
+						/* locate the text section at this adress.		*/
 #define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 192 kB for Monitor				*/
 #define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()				*/
 
@@ -167,9 +167,9 @@
  */
 
 #define CFG_MAX_FLASH_BANKS		1		/* Max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT		128		/* Max number of sectors on one chip 	*/
-#define CFG_FLASH_ERASE_TOUT	180000		/* Timeout for Flash Erase (in ms) 	*/
-#define CFG_FLASH_WRITE_TOUT	600		/* Timeout for Flash Write (in ms) 	*/
+#define CFG_MAX_FLASH_SECT		128		/* Max number of sectors on one chip	*/
+#define CFG_FLASH_ERASE_TOUT	180000		/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	600		/* Timeout for Flash Write (in ms)	*/
 
 
 #define	CFG_ENV_IS_IN_EEPROM
@@ -180,8 +180,8 @@
 
 #undef  CFG_ENV_IS_IN_FLASH
 #ifdef	CFG_ENV_IS_IN_FLASH
-#define	CFG_ENV_SIZE		0x00002000		/* Set whole sector as env 		*/
-#define CFG_ENV_OFFSET		((0 - CFG_FLASH_BASE) - CFG_ENV_SIZE) 		/* Environment starts at this adress 	*/
+#define	CFG_ENV_SIZE		0x00002000		/* Set whole sector as env		*/
+#define CFG_ENV_OFFSET		((0 - CFG_FLASH_BASE) - CFG_ENV_SIZE)		/* Environment starts at this adress	*/
 #endif
 
 
@@ -233,7 +233,7 @@
  *-----------------------------------------------------------------------
  * Data show cycle
  */
-#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_EARB | SIUMCR_GPC01 | SIUMCR_MLRC11) /* Disable data show cycle 	*/
+#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_EARB | SIUMCR_GPC01 | SIUMCR_MLRC11) /* Disable data show cycle	*/
 
 /*-----------------------------------------------------------------------
  * PLPRCR - PLL, Low-Power, and Reset Control Register
@@ -241,7 +241,7 @@
  * Set all bits to 40 Mhz
  *
  */
-#define CFG_OSC_CLK   	((uint)4000000) 	/* Oscillator clock is 4MHz 	*/
+#define CFG_OSC_CLK	((uint)4000000)		/* Oscillator clock is 4MHz	*/
 
 
 #define CFG_PLPRCR	(PLPRCR_MF_9 | PLPRCR_DIVF_0)
@@ -251,12 +251,12 @@
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_UMCR	(UMCR_FSPEED) 		/* IMB clock same as U-bus 	*/
+#define CFG_UMCR	(UMCR_FSPEED)		/* IMB clock same as U-bus	*/
 
 /*-----------------------------------------------------------------------
  * ICTRL - I-Bus Support Control Register
  */
-#define CFG_ICTRL	(ICTRL_ISCT_SER_7) 	/* Take out of serialized mode 	*/
+#define CFG_ICTRL	(ICTRL_ISCT_SER_7)	/* Take out of serialized mode	*/
 
 /*-----------------------------------------------------------------------
  * USIU - Memory Controller Register
diff --git a/include/configs/PCI5441.h b/include/configs/PCI5441.h
index 24b25d9850..abb9bfc25c 100644
--- a/include/configs/PCI5441.h
+++ b/include/configs/PCI5441.h
@@ -54,10 +54,10 @@
 
 /*------------------------------------------------------------------------
  * MEMORY ORGANIZATION
- * 	-Monitor at top.
- * 	-The heap is placed below the monitor.
- * 	-Global data is placed below the heap.
- * 	-The stack is placed below global data (&grows down).
+ *	-Monitor at top.
+ *	-The heap is placed below the monitor.
+ *	-Global data is placed below the heap.
+ *	-The stack is placed below global data (&grows down).
  *----------------------------------------------------------------------*/
 #define CFG_MONITOR_LEN		(128 * 1024)	/* Reserve 128k		*/
 #define CFG_GBL_DATA_SIZE	128		/* Global data size rsvd*/
@@ -87,7 +87,7 @@
 #define	CFG_ENV_IS_IN_FLASH	1		/* Environment in flash */
 #define CFG_ENV_SIZE		(64 * 1024)	/* 64 KByte (1 sector)	*/
 #define CONFIG_ENV_OVERWRITE			/* Serial change Ok	*/
-#define CFG_ENV_ADDR 	(CFG_RESET_ADDR + CFG_MONITOR_LEN)
+#define CFG_ENV_ADDR	(CFG_RESET_ADDR + CFG_MONITOR_LEN)
 
 /*------------------------------------------------------------------------
  * CONSOLE
@@ -155,8 +155,8 @@
 #define	CFG_LONGHELP				/* Provide extended help*/
 #define	CFG_PROMPT		"==> "		/* Command prompt	*/
 #define	CFG_CBSIZE		256		/* Console I/O buf size	*/
-#define	CFG_MAXARGS		16	    	/* Max command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE 	/* Boot arg buf size	*/
+#define	CFG_MAXARGS		16		/* Max command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot arg buf size	*/
 #define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print buf size	*/
 #define	CFG_LOAD_ADDR		CFG_SDRAM_BASE	/* Default load address	*/
 #define CFG_MEMTEST_START	CFG_SDRAM_BASE	/* Start addr for test	*/
diff --git a/include/configs/PIP405.h b/include/configs/PIP405.h
index b83520d7c1..5890012b4e 100644
--- a/include/configs/PIP405.h
+++ b/include/configs/PIP405.h
@@ -123,7 +123,7 @@
 #define CONFIG_BOOTDELAY	5
 /* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
 /* #define CONFIG_BOOT_RETRY_TIME	-10	/XXX* feature is available but not enabled */
-#define CONFIG_ZERO_BOOTDELAY_CHECK  	/* check console even if bootdelay = 0 */
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check console even if bootdelay = 0 */
 
 
 #define CONFIG_BOOTCOMMAND	"diskboot 400000 0:1; bootm" /* autoboot command		*/
@@ -252,7 +252,7 @@
 #define CFG_TEMP_STACK_OCM	1
 #define CFG_OCM_DATA_ADDR	0xF0000000
 #define CFG_OCM_DATA_SIZE	0x1000
-#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR 	/* inside of On Chip SRAM    */
+#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR	/* inside of On Chip SRAM    */
 #define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE	/* End of On Chip SRAM	       */
 #define CFG_GBL_DATA_SIZE	64		/* size in bytes reserved for initial data */
 #define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
diff --git a/include/configs/PM520.h b/include/configs/PM520.h
index ad480a6c9e..6eb6444925 100644
--- a/include/configs/PM520.h
+++ b/include/configs/PM520.h
@@ -159,7 +159,7 @@
 /*
  * IPB Bus clocking configuration.
  */
-#undef CFG_IPBCLK_EQUALS_XLBCLK   		/* define for 133MHz speed */
+#undef CFG_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
 #endif
 /*
  * I2C configuration
diff --git a/include/configs/PM826.h b/include/configs/PM826.h
index cf7314ddb4..36e9aa56ea 100644
--- a/include/configs/PM826.h
+++ b/include/configs/PM826.h
@@ -47,9 +47,9 @@
 
 #undef	CONFIG_BOOTARGS
 #define CONFIG_BOOTCOMMAND							\
-	"bootp; " 								\
-	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " 	\
-	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " 	\
+	"bootp; "								\
+	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "	\
 	"bootm"
 
 /* enable I2C and select the hardware/software driver */
diff --git a/include/configs/PM856.h b/include/configs/PM856.h
index 38a26dc8aa..9355aafa61 100644
--- a/include/configs/PM856.h
+++ b/include/configs/PM856.h
@@ -43,7 +43,7 @@
 #define CONFIG_PM856		1	/* PM856 board specific */
 
 #define CONFIG_PCI
-#define CONFIG_TSEC_ENET 		/* tsec ethernet support */
+#define CONFIG_TSEC_ENET		/* tsec ethernet support */
 #define CONFIG_ENV_OVERWRITE
 #undef  CONFIG_SPD_EEPROM		/* do not use SPD EEPROM for DDR setup*/
 #define CONFIG_DDR_ECC			/* only for ECC DDR module */
@@ -92,7 +92,7 @@
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  */
-#define CFG_CCSRBAR_DEFAULT 	0xff700000	/* CCSRBAR Default */
+#define CFG_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
 #define CFG_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
 #define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */
@@ -141,7 +141,7 @@
 #define CFG_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
 #define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
 
-#define CFG_MONITOR_BASE    	TEXT_BASE	/* start of monitor */
+#define CFG_MONITOR_BASE	TEXT_BASE	/* start of monitor */
 
 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
 #define CFG_RAMBOOT
@@ -167,16 +167,16 @@
 
 
 #define CONFIG_L1_INIT_RAM
-#define CFG_INIT_RAM_LOCK 	1
+#define CFG_INIT_RAM_LOCK	1
 #define CFG_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
-#define CFG_INIT_RAM_END    	0x4000	    	/* End of used area in RAM */
+#define CFG_INIT_RAM_END	0x4000		/* End of used area in RAM */
 
-#define CFG_GBL_DATA_SIZE  	128		/* num bytes initial data */
+#define CFG_GBL_DATA_SIZE	128		/* num bytes initial data */
 #define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 #define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
 
-#define CFG_MONITOR_LEN	    	(512 * 1024)    /* Reserve 512 kB for Mon */
-#define CFG_MALLOC_LEN	    	(128 * 1024)    /* Reserved for malloc */
+#define CFG_MONITOR_LEN		(512 * 1024)    /* Reserve 512 kB for Mon */
+#define CFG_MALLOC_LEN		(128 * 1024)    /* Reserved for malloc */
 
 /* Serial Port */
 #define CONFIG_CONS_ON_SCC	/* define if console on SCC */
@@ -236,7 +236,7 @@
 #if defined(CONFIG_PCI)
 
 #define CONFIG_NET_MULTI
-#define CONFIG_PCI_PNP	               	/* do pci plug-and-play */
+#define CONFIG_PCI_PNP			/* do pci plug-and-play */
 
 #undef CONFIG_EEPRO100
 #undef CONFIG_TULIP
@@ -244,7 +244,7 @@
 #if !defined(CONFIG_PCI_PNP)
     #define PCI_ENET0_IOADDR	0xe0000000
     #define PCI_ENET0_MEMADDR	0xe0000000
-    #define PCI_IDSEL_NUMBER	0x0c 	/* slot0->3(IDSEL)=12->15 */
+    #define PCI_IDSEL_NUMBER	0x0c	/* slot0->3(IDSEL)=12->15 */
 #endif
 
 #undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
@@ -256,7 +256,7 @@
 #if defined(CONFIG_TSEC_ENET)
 
 #ifndef CONFIG_NET_MULTI
-#define CONFIG_NET_MULTI 	1
+#define CONFIG_NET_MULTI	1
 #endif
 
 #define CONFIG_MII		1	/* MII PHY management */
diff --git a/include/configs/PN62.h b/include/configs/PN62.h
index 72acf5ae8d..da7d8b82b1 100644
--- a/include/configs/PN62.h
+++ b/include/configs/PN62.h
@@ -73,7 +73,7 @@
 #define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
 
 #define CONFIG_SERVERIP		10.0.0.201
-#define CONFIG_IPADDR 		10.0.0.200
+#define CONFIG_IPADDR		10.0.0.200
 #define CONFIG_ROOTPATH		/opt/eldk/ppc_82xx
 #define CONFIG_NETMASK		255.255.255.0
 #undef CONFIG_BOOTARGS
@@ -81,7 +81,7 @@
 /* Boot Linux with NFS root filesystem */
 #define CONFIG_BOOTCOMMAND \
 			"setenv verify y;" \
-       			"setenv bootargs console=ttyS0,19200 mem=31M quiet " \
+			"setenv bootargs console=ttyS0,19200 mem=31M quiet " \
 			"root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
 			"ip=${ipaddr}:${serverip}::${netmask}:pn62:eth0:off;" \
 			"loadp 100000; bootm"
@@ -90,7 +90,7 @@
 /* Boot Linux with RAMdisk based filesystem (initrd, BusyBox) */
 #define CONFIG_BOOTCOMMAND \
 			"setenv verify n;" \
-       			"setenv bootargs console=ttyS0,19200 mem=31M quiet " \
+			"setenv bootargs console=ttyS0,19200 mem=31M quiet " \
 			"root=/dev/ram rw " \
 			"ip=${ipaddr}:${serverip}::${netmask}:pn62:eth0:off;" \
 			"loadp 200000; bootm"
@@ -128,7 +128,7 @@
 /*
  * Networking stuff
  */
-#define CONFIG_NET_MULTI       			/* Multi ethernet cards support */
+#define CONFIG_NET_MULTI			/* Multi ethernet cards support */
 
 #define CONFIG_PCNET				/* there are 2 AMD PCnet 79C973	*/
 #define CONFIG_PCNET_79C973
@@ -153,9 +153,9 @@
 /*#define CFG_GBL_DATA_SIZE    256*/
 #define CFG_GBL_DATA_SIZE	128
 
-#define CFG_INIT_RAM_ADDR   	0x40000000
-#define CFG_INIT_RAM_END    	0x1000
-#define CFG_GBL_DATA_OFFSET 	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_RAM_ADDR	0x40000000
+#define CFG_INIT_RAM_END	0x1000
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 
 
 #define CFG_NO_FLASH		1		/* There is no FLASH memory	*/
diff --git a/include/configs/QS823.h b/include/configs/QS823.h
index 3dd84e8c57..cef9f42dfd 100644
--- a/include/configs/QS823.h
+++ b/include/configs/QS823.h
@@ -492,12 +492,12 @@
 
 /* For boards with 16M of SDRAM */
 #define SDRAM_16M_MAX_SIZE	0x01000000	/* max 16MB SDRAM */
-#define CFG_16M_MAMR 		(vMAMR_PTA | MAMR_AMA_TYPE_0 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A11 |\
+#define CFG_16M_MAMR		(vMAMR_PTA | MAMR_AMA_TYPE_0 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A11 |\
 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
 
 /* For boards with 32M of SDRAM */
 #define SDRAM_32M_MAX_SIZE	0x02000000	/* max 32MB SDRAM */
-#define CFG_32M_MAMR 		(vMAMR_PTA | MAMR_AMA_TYPE_1 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A10 |\
+#define CFG_32M_MAMR		(vMAMR_PTA | MAMR_AMA_TYPE_1 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A10 |\
 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
 
 
diff --git a/include/configs/QS850.h b/include/configs/QS850.h
index 7dd6eca9ca..ba5827a22d 100644
--- a/include/configs/QS850.h
+++ b/include/configs/QS850.h
@@ -492,12 +492,12 @@
 
 /* For boards with 16M of SDRAM */
 #define SDRAM_16M_MAX_SIZE	0x01000000	/* max 16MB SDRAM */
-#define CFG_16M_MAMR 		(vMAMR_PTA | MAMR_AMA_TYPE_0 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A11 |\
+#define CFG_16M_MAMR		(vMAMR_PTA | MAMR_AMA_TYPE_0 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A11 |\
 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
 
 /* For boards with 32M of SDRAM */
 #define SDRAM_32M_MAX_SIZE	0x02000000	/* max 32MB SDRAM */
-#define CFG_32M_MAMR 		(vMAMR_PTA | MAMR_AMA_TYPE_1 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A10 |\
+#define CFG_32M_MAMR		(vMAMR_PTA | MAMR_AMA_TYPE_1 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A10 |\
 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
 
 
diff --git a/include/configs/R360MPI.h b/include/configs/R360MPI.h
index f4aecfc0bd..a653cca96f 100644
--- a/include/configs/R360MPI.h
+++ b/include/configs/R360MPI.h
@@ -62,9 +62,9 @@
 
 #undef	CONFIG_BOOTARGS
 #define CONFIG_BOOTCOMMAND							\
-	"bootp; " 								\
-	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " 	\
-	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " 	\
+	"bootp; "								\
+	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "	\
 	"bootm"
 
 #undef	CONFIG_SCC1_ENET
diff --git a/include/configs/RBC823.h b/include/configs/RBC823.h
index e3c75617ec..9222d21554 100644
--- a/include/configs/RBC823.h
+++ b/include/configs/RBC823.h
@@ -65,9 +65,9 @@
 
 #undef	CONFIG_BOOTARGS
 #define CONFIG_BOOTCOMMAND							\
-	"bootp; " 								\
-	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " 	\
-	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " 	\
+	"bootp; "								\
+	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "	\
 	"bootm"
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
diff --git a/include/configs/RPXClassic.h b/include/configs/RPXClassic.h
index 793b1db889..706e2aadc7 100644
--- a/include/configs/RPXClassic.h
+++ b/include/configs/RPXClassic.h
@@ -78,9 +78,9 @@
 
 #undef	CONFIG_BOOTARGS
 #define CONFIG_BOOTCOMMAND							\
-	"tftpboot; " 								\
-	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " 	\
-	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " 	\
+	"tftpboot; "								\
+	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "	\
 	"bootm"
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
@@ -467,7 +467,7 @@
 #define BCSR3 0xFA400003
 
 #define BCSR0_ENMONXCVR	0x01	/* Monitor XVCR Control */
-#define BCSR0_ENNVRAM	0x02 	/* CS4# Control */
+#define BCSR0_ENNVRAM	0x02	/* CS4# Control */
 #define BCSR0_LED5		0x04	/* LED5 control 0='on' 1='off' */
 #define BCSR0_LED4		0x08	/* LED4 control 0='on' 1='off' */
 #define BCSR0_FULLDPLX	0x10	/* Ethernet XCVR Control */
diff --git a/include/configs/RPXlite.h b/include/configs/RPXlite.h
index 3c5e6b8913..671094b69d 100644
--- a/include/configs/RPXlite.h
+++ b/include/configs/RPXlite.h
@@ -51,9 +51,9 @@
 
 #undef	CONFIG_BOOTARGS
 #define CONFIG_BOOTCOMMAND							\
-	"bootp; " 								\
-	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " 	\
-	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " 	\
+	"bootp; "								\
+	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "	\
 	"bootm"
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
@@ -156,7 +156,7 @@
 #define	CFG_DIRECT_FLASH_TFTP
 
 #define	CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_SECT_SIZE	0x40000 	/* We use one complete sector	*/
+#define CFG_ENV_SECT_SIZE	0x40000	/* We use one complete sector		*/
 #define CFG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
 
 #define CONFIG_ENV_OVERWRITE
@@ -361,7 +361,7 @@
 #define BCSR3 0xFA400003
 
 #define BCSR0_ENMONXCVR	0x01	/* Monitor XVCR Control */
-#define BCSR0_ENNVRAM	0x02 	/* CS4# Control */
+#define BCSR0_ENNVRAM	0x02	/* CS4# Control */
 #define BCSR0_LED5	0x04	/* LED5 control 0='on' 1='off' */
 #define BCSR0_LED4	0x08	/* LED4 control 0='on' 1='off' */
 #define BCSR0_FULLDPLX	0x10	/* Ethernet XCVR Control */
diff --git a/include/configs/RRvision.h b/include/configs/RRvision.h
index 32e2285454..6a71801935 100644
--- a/include/configs/RRvision.h
+++ b/include/configs/RRvision.h
@@ -119,7 +119,7 @@
 
 /* enable I2C and select the hardware/software driver */
 #undef	CONFIG_HARD_I2C			/* I2C with hardware support	*/
-#define	CONFIG_SOFT_I2C         	/* I2C bit-banged		*/
+#define	CONFIG_SOFT_I2C			/* I2C bit-banged		*/
 
 # define CFG_I2C_SPEED		50000	/* 50 kHz is supposed to work	*/
 # define CFG_I2C_SLAVE		0xFE
diff --git a/include/configs/Rattler.h b/include/configs/Rattler.h
index 428c0c2b59..01ebc8f6e0 100644
--- a/include/configs/Rattler.h
+++ b/include/configs/Rattler.h
@@ -250,13 +250,13 @@
 /* Hard reset configuration word */
 #define CFG_HRCW_MASTER		0x0A06875A /* Not used - provided by FPGA */
 /* No slaves */
-#define CFG_HRCW_SLAVE1 	0
-#define CFG_HRCW_SLAVE2 	0
-#define CFG_HRCW_SLAVE3 	0
-#define CFG_HRCW_SLAVE4 	0
-#define CFG_HRCW_SLAVE5 	0
-#define CFG_HRCW_SLAVE6 	0
-#define CFG_HRCW_SLAVE7 	0
+#define CFG_HRCW_SLAVE1		0
+#define CFG_HRCW_SLAVE2		0
+#define CFG_HRCW_SLAVE3		0
+#define CFG_HRCW_SLAVE4		0
+#define CFG_HRCW_SLAVE5		0
+#define CFG_HRCW_SLAVE6		0
+#define CFG_HRCW_SLAVE7		0
 
 #define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH */
 #define BOOTFLAG_WARM		0x02	/* Software reboot                  */
diff --git a/include/configs/SBC8540.h b/include/configs/SBC8540.h
index 946b3c2d8a..ff64378f20 100644
--- a/include/configs/SBC8540.h
+++ b/include/configs/SBC8540.h
@@ -48,7 +48,7 @@
 
 #define CONFIG_CPM2		1	/* has CPM2 */
 
-#define CONFIG_SBC8540      	1   	/* configuration for SBC8560 board */
+#define CONFIG_SBC8540		1	/* configuration for SBC8560 board */
 
 #define CONFIG_MPC8560ADS	1	/* MPC8560ADS board specific (supplement)	*/
 
diff --git a/include/configs/SCM.h b/include/configs/SCM.h
index bc5389fe8a..febfc39263 100644
--- a/include/configs/SCM.h
+++ b/include/configs/SCM.h
@@ -67,9 +67,9 @@
 
 #undef	CONFIG_BOOTARGS
 #define CONFIG_BOOTCOMMAND							\
-	"bootp; " 								\
-	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " 	\
-	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " 	\
+	"bootp; "								\
+	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "	\
 	"bootm"
 
 /* enable I2C and select the hardware/software driver */
@@ -165,7 +165,7 @@
  * - Enable Full Duplex in FSMR
  */
 # define CFG_CMXFCR_MASK	(CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
-# define CFG_CMXFCR_VALUE 	(CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
+# define CFG_CMXFCR_VALUE	(CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
 # define CFG_CPMFCR_RAMTYPE	0
 # define CFG_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
 
diff --git a/include/configs/SL8245.h b/include/configs/SL8245.h
index 4d9d41b927..31853c8de3 100644
--- a/include/configs/SL8245.h
+++ b/include/configs/SL8245.h
@@ -90,10 +90,10 @@
  * (Set up by the startup code)
  * Please note that CFG_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE	    	0x00000000
+#define CFG_SDRAM_BASE		0x00000000
 
 #define CFG_FLASH_BASE0_PRELIM	0xFF800000	/* FLASH bank on RCS#0 */
-#define CFG_FLASH_BASE 		CFG_FLASH_BASE0_PRELIM
+#define CFG_FLASH_BASE		CFG_FLASH_BASE0_PRELIM
 #define CFG_FLASH_BANKS		{ CFG_FLASH_BASE0_PRELIM }
 
 #define CFG_RESET_ADDRESS   0xFFF00100
diff --git a/include/configs/SM850.h b/include/configs/SM850.h
index 41a54f0f5a..465db4735f 100644
--- a/include/configs/SM850.h
+++ b/include/configs/SM850.h
@@ -54,9 +54,9 @@
 
 #undef	CONFIG_BOOTARGS
 #define CONFIG_BOOTCOMMAND							\
-	"bootp; " 								\
-	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " 	\
-	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " 	\
+	"bootp; "								\
+	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "	\
 	"bootm"
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
diff --git a/include/configs/SXNI855T.h b/include/configs/SXNI855T.h
index 8f2a5ece2c..3aee45c3c7 100644
--- a/include/configs/SXNI855T.h
+++ b/include/configs/SXNI855T.h
@@ -204,7 +204,7 @@
 #define ADDR_PAGE 2
 #define ADDR_COLUMN_PAGE 3
 
-#define NAND_ChipID_UNKNOWN 	0x00
+#define NAND_ChipID_UNKNOWN	0x00
 #define NAND_MAX_FLOORS 1
 #define NAND_MAX_CHIPS 1
 
@@ -250,7 +250,7 @@
 #define CFG_MEMTEST_START	0x0100000	/* memtest works on	*/
 #define CFG_MEMTEST_END		0x0400000	/* 1 ... 4 MB in DRAM	*/
 
-#define CFG_LOAD_ADDR	 	0x00100000
+#define CFG_LOAD_ADDR		0x00100000
 
 #define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
 
diff --git a/include/configs/TOP5200.h b/include/configs/TOP5200.h
index 1affcfdebb..71fa36baae 100644
--- a/include/configs/TOP5200.h
+++ b/include/configs/TOP5200.h
@@ -176,7 +176,7 @@
 /*
  * IPB Bus clocking configuration.
  */
-#undef CFG_IPBCLK_EQUALS_XLBCLK   		/* define for 133MHz speed */
+#undef CFG_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
 
 /*
  * I2C configuration
diff --git a/include/configs/TOP860.h b/include/configs/TOP860.h
index 8237ba1af3..151c407c84 100644
--- a/include/configs/TOP860.h
+++ b/include/configs/TOP860.h
@@ -201,10 +201,10 @@
  * defines we need to get FEC running
  */
 #define	CONFIG_NET_MULTI	1	/* the only way to get the FEC in */
-#define CONFIG_FEC_ENET 	1	/* Ethernet only via FEC	*/
-#define	FEC_ENET			1	/* eth.c needs it that way... */
+#define CONFIG_FEC_ENET		1	/* Ethernet only via FEC	*/
+#define	FEC_ENET		1	/* eth.c needs it that way... */
 #define CFG_DISCOVER_PHY	1
-#define CONFIG_MII			1
+#define CONFIG_MII		1
 #define CONFIG_MII_INIT		1
 #define CONFIG_PHY_ADDR		31
 
@@ -287,7 +287,7 @@
  *-----------------------------------------------------------------------
  * set up SYPCR:
  *	16	SWTC	0xffff		Software watchdog timer count
- *	8	BMT		0xff 		Bus monitor timing
+ *	8	BMT		0xff		Bus monitor timing
  *	1	BME		1			Bus monitor enable
  *	3	0		000
  *	1	SWF		1			Software watchdog freeze
@@ -297,7 +297,7 @@
  */
 #if defined (CONFIG_WATCHDOG)
  #define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
-			 		 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+					 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 #else
  #define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF)
 #endif
diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h
index 02a16ac0a6..a86939e097 100644
--- a/include/configs/TQM834x.h
+++ b/include/configs/TQM834x.h
@@ -176,7 +176,7 @@ extern int tqm834x_num_flash_banks;
 #define CFG_INIT_RAM_ADDR	0x20000000	/* Initial RAM address */
 #define CFG_INIT_RAM_END	0x1000		/* End of used area in RAM*/
 
-#define CFG_GBL_DATA_SIZE  	0x100		/* num bytes initial data */
+#define CFG_GBL_DATA_SIZE	0x100		/* num bytes initial data */
 #define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 #define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
 
@@ -231,7 +231,7 @@ extern int tqm834x_num_flash_banks;
 /*
  * TSEC
  */
-#define CONFIG_TSEC_ENET 		/* tsec ethernet support */
+#define CONFIG_TSEC_ENET		/* tsec ethernet support */
 #define CONFIG_MII
 
 #define CFG_TSEC1_OFFSET	0x24000
diff --git a/include/configs/Total5200.h b/include/configs/Total5200.h
index 2507d77776..31f10dd87c 100644
--- a/include/configs/Total5200.h
+++ b/include/configs/Total5200.h
@@ -178,7 +178,7 @@
 /*
  * IPB Bus clocking configuration.
  */
-#undef CFG_IPBCLK_EQUALS_XLBCLK   		/* define for 133MHz speed */
+#undef CFG_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
 #endif
 
 /*
diff --git a/include/configs/VCMA9.h b/include/configs/VCMA9.h
index df6894f324..ad8db613ec 100644
--- a/include/configs/VCMA9.h
+++ b/include/configs/VCMA9.h
@@ -44,7 +44,7 @@
 #define USE_920T_MMU		1
 #undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff	*/
 
-#define CONFIG_CMDLINE_TAG	 1	/* enable passing of ATAGs    	*/
+#define CONFIG_CMDLINE_TAG	 1	/* enable passing of ATAGs	*/
 #define CONFIG_SETUP_MEMORY_TAGS 1
 #define CONFIG_INITRD_TAG	 1
 
@@ -84,8 +84,8 @@
  * address 0x50 with 16bit addressing
  ***********************************************************/
 #define CONFIG_HARD_I2C			/* I2C with hardware support */
-#define CFG_I2C_SPEED 		100000	/* I2C speed */
-#define CFG_I2C_SLAVE 		0x7F	/* I2C slave addr */
+#define CFG_I2C_SPEED		100000	/* I2C speed */
+#define CFG_I2C_SLAVE		0x7F	/* I2C slave addr */
 
 #define CFG_I2C_EEPROM_ADDR	0x50
 #define CFG_I2C_EEPROM_ADDR_LEN	2
@@ -111,7 +111,7 @@
  */
 #define CONFIG_DRIVER_CS8900	1		/* we have a CS8900 on-board */
 #define CS8900_BASE		0x20000300
-#define CS8900_BUS16		1 		/* the Linux driver does accesses as shorts */
+#define CS8900_BUS16		1		/* the Linux driver does accesses as shorts */
 
 #define CONFIG_DRIVER_S3C24X0_I2C	1	/* we use the buildin I2C controller */
 
@@ -145,7 +145,7 @@
 #define CONFIG_BOOTDELAY	5
 /* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
 /* #define CONFIG_BOOT_RETRY_TIME	-10	/XXX* feature is available but not enabled */
-#define CONFIG_ZERO_BOOTDELAY_CHECK  	/* check console even if bootdelay = 0 */
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check console even if bootdelay = 0 */
 
 #define CONFIG_NETMASK          255.255.255.0
 #define CONFIG_IPADDR		10.0.0.110
@@ -262,7 +262,7 @@
 #define ADDR_PAGE 2
 #define ADDR_COLUMN_PAGE 3
 
-#define NAND_ChipID_UNKNOWN 	0x00
+#define NAND_ChipID_UNKNOWN	0x00
 #define NAND_MAX_FLOORS 1
 #define NAND_MAX_CHIPS 1
 
diff --git a/include/configs/VoVPN-GW.h b/include/configs/VoVPN-GW.h
index 14057847b8..db05d82bfc 100644
--- a/include/configs/VoVPN-GW.h
+++ b/include/configs/VoVPN-GW.h
@@ -369,7 +369,7 @@
 /*
  * MEMORY MAP
  * ----------
- * CS0 - FLASH    8MB/8Bit 	base=0xff800000 (boot: 0xfe000000, 8x mirrored)
+ * CS0 - FLASH    8MB/8Bit	base=0xff800000 (boot: 0xfe000000, 8x mirrored)
  * CS1 - SDRAM   32MB/64Bit	base=0x00000000
  * CS2 - DSP/SL1  1MB/16Bit	base=0xf0100000
  * CS3 - DSP/SL2  1MB/16Bit	base=0xf0200000
diff --git a/include/configs/W7OLMC.h b/include/configs/W7OLMC.h
index 7017fff5de..bb6b6b9d26 100644
--- a/include/configs/W7OLMC.h
+++ b/include/configs/W7OLMC.h
@@ -154,10 +154,10 @@
 #define CFG_PCI_SUBSYS_DEVICEID 0x0156		/* PCI Device ID: 405GP		*/
 #define CFG_PCI_PTM1LA		0x00000000	/* point to sdram		*/
 #define CFG_PCI_PTM1MS		0x80000001	/* 2GB, enable hard-wired to 1	*/
-#define CFG_PCI_PTM1PCI 	0x00000000      /* Host: use this pci address   */
-#define CFG_PCI_PTM2LA		0x00000000	/* disabled		*/
-#define CFG_PCI_PTM2MS		0x00000000	/* disabled		*/
-#define CFG_PCI_PTM2PCI 	0x00000000      /* Host: use this pci address   */
+#define CFG_PCI_PTM1PCI		0x00000000      /* Host: use this pci address   */
+#define CFG_PCI_PTM2LA		0x00000000	/* disabled			*/
+#define CFG_PCI_PTM2MS		0x00000000	/* disabled			*/
+#define CFG_PCI_PTM2PCI		0x00000000      /* Host: use this pci address   */
 
 /*-----------------------------------------------------------------------
  * Set up values for external bus controller
diff --git a/include/configs/W7OLMG.h b/include/configs/W7OLMG.h
index bfb3156f6f..3050cafa1d 100644
--- a/include/configs/W7OLMG.h
+++ b/include/configs/W7OLMG.h
@@ -161,10 +161,10 @@
 #define CFG_PCI_SUBSYS_DEVICEID 0x0156		/* PCI Device ID: 405GP		*/
 #define CFG_PCI_PTM1LA		0x00000000	/* point to sdram		*/
 #define CFG_PCI_PTM1MS		0x80000001	/* 2GB, enable hard-wired to 1	*/
-#define CFG_PCI_PTM1PCI 	0x00000000      /* Host: use this pci address   */
-#define CFG_PCI_PTM2LA		0x00000000	/* disabled		*/
-#define CFG_PCI_PTM2MS		0x00000000	/* disabled		*/
-#define CFG_PCI_PTM2PCI 	0x00000000      /* Host: use this pci address   */
+#define CFG_PCI_PTM1PCI		0x00000000      /* Host: use this pci address   */
+#define CFG_PCI_PTM2LA		0x00000000	/* disabled			*/
+#define CFG_PCI_PTM2MS		0x00000000	/* disabled			*/
+#define CFG_PCI_PTM2PCI		0x00000000      /* Host: use this pci address   */
 
 /*-----------------------------------------------------------------------
  * Set up values for external bus controller
diff --git a/include/configs/ZPC1900.h b/include/configs/ZPC1900.h
index 7c1a5b9e88..b04be766f5 100644
--- a/include/configs/ZPC1900.h
+++ b/include/configs/ZPC1900.h
@@ -200,13 +200,13 @@
 				 HRCW_MODCK_H0111                          \
 				) /* 0x16848207 */
 /* No slaves */
-#define CFG_HRCW_SLAVE1 	0
-#define CFG_HRCW_SLAVE2 	0
-#define CFG_HRCW_SLAVE3 	0
-#define CFG_HRCW_SLAVE4 	0
-#define CFG_HRCW_SLAVE5 	0
-#define CFG_HRCW_SLAVE6 	0
-#define CFG_HRCW_SLAVE7 	0
+#define CFG_HRCW_SLAVE1		0
+#define CFG_HRCW_SLAVE2		0
+#define CFG_HRCW_SLAVE3		0
+#define CFG_HRCW_SLAVE4		0
+#define CFG_HRCW_SLAVE5		0
+#define CFG_HRCW_SLAVE6		0
+#define CFG_HRCW_SLAVE7		0
 
 #define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH */
 #define BOOTFLAG_WARM		0x02	/* Software reboot                  */
diff --git a/include/configs/ads5121.h b/include/configs/ads5121.h
index 81e7c1e4db..c975a249c7 100644
--- a/include/configs/ads5121.h
+++ b/include/configs/ads5121.h
@@ -45,14 +45,25 @@
  */
 #define CONFIG_E300		1	/* E300 Family */
 #define CONFIG_MPC512X		1	/* MPC512X family */
+#define CONFIG_FSL_DIU_FB	1	/* FSL DIU */
+
+/* video */
+#undef CONFIG_VIDEO
+
+#if defined(CONFIG_VIDEO)
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#endif
 
 /* CONFIG_PCI is defined at config time */
 
 #define CFG_MPC512X_CLKIN	66000000	/* in Hz */
 
 #define CONFIG_BOARD_EARLY_INIT_F		/* call board_early_init_f() */
+#define CONFIG_MISC_INIT_R
 
 #define CFG_IMMR		0x80000000
+#define CFG_DIU_ADDR		(CFG_IMMR+0x2100)
 
 #define CFG_MEMTEST_START	0x00200000      /* memtest region */
 #define CFG_MEMTEST_END		0x00400000
@@ -127,28 +138,28 @@
 #define CFG_MICRON_OCD_DEFAULT	0x01010780
 
 /* DDR Priority Manager Configuration */
-#define CFG_MDDRCGRP_PM_CFG1	0x000777AA
-#define CFG_MDDRCGRP_PM_CFG2	0x00000055
-#define CFG_MDDRCGRP_HIPRIO_CFG	0x00000000
-#define CFG_MDDRCGRP_LUT0_MU    0x11111117
-#define CFG_MDDRCGRP_LUT0_ML	0x7777777A
-#define CFG_MDDRCGRP_LUT1_MU    0x4444EEEE
-#define CFG_MDDRCGRP_LUT1_ML	0xEEEEEEEE
-#define CFG_MDDRCGRP_LUT2_MU    0x44444444
+#define CFG_MDDRCGRP_PM_CFG1	0x00077777
+#define CFG_MDDRCGRP_PM_CFG2	0x00000000
+#define CFG_MDDRCGRP_HIPRIO_CFG	0x00000001
+#define CFG_MDDRCGRP_LUT0_MU	0xFFEEDDCC
+#define CFG_MDDRCGRP_LUT0_ML	0xBBAAAAAA
+#define CFG_MDDRCGRP_LUT1_MU	0x66666666
+#define CFG_MDDRCGRP_LUT1_ML	0x55555555
+#define CFG_MDDRCGRP_LUT2_MU	0x44444444
 #define CFG_MDDRCGRP_LUT2_ML	0x44444444
-#define CFG_MDDRCGRP_LUT3_MU    0x55555555
+#define CFG_MDDRCGRP_LUT3_MU	0x55555555
 #define CFG_MDDRCGRP_LUT3_ML	0x55555558
-#define CFG_MDDRCGRP_LUT4_MU    0x11111111
-#define CFG_MDDRCGRP_LUT4_ML	0x1111117C
-#define CFG_MDDRCGRP_LUT0_AU    0x33333377
-#define CFG_MDDRCGRP_LUT0_AL	0x7777EEEE
-#define CFG_MDDRCGRP_LUT1_AU    0x11111111
-#define CFG_MDDRCGRP_LUT1_AL	0x11111111
-#define CFG_MDDRCGRP_LUT2_AU    0x11111111
+#define CFG_MDDRCGRP_LUT4_MU	0x11111111
+#define CFG_MDDRCGRP_LUT4_ML	0x11111122
+#define CFG_MDDRCGRP_LUT0_AU	0xaaaaaaaa
+#define CFG_MDDRCGRP_LUT0_AL	0xaaaaaaaa
+#define CFG_MDDRCGRP_LUT1_AU	0x66666666
+#define CFG_MDDRCGRP_LUT1_AL	0x66666666
+#define CFG_MDDRCGRP_LUT2_AU	0x11111111
 #define CFG_MDDRCGRP_LUT2_AL	0x11111111
-#define CFG_MDDRCGRP_LUT3_AU    0x11111111
+#define CFG_MDDRCGRP_LUT3_AU	0x11111111
 #define CFG_MDDRCGRP_LUT3_AL	0x11111111
-#define CFG_MDDRCGRP_LUT4_AU    0x11111111
+#define CFG_MDDRCGRP_LUT4_AU	0x11111111
 #define CFG_MDDRCGRP_LUT4_AL	0x11111111
 
 /*
@@ -161,7 +172,7 @@
 #define CFG_FLASH_USE_BUFFER_WRITE
 
 #define CFG_MAX_FLASH_BANKS	1		/* number of banks */
-#define CFG_FLASH_BANKS_LIST 	{CFG_FLASH_BASE}
+#define CFG_FLASH_BANKS_LIST	{CFG_FLASH_BASE}
 #define CFG_MAX_FLASH_SECT	256		/* max sectors per device */
 
 #undef CFG_FLASH_CHECKSUM
@@ -189,7 +200,11 @@
 
 #define CFG_MONITOR_BASE	TEXT_BASE		/* Start of monitor */
 #define CFG_MONITOR_LEN		(256 * 1024)		/* Reserve 256 kB for Mon */
-#define CFG_MALLOC_LEN		(512 * 1024)		/* Reserved for malloc */
+#ifdef	CONFIG_FSL_DIU_FB
+#define CFG_MALLOC_LEN		(6 * 1024 * 1024)	/* Reserved for malloc */
+#else
+#define CFG_MALLOC_LEN		(512 * 1024)
+#endif
 
 /*
  * Serial Port
diff --git a/include/configs/adsvix.h b/include/configs/adsvix.h
index 703d3124e6..427b5482f5 100644
--- a/include/configs/adsvix.h
+++ b/include/configs/adsvix.h
@@ -359,7 +359,7 @@
 /* Flash environment locations */
 #define CFG_ENV_IS_IN_FLASH	1
 #define CFG_ENV_ADDR		(PHYS_FLASH_1 + CFG_MONITOR_LEN)	/* Addr of Environment Sector	*/
-#define CFG_ENV_SIZE		0x20000	/* Total Size of Environment     	*/
+#define CFG_ENV_SIZE		0x20000	/* Total Size of Environment	*/
 #define CFG_ENV_SECT_SIZE	0x20000	/* Total Size of Environment Sector	*/
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/apollon.h b/include/configs/apollon.h
index 294cd26978..89732968ad 100755..100644
--- a/include/configs/apollon.h
+++ b/include/configs/apollon.h
@@ -174,7 +174,7 @@
 #define	CFG_MAXARGS	16	/* max number of command args */
 #define	CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
 
-#define	CFG_MEMTEST_START 	(OMAP2420_SDRC_CS0)	/* memtest works on */
+#define	CFG_MEMTEST_START	(OMAP2420_SDRC_CS0)	/* memtest works on */
 #define	CFG_MEMTEST_END		(OMAP2420_SDRC_CS0+SZ_31M)
 
 #undef	CFG_CLKS_IN_HZ	/* everything, incl board info, in Hz */
diff --git a/include/configs/armadillo.h b/include/configs/armadillo.h
index 73a88854b3..98a83db296 100644
--- a/include/configs/armadillo.h
+++ b/include/configs/armadillo.h
@@ -41,9 +41,9 @@
  * (easy to change)
  */
 #define CONFIG_ARM7		1	/* This is a ARM7 CPU	*/
-#define CONFIG_ARMADILLO 	1	/* on an Armadillo Board      */
+#define CONFIG_ARMADILLO	1	/* on an Armadillo Board      */
 #define CONFIG_ARM_THUMB	1	/* this is an ARM720TDMI */
-#undef  CONFIG_ARM7_REVD	 	/* disable ARM720 REV.D Workarounds */
+#undef  CONFIG_ARM7_REVD		/* disable ARM720 REV.D Workarounds */
 
 #undef CONFIG_USE_IRQ			/* don't need them anymore */
 
@@ -88,7 +88,7 @@
 
 
 #define CONFIG_BOOTDELAY	3
-#define CONFIG_BOOTARGS    	"root=/dev/ram0 rootfstype=ext2 console=ttyAM0,115200"
+#define CONFIG_BOOTARGS		"root=/dev/ram0 rootfstype=ext2 console=ttyAM0,115200"
 
 #define CONFIG_BOOTCOMMAND	"bootm 40000 180000"
 
diff --git a/include/configs/atc.h b/include/configs/atc.h
index 4ef50c23f0..285b4e4da0 100644
--- a/include/configs/atc.h
+++ b/include/configs/atc.h
@@ -111,7 +111,7 @@
 #define CONFIG_BOOTCOMMAND						\
 	"bootp;"							\
 	"setenv bootargs root=/dev/nfs rw "				\
-	"nfsroot=${serverip}:${rootpath} " 				\
+	"nfsroot=${serverip}:${rootpath} "				\
 	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;"\
 	"bootm"
 
@@ -182,9 +182,9 @@
 
 #define CONFIG_RTC_DS12887
 
-#define RTC_BASE_ADDR 		0xF5000000
-#define RTC_PORT_ADDR 		RTC_BASE_ADDR + 0x800
-#define RTC_PORT_DATA 		RTC_BASE_ADDR + 0x808
+#define RTC_BASE_ADDR		0xF5000000
+#define RTC_PORT_ADDR		RTC_BASE_ADDR + 0x800
+#define RTC_PORT_DATA		RTC_BASE_ADDR + 0x808
 
 #define CONFIG_MISC_INIT_R
 
diff --git a/include/configs/barco.h b/include/configs/barco.h
index 0bb446f784..4f57067db1 100644
--- a/include/configs/barco.h
+++ b/include/configs/barco.h
@@ -96,8 +96,8 @@
 
 
 #define CONFIG_HUSH_PARSER	1 /* use "hush" command parser */
-#define CONFIG_BOOTDELAY 	1
-#define CONFIG_BOOTCOMMAND 	"boot_default"
+#define CONFIG_BOOTDELAY	1
+#define CONFIG_BOOTCOMMAND	"boot_default"
 
 /*
  * Miscellaneous configurable options
@@ -135,9 +135,9 @@
 
 #define CONFIG_LOGBUFFER
 #ifdef	CONFIG_LOGBUFFER
-#define CFG_STDOUT_ADDR 	0x1FFC000
+#define CFG_STDOUT_ADDR		0x1FFC000
 #else
-#define CFG_STDOUT_ADDR 	0x2B9000
+#define CFG_STDOUT_ADDR		0x2B9000
 #endif
 
 #define CFG_RESET_ADDRESS	0xFFF00100
@@ -158,9 +158,9 @@
 
 #define CFG_GBL_DATA_SIZE	128
 
-#define CFG_INIT_RAM_ADDR     0x40000000
-#define CFG_INIT_RAM_END      0x1000
-#define CFG_GBL_DATA_OFFSET  (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_RAM_ADDR	0x40000000
+#define CFG_INIT_RAM_END	0x1000
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 
 #endif
 
diff --git a/include/configs/bf533-stamp.h b/include/configs/bf533-stamp.h
index 66a0af683d..d70aa1087c 100644
--- a/include/configs/bf533-stamp.h
+++ b/include/configs/bf533-stamp.h
@@ -25,7 +25,7 @@
 #define CONFIG_SMC91111_BASE	0x20300300
 
 /* FLASH/ETHERNET uses the same address range */
-#define SHARED_RESOURCES 	1
+#define SHARED_RESOURCES	1
 
 /* Is I2C bit-banged? */
 #define CONFIG_SOFT_I2C		1
@@ -112,7 +112,7 @@
 #endif
 
 #define	CFG_ENV_SIZE		0x2000
-#define CFG_ENV_SECT_SIZE 	0x2000	/* Total Size of Environment Sector */
+#define CFG_ENV_SECT_SIZE	0x2000	/* Total Size of Environment Sector */
 #define	ENV_IS_EMBEDDED
 
 #define CFG_FLASH_ERASE_TOUT	30000	/* Timeout for Chip Erase (in ms) */
@@ -123,7 +123,7 @@
 #define CFG_JFFS2_FIRST_BANK 0
 #define CFG_JFFS2_NUM_BANKS  1
 /* 512k reserved for u-boot */
-#define CFG_JFFS2_FIRST_SECTOR 	11
+#define CFG_JFFS2_FIRST_SECTOR	11
 
 /*
  * following timeouts shall be used once the
@@ -148,7 +148,7 @@
 #define CFG_MEMTEST_END		(CFG_MAX_RAM_SIZE - 0x80000 - 1)
 #define CONFIG_LOADADDR		0x01000000
 
-#define CFG_LOAD_ADDR 		CONFIG_LOADADDR
+#define CFG_LOAD_ADDR		CONFIG_LOADADDR
 #define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
 #define CFG_MALLOC_LEN		(128 << 10)     /* Reserve 128 kB for malloc()	*/
 #define CFG_GBL_DATA_SIZE	0x4000		/* Reserve 16k for Global Data  */
diff --git a/include/configs/bf537-stamp.h b/include/configs/bf537-stamp.h
index 39c7359d3e..a881d53289 100644
--- a/include/configs/bf537-stamp.h
+++ b/include/configs/bf537-stamp.h
@@ -103,11 +103,11 @@
 #define CFG_LONGHELP		1
 #define CONFIG_BOOTDELAY	5
 #define CONFIG_BOOT_RETRY_TIME	-1	/* Enable this if bootretry required, currently its disabled */
-#define CONFIG_BOOTCOMMAND 	"run ramboot"
+#define CONFIG_BOOTCOMMAND	"run ramboot"
 
 #if defined(CONFIG_POST_TEST)
 /* POST support */
-#define CONFIG_POST 		( CFG_POST_MEMORY | \
+#define CONFIG_POST		( CFG_POST_MEMORY | \
 				  CFG_POST_UART	  | \
 				  CFG_POST_FLASH  | \
 				  CFG_POST_ETHER  | \
@@ -208,7 +208,7 @@
 #else
 #define	CFG_CBSIZE		256	/* Console I/O Buffer Size */
 #endif
-#define CFG_MAX_RAM_SIZE       	(CONFIG_MEM_SIZE * 1024*1024)
+#define CFG_MAX_RAM_SIZE	(CONFIG_MEM_SIZE * 1024*1024)
 #define	CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
 #define	CFG_MAXARGS		16	/* max number of command args */
 #define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size */
@@ -281,10 +281,10 @@
 #define NAND_MAX_CHIPS		1
 #define BFIN_NAND_READY		PF3
 
-#define NAND_WAIT_READY(nand)  			\
-	do { 					\
-		int timeout = 0; 		\
-		while(!(*pPORTFIO & PF3)) 	\
+#define NAND_WAIT_READY(nand)			\
+	do {					\
+		int timeout = 0;		\
+		while(!(*pPORTFIO & PF3))	\
 			if (timeout++ > 100000)	\
 				break;		\
 	} while (0)
diff --git a/include/configs/bf561-ezkit.h b/include/configs/bf561-ezkit.h
index 641548dafd..e99e97924c 100644
--- a/include/configs/bf561-ezkit.h
+++ b/include/configs/bf561-ezkit.h
@@ -148,28 +148,27 @@
 
 #if (CONFIG_DRIVER_SMC91111)
 #define CONFIG_EXTRA_ENV_SETTINGS \
-	"ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" 		\
+	"ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0"	 \
 	"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):"	\
-		"$(rootpath) console=ttyBF0,57600\0"						\
+		"$(rootpath) console=ttyBF0,57600\0"			\
 	"addip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip):"	\
 		"$(gatewayip):$(netmask):$(hostname):eth0:off\0"	\
-	"ramboot=tftpboot $(loadaddr) linux; "		\
+	"ramboot=tftpboot $(loadaddr) linux; "				\
 		"run ramargs; run addip; bootelf\0"			\
-	"nfsboot=tftpboot $(loadaddr) linux; "		\
+	"nfsboot=tftpboot $(loadaddr) linux; "				\
 		"run nfsargs; run addip; bootelf\0"			\
-	"update=tftpboot $(loadaddr) u-boot.bin; "	\
+	"update=tftpboot $(loadaddr) u-boot.bin; "			\
 		"protect off 0x20000000 0x2003FFFF; "			\
 		"erase 0x20000000 0x2003FFFF; "				\
-		"cp.b $(loadaddr) 0x20000000 $(filesize)\0" \
+		"cp.b $(loadaddr) 0x20000000 $(filesize)\0"		\
 	""
 #else
 #define CONFIG_EXTRA_ENV_SETTINGS \
-	"ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0"		\
+	"ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0"	 \
 	"flashboot=bootm 0x20100000\0"					\
 	""
 #endif
 
-
 /*
  * BOOTP options
  */
@@ -178,7 +177,6 @@
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_HOSTNAME
 
-
 /*
  * Command line configuration.
  */
@@ -193,7 +191,6 @@
 #define CONFIG_CMD_DHCP
 #endif
 
-
 /*
  * Console settings
  */
diff --git a/include/configs/bubinga.h b/include/configs/bubinga.h
index cbd74a0d8d..75dd4e7e67 100644
--- a/include/configs/bubinga.h
+++ b/include/configs/bubinga.h
@@ -302,7 +302,7 @@
 #define CFG_FLASH_WORD_SIZE     unsigned char
 
 #ifdef CFG_ENV_IS_IN_FLASH
-#define CFG_ENV_SECT_SIZE	0x10000 	/* size of one complete sector	*/
+#define CFG_ENV_SECT_SIZE	0x10000	/* size of one complete sector	*/
 #define CFG_ENV_ADDR		(CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
 #define	CFG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
 
diff --git a/include/configs/c2mon.h b/include/configs/c2mon.h
index a5621b8056..6f0d4b0f80 100644
--- a/include/configs/c2mon.h
+++ b/include/configs/c2mon.h
@@ -54,9 +54,9 @@
 
 #undef	CONFIG_BOOTARGS
 #define CONFIG_BOOTCOMMAND							\
-	"bootp; " 								\
-	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " 	\
-	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " 	\
+	"bootp; "								\
+	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "	\
 	"bootm"
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
diff --git a/include/configs/canmb.h b/include/configs/canmb.h
index 440972c4dc..0f7bb619ce 100644
--- a/include/configs/canmb.h
+++ b/include/configs/canmb.h
@@ -31,7 +31,7 @@
 
 #define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU */
 #define CONFIG_MPC5200		1	/* More exactly a MPC5200 */
-#define CONFIG_CANMB  		1	/* ... on canmb board - we need this for FEC.C */
+#define CONFIG_CANMB		1	/* ... on canmb board - we need this for FEC.C */
 
 #define CFG_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz */
 
@@ -115,7 +115,7 @@
 /*
  * IPB Bus clocking configuration.
  */
-#undef CFG_IPBCLK_EQUALS_XLBCLK   		/* define for 133MHz speed */
+#undef CFG_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
 
 /*
  * Flash configuration, expect one 16 Megabyte Bank at most
diff --git a/include/configs/cerf250.h b/include/configs/cerf250.h
index e06735da63..c801f037e1 100644
--- a/include/configs/cerf250.h
+++ b/include/configs/cerf250.h
@@ -39,7 +39,7 @@
 #define BOARD_LATE_INIT		1
 #define CONFIG_BAUDRATE		38400
 
-#undef 	CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff */
+#undef	CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff */
 
 /*
  * Size of malloc() pool
@@ -104,7 +104,7 @@
 #define CFG_PROMPT			"=> "		/* Monitor Command Prompt */
 #endif
 #define CFG_CBSIZE			256			/* Console I/O Buffer Size	*/
-#define CFG_PBSIZE 			(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
+#define CFG_PBSIZE			(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
 										/* Print Buffer Size */
 #define CFG_MAXARGS			16			/* max number of command args	*/
 #define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
@@ -137,21 +137,21 @@
 /*
  * Physical Memory Map
  */
-#define CONFIG_NR_DRAM_BANKS	4	   		/* we have 2 banks of DRAM */
-#define PHYS_SDRAM_1			0xa0000000 	/* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE		0x04000000 	/* 64 MB */
-#define PHYS_SDRAM_2			0xa4000000 	/* SDRAM Bank #2 */
-#define PHYS_SDRAM_2_SIZE		0x00000000 	/* 0 MB */
-#define PHYS_SDRAM_3			0xa8000000 	/* SDRAM Bank #3 */
-#define PHYS_SDRAM_3_SIZE		0x00000000 	/* 0 MB */
-#define PHYS_SDRAM_4			0xac000000 	/* SDRAM Bank #4 */
-#define PHYS_SDRAM_4_SIZE		0x00000000 	/* 0 MB */
-
-#define PHYS_FLASH_1			0x00000000 	/* Flash Bank #1 */
-#define PHYS_FLASH_2			0x04000000 	/* Flash Bank #2 */
-#define PHYS_FLASH_SIZE			0x02000000 	/* 32 MB */
-#define PHYS_FLASH_BANK_SIZE		0x02000000 	/* 32 MB Banks */
-#define PHYS_FLASH_SECT_SIZE		0x00040000 	/* 256 KB sectors (x2) */
+#define CONFIG_NR_DRAM_BANKS	4			/* we have 2 banks of DRAM */
+#define PHYS_SDRAM_1			0xa0000000	/* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE		0x04000000	/* 64 MB */
+#define PHYS_SDRAM_2			0xa4000000	/* SDRAM Bank #2 */
+#define PHYS_SDRAM_2_SIZE		0x00000000	/* 0 MB */
+#define PHYS_SDRAM_3			0xa8000000	/* SDRAM Bank #3 */
+#define PHYS_SDRAM_3_SIZE		0x00000000	/* 0 MB */
+#define PHYS_SDRAM_4			0xac000000	/* SDRAM Bank #4 */
+#define PHYS_SDRAM_4_SIZE		0x00000000	/* 0 MB */
+
+#define PHYS_FLASH_1			0x00000000	/* Flash Bank #1 */
+#define PHYS_FLASH_2			0x04000000	/* Flash Bank #2 */
+#define PHYS_FLASH_SIZE			0x02000000	/* 32 MB */
+#define PHYS_FLASH_BANK_SIZE		0x02000000	/* 32 MB Banks */
+#define PHYS_FLASH_SECT_SIZE		0x00040000	/* 256 KB sectors (x2) */
 
 #define CFG_DRAM_BASE			0xa0000000
 #define CFG_DRAM_SIZE			0x04000000
@@ -210,7 +210,7 @@
  * FLASH and environment organization
  */
 #define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	128  	/* max number of sectors on one chip    */
+#define CFG_MAX_FLASH_SECT	128	/* max number of sectors on one chip    */
 
 /* timeout values are in ticks */
 #define CFG_FLASH_ERASE_TOUT	(25*CFG_HZ) /* Timeout for Flash Erase */
diff --git a/include/configs/cmi_mpc5xx.h b/include/configs/cmi_mpc5xx.h
index a869364c60..ac2b7a1e71 100644
--- a/include/configs/cmi_mpc5xx.h
+++ b/include/configs/cmi_mpc5xx.h
@@ -24,7 +24,7 @@
  * File:		cmi_mpc5xx.h
  *
  * Discription:		Config header file for cmi
- * 			board  using an MPC5xx CPU
+ *			board  using an MPC5xx CPU
  *
  */
 
@@ -36,7 +36,7 @@
  */
 
 #define CONFIG_MPC555		1		/* This is an MPC555 CPU		*/
-#define CONFIG_CMI		1		/* Using the customized cmi board 	*/
+#define CONFIG_CMI		1		/* Using the customized cmi board	*/
 
 /* Serial Console Configuration */
 #define	CONFIG_5xx_CONS_SCI1
@@ -79,11 +79,11 @@
 #else
 #define CONFIG_BOOTDELAY	5		/* autoboot after 5 seconds		*/
 #endif
-#define CONFIG_BOOTCOMMAND	"go 02034004" 	/* autoboot command			*/
+#define CONFIG_BOOTCOMMAND	"go 02034004"	/* autoboot command			*/
 
 #define CONFIG_BOOTARGS		""		/* Assuming OS Image in 4 flash sector at offset 4004 */
 
-#define CONFIG_WATCHDOG				/* turn on platform specific watchdog 	*/
+#define CONFIG_WATCHDOG				/* turn on platform specific watchdog	*/
 
 #define CONFIG_STATUS_LED	1		/* Enable status led */
 
@@ -121,30 +121,30 @@
 /*
  * Internal Memory Mapped (This is not the IMMR content)
  */
-#define CFG_IMMR		0x01000000				/* Physical start adress of internal memory map */
+#define CFG_IMMR		0x01000000		/* Physical start adress of internal memory map */
 
 /*
  * Definitions for initial stack pointer and data area
  */
-#define CFG_INIT_RAM_ADDR	(CFG_IMMR + 0x003f9800)      		/* Physical start adress of internal MPC555 writable RAM */
-#define	CFG_INIT_RAM_END	(CFG_IMMR + 0x003fffff)       		/* Physical end adress of internal MPC555 used RAM area	*/
-#define	CFG_GBL_DATA_SIZE	64					/* Size in bytes reserved for initial global data */
+#define CFG_INIT_RAM_ADDR	(CFG_IMMR + 0x003f9800)	/* Physical start adress of internal MPC555 writable RAM */
+#define	CFG_INIT_RAM_END	(CFG_IMMR + 0x003fffff)	/* Physical end adress of internal MPC555 used RAM area	*/
+#define	CFG_GBL_DATA_SIZE	64			/* Size in bytes reserved for initial global data */
 #define CFG_GBL_DATA_OFFSET	((CFG_INIT_RAM_END - CFG_INIT_RAM_ADDR) - CFG_GBL_DATA_SIZE) /* Offset from the beginning of ram */
-#define	CFG_INIT_SP_ADDR	0x013fa000				/* Physical start adress of inital stack */
+#define	CFG_INIT_SP_ADDR	0x013fa000		/* Physical start adress of inital stack */
 
 /*
  * Start addresses for the final memory configuration
  * Please note that CFG_SDRAM_BASE _must_ start at 0
  */
-#define	CFG_SDRAM_BASE		0x00000000	/* Monitor won't change memory map 			*/
+#define	CFG_SDRAM_BASE		0x00000000	/* Monitor won't change memory map			*/
 #define CFG_FLASH_BASE		0x02000000	/* External flash */
 #define PLD_BASE		0x03000000	/* PLD  */
 #define ANYBUS_BASE		0x03010000	/* Anybus Module */
 
 #define CFG_RESET_ADRESS	0x01000000	/* Adress which causes reset */
-#define	CFG_MONITOR_BASE	CFG_FLASH_BASE	/* TEXT_BASE is defined in the board config.mk file. 	*/
-						/* This adress is given to the linker with -Ttext to 	*/
-						/* locate the text section at this adress. 		*/
+#define	CFG_MONITOR_BASE	CFG_FLASH_BASE	/* TEXT_BASE is defined in the board config.mk file.	*/
+						/* This adress is given to the linker with -Ttext to	*/
+						/* locate the text section at this adress.		*/
 #define	CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor				*/
 #define	CFG_MALLOC_LEN		(64 << 10)	/* Reserve 128 kB for malloc()				*/
 
@@ -163,16 +163,16 @@
  */
 
 #define CFG_MAX_FLASH_BANKS	1		/* Max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	64		/* Max number of sectors on one chip 	*/
-#define CFG_FLASH_ERASE_TOUT	180000		/* Timeout for Flash Erase (in ms) 	*/
-#define CFG_FLASH_WRITE_TOUT	600		/* Timeout for Flash Write (in ms) 	*/
+#define CFG_MAX_FLASH_SECT	64		/* Max number of sectors on one chip	*/
+#define CFG_FLASH_ERASE_TOUT	180000		/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	600		/* Timeout for Flash Write (in ms)	*/
 #define CFG_FLASH_PROTECTION    1		/* Physically section protection on	*/
 
 #define	CFG_ENV_IS_IN_FLASH	1
 
 #ifdef	CFG_ENV_IS_IN_FLASH
-#define CFG_ENV_OFFSET		0x00020000	/* Environment starts at this adress 	*/
-#define	CFG_ENV_SIZE		0x00010000	/* Set whole sector as env 		*/
+#define CFG_ENV_OFFSET		0x00020000	/* Environment starts at this adress	*/
+#define	CFG_ENV_SIZE		0x00010000	/* Set whole sector as env		*/
 #define	CFG_USE_PPCENV				/* Environment embedded in sect .ppcenv */
 #endif
 
@@ -219,7 +219,7 @@
  *-----------------------------------------------------------------------
  * Data show cycle
  */
-#define CFG_SIUMCR	(SIUMCR_DBGC00)		/* Disable data show cycle 	*/
+#define CFG_SIUMCR	(SIUMCR_DBGC00)		/* Disable data show cycle	*/
 
 /*-----------------------------------------------------------------------
  * PLPRCR - PLL, Low-Power, and Reset Control Register
@@ -227,7 +227,7 @@
  * Set all bits to 40 Mhz
  *
  */
-#define CFG_OSC_CLK   	((uint)4000000) 	/* Oscillator clock is 4MHz 	*/
+#define CFG_OSC_CLK	((uint)4000000)		/* Oscillator clock is 4MHz	*/
 #define CFG_PLPRCR	(PLPRCR_MF_9 | PLPRCR_DIVF_0)
 
 
@@ -236,12 +236,12 @@
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_UMCR	(UMCR_FSPEED) 		/* IMB clock same as U-bus 	*/
+#define CFG_UMCR	(UMCR_FSPEED)		/* IMB clock same as U-bus	*/
 
 /*-----------------------------------------------------------------------
  * ICTRL - I-Bus Support Control Register
  */
-#define CFG_ICTRL	(ICTRL_ISCT_SER_7) 	/* Take out of serialized mode 	*/
+#define CFG_ICTRL	(ICTRL_ISCT_SER_7)	/* Take out of serialized mode	*/
 
 /*-----------------------------------------------------------------------
  * USIU - Memory Controller Register
@@ -256,7 +256,7 @@
 #define CFG_OR2_PRELIM		(OR_ADDR_MK_FF)
 #define CFG_BR3_PRELIM		(PLD_BASE | BR_V | BR_BI | BR_LBDIR | BR_PS_8)
 #define CFG_OR3_PRELIM		(OR_ADDR_MK_FF | OR_TRLX | OR_BSCY | OR_SCY_8 | \
-			 	 OR_ACS_10 | OR_ETHR | OR_CSNT)
+				 OR_ACS_10 | OR_ETHR | OR_CSNT)
 
 #define FLASH_BASE0_PRELIM	CFG_FLASH_BASE	/* We don't realign the flash	*/
 
diff --git a/include/configs/cobra5272.h b/include/configs/cobra5272.h
index c7e3899e63..649b053c2b 100644
--- a/include/configs/cobra5272.h
+++ b/include/configs/cobra5272.h
@@ -101,7 +101,7 @@
  * bootloader residing in flash ('chainloading'); if you want to use
  * chainloading or want to compile a u-boot binary that can be loaded into
  * RAM via BDM set
- * 	"#if 0" to "#if 1"
+ *	"#if 0" to "#if 1"
  * You will need a first stage bootloader then, e. g. colilo or a working BDM
  * cable (Background Debug Mode)
  *
@@ -165,7 +165,7 @@
 
 #	define CFG_FEC0_PINMUX		0
 #	define CFG_FEC0_MIIBASE		CFG_FEC0_IOBASE
-#	define MCFFEC_TOUT_LOOP 	50000
+#	define MCFFEC_TOUT_LOOP		50000
 /* If CFG_DISCOVER_PHY is not defined - hardcoded */
 #	ifndef CFG_DISCOVER_PHY
 #		define FECDUPLEX	FULL
diff --git a/include/configs/csb226.h b/include/configs/csb226.h
index 0be0f21924..a807d0084d 100644
--- a/include/configs/csb226.h
+++ b/include/configs/csb226.h
@@ -37,7 +37,7 @@
  * High Level Configuration Options
  * (easy to change)
  */
-#define CONFIG_PXA250 		1	/* This is an PXA250 CPU            */
+#define CONFIG_PXA250		1	/* This is an PXA250 CPU            */
 #define CONFIG_CSB226		1	/* on a CSB226 board                */
 
 #undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff      */
diff --git a/include/configs/csb272.h b/include/configs/csb272.h
index a24478d0b3..15bf1772b9 100644
--- a/include/configs/csb272.h
+++ b/include/configs/csb272.h
@@ -33,7 +33,7 @@
  * (easy to change)
  */
 
-#define CONFIG_405GP		1	/* This is a PPC405GP CPU     	*/
+#define CONFIG_405GP		1	/* This is a PPC405GP CPU	*/
 #define CONFIG_4xx		1	/* ...member of PPC4xx family   */
 #define CONFIG_CSB272		1	/* on a Cogent CSB272 board     */
 #define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f()    */
@@ -182,7 +182,7 @@
  */
 #define CONFIG_MII		1	/* MII PHY management		*/
 #define CONFIG_PHY_ADDR		0	/* PHY address			*/
-#define CONFIG_PHY_CMD_DELAY	40	/* PHY COMMAND delay 		*/
+#define CONFIG_PHY_CMD_DELAY	40	/* PHY COMMAND delay		*/
 					/* 32usec min. for LXT971A	*/
 #define CONFIG_PHY_RESET_DELAY	300	/* PHY RESET recovery delay	*/
 
diff --git a/include/configs/csb472.h b/include/configs/csb472.h
index 064650cfca..b06c0a269d 100644
--- a/include/configs/csb472.h
+++ b/include/configs/csb472.h
@@ -33,7 +33,7 @@
  * (easy to change)
  */
 
-#define CONFIG_405GP		1	/* This is a PPC405GP CPU     	*/
+#define CONFIG_405GP		1	/* This is a PPC405GP CPU	*/
 #define CONFIG_4xx		1	/* ...member of PPC4xx family   */
 #define CONFIG_CSB472		1	/* on a Cogent CSB472 board     */
 #define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f()    */
@@ -181,7 +181,7 @@
  */
 #define CONFIG_MII		1	/* MII PHY management		*/
 #define CONFIG_PHY_ADDR		0	/* PHY address			*/
-#define CONFIG_PHY_CMD_DELAY	40	/* PHY COMMAND delay 		*/
+#define CONFIG_PHY_CMD_DELAY	40	/* PHY COMMAND delay		*/
 					/* 32usec min. for LXT971A	*/
 #define CONFIG_PHY_RESET_DELAY	300	/* PHY RESET recovery delay	*/
 
diff --git a/include/configs/davinci_dvevm.h b/include/configs/davinci_dvevm.h
index 8ecd0595a2..632c4c2bf9 100644
--- a/include/configs/davinci_dvevm.h
+++ b/include/configs/davinci_dvevm.h
@@ -145,16 +145,16 @@
 #define CFG_MAX_FLASH_BANKS	1		/* max number of flash banks */
 #define CFG_FLASH_SECT_SZ	0x10000		/* 64KB sect size AMD Flash */
 #define CFG_ENV_OFFSET		(CFG_FLASH_SECT_SZ*3)
-#define PHYS_FLASH_1		0x02000000	/* CS2 Base address 	 */
+#define PHYS_FLASH_1		0x02000000	/* CS2 Base address	 */
 #define CFG_FLASH_BASE		PHYS_FLASH_1	/* Flash Base for U-Boot */
-#define PHYS_FLASH_SIZE		0x2000000	/* Flash size 32MB 	 */
+#define PHYS_FLASH_SIZE		0x2000000	/* Flash size 32MB	 */
 #define CFG_MAX_FLASH_SECT	(PHYS_FLASH_SIZE/CFG_FLASH_SECT_SZ)
 #define CFG_ENV_SECT_SIZE	CFG_FLASH_SECT_SZ	/* Env sector Size */
 #endif
 /*==============================*/
 /* U-Boot general configuration */
 /*==============================*/
-#undef 	CONFIG_USE_IRQ			/* No IRQ/FIQ in U-Boot */
+#undef	CONFIG_USE_IRQ			/* No IRQ/FIQ in U-Boot */
 #define CONFIG_MISC_INIT_R
 #undef CONFIG_BOOTDELAY
 #define CONFIG_BOOTFILE		"uImage"	/* Boot file name */
diff --git a/include/configs/davinci_schmoogie.h b/include/configs/davinci_schmoogie.h
index 96c9a30147..10166a1477 100644
--- a/include/configs/davinci_schmoogie.h
+++ b/include/configs/davinci_schmoogie.h
@@ -102,7 +102,7 @@
 /*==============================*/
 /* U-Boot general configuration */
 /*==============================*/
-#undef 	CONFIG_USE_IRQ			/* No IRQ/FIQ in U-Boot */
+#undef	CONFIG_USE_IRQ			/* No IRQ/FIQ in U-Boot */
 #define CONFIG_MISC_INIT_R
 #undef CONFIG_BOOTDELAY
 #define CONFIG_BOOTFILE		"uImage"	/* Boot file name */
diff --git a/include/configs/davinci_sonata.h b/include/configs/davinci_sonata.h
index de8c4fac2b..ba68605a05 100644
--- a/include/configs/davinci_sonata.h
+++ b/include/configs/davinci_sonata.h
@@ -140,16 +140,16 @@
 #define CFG_MAX_FLASH_BANKS	1		/* max number of flash banks */
 #define CFG_FLASH_SECT_SZ	0x20000		/* 128KB sect size AMD Flash */
 #define CFG_ENV_OFFSET		(CFG_FLASH_SECT_SZ*2)
-#define PHYS_FLASH_1		0x02000000	/* CS2 Base address 	 */
+#define PHYS_FLASH_1		0x02000000	/* CS2 Base address	 */
 #define CFG_FLASH_BASE		PHYS_FLASH_1	/* Flash Base for U-Boot */
-#define PHYS_FLASH_SIZE		0x2000000	/* Flash size 32MB 	 */
+#define PHYS_FLASH_SIZE		0x2000000	/* Flash size 32MB	 */
 #define CFG_MAX_FLASH_SECT	(PHYS_FLASH_SIZE/CFG_FLASH_SECT_SZ)
 #define CFG_ENV_SECT_SIZE	CFG_FLASH_SECT_SZ	/* Env sector Size */
 #endif
 /*==============================*/
 /* U-Boot general configuration */
 /*==============================*/
-#undef 	CONFIG_USE_IRQ			/* No IRQ/FIQ in U-Boot */
+#undef	CONFIG_USE_IRQ			/* No IRQ/FIQ in U-Boot */
 #define CONFIG_MISC_INIT_R
 #undef CONFIG_BOOTDELAY
 #define CONFIG_BOOTFILE		"uImage"	/* Boot file name */
diff --git a/include/configs/dnp1110.h b/include/configs/dnp1110.h
index d32e046023..e7873e95fd 100644
--- a/include/configs/dnp1110.h
+++ b/include/configs/dnp1110.h
@@ -83,7 +83,7 @@
 
 
 #define CONFIG_BOOTDELAY	3
-#define CONFIG_BOOTARGS    	"root=ramfs devfs=mount console=ttySA0,115200"
+#define CONFIG_BOOTARGS		"root=ramfs devfs=mount console=ttySA0,115200"
 #define CONFIG_ETHADDR		02:80:ad:20:31:b8
 #define CONFIG_NETMASK          255.255.0.0
 #define CONFIG_IPADDR		172.22.2.23
diff --git a/include/configs/ep7312.h b/include/configs/ep7312.h
index f5cf477a31..54330821b1 100644
--- a/include/configs/ep7312.h
+++ b/include/configs/ep7312.h
@@ -34,7 +34,7 @@
 #define CONFIG_ARM7		1	/* This is a ARM7 CPU	*/
 #define CONFIG_EP7312		1	/* on an EP7312 Board      */
 #define CONFIG_ARM_THUMB	1	/* this is an ARM720TDMI */
-#undef  CONFIG_ARM7_REVD	 	/* disable ARM720 REV.D Workarounds */
+#undef  CONFIG_ARM7_REVD		/* disable ARM720 REV.D Workarounds */
 
 #undef CONFIG_USE_IRQ			/* don't need them anymore */
 
@@ -81,8 +81,8 @@
 
 
 #define CONFIG_BOOTDELAY	3
-#define CONFIG_BOOTARGS    	"devfs=mount root=ramfs console=ttyS0,9600"
-#define CONFIG_ETHADDR	08:00:3e:21:c7:f7
+#define CONFIG_BOOTARGS		"devfs=mount root=ramfs console=ttyS0,9600"
+#define CONFIG_ETHADDR		08:00:3e:21:c7:f7
 /*#define CONFIG_NETMASK        255.255.0.0	*/
 /*#define CONFIG_IPADDR		172.22.2.128	*/
 /*#define CONFIG_SERVERIP	172.22.2.126	*/
diff --git a/include/configs/ep8248.h b/include/configs/ep8248.h
index cebe849f66..8a220b6816 100644
--- a/include/configs/ep8248.h
+++ b/include/configs/ep8248.h
@@ -234,13 +234,13 @@
 /* Hard reset configuration word */
 #define CFG_HRCW_MASTER		0x0C40025A /* Not used - provided by FPGA */
 /* No slaves */
-#define CFG_HRCW_SLAVE1 	0
-#define CFG_HRCW_SLAVE2 	0
-#define CFG_HRCW_SLAVE3 	0
-#define CFG_HRCW_SLAVE4 	0
-#define CFG_HRCW_SLAVE5 	0
-#define CFG_HRCW_SLAVE6 	0
-#define CFG_HRCW_SLAVE7 	0
+#define CFG_HRCW_SLAVE1		0
+#define CFG_HRCW_SLAVE2		0
+#define CFG_HRCW_SLAVE3		0
+#define CFG_HRCW_SLAVE4		0
+#define CFG_HRCW_SLAVE5		0
+#define CFG_HRCW_SLAVE6		0
+#define CFG_HRCW_SLAVE7		0
 
 #define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH */
 #define BOOTFLAG_WARM		0x02	/* Software reboot                  */
diff --git a/include/configs/ep8260.h b/include/configs/ep8260.h
index 490db5fefd..0ce6b80b90 100644
--- a/include/configs/ep8260.h
+++ b/include/configs/ep8260.h
@@ -28,17 +28,17 @@
  * board/config.h - configuration options, board specific
  *
  * "EP8260 H, V.1.1"
- * 	- 64M 60x Bus SDRAM
- * 	- 32M Local Bus SDRAM
- * 	- 16M Flash (4 x AM29DL323DB90WDI)
- * 	- 128k NVRAM with RTC
+ *	- 64M 60x Bus SDRAM
+ *	- 32M Local Bus SDRAM
+ *	- 16M Flash (4 x AM29DL323DB90WDI)
+ *	- 128k NVRAM with RTC
  *
  * "EP8260 H2, V.1.3" (CFG_EP8260_H2)
- * 	- 300MHz/133MHz/66MHz
- * 	- 64M 60x Bus SDRAM
- * 	- 32M Local Bus SDRAM
- * 	- 32M Flash
- * 	- 128k NVRAM with RTC
+ *	- 300MHz/133MHz/66MHz
+ *	- 64M 60x Bus SDRAM
+ *	- 32M Local Bus SDRAM
+ *	- 32M Flash
+ *	- 128k NVRAM with RTC
  */
 
 #ifndef __CONFIG_H
@@ -408,7 +408,7 @@
 			 CFG_SBC_HRCW_IMMR       |\
 			 HRCW_APPC10             |\
 			 HRCW_CS10PC01           |\
-			 CFG_SBC_MODCK_H 	 |\
+			 CFG_SBC_MODCK_H	 |\
 			 CFG_SBC_HRCW_BOOT_FLAGS)
 #else
 #define CFG_HRCW_MASTER 0x10400245
diff --git a/include/configs/ep82xxm.h b/include/configs/ep82xxm.h
index 8e5d6e57c7..ac5847ce12 100644
--- a/include/configs/ep82xxm.h
+++ b/include/configs/ep82xxm.h
@@ -229,7 +229,7 @@
 #endif /* CFG_ENV_IS_IN_EEPROM */
 
 /* RTC Configuration */
-#define CONFIG_RTC_M41T11	1 	/* uses a M41T81 */
+#define CONFIG_RTC_M41T11	1	/* uses a M41T81 */
 #define CFG_I2C_RTC_ADDR	0x68
 #define CONFIG_M41T11_BASE_YEAR	1900
 
@@ -353,13 +353,13 @@
 /* Hard reset configuration word */
 #define CFG_HRCW_MASTER		0 /*0x1C800641*/  /* Not used - provided by CPLD */
 /* No slaves */
-#define CFG_HRCW_SLAVE1 	0
-#define CFG_HRCW_SLAVE2 	0
-#define CFG_HRCW_SLAVE3 	0
-#define CFG_HRCW_SLAVE4 	0
-#define CFG_HRCW_SLAVE5 	0
-#define CFG_HRCW_SLAVE6 	0
-#define CFG_HRCW_SLAVE7 	0
+#define CFG_HRCW_SLAVE1		0
+#define CFG_HRCW_SLAVE2		0
+#define CFG_HRCW_SLAVE3		0
+#define CFG_HRCW_SLAVE4		0
+#define CFG_HRCW_SLAVE5		0
+#define CFG_HRCW_SLAVE6		0
+#define CFG_HRCW_SLAVE7		0
 
 #define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH */
 #define BOOTFLAG_WARM		0x02	/* Software reboot                  */
diff --git a/include/configs/evb4510.h b/include/configs/evb4510.h
index 66500c21e0..1571477d02 100644
--- a/include/configs/evb4510.h
+++ b/include/configs/evb4510.h
@@ -98,7 +98,7 @@
 
 #define CONFIG_BOOTDELAY	2
 #define CONFIG_BOOTCOMMAND	"tftp 100000 uImage"
-/* #define CONFIG_BOOTARGS    	"console=ttyS0,19200 initrd=0x100a0040,530K root=/dev/ram keepinitrd" */
+/* #define CONFIG_BOOTARGS	"console=ttyS0,19200 initrd=0x100a0040,530K root=/dev/ram keepinitrd" */
 
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE	19200		/* speed to run kgdb serial port */
diff --git a/include/configs/gr_cpci_ax2000.h b/include/configs/gr_cpci_ax2000.h
index 1276f4d83a..ffe7671ec0 100644
--- a/include/configs/gr_cpci_ax2000.h
+++ b/include/configs/gr_cpci_ax2000.h
@@ -58,7 +58,7 @@
 #define CONFIG_LEON_RAM_SELECT CONFIG_LEON_RAM_SRAM
 
 /* CPU / AMBA BUS configuration */
-#define CONFIG_SYS_CLK_FREQ 	20000000	/* 20MHz */
+#define CONFIG_SYS_CLK_FREQ	20000000	/* 20MHz */
 
 /* Number of SPARC register windows */
 #define CFG_SPARC_NWINDOWS 8
diff --git a/include/configs/gr_ep2s60.h b/include/configs/gr_ep2s60.h
index 710a082e97..7b1d582202 100644
--- a/include/configs/gr_ep2s60.h
+++ b/include/configs/gr_ep2s60.h
@@ -39,10 +39,10 @@
 #define CONFIG_LEON3		/* This is an LEON3 CPU */
 #define CONFIG_LEON		1	/* This is an LEON CPU */
 /* Altera NIOS Development board, Stratix II board */
-#define CONFIG_GR_EP2S60 	1
+#define CONFIG_GR_EP2S60	1
 
 /* CPU / AMBA BUS configuration */
-#define CONFIG_SYS_CLK_FREQ 	96000000	/* 96MHz */
+#define CONFIG_SYS_CLK_FREQ	96000000	/* 96MHz */
 
 /* Number of SPARC register windows */
 #define CFG_SPARC_NWINDOWS 8
diff --git a/include/configs/gr_xc3s_1500.h b/include/configs/gr_xc3s_1500.h
index 1fdef3d4ab..6fe2b7cc3b 100644
--- a/include/configs/gr_xc3s_1500.h
+++ b/include/configs/gr_xc3s_1500.h
@@ -39,7 +39,7 @@
 #define CONFIG_GRXC3S1500	1	/* ... on GR-XC3S-1500 board */
 
 /* CPU / AMBA BUS configuration */
-#define CONFIG_SYS_CLK_FREQ 	40000000	/* 40MHz */
+#define CONFIG_SYS_CLK_FREQ	40000000	/* 40MHz */
 
 /* Number of SPARC register windows */
 #define CFG_SPARC_NWINDOWS 8
diff --git a/include/configs/grsim.h b/include/configs/grsim.h
index 60ad396f5f..3fb8eb3a61 100644
--- a/include/configs/grsim.h
+++ b/include/configs/grsim.h
@@ -46,7 +46,7 @@
 #define CONFIG_TSIM		1	/* ... running on TSIM */
 
 /* CPU / AMBA BUS configuration */
-#define CONFIG_SYS_CLK_FREQ 	40000000	/* 40MHz */
+#define CONFIG_SYS_CLK_FREQ	40000000	/* 40MHz */
 
 /* Number of SPARC register windows */
 #define CFG_SPARC_NWINDOWS 8
diff --git a/include/configs/grsim_leon2.h b/include/configs/grsim_leon2.h
index 2ad5b95a17..406ce3df37 100644
--- a/include/configs/grsim_leon2.h
+++ b/include/configs/grsim_leon2.h
@@ -45,7 +45,7 @@
 #define CONFIG_TSIM		1	/* ... running on TSIM */
 
 /* CPU / AMBA BUS configuration */
-#define CONFIG_SYS_CLK_FREQ 	40000000	/* 40MHz */
+#define CONFIG_SYS_CLK_FREQ	40000000	/* 40MHz */
 
 /* Number of SPARC register windows */
 #define CFG_SPARC_NWINDOWS 8
diff --git a/include/configs/hcu4.h b/include/configs/hcu4.h
index 4ecaf90abc..13b0358cb6 100644
--- a/include/configs/hcu4.h
+++ b/include/configs/hcu4.h
@@ -127,14 +127,14 @@
 
 #ifdef  CFG_ENV_IS_IN_EEPROM
 /* Put the environment after the SDRAM configuration */
-#define PROM_SIZE 	2048
+#define PROM_SIZE	2048
 #define CFG_ENV_OFFSET	 512
 #define CFG_ENV_SIZE	(PROM_SIZE-CFG_ENV_OFFSET)
 #endif
 
 #ifdef CFG_ENV_IS_IN_FLASH
 /* Put the environment in Flash */
-#define CFG_ENV_SECT_SIZE	0x10000 	/* size of one complete sector	*/
+#define CFG_ENV_SECT_SIZE	0x10000	/* size of one complete sector	*/
 #define CFG_ENV_ADDR		((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
 #define	CFG_ENV_SIZE		8*1024	/* 8 KB Environment Sector	*/
 
diff --git a/include/configs/hcu5.h b/include/configs/hcu5.h
index f5f11978da..20808681f3 100644
--- a/include/configs/hcu5.h
+++ b/include/configs/hcu5.h
@@ -113,7 +113,7 @@
 
 #ifdef  CFG_ENV_IS_IN_EEPROM
 /* Put the environment after the SDRAM and bootstrap configuration */
-#define PROM_SIZE 	2048
+#define PROM_SIZE	2048
 #define CFG_BOOSTRAP_OPTION_OFFSET	 512
 #define CFG_ENV_OFFSET	 (CFG_BOOSTRAP_OPTION_OFFSET + 0x10)
 #define CFG_ENV_SIZE	(PROM_SIZE-CFG_ENV_OFFSET)
@@ -134,7 +134,7 @@
 /*-----------------------------------------------------------------------
  * DDR SDRAM
  *----------------------------------------------------------------------*/
-#define CFG_MBYTES_SDRAM        (128)		/* 128 MB or 256 MB  	*/
+#define CFG_MBYTES_SDRAM        (128)		/* 128 MB or 256 MB	*/
 #define CFG_DDR_CACHED_ADDR	0x50000000	/* setup 2nd TLB cached here */
 #undef  CONFIG_DDR_DATA_EYE		/* Do not use DDR2 optimization	*/
 #define CONFIG_DDR_ECC		1	/* enable ECC			*/
@@ -176,13 +176,13 @@
 /* Setup some board specific values for the default environment variables */
 #define CONFIG_HOSTNAME		hcu5
 #define CONFIG_IPADDR		172.25.1.99
-#define CONFIG_ETHADDR      	00:60:13:00:00:00 /* Netstal Machines AG MAC */
+#define CONFIG_ETHADDR	00:60:13:00:00:00 /* Netstal Machines AG MAC */
 #define CONFIG_OVERWRITE_ETHADDR_ONCE
 #define CONFIG_SERVERIP		172.25.1.3
 
 #define CFG_TFTP_LOADADDR 0x01000000 /* @16 MB */
 
-#define	CONFIG_EXTRA_ENV_SETTINGS				\
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
 	"netdev=eth0\0"							\
 	"loadaddr=0x01000000\0"						\
 	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
@@ -192,11 +192,11 @@
 		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
 		":${hostname}:${netdev}:off panic=1\0"			\
 	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
-	"nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" 	\
+	"nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"		\
 		"bootm\0"						\
-		"bootfile=hcu5/uImage\0" 				\
-		"rootpath=/home/hcu/eldk/ppc_4xxFP\0"		 	\
-		"load=tftp 100000 hcu5/u-boot.bin\0"		 	\
+		"bootfile=hcu5/uImage\0"				\
+		"rootpath=/home/hcu/eldk/ppc_4xxFP\0"			\
+		"load=tftp 100000 hcu5/u-boot.bin\0"			\
 	"update=protect off FFFB0000 FFFFFFFF;era FFFB0000 FFFFFFFF;"	\
 		"cp.b 100000 FFFB0000 50000\0"			        \
 	"upd=run load update\0"						\
@@ -204,9 +204,9 @@
 	"vx=tftp ${loadaddr} ${vx_rom};run vxargs; bootvx\0"		\
 	"vxargs=setenv bootargs emac(0,0)c:${vx_rom} e=${ipaddr}"	\
 	" h=${serverip} u=dpu pw=netstal8752 tn=hcu5 f=0x3008\0"	\
-	"usbargs=setenv bootargs root=/dev/sda1 ro\0"     	     	\
+	"usbargs=setenv bootargs root=/dev/sda1 ro\0"			\
 	"linux=usb start; ext2load usb 0 ${loadaddr} /boot/uImage;"     \
-	"run usbargs addip addtty; bootm\0"     			\
+	"run usbargs addip addtty; bootm\0"				\
 	"net_nfs_fdt=tftp 200000 ${bootfile};"				\
 		"tftp ${fdt_addr} ${fdt_file};"				\
 		"run nfsargs addip addtty;"				\
diff --git a/include/configs/hermes.h b/include/configs/hermes.h
index e3a2ed2803..48b23bdcd6 100644
--- a/include/configs/hermes.h
+++ b/include/configs/hermes.h
@@ -54,9 +54,9 @@
 
 #undef	CONFIG_BOOTARGS
 #define CONFIG_BOOTCOMMAND							\
-	"bootp; " 								\
-	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " 	\
-	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " 	\
+	"bootp; "								\
+	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "	\
 	"bootm"
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
@@ -105,7 +105,7 @@
 
 #define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
-#define	CFG_ALLOC_DPRAM		1	/* use allocation routines 	*/
+#define	CFG_ALLOC_DPRAM		1	/* use allocation routines	*/
 /*
  * Low Level Configuration Settings
  * (address mappings, register initial values, etc.)
@@ -227,7 +227,7 @@
 /* +0x0282 => 0x03800000 */
 #define CFG_SCCR	(SCCR_COM00	|   SCCR_TBS	  |	\
 			 SCCR_RTDIV	|   SCCR_RTSEL	  |	\
-			 /*SCCR_CRQEN|*/  /*SCCR_PRQEN|*/ 	\
+			 /*SCCR_CRQEN|*/  /*SCCR_PRQEN|*/	\
 			 SCCR_EBDF00	|   SCCR_DFSYNC00 |	\
 			 SCCR_DFBRG00	|   SCCR_DFNL000  |	\
 			 SCCR_DFNH000)
diff --git a/include/configs/idmr.h b/include/configs/idmr.h
index 2ed51f7784..7c3ebad4b7 100644
--- a/include/configs/idmr.h
+++ b/include/configs/idmr.h
@@ -164,7 +164,7 @@
 
 #	define CFG_FEC0_PINMUX		0
 #	define CFG_FEC0_MIIBASE		CFG_FEC0_IOBASE
-#	define MCFFEC_TOUT_LOOP 	50000
+#	define MCFFEC_TOUT_LOOP		50000
 /* If CFG_DISCOVER_PHY is not defined - hardcoded */
 #	ifndef CFG_DISCOVER_PHY
 #		define FECDUPLEX	FULL
diff --git a/include/configs/impa7.h b/include/configs/impa7.h
index 0e52ffe0a2..e9704fc9af 100644
--- a/include/configs/impa7.h
+++ b/include/configs/impa7.h
@@ -34,7 +34,7 @@
 #define CONFIG_ARM7		1	/* This is a ARM7 CPU	*/
 #define CONFIG_IMPA7		1	/* on an impA7 Board      */
 #define CONFIG_ARM_THUMB	1	/* this is an ARM720TDMI */
-#define CONFIG_ARM7_REVD	1 	/* enable ARM720 REV.D Workarounds */
+#define CONFIG_ARM7_REVD	1	/* enable ARM720 REV.D Workarounds */
 
 #undef CONFIG_USE_IRQ			/* don't need them anymore */
 
@@ -80,7 +80,7 @@
 
 
 #define CONFIG_BOOTDELAY	3
-#define CONFIG_BOOTARGS    	"devfs=mount root=ramfs console=ttyS0,9600"
+#define CONFIG_BOOTARGS		"devfs=mount root=ramfs console=ttyS0,9600"
 /*#define CONFIG_ETHADDR	08:00:3e:26:0a:5a	*/
 /*#define CONFIG_NETMASK        255.255.0.0	*/
 /*#define CONFIG_IPADDR		172.22.2.128	*/
diff --git a/include/configs/innokom.h b/include/configs/innokom.h
index 5310e0d428..2b65052671 100644
--- a/include/configs/innokom.h
+++ b/include/configs/innokom.h
@@ -34,7 +34,7 @@
  * High Level Configuration Options
  * (easy to change)
  */
-#define CONFIG_PXA250 		1	/* This is an PXA250 CPU            */
+#define CONFIG_PXA250		1	/* This is an PXA250 CPU            */
 #define CONFIG_INNOKOM		1	/* on an Auerswald Innokom board    */
 
 #undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff      */
@@ -136,11 +136,11 @@
 /*
  * I2C bus
  */
-#define CONFIG_HARD_I2C 		1
-#define CFG_I2C_SPEED 			50000
-#define CFG_I2C_SLAVE 			0xfe
+#define CONFIG_HARD_I2C			1
+#define CFG_I2C_SPEED			50000
+#define CFG_I2C_SLAVE			0xfe
 
-#define CFG_ENV_IS_IN_EEPROM 		1
+#define CFG_ENV_IS_IN_EEPROM		1
 
 #define CFG_ENV_OFFSET			0x00	/* environment starts here  */
 #define CFG_ENV_SIZE			1024	/* 1 KiB                    */
diff --git a/include/configs/integratorcp.h b/include/configs/integratorcp.h
index e1d1483b71..347fa0201d 100644
--- a/include/configs/integratorcp.h
+++ b/include/configs/integratorcp.h
@@ -140,7 +140,7 @@ SIB at Block62 End Block62 address 0x24f80000
  */
 #define CONFIG_NR_DRAM_BANKS	1		/* we have 1 bank of DRAM */
 #define PHYS_SDRAM_1		0x00000000	/* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE 	0x08000000	/* 128 MB */
+#define PHYS_SDRAM_1_SIZE	0x08000000	/* 128 MB */
 
 /*-----------------------------------------------------------------------
  * FLASH and environment organization
@@ -156,9 +156,9 @@ SIB at Block62 End Block62 address 0x24f80000
 
  */
 #define CFG_FLASH_BASE		0x24000000
-#define CFG_MAX_FLASH_SECT 	64
+#define CFG_MAX_FLASH_SECT	64
 #define CFG_MAX_FLASH_BANKS	1		/* max number of memory banks */
-#define PHYS_FLASH_SIZE 	0x01000000	/* 16MB */
+#define PHYS_FLASH_SIZE		0x01000000	/* 16MB */
 #define CFG_FLASH_ERASE_TOUT	(2*CFG_HZ)	/* Timeout for Flash Erase */
 #define CFG_FLASH_WRITE_TOUT	(2*CFG_HZ)	/* Timeout for Flash Write */
 
diff --git a/include/configs/ixdp425.h b/include/configs/ixdp425.h
index bc5f9e19bd..b7c43fedf3 100644
--- a/include/configs/ixdp425.h
+++ b/include/configs/ixdp425.h
@@ -165,7 +165,7 @@
  */
 #define CFG_SDR_CONFIG		0xd
 #define CFG_SDR_MODE_CONFIG	0x1
-#define CFG_SDRAM_REFRESH_CNT 	0x81a
+#define CFG_SDRAM_REFRESH_CNT	0x81a
 
 /*
  * GPIO settings
@@ -178,7 +178,7 @@
  * FLASH and environment organization
  */
 #define CFG_MAX_FLASH_BANKS     1       /* max number of memory banks           */
-#define CFG_MAX_FLASH_SECT      128 	/* max number of sectors on one chip    */
+#define CFG_MAX_FLASH_SECT      128	/* max number of sectors on one chip    */
 
 #define CFG_FLASH_CFI				/* The flash is CFI compatible	*/
 #define CFG_FLASH_CFI_DRIVER			/* Use common CFI driver	*/
@@ -193,7 +193,7 @@
 
 #define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
 
-#define CFG_ENV_SECT_SIZE	0x20000 	/* size of one complete sector	*/
+#define CFG_ENV_SECT_SIZE	0x20000	/* size of one complete sector	*/
 #define CFG_ENV_ADDR		(PHYS_FLASH_1 + 0x20000)
 #define	CFG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/
 
diff --git a/include/configs/ixdpg425.h b/include/configs/ixdpg425.h
index a3be0b51e6..05dc841e35 100644
--- a/include/configs/ixdpg425.h
+++ b/include/configs/ixdpg425.h
@@ -201,13 +201,13 @@
  */
 #define CFG_SDR_CONFIG		0x18
 #define CFG_SDR_MODE_CONFIG	0x1
-#define CFG_SDRAM_REFRESH_CNT 	0x81a
+#define CFG_SDRAM_REFRESH_CNT	0x81a
 
 /*
  * FLASH and environment organization
  */
 #define CFG_MAX_FLASH_BANKS     1       /* max number of memory banks           */
-#define CFG_MAX_FLASH_SECT      128 	/* max number of sectors on one chip    */
+#define CFG_MAX_FLASH_SECT      128	/* max number of sectors on one chip    */
 
 #define CFG_FLASH_CFI				/* The flash is CFI compatible	*/
 #define CFG_FLASH_CFI_DRIVER			/* Use common CFI driver	*/
@@ -225,7 +225,7 @@
 
 #define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
 
-#define CFG_ENV_SECT_SIZE	0x20000 	/* size of one complete sector	*/
+#define CFG_ENV_SECT_SIZE	0x20000	/* size of one complete sector	*/
 #define CFG_ENV_ADDR		(PHYS_FLASH_1 + 0x40000)
 #define	CFG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/
 
diff --git a/include/configs/jupiter.h b/include/configs/jupiter.h
index 0ac3e7e7b9..980e9fe9ce 100644
--- a/include/configs/jupiter.h
+++ b/include/configs/jupiter.h
@@ -142,7 +142,7 @@
 /*
  * IPB Bus clocking configuration.
  */
-#undef CFG_IPBSPEED_133   	/* define for 133MHz speed */
+#undef CFG_IPBSPEED_133			/* define for 133MHz speed */
 
 #if 0
 /* pass open firmware flat tree */
diff --git a/include/configs/kilauea.h b/include/configs/kilauea.h
index c7c42a4cdf..a59676870f 100644
--- a/include/configs/kilauea.h
+++ b/include/configs/kilauea.h
@@ -108,7 +108,7 @@
 #define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
 
 #ifdef CFG_ENV_IS_IN_FLASH
-#define CFG_ENV_SECT_SIZE	0x20000 	/* size of one complete sector	*/
+#define CFG_ENV_SECT_SIZE	0x20000	/* size of one complete sector	*/
 #define CFG_ENV_ADDR		(CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
 #define	CFG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
 
diff --git a/include/configs/korat.h b/include/configs/korat.h
index 48d73ac376..765566697f 100644
--- a/include/configs/korat.h
+++ b/include/configs/korat.h
@@ -225,7 +225,7 @@
 #define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
 
 #define CONFIG_HAS_ETH0
-#define CFG_RX_ETH_BUFFER	32	/* Number of ethernet rx 	*/
+#define CFG_RX_ETH_BUFFER	32	/* Number of ethernet rx	*/
 					/*   buffers & descriptors	*/
 #define CONFIG_NET_MULTI	1
 #define CONFIG_HAS_ETH1		1	/* add support for "eth1addr"	*/
@@ -308,7 +308,7 @@
 #define CFG_CBSIZE	        256	/* Console I/O Buffer Size	*/
 #endif
 #define CFG_PBSIZE              (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
-					/* Print Buffer Size 		*/
+					/* Print Buffer Size		*/
 #define CFG_MAXARGS	        16	/* max number of command args	*/
 #define CFG_BARGSIZE	        CFG_CBSIZE /* Boot Argument Buffer Size	*/
 
@@ -339,7 +339,7 @@
 #define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
 #define CFG_PCI_CACHE_LINE_SIZE	0	/* to avoid problems with PNP	*/
 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup	*/
-#define CFG_PCI_TARGBASE	0x80000000 	/* PCIaddr mapped to	*/
+#define CFG_PCI_TARGBASE	0x80000000	/* PCIaddr mapped to	*/
 						/*   CFG_PCI_MEMBASE	*/
 /* Board-specific PCI */
 #define CFG_PCI_TARGET_INIT
diff --git a/include/configs/lart.h b/include/configs/lart.h
index 8f18c9f1b1..4570398cd4 100644
--- a/include/configs/lart.h
+++ b/include/configs/lart.h
@@ -76,7 +76,7 @@
 
 
 #define CONFIG_BOOTDELAY	3
-#define CONFIG_BOOTARGS    	"root=ramfs devfs=mount console=ttySA0,9600"
+#define CONFIG_BOOTARGS		"root=ramfs devfs=mount console=ttySA0,9600"
 #define CONFIG_ETHADDR		08:00:3e:26:0a:5b
 #define CONFIG_NETMASK          255.255.0.0
 #define CONFIG_IPADDR		172.22.2.131
diff --git a/include/configs/linkstation.h b/include/configs/linkstation.h
index 518186b08c..d3908b9eaf 100644
--- a/include/configs/linkstation.h
+++ b/include/configs/linkstation.h
@@ -114,9 +114,9 @@
 #define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
 #define CFG_LOAD_ADDR		0x00800000	/* Default load address: 8 MB	*/
 
-#define CONFIG_BOOTCOMMAND  	"run bootcmd1"
+#define CONFIG_BOOTCOMMAND	"run bootcmd1"
 #define CONFIG_BOOTARGS		"root=/dev/sda1 console=ttyS1,57600 netconsole=@192.168.1.7/eth0,@192.168.1.1/00:50:BF:A4:59:71 rtc-rs5c372.probe=0,0x32 debug"
-#define CONFIG_NFSBOOTCOMMAND  	"bootp;run nfsargs;bootm"
+#define CONFIG_NFSBOOTCOMMAND	"bootp;run nfsargs;bootm"
 
 #define CFG_CONSOLE_IS_IN_ENV
 
@@ -214,28 +214,28 @@
  * (Set up by the startup code)
  * Please note that CFG_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE	    	0x00000000
+#define CFG_SDRAM_BASE		0x00000000
 
-#define CFG_FLASH_BASE      	0xFFC00000
+#define CFG_FLASH_BASE		0xFFC00000
 #define CFG_FLASH_SIZE		0x00400000
-#define CFG_MONITOR_BASE    	TEXT_BASE
+#define CFG_MONITOR_BASE	TEXT_BASE
 
-#define CFG_RESET_ADDRESS   	0xFFF00100
-#define CFG_EUMB_ADDR	    	0x80000000
+#define CFG_RESET_ADDRESS	0xFFF00100
+#define CFG_EUMB_ADDR		0x80000000
 #define CFG_PCI_MEM_ADDR	0xB0000000
 #define CFG_MISC_REGION_ADDR	0xFE000000
 
-#define CFG_MONITOR_LEN     	0x00040000	/* 256 kB			*/
-#define CFG_MALLOC_LEN      	(512 << 10)	/* Reserve some kB for malloc()	*/
+#define CFG_MONITOR_LEN		0x00040000	/* 256 kB			*/
+#define CFG_MALLOC_LEN		(512 << 10)	/* Reserve some kB for malloc()	*/
 
-#define CFG_MEMTEST_START   	0x00100000	/* memtest works on		*/
-#define CFG_MEMTEST_END	    	0x00800000	/* 1M ... 8M in DRAM		*/
+#define CFG_MEMTEST_START	0x00100000	/* memtest works on		*/
+#define CFG_MEMTEST_END		0x00800000	/* 1M ... 8M in DRAM		*/
 
 /* Maximum amount of RAM */
 #if defined(CONFIG_HLAN) || defined(CONFIG_LAN)
-#define CFG_MAX_RAM_SIZE    	0x04000000	/* 64MB of SDRAM  */
+#define CFG_MAX_RAM_SIZE	0x04000000	/* 64MB of SDRAM  */
 #elif defined(CONFIG_HGLAN) || defined(CONFIG_HTGL)
-#define CFG_MAX_RAM_SIZE    	0x08000000	/* 128MB of SDRAM */
+#define CFG_MAX_RAM_SIZE	0x08000000	/* 128MB of SDRAM */
 #else
 #error Unknown LinkStation type
 #endif
diff --git a/include/configs/logodl.h b/include/configs/logodl.h
index 2b2d37751e..047b4a4f71 100644
--- a/include/configs/logodl.h
+++ b/include/configs/logodl.h
@@ -34,7 +34,7 @@
  * High Level Configuration Options
  * (easy to change)
  */
-#define CONFIG_PXA250 		1	/* This is an PXA250 CPU            */
+#define CONFIG_PXA250		1	/* This is an PXA250 CPU            */
 #define CONFIG_GEALOG		1	/* on a Logotronic GEALOG SG board  */
 
 #undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff      */
diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h
index 1f669aa8f6..cf406c8c0d 100644
--- a/include/configs/lwmon5.h
+++ b/include/configs/lwmon5.h
@@ -88,15 +88,20 @@
 						/* unused GPT0 COMP reg	*/
 #define CFG_MEM_TOP_HIDE	(4 << 10) /* don't use last 4kbytes	*/
 					/* 440EPx errata CHIP 11	*/
+#define CFG_OCM_SIZE		(16 << 10)
 
 /* Additional registers for watchdog timer post test */
 
 #define CFG_WATCHDOG_TIME_ADDR	(CFG_PERIPHERAL_BASE + GPT0_MASK2)
 #define CFG_WATCHDOG_FLAGS_ADDR	(CFG_PERIPHERAL_BASE + GPT0_MASK1)
 #define CFG_DSPIC_TEST_ADDR	CFG_WATCHDOG_FLAGS_ADDR
+#define CFG_OCM_STATUS_ADDR	CFG_WATCHDOG_FLAGS_ADDR
 #define CFG_WATCHDOG_MAGIC	0x12480000
 #define CFG_WATCHDOG_MAGIC_MASK	0xFFFF0000
 #define CFG_DSPIC_TEST_MASK	0x00000001
+#define CFG_OCM_STATUS_OK	0x00009A00
+#define CFG_OCM_STATUS_FAIL	0x0000A300
+#define CFG_OCM_STATUS_MASK	0x0000FF00
 
 /*-----------------------------------------------------------------------
  * Serial Port
@@ -162,6 +167,7 @@
 				 CFG_POST_FPU	   | \
 				 CFG_POST_I2C	   | \
 				 CFG_POST_MEMORY   | \
+				 CFG_POST_OCM      | \
 				 CFG_POST_RTC      | \
 				 CFG_POST_SPR      | \
 				 CFG_POST_UART     | \
diff --git a/include/configs/makalu.h b/include/configs/makalu.h
index 67243d4e40..af066f3a8a 100644
--- a/include/configs/makalu.h
+++ b/include/configs/makalu.h
@@ -101,7 +101,7 @@
 #define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
 
 #ifdef CFG_ENV_IS_IN_FLASH
-#define CFG_ENV_SECT_SIZE	0x20000 	/* size of one complete sector	*/
+#define CFG_ENV_SECT_SIZE	0x20000	/* size of one complete sector	*/
 #define CFG_ENV_ADDR		(CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
 #define	CFG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
 
diff --git a/include/configs/mcu25.h b/include/configs/mcu25.h
index c5b6e8f68d..4e9645e585 100644
--- a/include/configs/mcu25.h
+++ b/include/configs/mcu25.h
@@ -45,7 +45,7 @@
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
 *----------------------------------------------------------------------*/
-#define CFG_MONITOR_LEN 	(320 * 1024) /* Reserve 320 kB for Monitor */
+#define CFG_MONITOR_LEN		(320 * 1024) /* Reserve 320 kB for Monitor */
 #define CFG_MALLOC_LEN		(256 * 1024) /* Reserve 256 kB for malloc() */
 
 
@@ -54,13 +54,13 @@
 #define CFG_MONITOR_BASE	TEXT_BASE
 
 /* ... with on-chip memory here (4KBytes) */
-#define CFG_OCM_DATA_ADDR 0xF4000000
-#define CFG_OCM_DATA_SIZE 0x00001000
+#define CFG_OCM_DATA_ADDR	0xF4000000
+#define CFG_OCM_DATA_SIZE	0x00001000
 /* Do not set up locked dcache as init ram. */
 #undef CFG_INIT_DCACHE_CS
 
 /* Use the On-Chip-Memory (OCM) as a temporary stack for the startup code. */
-#define CFG_TEMP_STACK_OCM 1
+#define CFG_TEMP_STACK_OCM	1
 
 #define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR	/* OCM		*/
 #define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE
@@ -127,7 +127,7 @@
 
 #ifdef  CFG_ENV_IS_IN_EEPROM
 /* Put the environment after the SDRAM configuration */
-#define PROM_SIZE 	2048
+#define PROM_SIZE	2048
 #define CFG_ENV_OFFSET	 512
 #define CFG_ENV_SIZE	(PROM_SIZE-CFG_ENV_OFFSET)
 #endif
diff --git a/include/configs/mecp5200.h b/include/configs/mecp5200.h
index 49919fbafb..5218d9ca97 100644
--- a/include/configs/mecp5200.h
+++ b/include/configs/mecp5200.h
@@ -154,7 +154,7 @@
 /*
  * IPB Bus clocking configuration.
  */
-#undef CFG_IPBSPEED_133   		/* define for 133MHz speed */
+#undef CFG_IPBSPEED_133			/* define for 133MHz speed */
 #endif
 /*
  * I2C configuration
diff --git a/include/configs/mgcoge.h b/include/configs/mgcoge.h
index 2924acc7a3..59ff96b5c5 100644
--- a/include/configs/mgcoge.h
+++ b/include/configs/mgcoge.h
@@ -188,13 +188,13 @@
 #define CFG_HRCW_MASTER		0x0604b211
 
 /* No slaves */
-#define CFG_HRCW_SLAVE1 	0
-#define CFG_HRCW_SLAVE2 	0
-#define CFG_HRCW_SLAVE3 	0
-#define CFG_HRCW_SLAVE4 	0
-#define CFG_HRCW_SLAVE5 	0
-#define CFG_HRCW_SLAVE6 	0
-#define CFG_HRCW_SLAVE7 	0
+#define CFG_HRCW_SLAVE1		0
+#define CFG_HRCW_SLAVE2		0
+#define CFG_HRCW_SLAVE3		0
+#define CFG_HRCW_SLAVE4		0
+#define CFG_HRCW_SLAVE5		0
+#define CFG_HRCW_SLAVE6		0
+#define CFG_HRCW_SLAVE7		0
 
 #define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH */
 #define BOOTFLAG_WARM		0x02	/* Software reboot                  */
diff --git a/include/configs/modnet50.h b/include/configs/modnet50.h
index 4461bdfd18..5159897db3 100644
--- a/include/configs/modnet50.h
+++ b/include/configs/modnet50.h
@@ -90,7 +90,8 @@
 /*#define CONFIG_BOOTDELAY	10*/
 /* args and cmd for uClinux-image @ 0x10020000, ramdisk-image @ 0x100a0000 */
 #define CONFIG_BOOTCOMMAND	"bootm 0x10020000 0x100a0000"
-#define CONFIG_BOOTARGS    	"console=ttyS0,38400 initrd=0x100a0040,530K root=/dev/ram keepinitrd"
+#define CONFIG_BOOTARGS		"console=ttyS0,38400 initrd=0x100a0040,530K " \
+					"root=/dev/ram keepinitrd"
 
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE	230400		/* speed to run kgdb serial port */
diff --git a/include/configs/ms7720se.h b/include/configs/ms7720se.h
index 9c94c4e793..5e79a27111 100644
--- a/include/configs/ms7720se.h
+++ b/include/configs/ms7720se.h
@@ -96,7 +96,7 @@
 #define CFG_ENV_SECT_SIZE	(64 * 1024)
 #define CFG_ENV_SIZE		CFG_ENV_SECT_SIZE
 #define CFG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
-#define CFG_FLASH_ERASE_TOUT  	120000
+#define CFG_FLASH_ERASE_TOUT	120000
 #define CFG_FLASH_WRITE_TOUT	500
 
 /* Board Clock */
diff --git a/include/configs/ms7722se.h b/include/configs/ms7722se.h
index 85380373da..8d92a13e1c 100644
--- a/include/configs/ms7722se.h
+++ b/include/configs/ms7722se.h
@@ -39,7 +39,7 @@
 
 #define CONFIG_BAUDRATE		115200
 #define CONFIG_BOOTDELAY	3
-#define CONFIG_BOOTARGS    	"console=ttySC0,115200 root=1f01"
+#define CONFIG_BOOTARGS		"console=ttySC0,115200 root=1f01"
 #define CONFIG_NETMASK          255.255.255.0
 #define CONFIG_IPADDR		192.168.0.22
 #define CONFIG_SERVERIP		192.168.0.1
@@ -86,7 +86,7 @@
 #define CFG_LOAD_ADDR	(CFG_SDRAM_BASE + 4 * 1024 * 1024)	/* default load address for scripts ?!? */
 
 #define CFG_MONITOR_BASE	(MS7722SE_FLASH_BASE_1)	/* Address of u-boot image
-						   	in Flash (NOT run time address in SDRAM) ?!? */
+							in Flash (NOT run time address in SDRAM) ?!? */
 #define CFG_MONITOR_LEN	(128 * 1024)		/* */
 #define CFG_MALLOC_LEN	(256 * 1024)		/* Size of DRAM reserved for malloc() use */
 #define CFG_GBL_DATA_SIZE	(256)		/* size in bytes reserved for initial data */
@@ -101,7 +101,7 @@
 #define CFG_FLASH_BASE		(MS7722SE_FLASH_BASE_1)	/* Physical start address of Flash memory */
 
 #define CFG_MAX_FLASH_SECT	150		/* Max number of sectors on each
-				   			Flash chip */
+							Flash chip */
 
 /* if you use all NOR Flash , you change dip-switch. Please see MS7722SE01 Manual. */
 #define CFG_MAX_FLASH_BANKS	2
@@ -123,7 +123,7 @@
 #define CFG_ENV_SECT_SIZE	(8 * 1024)
 #define CFG_ENV_SIZE		(CFG_ENV_SECT_SIZE)
 #define CFG_ENV_ADDR		(CFG_FLASH_BASE + (1 * CFG_ENV_SECT_SIZE))
-#define CFG_ENV_OFFSET		(CFG_ENV_ADDR - CFG_FLASH_BASE) 	/* Offset of env Flash sector relative to CFG_FLASH_BASE */
+#define CFG_ENV_OFFSET		(CFG_ENV_ADDR - CFG_FLASH_BASE)	/* Offset of env Flash sector relative to CFG_FLASH_BASE */
 #define CFG_ENV_SIZE_REDUND	(CFG_ENV_SECT_SIZE)
 #define CFG_ENV_ADDR_REDUND	(CFG_FLASH_BASE + (2 * CFG_ENV_SECT_SIZE))
 
diff --git a/include/configs/ms7750se.h b/include/configs/ms7750se.h
index a25364dd38..3000c77c11 100644
--- a/include/configs/ms7750se.h
+++ b/include/configs/ms7750se.h
@@ -48,7 +48,7 @@
 #define BOARD_LATE_INIT		1
 
 #define CONFIG_BOOTDELAY	-1
-#define CONFIG_BOOTARGS    	"console=ttySC0,38400"
+#define CONFIG_BOOTARGS		"console=ttySC0,38400"
 #define CONFIG_ENV_OVERWRITE	1
 
 /* SDRAM */
@@ -71,8 +71,8 @@
 /* #define CFG_FLASH_BASE		(0xA1000000)*/
 #define CFG_FLASH_BASE		(0xA0000000)
 #define CFG_MAX_FLASH_BANKS	(1)	/* Max number of
-				 	 * Flash memory banks
-				 	 */
+					 * Flash memory banks
+					 */
 #define CFG_MAX_FLASH_SECT	142
 #define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE }
 
@@ -96,7 +96,7 @@
 #define CFG_ENV_SECT_SIZE	0x20000
 #define CFG_ENV_SIZE		(CFG_ENV_SECT_SIZE)
 #define CFG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
-#define CFG_FLASH_ERASE_TOUT  	120000
+#define CFG_FLASH_ERASE_TOUT	120000
 #define CFG_FLASH_WRITE_TOUT	500
 
 /* Board Clock */
diff --git a/include/configs/netstar.h b/include/configs/netstar.h
index a48893d1eb..d4deda407f 100644
--- a/include/configs/netstar.h
+++ b/include/configs/netstar.h
@@ -180,16 +180,16 @@
 	"if test -n $swapos; then "						\
 		"setenv swapos; saveenv; "					\
 	"else "									\
-		"if test $ospart -eq 0; then setenv ospart 1;" 			\
-			"else setenv ospart 0; 		fi; "			\
+		"if test $ospart -eq 0; then setenv ospart 1;"			\
+			"else setenv ospart 0;		fi; "			\
 	"fi\0"									\
 	"nfsargs=setenv bootargs $bootargs "					\
-		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off " 	\
+		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off "	\
 		"nfsroot=$rootpath root=/dev/nfs\0"				\
 	"flashargs=run setpart;setenv bootargs $bootargs "			\
 		"root=mtd:rootfs$ospart ro "					\
 		"rootfstype=jffs2\0"						\
-	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off\0" 		\
+	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off\0"		\
 	"fboot=run flashargs;nboot kernel$ospart\0"				\
 	"nboot=bootp;run nfsargs;tftp\0"
 
diff --git a/include/configs/ns9750dev.h b/include/configs/ns9750dev.h
index 1d691f9731..f30cb46cf7 100644
--- a/include/configs/ns9750dev.h
+++ b/include/configs/ns9750dev.h
@@ -62,7 +62,7 @@
 /*
  * select serial console configuration
  */
-#define CONFIG_CONS_INDEX          1 		/* Port B */
+#define CONFIG_CONS_INDEX          1		/* Port B */
 
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
@@ -93,7 +93,7 @@
 
 
 #define CONFIG_BOOTDELAY	3
-/*#define CONFIG_BOOTARGS    	"root=ramfs devfs=mount console=ttySA0,9600" */
+/*#define CONFIG_BOOTARGS	"root=ramfs devfs=mount console=ttySA0,9600" */
 
 #define CONFIG_ETHADDR		00:04:f3:ff:ff:fb /*@TODO unset */
 #define CONFIG_NETMASK          255.255.255.0
diff --git a/include/configs/p3mx.h b/include/configs/p3mx.h
index 45dc3432db..0dac5161ba 100644
--- a/include/configs/p3mx.h
+++ b/include/configs/p3mx.h
@@ -138,9 +138,9 @@
 
 #define CFG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/
 #if defined (CONFIG_P3M750)
-#define CFG_ENV_SECT_SIZE	0x20000 	/* one sector (1 device)*/
+#define CFG_ENV_SECT_SIZE	0x20000	/* one sector (1 device)		*/
 #elif defined (CONFIG_P3M7448)
-#define CFG_ENV_SECT_SIZE	0x40000 	/* two sectors (2 devices parallel */
+#define CFG_ENV_SECT_SIZE	0x40000	/* two sectors (2 devices parallel	*/
 #endif
 #define	CFG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/
 #define CFG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
diff --git a/include/configs/pcu_e.h b/include/configs/pcu_e.h
index e3c884392c..7e393f7611 100644
--- a/include/configs/pcu_e.h
+++ b/include/configs/pcu_e.h
@@ -228,7 +228,7 @@
 #if 0
 /* Start port with environment in flash; switch to SPI EEPROM later */
 #define	CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_SIZE		0x2000	/* Total Size of Environment 		*/
+#define CFG_ENV_SIZE		0x2000	/* Total Size of Environment		*/
 #define CFG_ENV_ADDR	    0xFFFFE000	/* Address    of Environment Sector	*/
 #define CFG_ENV_SECT_SIZE	0x2000	/* use the top-most 8k boot sector	*/
 #define	CFG_ENV_IS_EMBEDDED	1	/* short-cut compile-time test		*/
@@ -313,7 +313,7 @@
 /* 0x01800000 */
 #define CFG_SCCR	(SCCR_COM00	| /*SCCR_TBS|*/		\
 			 SCCR_RTDIV	|   SCCR_RTSEL	  |	\
-			 /*SCCR_CRQEN|*/  /*SCCR_PRQEN|*/ 	\
+			 /*SCCR_CRQEN|*/  /*SCCR_PRQEN|*/	\
 			 SCCR_EBDF00 |   SCCR_DFSYNC00 |	\
 			 SCCR_DFBRG00	|   SCCR_DFNL000  |	\
 			 SCCR_DFNH000	|   SCCR_DFLCD100 |	\
diff --git a/include/configs/pdnb3.h b/include/configs/pdnb3.h
index ac72f983ea..aca70dce69 100644
--- a/include/configs/pdnb3.h
+++ b/include/configs/pdnb3.h
@@ -211,7 +211,7 @@
  */
 #define CFG_SDR_CONFIG		0x18
 #define CFG_SDR_MODE_CONFIG	0x1
-#define CFG_SDRAM_REFRESH_CNT 	0x81a
+#define CFG_SDRAM_REFRESH_CNT	0x81a
 
 /*
  * FLASH and environment organization
@@ -251,7 +251,7 @@
 #define CFG_ENV_SECT_SIZE	0x20000 /* size of one complete sector		*/
 #define	CFG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
 #else
-#define CFG_ENV_SECT_SIZE	0x1000 	/* size of one complete sector		*/
+#define CFG_ENV_SECT_SIZE	0x1000	/* size of one complete sector		*/
 #define	CFG_ENV_SIZE		0x1000	/* Total Size of Environment Sector	*/
 
 /* Address and size of Redundant Environment Sector	*/
diff --git a/include/configs/ppmc8260.h b/include/configs/ppmc8260.h
index fb5ae99e4c..56b4d92f1a 100644
--- a/include/configs/ppmc8260.h
+++ b/include/configs/ppmc8260.h
@@ -237,7 +237,7 @@
 /* Define a command string that is automatically executed when no character
  * is read on the console interface withing "Boot Delay" after reset.
  */
-#undef	CONFIG_BOOT_ROOT_INITRD 	/* Use ram disk for the root file system */
+#undef	CONFIG_BOOT_ROOT_INITRD		/* Use ram disk for the root file system */
 #define	CONFIG_BOOT_ROOT_NFS		/* Use a NFS mounted root file system */
 
 #ifdef CONFIG_BOOT_ROOT_INITRD
diff --git a/include/configs/r7780mp.h b/include/configs/r7780mp.h
index 42787f4fd1..4e895806ae 100644
--- a/include/configs/r7780mp.h
+++ b/include/configs/r7780mp.h
@@ -113,7 +113,7 @@
 #define CFG_ENV_SECT_SIZE	(16 * 1024)
 #define CFG_ENV_SIZE		(CFG_ENV_SECT_SIZE)
 #define CFG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
-#define CFG_FLASH_ERASE_TOUT  	120000
+#define CFG_FLASH_ERASE_TOUT	120000
 #define CFG_FLASH_WRITE_TOUT	500
 
 /* Board Clock */
diff --git a/include/configs/rmu.h b/include/configs/rmu.h
index 2ca60b731e..28fb7c3318 100644
--- a/include/configs/rmu.h
+++ b/include/configs/rmu.h
@@ -51,9 +51,9 @@
 
 #undef	CONFIG_BOOTARGS
 #define CONFIG_BOOTCOMMAND							\
-	"bootp; " 								\
-	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " 	\
-	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " 	\
+	"bootp; "								\
+	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "	\
 	"bootm"
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
@@ -399,7 +399,7 @@
 #define BCSR3	(CFG_BCSR_BASE + 3)
 
 #define BCSR0_ENMONXCVR	0x01	/* Monitor XVCR Control */
-#define BCSR0_ENNVRAM	0x02 	/* CS4# Control */
+#define BCSR0_ENNVRAM	0x02	/* CS4# Control */
 #define BCSR0_LED5	0x04	/* LED5 control 0='on' 1='off' */
 #define BCSR0_LED4	0x08	/* LED4 control 0='on' 1='off' */
 #define BCSR0_FULLDPLX	0x10	/* Ethernet XCVR Control */
diff --git a/include/configs/rsdproto.h b/include/configs/rsdproto.h
index 40a05fa5e8..6251383f55 100644
--- a/include/configs/rsdproto.h
+++ b/include/configs/rsdproto.h
@@ -53,7 +53,7 @@
  */
 #undef	CONFIG_CONS_ON_SMC		/* define if console on SMC */
 #define	CONFIG_CONS_ON_SCC		/* define if console on SCC */
-#undef 	CONFIG_CONS_NONE		/* define if console on neither */
+#undef	CONFIG_CONS_NONE		/* define if console on neither */
 #define CONFIG_CONS_INDEX	1	/* which SMC/SCC channel for console */
 
 /*
@@ -91,7 +91,7 @@
 #define CONFIG_ENV_OVERWRITE
 
 /* enable I2C */
-#define CONFIG_HARD_I2C        	1	/* I2C with hardware support */
+#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
 #define CFG_I2C_SPEED		50000	/* I2C speed and slave address */
 #define CFG_I2C_SLAVE		0x30
 
@@ -128,7 +128,7 @@
 #define CFG_RSD_BOOT_LOW 1
 
 #define CONFIG_BOOTDELAY	5
-#define CONFIG_BOOTARGS    	"devfs=mount root=ramfs"
+#define CONFIG_BOOTARGS		"devfs=mount root=ramfs"
 #define CONFIG_ETHADDR		08:00:3e:26:0a:5a
 #define CONFIG_NETMASK          255.255.0.0
 
@@ -176,14 +176,14 @@
 #define PHYS_SDRAM_LOCAL	0x40000000 /* SDRAM (Local Bus) */
 #define PHYS_SDRAM_LOCAL_SIZE	0x04000000 /* 64 MB */
 
-#define PHYS_DPRAM_PCI       	0xE8000000 /* DPRAM PPC/PCI */
-#define PHYS_DPRAM_PCI_SIZE   	0x00020000 /* 128 KB */
+#define PHYS_DPRAM_PCI		0xE8000000 /* DPRAM PPC/PCI */
+#define PHYS_DPRAM_PCI_SIZE	0x00020000 /* 128 KB */
 
 /*#define PHYS_DPRAM_PCI_SEM	0x04020000 / * DPRAM PPC/PCI Semaphore */
 /*#define PHYS_DPRAM_PCI_SEM_SIZE	0x00000001 / * 1 Byte */
 
-#define PHYS_DPRAM_SHARC       	0xE8100000 /* DPRAM PPC/Sharc */
-#define PHYS_DPRAM_SHARC_SIZE 	0x00040000 /* 256 KB */
+#define PHYS_DPRAM_SHARC	0xE8100000 /* DPRAM PPC/Sharc */
+#define PHYS_DPRAM_SHARC_SIZE	0x00040000 /* 256 KB */
 
 /*#define PHYS_DPRAM_SHARC_SEM	0x04140000 / * DPRAM PPC/Sharc Semaphore */
 /*#define PHYS_DPRAM_SHARC_SEM_SIZE 0x00000001 / * 1 Byte */
diff --git a/include/configs/sacsng.h b/include/configs/sacsng.h
index ec7d34aa9e..4974fb43f7 100644
--- a/include/configs/sacsng.h
+++ b/include/configs/sacsng.h
@@ -441,7 +441,7 @@
 /* Define a command string that is automatically executed when no character
  * is read on the console interface withing "Boot Delay" after reset.
  */
-#undef	CONFIG_BOOT_ROOT_INITRD 	/* Use ram disk for the root file system */
+#undef	CONFIG_BOOT_ROOT_INITRD		/* Use ram disk for the root file system */
 #define	CONFIG_BOOT_ROOT_NFS		/* Use a NFS mounted root file system */
 
 #ifdef CONFIG_BOOT_ROOT_INITRD
diff --git a/include/configs/sbc2410x.h b/include/configs/sbc2410x.h
index 9b05bd6c8c..08cadf6271 100644
--- a/include/configs/sbc2410x.h
+++ b/include/configs/sbc2410x.h
@@ -106,7 +106,9 @@
 
 
 #define CONFIG_BOOTDELAY	3
-#define CONFIG_BOOTARGS    	"console=ttySAC0 root=/dev/nfs nfsroot=192.168.0.1:/friendly-arm/rootfs_netserv ip=192.168.0.69:192.168.0.1:192.168.0.1:255.255.255.0:debian:eth0:off"
+#define CONFIG_BOOTARGS		"console=ttySAC0 root=/dev/nfs " \
+		"nfsroot=192.168.0.1:/friendly-arm/rootfs_netserv " \
+		"ip=192.168.0.69:192.168.0.1:192.168.0.1:255.255.255.0:debian:eth0:off"
 #define CONFIG_ETHADDR	        08:00:3e:26:0a:5b
 #define CONFIG_NETMASK          255.255.255.0
 #define CONFIG_IPADDR		192.168.0.69
@@ -205,7 +207,7 @@
 #define ADDR_PAGE 2
 #define ADDR_COLUMN_PAGE 3
 
-#define NAND_ChipID_UNKNOWN 	0x00
+#define NAND_ChipID_UNKNOWN	0x00
 #define NAND_MAX_FLOORS 1
 #define NAND_MAX_CHIPS 1
 
diff --git a/include/configs/sbc8260.h b/include/configs/sbc8260.h
index 60633987f6..7993137211 100644
--- a/include/configs/sbc8260.h
+++ b/include/configs/sbc8260.h
@@ -387,7 +387,7 @@
 /* Define a command string that is automatically executed when no character
  * is read on the console interface withing "Boot Delay" after reset.
  */
-#undef	CONFIG_BOOT_ROOT_INITRD 	/* Use ram disk for the root file system */
+#undef	CONFIG_BOOT_ROOT_INITRD		/* Use ram disk for the root file system */
 #define	CONFIG_BOOT_ROOT_NFS		/* Use a NFS mounted root file system */
 
 #ifdef CONFIG_BOOT_ROOT_INITRD
diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h
index c84b70a87d..358fc0208e 100644
--- a/include/configs/sbc8548.h
+++ b/include/configs/sbc8548.h
@@ -176,7 +176,7 @@
 #define CFG_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
 #define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
 
-#define CFG_MONITOR_BASE    	TEXT_BASE	/* start of monitor */
+#define CFG_MONITOR_BASE	TEXT_BASE	/* start of monitor */
 
 #define CFG_FLASH_CFI_DRIVER
 #define CFG_FLASH_CFI
diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h
index 20da73e0fa..3cd9ff80f6 100644
--- a/include/configs/sbc8641d.h
+++ b/include/configs/sbc8641d.h
@@ -55,13 +55,13 @@
 #define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
 #define CONFIG_FSL_LAW		1	/* Use common FSL init code */
 
-#define CONFIG_TSEC_ENET 		/* tsec ethernet support */
+#define CONFIG_TSEC_ENET		/* tsec ethernet support */
 #define CONFIG_ENV_OVERWRITE
 
 #undef CONFIG_SPD_EEPROM		/* Do not use SPD EEPROM for DDR setup*/
 #undef CONFIG_DDR_DLL			/* possible DLL fix needed */
 #define CONFIG_DDR_2T_TIMING		/* Sets the 2T timing bit */
-#undef CONFIG_DDR_ECC  			/* only for ECC DDR module */
+#undef CONFIG_DDR_ECC			/* only for ECC DDR module */
 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
 #define CONFIG_MEM_INIT_VALUE		0xDeadBeef
 #define CONFIG_NUM_DDR_CONTROLLERS     2
@@ -94,7 +94,7 @@
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  */
-#define CFG_CCSRBAR_DEFAULT 	0xff700000	/* CCSRBAR Default */
+#define CFG_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
 #define CFG_CCSRBAR		0xf8000000	/* relocated CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */
 
@@ -219,7 +219,7 @@
 #undef	CFG_FLASH_CHECKSUM
 #define CFG_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
 #define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
-#define CFG_MONITOR_BASE    	TEXT_BASE	/* start of monitor */
+#define CFG_MONITOR_BASE	TEXT_BASE	/* start of monitor */
 
 #define CFG_FLASH_CFI_DRIVER
 #define CFG_FLASH_CFI
@@ -236,14 +236,14 @@
 #else
 #define CFG_INIT_RAM_ADDR	0xf8400000	/* Initial RAM address */
 #endif
-#define CFG_INIT_RAM_END    	0x4000	    	/* End of used area in RAM */
+#define CFG_INIT_RAM_END	0x4000		/* End of used area in RAM */
 
-#define CFG_GBL_DATA_SIZE  	128		/* num bytes initial data */
+#define CFG_GBL_DATA_SIZE	128		/* num bytes initial data */
 #define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 #define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
 
-#define CFG_MONITOR_LEN	    	(256 * 1024)    /* Reserve 256 kB for Mon */
-#define CFG_MALLOC_LEN	    	(128 * 1024)    /* Reserved for malloc */
+#define CFG_MONITOR_LEN		(256 * 1024)    /* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN		(128 * 1024)    /* Reserved for malloc */
 
 /* Serial Port */
 #define CONFIG_CONS_INDEX     1
@@ -323,7 +323,7 @@
 #undef CFG_SCSI_SCAN_BUS_REVERSE
 
 #define CONFIG_NET_MULTI
-#define CONFIG_PCI_PNP	               	/* do pci plug-and-play */
+#define CONFIG_PCI_PNP			/* do pci plug-and-play */
 
 #undef CONFIG_EEPRO100
 #undef CONFIG_TULIP
@@ -331,7 +331,7 @@
 #if !defined(CONFIG_PCI_PNP)
     #define PCI_ENET0_IOADDR	0xe0000000
     #define PCI_ENET0_MEMADDR	0xe0000000
-    #define PCI_IDSEL_NUMBER	0x0c 	/* slot0->3(IDSEL)=12->15 */
+    #define PCI_IDSEL_NUMBER	0x0c	/* slot0->3(IDSEL)=12->15 */
 #endif
 
 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
@@ -343,7 +343,7 @@
 #define CONFIG_SATA_ULI5288
 #define CFG_SCSI_MAX_SCSI_ID	4
 #define CFG_SCSI_MAX_LUN	1
-#define CFG_SCSI_MAX_DEVICE 	(CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN)
+#define CFG_SCSI_MAX_DEVICE	(CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN)
 #define CFG_SCSI_MAXDEVICE	CFG_SCSI_MAX_DEVICE
 #endif
 
@@ -352,7 +352,7 @@
 #if defined(CONFIG_TSEC_ENET)
 
 #ifndef CONFIG_NET_MULTI
-#define CONFIG_NET_MULTI 	1
+#define CONFIG_NET_MULTI	1
 #endif
 
 /* #define CONFIG_MII		1 */	/* MII PHY management */
diff --git a/include/configs/sc520_cdp.h b/include/configs/sc520_cdp.h
index 4df461dd96..0e830b878d 100644
--- a/include/configs/sc520_cdp.h
+++ b/include/configs/sc520_cdp.h
@@ -87,7 +87,7 @@
 #define CONFIG_CMD_EEPROM
 
 #define CONFIG_BOOTDELAY	15
-#define CONFIG_BOOTARGS    	"root=/dev/mtdblock0 console=ttyS0,9600"
+#define CONFIG_BOOTARGS		"root=/dev/mtdblock0 console=ttyS0,9600"
 /* #define CONFIG_BOOTCOMMAND	"bootm 38000000" */
 
 #if defined(CONFIG_CMD_KGDB)
diff --git a/include/configs/sc520_spunk.h b/include/configs/sc520_spunk.h
index c6f7f1526c..051b2e0f58 100644
--- a/include/configs/sc520_spunk.h
+++ b/include/configs/sc520_spunk.h
@@ -88,8 +88,12 @@
 
 
 #define CONFIG_BOOTDELAY	15
-#define CONFIG_BOOTARGS    	"root=/dev/mtdblock1 console=ttyS0,9600 mtdparts=phys:7936k(root),256k(uboot) "
-#define CONFIG_BOOTCOMMAND	"setenv bootargs root=/dev/nfs ip=autoconf console=ttyS0,9600 mtdparts=phys:7808k(root),128k(env),256k(uboot); bootp; bootm"
+#define CONFIG_BOOTARGS		"root=/dev/mtdblock1 console=ttyS0,9600 " \
+					"mtdparts=phys:7936k(root),256k(uboot) "
+#define CONFIG_BOOTCOMMAND	"setenv bootargs root=/dev/nfs ip=autoconf " \
+					"console=ttyS0,9600 " \
+					"mtdparts=phys:7808k(root),128k(env),256k(uboot);" \
+					"bootp;bootm"
 
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE	115200		/* speed to run kgdb serial port */
diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h
index 555316ff63..48251f3948 100644
--- a/include/configs/sequoia.h
+++ b/include/configs/sequoia.h
@@ -318,7 +318,7 @@
 #define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
 
 #define CONFIG_HAS_ETH0
-#define CFG_RX_ETH_BUFFER	32	/* Number of ethernet rx 	*/
+#define CFG_RX_ETH_BUFFER	32	/* Number of ethernet rx	*/
 					/*   buffers & descriptors	*/
 #define CONFIG_NET_MULTI	1
 #define CONFIG_HAS_ETH1		1	/* add support for "eth1addr"	*/
@@ -417,7 +417,7 @@
 #define CFG_CBSIZE	        256	/* Console I/O Buffer Size	*/
 #endif
 #define CFG_PBSIZE              (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
-					/* Print Buffer Size 		*/
+					/* Print Buffer Size		*/
 #define CFG_MAXARGS	        16	/* max number of command args	*/
 #define CFG_BARGSIZE	        CFG_CBSIZE /* Boot Argument Buffer Size	*/
 
@@ -443,7 +443,7 @@
 #define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
 #define CFG_PCI_CACHE_LINE_SIZE	0	/* to avoid problems with PNP	*/
 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup	*/
-#define CFG_PCI_TARGBASE	0x80000000 	/* PCIaddr mapped to	*/
+#define CFG_PCI_TARGBASE	0x80000000	/* PCIaddr mapped to	*/
 						/*   CFG_PCI_MEMBASE	*/
 /* Board-specific PCI */
 #define CFG_PCI_TARGET_INIT
diff --git a/include/configs/shannon.h b/include/configs/shannon.h
index c1fa53f1a8..8bbc730cb9 100644
--- a/include/configs/shannon.h
+++ b/include/configs/shannon.h
@@ -83,7 +83,7 @@
 
 
 #define CONFIG_BOOTDELAY	3
-#define CONFIG_BOOTARGS    	"root=ramfs devfs=mount console=ttySA0,115200"
+#define CONFIG_BOOTARGS		"root=ramfs devfs=mount console=ttySA0,115200"
 #define CONFIG_NETMASK          255.255.0.0
 #define CONFIG_BOOTCOMMAND	"help"
 
diff --git a/include/configs/smdk2400.h b/include/configs/smdk2400.h
index 05f6053727..ac1642e1fc 100644
--- a/include/configs/smdk2400.h
+++ b/include/configs/smdk2400.h
@@ -114,17 +114,9 @@
 
 
 #define CONFIG_BOOTDELAY	3
-#if 0
-#define CONFIG_BOOTARGS    	"root=ramfs devfs=mount console=ttySA0,9600"
-#define CONFIG_ETHADDR		08:00:3e:26:0a:5b
-#endif
 #define CONFIG_NETMASK          255.255.255.0
 #define CONFIG_IPADDR		134.98.93.36
 #define CONFIG_SERVERIP		134.98.93.22
-#if 0
-#define CONFIG_BOOTFILE		"elinos-lart"
-#define CONFIG_BOOTCOMMAND	"tftp; bootm"
-#endif
 
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE	115200		/* speed to run kgdb serial port */
diff --git a/include/configs/smdk2410.h b/include/configs/smdk2410.h
index 18a036c2b6..efe4693ec6 100644
--- a/include/configs/smdk2410.h
+++ b/include/configs/smdk2410.h
@@ -93,7 +93,7 @@
 
 
 #define CONFIG_BOOTDELAY	3
-/*#define CONFIG_BOOTARGS    	"root=ramfs devfs=mount console=ttySA0,9600" */
+/*#define CONFIG_BOOTARGS	"root=ramfs devfs=mount console=ttySA0,9600" */
 /*#define CONFIG_ETHADDR	08:00:3e:26:0a:5b */
 #define CONFIG_NETMASK          255.255.255.0
 #define CONFIG_IPADDR		10.0.0.110
diff --git a/include/configs/socrates.h b/include/configs/socrates.h
new file mode 100644
index 0000000000..23ed87f338
--- /dev/null
+++ b/include/configs/socrates.h
@@ -0,0 +1,422 @@
+/*
+ * (C) Copyright 2008
+ * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
+ *
+ * Wolfgang Denk <wd@denx.de>
+ * Copyright 2004 Freescale Semiconductor.
+ * (C) Copyright 2002,2003 Motorola,Inc.
+ * Xianghua Xiao <X.Xiao@motorola.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Socrates
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE		1	/* BOOKE			*/
+#define CONFIG_E500		1	/* BOOKE e500 family		*/
+#define CONFIG_MPC85xx		1	/* MPC8540/60/55/41		*/
+#define CONFIG_MPC8544		1
+#define CONFIG_SOCRATES		1
+
+#define CONFIG_PCI
+
+#define CONFIG_TSEC_ENET		/* tsec ethernet support	*/
+
+#define CONFIG_MISC_INIT_R	1	/* Call misc_init_r		*/
+
+#define CONFIG_FSL_LAW		1	/* Use common FSL init code */
+
+/*
+ * Only possible on E500 Version 2 or newer cores.
+ */
+#define CONFIG_ENABLE_36BIT_PHYS	1
+
+/*
+ * sysclk for MPC85xx
+ *
+ * Two valid values are:
+ *    33000000
+ *    66000000
+ *
+ * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
+ * is likely the desired value here, so that is now the default.
+ * The board, however, can run at 66MHz.  In any event, this value
+ * must match the settings of some switches.  Details can be found
+ * in the README.mpc85xxads.
+ */
+
+#ifndef CONFIG_SYS_CLK_FREQ
+#define CONFIG_SYS_CLK_FREQ	66666666
+#endif
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE			/* toggle L2 cache		*/
+#define CONFIG_BTB			/* toggle branch predition	*/
+#define CONFIG_ADDR_STREAMING		/* toggle addr streaming	*/
+
+#define CFG_INIT_DBCR DBCR_IDM		/* Enable Debug Exceptions	*/
+
+#undef	CFG_DRAM_TEST			/* memory test, takes time	*/
+#define CFG_MEMTEST_START	0x00000000
+#define CFG_MEMTEST_END		0x10000000
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CFG_CCSRBAR_DEFAULT	0xFF700000	/* CCSRBAR Default	*/
+#define CFG_CCSRBAR		0xE0000000	/* relocated CCSRBAR	*/
+#define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
+#define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR	*/
+
+/*
+ * DDR Setup
+ */
+#define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory	*/
+#define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
+
+#define CONFIG_DDR_DEFAULT_CL	30		/* CAS latency 3	*/
+
+/* Hardcoded values, to use instead of SPD */
+#define CFG_DDR_CS0_BNDS		0x0000000f
+#define CFG_DDR_CS0_CONFIG		0x80010102
+#define CFG_DDR_TIMING_0		0x00260802
+#define CFG_DDR_TIMING_1		0x3935D322
+#define CFG_DDR_TIMING_2		0x14904CC8
+#define CFG_DDR_MODE			0x00480432
+#define CFG_DDR_INTERVAL		0x030C0100
+#define CFG_DDR_CONFIG_2		0x04400000
+#define CFG_DDR_CONFIG			0xC3008000
+#define CFG_DDR_CLK_CONTROL		0x03800000
+#define CFG_SDRAM_SIZE			256 /* in Megs */
+
+#define CONFIG_SPD_EEPROM	1 	/* Use SPD EEPROM for DDR setup*/
+#define SPD_EEPROM_ADDRESS	0x50		/* DDR DIMM */
+#define MPC85xx_DDR_SDRAM_CLK_CNTL	/* 85xx has clock control reg */
+
+/*
+ * Flash on the Local Bus
+ */
+/*
+ * Flash on the LocalBus
+ */
+#define CFG_LBC_CACHE_BASE	0xf0000000	/* Localbus cacheable	 */
+
+#define CFG_FLASH0		0xFE000000
+#define CFG_FLASH1		0xFC000000
+#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH1, CFG_FLASH0 }
+
+#define CFG_LBC_FLASH_BASE	CFG_FLASH1	/* Localbus flash start	*/
+#define CFG_FLASH_BASE		CFG_LBC_FLASH_BASE /* start of FLASH	*/
+
+#define CFG_BR0_PRELIM		0xfe001001	/* port size 16bit	*/
+#define CFG_OR0_PRELIM		0xfe000ff7	/* 32MB Flash		*/
+#define CFG_BR1_PRELIM		0xfc001001	/* port size 16bit	*/
+#define CFG_OR1_PRELIM		0xfe000ff7	/* 32MB Flash		*/
+
+#define CFG_FLASH_CFI				/* flash is CFI compat.	*/
+#define CFG_FLASH_CFI_DRIVER			/* Use common CFI driver*/
+#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector	*/
+
+#define CFG_MAX_FLASH_BANKS	2		/* number of banks	*/
+#define CFG_MAX_FLASH_SECT	256		/* sectors per device	*/
+#undef	CFG_FLASH_CHECKSUM
+#define CFG_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms)	*/
+
+#define CFG_MONITOR_BASE	TEXT_BASE	/* start of monitor	*/
+
+#define CFG_LBC_LCRR		0x00030008    /* LB clock ratio reg	*/
+#define CFG_LBC_LBCR		0x00000000    /* LB config reg		*/
+#define CFG_LBC_LSRT		0x20000000    /* LB sdram refresh timer	*/
+#define CFG_LBC_MRTPR		0x20000000    /* LB refresh timer presc.*/
+
+#define CONFIG_L1_INIT_RAM
+#define CFG_INIT_RAM_LOCK	1
+#define CFG_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address	*/
+#define CFG_INIT_RAM_END	0x4000		/* End used area in RAM	*/
+
+#define CFG_GBL_DATA_SIZE	128		/* num bytes initial data*/
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256kB for Mon*/
+#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserved for malloc	*/
+
+/* Serial Port */
+
+#define CONFIG_CONS_INDEX     1
+#undef	CONFIG_SERIAL_SOFTWARE_FIFO
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE	1
+#define CFG_NS16550_CLK		get_bus_freq(0)
+
+#define CFG_NS16550_COM1	(CFG_CCSRBAR+0x4500)
+#define CFG_NS16550_COM2	(CFG_CCSRBAR+0x4600)
+
+#define CONFIG_BAUDRATE         115200
+
+#define CFG_BAUDRATE_TABLE  \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
+#define CFG_HUSH_PARSER		1	/* Use the HUSH parser		*/
+#ifdef	CFG_HUSH_PARSER
+#define	CFG_PROMPT_HUSH_PS2	"> "
+#endif
+
+
+/*
+ * I2C
+ */
+#define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C			/* I2C with hardware support	*/
+#undef	CONFIG_SOFT_I2C			/* I2C bit-banged		*/
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
+#define CFG_I2C_SLAVE		0x7F
+#define CFG_I2C_NOPROBES	{0x48}	/* Don't probe these addrs	*/
+#define CFG_I2C_OFFSET		0x3000
+
+/* I2C RTC */
+#define CONFIG_RTC_RX8025		/* Use Epson rx8025 rtc via i2c	*/
+#define CFG_I2C_RTC_ADDR	0x32	/* at address 0x32		*/
+
+/* I2C temp sensor */
+/* Socrates uses Maxim's	DS75, which is compatible with LM75 */
+#define CONFIG_DTT_LM75		1
+#define CONFIG_DTT_SENSORS	{4}		/* Sensor addresses	*/
+#define CFG_DTT_MAX_TEMP	125
+#define CFG_DTT_LOW_TEMP	-55
+#define CFG_DTT_HYSTERESIS	3
+#define CFG_EEPROM_PAGE_WRITE_ENABLE	/* necessary for the LM75 chip */
+#define CFG_EEPROM_PAGE_WRITE_BITS	4
+
+/* RapidIO MMU */
+#define CFG_RIO_MEM_BASE	0xc0000000	/* base address		*/
+#define CFG_RIO_MEM_PHYS	CFG_RIO_MEM_BASE
+#define CFG_RIO_MEM_SIZE	0x20000000	/* 128M			*/
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1.
+ */
+#define CFG_PCI_PHYS		0x80000000	/* 1G PCI TLB */
+
+
+#define CFG_PCI1_MEM_BASE	0x80000000
+#define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
+#define CFG_PCI1_MEM_SIZE	0x20000000	/* 512M			*/
+#define CFG_PCI1_IO_BASE	0xE2000000
+#define CFG_PCI1_IO_PHYS	CFG_PCI1_IO_BASE
+#define CFG_PCI1_IO_SIZE	0x01000000	/* 16M			*/
+
+#if defined(CONFIG_PCI)
+#define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
+
+#define CONFIG_EEPRO100
+#undef CONFIG_TULIP
+
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup	*/
+#define CFG_PCI_SUBSYS_VENDORID 0x1057	/* Motorola			*/
+
+#endif	/* CONFIG_PCI */
+
+
+#define CONFIG_NET_MULTI	1
+#define CONFIG_MII		1	/* MII PHY management */
+#define CONFIG_TSEC1	1
+#define CONFIG_TSEC1_NAME	"TSEC0"
+#define CONFIG_TSEC3	1
+#define CONFIG_TSEC3_NAME	"TSEC1"
+#undef CONFIG_MPC85XX_FEC
+
+#define TSEC1_PHY_ADDR		0
+#define TSEC3_PHY_ADDR		1
+
+#define TSEC1_PHYIDX		0
+#define TSEC3_PHYIDX		0
+#define TSEC1_FLAGS		TSEC_GIGABIT
+#define TSEC3_FLAGS		TSEC_GIGABIT
+
+/* Options are: TSEC[0,1] */
+#define CONFIG_ETHPRIME		"TSEC0"
+#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
+
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+
+/*
+ * Environment
+ */
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_SECT_SIZE	0x20000 /* 128K(one sector) for env	*/
+#define CFG_ENV_ADDR		(CFG_MONITOR_BASE - CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE		0x4000
+#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#define	CONFIG_TIMESTAMP		/* Print image info with ts	*/
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DTT
+#undef CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SNTP
+#define CONFIG_CMD_USB
+
+
+#if defined(CONFIG_PCI)
+    #define CONFIG_CMD_PCI
+#endif
+
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_LOAD_ADDR	0x2000000	/* default load address		*/
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+
+#if defined(CONFIG_CMD_KGDB)
+    #define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+    #define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buf Size	*/
+#define CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CFG_HZ		1000		/* decrementer freq: 1ms ticks	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux	*/
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot		*/
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port*/
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use	*/
+#endif
+
+
+#define CONFIG_LOADADDR	 200000		/* default addr for tftp & bootm*/
+
+#define CONFIG_BOOTDELAY 5		/* -1 disables auto-boot	*/
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS		/* the boot command will set bootargs	*/
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"bootfile=$hostname/uImage\0"					\
+	"netdev=eth0\0"							\
+	"consdev=ttyS0\0"						\
+	"hostname=socrates\0"						\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=$serverip:$rootpath\0"				\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs $bootargs "				\
+		"ip=$ipaddr:$serverip:$gatewayip:$netmask"		\
+		":$hostname:$netdev:off panic=1\0"			\
+	"addcons=setenv bootargs $bootargs "				\
+		"console=$consdev,$baudrate\0"				\
+	"flash_self=run ramargs addip addcons;"				\
+		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"	\
+	"flash_nfs=run nfsargs addip addcons;"				\
+		"bootm ${kernel_addr} - ${fdt_addr}\0"			\
+	"net_nfs=tftp ${kernel_addr_r} ${bootfile}; "			\
+		"tftp ${fdt_addr_r} ${fdt_file}; "			\
+		"run nfsargs addip addcons;"				\
+		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\
+	"fdt_file=$hostname/socrates.dtb\0"					\
+	"fdt_addr_r=B00000\0"						\
+	"fdt_addr=FC1E0000\0"						\
+	"rootpath=/opt/eldk/ppc_85xx\0"					\
+	"kernel_addr=FC000000\0"					\
+	"kernel_addr_r=200000\0"					\
+	"ramdisk_addr=FC200000\0"					\
+	"ramdisk_addr_r=400000\0"					\
+	"load=tftp 100000 $hostname/u-boot.bin\0"		\
+	"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;"	\
+		"cp.b 100000 fffc0000 40000;"			        \
+		"setenv filesize;saveenv\0"				\
+	"upd=run load update\0"						\
+	""
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT	1
+#define CONFIG_OF_BOARD_SETUP	1
+
+/* USB support */
+#define CONFIG_USB_OHCI_NEW		1
+#define CONFIG_PCI_OHCI			1
+#define CONFIG_PCI_OHCI_DEVNO		3 /* Number in PCI list */
+#define CFG_USB_OHCI_MAX_ROOT_PORTS	15
+#define CFG_USB_OHCI_SLOT_NAME		"ohci_pci"
+#define CFG_OHCI_SWAP_REG_ACCESS	1
+#define CONFIG_DOS_PARTITION		1
+#define CONFIG_USB_STORAGE		1
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/sorcery.h b/include/configs/sorcery.h
index b622a30783..c62b9775c6 100644
--- a/include/configs/sorcery.h
+++ b/include/configs/sorcery.h
@@ -189,7 +189,7 @@
 
 #define CFG_FLASH_CFI_DRIVER
 #define CFG_FLASH_CFI
-#define CFG_FLASH_BANKS_LIST 	{ CFG_FLASH_BASE,  \
+#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE,  \
 				CFG_FLASH_BASE+0x04000000 } /* two banks */
 
 /*
@@ -243,12 +243,12 @@
 
 /* SDRAM configuration (for SPD) */
 #define CFG_SDRAM_TOTAL_BANKS		1
-#define CFG_SDRAM_SPD_I2C_ADDR		0x50  		/* 7bit */
+#define CFG_SDRAM_SPD_I2C_ADDR		0x50		/* 7bit */
 #define CFG_SDRAM_SPD_SIZE		0x100
-#define CFG_SDRAM_CAS_LATENCY		5 		/* (CL=2.5)x2 */
+#define CFG_SDRAM_CAS_LATENCY		5		/* (CL=2.5)x2 */
 
 /* SDRAM drive strength register (for SSTL_2 class II)*/
-#define CFG_SDRAM_DRIVE_STRENGTH 	((DRIVE_STRENGTH_HIGH << SDRAMDS_SBE_SHIFT) | \
+#define CFG_SDRAM_DRIVE_STRENGTH	((DRIVE_STRENGTH_HIGH << SDRAMDS_SBE_SHIFT) | \
 					 (DRIVE_STRENGTH_HIGH << SDRAMDS_SBC_SHIFT) | \
 					 (DRIVE_STRENGTH_HIGH << SDRAMDS_SBA_SHIFT) | \
 					 (DRIVE_STRENGTH_HIGH << SDRAMDS_SBS_SHIFT) | \
@@ -285,7 +285,7 @@
 
 #define CFG_CACHELINE_SIZE	32	/* For MPC8220 CPUs */
 #if defined(CONFIG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT	5   	/* log base 2 of the above value */
+#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
 #endif
 
 /*
diff --git a/include/configs/stxgp3.h b/include/configs/stxgp3.h
index fc5d0cc76a..ec04a30bec 100644
--- a/include/configs/stxgp3.h
+++ b/include/configs/stxgp3.h
@@ -42,8 +42,8 @@
 #define CONFIG_CPM2		1	/* has CPM2 */
 #define CONFIG_STXGP3		1	/* Silicon Tx GPPP board specific*/
 
-#undef  CONFIG_PCI	         	/* pci ethernet support	*/
-#define CONFIG_TSEC_ENET 		/* tsec ethernet support*/
+#undef  CONFIG_PCI			/* pci ethernet support	*/
+#define CONFIG_TSEC_ENET		/* tsec ethernet support*/
 #undef  CONFIG_ETHER_ON_FCC             /* cpm FCC ethernet support */
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup */
@@ -100,7 +100,7 @@
 #define CFG_OR1_PRELIM		0xffff0ff7      /* 64K is enough */
 #define CFG_LBC_LCLDEVS_BASE	0xfc000000	/* Base of localbus devices */
 
-#define CFG_MONITOR_BASE    	TEXT_BASE	/* start of monitor	*/
+#define CFG_MONITOR_BASE	TEXT_BASE	/* start of monitor	*/
 
 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
 #define CFG_RAMBOOT
@@ -109,9 +109,9 @@
 #endif
 
 #ifdef CFG_RAMBOOT
-#define CFG_CCSRBAR_DEFAULT 	0x40000000	/* CCSRBAR by BDI cfg	*/
+#define CFG_CCSRBAR_DEFAULT	0x40000000	/* CCSRBAR by BDI cfg	*/
 #else
-#define CFG_CCSRBAR_DEFAULT 	0xff700000	/* CCSRBAR Default	*/
+#define CFG_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default	*/
 #endif
 #define CFG_CCSRBAR             0xfdf00000      /* relocated CCSRBAR    */
 #define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
@@ -129,14 +129,14 @@
 #define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory  */
 #define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
 
-#define SPD_EEPROM_ADDRESS 	0x54     	/*  DDR DIMM */
+#define SPD_EEPROM_ADDRESS	0x54		/*  DDR DIMM */
 
 #undef CONFIG_CLOCKS_IN_MHZ
 
 /* local bus definitions */
 #define CFG_BR2_PRELIM		0xf8001861	/* 64MB localbus SDRAM  */
 #define CFG_OR2_PRELIM		0xfc006901
-#define CFG_LBC_LCRR		0x00030004	/* local bus freq 	*/
+#define CFG_LBC_LCRR		0x00030004	/* local bus freq	*/
 #define CFG_LBC_LBCR		0x00000000
 #define CFG_LBC_LSRT		0x20000000
 #define CFG_LBC_MRTPR		0x20000000
@@ -147,23 +147,23 @@
 #define CFG_LBC_LSDMR_5		0x4061b723
 
 #define CONFIG_L1_INIT_RAM
-#define CFG_INIT_RAM_LOCK 	1
+#define CFG_INIT_RAM_LOCK	1
 #define CFG_INIT_RAM_ADDR       0x60000000      /* Initial RAM address  */
-#define CFG_INIT_RAM_END    	0x4000	    	/* End of used area in RAM */
+#define CFG_INIT_RAM_END	0x4000		/* End of used area in RAM */
 
-#define CFG_GBL_DATA_SIZE  	128		/* num bytes initial data */
+#define CFG_GBL_DATA_SIZE	128		/* num bytes initial data */
 #define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 #define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
 
-#define CFG_MONITOR_LEN	    	(256 * 1024)    /* Reserve 256 kB for Mon */
-#define CFG_MALLOC_LEN	    	(128 * 1024)    /* Reserved for malloc */
+#define CFG_MONITOR_LEN		(256 * 1024)    /* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN		(128 * 1024)    /* Reserved for malloc */
 
 /* Serial Port */
-#define CONFIG_CONS_ON_SCC              	/* define if console on SCC */
-#undef  CONFIG_CONS_NONE                	/* define if console on something else */
-#define CONFIG_CONS_INDEX       2       	/* which serial channel for console */
+#define CONFIG_CONS_ON_SCC		/* define if console on SCC */
+#undef  CONFIG_CONS_NONE		/* define if console on something else */
+#define CONFIG_CONS_INDEX       2	/* which serial channel for console */
 
-#define CONFIG_BAUDRATE	 	38400
+#define CONFIG_BAUDRATE		38400
 
 #define CFG_BAUDRATE_TABLE  \
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
@@ -205,18 +205,18 @@
 #define CFG_PCI1_IO_PHYS	CFG_PCI1_IO_BASE
 #define CFG_PCI1_IO_SIZE	0x01000000	/* 16 M */
 
-#if defined(CONFIG_PCI) 		/* PCI Ethernet card */
+#if defined(CONFIG_PCI)			/* PCI Ethernet card */
 
 #define CONFIG_NET_MULTI
-#define CONFIG_PCI_PNP	               	/* do pci plug-and-play */
+#define CONFIG_PCI_PNP			/* do pci plug-and-play */
 
 #undef CONFIG_EEPRO100
 #undef CONFIG_TULIP
 
 #if !defined(CONFIG_PCI_PNP)
-  #define PCI_ENET0_IOADDR    	0xe0000000
+  #define PCI_ENET0_IOADDR	0xe0000000
   #define PCI_ENET0_MEMADDR     0xe0000000
-  #define PCI_IDSEL_NUMBER      0x0c 	/* slot0->3(IDSEL)=12->15 */
+  #define PCI_IDSEL_NUMBER      0x0c	/* slot0->3(IDSEL)=12->15 */
 #endif
 
 #undef CONFIG_PCI_SCAN_SHOW
@@ -227,7 +227,7 @@
 #if defined(CONFIG_TSEC_ENET)
 
 #ifndef CONFIG_NET_MULTI
-#define CONFIG_NET_MULTI 	1
+#define CONFIG_NET_MULTI	1
 #endif
 
 #define CONFIG_MII		1	/* MII PHY management		*/
@@ -270,7 +270,7 @@
 #elif (CONFIG_ETHER_INDEX == 3)
   /* need more definitions here for FE3 */
   #define FETH3_RST		0x80
-#endif  				/* CONFIG_ETHER_INDEX */
+#endif	/* CONFIG_ETHER_INDEX */
 
 /* MDIO is done through the TSEC0 control.
 */
@@ -375,20 +375,20 @@
 /*Note: change below for your network setting!!! */
 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
 #define CONFIG_HAS_ETH0
-#define CONFIG_ETHADDR	 00:e0:0c:07:9b:8a
+#define CONFIG_ETHADDR		 00:e0:0c:07:9b:8a
 #define CONFIG_HAS_ETH1
-#define CONFIG_ETH1ADDR  00:e0:0c:07:9b:8b
+#define CONFIG_ETH1ADDR		 00:e0:0c:07:9b:8b
 #define CONFIG_HAS_ETH2
-#define CONFIG_ETH2ADDR  00:e0:0c:07:9b:8c
+#define CONFIG_ETH2ADDR		 00:e0:0c:07:9b:8c
 #endif
 
-#define CONFIG_SERVERIP 	192.168.85.1
-#define CONFIG_IPADDR  		192.168.85.60
+#define CONFIG_SERVERIP		192.168.85.1
+#define CONFIG_IPADDR		192.168.85.60
 #define CONFIG_GATEWAYIP	192.168.85.1
 #define CONFIG_NETMASK		255.255.255.0
-#define CONFIG_HOSTNAME 	STX_GP3
-#define CONFIG_ROOTPATH 	/gppproot
-#define CONFIG_BOOTFILE 	uImage
+#define CONFIG_HOSTNAME		STX_GP3
+#define CONFIG_ROOTPATH		/gppproot
+#define CONFIG_BOOTFILE		uImage
 #define CONFIG_LOADADDR		0x1000000
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/stxssa.h b/include/configs/stxssa.h
index 15f690af16..d033c866d7 100644
--- a/include/configs/stxssa.h
+++ b/include/configs/stxssa.h
@@ -69,10 +69,10 @@
 #define  CONFIG_BTB				/* toggle branch predition */
 #define  CONFIG_ADDR_STREAMING			/* toggle addr streaming	*/
 
-#define CONFIG_BOARD_EARLY_INIT_F   1	     	/* Call board_pre_init	 */
+#define CONFIG_BOARD_EARLY_INIT_F   1		/* Call board_pre_init	 */
 
-#undef	CFG_DRAM_TEST			    	/* memory test, takes time	*/
-#define CFG_MEMTEST_START	0x00200000  	/* memtest region */
+#undef	CFG_DRAM_TEST				/* memory test, takes time	*/
+#define CFG_MEMTEST_START	0x00200000	/* memtest region */
 #define CFG_MEMTEST_END		0x00400000
 
 
@@ -232,7 +232,7 @@
 #define CFG_PCI2_IO_PHYS	0xe3000000
 #define CFG_PCI2_IO_SIZE	0x01000000	/* 16M */
 
-#if defined(CONFIG_PCI) 		/* PCI Ethernet card */
+#if defined(CONFIG_PCI)			/* PCI Ethernet card */
 #define CONFIG_MPC85XX_PCI2	1
 #define CONFIG_NET_MULTI
 #define CONFIG_PCI_PNP			/* do pci plug-and-play */
@@ -428,13 +428,13 @@
 #define CONFIG_BOOTDELAY	3	/* -1 disable autoboot */
 #define CONFIG_BOOTCOMMAND	"bootm 0xffc00000 0xffd00000"
 #define CONFIG_BOOTARGS		"root=/dev/nfs rw ip=any console=ttyS1,$baudrate"
-#define CONFIG_SERVERIP 	192.168.85.1
+#define CONFIG_SERVERIP		192.168.85.1
 #define CONFIG_IPADDR		192.168.85.60
 #define CONFIG_GATEWAYIP	192.168.85.1
 #define CONFIG_NETMASK		255.255.255.0
-#define CONFIG_HOSTNAME 	STX_SSA
-#define CONFIG_ROOTPATH 	/gppproot
-#define CONFIG_BOOTFILE 	uImage
+#define CONFIG_HOSTNAME		STX_SSA
+#define CONFIG_ROOTPATH		/gppproot
+#define CONFIG_BOOTFILE		uImage
 #define CONFIG_LOADADDR		0x1000000
 
 #else /* ENV IS IN FLASH		-- use a full-blown envionment */
diff --git a/include/configs/stxxtc.h b/include/configs/stxxtc.h
index a3ab798977..97a1032af0 100644
--- a/include/configs/stxxtc.h
+++ b/include/configs/stxxtc.h
@@ -63,9 +63,9 @@
 
 #undef	CONFIG_BOOTARGS
 #define CONFIG_BOOTCOMMAND							\
-	"tftpboot; " 								\
-	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " 	\
-	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " 	\
+	"tftpboot; "								\
+	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "	\
 	"bootm"
 
 #define CONFIG_AUTOSCRIPT
@@ -93,7 +93,7 @@
 
 #define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
 
-#define	CONFIG_NET_MULTI	1 	/* the only way to get the FEC in */
+#define	CONFIG_NET_MULTI	1	/* the only way to get the FEC in */
 #define	FEC_ENET		1	/* eth.c needs it that way... */
 #undef CFG_DISCOVER_PHY
 #define CONFIG_MII		1
@@ -101,7 +101,7 @@
 #undef CONFIG_RMII
 
 #define CONFIG_ETHER_ON_FEC1	1
-#define CONFIG_FEC1_PHY		1 	/* phy address of FEC */
+#define CONFIG_FEC1_PHY		1	/* phy address of FEC */
 #undef CONFIG_FEC1_PHY_NORXERR
 
 #define CONFIG_ETHER_ON_FEC2	1
@@ -214,7 +214,7 @@
 
 #define CFG_FLASH_CFI		1
 #define CFG_FLASH_CFI_DRIVER	1
-#undef CFG_FLASH_USE_BUFFER_WRITE 	/* use buffered writes (20x faster) */
+#undef CFG_FLASH_USE_BUFFER_WRITE	/* use buffered writes (20x faster) */
 #define CFG_MAX_FLASH_SECT	128	/* max number of sectors on one chip */
 #define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks	*/
 
@@ -283,11 +283,11 @@
 #if MPC8XX_HZ == 50000000
 #define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
 			 (1 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
-		 	 PLPRCR_TEXPS)
+			 PLPRCR_TEXPS)
 #elif MPC8XX_HZ == 66666666
 #define CFG_PLPRCR	((1 << PLPRCR_MFN_SHIFT) | (2 << PLPRCR_MFD_SHIFT) | \
 			 (1 << PLPRCR_S_SHIFT) | (13 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
-		 	 PLPRCR_TEXPS)
+			 PLPRCR_TEXPS)
 #else
 #error unsupported CPU freq for XIN = 10MHz
 #endif
@@ -462,7 +462,7 @@
 #define ADDR_COLUMN		1
 #define ADDR_PAGE		2
 #define ADDR_COLUMN_PAGE	3
-#define NAND_ChipID_UNKNOWN 	0x00
+#define NAND_ChipID_UNKNOWN	0x00
 #define NAND_MAX_FLOORS		1
 #define NAND_MAX_CHIPS		1
 
diff --git a/include/configs/svm_sc8xx.h b/include/configs/svm_sc8xx.h
index 3b90f3ceb1..70336b5ebd 100644
--- a/include/configs/svm_sc8xx.h
+++ b/include/configs/svm_sc8xx.h
@@ -68,7 +68,7 @@
 
 #undef	CONFIG_WATCHDOG			/* watchdog */
 
-#define CONFIG_SVM_SC8xx		1	/* ...on SVM SC8xx series 	*/
+#define CONFIG_SVM_SC8xx		1	/* ...on SVM SC8xx series	*/
 
 #ifdef	CONFIG_LCD			/* with LCD controller ?	*/
 /* #define CONFIG_NEC_NL6448BC20 1 / * use NEC NL6448BC20 display	*/
@@ -109,8 +109,8 @@
 	"ramdisk_addr=48100000\0"                                       \
 	""
 #define CONFIG_BOOTCOMMAND							\
-	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " 	\
-	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " 	\
+	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "	\
 	"tftpboot 0x210000 pImage-sc855t;bootm 0x210000"
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
@@ -363,14 +363,14 @@
  *-----------------------------------------------------------------------
  */
 
-#undef	CONFIG_IDE_8xx_PCCARD   	/* Use IDE with PC Card	Adapter	*/
+#undef	CONFIG_IDE_8xx_PCCARD		/* Use IDE with PC Card	Adapter	*/
 
 #define	CONFIG_IDE_8xx_DIRECT	1	/* Direct IDE    not supported	*/
 #undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
 #undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
 
 #define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define CFG_IDE_MAXDEVICE	1 	/* max. 1 drive per IDE bus	*/
+#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
 
 #define CFG_ATA_BASE_ADDR       0xFE100010
 #define CFG_ATA_IDE0_OFFSET     0x0000
diff --git a/include/configs/taihu.h b/include/configs/taihu.h
index 8a1ff1acba..c060b1e340 100644
--- a/include/configs/taihu.h
+++ b/include/configs/taihu.h
@@ -363,7 +363,7 @@ unsigned char spi_read(void);
 { GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25	UART0_DSR		*/	\
 { GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26	UART0_RI		*/	\
 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27	UART0_DTR		*/	\
-{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28	UART1_Rx    UART0 	*/	\
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28	UART1_Rx    UART0	*/	\
 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29	UART1_Tx		*/	\
 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO30	RejectPkt0  User LED1	*/	\
 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO31	RejectPkt1  User LED2	*/	\
diff --git a/include/configs/trab.h b/include/configs/trab.h
index b9088a89ab..de36fca11e 100644
--- a/include/configs/trab.h
+++ b/include/configs/trab.h
@@ -69,8 +69,8 @@
  * address 0x54 with 8bit addressing
  ***********************************************************/
 #define CONFIG_HARD_I2C			/* I2C with hardware support */
-#define CFG_I2C_SPEED 		100000	/* I2C speed */
-#define CFG_I2C_SLAVE 		0x7F	/* I2C slave addr */
+#define CFG_I2C_SPEED		100000	/* I2C speed */
+#define CFG_I2C_SLAVE		0x7F	/* I2C slave addr */
 
 #define CFG_I2C_EEPROM_ADDR	0x54	/* EEPROM address */
 #define CFG_I2C_EEPROM_ADDR_LEN	1	/* 1 address byte */
@@ -237,7 +237,7 @@
 	"mdm_init2=ATS0=1\0" \
 	"mdm_flow_control=rts/cts\0"
 #endif	/* CFG_HUSH_PARSER */
-#else	/* CONFIG_FLASH_8MB 	 => 8 MB flash */
+#else	/* CONFIG_FLASH_8MB	 => 8 MB flash */
 #ifdef CFG_HUSH_PARSER
 #define	CONFIG_EXTRA_ENV_SETTINGS	\
 	"nfs_args=setenv bootargs root=/dev/nfs rw " \
diff --git a/include/configs/trizepsiv.h b/include/configs/trizepsiv.h
index 7a15d97cb0..25155ad349 100644
--- a/include/configs/trizepsiv.h
+++ b/include/configs/trizepsiv.h
@@ -303,7 +303,7 @@
 #define CFG_MONITOR_LEN		0x40000
 
 #define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	4 + 255  /* max number of sectors on one chip    */
+#define CFG_MAX_FLASH_SECT	4 + 255  /* max number of sectors on one chip   */
 
 /* timeout values are in ticks */
 #define CFG_FLASH_ERASE_TOUT	(25*CFG_HZ) /* Timeout for Flash Erase */
@@ -314,8 +314,8 @@
 
 /* Flash environment locations */
 #define CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_ADDR		(PHYS_FLASH_1 + CFG_MONITOR_LEN)	/* Addr of Environment Sector	*/
-#define CFG_ENV_SIZE		0x40000	/* Total Size of Environment     	*/
+#define CFG_ENV_ADDR		(PHYS_FLASH_1 + CFG_MONITOR_LEN) /* Addr of Environment Sector	*/
+#define CFG_ENV_SIZE		0x40000	/* Total Size of Environment		*/
 #define CFG_ENV_SECT_SIZE	0x40000	/* Total Size of Environment Sector	*/
 
 /* Address and size of Redundant Environment Sector	*/
diff --git a/include/configs/uc100.h b/include/configs/uc100.h
index 3c2de40dfc..e74b1bb85b 100644
--- a/include/configs/uc100.h
+++ b/include/configs/uc100.h
@@ -243,7 +243,7 @@
 
 #define	CFG_ENV_IS_IN_FLASH	1
 #define CFG_ENV_ADDR		(CFG_MONITOR_BASE+CFG_MONITOR_LEN)
-#define CFG_ENV_SECT_SIZE	0x20000 	/* size of one complete sector	*/
+#define CFG_ENV_SECT_SIZE	0x20000	/* size of one complete sector		*/
 #define	CFG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
 
 /* Address and size of Redundant Environment Sector	*/
diff --git a/include/configs/utx8245.h b/include/configs/utx8245.h
index cd00c49fc2..287a6187a2 100644
--- a/include/configs/utx8245.h
+++ b/include/configs/utx8245.h
@@ -58,7 +58,7 @@
 #define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 #define CONFIG_BOOTDELAY	2
-#define CONFIG_AUTOBOOT_PROMPT 	"autoboot in %d seconds\n"
+#define CONFIG_AUTOBOOT_PROMPT	"autoboot in %d seconds\n"
 #define CONFIG_BOOTCOMMAND	"run nfsboot"	/* autoboot command	*/
 #define CONFIG_BOOTARGS		"root=/dev/ram console=ttyS0,57600" /* RAMdisk */
 #define CONFIG_ETHADDR		00:AA:00:14:00:05	/* UTX5 */
@@ -255,7 +255,7 @@ protect on ${u-boot_startaddr} ${u-boot_endaddr}"
 									mem_freq = 100MHz */
 
 #define CFG_BANK7_ROW	0		/* SDRAM bank 7-0 row address */
-#define CFG_BANK6_ROW	0		/* 	bit count */
+#define CFG_BANK6_ROW	0		/*	bit count */
 #define CFG_BANK5_ROW	0
 #define CFG_BANK4_ROW	0
 #define CFG_BANK3_ROW	0
@@ -278,7 +278,7 @@ protect on ${u-boot_startaddr} ${u-boot_endaddr}"
 #define CFG_ACTTOPRE	    7	    /* trcd + (burst length - 1) + trdl */
 #define CFG_SDMODE_CAS_LAT  3	    /* SDMODE CAS latancy */
 #define CFG_SDMODE_WRAP	    0	    /* SDMODE wrap type, sequential */
-#define CFG_ACTORW	    	2		/* trcd min */
+#define CFG_ACTORW		2		/* trcd min */
 #define CFG_DBUS_SIZE2		1		/* set for 8-bit RCS1, clear for 32,64 */
 #define CFG_REGISTERD_TYPE_BUFFER 1
 #define CFG_EXTROM	    0			/* we don't need extended ROM space */
diff --git a/include/configs/v37.h b/include/configs/v37.h
index 47851c2814..751d702135 100644
--- a/include/configs/v37.h
+++ b/include/configs/v37.h
@@ -34,7 +34,7 @@
  */
 
 #define CONFIG_MPC823		1	/* This is a MPC823 CPU		*/
-#define CONFIG_V37		1	/* ...on a Marel V37 board 	*/
+#define CONFIG_V37		1	/* ...on a Marel V37 board	*/
 
 #define CONFIG_LCD
 #define CONFIG_SHARP_LQ084V1DG21
@@ -63,10 +63,10 @@
 #undef	CONFIG_BOOTARGS
 
 #define CONFIG_BOOTCOMMAND							\
-	"tftpboot; " 								\
+	"tftpboot; "								\
 	"setenv bootargs console=tty0 "                                   \
-	"root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "		 	\
-	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " 	\
+	"root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "			\
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "	\
 	"bootm"
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
@@ -333,7 +333,7 @@
 
 #define CFG_PRELIM_OR_AM	0xFE000000	/* OR addr mask */
 
-#define CFG_OR_TIMING_FLASH 	0xF56
+#define CFG_OR_TIMING_FLASH	0xF56
 
 #define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
 #define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V)
diff --git a/include/configs/versatile.h b/include/configs/versatile.h
index d250150127..a88d356b17 100644
--- a/include/configs/versatile.h
+++ b/include/configs/versatile.h
@@ -80,7 +80,7 @@
 
 #define CONFIG_DRIVER_SMC91111
 #define CONFIG_SMC_USE_32_BIT
-#define CONFIG_SMC91111_BASE    	0x10010000
+#define CONFIG_SMC91111_BASE	0x10010000
 #undef CONFIG_SMC91111_EXT_PHY
 
 /*
diff --git a/include/configs/wepep250.h b/include/configs/wepep250.h
index c67b301227..f2efe9f410 100644
--- a/include/configs/wepep250.h
+++ b/include/configs/wepep250.h
@@ -132,9 +132,9 @@
 /*
  * Configuration for FLASH memory
  */
-#define CFG_MAX_FLASH_BANKS    	1  	/* FLASH banks count (not chip count)*/
-#define CFG_MAX_FLASH_SECT     	128	/* number of sector in FLASH bank    */
-#define WEP_FLASH_BUS_WIDTH 	4	/* we use 32 bit FLASH memory...     */
+#define CFG_MAX_FLASH_BANKS	1	/* FLASH banks count (not chip count)*/
+#define CFG_MAX_FLASH_SECT	128	/* number of sector in FLASH bank    */
+#define WEP_FLASH_BUS_WIDTH	4	/* we use 32 bit FLASH memory...     */
 #define WEP_FLASH_INTERLEAVE	2	/* ... made of 2 chips */
 #define WEP_FLASH_BANK_SIZE  0x2000000  /* size of one flash bank*/
 #define WEP_FLASH_SECT_SIZE  0x0040000  /* size of erase sector */
diff --git a/include/configs/xaeniax.h b/include/configs/xaeniax.h
index 7418986caa..dc0ee0b223 100644
--- a/include/configs/xaeniax.h
+++ b/include/configs/xaeniax.h
@@ -97,7 +97,7 @@
 #define CONFIG_BOOTCOMMAND	"bootm 0x00100000"
 #define CONFIG_BOOTARGS		"console=ttyS1,115200"
 #define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS 	1
+#define CONFIG_SETUP_MEMORY_TAGS	1
 #define CONFIG_INITRD_TAG		1
 
 #if defined(CONFIG_CMD_KGDB)
diff --git a/include/configs/xupv2p.h b/include/configs/xupv2p.h
index c738567a5f..570d6a8021 100644
--- a/include/configs/xupv2p.h
+++ b/include/configs/xupv2p.h
@@ -124,7 +124,7 @@
  * 0x3FFB_F000	CFG_MONITOR_BASE
  *					MONITOR_CODE	256kB	Env
  * 0x3FFF_F000	CFG_GBL_DATA_OFFSET
- * 					GLOBAL_DATA	4kB	bd, gd
+ *					GLOBAL_DATA	4kB	bd, gd
  * 0x4000_0000	CFG_SDRAM_BASE + CFG_SDRAM_SIZE
  */
 
@@ -194,13 +194,13 @@
 #define	CFG_LONGHELP
 #define	CFG_LOAD_ADDR	0x12000000 /* default load address */
 
-#define	CONFIG_BOOTDELAY 	30
+#define	CONFIG_BOOTDELAY	30
 #define	CONFIG_BOOTARGS		"root=romfs"
 #define	CONFIG_HOSTNAME		"xupv2p"
-#define	CONFIG_BOOTCOMMAND 	"base 0;tftp 11000000 image.img;bootm"
+#define	CONFIG_BOOTCOMMAND	"base 0;tftp 11000000 image.img;bootm"
 #define	CONFIG_IPADDR		192.168.0.3
-#define	CONFIG_SERVERIP 	192.168.0.5
-#define	CONFIG_GATEWAYIP 	192.168.0.1
+#define	CONFIG_SERVERIP		192.168.0.5
+#define	CONFIG_GATEWAYIP	192.168.0.1
 #define	CONFIG_ETHADDR		00:E0:0C:00:00:FD
 
 /* architecture dependent code */
diff --git a/include/div64.h b/include/div64.h
index 2e0ba8389e..c495aefb01 100644
--- a/include/div64.h
+++ b/include/div64.h
@@ -8,9 +8,9 @@
  *
  * uint32_t do_div(uint64_t *n, uint32_t base)
  * {
- * 	uint32_t remainder = *n % base;
- * 	*n = *n / base;
- * 	return remainder;
+ *	uint32_t remainder = *n % base;
+ *	*n = *n / base;
+ *	return remainder;
  * }
  *
  * NOTE: macro parameter n is evaluated multiple times,
@@ -31,7 +31,7 @@ extern uint32_t __div64_32(uint64_t *dividend, uint32_t divisor);
 	if (((n) >> 32) == 0) {			\
 		__rem = (uint32_t)(n) % __base;		\
 		(n) = (uint32_t)(n) / __base;		\
-	} else 						\
+	} else						\
 		__rem = __div64_32(&(n), __base);	\
 	__rem;						\
  })
diff --git a/include/dm9161.h b/include/dm9161.h
index d5d0e8d3ab..218f15c4be 100644
--- a/include/dm9161.h
+++ b/include/dm9161.h
@@ -15,7 +15,7 @@
 
 /* DAVICOM PHYSICAL LAYER TRANSCEIVER DM9161 */
 
-#define	DM9161_BMCR 		0	/* Basic Mode Control Register */
+#define	DM9161_BMCR		0	/* Basic Mode Control Register */
 #define DM9161_BMSR		1	/* Basic Mode Status Register */
 #define DM9161_PHYID1		2	/* PHY Idendifier Register 1 */
 #define DM9161_PHYID2		3	/* PHY Idendifier Register 2 */
@@ -32,7 +32,7 @@
 
 
 /* --Bit definitions: DM9161_BMCR */
-#define DM9161_RESET   	         (1 << 15)	/* 1= Software Reset; 0=Normal Operation */
+#define DM9161_RESET	         (1 << 15)	/* 1= Software Reset; 0=Normal Operation */
 #define DM9161_LOOPBACK	         (1 << 14)	/* 1=loopback Enabled; 0=Normal Operation */
 #define DM9161_SPEED_SELECT      (1 << 13)	/* 1=100Mbps; 0=10Mbps */
 #define DM9161_AUTONEG	         (1 << 12)
diff --git a/include/elf.h b/include/elf.h
index d0febc58cd..a9839df3f2 100644
--- a/include/elf.h
+++ b/include/elf.h
@@ -43,9 +43,9 @@
 #include <stdint.h>
 #elif defined(__WIN32__)
 #include <unistd.h>
-typedef 	 unsigned char	 uint8_t;
-typedef 	 unsigned short  uint16_t;
-typedef 	 unsigned int	 uint32_t;
+typedef	 unsigned char	 uint8_t;
+typedef	 unsigned short  uint16_t;
+typedef	 unsigned int	 uint32_t;
 #endif
 
 /*
@@ -415,7 +415,7 @@ typedef struct
 /* Extract relocation info - r_info */
 #define ELF32_R_SYM(i)		((i) >> 8)
 #define ELF32_R_TYPE(i)		((unsigned char) (i))
-#define ELF32_R_INFO(s,t) 	(((s) << 8) + (unsigned char)(t))
+#define ELF32_R_INFO(s,t)	(((s) << 8) + (unsigned char)(t))
 
 /* Program Header */
 typedef struct {
diff --git a/include/fat.h b/include/fat.h
index f993ccab1c..59de3fbec5 100644
--- a/include/fat.h
+++ b/include/fat.h
@@ -101,7 +101,7 @@
 #else
 #define FAT2CPU16(x)	((((x) & 0x00ff) << 8) | (((x) & 0xff00) >> 8))
 #define FAT2CPU32(x)	((((x) & 0x000000ff) << 24)  |	\
-	 		 (((x) & 0x0000ff00) << 8)  |	\
+			 (((x) & 0x0000ff00) << 8)  |	\
 			 (((x) & 0x00ff0000) >> 8)  |	\
 			 (((x) & 0xff000000) >> 24))
 #endif
diff --git a/include/flash.h b/include/flash.h
index 2ed1e20fd2..af8a7c0883 100644
--- a/include/flash.h
+++ b/include/flash.h
@@ -51,10 +51,10 @@ typedef struct {
 	ushort	device_id2;		/* extended device id			*/
 	ushort	ext_addr;		/* extended query table address		*/
 	ushort	cfi_version;		/* cfi version				*/
-	ushort	cfi_offset;		/* offset for cfi query 		*/
+	ushort	cfi_offset;		/* offset for cfi query			*/
 	ulong   addr_unlock1;		/* unlock address 1 for AMD flash roms  */
 	ulong   addr_unlock2;		/* unlock address 2 for AMD flash roms  */
-	const char *name;		/* human-readable name 	                */
+	const char *name;		/* human-readable name	                */
 #endif
 } flash_info_t;
 
diff --git a/include/fpga.h b/include/fpga.h
index a038aa1895..52d93b1009 100644
--- a/include/fpga.h
+++ b/include/fpga.h
@@ -22,7 +22,7 @@
  *
  */
 
-#include <linux/types.h>               /* for ulong typedef */
+#include <linux/types.h>	       /* for ulong typedef */
 
 #ifndef _FPGA_H_
 #define _FPGA_H_
@@ -33,41 +33,41 @@
 
 /* these probably belong somewhere else */
 #ifndef FALSE
-#define FALSE	(0)
+#define FALSE			(0)
 #endif
 #ifndef TRUE
-#define TRUE 	(!FALSE)
+#define TRUE			(!FALSE)
 #endif
 
 /* CONFIG_FPGA bit assignments */
-#define CFG_FPGA_MAN(x)	(x)
-#define CFG_FPGA_DEV(x)	((x) << 8 )
-#define CFG_FPGA_IF(x)	((x) << 16 )
+#define CFG_FPGA_MAN(x)		(x)
+#define CFG_FPGA_DEV(x)		((x) << 8 )
+#define CFG_FPGA_IF(x)		((x) << 16 )
 
 /* FPGA Manufacturer bits in CONFIG_FPGA */
-#define CFG_FPGA_XILINX 		CFG_FPGA_MAN( 0x1 )
-#define CFG_FPGA_ALTERA			CFG_FPGA_MAN( 0x2 )
+#define CFG_FPGA_XILINX		CFG_FPGA_MAN( 0x1 )
+#define CFG_FPGA_ALTERA		CFG_FPGA_MAN( 0x2 )
 
 
 /* fpga_xxxx function return value definitions */
-#define FPGA_SUCCESS         0
-#define FPGA_FAIL           -1
+#define FPGA_SUCCESS		0
+#define FPGA_FAIL		-1
 
 /* device numbers must be non-negative */
-#define FPGA_INVALID_DEVICE -1
+#define FPGA_INVALID_DEVICE	-1
 
 /* root data type defintions */
-typedef enum {                 /* typedef fpga_type */
-	fpga_min_type,             /* range check value */
-    fpga_xilinx,               /* Xilinx Family) */
-    fpga_altera,               /* unimplemented */
-    fpga_undefined             /* invalid range check value */
-} fpga_type;                   /* end, typedef fpga_type */
+typedef enum {			/* typedef fpga_type */
+	fpga_min_type,		/* range check value */
+	fpga_xilinx,		/* Xilinx Family) */
+	fpga_altera,		/* unimplemented */
+	fpga_undefined		/* invalid range check value */
+} fpga_type;			/* end, typedef fpga_type */
 
-typedef struct {               /* typedef fpga_desc */
-    fpga_type   devtype;       /* switch value to select sub-functions */
-    void *      devdesc;       /* real device descriptor */
-} fpga_desc;                   /* end, typedef fpga_desc */
+typedef struct {		/* typedef fpga_desc */
+	fpga_type devtype;	/* switch value to select sub-functions */
+	void *devdesc;		/* real device descriptor */
+} fpga_desc;			/* end, typedef fpga_desc */
 
 
 /* root function definitions */
diff --git a/include/galileo/gt64260R.h b/include/galileo/gt64260R.h
index ebf087afca..c2cfb0670e 100644
--- a/include/galileo/gt64260R.h
+++ b/include/galileo/gt64260R.h
@@ -14,154 +14,154 @@
 #define	CPU_MASTER_CONTROL	0x160
 
 /****************************************/
-/* Processor Address Space				*/
+/* Processor Address Space		*/
 /****************************************/
 
 /* Sdram's BAR'S */
-#define SCS_0_LOW_DECODE_ADDRESS							0x008
-#define SCS_0_HIGH_DECODE_ADDRESS							0x010
-#define SCS_1_LOW_DECODE_ADDRESS							0x208
-#define SCS_1_HIGH_DECODE_ADDRESS							0x210
-#define SCS_2_LOW_DECODE_ADDRESS							0x018
-#define SCS_2_HIGH_DECODE_ADDRESS							0x020
-#define SCS_3_LOW_DECODE_ADDRESS							0x218
-#define SCS_3_HIGH_DECODE_ADDRESS							0x220
+#define SCS_0_LOW_DECODE_ADDRESS			0x008
+#define SCS_0_HIGH_DECODE_ADDRESS			0x010
+#define SCS_1_LOW_DECODE_ADDRESS			0x208
+#define SCS_1_HIGH_DECODE_ADDRESS			0x210
+#define SCS_2_LOW_DECODE_ADDRESS			0x018
+#define SCS_2_HIGH_DECODE_ADDRESS			0x020
+#define SCS_3_LOW_DECODE_ADDRESS			0x218
+#define SCS_3_HIGH_DECODE_ADDRESS			0x220
 /* Devices BAR'S */
-#define CS_0_LOW_DECODE_ADDRESS							    0x028
-#define CS_0_HIGH_DECODE_ADDRESS							0x030
-#define CS_1_LOW_DECODE_ADDRESS							    0x228
-#define CS_1_HIGH_DECODE_ADDRESS							0x230
-#define CS_2_LOW_DECODE_ADDRESS							    0x248
-#define CS_2_HIGH_DECODE_ADDRESS							0x250
-#define CS_3_LOW_DECODE_ADDRESS							    0x038
-#define CS_3_HIGH_DECODE_ADDRESS							0x040
-#define BOOTCS_LOW_DECODE_ADDRESS							0x238
-#define BOOTCS_HIGH_DECODE_ADDRESS							0x240
-
-#define PCI_0I_O_LOW_DECODE_ADDRESS							0x048
-#define PCI_0I_O_HIGH_DECODE_ADDRESS						0x050
-#define PCI_0MEMORY0_LOW_DECODE_ADDRESS						0x058
-#define PCI_0MEMORY0_HIGH_DECODE_ADDRESS					0x060
-#define PCI_0MEMORY1_LOW_DECODE_ADDRESS						0x080
-#define PCI_0MEMORY1_HIGH_DECODE_ADDRESS					0x088
-#define PCI_0MEMORY2_LOW_DECODE_ADDRESS						0x258
-#define PCI_0MEMORY2_HIGH_DECODE_ADDRESS					0x260
-#define PCI_0MEMORY3_LOW_DECODE_ADDRESS						0x280
-#define PCI_0MEMORY3_HIGH_DECODE_ADDRESS					0x288
-
-#define PCI_1I_O_LOW_DECODE_ADDRESS							0x090
-#define PCI_1I_O_HIGH_DECODE_ADDRESS						0x098
-#define PCI_1MEMORY0_LOW_DECODE_ADDRESS						0x0a0
-#define PCI_1MEMORY0_HIGH_DECODE_ADDRESS					0x0a8
-#define PCI_1MEMORY1_LOW_DECODE_ADDRESS						0x0b0
-#define PCI_1MEMORY1_HIGH_DECODE_ADDRESS					0x0b8
-#define PCI_1MEMORY2_LOW_DECODE_ADDRESS						0x2a0
-#define PCI_1MEMORY2_HIGH_DECODE_ADDRESS					0x2a8
-#define PCI_1MEMORY3_LOW_DECODE_ADDRESS						0x2b0
-#define PCI_1MEMORY3_HIGH_DECODE_ADDRESS					0x2b8
+#define CS_0_LOW_DECODE_ADDRESS				0x028
+#define CS_0_HIGH_DECODE_ADDRESS			0x030
+#define CS_1_LOW_DECODE_ADDRESS				0x228
+#define CS_1_HIGH_DECODE_ADDRESS			0x230
+#define CS_2_LOW_DECODE_ADDRESS				0x248
+#define CS_2_HIGH_DECODE_ADDRESS			0x250
+#define CS_3_LOW_DECODE_ADDRESS				0x038
+#define CS_3_HIGH_DECODE_ADDRESS			0x040
+#define BOOTCS_LOW_DECODE_ADDRESS			0x238
+#define BOOTCS_HIGH_DECODE_ADDRESS			0x240
+
+#define PCI_0I_O_LOW_DECODE_ADDRESS			0x048
+#define PCI_0I_O_HIGH_DECODE_ADDRESS			0x050
+#define PCI_0MEMORY0_LOW_DECODE_ADDRESS			0x058
+#define PCI_0MEMORY0_HIGH_DECODE_ADDRESS		0x060
+#define PCI_0MEMORY1_LOW_DECODE_ADDRESS			0x080
+#define PCI_0MEMORY1_HIGH_DECODE_ADDRESS		0x088
+#define PCI_0MEMORY2_LOW_DECODE_ADDRESS			0x258
+#define PCI_0MEMORY2_HIGH_DECODE_ADDRESS		0x260
+#define PCI_0MEMORY3_LOW_DECODE_ADDRESS			0x280
+#define PCI_0MEMORY3_HIGH_DECODE_ADDRESS		0x288
+
+#define PCI_1I_O_LOW_DECODE_ADDRESS			0x090
+#define PCI_1I_O_HIGH_DECODE_ADDRESS			0x098
+#define PCI_1MEMORY0_LOW_DECODE_ADDRESS			0x0a0
+#define PCI_1MEMORY0_HIGH_DECODE_ADDRESS		0x0a8
+#define PCI_1MEMORY1_LOW_DECODE_ADDRESS			0x0b0
+#define PCI_1MEMORY1_HIGH_DECODE_ADDRESS		0x0b8
+#define PCI_1MEMORY2_LOW_DECODE_ADDRESS			0x2a0
+#define PCI_1MEMORY2_HIGH_DECODE_ADDRESS		0x2a8
+#define PCI_1MEMORY3_LOW_DECODE_ADDRESS			0x2b0
+#define PCI_1MEMORY3_HIGH_DECODE_ADDRESS		0x2b8
 
 
-#define INTERNAL_SPACE_DECODE								0x068
+#define INTERNAL_SPACE_DECODE				0x068
 
-#define CPU_0_LOW_DECODE_ADDRESS                            0x290
-#define CPU_0_HIGH_DECODE_ADDRESS                           0x298
-#define CPU_1_LOW_DECODE_ADDRESS                            0x2c0
-#define CPU_1_HIGH_DECODE_ADDRESS                           0x2c8
+#define CPU_0_LOW_DECODE_ADDRESS			0x290
+#define CPU_0_HIGH_DECODE_ADDRESS			0x298
+#define CPU_1_LOW_DECODE_ADDRESS			0x2c0
+#define CPU_1_HIGH_DECODE_ADDRESS			0x2c8
 
-#define PCI_0I_O_ADDRESS_REMAP								0x0f0
-#define PCI_0MEMORY0_ADDRESS_REMAP  			   			0x0f8
-#define PCI_0MEMORY0_HIGH_ADDRESS_REMAP			   			0x320
-#define PCI_0MEMORY1_ADDRESS_REMAP  			   			0x100
-#define PCI_0MEMORY1_HIGH_ADDRESS_REMAP			   			0x328
-#define PCI_0MEMORY2_ADDRESS_REMAP  			   			0x2f8
-#define PCI_0MEMORY2_HIGH_ADDRESS_REMAP			   			0x330
-#define PCI_0MEMORY3_ADDRESS_REMAP  			   			0x300
-#define PCI_0MEMORY3_HIGH_ADDRESS_REMAP			   			0x338
+#define PCI_0I_O_ADDRESS_REMAP				0x0f0
+#define PCI_0MEMORY0_ADDRESS_REMAP			0x0f8
+#define PCI_0MEMORY0_HIGH_ADDRESS_REMAP			0x320
+#define PCI_0MEMORY1_ADDRESS_REMAP			0x100
+#define PCI_0MEMORY1_HIGH_ADDRESS_REMAP			0x328
+#define PCI_0MEMORY2_ADDRESS_REMAP			0x2f8
+#define PCI_0MEMORY2_HIGH_ADDRESS_REMAP			0x330
+#define PCI_0MEMORY3_ADDRESS_REMAP			0x300
+#define PCI_0MEMORY3_HIGH_ADDRESS_REMAP			0x338
 
-#define PCI_1I_O_ADDRESS_REMAP								0x108
-#define PCI_1MEMORY0_ADDRESS_REMAP  				   		0x110
-#define PCI_1MEMORY0_HIGH_ADDRESS_REMAP				   		0x340
-#define PCI_1MEMORY1_ADDRESS_REMAP  					   	0x118
-#define PCI_1MEMORY1_HIGH_ADDRESS_REMAP					   	0x348
-#define PCI_1MEMORY2_ADDRESS_REMAP  					   	0x310
-#define PCI_1MEMORY2_HIGH_ADDRESS_REMAP					   	0x350
-#define PCI_1MEMORY3_ADDRESS_REMAP  					   	0x318
-#define PCI_1MEMORY3_HIGH_ADDRESS_REMAP					   	0x358
+#define PCI_1I_O_ADDRESS_REMAP				0x108
+#define PCI_1MEMORY0_ADDRESS_REMAP			0x110
+#define PCI_1MEMORY0_HIGH_ADDRESS_REMAP			0x340
+#define PCI_1MEMORY1_ADDRESS_REMAP			0x118
+#define PCI_1MEMORY1_HIGH_ADDRESS_REMAP			0x348
+#define PCI_1MEMORY2_ADDRESS_REMAP			0x310
+#define PCI_1MEMORY2_HIGH_ADDRESS_REMAP			0x350
+#define PCI_1MEMORY3_ADDRESS_REMAP			0x318
+#define PCI_1MEMORY3_HIGH_ADDRESS_REMAP			0x358
 
 
 /****************************************/
-/* CPU Sync Barrier             		*/
+/* CPU Sync Barrier			*/
 /****************************************/
 
-#define PCI_0SYNC_BARIER_VIRTUAL_REGISTER					0x0c0
-#define PCI_1SYNC_BARIER_VIRTUAL_REGISTER					0x0c8
+#define PCI_0SYNC_BARIER_VIRTUAL_REGISTER		0x0c0
+#define PCI_1SYNC_BARIER_VIRTUAL_REGISTER		0x0c8
 
 
 /****************************************/
-/* CPU Access Protect             		*/
+/* CPU Access Protect			*/
 /****************************************/
 
-#define CPU_LOW_PROTECT_ADDRESS_0                           0x180
-#define CPU_HIGH_PROTECT_ADDRESS_0                          0x188
-#define CPU_LOW_PROTECT_ADDRESS_1                           0x190
-#define CPU_HIGH_PROTECT_ADDRESS_1                          0x198
-#define CPU_LOW_PROTECT_ADDRESS_2                           0x1a0
-#define CPU_HIGH_PROTECT_ADDRESS_2                          0x1a8
-#define CPU_LOW_PROTECT_ADDRESS_3                           0x1b0
-#define CPU_HIGH_PROTECT_ADDRESS_3                          0x1b8
-#define CPU_LOW_PROTECT_ADDRESS_4                           0x1c0
-#define CPU_HIGH_PROTECT_ADDRESS_4                          0x1c8
-#define CPU_LOW_PROTECT_ADDRESS_5                           0x1d0
-#define CPU_HIGH_PROTECT_ADDRESS_5                          0x1d8
-#define CPU_LOW_PROTECT_ADDRESS_6                           0x1e0
-#define CPU_HIGH_PROTECT_ADDRESS_6                          0x1e8
-#define CPU_LOW_PROTECT_ADDRESS_7                           0x1f0
-#define CPU_HIGH_PROTECT_ADDRESS_7                          0x1f8
+#define CPU_LOW_PROTECT_ADDRESS_0			0x180
+#define CPU_HIGH_PROTECT_ADDRESS_0			0x188
+#define CPU_LOW_PROTECT_ADDRESS_1			0x190
+#define CPU_HIGH_PROTECT_ADDRESS_1			0x198
+#define CPU_LOW_PROTECT_ADDRESS_2			0x1a0
+#define CPU_HIGH_PROTECT_ADDRESS_2			0x1a8
+#define CPU_LOW_PROTECT_ADDRESS_3			0x1b0
+#define CPU_HIGH_PROTECT_ADDRESS_3			0x1b8
+#define CPU_LOW_PROTECT_ADDRESS_4			0x1c0
+#define CPU_HIGH_PROTECT_ADDRESS_4			0x1c8
+#define CPU_LOW_PROTECT_ADDRESS_5			0x1d0
+#define CPU_HIGH_PROTECT_ADDRESS_5			0x1d8
+#define CPU_LOW_PROTECT_ADDRESS_6			0x1e0
+#define CPU_HIGH_PROTECT_ADDRESS_6			0x1e8
+#define CPU_LOW_PROTECT_ADDRESS_7			0x1f0
+#define CPU_HIGH_PROTECT_ADDRESS_7			0x1f8
 
 
 /****************************************/
-/*          Snoop Control          		*/
+/*	    Snoop Control		*/
 /****************************************/
 
-#define SNOOP_BASE_ADDRESS_0                                0x380
-#define SNOOP_TOP_ADDRESS_0                                 0x388
-#define SNOOP_BASE_ADDRESS_1                                0x390
-#define SNOOP_TOP_ADDRESS_1                                 0x398
-#define SNOOP_BASE_ADDRESS_2                                0x3a0
-#define SNOOP_TOP_ADDRESS_2                                 0x3a8
-#define SNOOP_BASE_ADDRESS_3                                0x3b0
-#define SNOOP_TOP_ADDRESS_3                                 0x3b8
+#define SNOOP_BASE_ADDRESS_0				0x380
+#define SNOOP_TOP_ADDRESS_0				0x388
+#define SNOOP_BASE_ADDRESS_1				0x390
+#define SNOOP_TOP_ADDRESS_1				0x398
+#define SNOOP_BASE_ADDRESS_2				0x3a0
+#define SNOOP_TOP_ADDRESS_2				0x3a8
+#define SNOOP_BASE_ADDRESS_3				0x3b0
+#define SNOOP_TOP_ADDRESS_3				0x3b8
 
 /****************************************/
-/*          CPU Error Report       		*/
+/*	    CPU Error Report		*/
 /****************************************/
 
-#define CPU_ERROR_ADDRESS_LOW 							    0x070
-#define CPU_ERROR_ADDRESS_HIGH 							    0x078
-#define CPU_ERROR_DATA_LOW                                  0x128
-#define CPU_ERROR_DATA_HIGH                                 0x130
-#define CPU_ERROR_PARITY                                    0x138
-#define CPU_ERROR_CAUSE                                     0x140
-#define CPU_ERROR_MASK                                      0x148
+#define CPU_ERROR_ADDRESS_LOW				0x070
+#define CPU_ERROR_ADDRESS_HIGH				0x078
+#define CPU_ERROR_DATA_LOW				0x128
+#define CPU_ERROR_DATA_HIGH				0x130
+#define CPU_ERROR_PARITY				0x138
+#define CPU_ERROR_CAUSE					0x140
+#define CPU_ERROR_MASK					0x148
 
 /****************************************/
-/*          Pslave Debug           		*/
+/*	    Pslave Debug		*/
 /****************************************/
 
-#define X_0_ADDRESS                                         0x360
-#define X_0_COMMAND_ID                                      0x368
-#define X_1_ADDRESS                                         0x370
-#define X_1_COMMAND_ID                                      0x378
-#define WRITE_DATA_LOW                                      0x3c0
-#define WRITE_DATA_HIGH                                     0x3c8
-#define WRITE_BYTE_ENABLE                                   0x3e0
-#define READ_DATA_LOW                                       0x3d0
-#define READ_DATA_HIGH                                      0x3d8
-#define READ_ID                                             0x3e8
+#define X_0_ADDRESS					0x360
+#define X_0_COMMAND_ID					0x368
+#define X_1_ADDRESS					0x370
+#define X_1_COMMAND_ID					0x378
+#define WRITE_DATA_LOW					0x3c0
+#define WRITE_DATA_HIGH					0x3c8
+#define WRITE_BYTE_ENABLE				0x3e0
+#define READ_DATA_LOW					0x3d0
+#define READ_DATA_HIGH					0x3d8
+#define READ_ID						0x3e8
 
 
 /****************************************/
-/* SDRAM and Device Address Space		*/
+/* SDRAM and Device Address Space	*/
 /****************************************/
 
 
@@ -191,1004 +191,1004 @@
 
 
 /****************************************/
-/* SDRAM Error Report 			*/
+/* SDRAM Error Report			*/
 /****************************************/
 
-#define SDRAM_ERROR_DATA_LOW                                0x484
-#define SDRAM_ERROR_DATA_HIGH                               0x480
-#define SDRAM_AND_DEVICE_ERROR_ADDRESS                      0x490
-#define SDRAM_RECEIVED_ECC                                  0x488
-#define SDRAM_CALCULATED_ECC                                0x48c
-#define SDRAM_ECC_CONTROL                                   0x494
-#define SDRAM_ECC_ERROR_COUNTER                             0x498
+#define SDRAM_ERROR_DATA_LOW				0x484
+#define SDRAM_ERROR_DATA_HIGH				0x480
+#define SDRAM_AND_DEVICE_ERROR_ADDRESS			0x490
+#define SDRAM_RECEIVED_ECC				0x488
+#define SDRAM_CALCULATED_ECC				0x48c
+#define SDRAM_ECC_CONTROL				0x494
+#define SDRAM_ECC_ERROR_COUNTER				0x498
 
 
 /****************************************/
 /* SDunit Debug (for internal use)	*/
 /****************************************/
 
-#define X0_ADDRESS                                          0x500
-#define X0_COMMAND_AND_ID                                   0x504
-#define X0_WRITE_DATA_LOW                                   0x508
-#define X0_WRITE_DATA_HIGH                                  0x50c
-#define X0_WRITE_BYTE_ENABLE                                0x518
-#define X0_READ_DATA_LOW                                    0x510
-#define X0_READ_DATA_HIGH                                   0x514
-#define X0_READ_ID                                          0x51c
-#define X1_ADDRESS                                          0x520
-#define X1_COMMAND_AND_ID                                   0x524
-#define X1_WRITE_DATA_LOW                                   0x528
-#define X1_WRITE_DATA_HIGH                                  0x52c
-#define X1_WRITE_BYTE_ENABLE                                0x538
-#define X1_READ_DATA_LOW                                    0x530
-#define X1_READ_DATA_HIGH                                   0x534
-#define X1_READ_ID                                          0x53c
-#define X0_SNOOP_ADDRESS                                    0x540
-#define X0_SNOOP_COMMAND                                    0x544
-#define X1_SNOOP_ADDRESS                                    0x548
-#define X1_SNOOP_COMMAND                                    0x54c
-
-
-/****************************************/
-/* Device Parameters					*/
-/****************************************/
-
-#define DEVICE_BANK0PARAMETERS								0x45c
-#define DEVICE_BANK1PARAMETERS								0x460
-#define DEVICE_BANK2PARAMETERS								0x464
-#define DEVICE_BANK3PARAMETERS								0x468
-#define DEVICE_BOOT_BANK_PARAMETERS							0x46c
-#define DEVICE_CONTROL                                      0x4c0
-#define DEVICE_CROSS_BAR_CONTROL_LOW                        0x4c8
-#define DEVICE_CROSS_BAR_CONTROL_HIGH                       0x4cc
-#define DEVICE_CROSS_BAR_TIMEOUT                            0x4c4
-
-
-/****************************************/
-/* Device Interrupt 					*/
-/****************************************/
-
-#define DEVICE_INTERRUPT_CAUSE                              0x4d0
-#define DEVICE_INTERRUPT_MASK                               0x4d4
-#define DEVICE_ERROR_ADDRESS                                0x4d8
-
-/****************************************/
-/* DMA Record							*/
-/****************************************/
-
-#define CHANNEL0_DMA_BYTE_COUNT						0x800
-#define CHANNEL1_DMA_BYTE_COUNT	 							0x804
-#define CHANNEL2_DMA_BYTE_COUNT	 							0x808
-#define CHANNEL3_DMA_BYTE_COUNT	 							0x80C
-#define CHANNEL4_DMA_BYTE_COUNT								0x900
-#define CHANNEL5_DMA_BYTE_COUNT	 							0x904
-#define CHANNEL6_DMA_BYTE_COUNT	 							0x908
-#define CHANNEL7_DMA_BYTE_COUNT	 							0x90C
-#define CHANNEL0_DMA_SOURCE_ADDRESS							0x810
-#define CHANNEL1_DMA_SOURCE_ADDRESS							0x814
-#define CHANNEL2_DMA_SOURCE_ADDRESS							0x818
-#define CHANNEL3_DMA_SOURCE_ADDRESS							0x81C
-#define CHANNEL4_DMA_SOURCE_ADDRESS							0x910
-#define CHANNEL5_DMA_SOURCE_ADDRESS							0x914
-#define CHANNEL6_DMA_SOURCE_ADDRESS							0x918
-#define CHANNEL7_DMA_SOURCE_ADDRESS							0x91C
-#define CHANNEL0_DMA_DESTINATION_ADDRESS					0x820
-#define CHANNEL1_DMA_DESTINATION_ADDRESS					0x824
-#define CHANNEL2_DMA_DESTINATION_ADDRESS					0x828
-#define CHANNEL3_DMA_DESTINATION_ADDRESS					0x82C
-#define CHANNEL4_DMA_DESTINATION_ADDRESS					0x920
-#define CHANNEL5_DMA_DESTINATION_ADDRESS					0x924
-#define CHANNEL6_DMA_DESTINATION_ADDRESS					0x928
-#define CHANNEL7_DMA_DESTINATION_ADDRESS					0x92C
-#define CHANNEL0NEXT_RECORD_POINTER							0x830
-#define CHANNEL1NEXT_RECORD_POINTER							0x834
-#define CHANNEL2NEXT_RECORD_POINTER							0x838
-#define CHANNEL3NEXT_RECORD_POINTER							0x83C
-#define CHANNEL4NEXT_RECORD_POINTER							0x930
-#define CHANNEL5NEXT_RECORD_POINTER							0x934
-#define CHANNEL6NEXT_RECORD_POINTER							0x938
-#define CHANNEL7NEXT_RECORD_POINTER							0x93C
-#define CHANNEL0CURRENT_DESCRIPTOR_POINTER					0x870
-#define CHANNEL1CURRENT_DESCRIPTOR_POINTER					0x874
-#define CHANNEL2CURRENT_DESCRIPTOR_POINTER					0x878
-#define CHANNEL3CURRENT_DESCRIPTOR_POINTER					0x87C
-#define CHANNEL4CURRENT_DESCRIPTOR_POINTER					0x970
-#define CHANNEL5CURRENT_DESCRIPTOR_POINTER					0x974
-#define CHANNEL6CURRENT_DESCRIPTOR_POINTER					0x978
-#define CHANNEL7CURRENT_DESCRIPTOR_POINTER					0x97C
-#define CHANNEL0_DMA_SOURCE_HIGH_PCI_ADDRESS                0x890
-#define CHANNEL1_DMA_SOURCE_HIGH_PCI_ADDRESS                0x894
-#define CHANNEL2_DMA_SOURCE_HIGH_PCI_ADDRESS                0x898
-#define CHANNEL3_DMA_SOURCE_HIGH_PCI_ADDRESS                0x89c
-#define CHANNEL4_DMA_SOURCE_HIGH_PCI_ADDRESS                0x990
-#define CHANNEL5_DMA_SOURCE_HIGH_PCI_ADDRESS                0x994
-#define CHANNEL6_DMA_SOURCE_HIGH_PCI_ADDRESS                0x998
-#define CHANNEL7_DMA_SOURCE_HIGH_PCI_ADDRESS                0x99c
-#define CHANNEL0_DMA_DESTINATION_HIGH_PCI_ADDRESS           0x8a0
-#define CHANNEL1_DMA_DESTINATION_HIGH_PCI_ADDRESS           0x8a4
-#define CHANNEL2_DMA_DESTINATION_HIGH_PCI_ADDRESS           0x8a8
-#define CHANNEL3_DMA_DESTINATION_HIGH_PCI_ADDRESS           0x8ac
-#define CHANNEL4_DMA_DESTINATION_HIGH_PCI_ADDRESS           0x9a0
-#define CHANNEL5_DMA_DESTINATION_HIGH_PCI_ADDRESS           0x9a4
-#define CHANNEL6_DMA_DESTINATION_HIGH_PCI_ADDRESS           0x9a8
-#define CHANNEL7_DMA_DESTINATION_HIGH_PCI_ADDRESS           0x9ac
-#define CHANNEL0_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS   0x8b0
-#define CHANNEL1_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS   0x8b4
-#define CHANNEL2_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS   0x8b8
-#define CHANNEL3_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS   0x8bc
-#define CHANNEL4_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS   0x9b0
-#define CHANNEL5_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS   0x9b4
-#define CHANNEL6_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS   0x9b8
-#define CHANNEL7_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS   0x9bc
-
-/****************************************/
-/* DMA Channel Control					*/
-/****************************************/
-
-#define CHANNEL0CONTROL 									0x840
-#define CHANNEL0CONTROL_HIGH								0x880
-#define CHANNEL1CONTROL 									0x844
-#define CHANNEL1CONTROL_HIGH								0x884
-#define CHANNEL2CONTROL 									0x848
-#define CHANNEL2CONTROL_HIGH								0x888
-#define CHANNEL3CONTROL 									0x84C
-#define CHANNEL3CONTROL_HIGH								0x88C
-
-#define CHANNEL4CONTROL 									0x940
-#define CHANNEL4CONTROL_HIGH								0x980
-#define CHANNEL5CONTROL 									0x944
-#define CHANNEL5CONTROL_HIGH								0x984
-#define CHANNEL6CONTROL 									0x948
-#define CHANNEL6CONTROL_HIGH								0x988
-#define CHANNEL7CONTROL 									0x94C
-#define CHANNEL7CONTROL_HIGH								0x98C
-
-
-/****************************************/
-/* DMA Arbiter							*/
-/****************************************/
-
-#define ARBITER_CONTROL_0_3									0x860
-#define ARBITER_CONTROL_4_7									0x960
-
-
-/****************************************/
-/* DMA Interrupt						*/
-/****************************************/
-
-#define CHANELS0_3_INTERRUPT_CAUSE                          0x8c0
-#define CHANELS0_3_INTERRUPT_MASK                           0x8c4
-#define CHANELS0_3_ERROR_ADDRESS                            0x8c8
-#define CHANELS0_3_ERROR_SELECT                             0x8cc
-#define CHANELS4_7_INTERRUPT_CAUSE                          0x9c0
-#define CHANELS4_7_INTERRUPT_MASK                           0x9c4
-#define CHANELS4_7_ERROR_ADDRESS                            0x9c8
-#define CHANELS4_7_ERROR_SELECT                             0x9cc
-
-
-/****************************************/
-/* DMA Debug (for internal use)         */
-/****************************************/
-
-#define DMA_X0_ADDRESS                                      0x8e0
-#define DMA_X0_COMMAND_AND_ID                               0x8e4
-#define DMA_X0_WRITE_DATA_LOW                               0x8e8
-#define DMA_X0_WRITE_DATA_HIGH                              0x8ec
-#define DMA_X0_WRITE_BYTE_ENABLE                            0x8f8
-#define DMA_X0_READ_DATA_LOW                                0x8f0
-#define DMA_X0_READ_DATA_HIGH                               0x8f4
-#define DMA_X0_READ_ID                                      0x8fc
-#define DMA_X1_ADDRESS                                      0x9e0
-#define DMA_X1_COMMAND_AND_ID                               0x9e4
-#define DMA_X1_WRITE_DATA_LOW                               0x9e8
-#define DMA_X1_WRITE_DATA_HIGH                              0x9ec
-#define DMA_X1_WRITE_BYTE_ENABLE                            0x9f8
-#define DMA_X1_READ_DATA_LOW                                0x9f0
-#define DMA_X1_READ_DATA_HIGH                               0x9f4
-#define DMA_X1_READ_ID                                      0x9fc
-
-/****************************************/
-/* Timer_Counter 						*/
-/****************************************/
-
-#define TIMER_COUNTER0										0x850
-#define TIMER_COUNTER1										0x854
-#define TIMER_COUNTER2										0x858
-#define TIMER_COUNTER3										0x85C
-#define TIMER_COUNTER_0_3_CONTROL							0x864
-#define TIMER_COUNTER_0_3_INTERRUPT_CAUSE					0x868
-#define TIMER_COUNTER_0_3_INTERRUPT_MASK      				0x86c
-#define TIMER_COUNTER4										0x950
-#define TIMER_COUNTER5										0x954
-#define TIMER_COUNTER6										0x958
-#define TIMER_COUNTER7										0x95C
-#define TIMER_COUNTER_4_7_CONTROL							0x964
-#define TIMER_COUNTER_4_7_INTERRUPT_CAUSE					0x968
-#define TIMER_COUNTER_4_7_INTERRUPT_MASK      				0x96c
-
-/****************************************/
-/* PCI Slave Address Decoding           */
-/****************************************/
-
-#define PCI_0SCS_0_BANK_SIZE								0xc08
-#define PCI_1SCS_0_BANK_SIZE								0xc88
-#define PCI_0SCS_1_BANK_SIZE								0xd08
-#define PCI_1SCS_1_BANK_SIZE								0xd88
-#define PCI_0SCS_2_BANK_SIZE								0xc0c
-#define PCI_1SCS_2_BANK_SIZE								0xc8c
-#define PCI_0SCS_3_BANK_SIZE								0xd0c
-#define PCI_1SCS_3_BANK_SIZE								0xd8c
-#define PCI_0CS_0_BANK_SIZE							    	0xc10
-#define PCI_1CS_0_BANK_SIZE							    	0xc90
-#define PCI_0CS_1_BANK_SIZE							    	0xd10
-#define PCI_1CS_1_BANK_SIZE							    	0xd90
-#define PCI_0CS_2_BANK_SIZE							    	0xd18
-#define PCI_1CS_2_BANK_SIZE							    	0xd98
-#define PCI_0CS_3_BANK_SIZE					        		0xc14
-#define PCI_1CS_3_BANK_SIZE					        		0xc94
-#define PCI_0CS_BOOT_BANK_SIZE							    0xd14
-#define PCI_1CS_BOOT_BANK_SIZE							    0xd94
-#define PCI_0P2P_MEM0_BAR_SIZE                              0xd1c
-#define PCI_1P2P_MEM0_BAR_SIZE                              0xd9c
-#define PCI_0P2P_MEM1_BAR_SIZE                              0xd20
-#define PCI_1P2P_MEM1_BAR_SIZE                              0xda0
-#define PCI_0P2P_I_O_BAR_SIZE                               0xd24
-#define PCI_1P2P_I_O_BAR_SIZE                               0xda4
-#define PCI_0CPU_BAR_SIZE                                   0xd28
-#define PCI_1CPU_BAR_SIZE                                   0xda8
-#define PCI_0DAC_SCS_0_BANK_SIZE                            0xe00
-#define PCI_1DAC_SCS_0_BANK_SIZE                            0xe80
-#define PCI_0DAC_SCS_1_BANK_SIZE                            0xe04
-#define PCI_1DAC_SCS_1_BANK_SIZE                            0xe84
-#define PCI_0DAC_SCS_2_BANK_SIZE                            0xe08
-#define PCI_1DAC_SCS_2_BANK_SIZE                            0xe88
-#define PCI_0DAC_SCS_3_BANK_SIZE                            0xe0c
-#define PCI_1DAC_SCS_3_BANK_SIZE                            0xe8c
-#define PCI_0DAC_CS_0_BANK_SIZE                             0xe10
-#define PCI_1DAC_CS_0_BANK_SIZE                             0xe90
-#define PCI_0DAC_CS_1_BANK_SIZE                             0xe14
-#define PCI_1DAC_CS_1_BANK_SIZE                             0xe94
-#define PCI_0DAC_CS_2_BANK_SIZE                             0xe18
-#define PCI_1DAC_CS_2_BANK_SIZE                             0xe98
-#define PCI_0DAC_CS_3_BANK_SIZE                             0xe1c
-#define PCI_1DAC_CS_3_BANK_SIZE                             0xe9c
-#define PCI_0DAC_BOOTCS_BANK_SIZE                           0xe20
-#define PCI_1DAC_BOOTCS_BANK_SIZE                           0xea0
-#define PCI_0DAC_P2P_MEM0_BAR_SIZE                          0xe24
-#define PCI_1DAC_P2P_MEM0_BAR_SIZE                          0xea4
-#define PCI_0DAC_P2P_MEM1_BAR_SIZE                          0xe28
-#define PCI_1DAC_P2P_MEM1_BAR_SIZE                          0xea8
-#define PCI_0DAC_CPU_BAR_SIZE                               0xe2c
-#define PCI_1DAC_CPU_BAR_SIZE                               0xeac
-#define PCI_0EXPANSION_ROM_BAR_SIZE                         0xd2c
-#define PCI_1EXPANSION_ROM_BAR_SIZE                         0xdac
-#define PCI_0BASE_ADDRESS_REGISTERS_ENABLE 					0xc3c
-#define PCI_1BASE_ADDRESS_REGISTERS_ENABLE 					0xcbc
-#define PCI_0SCS_0_BASE_ADDRESS_REMAP						0xc48
-#define PCI_1SCS_0_BASE_ADDRESS_REMAP						0xcc8
-#define PCI_0SCS_1_BASE_ADDRESS_REMAP						0xd48
-#define PCI_1SCS_1_BASE_ADDRESS_REMAP						0xdc8
-#define PCI_0SCS_2_BASE_ADDRESS_REMAP						0xc4c
-#define PCI_1SCS_2_BASE_ADDRESS_REMAP						0xccc
-#define PCI_0SCS_3_BASE_ADDRESS_REMAP						0xd4c
-#define PCI_1SCS_3_BASE_ADDRESS_REMAP						0xdcc
-#define PCI_0CS_0_BASE_ADDRESS_REMAP						0xc50
-#define PCI_1CS_0_BASE_ADDRESS_REMAP						0xcd0
-#define PCI_0CS_1_BASE_ADDRESS_REMAP						0xd50
-#define PCI_1CS_1_BASE_ADDRESS_REMAP						0xdd0
-#define PCI_0CS_2_BASE_ADDRESS_REMAP						0xd58
-#define PCI_1CS_2_BASE_ADDRESS_REMAP						0xdd8
-#define PCI_0CS_3_BASE_ADDRESS_REMAP           				0xc54
-#define PCI_1CS_3_BASE_ADDRESS_REMAP           				0xcd4
-#define PCI_0CS_BOOTCS_BASE_ADDRESS_REMAP      				0xd54
-#define PCI_1CS_BOOTCS_BASE_ADDRESS_REMAP      				0xdd4
-#define PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_LOW                0xd5c
-#define PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_LOW                0xddc
-#define PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_HIGH               0xd60
-#define PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_HIGH               0xde0
-#define PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_LOW                0xd64
-#define PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_LOW                0xde4
-#define PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_HIGH               0xd68
-#define PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_HIGH               0xde8
-#define PCI_0P2P_I_O_BASE_ADDRESS_REMAP                     0xd6c
-#define PCI_1P2P_I_O_BASE_ADDRESS_REMAP                     0xdec
-#define PCI_0CPU_BASE_ADDRESS_REMAP                         0xd70
-#define PCI_1CPU_BASE_ADDRESS_REMAP                         0xdf0
-#define PCI_0DAC_SCS_0_BASE_ADDRESS_REMAP                   0xf00
-#define PCI_1DAC_SCS_0_BASE_ADDRESS_REMAP                   0xff0
-#define PCI_0DAC_SCS_1_BASE_ADDRESS_REMAP                   0xf04
-#define PCI_1DAC_SCS_1_BASE_ADDRESS_REMAP                   0xf84
-#define PCI_0DAC_SCS_2_BASE_ADDRESS_REMAP                   0xf08
-#define PCI_1DAC_SCS_2_BASE_ADDRESS_REMAP                   0xf88
-#define PCI_0DAC_SCS_3_BASE_ADDRESS_REMAP                   0xf0c
-#define PCI_1DAC_SCS_3_BASE_ADDRESS_REMAP                   0xf8c
-#define PCI_0DAC_CS_0_BASE_ADDRESS_REMAP                    0xf10
-#define PCI_1DAC_CS_0_BASE_ADDRESS_REMAP                    0xf90
-#define PCI_0DAC_CS_1_BASE_ADDRESS_REMAP                    0xf14
-#define PCI_1DAC_CS_1_BASE_ADDRESS_REMAP                    0xf94
-#define PCI_0DAC_CS_2_BASE_ADDRESS_REMAP                    0xf18
-#define PCI_1DAC_CS_2_BASE_ADDRESS_REMAP                    0xf98
-#define PCI_0DAC_CS_3_BASE_ADDRESS_REMAP                    0xf1c
-#define PCI_1DAC_CS_3_BASE_ADDRESS_REMAP                    0xf9c
-#define PCI_0DAC_BOOTCS_BASE_ADDRESS_REMAP                  0xf20
-#define PCI_1DAC_BOOTCS_BASE_ADDRESS_REMAP                  0xfa0
-#define PCI_0DAC_P2P_MEM0_BASE_ADDRESS_REMAP_LOW            0xf24
-#define PCI_1DAC_P2P_MEM0_BASE_ADDRESS_REMAP_LOW            0xfa4
-#define PCI_0DAC_P2P_MEM0_BASE_ADDRESS_REMAP_HIGH           0xf28
-#define PCI_1DAC_P2P_MEM0_BASE_ADDRESS_REMAP_HIGH           0xfa8
-#define PCI_0DAC_P2P_MEM1_BASE_ADDRESS_REMAP_LOW            0xf2c
-#define PCI_1DAC_P2P_MEM1_BASE_ADDRESS_REMAP_LOW            0xfac
-#define PCI_0DAC_P2P_MEM1_BASE_ADDRESS_REMAP_HIGH           0xf30
-#define PCI_1DAC_P2P_MEM1_BASE_ADDRESS_REMAP_HIGH           0xfb0
-#define PCI_0DAC_CPU_BASE_ADDRESS_REMAP                     0xf34
-#define PCI_1DAC_CPU_BASE_ADDRESS_REMAP                     0xfb4
-#define PCI_0EXPANSION_ROM_BASE_ADDRESS_REMAP               0xf38
-#define PCI_1EXPANSION_ROM_BASE_ADDRESS_REMAP               0xfb8
-#define PCI_0ADDRESS_DECODE_CONTROL                         0xd3c
-#define PCI_1ADDRESS_DECODE_CONTROL                         0xdbc
-
-/****************************************/
-/* PCI Control                          */
-/****************************************/
-
-#define PCI_0COMMAND										0xc00
-#define PCI_1COMMAND										0xc80
-#define PCI_0MODE                                           0xd00
-#define PCI_1MODE                                           0xd80
-#define PCI_0TIMEOUT_RETRY									0xc04
-#define PCI_1TIMEOUT_RETRY									0xc84
-#define PCI_0READ_BUFFER_DISCARD_TIMER                      0xd04
-#define PCI_1READ_BUFFER_DISCARD_TIMER                      0xd84
-#define MSI_0TRIGGER_TIMER                                  0xc38
-#define MSI_1TRIGGER_TIMER                                  0xcb8
-#define PCI_0ARBITER_CONTROL                                0x1d00
-#define PCI_1ARBITER_CONTROL                                0x1d80
+#define X0_ADDRESS					0x500
+#define X0_COMMAND_AND_ID				0x504
+#define X0_WRITE_DATA_LOW				0x508
+#define X0_WRITE_DATA_HIGH				0x50c
+#define X0_WRITE_BYTE_ENABLE				0x518
+#define X0_READ_DATA_LOW				0x510
+#define X0_READ_DATA_HIGH				0x514
+#define X0_READ_ID					0x51c
+#define X1_ADDRESS					0x520
+#define X1_COMMAND_AND_ID				0x524
+#define X1_WRITE_DATA_LOW				0x528
+#define X1_WRITE_DATA_HIGH				0x52c
+#define X1_WRITE_BYTE_ENABLE				0x538
+#define X1_READ_DATA_LOW				0x530
+#define X1_READ_DATA_HIGH				0x534
+#define X1_READ_ID					0x53c
+#define X0_SNOOP_ADDRESS				0x540
+#define X0_SNOOP_COMMAND				0x544
+#define X1_SNOOP_ADDRESS				0x548
+#define X1_SNOOP_COMMAND				0x54c
+
+
+/****************************************/
+/* Device Parameters			*/
+/****************************************/
+
+#define DEVICE_BANK0PARAMETERS				0x45c
+#define DEVICE_BANK1PARAMETERS				0x460
+#define DEVICE_BANK2PARAMETERS				0x464
+#define DEVICE_BANK3PARAMETERS				0x468
+#define DEVICE_BOOT_BANK_PARAMETERS			0x46c
+#define DEVICE_CONTROL					0x4c0
+#define DEVICE_CROSS_BAR_CONTROL_LOW			0x4c8
+#define DEVICE_CROSS_BAR_CONTROL_HIGH			0x4cc
+#define DEVICE_CROSS_BAR_TIMEOUT			0x4c4
+
+
+/****************************************/
+/* Device Interrupt			*/
+/****************************************/
+
+#define DEVICE_INTERRUPT_CAUSE				0x4d0
+#define DEVICE_INTERRUPT_MASK				0x4d4
+#define DEVICE_ERROR_ADDRESS				0x4d8
+
+/****************************************/
+/* DMA Record				*/
+/****************************************/
+
+#define CHANNEL0_DMA_BYTE_COUNT				0x800
+#define CHANNEL1_DMA_BYTE_COUNT				0x804
+#define CHANNEL2_DMA_BYTE_COUNT				0x808
+#define CHANNEL3_DMA_BYTE_COUNT				0x80C
+#define CHANNEL4_DMA_BYTE_COUNT				0x900
+#define CHANNEL5_DMA_BYTE_COUNT				0x904
+#define CHANNEL6_DMA_BYTE_COUNT				0x908
+#define CHANNEL7_DMA_BYTE_COUNT				0x90C
+#define CHANNEL0_DMA_SOURCE_ADDRESS			0x810
+#define CHANNEL1_DMA_SOURCE_ADDRESS			0x814
+#define CHANNEL2_DMA_SOURCE_ADDRESS			0x818
+#define CHANNEL3_DMA_SOURCE_ADDRESS			0x81C
+#define CHANNEL4_DMA_SOURCE_ADDRESS			0x910
+#define CHANNEL5_DMA_SOURCE_ADDRESS			0x914
+#define CHANNEL6_DMA_SOURCE_ADDRESS			0x918
+#define CHANNEL7_DMA_SOURCE_ADDRESS			0x91C
+#define CHANNEL0_DMA_DESTINATION_ADDRESS		0x820
+#define CHANNEL1_DMA_DESTINATION_ADDRESS		0x824
+#define CHANNEL2_DMA_DESTINATION_ADDRESS		0x828
+#define CHANNEL3_DMA_DESTINATION_ADDRESS		0x82C
+#define CHANNEL4_DMA_DESTINATION_ADDRESS		0x920
+#define CHANNEL5_DMA_DESTINATION_ADDRESS		0x924
+#define CHANNEL6_DMA_DESTINATION_ADDRESS		0x928
+#define CHANNEL7_DMA_DESTINATION_ADDRESS		0x92C
+#define CHANNEL0NEXT_RECORD_POINTER			0x830
+#define CHANNEL1NEXT_RECORD_POINTER			0x834
+#define CHANNEL2NEXT_RECORD_POINTER			0x838
+#define CHANNEL3NEXT_RECORD_POINTER			0x83C
+#define CHANNEL4NEXT_RECORD_POINTER			0x930
+#define CHANNEL5NEXT_RECORD_POINTER			0x934
+#define CHANNEL6NEXT_RECORD_POINTER			0x938
+#define CHANNEL7NEXT_RECORD_POINTER			0x93C
+#define CHANNEL0CURRENT_DESCRIPTOR_POINTER		0x870
+#define CHANNEL1CURRENT_DESCRIPTOR_POINTER		0x874
+#define CHANNEL2CURRENT_DESCRIPTOR_POINTER		0x878
+#define CHANNEL3CURRENT_DESCRIPTOR_POINTER		0x87C
+#define CHANNEL4CURRENT_DESCRIPTOR_POINTER		0x970
+#define CHANNEL5CURRENT_DESCRIPTOR_POINTER		0x974
+#define CHANNEL6CURRENT_DESCRIPTOR_POINTER		0x978
+#define CHANNEL7CURRENT_DESCRIPTOR_POINTER		0x97C
+#define CHANNEL0_DMA_SOURCE_HIGH_PCI_ADDRESS		0x890
+#define CHANNEL1_DMA_SOURCE_HIGH_PCI_ADDRESS		0x894
+#define CHANNEL2_DMA_SOURCE_HIGH_PCI_ADDRESS		0x898
+#define CHANNEL3_DMA_SOURCE_HIGH_PCI_ADDRESS		0x89c
+#define CHANNEL4_DMA_SOURCE_HIGH_PCI_ADDRESS		0x990
+#define CHANNEL5_DMA_SOURCE_HIGH_PCI_ADDRESS		0x994
+#define CHANNEL6_DMA_SOURCE_HIGH_PCI_ADDRESS		0x998
+#define CHANNEL7_DMA_SOURCE_HIGH_PCI_ADDRESS		0x99c
+#define CHANNEL0_DMA_DESTINATION_HIGH_PCI_ADDRESS	0x8a0
+#define CHANNEL1_DMA_DESTINATION_HIGH_PCI_ADDRESS	0x8a4
+#define CHANNEL2_DMA_DESTINATION_HIGH_PCI_ADDRESS	0x8a8
+#define CHANNEL3_DMA_DESTINATION_HIGH_PCI_ADDRESS	0x8ac
+#define CHANNEL4_DMA_DESTINATION_HIGH_PCI_ADDRESS	0x9a0
+#define CHANNEL5_DMA_DESTINATION_HIGH_PCI_ADDRESS	0x9a4
+#define CHANNEL6_DMA_DESTINATION_HIGH_PCI_ADDRESS	0x9a8
+#define CHANNEL7_DMA_DESTINATION_HIGH_PCI_ADDRESS	0x9ac
+#define CHANNEL0_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS  0x8b0
+#define CHANNEL1_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS  0x8b4
+#define CHANNEL2_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS  0x8b8
+#define CHANNEL3_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS  0x8bc
+#define CHANNEL4_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS  0x9b0
+#define CHANNEL5_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS  0x9b4
+#define CHANNEL6_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS  0x9b8
+#define CHANNEL7_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS  0x9bc
+
+/****************************************/
+/* DMA Channel Control			*/
+/****************************************/
+
+#define CHANNEL0CONTROL					0x840
+#define CHANNEL0CONTROL_HIGH				0x880
+#define CHANNEL1CONTROL					0x844
+#define CHANNEL1CONTROL_HIGH				0x884
+#define CHANNEL2CONTROL					0x848
+#define CHANNEL2CONTROL_HIGH				0x888
+#define CHANNEL3CONTROL					0x84C
+#define CHANNEL3CONTROL_HIGH				0x88C
+
+#define CHANNEL4CONTROL					0x940
+#define CHANNEL4CONTROL_HIGH				0x980
+#define CHANNEL5CONTROL					0x944
+#define CHANNEL5CONTROL_HIGH				0x984
+#define CHANNEL6CONTROL					0x948
+#define CHANNEL6CONTROL_HIGH				0x988
+#define CHANNEL7CONTROL					0x94C
+#define CHANNEL7CONTROL_HIGH				0x98C
+
+
+/****************************************/
+/* DMA Arbiter				*/
+/****************************************/
+
+#define ARBITER_CONTROL_0_3										0x860
+#define ARBITER_CONTROL_4_7										0x960
+
+
+/****************************************/
+/* DMA Interrupt			*/
+/****************************************/
+
+#define CHANELS0_3_INTERRUPT_CAUSE			0x8c0
+#define CHANELS0_3_INTERRUPT_MASK			0x8c4
+#define CHANELS0_3_ERROR_ADDRESS			0x8c8
+#define CHANELS0_3_ERROR_SELECT				0x8cc
+#define CHANELS4_7_INTERRUPT_CAUSE			0x9c0
+#define CHANELS4_7_INTERRUPT_MASK			0x9c4
+#define CHANELS4_7_ERROR_ADDRESS			0x9c8
+#define CHANELS4_7_ERROR_SELECT				0x9cc
+
+
+/****************************************/
+/* DMA Debug (for internal use)		*/
+/****************************************/
+
+#define DMA_X0_ADDRESS					0x8e0
+#define DMA_X0_COMMAND_AND_ID				0x8e4
+#define DMA_X0_WRITE_DATA_LOW				0x8e8
+#define DMA_X0_WRITE_DATA_HIGH				0x8ec
+#define DMA_X0_WRITE_BYTE_ENABLE			0x8f8
+#define DMA_X0_READ_DATA_LOW				0x8f0
+#define DMA_X0_READ_DATA_HIGH				0x8f4
+#define DMA_X0_READ_ID					0x8fc
+#define DMA_X1_ADDRESS					0x9e0
+#define DMA_X1_COMMAND_AND_ID				0x9e4
+#define DMA_X1_WRITE_DATA_LOW				0x9e8
+#define DMA_X1_WRITE_DATA_HIGH				0x9ec
+#define DMA_X1_WRITE_BYTE_ENABLE			0x9f8
+#define DMA_X1_READ_DATA_LOW				0x9f0
+#define DMA_X1_READ_DATA_HIGH				0x9f4
+#define DMA_X1_READ_ID					0x9fc
+
+/****************************************/
+/* Timer_Counter			*/
+/****************************************/
+
+#define TIMER_COUNTER0					0x850
+#define TIMER_COUNTER1					0x854
+#define TIMER_COUNTER2					0x858
+#define TIMER_COUNTER3					0x85C
+#define TIMER_COUNTER_0_3_CONTROL			0x864
+#define TIMER_COUNTER_0_3_INTERRUPT_CAUSE		0x868
+#define TIMER_COUNTER_0_3_INTERRUPT_MASK		0x86c
+#define TIMER_COUNTER4					0x950
+#define TIMER_COUNTER5					0x954
+#define TIMER_COUNTER6					0x958
+#define TIMER_COUNTER7					0x95C
+#define TIMER_COUNTER_4_7_CONTROL			0x964
+#define TIMER_COUNTER_4_7_INTERRUPT_CAUSE		0x968
+#define TIMER_COUNTER_4_7_INTERRUPT_MASK		0x96c
+
+/****************************************/
+/* PCI Slave Address Decoding		*/
+/****************************************/
+
+#define PCI_0SCS_0_BANK_SIZE				0xc08
+#define PCI_1SCS_0_BANK_SIZE				0xc88
+#define PCI_0SCS_1_BANK_SIZE				0xd08
+#define PCI_1SCS_1_BANK_SIZE				0xd88
+#define PCI_0SCS_2_BANK_SIZE				0xc0c
+#define PCI_1SCS_2_BANK_SIZE				0xc8c
+#define PCI_0SCS_3_BANK_SIZE				0xd0c
+#define PCI_1SCS_3_BANK_SIZE				0xd8c
+#define PCI_0CS_0_BANK_SIZE				0xc10
+#define PCI_1CS_0_BANK_SIZE				0xc90
+#define PCI_0CS_1_BANK_SIZE				0xd10
+#define PCI_1CS_1_BANK_SIZE				0xd90
+#define PCI_0CS_2_BANK_SIZE				0xd18
+#define PCI_1CS_2_BANK_SIZE				0xd98
+#define PCI_0CS_3_BANK_SIZE				0xc14
+#define PCI_1CS_3_BANK_SIZE				0xc94
+#define PCI_0CS_BOOT_BANK_SIZE				0xd14
+#define PCI_1CS_BOOT_BANK_SIZE				0xd94
+#define PCI_0P2P_MEM0_BAR_SIZE				0xd1c
+#define PCI_1P2P_MEM0_BAR_SIZE				0xd9c
+#define PCI_0P2P_MEM1_BAR_SIZE				0xd20
+#define PCI_1P2P_MEM1_BAR_SIZE				0xda0
+#define PCI_0P2P_I_O_BAR_SIZE				0xd24
+#define PCI_1P2P_I_O_BAR_SIZE				0xda4
+#define PCI_0CPU_BAR_SIZE				0xd28
+#define PCI_1CPU_BAR_SIZE				0xda8
+#define PCI_0DAC_SCS_0_BANK_SIZE			0xe00
+#define PCI_1DAC_SCS_0_BANK_SIZE			0xe80
+#define PCI_0DAC_SCS_1_BANK_SIZE			0xe04
+#define PCI_1DAC_SCS_1_BANK_SIZE			0xe84
+#define PCI_0DAC_SCS_2_BANK_SIZE			0xe08
+#define PCI_1DAC_SCS_2_BANK_SIZE			0xe88
+#define PCI_0DAC_SCS_3_BANK_SIZE			0xe0c
+#define PCI_1DAC_SCS_3_BANK_SIZE			0xe8c
+#define PCI_0DAC_CS_0_BANK_SIZE				0xe10
+#define PCI_1DAC_CS_0_BANK_SIZE				0xe90
+#define PCI_0DAC_CS_1_BANK_SIZE				0xe14
+#define PCI_1DAC_CS_1_BANK_SIZE				0xe94
+#define PCI_0DAC_CS_2_BANK_SIZE				0xe18
+#define PCI_1DAC_CS_2_BANK_SIZE				0xe98
+#define PCI_0DAC_CS_3_BANK_SIZE				0xe1c
+#define PCI_1DAC_CS_3_BANK_SIZE				0xe9c
+#define PCI_0DAC_BOOTCS_BANK_SIZE			0xe20
+#define PCI_1DAC_BOOTCS_BANK_SIZE			0xea0
+#define PCI_0DAC_P2P_MEM0_BAR_SIZE			0xe24
+#define PCI_1DAC_P2P_MEM0_BAR_SIZE			0xea4
+#define PCI_0DAC_P2P_MEM1_BAR_SIZE			0xe28
+#define PCI_1DAC_P2P_MEM1_BAR_SIZE			0xea8
+#define PCI_0DAC_CPU_BAR_SIZE				0xe2c
+#define PCI_1DAC_CPU_BAR_SIZE				0xeac
+#define PCI_0EXPANSION_ROM_BAR_SIZE			0xd2c
+#define PCI_1EXPANSION_ROM_BAR_SIZE			0xdac
+#define PCI_0BASE_ADDRESS_REGISTERS_ENABLE		0xc3c
+#define PCI_1BASE_ADDRESS_REGISTERS_ENABLE		0xcbc
+#define PCI_0SCS_0_BASE_ADDRESS_REMAP			0xc48
+#define PCI_1SCS_0_BASE_ADDRESS_REMAP			0xcc8
+#define PCI_0SCS_1_BASE_ADDRESS_REMAP			0xd48
+#define PCI_1SCS_1_BASE_ADDRESS_REMAP			0xdc8
+#define PCI_0SCS_2_BASE_ADDRESS_REMAP			0xc4c
+#define PCI_1SCS_2_BASE_ADDRESS_REMAP			0xccc
+#define PCI_0SCS_3_BASE_ADDRESS_REMAP			0xd4c
+#define PCI_1SCS_3_BASE_ADDRESS_REMAP			0xdcc
+#define PCI_0CS_0_BASE_ADDRESS_REMAP			0xc50
+#define PCI_1CS_0_BASE_ADDRESS_REMAP			0xcd0
+#define PCI_0CS_1_BASE_ADDRESS_REMAP			0xd50
+#define PCI_1CS_1_BASE_ADDRESS_REMAP			0xdd0
+#define PCI_0CS_2_BASE_ADDRESS_REMAP			0xd58
+#define PCI_1CS_2_BASE_ADDRESS_REMAP			0xdd8
+#define PCI_0CS_3_BASE_ADDRESS_REMAP			0xc54
+#define PCI_1CS_3_BASE_ADDRESS_REMAP			0xcd4
+#define PCI_0CS_BOOTCS_BASE_ADDRESS_REMAP		0xd54
+#define PCI_1CS_BOOTCS_BASE_ADDRESS_REMAP		0xdd4
+#define PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_LOW		0xd5c
+#define PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_LOW		0xddc
+#define PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_HIGH		0xd60
+#define PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_HIGH		0xde0
+#define PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_LOW		0xd64
+#define PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_LOW		0xde4
+#define PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_HIGH		0xd68
+#define PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_HIGH		0xde8
+#define PCI_0P2P_I_O_BASE_ADDRESS_REMAP			0xd6c
+#define PCI_1P2P_I_O_BASE_ADDRESS_REMAP			0xdec
+#define PCI_0CPU_BASE_ADDRESS_REMAP			0xd70
+#define PCI_1CPU_BASE_ADDRESS_REMAP			0xdf0
+#define PCI_0DAC_SCS_0_BASE_ADDRESS_REMAP		0xf00
+#define PCI_1DAC_SCS_0_BASE_ADDRESS_REMAP		0xff0
+#define PCI_0DAC_SCS_1_BASE_ADDRESS_REMAP		0xf04
+#define PCI_1DAC_SCS_1_BASE_ADDRESS_REMAP		0xf84
+#define PCI_0DAC_SCS_2_BASE_ADDRESS_REMAP		0xf08
+#define PCI_1DAC_SCS_2_BASE_ADDRESS_REMAP		0xf88
+#define PCI_0DAC_SCS_3_BASE_ADDRESS_REMAP		0xf0c
+#define PCI_1DAC_SCS_3_BASE_ADDRESS_REMAP		0xf8c
+#define PCI_0DAC_CS_0_BASE_ADDRESS_REMAP		0xf10
+#define PCI_1DAC_CS_0_BASE_ADDRESS_REMAP		0xf90
+#define PCI_0DAC_CS_1_BASE_ADDRESS_REMAP		0xf14
+#define PCI_1DAC_CS_1_BASE_ADDRESS_REMAP		0xf94
+#define PCI_0DAC_CS_2_BASE_ADDRESS_REMAP		0xf18
+#define PCI_1DAC_CS_2_BASE_ADDRESS_REMAP		0xf98
+#define PCI_0DAC_CS_3_BASE_ADDRESS_REMAP		0xf1c
+#define PCI_1DAC_CS_3_BASE_ADDRESS_REMAP		0xf9c
+#define PCI_0DAC_BOOTCS_BASE_ADDRESS_REMAP		0xf20
+#define PCI_1DAC_BOOTCS_BASE_ADDRESS_REMAP		0xfa0
+#define PCI_0DAC_P2P_MEM0_BASE_ADDRESS_REMAP_LOW	0xf24
+#define PCI_1DAC_P2P_MEM0_BASE_ADDRESS_REMAP_LOW	0xfa4
+#define PCI_0DAC_P2P_MEM0_BASE_ADDRESS_REMAP_HIGH	0xf28
+#define PCI_1DAC_P2P_MEM0_BASE_ADDRESS_REMAP_HIGH	0xfa8
+#define PCI_0DAC_P2P_MEM1_BASE_ADDRESS_REMAP_LOW	0xf2c
+#define PCI_1DAC_P2P_MEM1_BASE_ADDRESS_REMAP_LOW	0xfac
+#define PCI_0DAC_P2P_MEM1_BASE_ADDRESS_REMAP_HIGH	0xf30
+#define PCI_1DAC_P2P_MEM1_BASE_ADDRESS_REMAP_HIGH	0xfb0
+#define PCI_0DAC_CPU_BASE_ADDRESS_REMAP			0xf34
+#define PCI_1DAC_CPU_BASE_ADDRESS_REMAP			0xfb4
+#define PCI_0EXPANSION_ROM_BASE_ADDRESS_REMAP		0xf38
+#define PCI_1EXPANSION_ROM_BASE_ADDRESS_REMAP		0xfb8
+#define PCI_0ADDRESS_DECODE_CONTROL			0xd3c
+#define PCI_1ADDRESS_DECODE_CONTROL			0xdbc
+
+/****************************************/
+/* PCI Control				*/
+/****************************************/
+
+#define PCI_0COMMAND					0xc00
+#define PCI_1COMMAND					0xc80
+#define PCI_0MODE					0xd00
+#define PCI_1MODE					0xd80
+#define PCI_0TIMEOUT_RETRY				0xc04
+#define PCI_1TIMEOUT_RETRY				0xc84
+#define PCI_0READ_BUFFER_DISCARD_TIMER			0xd04
+#define PCI_1READ_BUFFER_DISCARD_TIMER			0xd84
+#define MSI_0TRIGGER_TIMER				0xc38
+#define MSI_1TRIGGER_TIMER				0xcb8
+#define PCI_0ARBITER_CONTROL				0x1d00
+#define PCI_1ARBITER_CONTROL				0x1d80
 /* changing untill here */
-#define PCI_0CROSS_BAR_CONTROL_LOW                           0x1d08
-#define PCI_0CROSS_BAR_CONTROL_HIGH                          0x1d0c
-#define PCI_0CROSS_BAR_TIMEOUT                               0x1d04
-#define PCI_0READ_RESPONSE_CROSS_BAR_CONTROL_LOW             0x1d18
-#define PCI_0READ_RESPONSE_CROSS_BAR_CONTROL_HIGH            0x1d1c
-#define PCI_0SYNC_BARRIER_VIRTUAL_REGISTER                   0x1d10
-#define PCI_0P2P_CONFIGURATION                               0x1d14
-#define PCI_0ACCESS_CONTROL_BASE_0_LOW                       0x1e00
-#define PCI_0ACCESS_CONTROL_BASE_0_HIGH                      0x1e04
-#define PCI_0ACCESS_CONTROL_TOP_0                            0x1e08
-#define PCI_0ACCESS_CONTROL_BASE_1_LOW                       0x1e10
-#define PCI_0ACCESS_CONTROL_BASE_1_HIGH                      0x1e14
-#define PCI_0ACCESS_CONTROL_TOP_1                            0x1e18
-#define PCI_0ACCESS_CONTROL_BASE_2_LOW                       0x1e20
-#define PCI_0ACCESS_CONTROL_BASE_2_HIGH                      0x1e24
-#define PCI_0ACCESS_CONTROL_TOP_2                            0x1e28
-#define PCI_0ACCESS_CONTROL_BASE_3_LOW                       0x1e30
-#define PCI_0ACCESS_CONTROL_BASE_3_HIGH                      0x1e34
-#define PCI_0ACCESS_CONTROL_TOP_3                            0x1e38
-#define PCI_0ACCESS_CONTROL_BASE_4_LOW                       0x1e40
-#define PCI_0ACCESS_CONTROL_BASE_4_HIGH                      0x1e44
-#define PCI_0ACCESS_CONTROL_TOP_4                            0x1e48
-#define PCI_0ACCESS_CONTROL_BASE_5_LOW                       0x1e50
-#define PCI_0ACCESS_CONTROL_BASE_5_HIGH                      0x1e54
-#define PCI_0ACCESS_CONTROL_TOP_5                            0x1e58
-#define PCI_0ACCESS_CONTROL_BASE_6_LOW                       0x1e60
-#define PCI_0ACCESS_CONTROL_BASE_6_HIGH                      0x1e64
-#define PCI_0ACCESS_CONTROL_TOP_6                            0x1e68
-#define PCI_0ACCESS_CONTROL_BASE_7_LOW                       0x1e70
-#define PCI_0ACCESS_CONTROL_BASE_7_HIGH                      0x1e74
-#define PCI_0ACCESS_CONTROL_TOP_7                            0x1e78
-#define PCI_1CROSS_BAR_CONTROL_LOW                           0x1d88
-#define PCI_1CROSS_BAR_CONTROL_HIGH                          0x1d8c
-#define PCI_1CROSS_BAR_TIMEOUT                               0x1d84
-#define PCI_1READ_RESPONSE_CROSS_BAR_CONTROL_LOW             0x1d98
-#define PCI_1READ_RESPONSE_CROSS_BAR_CONTROL_HIGH            0x1d9c
-#define PCI_1SYNC_BARRIER_VIRTUAL_REGISTER                   0x1d90
-#define PCI_1P2P_CONFIGURATION                               0x1d94
-#define PCI_1ACCESS_CONTROL_BASE_0_LOW                       0x1e80
-#define PCI_1ACCESS_CONTROL_BASE_0_HIGH                      0x1e84
-#define PCI_1ACCESS_CONTROL_TOP_0                            0x1e88
-#define PCI_1ACCESS_CONTROL_BASE_1_LOW                       0x1e90
-#define PCI_1ACCESS_CONTROL_BASE_1_HIGH                      0x1e94
-#define PCI_1ACCESS_CONTROL_TOP_1                            0x1e98
-#define PCI_1ACCESS_CONTROL_BASE_2_LOW                       0x1ea0
-#define PCI_1ACCESS_CONTROL_BASE_2_HIGH                      0x1ea4
-#define PCI_1ACCESS_CONTROL_TOP_2                            0x1ea8
-#define PCI_1ACCESS_CONTROL_BASE_3_LOW                       0x1eb0
-#define PCI_1ACCESS_CONTROL_BASE_3_HIGH                      0x1eb4
-#define PCI_1ACCESS_CONTROL_TOP_3                            0x1eb8
-#define PCI_1ACCESS_CONTROL_BASE_4_LOW                       0x1ec0
-#define PCI_1ACCESS_CONTROL_BASE_4_HIGH                      0x1ec4
-#define PCI_1ACCESS_CONTROL_TOP_4                            0x1ec8
-#define PCI_1ACCESS_CONTROL_BASE_5_LOW                       0x1ed0
-#define PCI_1ACCESS_CONTROL_BASE_5_HIGH                      0x1ed4
-#define PCI_1ACCESS_CONTROL_TOP_5                            0x1ed8
-#define PCI_1ACCESS_CONTROL_BASE_6_LOW                       0x1ee0
-#define PCI_1ACCESS_CONTROL_BASE_6_HIGH                      0x1ee4
-#define PCI_1ACCESS_CONTROL_TOP_6                            0x1ee8
-#define PCI_1ACCESS_CONTROL_BASE_7_LOW                       0x1ef0
-#define PCI_1ACCESS_CONTROL_BASE_7_HIGH                      0x1ef4
-#define PCI_1ACCESS_CONTROL_TOP_7                            0x1ef8
-
-/****************************************/
-/* PCI Snoop Control                    */
-/****************************************/
-
-#define PCI_0SNOOP_CONTROL_BASE_0_LOW                        0x1f00
-#define PCI_0SNOOP_CONTROL_BASE_0_HIGH                       0x1f04
-#define PCI_0SNOOP_CONTROL_TOP_0                             0x1f08
-#define PCI_0SNOOP_CONTROL_BASE_1_0_LOW                      0x1f10
-#define PCI_0SNOOP_CONTROL_BASE_1_0_HIGH                     0x1f14
-#define PCI_0SNOOP_CONTROL_TOP_1                             0x1f18
-#define PCI_0SNOOP_CONTROL_BASE_2_0_LOW                      0x1f20
-#define PCI_0SNOOP_CONTROL_BASE_2_0_HIGH                     0x1f24
-#define PCI_0SNOOP_CONTROL_TOP_2                             0x1f28
-#define PCI_0SNOOP_CONTROL_BASE_3_0_LOW                      0x1f30
-#define PCI_0SNOOP_CONTROL_BASE_3_0_HIGH                     0x1f34
-#define PCI_0SNOOP_CONTROL_TOP_3                             0x1f38
-#define PCI_1SNOOP_CONTROL_BASE_0_LOW                        0x1f80
-#define PCI_1SNOOP_CONTROL_BASE_0_HIGH                       0x1f84
-#define PCI_1SNOOP_CONTROL_TOP_0                             0x1f88
-#define PCI_1SNOOP_CONTROL_BASE_1_0_LOW                      0x1f90
-#define PCI_1SNOOP_CONTROL_BASE_1_0_HIGH                     0x1f94
-#define PCI_1SNOOP_CONTROL_TOP_1                             0x1f98
-#define PCI_1SNOOP_CONTROL_BASE_2_0_LOW                      0x1fa0
-#define PCI_1SNOOP_CONTROL_BASE_2_0_HIGH                     0x1fa4
-#define PCI_1SNOOP_CONTROL_TOP_2                             0x1fa8
-#define PCI_1SNOOP_CONTROL_BASE_3_0_LOW                      0x1fb0
-#define PCI_1SNOOP_CONTROL_BASE_3_0_HIGH                     0x1fb4
-#define PCI_1SNOOP_CONTROL_TOP_3                             0x1fb8
-
-/****************************************/
-/* PCI Configuration Address            */
-/****************************************/
-
-#define PCI_0CONFIGURATION_ADDRESS 							0xcf8
-#define PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER           	0xcfc
-#define PCI_1CONFIGURATION_ADDRESS 							0xc78
-#define PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER           	0xc7c
-#define PCI_0INTERRUPT_ACKNOWLEDGE_VIRTUAL_REGISTER			0xc34
-#define PCI_1INTERRUPT_ACKNOWLEDGE_VIRTUAL_REGISTER			0xcb4
-
-/****************************************/
-/* PCI Error Report                     */
+#define PCI_0CROSS_BAR_CONTROL_LOW			0x1d08
+#define PCI_0CROSS_BAR_CONTROL_HIGH			0x1d0c
+#define PCI_0CROSS_BAR_TIMEOUT				0x1d04
+#define PCI_0READ_RESPONSE_CROSS_BAR_CONTROL_LOW	0x1d18
+#define PCI_0READ_RESPONSE_CROSS_BAR_CONTROL_HIGH	0x1d1c
+#define PCI_0SYNC_BARRIER_VIRTUAL_REGISTER		0x1d10
+#define PCI_0P2P_CONFIGURATION				0x1d14
+#define PCI_0ACCESS_CONTROL_BASE_0_LOW			0x1e00
+#define PCI_0ACCESS_CONTROL_BASE_0_HIGH			0x1e04
+#define PCI_0ACCESS_CONTROL_TOP_0			0x1e08
+#define PCI_0ACCESS_CONTROL_BASE_1_LOW			0x1e10
+#define PCI_0ACCESS_CONTROL_BASE_1_HIGH			0x1e14
+#define PCI_0ACCESS_CONTROL_TOP_1			0x1e18
+#define PCI_0ACCESS_CONTROL_BASE_2_LOW			0x1e20
+#define PCI_0ACCESS_CONTROL_BASE_2_HIGH			0x1e24
+#define PCI_0ACCESS_CONTROL_TOP_2			0x1e28
+#define PCI_0ACCESS_CONTROL_BASE_3_LOW			0x1e30
+#define PCI_0ACCESS_CONTROL_BASE_3_HIGH			0x1e34
+#define PCI_0ACCESS_CONTROL_TOP_3			0x1e38
+#define PCI_0ACCESS_CONTROL_BASE_4_LOW			0x1e40
+#define PCI_0ACCESS_CONTROL_BASE_4_HIGH			0x1e44
+#define PCI_0ACCESS_CONTROL_TOP_4			0x1e48
+#define PCI_0ACCESS_CONTROL_BASE_5_LOW			0x1e50
+#define PCI_0ACCESS_CONTROL_BASE_5_HIGH			0x1e54
+#define PCI_0ACCESS_CONTROL_TOP_5			0x1e58
+#define PCI_0ACCESS_CONTROL_BASE_6_LOW			0x1e60
+#define PCI_0ACCESS_CONTROL_BASE_6_HIGH			0x1e64
+#define PCI_0ACCESS_CONTROL_TOP_6			0x1e68
+#define PCI_0ACCESS_CONTROL_BASE_7_LOW			0x1e70
+#define PCI_0ACCESS_CONTROL_BASE_7_HIGH			0x1e74
+#define PCI_0ACCESS_CONTROL_TOP_7			0x1e78
+#define PCI_1CROSS_BAR_CONTROL_LOW			0x1d88
+#define PCI_1CROSS_BAR_CONTROL_HIGH			0x1d8c
+#define PCI_1CROSS_BAR_TIMEOUT				0x1d84
+#define PCI_1READ_RESPONSE_CROSS_BAR_CONTROL_LOW	0x1d98
+#define PCI_1READ_RESPONSE_CROSS_BAR_CONTROL_HIGH	0x1d9c
+#define PCI_1SYNC_BARRIER_VIRTUAL_REGISTER		0x1d90
+#define PCI_1P2P_CONFIGURATION				0x1d94
+#define PCI_1ACCESS_CONTROL_BASE_0_LOW			0x1e80
+#define PCI_1ACCESS_CONTROL_BASE_0_HIGH			0x1e84
+#define PCI_1ACCESS_CONTROL_TOP_0			0x1e88
+#define PCI_1ACCESS_CONTROL_BASE_1_LOW			0x1e90
+#define PCI_1ACCESS_CONTROL_BASE_1_HIGH			0x1e94
+#define PCI_1ACCESS_CONTROL_TOP_1			0x1e98
+#define PCI_1ACCESS_CONTROL_BASE_2_LOW			0x1ea0
+#define PCI_1ACCESS_CONTROL_BASE_2_HIGH			0x1ea4
+#define PCI_1ACCESS_CONTROL_TOP_2			0x1ea8
+#define PCI_1ACCESS_CONTROL_BASE_3_LOW			0x1eb0
+#define PCI_1ACCESS_CONTROL_BASE_3_HIGH			0x1eb4
+#define PCI_1ACCESS_CONTROL_TOP_3			0x1eb8
+#define PCI_1ACCESS_CONTROL_BASE_4_LOW			0x1ec0
+#define PCI_1ACCESS_CONTROL_BASE_4_HIGH			0x1ec4
+#define PCI_1ACCESS_CONTROL_TOP_4			0x1ec8
+#define PCI_1ACCESS_CONTROL_BASE_5_LOW			0x1ed0
+#define PCI_1ACCESS_CONTROL_BASE_5_HIGH			0x1ed4
+#define PCI_1ACCESS_CONTROL_TOP_5			0x1ed8
+#define PCI_1ACCESS_CONTROL_BASE_6_LOW			0x1ee0
+#define PCI_1ACCESS_CONTROL_BASE_6_HIGH			0x1ee4
+#define PCI_1ACCESS_CONTROL_TOP_6			0x1ee8
+#define PCI_1ACCESS_CONTROL_BASE_7_LOW			0x1ef0
+#define PCI_1ACCESS_CONTROL_BASE_7_HIGH			0x1ef4
+#define PCI_1ACCESS_CONTROL_TOP_7			0x1ef8
+
+/****************************************/
+/* PCI Snoop Control			*/
+/****************************************/
+
+#define PCI_0SNOOP_CONTROL_BASE_0_LOW			0x1f00
+#define PCI_0SNOOP_CONTROL_BASE_0_HIGH			0x1f04
+#define PCI_0SNOOP_CONTROL_TOP_0			0x1f08
+#define PCI_0SNOOP_CONTROL_BASE_1_0_LOW			0x1f10
+#define PCI_0SNOOP_CONTROL_BASE_1_0_HIGH		0x1f14
+#define PCI_0SNOOP_CONTROL_TOP_1			0x1f18
+#define PCI_0SNOOP_CONTROL_BASE_2_0_LOW			0x1f20
+#define PCI_0SNOOP_CONTROL_BASE_2_0_HIGH		0x1f24
+#define PCI_0SNOOP_CONTROL_TOP_2			0x1f28
+#define PCI_0SNOOP_CONTROL_BASE_3_0_LOW			0x1f30
+#define PCI_0SNOOP_CONTROL_BASE_3_0_HIGH		0x1f34
+#define PCI_0SNOOP_CONTROL_TOP_3			0x1f38
+#define PCI_1SNOOP_CONTROL_BASE_0_LOW			0x1f80
+#define PCI_1SNOOP_CONTROL_BASE_0_HIGH			0x1f84
+#define PCI_1SNOOP_CONTROL_TOP_0			0x1f88
+#define PCI_1SNOOP_CONTROL_BASE_1_0_LOW			0x1f90
+#define PCI_1SNOOP_CONTROL_BASE_1_0_HIGH		0x1f94
+#define PCI_1SNOOP_CONTROL_TOP_1			0x1f98
+#define PCI_1SNOOP_CONTROL_BASE_2_0_LOW			0x1fa0
+#define PCI_1SNOOP_CONTROL_BASE_2_0_HIGH		0x1fa4
+#define PCI_1SNOOP_CONTROL_TOP_2			0x1fa8
+#define PCI_1SNOOP_CONTROL_BASE_3_0_LOW			0x1fb0
+#define PCI_1SNOOP_CONTROL_BASE_3_0_HIGH		0x1fb4
+#define PCI_1SNOOP_CONTROL_TOP_3			0x1fb8
+
+/****************************************/
+/* PCI Configuration Address		*/
+/****************************************/
+
+#define PCI_0CONFIGURATION_ADDRESS			0xcf8
+#define PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER	0xcfc
+#define PCI_1CONFIGURATION_ADDRESS			0xc78
+#define PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER	0xc7c
+#define PCI_0INTERRUPT_ACKNOWLEDGE_VIRTUAL_REGISTER	0xc34
+#define PCI_1INTERRUPT_ACKNOWLEDGE_VIRTUAL_REGISTER	0xcb4
+
+/****************************************/
+/* PCI Error Report			*/
 /****************************************/
 
 #define PCI_0SERR_MASK										 0xc28
-#define PCI_0ERROR_ADDRESS_LOW                               0x1d40
-#define PCI_0ERROR_ADDRESS_HIGH                              0x1d44
-#define PCI_0ERROR_DATA_LOW                                  0x1d48
-#define PCI_0ERROR_DATA_HIGH                                 0x1d4c
-#define PCI_0ERROR_COMMAND                                   0x1d50
-#define PCI_0ERROR_CAUSE                                     0x1d58
-#define PCI_0ERROR_MASK                                      0x1d5c
+#define PCI_0ERROR_ADDRESS_LOW				0x1d40
+#define PCI_0ERROR_ADDRESS_HIGH				0x1d44
+#define PCI_0ERROR_DATA_LOW				0x1d48
+#define PCI_0ERROR_DATA_HIGH				0x1d4c
+#define PCI_0ERROR_COMMAND				0x1d50
+#define PCI_0ERROR_CAUSE				0x1d58
+#define PCI_0ERROR_MASK					0x1d5c
 #define PCI_1SERR_MASK										 0xca8
-#define PCI_1ERROR_ADDRESS_LOW                               0x1dc0
-#define PCI_1ERROR_ADDRESS_HIGH                              0x1dc4
-#define PCI_1ERROR_DATA_LOW                                  0x1dc8
-#define PCI_1ERROR_DATA_HIGH                                 0x1dcc
-#define PCI_1ERROR_COMMAND                                   0x1dd0
-#define PCI_1ERROR_CAUSE                                     0x1dd8
-#define PCI_1ERROR_MASK                                      0x1ddc
+#define PCI_1ERROR_ADDRESS_LOW				0x1dc0
+#define PCI_1ERROR_ADDRESS_HIGH				0x1dc4
+#define PCI_1ERROR_DATA_LOW				0x1dc8
+#define PCI_1ERROR_DATA_HIGH				0x1dcc
+#define PCI_1ERROR_COMMAND				0x1dd0
+#define PCI_1ERROR_CAUSE				0x1dd8
+#define PCI_1ERROR_MASK					0x1ddc
 
 
 /****************************************/
-/* Lslave Debug  (for internal use)     */
+/* Lslave Debug  (for internal use)	*/
 /****************************************/
 
-#define L_SLAVE_X0_ADDRESS                                  0x1d20
-#define L_SLAVE_X0_COMMAND_AND_ID                           0x1d24
-#define L_SLAVE_X1_ADDRESS                                  0x1d28
-#define L_SLAVE_X1_COMMAND_AND_ID                           0x1d2c
-#define L_SLAVE_WRITE_DATA_LOW                              0x1d30
-#define L_SLAVE_WRITE_DATA_HIGH                             0x1d34
-#define L_SLAVE_WRITE_BYTE_ENABLE                           0x1d60
-#define L_SLAVE_READ_DATA_LOW                               0x1d38
-#define L_SLAVE_READ_DATA_HIGH                              0x1d3c
-#define L_SLAVE_READ_ID                                     0x1d64
+#define L_SLAVE_X0_ADDRESS				0x1d20
+#define L_SLAVE_X0_COMMAND_AND_ID			0x1d24
+#define L_SLAVE_X1_ADDRESS				0x1d28
+#define L_SLAVE_X1_COMMAND_AND_ID			0x1d2c
+#define L_SLAVE_WRITE_DATA_LOW				0x1d30
+#define L_SLAVE_WRITE_DATA_HIGH				0x1d34
+#define L_SLAVE_WRITE_BYTE_ENABLE			0x1d60
+#define L_SLAVE_READ_DATA_LOW				0x1d38
+#define L_SLAVE_READ_DATA_HIGH				0x1d3c
+#define L_SLAVE_READ_ID					0x1d64
 
 /****************************************/
-/* PCI Configuration Function 0         */
+/* PCI Configuration Function 0		*/
 /****************************************/
 
-#define PCI_DEVICE_AND_VENDOR_ID 							0x000
-#define PCI_STATUS_AND_COMMAND								0x004
-#define PCI_CLASS_CODE_AND_REVISION_ID				        0x008
-#define PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE 		0x00C
-#define PCI_SCS_0_BASE_ADDRESS	    						0x010
-#define PCI_SCS_1_BASE_ADDRESS 							    0x014
-#define PCI_SCS_2_BASE_ADDRESS 							    0x018
-#define PCI_SCS_3_BASE_ADDRESS      						0x01C
-#define PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS	0x020
-#define PCI_INTERNAL_REGISTERS_I_OMAPPED_BASE_ADDRESS		0x024
-#define PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID			0x02C
-#define PCI_EXPANSION_ROM_BASE_ADDRESS_REGISTER				0x030
-#define PCI_CAPABILTY_LIST_POINTER                          0x034
-#define PCI_INTERRUPT_PIN_AND_LINE 						    0x03C
-#define PCI_POWER_MANAGEMENT_CAPABILITY                     0x040
-#define PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL             0x044
-#define PCI_VPD_ADDRESS                                     0x048
-#define PCI_VPD_DATA                                        0x04c
-#define PCI_MSI_MESSAGE_CONTROL                             0x050
-#define PCI_MSI_MESSAGE_ADDRESS                             0x054
-#define PCI_MSI_MESSAGE_UPPER_ADDRESS                       0x058
-#define PCI_MSI_MESSAGE_DATA                                0x05c
-#define PCI_COMPACT_PCI_HOT_SWAP_CAPABILITY                 0x058
+#define PCI_DEVICE_AND_VENDOR_ID			0x000
+#define PCI_STATUS_AND_COMMAND				0x004
+#define PCI_CLASS_CODE_AND_REVISION_ID			0x008
+#define PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE	0x00C
+#define PCI_SCS_0_BASE_ADDRESS				0x010
+#define PCI_SCS_1_BASE_ADDRESS				0x014
+#define PCI_SCS_2_BASE_ADDRESS				0x018
+#define PCI_SCS_3_BASE_ADDRESS				0x01C
+#define PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS  0x020
+#define PCI_INTERNAL_REGISTERS_I_OMAPPED_BASE_ADDRESS	0x024
+#define PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID	0x02C
+#define PCI_EXPANSION_ROM_BASE_ADDRESS_REGISTER		0x030
+#define PCI_CAPABILTY_LIST_POINTER			0x034
+#define PCI_INTERRUPT_PIN_AND_LINE			0x03C
+#define PCI_POWER_MANAGEMENT_CAPABILITY			0x040
+#define PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL		0x044
+#define PCI_VPD_ADDRESS					0x048
+#define PCI_VPD_DATA					0x04c
+#define PCI_MSI_MESSAGE_CONTROL				0x050
+#define PCI_MSI_MESSAGE_ADDRESS				0x054
+#define PCI_MSI_MESSAGE_UPPER_ADDRESS			0x058
+#define PCI_MSI_MESSAGE_DATA				0x05c
+#define PCI_COMPACT_PCI_HOT_SWAP_CAPABILITY		0x058
 
 /****************************************/
-/* PCI Configuration Function 1         */
+/* PCI Configuration Function 1		*/
 /****************************************/
 
-#define PCI_CS_0_BASE_ADDRESS	    						0x110
-#define PCI_CS_1_BASE_ADDRESS 							    0x114
-#define PCI_CS_2_BASE_ADDRESS 							    0x118
-#define PCI_CS_3_BASE_ADDRESS     					        0x11c
-#define PCI_BOOTCS_BASE_ADDRESS                     	    0x120
+#define PCI_CS_0_BASE_ADDRESS				0x110
+#define PCI_CS_1_BASE_ADDRESS				0x114
+#define PCI_CS_2_BASE_ADDRESS				0x118
+#define PCI_CS_3_BASE_ADDRESS				0x11c
+#define PCI_BOOTCS_BASE_ADDRESS				0x120
 
 /****************************************/
-/* PCI Configuration Function 2         */
+/* PCI Configuration Function 2		*/
 /****************************************/
 
-#define PCI_P2P_MEM0_BASE_ADDRESS	    					0x210
-#define PCI_P2P_MEM1_BASE_ADDRESS 							0x214
-#define PCI_P2P_I_O_BASE_ADDRESS 							0x218
-#define PCI_CPU_BASE_ADDRESS      						    0x21c
+#define PCI_P2P_MEM0_BASE_ADDRESS			0x210
+#define PCI_P2P_MEM1_BASE_ADDRESS			0x214
+#define PCI_P2P_I_O_BASE_ADDRESS			0x218
+#define PCI_CPU_BASE_ADDRESS				0x21c
 
 /****************************************/
-/* PCI Configuration Function 4         */
+/* PCI Configuration Function 4		*/
 /****************************************/
 
-#define PCI_DAC_SCS_0_BASE_ADDRESS_LOW 						0x410
-#define PCI_DAC_SCS_0_BASE_ADDRESS_HIGH					    0x414
-#define PCI_DAC_SCS_1_BASE_ADDRESS_LOW   				    0x418
-#define PCI_DAC_SCS_1_BASE_ADDRESS_HIGH  				    0x41c
-#define PCI_DAC_P2P_MEM0_BASE_ADDRESS_LOW              	    0x420
-#define PCI_DAC_P2P_MEM0_BASE_ADDRESS_HIGH             	    0x424
-
-
-/****************************************/
-/* PCI Configuration Function 5         */
-/****************************************/
-
-#define PCI_DAC_SCS_2_BASE_ADDRESS_LOW 						0x510
-#define PCI_DAC_SCS_2_BASE_ADDRESS_HIGH					    0x514
-#define PCI_DAC_SCS_3_BASE_ADDRESS_LOW   				    0x518
-#define PCI_DAC_SCS_3_BASE_ADDRESS_HIGH  				    0x51c
-#define PCI_DAC_P2P_MEM1_BASE_ADDRESS_LOW              	    0x520
-#define PCI_DAC_P2P_MEM1_BASE_ADDRESS_HIGH             	    0x524
+#define PCI_DAC_SCS_0_BASE_ADDRESS_LOW			0x410
+#define PCI_DAC_SCS_0_BASE_ADDRESS_HIGH			0x414
+#define PCI_DAC_SCS_1_BASE_ADDRESS_LOW			0x418
+#define PCI_DAC_SCS_1_BASE_ADDRESS_HIGH			0x41c
+#define PCI_DAC_P2P_MEM0_BASE_ADDRESS_LOW		0x420
+#define PCI_DAC_P2P_MEM0_BASE_ADDRESS_HIGH		0x424
+
+
+/****************************************/
+/* PCI Configuration Function 5		*/
+/****************************************/
+
+#define PCI_DAC_SCS_2_BASE_ADDRESS_LOW			0x510
+#define PCI_DAC_SCS_2_BASE_ADDRESS_HIGH			0x514
+#define PCI_DAC_SCS_3_BASE_ADDRESS_LOW			0x518
+#define PCI_DAC_SCS_3_BASE_ADDRESS_HIGH			0x51c
+#define PCI_DAC_P2P_MEM1_BASE_ADDRESS_LOW		0x520
+#define PCI_DAC_P2P_MEM1_BASE_ADDRESS_HIGH		0x524
 
 
-/****************************************/
-/* PCI Configuration Function 6         */
-/****************************************/
-
-#define PCI_DAC_CS_0_BASE_ADDRESS_LOW 						0x610
-#define PCI_DAC_CS_0_BASE_ADDRESS_HIGH					    0x614
-#define PCI_DAC_CS_1_BASE_ADDRESS_LOW   				    0x618
-#define PCI_DAC_CS_1_BASE_ADDRESS_HIGH  				    0x61c
-#define PCI_DAC_CS_2_BASE_ADDRESS_LOW            	        0x620
-#define PCI_DAC_CS_2_BASE_ADDRESS_HIGH           	        0x624
-
-/****************************************/
-/* PCI Configuration Function 7         */
-/****************************************/
-
-#define PCI_DAC_CS_3_BASE_ADDRESS_LOW 						0x710
-#define PCI_DAC_CS_3_BASE_ADDRESS_HIGH					    0x714
-#define PCI_DAC_BOOTCS_BASE_ADDRESS_LOW   				    0x718
-#define PCI_DAC_BOOTCS_BASE_ADDRESS_HIGH  				    0x71c
-#define PCI_DAC_CPU_BASE_ADDRESS_LOW            	        0x720
-#define PCI_DAC_CPU_BASE_ADDRESS_HIGH           	        0x724
-
-/****************************************/
-/* Interrupts 				*/
-/****************************************/
-
-#define LOW_INTERRUPT_CAUSE_REGISTER   						0xc18
-#define HIGH_INTERRUPT_CAUSE_REGISTER						0xc68
-#define CPU_INTERRUPT_MASK_REGISTER_LOW						0xc1c
-#define CPU_INTERRUPT_MASK_REGISTER_HIGH					0xc6c
-#define CPU_SELECT_CAUSE_REGISTER							0xc70
-#define PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW				0xc24
-#define PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH				0xc64
-#define PCI_0SELECT_CAUSE                                   0xc74
-#define PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW				0xca4
-#define PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH				0xce4
-#define PCI_1SELECT_CAUSE                                   0xcf4
-#define CPU_INT_0_MASK                                      0xe60
-#define CPU_INT_1_MASK                                      0xe64
-#define CPU_INT_2_MASK                                      0xe68
-#define CPU_INT_3_MASK                                      0xe6c
-
-/****************************************/
-/* I20 Support registers				*/
-/****************************************/
-
-#define INBOUND_MESSAGE_REGISTER0_PCI_SIDE					0x010
-#define INBOUND_MESSAGE_REGISTER1_PCI_SIDE  				0x014
-#define OUTBOUND_MESSAGE_REGISTER0_PCI_SIDE 				0x018
-#define OUTBOUND_MESSAGE_REGISTER1_PCI_SIDE  				0x01C
-#define INBOUND_DOORBELL_REGISTER_PCI_SIDE  				0x020
-#define INBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE  			0x024
-#define INBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE			0x028
-#define OUTBOUND_DOORBELL_REGISTER_PCI_SIDE 				0x02C
-#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE   		0x030
-#define OUTBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE   		0x034
-#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE  		0x040
-#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE   	0x044
-#define QUEUE_CONTROL_REGISTER_PCI_SIDE 					0x050
-#define QUEUE_BASE_ADDRESS_REGISTER_PCI_SIDE 				0x054
-#define INBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE			0x060
-#define INBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE  		0x064
-#define INBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE 		0x068
-#define INBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE 		0x06C
-#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE		0x070
-#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE		0x074
-#define OUTBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE		0x078
-#define OUTBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE		0x07C
-
-#define INBOUND_MESSAGE_REGISTER0_CPU_SIDE					0x1C10
-#define INBOUND_MESSAGE_REGISTER1_CPU_SIDE  				0x1C14
-#define OUTBOUND_MESSAGE_REGISTER0_CPU_SIDE 				0x1C18
-#define OUTBOUND_MESSAGE_REGISTER1_CPU_SIDE  				0x1C1C
-#define INBOUND_DOORBELL_REGISTER_CPU_SIDE  				0x1C20
-#define INBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE  			0x1C24
-#define INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE			0x1C28
-#define OUTBOUND_DOORBELL_REGISTER_CPU_SIDE 				0x1C2C
-#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE   		0x1C30
-#define OUTBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE   		0x1C34
-#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE  		0x1C40
-#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE   	0x1C44
-#define QUEUE_CONTROL_REGISTER_CPU_SIDE 					0x1C50
-#define QUEUE_BASE_ADDRESS_REGISTER_CPU_SIDE 				0x1C54
-#define INBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE			0x1C60
-#define INBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE  		0x1C64
-#define INBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE 		0x1C68
-#define INBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE 		0x1C6C
-#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE		0x1C70
-#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE		0x1C74
-#define OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE		0x1C78
-#define OUTBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE		0x1C7C
-
-/****************************************/
-/* Communication Unit Registers         */
-/****************************************/
-
-#define ETHERNET_0_ADDRESS_CONTROL_LOW						0xf200
-#define ETHERNET_0_ADDRESS_CONTROL_HIGH                     0xf204
-#define ETHERNET_0_RECEIVE_BUFFER_PCI_HIGH_ADDRESS          0xf208
-#define ETHERNET_0_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS         0xf20c
-#define ETHERNET_0_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS      0xf210
-#define ETHERNET_0_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS     0xf214
-#define ETHERNET_0_HASH_TABLE_PCI_HIGH_ADDRESS              0xf218
-#define ETHERNET_1_ADDRESS_CONTROL_LOW                      0xf220
-#define ETHERNET_1_ADDRESS_CONTROL_HIGH                     0xf224
-#define ETHERNET_1_RECEIVE_BUFFER_PCI_HIGH_ADDRESS          0xf228
-#define ETHERNET_1_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS         0xf22c
-#define ETHERNET_1_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS      0xf230
-#define ETHERNET_1_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS     0xf234
-#define ETHERNET_1_HASH_TABLE_PCI_HIGH_ADDRESS              0xf238
-#define ETHERNET_2_ADDRESS_CONTROL_LOW                      0xf240
-#define ETHERNET_2_ADDRESS_CONTROL_HIGH                     0xf244
-#define ETHERNET_2_RECEIVE_BUFFER_PCI_HIGH_ADDRESS          0xf248
-#define ETHERNET_2_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS         0xf24c
-#define ETHERNET_2_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS      0xf250
-#define ETHERNET_2_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS     0xf254
-#define ETHERNET_2_HASH_TABLE_PCI_HIGH_ADDRESS              0xf258
-#define MPSC_0_ADDRESS_CONTROL_LOW                          0xf280
-#define MPSC_0_ADDRESS_CONTROL_HIGH                         0xf284
-#define MPSC_0_RECEIVE_BUFFER_PCI_HIGH_ADDRESS              0xf288
-#define MPSC_0_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS             0xf28c
-#define MPSC_0_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS          0xf290
-#define MPSC_0_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS         0xf294
-#define MPSC_1_ADDRESS_CONTROL_LOW                          0xf2c0
-#define MPSC_1_ADDRESS_CONTROL_HIGH                         0xf2c4
-#define MPSC_1_RECEIVE_BUFFER_PCI_HIGH_ADDRESS              0xf2c8
-#define MPSC_1_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS             0xf2cc
-#define MPSC_1_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS          0xf2d0
-#define MPSC_1_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS         0xf2d4
-#define SERIAL_INIT_PCI_HIGH_ADDRESS                        0xf320
-#define SERIAL_INIT_LAST_DATA                               0xf324
-#define SERIAL_INIT_STATUS_AND_CONTROL                      0xf328
-#define COMM_UNIT_ARBITER_CONTROL                           0xf300
-#define COMM_UNIT_CROSS_BAR_TIMEOUT                         0xf304
-#define COMM_UNIT_INTERRUPT_CAUSE                           0xf310
-#define COMM_UNIT_INTERRUPT_MASK                            0xf314
-#define COMM_UNIT_ERROR_ADDRESS                             0xf314
-
-/****************************************/
-/* Cunit Debug  (for internal use)     */
-/****************************************/
-
-#define CUNIT_ADDRESS                                       0xf340
-#define CUNIT_COMMAND_AND_ID                                0xf344
-#define CUNIT_WRITE_DATA_LOW                                0xf348
-#define CUNIT_WRITE_DATA_HIGH                               0xf34c
-#define CUNIT_WRITE_BYTE_ENABLE                             0xf358
-#define CUNIT_READ_DATA_LOW                                 0xf350
-#define CUNIT_READ_DATA_HIGH                                0xf354
-#define CUNIT_READ_ID                                       0xf35c
-
-/****************************************/
-/* Fast Ethernet Unit Registers         */
+/****************************************/
+/* PCI Configuration Function 6		*/
+/****************************************/
+
+#define PCI_DAC_CS_0_BASE_ADDRESS_LOW			0x610
+#define PCI_DAC_CS_0_BASE_ADDRESS_HIGH			0x614
+#define PCI_DAC_CS_1_BASE_ADDRESS_LOW			0x618
+#define PCI_DAC_CS_1_BASE_ADDRESS_HIGH			0x61c
+#define PCI_DAC_CS_2_BASE_ADDRESS_LOW			0x620
+#define PCI_DAC_CS_2_BASE_ADDRESS_HIGH			0x624
+
+/****************************************/
+/* PCI Configuration Function 7		*/
+/****************************************/
+
+#define PCI_DAC_CS_3_BASE_ADDRESS_LOW			0x710
+#define PCI_DAC_CS_3_BASE_ADDRESS_HIGH			0x714
+#define PCI_DAC_BOOTCS_BASE_ADDRESS_LOW			0x718
+#define PCI_DAC_BOOTCS_BASE_ADDRESS_HIGH		0x71c
+#define PCI_DAC_CPU_BASE_ADDRESS_LOW			0x720
+#define PCI_DAC_CPU_BASE_ADDRESS_HIGH			0x724
+
+/****************************************/
+/* Interrupts				*/
+/****************************************/
+
+#define LOW_INTERRUPT_CAUSE_REGISTER			0xc18
+#define HIGH_INTERRUPT_CAUSE_REGISTER			0xc68
+#define CPU_INTERRUPT_MASK_REGISTER_LOW			0xc1c
+#define CPU_INTERRUPT_MASK_REGISTER_HIGH		0xc6c
+#define CPU_SELECT_CAUSE_REGISTER			0xc70
+#define PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW		0xc24
+#define PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH		0xc64
+#define PCI_0SELECT_CAUSE				0xc74
+#define PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW		0xca4
+#define PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH		0xce4
+#define PCI_1SELECT_CAUSE				0xcf4
+#define CPU_INT_0_MASK					0xe60
+#define CPU_INT_1_MASK					0xe64
+#define CPU_INT_2_MASK					0xe68
+#define CPU_INT_3_MASK					0xe6c
+
+/****************************************/
+/* I20 Support registers		*/
+/****************************************/
+
+#define INBOUND_MESSAGE_REGISTER0_PCI_SIDE		0x010
+#define INBOUND_MESSAGE_REGISTER1_PCI_SIDE		0x014
+#define OUTBOUND_MESSAGE_REGISTER0_PCI_SIDE		0x018
+#define OUTBOUND_MESSAGE_REGISTER1_PCI_SIDE		0x01C
+#define INBOUND_DOORBELL_REGISTER_PCI_SIDE		0x020
+#define INBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE	0x024
+#define INBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE	0x028
+#define OUTBOUND_DOORBELL_REGISTER_PCI_SIDE		0x02C
+#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE	0x030
+#define OUTBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE	0x034
+#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE	0x040
+#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE	0x044
+#define QUEUE_CONTROL_REGISTER_PCI_SIDE			0x050
+#define QUEUE_BASE_ADDRESS_REGISTER_PCI_SIDE		0x054
+#define INBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE	0x060
+#define INBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE	0x064
+#define INBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE	0x068
+#define INBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE	0x06C
+#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE	0x070
+#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE	0x074
+#define OUTBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE	0x078
+#define OUTBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE	0x07C
+
+#define INBOUND_MESSAGE_REGISTER0_CPU_SIDE		0x1C10
+#define INBOUND_MESSAGE_REGISTER1_CPU_SIDE		0x1C14
+#define OUTBOUND_MESSAGE_REGISTER0_CPU_SIDE		0x1C18
+#define OUTBOUND_MESSAGE_REGISTER1_CPU_SIDE		0x1C1C
+#define INBOUND_DOORBELL_REGISTER_CPU_SIDE		0x1C20
+#define INBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE	0x1C24
+#define INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE	0x1C28
+#define OUTBOUND_DOORBELL_REGISTER_CPU_SIDE		0x1C2C
+#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE	0x1C30
+#define OUTBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE	0x1C34
+#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE	0x1C40
+#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE	0x1C44
+#define QUEUE_CONTROL_REGISTER_CPU_SIDE			0x1C50
+#define QUEUE_BASE_ADDRESS_REGISTER_CPU_SIDE		0x1C54
+#define INBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE	0x1C60
+#define INBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE	0x1C64
+#define INBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE	0x1C68
+#define INBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE	0x1C6C
+#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE	0x1C70
+#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE	0x1C74
+#define OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE	0x1C78
+#define OUTBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE	0x1C7C
+
+/****************************************/
+/* Communication Unit Registers		*/
+/****************************************/
+
+#define ETHERNET_0_ADDRESS_CONTROL_LOW			0xf200
+#define ETHERNET_0_ADDRESS_CONTROL_HIGH			0xf204
+#define ETHERNET_0_RECEIVE_BUFFER_PCI_HIGH_ADDRESS	0xf208
+#define ETHERNET_0_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS	0xf20c
+#define ETHERNET_0_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS	0xf210
+#define ETHERNET_0_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf214
+#define ETHERNET_0_HASH_TABLE_PCI_HIGH_ADDRESS		0xf218
+#define ETHERNET_1_ADDRESS_CONTROL_LOW			0xf220
+#define ETHERNET_1_ADDRESS_CONTROL_HIGH			0xf224
+#define ETHERNET_1_RECEIVE_BUFFER_PCI_HIGH_ADDRESS	0xf228
+#define ETHERNET_1_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS	0xf22c
+#define ETHERNET_1_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS	0xf230
+#define ETHERNET_1_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf234
+#define ETHERNET_1_HASH_TABLE_PCI_HIGH_ADDRESS		0xf238
+#define ETHERNET_2_ADDRESS_CONTROL_LOW			0xf240
+#define ETHERNET_2_ADDRESS_CONTROL_HIGH			0xf244
+#define ETHERNET_2_RECEIVE_BUFFER_PCI_HIGH_ADDRESS	0xf248
+#define ETHERNET_2_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS	0xf24c
+#define ETHERNET_2_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS	0xf250
+#define ETHERNET_2_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf254
+#define ETHERNET_2_HASH_TABLE_PCI_HIGH_ADDRESS		0xf258
+#define MPSC_0_ADDRESS_CONTROL_LOW			0xf280
+#define MPSC_0_ADDRESS_CONTROL_HIGH			0xf284
+#define MPSC_0_RECEIVE_BUFFER_PCI_HIGH_ADDRESS		0xf288
+#define MPSC_0_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS		0xf28c
+#define MPSC_0_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS	0xf290
+#define MPSC_0_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS	0xf294
+#define MPSC_1_ADDRESS_CONTROL_LOW			0xf2c0
+#define MPSC_1_ADDRESS_CONTROL_HIGH			0xf2c4
+#define MPSC_1_RECEIVE_BUFFER_PCI_HIGH_ADDRESS		0xf2c8
+#define MPSC_1_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS		0xf2cc
+#define MPSC_1_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS	0xf2d0
+#define MPSC_1_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS	0xf2d4
+#define SERIAL_INIT_PCI_HIGH_ADDRESS			0xf320
+#define SERIAL_INIT_LAST_DATA				0xf324
+#define SERIAL_INIT_STATUS_AND_CONTROL			0xf328
+#define COMM_UNIT_ARBITER_CONTROL			0xf300
+#define COMM_UNIT_CROSS_BAR_TIMEOUT			0xf304
+#define COMM_UNIT_INTERRUPT_CAUSE			0xf310
+#define COMM_UNIT_INTERRUPT_MASK			0xf314
+#define COMM_UNIT_ERROR_ADDRESS				0xf314
+
+/****************************************/
+/* Cunit Debug	(for internal use)     */
+/****************************************/
+
+#define CUNIT_ADDRESS					0xf340
+#define CUNIT_COMMAND_AND_ID				0xf344
+#define CUNIT_WRITE_DATA_LOW				0xf348
+#define CUNIT_WRITE_DATA_HIGH				0xf34c
+#define CUNIT_WRITE_BYTE_ENABLE				0xf358
+#define CUNIT_READ_DATA_LOW				0xf350
+#define CUNIT_READ_DATA_HIGH				0xf354
+#define CUNIT_READ_ID					0xf35c
+
+/****************************************/
+/* Fast Ethernet Unit Registers		*/
 /****************************************/
 
 /* Ethernet */
 
-#define ETHERNET_PHY_ADDRESS_REGISTER                       0x2000
-#define ETHERNET_SMI_REGISTER                               0x2010
+#define ETHERNET_PHY_ADDRESS_REGISTER			0x2000
+#define ETHERNET_SMI_REGISTER				0x2010
 
 /* Ethernet 0 */
 
-#define ETHERNET0_PORT_CONFIGURATION_REGISTER               0x2400
-#define ETHERNET0_PORT_CONFIGURATION_EXTEND_REGISTER        0x2408
-#define ETHERNET0_PORT_COMMAND_REGISTER                     0x2410
-#define ETHERNET0_PORT_STATUS_REGISTER                      0x2418
-#define ETHERNET0_SERIAL_PARAMETRS_REGISTER                 0x2420
-#define ETHERNET0_HASH_TABLE_POINTER_REGISTER               0x2428
-#define ETHERNET0_FLOW_CONTROL_SOURCE_ADDRESS_LOW           0x2430
-#define ETHERNET0_FLOW_CONTROL_SOURCE_ADDRESS_HIGH          0x2438
-#define ETHERNET0_SDMA_CONFIGURATION_REGISTER               0x2440
-#define ETHERNET0_SDMA_COMMAND_REGISTER                     0x2448
-#define ETHERNET0_INTERRUPT_CAUSE_REGISTER                  0x2450
-#define ETHERNET0_INTERRUPT_MASK_REGISTER                   0x2458
-#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER0              0x2480
-#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER1              0x2484
-#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER2              0x2488
-#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER3              0x248c
-#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER0            0x24a0
-#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER1            0x24a4
-#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER2            0x24a8
-#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER3            0x24ac
-#define ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER0            0x24e0
-#define ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER1            0x24e4
-#define ETHERNET0_MIB_COUNTER_BASE                          0x2500
+#define ETHERNET0_PORT_CONFIGURATION_REGISTER		0x2400
+#define ETHERNET0_PORT_CONFIGURATION_EXTEND_REGISTER	0x2408
+#define ETHERNET0_PORT_COMMAND_REGISTER			0x2410
+#define ETHERNET0_PORT_STATUS_REGISTER			0x2418
+#define ETHERNET0_SERIAL_PARAMETRS_REGISTER		0x2420
+#define ETHERNET0_HASH_TABLE_POINTER_REGISTER		0x2428
+#define ETHERNET0_FLOW_CONTROL_SOURCE_ADDRESS_LOW	0x2430
+#define ETHERNET0_FLOW_CONTROL_SOURCE_ADDRESS_HIGH	0x2438
+#define ETHERNET0_SDMA_CONFIGURATION_REGISTER		0x2440
+#define ETHERNET0_SDMA_COMMAND_REGISTER			0x2448
+#define ETHERNET0_INTERRUPT_CAUSE_REGISTER		0x2450
+#define ETHERNET0_INTERRUPT_MASK_REGISTER		0x2458
+#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER0		0x2480
+#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER1		0x2484
+#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER2		0x2488
+#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER3		0x248c
+#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER0	0x24a0
+#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER1	0x24a4
+#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER2	0x24a8
+#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER3	0x24ac
+#define ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER0	0x24e0
+#define ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER1	0x24e4
+#define ETHERNET0_MIB_COUNTER_BASE			0x2500
 
 /* Ethernet 1 */
 
-#define ETHERNET1_PORT_CONFIGURATION_REGISTER               0x2800
-#define ETHERNET1_PORT_CONFIGURATION_EXTEND_REGISTER        0x2808
-#define ETHERNET1_PORT_COMMAND_REGISTER                     0x2810
-#define ETHERNET1_PORT_STATUS_REGISTER                      0x2818
-#define ETHERNET1_SERIAL_PARAMETRS_REGISTER                 0x2820
-#define ETHERNET1_HASH_TABLE_POINTER_REGISTER               0x2828
-#define ETHERNET1_FLOW_CONTROL_SOURCE_ADDRESS_LOW           0x2830
-#define ETHERNET1_FLOW_CONTROL_SOURCE_ADDRESS_HIGH          0x2838
-#define ETHERNET1_SDMA_CONFIGURATION_REGISTER               0x2840
-#define ETHERNET1_SDMA_COMMAND_REGISTER                     0x2848
-#define ETHERNET1_INTERRUPT_CAUSE_REGISTER                  0x2850
-#define ETHERNET1_INTERRUPT_MASK_REGISTER                   0x2858
-#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER0              0x2880
-#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER1              0x2884
-#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER2              0x2888
-#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER3              0x288c
-#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER0            0x28a0
-#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER1            0x28a4
-#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER2            0x28a8
-#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER3            0x28ac
-#define ETHERNET1_CURRENT_TX_DESCRIPTOR_POINTER0            0x28e0
-#define ETHERNET1_CURRENT_TX_DESCRIPTOR_POINTER1            0x28e4
-#define ETHERNET1_MIB_COUNTER_BASE                          0x2900
+#define ETHERNET1_PORT_CONFIGURATION_REGISTER		0x2800
+#define ETHERNET1_PORT_CONFIGURATION_EXTEND_REGISTER	0x2808
+#define ETHERNET1_PORT_COMMAND_REGISTER			0x2810
+#define ETHERNET1_PORT_STATUS_REGISTER			0x2818
+#define ETHERNET1_SERIAL_PARAMETRS_REGISTER		0x2820
+#define ETHERNET1_HASH_TABLE_POINTER_REGISTER		0x2828
+#define ETHERNET1_FLOW_CONTROL_SOURCE_ADDRESS_LOW	0x2830
+#define ETHERNET1_FLOW_CONTROL_SOURCE_ADDRESS_HIGH	0x2838
+#define ETHERNET1_SDMA_CONFIGURATION_REGISTER		0x2840
+#define ETHERNET1_SDMA_COMMAND_REGISTER			0x2848
+#define ETHERNET1_INTERRUPT_CAUSE_REGISTER		0x2850
+#define ETHERNET1_INTERRUPT_MASK_REGISTER		0x2858
+#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER0		0x2880
+#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER1		0x2884
+#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER2		0x2888
+#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER3		0x288c
+#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER0	0x28a0
+#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER1	0x28a4
+#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER2	0x28a8
+#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER3	0x28ac
+#define ETHERNET1_CURRENT_TX_DESCRIPTOR_POINTER0	0x28e0
+#define ETHERNET1_CURRENT_TX_DESCRIPTOR_POINTER1	0x28e4
+#define ETHERNET1_MIB_COUNTER_BASE			0x2900
 
 /* Ethernet 2 */
 
-#define ETHERNET2_PORT_CONFIGURATION_REGISTER               0x2c00
-#define ETHERNET2_PORT_CONFIGURATION_EXTEND_REGISTER        0x2c08
-#define ETHERNET2_PORT_COMMAND_REGISTER                     0x2c10
-#define ETHERNET2_PORT_STATUS_REGISTER                      0x2c18
-#define ETHERNET2_SERIAL_PARAMETRS_REGISTER                 0x2c20
-#define ETHERNET2_HASH_TABLE_POINTER_REGISTER               0x2c28
-#define ETHERNET2_FLOW_CONTROL_SOURCE_ADDRESS_LOW           0x2c30
-#define ETHERNET2_FLOW_CONTROL_SOURCE_ADDRESS_HIGH          0x2c38
-#define ETHERNET2_SDMA_CONFIGURATION_REGISTER               0x2c40
-#define ETHERNET2_SDMA_COMMAND_REGISTER                     0x2c48
-#define ETHERNET2_INTERRUPT_CAUSE_REGISTER                  0x2c50
-#define ETHERNET2_INTERRUPT_MASK_REGISTER                   0x2c58
-#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER0              0x2c80
-#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER1              0x2c84
-#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER2              0x2c88
-#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER3              0x2c8c
-#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER0            0x2ca0
-#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER1            0x2ca4
-#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER2            0x2ca8
-#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER3            0x2cac
-#define ETHERNET2_CURRENT_TX_DESCRIPTOR_POINTER0            0x2ce0
-#define ETHERNET2_CURRENT_TX_DESCRIPTOR_POINTER1            0x2ce4
-#define ETHERNET2_MIB_COUNTER_BASE                          0x2d00
-
-/****************************************/
-/* SDMA Registers                       */
-/****************************************/
-
-#define SDMA_GROUP_CONFIGURATION_REGISTER                   0xb1f0
-#define CHANNEL0_CONFIGURATION_REGISTER                     0x4000
-#define CHANNEL0_COMMAND_REGISTER                           0x4008
-#define CHANNEL0_RX_CMD_STATUS                              0x4800
-#define CHANNEL0_RX_PACKET_AND_BUFFER_SIZES                 0x4804
-#define CHANNEL0_RX_BUFFER_POINTER                          0x4808
-#define CHANNEL0_RX_NEXT_POINTER                            0x480c
-#define CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER              0x4810
-#define CHANNEL0_TX_CMD_STATUS                              0x4C00
-#define CHANNEL0_TX_PACKET_SIZE                             0x4C04
-#define CHANNEL0_TX_BUFFER_POINTER                          0x4C08
-#define CHANNEL0_TX_NEXT_POINTER                            0x4C0c
-#define CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER              0x4c10
-#define CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER                0x4c14
-#define CHANNEL1_CONFIGURATION_REGISTER                     0x5000
-#define CHANNEL1_COMMAND_REGISTER                           0x5008
-#define CHANNEL1_RX_CMD_STATUS                              0x5800
-#define CHANNEL1_RX_PACKET_AND_BUFFER_SIZES                 0x5804
-#define CHANNEL1_RX_BUFFER_POINTER                          0x5808
-#define CHANNEL1_RX_NEXT_POINTER                            0x580c
-#define CHANNEL1_TX_CMD_STATUS                              0x5C00
-#define CHANNEL1_TX_PACKET_SIZE                             0x5C04
-#define CHANNEL1_TX_BUFFER_POINTER                          0x5C08
-#define CHANNEL1_TX_NEXT_POINTER                            0x5C0c
-#define CHANNEL1_CURRENT_RX_DESCRIPTOR_POINTER              0x5810
-#define CHANNEL1_CURRENT_TX_DESCRIPTOR_POINTER              0x5c10
-#define CHANNEL1_FIRST_TX_DESCRIPTOR_POINTER                0x5c14
-#define CHANNEL2_CONFIGURATION_REGISTER                     0x6000
-#define CHANNEL2_COMMAND_REGISTER                           0x6008
-#define CHANNEL2_RX_CMD_STATUS                              0x6800
-#define CHANNEL2_RX_PACKET_AND_BUFFER_SIZES                 0x6804
-#define CHANNEL2_RX_BUFFER_POINTER                          0x6808
-#define CHANNEL2_RX_NEXT_POINTER                            0x680c
-#define CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER              0x6810
-#define CHANNEL2_TX_CMD_STATUS                              0x6C00
-#define CHANNEL2_TX_PACKET_SIZE                             0x6C04
-#define CHANNEL2_TX_BUFFER_POINTER                          0x6C08
-#define CHANNEL2_TX_NEXT_POINTER                            0x6C0c
-#define CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER              0x6810
-#define CHANNEL2_CURRENT_TX_DESCRIPTOR_POINTER              0x6c10
-#define CHANNEL2_FIRST_TX_DESCRIPTOR_POINTER                0x6c14
+#define ETHERNET2_PORT_CONFIGURATION_REGISTER		0x2c00
+#define ETHERNET2_PORT_CONFIGURATION_EXTEND_REGISTER	0x2c08
+#define ETHERNET2_PORT_COMMAND_REGISTER			0x2c10
+#define ETHERNET2_PORT_STATUS_REGISTER			0x2c18
+#define ETHERNET2_SERIAL_PARAMETRS_REGISTER		0x2c20
+#define ETHERNET2_HASH_TABLE_POINTER_REGISTER		0x2c28
+#define ETHERNET2_FLOW_CONTROL_SOURCE_ADDRESS_LOW	0x2c30
+#define ETHERNET2_FLOW_CONTROL_SOURCE_ADDRESS_HIGH	0x2c38
+#define ETHERNET2_SDMA_CONFIGURATION_REGISTER		0x2c40
+#define ETHERNET2_SDMA_COMMAND_REGISTER			0x2c48
+#define ETHERNET2_INTERRUPT_CAUSE_REGISTER		0x2c50
+#define ETHERNET2_INTERRUPT_MASK_REGISTER		0x2c58
+#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER0		0x2c80
+#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER1		0x2c84
+#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER2		0x2c88
+#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER3		0x2c8c
+#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER0	0x2ca0
+#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER1	0x2ca4
+#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER2	0x2ca8
+#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER3	0x2cac
+#define ETHERNET2_CURRENT_TX_DESCRIPTOR_POINTER0	0x2ce0
+#define ETHERNET2_CURRENT_TX_DESCRIPTOR_POINTER1	0x2ce4
+#define ETHERNET2_MIB_COUNTER_BASE			0x2d00
+
+/****************************************/
+/* SDMA Registers			*/
+/****************************************/
+
+#define SDMA_GROUP_CONFIGURATION_REGISTER		0xb1f0
+#define CHANNEL0_CONFIGURATION_REGISTER			0x4000
+#define CHANNEL0_COMMAND_REGISTER			0x4008
+#define CHANNEL0_RX_CMD_STATUS				0x4800
+#define CHANNEL0_RX_PACKET_AND_BUFFER_SIZES		0x4804
+#define CHANNEL0_RX_BUFFER_POINTER			0x4808
+#define CHANNEL0_RX_NEXT_POINTER			0x480c
+#define CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER		0x4810
+#define CHANNEL0_TX_CMD_STATUS				0x4C00
+#define CHANNEL0_TX_PACKET_SIZE				0x4C04
+#define CHANNEL0_TX_BUFFER_POINTER			0x4C08
+#define CHANNEL0_TX_NEXT_POINTER			0x4C0c
+#define CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER		0x4c10
+#define CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER		0x4c14
+#define CHANNEL1_CONFIGURATION_REGISTER			0x5000
+#define CHANNEL1_COMMAND_REGISTER			0x5008
+#define CHANNEL1_RX_CMD_STATUS				0x5800
+#define CHANNEL1_RX_PACKET_AND_BUFFER_SIZES		0x5804
+#define CHANNEL1_RX_BUFFER_POINTER			0x5808
+#define CHANNEL1_RX_NEXT_POINTER			0x580c
+#define CHANNEL1_TX_CMD_STATUS				0x5C00
+#define CHANNEL1_TX_PACKET_SIZE				0x5C04
+#define CHANNEL1_TX_BUFFER_POINTER			0x5C08
+#define CHANNEL1_TX_NEXT_POINTER			0x5C0c
+#define CHANNEL1_CURRENT_RX_DESCRIPTOR_POINTER		0x5810
+#define CHANNEL1_CURRENT_TX_DESCRIPTOR_POINTER		0x5c10
+#define CHANNEL1_FIRST_TX_DESCRIPTOR_POINTER		0x5c14
+#define CHANNEL2_CONFIGURATION_REGISTER			0x6000
+#define CHANNEL2_COMMAND_REGISTER			0x6008
+#define CHANNEL2_RX_CMD_STATUS				0x6800
+#define CHANNEL2_RX_PACKET_AND_BUFFER_SIZES		0x6804
+#define CHANNEL2_RX_BUFFER_POINTER			0x6808
+#define CHANNEL2_RX_NEXT_POINTER			0x680c
+#define CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER		0x6810
+#define CHANNEL2_TX_CMD_STATUS				0x6C00
+#define CHANNEL2_TX_PACKET_SIZE				0x6C04
+#define CHANNEL2_TX_BUFFER_POINTER			0x6C08
+#define CHANNEL2_TX_NEXT_POINTER			0x6C0c
+#define CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER		0x6810
+#define CHANNEL2_CURRENT_TX_DESCRIPTOR_POINTER		0x6c10
+#define CHANNEL2_FIRST_TX_DESCRIPTOR_POINTER		0x6c14
 
 /* SDMA Interrupt */
 
-#define SDMA_CAUSE                                          0xb820
-#define SDMA_MASK                                           0xb8a0
+#define SDMA_CAUSE					0xb820
+#define SDMA_MASK					0xb8a0
 
 
 /****************************************/
-/* Baude Rate Generators Registers      */
+/* Baude Rate Generators Registers	*/
 /****************************************/
 
 /* BRG 0 */
 
-#define BRG0_CONFIGURATION_REGISTER                         0xb200
-#define BRG0_BAUDE_TUNING_REGISTER                          0xb204
+#define BRG0_CONFIGURATION_REGISTER			0xb200
+#define BRG0_BAUDE_TUNING_REGISTER			0xb204
 
 /* BRG 1 */
 
-#define BRG1_CONFIGURATION_REGISTER                         0xb208
-#define BRG1_BAUDE_TUNING_REGISTER                          0xb20c
+#define BRG1_CONFIGURATION_REGISTER			0xb208
+#define BRG1_BAUDE_TUNING_REGISTER			0xb20c
 
 /* BRG 2 */
 
-#define BRG2_CONFIGURATION_REGISTER                         0xb210
-#define BRG2_BAUDE_TUNING_REGISTER                          0xb214
+#define BRG2_CONFIGURATION_REGISTER			0xb210
+#define BRG2_BAUDE_TUNING_REGISTER			0xb214
 
 /* BRG Interrupts */
 
-#define BRG_CAUSE_REGISTER                                  0xb834
-#define BRG_MASK_REGISTER                                   0xb8b4
+#define BRG_CAUSE_REGISTER				0xb834
+#define BRG_MASK_REGISTER				0xb8b4
 
 /* MISC */
 
-#define MAIN_ROUTING_REGISTER                               0xb400
-#define RECEIVE_CLOCK_ROUTING_REGISTER                      0xb404
-#define TRANSMIT_CLOCK_ROUTING_REGISTER                     0xb408
-#define COMM_UNIT_ARBITER_CONFIGURATION_REGISTER            0xb40c
-#define WATCHDOG_CONFIGURATION_REGISTER                     0xb410
-#define WATCHDOG_VALUE_REGISTER                             0xb414
+#define MAIN_ROUTING_REGISTER				0xb400
+#define RECEIVE_CLOCK_ROUTING_REGISTER			0xb404
+#define TRANSMIT_CLOCK_ROUTING_REGISTER			0xb408
+#define COMM_UNIT_ARBITER_CONFIGURATION_REGISTER	0xb40c
+#define WATCHDOG_CONFIGURATION_REGISTER			0xb410
+#define WATCHDOG_VALUE_REGISTER				0xb414
 
 
 /****************************************/
-/* Flex TDM Registers                   */
+/* Flex TDM Registers			*/
 /****************************************/
 
 /* FTDM Port */
 
-#define FLEXTDM_TRANSMIT_READ_POINTER                       0xa800
-#define FLEXTDM_RECEIVE_READ_POINTER                        0xa804
-#define FLEXTDM_CONFIGURATION_REGISTER                      0xa808
-#define FLEXTDM_AUX_CHANNELA_TX_REGISTER                    0xa80c
-#define FLEXTDM_AUX_CHANNELA_RX_REGISTER                    0xa810
-#define FLEXTDM_AUX_CHANNELB_TX_REGISTER                    0xa814
-#define FLEXTDM_AUX_CHANNELB_RX_REGISTER                    0xa818
+#define FLEXTDM_TRANSMIT_READ_POINTER			0xa800
+#define FLEXTDM_RECEIVE_READ_POINTER			0xa804
+#define FLEXTDM_CONFIGURATION_REGISTER			0xa808
+#define FLEXTDM_AUX_CHANNELA_TX_REGISTER		0xa80c
+#define FLEXTDM_AUX_CHANNELA_RX_REGISTER		0xa810
+#define FLEXTDM_AUX_CHANNELB_TX_REGISTER		0xa814
+#define FLEXTDM_AUX_CHANNELB_RX_REGISTER		0xa818
 
 /* FTDM Interrupts */
 
-#define FTDM_CAUSE_REGISTER                                 0xb830
-#define FTDM_MASK_REGISTER                                  0xb8b0
+#define FTDM_CAUSE_REGISTER				0xb830
+#define FTDM_MASK_REGISTER				0xb8b0
 
 
 /****************************************/
-/* GPP Interface Registers              */
+/* GPP Interface Registers		*/
 /****************************************/
 
-#define GPP_IO_CONTROL                                      0xf100
-#define GPP_LEVEL_CONTROL                                   0xf110
-#define GPP_VALUE                                           0xf104
-#define GPP_INTERRUPT_CAUSE                                 0xf108
-#define GPP_INTERRUPT_MASK                                  0xf10c
+#define GPP_IO_CONTROL					0xf100
+#define GPP_LEVEL_CONTROL				0xf110
+#define GPP_VALUE					0xf104
+#define GPP_INTERRUPT_CAUSE				0xf108
+#define GPP_INTERRUPT_MASK				0xf10c
 
-#define MPP_CONTROL0                                        0xf000
-#define MPP_CONTROL1                                        0xf004
-#define MPP_CONTROL2                                        0xf008
-#define MPP_CONTROL3                                        0xf00c
-#define DEBUG_PORT_MULTIPLEX                                0xf014
-#define SERIAL_PORT_MULTIPLEX                               0xf010
+#define MPP_CONTROL0					0xf000
+#define MPP_CONTROL1					0xf004
+#define MPP_CONTROL2					0xf008
+#define MPP_CONTROL3					0xf00c
+#define DEBUG_PORT_MULTIPLEX				0xf014
+#define SERIAL_PORT_MULTIPLEX				0xf010
 
 /****************************************/
-/* I2C Registers                        */
+/* I2C Registers			*/
 /****************************************/
 
-#define I2C_SLAVE_ADDRESS                                   0xc000
-#define I2C_EXTENDED_SLAVE_ADDRESS                          0xc040
-#define I2C_DATA                                            0xc004
-#define I2C_CONTROL                                         0xc008
-#define I2C_STATUS_BAUDE_RATE                               0xc00C
-#define I2C_SOFT_RESET                                      0xc01c
+#define I2C_SLAVE_ADDRESS				0xc000
+#define I2C_EXTENDED_SLAVE_ADDRESS			0xc040
+#define I2C_DATA					0xc004
+#define I2C_CONTROL					0xc008
+#define I2C_STATUS_BAUDE_RATE				0xc00C
+#define I2C_SOFT_RESET					0xc01c
 
 /****************************************/
-/* MPSC Registers                       */
+/* MPSC Registers			*/
 /****************************************/
 
 /* MPSC0  */
 
-#define MPSC0_MAIN_CONFIGURATION_LOW                        0x8000
-#define MPSC0_MAIN_CONFIGURATION_HIGH                       0x8004
-#define MPSC0_PROTOCOL_CONFIGURATION                        0x8008
-#define CHANNEL0_REGISTER1                                  0x800c
-#define CHANNEL0_REGISTER2                                  0x8010
-#define CHANNEL0_REGISTER3                                  0x8014
-#define CHANNEL0_REGISTER4                                  0x8018
-#define CHANNEL0_REGISTER5                                  0x801c
-#define CHANNEL0_REGISTER6                                  0x8020
-#define CHANNEL0_REGISTER7                                  0x8024
-#define CHANNEL0_REGISTER8                                  0x8028
-#define CHANNEL0_REGISTER9                                  0x802c
-#define CHANNEL0_REGISTER10                                 0x8030
-#define CHANNEL0_REGISTER11                                 0x8034
+#define MPSC0_MAIN_CONFIGURATION_LOW			0x8000
+#define MPSC0_MAIN_CONFIGURATION_HIGH			0x8004
+#define MPSC0_PROTOCOL_CONFIGURATION			0x8008
+#define CHANNEL0_REGISTER1				0x800c
+#define CHANNEL0_REGISTER2				0x8010
+#define CHANNEL0_REGISTER3				0x8014
+#define CHANNEL0_REGISTER4				0x8018
+#define CHANNEL0_REGISTER5				0x801c
+#define CHANNEL0_REGISTER6				0x8020
+#define CHANNEL0_REGISTER7				0x8024
+#define CHANNEL0_REGISTER8				0x8028
+#define CHANNEL0_REGISTER9				0x802c
+#define CHANNEL0_REGISTER10				0x8030
+#define CHANNEL0_REGISTER11				0x8034
 
 /* MPSC1  */
 
-#define MPSC1_MAIN_CONFIGURATION_LOW                        0x8840
-#define MPSC1_MAIN_CONFIGURATION_HIGH                       0x8844
-#define MPSC1_PROTOCOL_CONFIGURATION                        0x8848
-#define CHANNEL1_REGISTER1                                  0x884c
-#define CHANNEL1_REGISTER2                                  0x8850
-#define CHANNEL1_REGISTER3                                  0x8854
-#define CHANNEL1_REGISTER4                                  0x8858
-#define CHANNEL1_REGISTER5                                  0x885c
-#define CHANNEL1_REGISTER6                                  0x8860
-#define CHANNEL1_REGISTER7                                  0x8864
-#define CHANNEL1_REGISTER8                                  0x8868
-#define CHANNEL1_REGISTER9                                  0x886c
-#define CHANNEL1_REGISTER10                                 0x8870
-#define CHANNEL1_REGISTER11                                 0x8874
+#define MPSC1_MAIN_CONFIGURATION_LOW			0x8840
+#define MPSC1_MAIN_CONFIGURATION_HIGH			0x8844
+#define MPSC1_PROTOCOL_CONFIGURATION			0x8848
+#define CHANNEL1_REGISTER1				0x884c
+#define CHANNEL1_REGISTER2				0x8850
+#define CHANNEL1_REGISTER3				0x8854
+#define CHANNEL1_REGISTER4				0x8858
+#define CHANNEL1_REGISTER5				0x885c
+#define CHANNEL1_REGISTER6				0x8860
+#define CHANNEL1_REGISTER7				0x8864
+#define CHANNEL1_REGISTER8				0x8868
+#define CHANNEL1_REGISTER9				0x886c
+#define CHANNEL1_REGISTER10				0x8870
+#define CHANNEL1_REGISTER11				0x8874
 
 /* MPSC2  */
 
-#define MPSC2_MAIN_CONFIGURATION_LOW                        0x9040
-#define MPSC2_MAIN_CONFIGURATION_HIGH                       0x9044
-#define MPSC2_PROTOCOL_CONFIGURATION                        0x9048
-#define CHANNEL2_REGISTER1                                  0x904c
-#define CHANNEL2_REGISTER2                                  0x9050
-#define CHANNEL2_REGISTER3                                  0x9054
-#define CHANNEL2_REGISTER4                                  0x9058
-#define CHANNEL2_REGISTER5                                  0x905c
-#define CHANNEL2_REGISTER6                                  0x9060
-#define CHANNEL2_REGISTER7                                  0x9064
-#define CHANNEL2_REGISTER8                                  0x9068
-#define CHANNEL2_REGISTER9                                  0x906c
-#define CHANNEL2_REGISTER10                                 0x9070
-#define CHANNEL2_REGISTER11                                 0x9074
+#define MPSC2_MAIN_CONFIGURATION_LOW			0x9040
+#define MPSC2_MAIN_CONFIGURATION_HIGH			0x9044
+#define MPSC2_PROTOCOL_CONFIGURATION			0x9048
+#define CHANNEL2_REGISTER1				0x904c
+#define CHANNEL2_REGISTER2				0x9050
+#define CHANNEL2_REGISTER3				0x9054
+#define CHANNEL2_REGISTER4				0x9058
+#define CHANNEL2_REGISTER5				0x905c
+#define CHANNEL2_REGISTER6				0x9060
+#define CHANNEL2_REGISTER7				0x9064
+#define CHANNEL2_REGISTER8				0x9068
+#define CHANNEL2_REGISTER9				0x906c
+#define CHANNEL2_REGISTER10				0x9070
+#define CHANNEL2_REGISTER11				0x9074
 
 /* MPSCs Interupts  */
 
-#define MPSC0_CAUSE                                         0xb824
-#define MPSC0_MASK                                          0xb8a4
-#define MPSC1_CAUSE                                         0xb828
-#define MPSC1_MASK                                          0xb8a8
-#define MPSC2_CAUSE                                         0xb82c
-#define MPSC2_MASK                                          0xb8ac
+#define MPSC0_CAUSE					0xb824
+#define MPSC0_MASK					0xb8a4
+#define MPSC1_CAUSE					0xb828
+#define MPSC1_MASK					0xb8a8
+#define MPSC2_CAUSE					0xb82c
+#define MPSC2_MASK					0xb8ac
 
 #endif /* __INCgt64260rh */
diff --git a/include/i2c.h b/include/i2c.h
index 6e6c845312..a51c16464f 100644
--- a/include/i2c.h
+++ b/include/i2c.h
@@ -113,9 +113,9 @@ void  i2c_reg_write(uchar chip, uchar reg, uchar val);
  *  Change the active I2C bus.  Subsequent read/write calls will
  *  go to this one.
  *
- * 	bus - bus index, zero based
+ *	bus - bus index, zero based
  *
- * 	Returns: 0 on success, not 0 on failure
+ *	Returns: 0 on success, not 0 on failure
  *
  */
 int i2c_set_bus_num(unsigned int bus);
@@ -133,9 +133,9 @@ unsigned int i2c_get_bus_num(void);
  *
  *  Change the speed of the active I2C bus
  *
- * 	speed - bus speed in Hz
+ *	speed - bus speed in Hz
  *
- * 	Returns: 0 on success, not 0 on failure
+ *	Returns: 0 on success, not 0 on failure
  *
  */
 int i2c_set_bus_speed(unsigned int);
diff --git a/include/libfdt.h b/include/libfdt.h
index beeacb2e07..2a2b23d6c1 100644
--- a/include/libfdt.h
+++ b/include/libfdt.h
@@ -142,15 +142,15 @@ int fdt_next_node(const void *fdt, int offset, int *depth);
 
 #define fdt_get_header(fdt, field) \
 	(fdt32_to_cpu(((const struct fdt_header *)(fdt))->field))
-#define fdt_magic(fdt) 			(fdt_get_header(fdt, magic))
+#define fdt_magic(fdt)			(fdt_get_header(fdt, magic))
 #define fdt_totalsize(fdt)		(fdt_get_header(fdt, totalsize))
 #define fdt_off_dt_struct(fdt)		(fdt_get_header(fdt, off_dt_struct))
 #define fdt_off_dt_strings(fdt)		(fdt_get_header(fdt, off_dt_strings))
 #define fdt_off_mem_rsvmap(fdt)		(fdt_get_header(fdt, off_mem_rsvmap))
 #define fdt_version(fdt)		(fdt_get_header(fdt, version))
-#define fdt_last_comp_version(fdt) 	(fdt_get_header(fdt, last_comp_version))
-#define fdt_boot_cpuid_phys(fdt) 	(fdt_get_header(fdt, boot_cpuid_phys))
-#define fdt_size_dt_strings(fdt) 	(fdt_get_header(fdt, size_dt_strings))
+#define fdt_last_comp_version(fdt)	(fdt_get_header(fdt, last_comp_version))
+#define fdt_boot_cpuid_phys(fdt)	(fdt_get_header(fdt, boot_cpuid_phys))
+#define fdt_size_dt_strings(fdt)	(fdt_get_header(fdt, size_dt_strings))
 #define fdt_size_dt_struct(fdt)		(fdt_get_header(fdt, size_dt_struct))
 
 #define __fdt_set_hdr(name) \
@@ -445,7 +445,7 @@ uint32_t fdt_get_phandle(const void *fdt, int nodeoffset);
  *	0, on success
  *		buf contains the absolute path of the node at
  *		nodeoffset, as a NUL-terminated string.
- * 	-FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag
+ *	-FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag
  *	-FDT_ERR_NOSPACE, the path of the given node is longer than (bufsize-1)
  *		characters and will not fit in the given buffer.
  *	-FDT_ERR_BADMAGIC,
@@ -478,7 +478,7 @@ int fdt_get_path(const void *fdt, int nodeoffset, char *buf, int buflen);
 
  *	structure block offset of the node at node offset's ancestor
  *		of depth supernodedepth (>=0), on success
- * 	-FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag
+ *	-FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag
 *	-FDT_ERR_NOTFOUND, supernodedepth was greater than the depth of nodeoffset
  *	-FDT_ERR_BADMAGIC,
  *	-FDT_ERR_BADVERSION,
@@ -501,7 +501,7 @@ int fdt_supernode_atdepth_offset(const void *fdt, int nodeoffset,
  *
  * returns:
  *	depth of the node at nodeoffset (>=0), on success
- * 	-FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag
+ *	-FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag
  *	-FDT_ERR_BADMAGIC,
  *	-FDT_ERR_BADVERSION,
  *	-FDT_ERR_BADSTATE,
@@ -524,7 +524,7 @@ int fdt_node_depth(const void *fdt, int nodeoffset);
  * returns:
  *	stucture block offset of the parent of the node at nodeoffset
  *		(>=0), on success
- * 	-FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag
+ *	-FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag
  *	-FDT_ERR_BADMAGIC,
  *	-FDT_ERR_BADVERSION,
  *	-FDT_ERR_BADSTATE,
@@ -564,7 +564,7 @@ int fdt_parent_offset(const void *fdt, int nodeoffset);
  *		 on success
  *	-FDT_ERR_NOTFOUND, no node matching the criterion exists in the
  *		tree after startoffset
- * 	-FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag
+ *	-FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag
  *	-FDT_ERR_BADMAGIC,
  *	-FDT_ERR_BADVERSION,
  *	-FDT_ERR_BADSTATE,
@@ -611,7 +611,7 @@ int fdt_node_offset_by_phandle(const void *fdt, uint32_t phandle);
  *	1, if the node has a 'compatible' property, but it does not list
  *		the given string
  *	-FDT_ERR_NOTFOUND, if the given node has no 'compatible' property
- * 	-FDT_ERR_BADOFFSET, if nodeoffset does not refer to a BEGIN_NODE tag
+ *	-FDT_ERR_BADOFFSET, if nodeoffset does not refer to a BEGIN_NODE tag
  *	-FDT_ERR_BADMAGIC,
  *	-FDT_ERR_BADVERSION,
  *	-FDT_ERR_BADSTATE,
@@ -648,7 +648,7 @@ int fdt_node_check_compatible(const void *fdt, int nodeoffset,
  *		 on success
  *	-FDT_ERR_NOTFOUND, no node matching the criterion exists in the
  *		tree after startoffset
- * 	-FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag
+ *	-FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag
  *	-FDT_ERR_BADMAGIC,
  *	-FDT_ERR_BADVERSION,
  *	-FDT_ERR_BADSTATE,
diff --git a/include/linux/mtd/bbm.h b/include/linux/mtd/bbm.h
index f194cf1b3b..bffb25b257 100644
--- a/include/linux/mtd/bbm.h
+++ b/include/linux/mtd/bbm.h
@@ -26,8 +26,8 @@
  * struct nand_bbt_descr - bad block table descriptor
  * @param options	options for this descriptor
  * @param pages		the page(s) where we find the bbt, used with
- * 			option BBT_ABSPAGE when bbt is searched,
- * 			then we store the found bbts pages here.
+ *			option BBT_ABSPAGE when bbt is searched,
+ *			then we store the found bbts pages here.
  *			Its an array and supports up to 8 chips now
  * @param offs		offset of the pattern in the oob area of the page
  * @param veroffs	offset of the bbt version counter in the oob are of the page
diff --git a/include/linux/mtd/doc2000.h b/include/linux/mtd/doc2000.h
index eeb1d7e98e..29f6767865 100644
--- a/include/linux/mtd/doc2000.h
+++ b/include/linux/mtd/doc2000.h
@@ -19,8 +19,8 @@ struct DiskOnChip;
 #define DoC_DOCControl		0x1002
 #define DoC_FloorSelect		0x1003
 #define DoC_CDSNControl		0x1004
-#define DoC_CDSNDeviceSelect 	0x1005
-#define DoC_ECCConf 		0x1006
+#define DoC_CDSNDeviceSelect	0x1005
+#define DoC_ECCConf		0x1006
 #define DoC_2k_ECCStatus	0x1007
 
 #define DoC_CDSNSlowIO		0x100d
@@ -30,15 +30,15 @@ struct DiskOnChip;
 #define DoC_ECCSyndrome3	0x1013
 #define DoC_ECCSyndrome4	0x1014
 #define DoC_ECCSyndrome5	0x1015
-#define DoC_AliasResolution 	0x101b
+#define DoC_AliasResolution	0x101b
 #define DoC_ConfigInput		0x101c
-#define DoC_ReadPipeInit 	0x101d
-#define DoC_WritePipeTerm 	0x101e
-#define DoC_LastDataRead 	0x101f
-#define DoC_NOP 		0x1020
+#define DoC_ReadPipeInit	0x101d
+#define DoC_WritePipeTerm	0x101e
+#define DoC_LastDataRead	0x101f
+#define DoC_NOP			0x1020
 
-#define DoC_Mil_CDSN_IO 	0x0800
-#define DoC_2k_CDSN_IO 		0x1800
+#define DoC_Mil_CDSN_IO		0x0800
+#define DoC_2k_CDSN_IO		0x1800
 
 #define ReadDOC_(adr, reg)      ((volatile unsigned char)(*(volatile __u8 *)(((unsigned long)adr)+((reg)))))
 #define WriteDOC_(d, adr, reg)  do{ *(volatile __u8 *)(((unsigned long)adr)+((reg))) = (__u8)d; eieio();} while(0)
@@ -49,32 +49,32 @@ struct DiskOnChip;
 #define ReadDOC(adr, reg)      ReadDOC_(adr,DoC_##reg)
 #define WriteDOC(d, adr, reg)  WriteDOC_(d,adr,DoC_##reg)
 
-#define DOC_MODE_RESET 		0
-#define DOC_MODE_NORMAL 	1
-#define DOC_MODE_RESERVED1 	2
-#define DOC_MODE_RESERVED2 	3
-
-#define DOC_MODE_MDWREN 	4
-#define DOC_MODE_CLR_ERR 	0x80
-
-#define DOC_ChipID_UNKNOWN 	0x00
-#define DOC_ChipID_Doc2k 	0x20
-#define DOC_ChipID_DocMil 	0x30
-
-#define CDSN_CTRL_FR_B 		0x80
-#define CDSN_CTRL_ECC_IO 	0x20
-#define CDSN_CTRL_FLASH_IO 	0x10
-#define CDSN_CTRL_WP 		0x08
-#define CDSN_CTRL_ALE 		0x04
-#define CDSN_CTRL_CLE 		0x02
-#define CDSN_CTRL_CE 		0x01
-
-#define DOC_ECC_RESET 		0
-#define DOC_ECC_ERROR 		0x80
-#define DOC_ECC_RW 		0x20
-#define DOC_ECC__EN 		0x08
-#define DOC_TOGGLE_BIT 		0x04
-#define DOC_ECC_RESV 		0x02
+#define DOC_MODE_RESET		0
+#define DOC_MODE_NORMAL		1
+#define DOC_MODE_RESERVED1	2
+#define DOC_MODE_RESERVED2	3
+
+#define DOC_MODE_MDWREN		4
+#define DOC_MODE_CLR_ERR	0x80
+
+#define DOC_ChipID_UNKNOWN	0x00
+#define DOC_ChipID_Doc2k	0x20
+#define DOC_ChipID_DocMil	0x30
+
+#define CDSN_CTRL_FR_B		0x80
+#define CDSN_CTRL_ECC_IO	0x20
+#define CDSN_CTRL_FLASH_IO	0x10
+#define CDSN_CTRL_WP		0x08
+#define CDSN_CTRL_ALE		0x04
+#define CDSN_CTRL_CLE		0x02
+#define CDSN_CTRL_CE		0x01
+
+#define DOC_ECC_RESET		0
+#define DOC_ECC_ERROR		0x80
+#define DOC_ECC_RW		0x20
+#define DOC_ECC__EN		0x08
+#define DOC_TOGGLE_BIT		0x04
+#define DOC_ECC_RESV		0x02
 #define DOC_ECC_IGNORE		0x01
 
 /* We have to also set the reserved bit 1 for enable */
diff --git a/include/linux/mtd/mtd-abi.h b/include/linux/mtd/mtd-abi.h
index 3d1d416810..72d7341d75 100644
--- a/include/linux/mtd/mtd-abi.h
+++ b/include/linux/mtd/mtd-abi.h
@@ -46,7 +46,7 @@ struct mtd_oob_buf {
 
 
 /* Types of automatic ECC/Checksum available */
-#define MTD_ECC_NONE		0 	/* No automatic ECC available */
+#define MTD_ECC_NONE		0	/* No automatic ECC available */
 #define MTD_ECC_RS_DiskOnChip	1	/* Automatic ECC on DiskOnChip */
 #define MTD_ECC_SW		2	/* SW ECC for Toshiba & Samsung devices */
 
@@ -55,7 +55,7 @@ struct mtd_oob_buf {
 #define MTD_NANDECC_PLACE	1	/* Use the given placement in the structure (YAFFS1 legacy mode) */
 #define MTD_NANDECC_AUTOPLACE	2	/* Use the default placement scheme */
 #define MTD_NANDECC_PLACEONLY	3	/* Use the given placement in the structure (Do not store ecc result on read) */
-#define MTD_NANDECC_AUTOPL_USR 	4	/* Use the given autoplacement scheme rather than using the default */
+#define MTD_NANDECC_AUTOPL_USR	4	/* Use the given autoplacement scheme rather than using the default */
 
 struct mtd_info_user {
 	uint8_t type;
diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h
index 13e90803a1..71cb2d5c3b 100644
--- a/include/linux/mtd/mtd.h
+++ b/include/linux/mtd/mtd.h
@@ -13,7 +13,7 @@
 
 #define MAX_MTD_DEVICES 16
 
-#define MTD_ERASE_PENDING      	0x01
+#define MTD_ERASE_PENDING	0x01
 #define MTD_ERASING		0x02
 #define MTD_ERASE_SUSPEND	0x04
 #define MTD_ERASE_DONE          0x08
@@ -202,7 +202,7 @@ static inline void mtd_erase_callback(struct erase_info *instr)
 
 #ifdef CONFIG_MTD_DEBUG
 #define DEBUG(n, args...)				\
- 	do {						\
+	do {						\
 		if (n <= CONFIG_MTD_DEBUG_VERBOSE)	\
 			printk(KERN_INFO args);		\
 	} while(0)
diff --git a/include/linux/mtd/nand_legacy.h b/include/linux/mtd/nand_legacy.h
index a8769e72ad..b05e7267e4 100644
--- a/include/linux/mtd/nand_legacy.h
+++ b/include/linux/mtd/nand_legacy.h
@@ -104,12 +104,12 @@ struct Nand {
 };
 
 struct nand_chip {
-	int 		page_shift;
-	u_char 		*data_buf;
-	u_char 		*data_cache;
+	int		page_shift;
+	u_char		*data_buf;
+	u_char		*data_cache;
 	int		cache_page;
-	u_char 		ecc_code_buf[6];
-	u_char 		reserved[2];
+	u_char		ecc_code_buf[6];
+	u_char		reserved[2];
 	char ChipID; /* Type of DiskOnChip */
 	struct Nand *chips;
 	int chipshift;
diff --git a/include/linux/mtd/nftl.h b/include/linux/mtd/nftl.h
index 438130625d..b0337c3401 100644
--- a/include/linux/mtd/nftl.h
+++ b/include/linux/mtd/nftl.h
@@ -89,11 +89,11 @@ struct NFTLrecord {
 	__u16 numvunits;
 	__u16 lastEUN;                  /* should be suppressed */
 	__u16 numfreeEUNs;
-	__u16 LastFreeEUN; 		/* To speed up finding a free EUN */
+	__u16 LastFreeEUN;		/* To speed up finding a free EUN */
 	__u32 nr_sects;
 	int head,sect,cyl;
-	__u16 *EUNtable; 		/* [numvunits]: First EUN for each virtual unit  */
-	__u16 *ReplUnitTable; 		/* [numEUNs]: ReplUnitNumber for each */
+	__u16 *EUNtable;		/* [numvunits]: First EUN for each virtual unit  */
+	__u16 *ReplUnitTable;		/* [numEUNs]: ReplUnitNumber for each */
 	unsigned int nb_blocks;		/* number of physical blocks */
 	unsigned int nb_boot_blocks;	/* number of blocks used by the bios */
 };
diff --git a/include/lists.h b/include/lists.h
index 804b5cdca7..10a2a19273 100644
--- a/include/lists.h
+++ b/include/lists.h
@@ -1,8 +1,8 @@
 #ifndef _LISTS_H_
 #define _LISTS_H_
 
-#define LIST_START    	-1      /* Handy Constants that substitute for item positions */
-#define LIST_END      	0       /* END_OF_LIST means one past current length of list when */
+#define LIST_START	-1      /* Handy Constants that substitute for item positions */
+#define LIST_END	0       /* END_OF_LIST means one past current length of list when */
 				/* inserting. Otherwise it refers the last item in the list. */
 
 typedef struct
diff --git a/include/logbuff.h b/include/logbuff.h
index d415729053..d06d208844 100644
--- a/include/logbuff.h
+++ b/include/logbuff.h
@@ -31,8 +31,6 @@
 #define LOGBUFF_OVERHEAD (4096) /* Logbuffer overhead for extra info */
 #define LOGBUFF_RESERVE (LOGBUFF_LEN+LOGBUFF_OVERHEAD)
 
-#define LOGBUFF_INITIALIZED	(1<<31)
-
 /* The mapping used here has to be the same as in setup_ext_logbuff ()
    in linux/kernel/printk */
 
diff --git a/include/lxt971a.h b/include/lxt971a.h
index 2b5b6d44fb..f76c336879 100644
--- a/include/lxt971a.h
+++ b/include/lxt971a.h
@@ -30,75 +30,75 @@
 #define __LXT971A_H__
 
 /* PHY definitions (LXT971A) [2] */
-#define PHY_COMMON_CTRL    	 	(0x00)
-#define PHY_COMMON_STAT    	 	(0x01)
-#define PHY_COMMON_ID1    	 	(0x02)
-#define PHY_COMMON_ID2           	(0x03)
-#define PHY_COMMON_AUTO_ADV      	(0x04)
-#define PHY_COMMON_AUTO_LNKB     	(0x05)
-#define PHY_COMMON_AUTO_EXP      	(0x06)
-#define PHY_COMMON_AUTO_NEXT     	(0x07)
-#define PHY_COMMON_AUTO_LNKN     	(0x08)
-#define PHY_LXT971_PORT_CFG      	(0x10)
-#define PHY_LXT971_STAT2         	(0x11)
-#define PHY_LXT971_INT_ENABLE    	(0x12)
-#define PHY_LXT971_INT_STATUS    	(0x13)
-#define PHY_LXT971_LED_CFG       	(0x14)
-#define PHY_LXT971_DIG_CFG       	(0x1A)
-#define PHY_LXT971_TX_CTRL       	(0x1E)
+#define PHY_COMMON_CTRL			(0x00)
+#define PHY_COMMON_STAT			(0x01)
+#define PHY_COMMON_ID1			(0x02)
+#define PHY_COMMON_ID2			(0x03)
+#define PHY_COMMON_AUTO_ADV		(0x04)
+#define PHY_COMMON_AUTO_LNKB		(0x05)
+#define PHY_COMMON_AUTO_EXP		(0x06)
+#define PHY_COMMON_AUTO_NEXT		(0x07)
+#define PHY_COMMON_AUTO_LNKN		(0x08)
+#define PHY_LXT971_PORT_CFG		(0x10)
+#define PHY_LXT971_STAT2		(0x11)
+#define PHY_LXT971_INT_ENABLE		(0x12)
+#define PHY_LXT971_INT_STATUS		(0x13)
+#define PHY_LXT971_LED_CFG		(0x14)
+#define PHY_LXT971_DIG_CFG		(0x1A)
+#define PHY_LXT971_TX_CTRL		(0x1E)
 
 /* CTRL PHY Control Register Bit Fields */
-#define PHY_COMMON_CTRL_RESET  	 	(0x8000)
-#define PHY_COMMON_CTRL_LOOPBACK 	(0x4000)
-#define PHY_COMMON_CTRL_SPD_MA   	(0x2040)
-#define PHY_COMMON_CTRL_SPD_10   	(0x0000)
-#define PHY_COMMON_CTRL_SPD_100  	(0x2000)
-#define PHY_COMMON_CTRL_SPD_1000 	(0x0040)
-#define PHY_COMMON_CTRL_SPD_RES  	(0x2040)
-#define PHY_COMMON_CTRL_AUTO_NEG 	(0x1000)
-#define PHY_COMMON_CTRL_POWER_DN 	(0x0800)
-#define PHY_COMMON_CTRL_ISOLATE	 	(0x0400)
-#define PHY_COMMON_CTRL_RES_AUTO 	(0x0200)
-#define PHY_COMMON_CTRL_DUPLEX	 	(0x0100)
-#define PHY_COMMON_CTRL_COL_TEST 	(0x0080)
-#define PHY_COMMON_CTRL_RES1     	(0x003F)
+#define PHY_COMMON_CTRL_RESET		(0x8000)
+#define PHY_COMMON_CTRL_LOOPBACK	(0x4000)
+#define PHY_COMMON_CTRL_SPD_MA		(0x2040)
+#define PHY_COMMON_CTRL_SPD_10		(0x0000)
+#define PHY_COMMON_CTRL_SPD_100		(0x2000)
+#define PHY_COMMON_CTRL_SPD_1000	(0x0040)
+#define PHY_COMMON_CTRL_SPD_RES		(0x2040)
+#define PHY_COMMON_CTRL_AUTO_NEG	(0x1000)
+#define PHY_COMMON_CTRL_POWER_DN	(0x0800)
+#define PHY_COMMON_CTRL_ISOLATE		(0x0400)
+#define PHY_COMMON_CTRL_RES_AUTO	(0x0200)
+#define PHY_COMMON_CTRL_DUPLEX		(0x0100)
+#define PHY_COMMON_CTRL_COL_TEST	(0x0080)
+#define PHY_COMMON_CTRL_RES1		(0x003F)
 
 /* STAT Status Register Bit Fields */
-#define PHY_COMMON_STAT_100BT4	 	(0x8000)
-#define PHY_COMMON_STAT_100BXFD	 	(0x4000)
-#define PHY_COMMON_STAT_100BXHD	 	(0x2000)
-#define PHY_COMMON_STAT_10BTFD	 	(0x1000)
-#define PHY_COMMON_STAT_10BTHD	 	(0x0800)
-#define PHY_COMMON_STAT_100BT2FD 	(0x0400)
-#define PHY_COMMON_STAT_100BT2HD 	(0x0200)
-#define PHY_COMMON_STAT_EXT_STAT 	(0x0100)
-#define PHY_COMMON_STAT_RES1	 	(0x0080)
-#define PHY_COMMON_STAT_MF_PSUP	 	(0x0040)
-#define PHY_COMMON_STAT_AN_COMP  	(0x0020)
-#define PHY_COMMON_STAT_RMT_FLT	 	(0x0010)
-#define PHY_COMMON_STAT_AN_CAP	 	(0x0008)
-#define PHY_COMMON_STAT_LNK_STAT 	(0x0004)
-#define PHY_COMMON_STAT_JAB_DTCT 	(0x0002)
-#define PHY_COMMON_STAT_EXT_CAP	 	(0x0001)
+#define PHY_COMMON_STAT_100BT4		(0x8000)
+#define PHY_COMMON_STAT_100BXFD		(0x4000)
+#define PHY_COMMON_STAT_100BXHD		(0x2000)
+#define PHY_COMMON_STAT_10BTFD		(0x1000)
+#define PHY_COMMON_STAT_10BTHD		(0x0800)
+#define PHY_COMMON_STAT_100BT2FD	(0x0400)
+#define PHY_COMMON_STAT_100BT2HD	(0x0200)
+#define PHY_COMMON_STAT_EXT_STAT	(0x0100)
+#define PHY_COMMON_STAT_RES1		(0x0080)
+#define PHY_COMMON_STAT_MF_PSUP		(0x0040)
+#define PHY_COMMON_STAT_AN_COMP		(0x0020)
+#define PHY_COMMON_STAT_RMT_FLT		(0x0010)
+#define PHY_COMMON_STAT_AN_CAP		(0x0008)
+#define PHY_COMMON_STAT_LNK_STAT	(0x0004)
+#define PHY_COMMON_STAT_JAB_DTCT	(0x0002)
+#define PHY_COMMON_STAT_EXT_CAP		(0x0001)
 
 /* AUTO_ADV Auto-neg Advert Register Bit Fields */
-#define PHY_COMMON_AUTO_ADV_NP       	(0x8000)
+#define PHY_COMMON_AUTO_ADV_NP		(0x8000)
 #define PHY_COMMON_AUTO_ADV_RES1        (0x4000)
 #define PHY_COMMON_AUTO_ADV_RMT_FLT     (0x2000)
 #define PHY_COMMON_AUTO_ADV_RES2        (0x1000)
 #define PHY_COMMON_AUTO_ADV_AS_PAUSE    (0x0800)
 #define PHY_COMMON_AUTO_ADV_PAUSE       (0x0400)
 #define PHY_COMMON_AUTO_ADV_100BT4      (0x0200)
-#define PHY_COMMON_AUTO_ADV_100BTXFD   	(0x0100)
+#define PHY_COMMON_AUTO_ADV_100BTXFD	(0x0100)
 #define PHY_COMMON_AUTO_ADV_100BTX      (0x0080)
-#define PHY_COMMON_AUTO_ADV_10BTFD   	(0x0040)
-#define PHY_COMMON_AUTO_ADV_10BT     	(0x0020)
+#define PHY_COMMON_AUTO_ADV_10BTFD	(0x0040)
+#define PHY_COMMON_AUTO_ADV_10BT	(0x0020)
 #define PHY_COMMON_AUTO_ADV_SEL_FLD_MA  (0x001F)
 #define PHY_COMMON_AUTO_ADV_802_9       (0x0002)
 #define PHY_COMMON_AUTO_ADV_802_3       (0x0001)
 
 /* AUTO_LNKB Auto-neg Link Ability Register Bit Fields */
-#define PHY_COMMON_AUTO_LNKB_NP       	(0x8000)
+#define PHY_COMMON_AUTO_LNKB_NP		(0x8000)
 #define PHY_COMMON_AUTO_LNKB_ACK        (0x4000)
 #define PHY_COMMON_AUTO_LNKB_RMT_FLT    (0x2000)
 #define PHY_COMMON_AUTO_LNKB_RES2       (0x1000)
@@ -107,8 +107,8 @@
 #define PHY_COMMON_AUTO_LNKB_100BT4     (0x0200)
 #define PHY_COMMON_AUTO_LNKB_100BTXFD   (0x0100)
 #define PHY_COMMON_AUTO_LNKB_100BTX     (0x0080)
-#define PHY_COMMON_AUTO_LNKB_10BTFD   	(0x0040)
-#define PHY_COMMON_AUTO_LNKB_10BT     	(0x0020)
+#define PHY_COMMON_AUTO_LNKB_10BTFD	(0x0040)
+#define PHY_COMMON_AUTO_LNKB_10BT	(0x0020)
 #define PHY_COMMON_AUTO_LNKB_SEL_FLD_MA (0x001F)
 #define PHY_COMMON_AUTO_LNKB_802_9      (0x0002)
 #define PHY_COMMON_AUTO_LNKB_802_3      (0x0001)
@@ -159,20 +159,20 @@
 #define PHY_LXT971_PORT_CFG_FIBER_SEL   (0x0001)
 
 /* STAT2 Status Register #2 Bit Fields */
-#define PHY_LXT971_STAT2_RES1   	(0x8000)
-#define PHY_LXT971_STAT2_100BTX 	(0x4000)
+#define PHY_LXT971_STAT2_RES1		(0x8000)
+#define PHY_LXT971_STAT2_100BTX		(0x4000)
 #define PHY_LXT971_STAT2_TX_STATUS	(0x2000)
 #define PHY_LXT971_STAT2_RX_STATUS	(0x1000)
 #define PHY_LXT971_STAT2_COL_STATUS	(0x0800)
-#define PHY_LXT971_STAT2_LINK   	(0x0400)
+#define PHY_LXT971_STAT2_LINK		(0x0400)
 #define PHY_LXT971_STAT2_DUPLEX_MODE	(0x0200)
 #define PHY_LXT971_STAT2_AUTO_NEG	(0x0100)
-#define PHY_LXT971_STAT2_AUTO_NEG_COMP 	(0x0080)
-#define PHY_LXT971_STAT2_RES2   	(0x0040)
+#define PHY_LXT971_STAT2_AUTO_NEG_COMP	(0x0080)
+#define PHY_LXT971_STAT2_RES2		(0x0040)
 #define PHY_LXT971_STAT2_POLARITY	(0x0020)
-#define PHY_LXT971_STAT2_PAUSE  	(0x0010)
-#define PHY_LXT971_STAT2_ERROR  	(0x0008)
-#define PHY_LXT971_STAT2_RES3   	(0x0007)
+#define PHY_LXT971_STAT2_PAUSE		(0x0010)
+#define PHY_LXT971_STAT2_ERROR		(0x0008)
+#define PHY_LXT971_STAT2_RES3		(0x0007)
 
 /* INT_ENABLE Interrupt Enable Register Bit Fields */
 #define PHY_LXT971_INT_ENABLE_RES1      (0xFF00)
@@ -225,11 +225,11 @@
 #define PHY_LXT971_LED_CFG_SPEED        (0x0000)
 
 /* DIG_CFG Digitial Configuration Register Bit Fields */
-#define PHY_LXT971_DIG_CFG_RES1 	(0xF000)
+#define PHY_LXT971_DIG_CFG_RES1		(0xF000)
 #define PHY_LXT971_DIG_CFG_MII_DRIVE	(0x0800)
-#define PHY_LXT971_DIG_CFG_RES2 	(0x0400)
+#define PHY_LXT971_DIG_CFG_RES2		(0x0400)
 #define PHY_LXT971_DIG_CFG_SHOW_SYMBOL	(0x0200)
-#define PHY_LXT971_DIG_CFG_RES3 	(0x01FF)
+#define PHY_LXT971_DIG_CFG_RES3		(0x01FF)
 
 #define PHY_LXT971_MDIO_MAX_CLK		(8000000)
 #define PHY_MDIO_MAX_CLK		(2500000)
diff --git a/include/mpc106.h b/include/mpc106.h
index ab6d57e199..10ed0f4632 100644
--- a/include/mpc106.h
+++ b/include/mpc106.h
@@ -28,7 +28,7 @@
  * Defines for the MPC106 PCI Config address and data registers followed by
  * defines for the standard PCI device configuration header.
  */
-#define PCIDEVID_MPC106 		0x0
+#define PCIDEVID_MPC106			0x0
 
 /*
  * MPC106 Registers
@@ -36,7 +36,7 @@
 #define	MPC106_REG			0x80000000
 
 #ifdef CFG_ADDRESS_MAP_A
-#define MPC106_REG_ADDR 		0x80000cf8
+#define MPC106_REG_ADDR			0x80000cf8
 #define	MPC106_REG_DATA			0x80000cfc
 #define MPC106_ISA_IO_PHYS		0x80000000
 #define MPC106_ISA_IO_BUS		0x00000000
@@ -51,7 +51,7 @@
 #define	MPC106_PCI_MEMORY_BUS		0x80000000
 #define	MPC106_PCI_MEMORY_SIZE		0x80000000
 #else
-#define MPC106_REG_ADDR 		0xfec00cf8
+#define MPC106_REG_ADDR			0xfec00cf8
 #define	MPC106_REG_DATA			0xfee00cfc
 #define MPC106_ISA_MEM_PHYS		0xfd000000
 #define MPC106_ISA_MEM_BUS		0x00000000
@@ -77,9 +77,9 @@
 
 #define PCI_STAT_NO_RSV_BITS		0xffff
 
-#define PCI_BUSNUM       		0x40
-#define PCI_SUBBUSNUM    		0x41
-#define PCI_DISCOUNT     		0x42
+#define PCI_BUSNUM			0x40
+#define PCI_SUBBUSNUM			0x41
+#define PCI_DISCOUNT			0x42
 
 #define PCI_PICR1			0xA8
 #define PICR1_CF_CBA(value)		((value & 0xff) << 24)
diff --git a/include/net.h b/include/net.h
index 9a2f03fe98..79ddfa294a 100644
--- a/include/net.h
+++ b/include/net.h
@@ -240,7 +240,7 @@ typedef struct
 /*
  * ICMP stuff (just enough to handle (host) redirect messages)
  */
-#define ICMP_ECHO_REPLY		0	/* Echo reply 			*/
+#define ICMP_ECHO_REPLY		0	/* Echo reply			*/
 #define ICMP_REDIRECT		5	/* Redirect (change route)	*/
 #define ICMP_ECHO_REQUEST	8	/* Echo request			*/
 
@@ -327,12 +327,12 @@ extern unsigned		NetIPID;		/* IP ID (counting)		*/
 extern uchar		NetBcastAddr[6];	/* Ethernet boardcast address	*/
 extern uchar		NetEtherNullAddr[6];
 
-#define VLAN_NONE	4095			/* untagged 			*/
-#define VLAN_IDMASK	0x0fff			/* mask of valid vlan id 	*/
-extern ushort		NetOurVLAN;		/* Our VLAN 			*/
-extern ushort		NetOurNativeVLAN;	/* Our Native VLAN 		*/
+#define VLAN_NONE	4095			/* untagged			*/
+#define VLAN_IDMASK	0x0fff			/* mask of valid vlan id	*/
+extern ushort		NetOurVLAN;		/* Our VLAN			*/
+extern ushort		NetOurNativeVLAN;	/* Our Native VLAN		*/
 
-extern uchar		NetCDPAddr[6]; 		/* Ethernet CDP address		*/
+extern uchar		NetCDPAddr[6];		/* Ethernet CDP address		*/
 extern ushort		CDPNativeVLAN;		/* CDP returned native VLAN	*/
 extern ushort		CDPApplianceVLAN;	/* CDP returned appliance VLAN	*/
 
@@ -352,7 +352,7 @@ typedef enum { BOOTP, RARP, ARP, TFTP, DHCP, PING, DNS, NFS, CDP, NETCONS, SNTP
 extern char	BootFile[128];			/* Boot File name		*/
 
 #if defined(CONFIG_CMD_PING)
-extern IPaddr_t	NetPingIP;			/* the ip address to ping 		*/
+extern IPaddr_t	NetPingIP;			/* the ip address to ping		*/
 #endif
 
 #if defined(CONFIG_CMD_CDP)
@@ -362,7 +362,7 @@ extern ushort CDPApplianceVLAN;
 #endif
 
 #if defined(CONFIG_CMD_SNTP)
-extern IPaddr_t	NetNtpServerIP;			/* the ip address to NTP 	*/
+extern IPaddr_t	NetNtpServerIP;			/* the ip address to NTP	*/
 extern int NetTimeOffset;			/* offset time from UTC		*/
 #endif
 
@@ -376,7 +376,7 @@ extern void	NetStop(void);
 extern void	NetStartAgain(void);
 
 /* Get size of the ethernet header when we send */
-extern int 	NetEthHdrSize(void);
+extern int	NetEthHdrSize(void);
 
 /* Set ethernet header; returns the size of the header */
 extern int	NetSetEther(volatile uchar *, uchar *, uint);
diff --git a/include/nios2-epcs.h b/include/nios2-epcs.h
index 20e0c87c89..325cf71f67 100644
--- a/include/nios2-epcs.h
+++ b/include/nios2-epcs.h
@@ -29,7 +29,7 @@
 #define __NIOS2_EPCS_H__
 
 typedef struct epcs_devinfo_t {
-	const char 	*name;		/* Device name */
+	const char	*name;		/* Device name */
 	unsigned char	id;		/* Device silicon id */
 	unsigned char	size;		/* Total size log2(bytes)*/
 	unsigned char	num_sects;	/* Number of sectors */
diff --git a/include/nios2-io.h b/include/nios2-io.h
index d5c8652d5d..dc87f1f7f9 100644
--- a/include/nios2-io.h
+++ b/include/nios2-io.h
@@ -156,14 +156,14 @@ typedef volatile struct nios_jtag_t {
 #define NIOS_JTAG_WI		(1 << 9)	/* write intr pending*/
 #define NIOS_JTAG_AC		(1 << 10)	/* activity indicator */
 #define NIOS_JTAG_RRDY		(1 << 12)	/* read available */
-#define NIOS_JTAG_WSPACE(d) 	((d)>>16)	/* Write space avail */
+#define NIOS_JTAG_WSPACE(d)	((d)>>16)	/* Write space avail */
 
 /*------------------------------------------------------------------------
  * SYSTEM ID
  *----------------------------------------------------------------------*/
 typedef volatile struct nios_sysid_t {
-	unsigned 	id;			/* The system build id*/
-	unsigned 	timestamp;		/* Timestamp */
+	unsigned	id;			/* The system build id*/
+	unsigned	timestamp;		/* Timestamp */
 }nios_sysid_t;
 
 #endif /* __NIOS2IO_H__ */
diff --git a/include/ns7520_eth.h b/include/ns7520_eth.h
index 5019802a33..123e6f4c2a 100644
--- a/include/ns7520_eth.h
+++ b/include/ns7520_eth.h
@@ -28,7 +28,7 @@
 
 /* The port addresses */
 
-#define	NS7520_ETH_MODULE_BASE	 	(0xFF800000)
+#define	NS7520_ETH_MODULE_BASE		(0xFF800000)
 
 #define get_eth_reg_addr(c) \
      ((volatile unsigned int*) ( NS7520_ETH_MODULE_BASE+(unsigned int) (c)))
@@ -153,7 +153,7 @@
 
 /* MAC1 MAC Configuration Register 1 Bit Fields*/
 
-#define NS7520_ETH_MAC1_RES1 	 (0xFFFF0000)	/* Reserved */
+#define NS7520_ETH_MAC1_RES1	 (0xFFFF0000)	/* Reserved */
 #define NS7520_ETH_MAC1_SRST	 (0x00008000)	/* Soft Reset */
 #define NS7520_ETH_MAC1_SIMMRST	 (0x00004000)	/* Simulation Reset */
 #define NS7520_ETH_MAC1_RES2	 (0x00003000)	/* Reserved */
@@ -170,7 +170,7 @@
 
 /* MAC Configuration Register 2 Bit Fields*/
 
-#define NS7520_ETH_MAC2_RES1 	 (0xFFFF8000)	/* Reserved */
+#define NS7520_ETH_MAC2_RES1	 (0xFFFF8000)	/* Reserved */
 #define NS7520_ETH_MAC2_EDEFER	 (0x00004000)	/* Excess Deferral */
 #define NS7520_ETH_MAC2_BACKP	 (0x00002000)	/* Backpressure/NO back off */
 #define NS7520_ETH_MAC2_NOBO	 (0x00001000)	/* No back off */
@@ -179,7 +179,7 @@
 #define NS7520_ETH_MAC2_PUREP	 (0x00000100)	/* Pure preamble enforcement */
 #define NS7520_ETH_MAC2_AUTOP	 (0x00000080)	/* Auto detect PAD enable */
 #define NS7520_ETH_MAC2_VLANP	 (0x00000040)	/* VLAN pad enable */
-#define NS7520_ETH_MAC2_PADEN  	 (0x00000020)	/* PAD/CRC enable */
+#define NS7520_ETH_MAC2_PADEN	 (0x00000020)	/* PAD/CRC enable */
 #define NS7520_ETH_MAC2_CRCEN	 (0x00000010)	/* CRC enable */
 #define NS7520_ETH_MAC2_DELCRC	 (0x00000008)	/* Delayed CRC */
 #define NS7520_ETH_MAC2_HUGE	 (0x00000004)	/* Huge frame enable */
diff --git a/include/ns9750_bbus.h b/include/ns9750_bbus.h
index 0918931cb2..9485338f73 100644
--- a/include/ns9750_bbus.h
+++ b/include/ns9750_bbus.h
@@ -44,7 +44,7 @@
    They should be wrapped by cli()/sti() */
 #define set_gpio_cfg_reg_val(pin,cfg) \
 	*get_gpio_cfg_reg_addr(pin)=(*get_gpio_cfg_reg_addr((pin)) & \
-				 	~NS9750_GPIO_CFG_MASK((pin))) |\
+					~NS9750_GPIO_CFG_MASK((pin))) |\
 				NS9750_GPIO_CFG_VAL((pin),(cfg));
 
 #define NS9750_GPIO_CFG_MASK(pin)	(NS9750_GPIO_CFG_VAL(pin, \
@@ -93,16 +93,16 @@
 #define NS9750_BBUS_DMA_INT_BINT12	(0x00001000)
 #define NS9750_BBUS_DMA_INT_BINT11	(0x00000800)
 #define NS9750_BBUS_DMA_INT_BINT10	(0x00000400)
-#define NS9750_BBUS_DMA_INT_BINT9 	(0x00000200)
-#define NS9750_BBUS_DMA_INT_BINT8 	(0x00000100)
-#define NS9750_BBUS_DMA_INT_BINT7 	(0x00000080)
-#define NS9750_BBUS_DMA_INT_BINT6 	(0x00000040)
-#define NS9750_BBUS_DMA_INT_BINT5 	(0x00000020)
-#define NS9750_BBUS_DMA_INT_BINT4 	(0x00000010)
-#define NS9750_BBUS_DMA_INT_BINT3 	(0x00000008)
-#define NS9750_BBUS_DMA_INT_BINT2 	(0x00000004)
-#define NS9750_BBUS_DMA_INT_BINT1 	(0x00000002)
-#define NS9750_BBUS_DMA_INT_BINT0 	(0x00000001)
+#define NS9750_BBUS_DMA_INT_BINT9	(0x00000200)
+#define NS9750_BBUS_DMA_INT_BINT8	(0x00000100)
+#define NS9750_BBUS_DMA_INT_BINT7	(0x00000080)
+#define NS9750_BBUS_DMA_INT_BINT6	(0x00000040)
+#define NS9750_BBUS_DMA_INT_BINT5	(0x00000020)
+#define NS9750_BBUS_DMA_INT_BINT4	(0x00000010)
+#define NS9750_BBUS_DMA_INT_BINT3	(0x00000008)
+#define NS9750_BBUS_DMA_INT_BINT2	(0x00000004)
+#define NS9750_BBUS_DMA_INT_BINT1	(0x00000002)
+#define NS9750_BBUS_DMA_INT_BINT0	(0x00000001)
 
 #define NS9750_BBUS_USB_CFG_OUTEN	(0x00000008)
 #define NS9750_BBUS_USB_CFG_SPEED	(0x00000004)
diff --git a/include/ns9750_eth.h b/include/ns9750_eth.h
index 978c0bbdba..a6e5889b7b 100644
--- a/include/ns9750_eth.h
+++ b/include/ns9750_eth.h
@@ -33,19 +33,19 @@
 
 #include "lxt971a.h"
 
-#define	NS9750_ETH_MODULE_BASE	 	(0xA0600000)
+#define	NS9750_ETH_MODULE_BASE		(0xA0600000)
 
 #define get_eth_reg_addr(c) \
      ((volatile unsigned int*) ( NS9750_ETH_MODULE_BASE+(unsigned int) (c)))
 
-#define NS9750_ETH_EGCR1	 	(0x0000)
-#define NS9750_ETH_EGCR2	 	(0x0004)
-#define NS9750_ETH_EGSR		 	(0x0008)
-#define NS9750_ETH_FIFORX	 	(0x000C)
-#define NS9750_ETH_FIFOTX	 	(0x0010)
-#define NS9750_ETH_FIFOTXS	 	(0x0014)
-#define NS9750_ETH_ETSR		 	(0x0018)
-#define NS9750_ETH_ERSR		 	(0x001C)
+#define NS9750_ETH_EGCR1		(0x0000)
+#define NS9750_ETH_EGCR2		(0x0004)
+#define NS9750_ETH_EGSR			(0x0008)
+#define NS9750_ETH_FIFORX		(0x000C)
+#define NS9750_ETH_FIFOTX		(0x0010)
+#define NS9750_ETH_FIFOTXS		(0x0014)
+#define NS9750_ETH_ETSR			(0x0018)
+#define NS9750_ETH_ERSR			(0x001C)
 #define NS9750_ETH_MAC1			(0x0400)
 #define NS9750_ETH_MAC2			(0x0404)
 #define NS9750_ETH_IPGT			(0x0408)
@@ -64,9 +64,9 @@
 #define NS9750_ETH_SA2			(0x0444)
 #define NS9750_ETH_SA3			(0x0448)
 #define NS9750_ETH_SAFR			(0x0500)
-#define NS9750_ETH_HT1		 	(0x0504)
-#define NS9750_ETH_HT2		 	(0x0508)
-#define NS9750_ETH_STAT_BASE	 	(0x0680)
+#define NS9750_ETH_HT1			(0x0504)
+#define NS9750_ETH_HT2			(0x0508)
+#define NS9750_ETH_STAT_BASE		(0x0680)
 #define NS9750_ETH_RXAPTR		(0x0A00)
 #define NS9750_ETH_RXBPTR		(0x0A04)
 #define NS9750_ETH_RXCPTR		(0x0A08)
@@ -87,26 +87,26 @@
 
 /* register bit fields */
 
-#define NS9750_ETH_EGCR1_ERX	 	(0x80000000)
-#define NS9750_ETH_EGCR1_ERXDMA	 	(0x40000000)
-#define NS9750_ETH_EGCR1_ERXSHT	 	(0x10000000)
-#define NS9750_ETH_EGCR1_ERXSIZ	 	(0x08000000)
-#define NS9750_ETH_EGCR1_ETXSIZ	 	(0x04000000)
+#define NS9750_ETH_EGCR1_ERX		(0x80000000)
+#define NS9750_ETH_EGCR1_ERXDMA		(0x40000000)
+#define NS9750_ETH_EGCR1_ERXSHT		(0x10000000)
+#define NS9750_ETH_EGCR1_ERXSIZ		(0x08000000)
+#define NS9750_ETH_EGCR1_ETXSIZ		(0x04000000)
 #define NS9750_ETH_EGCR1_ETXDIAG	(0x02000000)
-#define NS9750_ETH_EGCR1_ERXBAD	 	(0x01000000)
-#define NS9750_ETH_EGCR1_ETX	 	(0x00800000)
-#define NS9750_ETH_EGCR1_ETXDMA	 	(0x00400000)
-#define NS9750_ETH_EGCR1_ETXWM	  	(0x00200000)
-#define NS9750_ETH_EGCR1_ERXADV	 	(0x00100000)
+#define NS9750_ETH_EGCR1_ERXBAD		(0x01000000)
+#define NS9750_ETH_EGCR1_ETX		(0x00800000)
+#define NS9750_ETH_EGCR1_ETXDMA		(0x00400000)
+#define NS9750_ETH_EGCR1_ETXWM		(0x00200000)
+#define NS9750_ETH_EGCR1_ERXADV		(0x00100000)
 #define NS9750_ETH_EGCR1_ERXINIT	(0x00080000)
-#define NS9750_ETH_EGCR1_PHY_MODE_MA  	(0x0000C000)
-#define NS9750_ETH_EGCR1_PHY_MODE_MII 	(0x00008000)
-#define NS9750_ETH_EGCR1_PHY_MODE_RMII 	(0x00004000)
-#define NS9750_ETH_EGCR1_RXCINV	 	(0x00001000)
-#define NS9750_ETH_EGCR1_TXCINV	 	(0x00000800)
+#define NS9750_ETH_EGCR1_PHY_MODE_MA	(0x0000C000)
+#define NS9750_ETH_EGCR1_PHY_MODE_MII	(0x00008000)
+#define NS9750_ETH_EGCR1_PHY_MODE_RMII	(0x00004000)
+#define NS9750_ETH_EGCR1_RXCINV		(0x00001000)
+#define NS9750_ETH_EGCR1_TXCINV		(0x00000800)
 #define NS9750_ETH_EGCR1_RXALIGN	(0x00000400)
-#define NS9750_ETH_EGCR1_MAC_HRST 	(0x00000200)
-#define NS9750_ETH_EGCR1_ITXA	 	(0x00000100)
+#define NS9750_ETH_EGCR1_MAC_HRST	(0x00000200)
+#define NS9750_ETH_EGCR1_ITXA		(0x00000100)
 
 #define NS9750_ETH_EGCR2_TPTV_MA	(0xFFFF0000)
 #define NS9750_ETH_EGCR2_TPCF		(0x00000040)
@@ -116,10 +116,10 @@
 #define NS9750_ETH_EGCR2_CLRCNT		(0x00000002)
 #define NS9750_ETH_EGCR2_STEN		(0x00000001)
 
-#define NS9750_ETH_EGSR_RXINIT	 	(0x00100000)
-#define NS9750_ETH_EGSR_TXFIFONF 	(0x00080000)
-#define NS9750_ETH_EGSR_TXFIFOH	 	(0x00040000)
-#define NS9750_ETH_EGSR_TXFIFOE	 	(0x00010000)
+#define NS9750_ETH_EGSR_RXINIT		(0x00100000)
+#define NS9750_ETH_EGSR_TXFIFONF	(0x00080000)
+#define NS9750_ETH_EGSR_TXFIFOH		(0x00040000)
+#define NS9750_ETH_EGSR_TXFIFOE		(0x00010000)
 
 #define NS9750_ETH_FIFOTXS_ALL		(0x00000055)
 #define NS9750_ETH_FIFOTXS_3		(0x000000d5)
@@ -127,116 +127,116 @@
 #define NS9750_ETH_FIFOTXS_1		(0x0000000D)
 #define NS9750_ETH_FIFOTXS_0		(0x00000003)
 
-#define NS9750_ETH_ETSR_TXOK	 	(0x00008000)
-#define NS9750_ETH_ETSR_TXBR	 	(0x00004000)
-#define NS9750_ETH_ETSR_TXMC	 	(0x00002000)
-#define NS9750_ETH_ETSR_TXAL	 	(0x00001000)
-#define NS9750_ETH_ETSR_TXAED	 	(0x00000800)
-#define NS9750_ETH_ETSR_TXAEC	 	(0x00000400)
-#define NS9750_ETH_ETSR_TXAUR	 	(0x00000200)
-#define NS9750_ETH_ETSR_TXAJ	 	(0x00000100)
-#define NS9750_ETH_ETSR_TXDEF	 	(0x00000040)
-#define NS9750_ETH_ETSR_TXCRC	 	(0x00000020)
-#define NS9750_ETH_ETSR_TXCOLC   	(0x0000000F)
+#define NS9750_ETH_ETSR_TXOK		(0x00008000)
+#define NS9750_ETH_ETSR_TXBR		(0x00004000)
+#define NS9750_ETH_ETSR_TXMC		(0x00002000)
+#define NS9750_ETH_ETSR_TXAL		(0x00001000)
+#define NS9750_ETH_ETSR_TXAED		(0x00000800)
+#define NS9750_ETH_ETSR_TXAEC		(0x00000400)
+#define NS9750_ETH_ETSR_TXAUR		(0x00000200)
+#define NS9750_ETH_ETSR_TXAJ		(0x00000100)
+#define NS9750_ETH_ETSR_TXDEF		(0x00000040)
+#define NS9750_ETH_ETSR_TXCRC		(0x00000020)
+#define NS9750_ETH_ETSR_TXCOLC		(0x0000000F)
 
 #define NS9750_ETH_ERSR_RXSIZE_MA	(0x0FFF0000)
-#define NS9750_ETH_ERSR_RXCE	 	(0x00008000)
-#define NS9750_ETH_ERSR_RXDV	 	(0x00004000)
-#define NS9750_ETH_ERSR_RXOK	 	(0x00002000)
-#define NS9750_ETH_ERSR_RXBR	 	(0x00001000)
-#define NS9750_ETH_ERSR_RXMC	 	(0x00000800)
-#define NS9750_ETH_ERSR_RXCRC	 	(0x00000400)
-#define NS9750_ETH_ERSR_RXDR	 	(0x00000200)
-#define NS9750_ETH_ERSR_RXCV	 	(0x00000100)
-#define NS9750_ETH_ERSR_RXSHT	 	(0x00000040)
-
-#define NS9750_ETH_MAC1_SRST	 	(0x00008000)
-#define NS9750_ETH_MAC1_SIMMRST	 	(0x00004000)
-#define NS9750_ETH_MAC1_RPEMCSR	 	(0x00000800)
-#define NS9750_ETH_MAC1_RPERFUN	 	(0x00000400)
-#define NS9750_ETH_MAC1_RPEMCST	 	(0x00000200)
-#define NS9750_ETH_MAC1_RPETFUN	 	(0x00000100)
-#define NS9750_ETH_MAC1_LOOPBK	 	(0x00000010)
-#define NS9750_ETH_MAC1_TXFLOW	 	(0x00000008)
-#define NS9750_ETH_MAC1_RXFLOW	 	(0x00000004)
-#define NS9750_ETH_MAC1_PALLRX	 	(0x00000002)
-#define NS9750_ETH_MAC1_RXEN	 	(0x00000001)
-
-#define NS9750_ETH_MAC2_EDEFER	 	(0x00004000)
-#define NS9750_ETH_MAC2_BACKP	 	(0x00002000)
-#define NS9750_ETH_MAC2_NOBO	 	(0x00001000)
-#define NS9750_ETH_MAC2_LONGP	 	(0x00000200)
-#define NS9750_ETH_MAC2_PUREP	 	(0x00000100)
-#define NS9750_ETH_MAC2_AUTOP	 	(0x00000080)
-#define NS9750_ETH_MAC2_VLANP	 	(0x00000040)
-#define NS9750_ETH_MAC2_PADEN  	 	(0x00000020)
-#define NS9750_ETH_MAC2_CRCEN	 	(0x00000010)
-#define NS9750_ETH_MAC2_DELCRC	 	(0x00000008)
-#define NS9750_ETH_MAC2_HUGE	 	(0x00000004)
-#define NS9750_ETH_MAC2_FLENC	 	(0x00000002)
-#define NS9750_ETH_MAC2_FULLD	 	(0x00000001)
-
-#define NS9750_ETH_IPGT_MA	 	(0x0000007F)
-
-#define NS9750_ETH_IPGR_IPGR1	 	(0x00007F00)
-#define NS9750_ETH_IPGR_IPGR2	 	(0x0000007F)
-
-#define NS9750_ETH_CLRT_CWIN	 	(0x00003F00)
-#define	NS9750_ETH_CLRT_RETX	 	(0x0000000F)
-
-#define NS9750_ETH_MAXF_MAXF	 	(0x0000FFFF)
-
-#define NS9750_ETH_SUPP_RPERMII	 	(0x00008000)
-#define NS9750_ETH_SUPP_SPEED  	 	(0x00000080)
-
-#define NS9750_ETH_TEST_TBACK	 	(0x00000004)
-#define NS9750_ETH_TEST_TPAUSE	 	(0x00000002)
-#define NS9750_ETH_TEST_SPQ	 	(0x00000001)
-
-#define NS9750_ETH_MCFG_RMIIM	 	(0x00008000)
-#define NS9750_ETH_MCFG_CLKS_MA	 	(0x0000001C)
-#define NS9750_ETH_MCFG_CLKS_4	 	(0x00000004)
-#define NS9750_ETH_MCFG_CLKS_6	 	(0x00000008)
-#define NS9750_ETH_MCFG_CLKS_8	 	(0x0000000C)
-#define NS9750_ETH_MCFG_CLKS_10	 	(0x00000010)
-#define NS9750_ETH_MCFG_CLKS_20	 	(0x00000014)
-#define NS9750_ETH_MCFG_CLKS_30	 	(0x00000018)
-#define NS9750_ETH_MCFG_CLKS_40	 	(0x0000001C)
-#define NS9750_ETH_MCFG_SPRE	 	(0x00000002)
-#define NS9750_ETH_MCFG_SCANI	 	(0x00000001)
-
-#define NS9750_ETH_MCMD_SCAN	 	(0x00000002)
-#define NS9750_ETH_MCMD_READ	 	(0x00000001)
-
-#define NS9750_ETH_MADR_DADR_MA	 	(0x00001F00)
-#define NS9750_ETH_MADR_RADR_MA	 	(0x0000001F)
-
-#define NS9750_ETH_MWTD_MA	 	(0x0000FFFF)
-
-#define NS9750_ETH_MRRD_MA	 	(0x0000FFFF)
+#define NS9750_ETH_ERSR_RXCE		(0x00008000)
+#define NS9750_ETH_ERSR_RXDV		(0x00004000)
+#define NS9750_ETH_ERSR_RXOK		(0x00002000)
+#define NS9750_ETH_ERSR_RXBR		(0x00001000)
+#define NS9750_ETH_ERSR_RXMC		(0x00000800)
+#define NS9750_ETH_ERSR_RXCRC		(0x00000400)
+#define NS9750_ETH_ERSR_RXDR		(0x00000200)
+#define NS9750_ETH_ERSR_RXCV		(0x00000100)
+#define NS9750_ETH_ERSR_RXSHT		(0x00000040)
+
+#define NS9750_ETH_MAC1_SRST		(0x00008000)
+#define NS9750_ETH_MAC1_SIMMRST		(0x00004000)
+#define NS9750_ETH_MAC1_RPEMCSR		(0x00000800)
+#define NS9750_ETH_MAC1_RPERFUN		(0x00000400)
+#define NS9750_ETH_MAC1_RPEMCST		(0x00000200)
+#define NS9750_ETH_MAC1_RPETFUN		(0x00000100)
+#define NS9750_ETH_MAC1_LOOPBK		(0x00000010)
+#define NS9750_ETH_MAC1_TXFLOW		(0x00000008)
+#define NS9750_ETH_MAC1_RXFLOW		(0x00000004)
+#define NS9750_ETH_MAC1_PALLRX		(0x00000002)
+#define NS9750_ETH_MAC1_RXEN		(0x00000001)
+
+#define NS9750_ETH_MAC2_EDEFER		(0x00004000)
+#define NS9750_ETH_MAC2_BACKP		(0x00002000)
+#define NS9750_ETH_MAC2_NOBO		(0x00001000)
+#define NS9750_ETH_MAC2_LONGP		(0x00000200)
+#define NS9750_ETH_MAC2_PUREP		(0x00000100)
+#define NS9750_ETH_MAC2_AUTOP		(0x00000080)
+#define NS9750_ETH_MAC2_VLANP		(0x00000040)
+#define NS9750_ETH_MAC2_PADEN		(0x00000020)
+#define NS9750_ETH_MAC2_CRCEN		(0x00000010)
+#define NS9750_ETH_MAC2_DELCRC		(0x00000008)
+#define NS9750_ETH_MAC2_HUGE		(0x00000004)
+#define NS9750_ETH_MAC2_FLENC		(0x00000002)
+#define NS9750_ETH_MAC2_FULLD		(0x00000001)
+
+#define NS9750_ETH_IPGT_MA		(0x0000007F)
+
+#define NS9750_ETH_IPGR_IPGR1		(0x00007F00)
+#define NS9750_ETH_IPGR_IPGR2		(0x0000007F)
+
+#define NS9750_ETH_CLRT_CWIN		(0x00003F00)
+#define	NS9750_ETH_CLRT_RETX		(0x0000000F)
+
+#define NS9750_ETH_MAXF_MAXF		(0x0000FFFF)
+
+#define NS9750_ETH_SUPP_RPERMII		(0x00008000)
+#define NS9750_ETH_SUPP_SPEED		(0x00000080)
+
+#define NS9750_ETH_TEST_TBACK		(0x00000004)
+#define NS9750_ETH_TEST_TPAUSE		(0x00000002)
+#define NS9750_ETH_TEST_SPQ		(0x00000001)
+
+#define NS9750_ETH_MCFG_RMIIM		(0x00008000)
+#define NS9750_ETH_MCFG_CLKS_MA		(0x0000001C)
+#define NS9750_ETH_MCFG_CLKS_4		(0x00000004)
+#define NS9750_ETH_MCFG_CLKS_6		(0x00000008)
+#define NS9750_ETH_MCFG_CLKS_8		(0x0000000C)
+#define NS9750_ETH_MCFG_CLKS_10		(0x00000010)
+#define NS9750_ETH_MCFG_CLKS_20		(0x00000014)
+#define NS9750_ETH_MCFG_CLKS_30		(0x00000018)
+#define NS9750_ETH_MCFG_CLKS_40		(0x0000001C)
+#define NS9750_ETH_MCFG_SPRE		(0x00000002)
+#define NS9750_ETH_MCFG_SCANI		(0x00000001)
+
+#define NS9750_ETH_MCMD_SCAN		(0x00000002)
+#define NS9750_ETH_MCMD_READ		(0x00000001)
+
+#define NS9750_ETH_MADR_DADR_MA		(0x00001F00)
+#define NS9750_ETH_MADR_RADR_MA		(0x0000001F)
+
+#define NS9750_ETH_MWTD_MA		(0x0000FFFF)
+
+#define NS9750_ETH_MRRD_MA		(0x0000FFFF)
 
 #define NS9750_ETH_MIND_MIILF		(0x00000008)
 #define NS9750_ETH_MIND_NVALID		(0x00000004)
-#define NS9750_ETH_MIND_SCAN	 	(0x00000002)
-#define NS9750_ETH_MIND_BUSY	 	(0x00000001)
+#define NS9750_ETH_MIND_SCAN		(0x00000002)
+#define NS9750_ETH_MIND_BUSY		(0x00000001)
 
-#define NS9750_ETH_SA1_OCTET1_MA 	(0x0000FF00)
-#define NS9750_ETH_SA1_OCTET2_MA 	(0x000000FF)
+#define NS9750_ETH_SA1_OCTET1_MA	(0x0000FF00)
+#define NS9750_ETH_SA1_OCTET2_MA	(0x000000FF)
 
-#define NS9750_ETH_SA2_OCTET3_MA 	(0x0000FF00)
-#define NS9750_ETH_SA2_OCTET4_MA 	(0x000000FF)
+#define NS9750_ETH_SA2_OCTET3_MA	(0x0000FF00)
+#define NS9750_ETH_SA2_OCTET4_MA	(0x000000FF)
 
-#define NS9750_ETH_SA3_OCTET5_MA 	(0x0000FF00)
-#define NS9750_ETH_SA3_OCTET6_MA 	(0x000000FF)
+#define NS9750_ETH_SA3_OCTET5_MA	(0x0000FF00)
+#define NS9750_ETH_SA3_OCTET6_MA	(0x000000FF)
 
-#define NS9750_ETH_SAFR_PRO	 	(0x00000008)
-#define NS9750_ETH_SAFR_PRM	 	(0x00000004)
-#define NS9750_ETH_SAFR_PRA	 	(0x00000002)
-#define NS9750_ETH_SAFR_BROAD	 	(0x00000001)
+#define NS9750_ETH_SAFR_PRO		(0x00000008)
+#define NS9750_ETH_SAFR_PRM		(0x00000004)
+#define NS9750_ETH_SAFR_PRA		(0x00000002)
+#define NS9750_ETH_SAFR_BROAD		(0x00000001)
 
-#define NS9750_ETH_HT1_MA	 	(0x0000FFFF)
+#define NS9750_ETH_HT1_MA		(0x0000FFFF)
 
-#define NS9750_ETH_HT2_MA	 	(0x0000FFFF)
+#define NS9750_ETH_HT2_MA		(0x0000FFFF)
 
 /* also valid for EINTREN */
 #define NS9750_ETH_EINTR_RXOVL_DATA	(0x02000000)
@@ -254,7 +254,7 @@
 #define NS9750_ETH_EINTR_TXBUFC		(0x00000010)
 #define NS9750_ETH_EINTR_TXBUFNR	(0x00000008)
 #define NS9750_ETH_EINTR_TXDONE		(0x00000004)
-#define NS9750_ETH_EINTR_TXERR 		(0x00000002)
+#define NS9750_ETH_EINTR_TXERR		(0x00000002)
 #define NS9750_ETH_EINTR_TXIDLE		(0x00000001)
 #define NS9750_ETH_EINTR_RX_MA	\
 	(NS9750_ETH_EINTR_RXOVL_DATA | \
@@ -289,7 +289,7 @@
 #define NS9750_ETH_RXFREE_A		(0x00000001)
 
 #ifndef NS9750_ETH_PHY_ADDRESS
-# define NS9750_ETH_PHY_ADDRESS	 	(0x0001) /* suitable for UNC20 */
+# define NS9750_ETH_PHY_ADDRESS		(0x0001) /* suitable for UNC20 */
 #endif /* NETARM_ETH_PHY_ADDRESS */
 
 #endif /* CONFIG_DRIVER_NS9750_ETHERNET */
diff --git a/include/ns9750_mem.h b/include/ns9750_mem.h
index 44c8ddcdd6..666e4127c8 100644
--- a/include/ns9750_mem.h
+++ b/include/ns9750_mem.h
@@ -35,23 +35,23 @@
 
 /* the register addresses */
 
-#define NS9750_MEM_CTRL     		(0x0000)
-#define NS9750_MEM_STATUS     		(0x0004)
-#define NS9750_MEM_CFG     		(0x0008)
-#define NS9750_MEM_DYN_CTRL 		(0x0020)
-#define NS9750_MEM_DYN_REFRESH 		(0x0024)
+#define NS9750_MEM_CTRL			(0x0000)
+#define NS9750_MEM_STATUS		(0x0004)
+#define NS9750_MEM_CFG			(0x0008)
+#define NS9750_MEM_DYN_CTRL		(0x0020)
+#define NS9750_MEM_DYN_REFRESH		(0x0024)
 #define NS9750_MEM_DYN_READ_CFG		(0x0028)
-#define NS9750_MEM_DYN_TRP     		(0x0030)
-#define NS9750_MEM_DYN_TRAS    		(0x0034)
-#define NS9750_MEM_DYN_TSREX   		(0x0038)
-#define NS9750_MEM_DYN_TAPR   		(0x003C)
-#define NS9750_MEM_DYN_TDAL    		(0x0040)
-#define NS9750_MEM_DYN_TWR     		(0x0044)
-#define NS9750_MEM_DYN_TRC     		(0x0048)
-#define NS9750_MEM_DYN_TRFC    		(0x004C)
-#define NS9750_MEM_DYN_TXSR    		(0x0050)
-#define NS9750_MEM_DYN_TRRD    		(0x0054)
-#define NS9750_MEM_DYN_TMRD    		(0x0058)
+#define NS9750_MEM_DYN_TRP		(0x0030)
+#define NS9750_MEM_DYN_TRAS		(0x0034)
+#define NS9750_MEM_DYN_TSREX		(0x0038)
+#define NS9750_MEM_DYN_TAPR		(0x003C)
+#define NS9750_MEM_DYN_TDAL		(0x0040)
+#define NS9750_MEM_DYN_TWR		(0x0044)
+#define NS9750_MEM_DYN_TRC		(0x0048)
+#define NS9750_MEM_DYN_TRFC		(0x004C)
+#define NS9750_MEM_DYN_TXSR		(0x0050)
+#define NS9750_MEM_DYN_TRRD		(0x0054)
+#define NS9750_MEM_DYN_TMRD		(0x0058)
 #define NS9750_MEM_STAT_EXT_WAIT	(0x0080)
 #define NS9750_MEM_DYN_CFG_BASE		(0x0100)
 #define NS9750_MEM_DYN_RAS_CAS_BASE	(0x0104)
@@ -102,7 +102,7 @@
 #define NS9750_MEM_DYN_REFRESH_MA	(0x000007FF)
 
 #define NS9750_MEM_DYN_READ_CFG_MA	(0x00000003)
-#define NS9750_MEM_DYN_READ_CFG_DELAY0 	(0x00000001)
+#define NS9750_MEM_DYN_READ_CFG_DELAY0	(0x00000001)
 #define NS9750_MEM_DYN_READ_CFG_DELAY1  (0x00000002)
 #define NS9750_MEM_DYN_READ_CFG_DELAY2	(0x00000003)
 
@@ -137,13 +137,13 @@
 #define NS9750_MEM_DYN_CFG_MD		(0x00000018)
 
 #define NS9750_MEM_DYN_RAS_CAS_CAS_MA	(0x00000300)
-#define NS9750_MEM_DYN_RAS_CAS_CAS_1 	(0x00000100)
-#define NS9750_MEM_DYN_RAS_CAS_CAS_2 	(0x00000200)
-#define NS9750_MEM_DYN_RAS_CAS_CAS_3 	(0x00000300)
+#define NS9750_MEM_DYN_RAS_CAS_CAS_1	(0x00000100)
+#define NS9750_MEM_DYN_RAS_CAS_CAS_2	(0x00000200)
+#define NS9750_MEM_DYN_RAS_CAS_CAS_3	(0x00000300)
 #define NS9750_MEM_DYN_RAS_CAS_RAS_MA	(0x00000003)
 #define NS9750_MEM_DYN_RAS_CAS_RAS_1	(0x00000001)
-#define NS9750_MEM_DYN_RAS_CAS_RAS_2 	(0x00000002)
-#define NS9750_MEM_DYN_RAS_CAS_RAS_3 	(0x00000003)
+#define NS9750_MEM_DYN_RAS_CAS_RAS_2	(0x00000002)
+#define NS9750_MEM_DYN_RAS_CAS_RAS_3	(0x00000003)
 
 #define NS9750_MEM_STAT_CFG_PSMC	(0x00100000)
 #define NS9750_MEM_STAT_CFG_BSMC	(0x00080000)
@@ -153,7 +153,7 @@
 #define NS9750_MEM_STAT_CFG_PM		(0x00000008)
 #define NS9750_MEM_STAT_CFG_MW_MA	(0x00000003)
 #define NS9750_MEM_STAT_CFG_MW_8	(0x00000000)
-#define NS9750_MEM_STAT_CFG_MW_16      	(0x00000001)
+#define NS9750_MEM_STAT_CFG_MW_16	(0x00000001)
 #define NS9750_MEM_STAT_CFG_MW_32	(0x00000002)
 
 #define NS9750_MEM_STAT_WAIT_WEN_MA	(0x0000000F)
diff --git a/include/ns9750_ser.h b/include/ns9750_ser.h
index e6ff3e1727..b5c297e436 100644
--- a/include/ns9750_ser.h
+++ b/include/ns9750_ser.h
@@ -75,7 +75,7 @@
 #define NS9750_SER_CTRL_A_ERXDMA	(0x00000100)
 #define NS9750_SER_CTRL_A_RIC_MA	(0x000000E0)
 #define NS9750_SER_CTRL_A_TIC_MA	(0x0000001E)
-#define NS9750_SER_CTRL_A_ETXDMA 	(0x00000001)
+#define NS9750_SER_CTRL_A_ETXDMA	(0x00000001)
 
 /* control B register */
 
@@ -130,21 +130,21 @@
 #define NS9750_SER_STAT_A_TEMPTY	(0x00000001)
 
 #define NS9750_SER_STAT_A_RX_COND_ERR ( NS9750_SER_STAT_A_RFE | \
-		 		        NS9750_SER_STAT_A_ROVER | \
+				        NS9750_SER_STAT_A_ROVER | \
 				        NS9750_SER_STAT_A_RPE )
 #define NS9750_SER_STAT_A_RX_COND_ALL ( NS9750_SER_STAT_A_RX_COND_ERR | \
 				        NS9750_SER_STAT_A_RBRK | \
 				        NS9750_SER_STAT_A_RRDY | \
-				    	NS9750_SER_STAT_A_RHALF | \
-				    	NS9750_SER_STAT_A_RBC | \
-				    	NS9750_SER_STAT_A_DCDI | \
-				    	NS9750_SER_STAT_A_RII | \
-				    	NS9750_SER_STAT_A_DSRI | \
-				    	NS9750_SER_STAT_A_CTSI )
+					NS9750_SER_STAT_A_RHALF | \
+					NS9750_SER_STAT_A_RBC | \
+					NS9750_SER_STAT_A_DCDI | \
+					NS9750_SER_STAT_A_RII | \
+					NS9750_SER_STAT_A_DSRI | \
+					NS9750_SER_STAT_A_CTSI )
 #define NS9750_SER_STAT_A_TX_COND_ALL ( NS9750_SER_STAT_A_TRDY | \
 				        NS9750_SER_STAT_A_THALF | \
 				        NS9750_SER_STAT_A_TBC | \
-				    	NS9750_SER_STAT_A_TEMPTY )
+					NS9750_SER_STAT_A_TEMPTY )
 /* bit rate register */
 
 #define NS9750_SER_BITRATE_EBIT		 (0x80000000)
@@ -161,13 +161,13 @@
 #define NS9750_SER_BITRATE_TXCINV	 (0x00800000)
 #define NS9750_SER_BITRATE_RXCINV	 (0x00400000)
 #define NS9750_SER_BITRATE_TCDR_MA	 (0x00180000)
-#define NS9750_SER_BITRATE_TCDR_1 	 (0x00000000)
-#define NS9750_SER_BITRATE_TCDR_8 	 (0x00080000)
+#define NS9750_SER_BITRATE_TCDR_1	 (0x00000000)
+#define NS9750_SER_BITRATE_TCDR_8	 (0x00080000)
 #define NS9750_SER_BITRATE_TCDR_16	 (0x00100000)
 #define NS9750_SER_BITRATE_TCDR_32	 (0x00180000)
 #define NS9750_SER_BITRATE_RCDR_MA	 (0x00070000)
-#define NS9750_SER_BITRATE_RCDR_1 	 (0x00000000)
-#define NS9750_SER_BITRATE_RCDR_8 	 (0x00020000)
+#define NS9750_SER_BITRATE_RCDR_1	 (0x00000000)
+#define NS9750_SER_BITRATE_RCDR_8	 (0x00020000)
 #define NS9750_SER_BITRATE_RCDR_16	 (0x00040000)
 #define NS9750_SER_BITRATE_RCDR_32	 (0x00060000)
 #define NS9750_SER_BITRATE_TICS		 (0x00010000)
diff --git a/include/ns9750_sys.h b/include/ns9750_sys.h
index c563cada09..f1dc2b2382 100644
--- a/include/ns9750_sys.h
+++ b/include/ns9750_sys.h
@@ -38,9 +38,9 @@
 #define NS9750_SYS_AHB_GEN		(0x0000)
 #define NS9750_SYS_BRC_BASE		(0x0004)
 #define NS9750_SYS_AHB_TIMEOUT		(0x0014)
-#define NS9750_SYS_AHB_ERROR1   	(0x0018)
-#define NS9750_SYS_AHB_ERROR2   	(0x001C)
-#define NS9750_SYS_AHB_MON    		(0x0020)
+#define NS9750_SYS_AHB_ERROR1		(0x0018)
+#define NS9750_SYS_AHB_ERROR2		(0x001C)
+#define NS9750_SYS_AHB_MON		(0x0020)
 #define NS9750_SYS_TIMER_COUNT_BASE	(0x0044)
 #define NS9750_SYS_TIMER_READ_BASE	(0x0084)
 #define NS9750_SYS_INT_VEC_ADR_BASE	(0x00C4)
@@ -120,27 +120,27 @@
 /* need to be n*8bit to Int Level */
 
 #define NS9750_SYS_INT_CFG_IE		(0x00000080)
-#define NS9750_SYS_INT_CFG_IT    	(0x00000020)
+#define NS9750_SYS_INT_CFG_IT		(0x00000020)
 #define NS9750_SYS_INT_CFG_IAD_MA	(0x0000001F)
 
-#define NS9750_SYS_TIMER_INT_STAT_MA 	(0x0000FFFF)
+#define NS9750_SYS_TIMER_INT_STAT_MA	(0x0000FFFF)
 
 #define NS9750_SYS_SW_WDOG_CFG_SWWE	(0x00000080)
 #define NS9750_SYS_SW_WDOG_CFG_SWWI	(0x00000020)
 #define NS9750_SYS_SW_WDOG_CFG_SWWIC	(0x00000010)
 #define NS9750_SYS_SW_WDOG_CFG_SWTCS_MA	(0x00000007)
-#define NS9750_SYS_SW_WDOG_CFG_SWTCS_2 	(0x00000000)
-#define NS9750_SYS_SW_WDOG_CFG_SWTCS_4 	(0x00000001)
-#define NS9750_SYS_SW_WDOG_CFG_SWTCS_8 	(0x00000002)
+#define NS9750_SYS_SW_WDOG_CFG_SWTCS_2	(0x00000000)
+#define NS9750_SYS_SW_WDOG_CFG_SWTCS_4	(0x00000001)
+#define NS9750_SYS_SW_WDOG_CFG_SWTCS_8	(0x00000002)
 #define NS9750_SYS_SW_WDOG_CFG_SWTCS_16	(0x00000003)
 #define NS9750_SYS_SW_WDOG_CFG_SWTCS_32	(0x00000004)
 #define NS9750_SYS_SW_WDOG_CFG_SWTCS_64	(0x00000005)
 
 #define NS9750_SYS_CLOCK_LPCS_MA	(0x00000380)
-#define NS9750_SYS_CLOCK_LPCS_1 	(0x00000000)
-#define NS9750_SYS_CLOCK_LPCS_2 	(0x00000080)
-#define NS9750_SYS_CLOCK_LPCS_4 	(0x00000100)
-#define NS9750_SYS_CLOCK_LPCS_8 	(0x00000180)
+#define NS9750_SYS_CLOCK_LPCS_1		(0x00000000)
+#define NS9750_SYS_CLOCK_LPCS_2		(0x00000080)
+#define NS9750_SYS_CLOCK_LPCS_4		(0x00000100)
+#define NS9750_SYS_CLOCK_LPCS_8		(0x00000180)
 #define NS9750_SYS_CLOCK_LPCS_EXT	(0x00000200)
 #define NS9750_SYS_CLOCK_BBC		(0x00000040)
 #define NS9750_SYS_CLOCK_LCC		(0x00000020)
@@ -185,22 +185,22 @@
 #define NS9750_SYS_PLL_CPCC_MA		(0x00000060)
 #define NS9750_SYS_PLL_NDSW_MA		(0x0000001F)
 
-#define NS9750_SYS_ACT_INT_STAT_MA 	(0x0000FFFF)
+#define NS9750_SYS_ACT_INT_STAT_MA	(0x0000FFFF)
 
 #define NS9750_SYS_TIMER_CTRL_TEN	(0x00008000)
 #define NS9750_SYS_TIMER_CTRL_INTC	(0x00000200)
 #define NS9750_SYS_TIMER_CTRL_TLCS_MA	(0x000001C0)
-#define NS9750_SYS_TIMER_CTRL_TLCS_1 	(0x00000000)
-#define NS9750_SYS_TIMER_CTRL_TLCS_2 	(0x00000040)
-#define NS9750_SYS_TIMER_CTRL_TLCS_4 	(0x00000080)
-#define NS9750_SYS_TIMER_CTRL_TLCS_8 	(0x000000C0)
+#define NS9750_SYS_TIMER_CTRL_TLCS_1	(0x00000000)
+#define NS9750_SYS_TIMER_CTRL_TLCS_2	(0x00000040)
+#define NS9750_SYS_TIMER_CTRL_TLCS_4	(0x00000080)
+#define NS9750_SYS_TIMER_CTRL_TLCS_8	(0x000000C0)
 #define NS9750_SYS_TIMER_CTRL_TLCS_16	(0x00000100)
 #define NS9750_SYS_TIMER_CTRL_TLCS_32	(0x00000140)
 #define NS9750_SYS_TIMER_CTRL_TLCS_64	(0x00000180)
 #define NS9750_SYS_TIMER_CTRL_TLCS_EXT	(0x000001C0)
 #define NS9750_SYS_TIMER_CTRL_TM_MA	(0x00000030)
-#define NS9750_SYS_TIMER_CTRL_TM_INT  	(0x00000000)
-#define NS9750_SYS_TIMER_CTRL_TM_LOW 	(0x00000010)
+#define NS9750_SYS_TIMER_CTRL_TM_INT	(0x00000000)
+#define NS9750_SYS_TIMER_CTRL_TM_LOW	(0x00000010)
 #define NS9750_SYS_TIMER_CTRL_TM_HIGH	(0x00000020)
 #define NS9750_SYS_TIMER_CTRL_INTS	(0x00000008)
 #define NS9750_SYS_TIMER_CTRL_UDS	(0x00000004)
diff --git a/include/pc_keyb.h b/include/pc_keyb.h
index ab51703e1a..5ba99e35a2 100644
--- a/include/pc_keyb.h
+++ b/include/pc_keyb.h
@@ -68,14 +68,14 @@ extern unsigned char aux_device_present;
 /*
  *	Status Register Bits
  */
-#define KBD_STAT_OBF 		0x01	/* Keyboard output buffer full */
-#define KBD_STAT_IBF 		0x02	/* Keyboard input buffer full */
+#define KBD_STAT_OBF		0x01	/* Keyboard output buffer full */
+#define KBD_STAT_IBF		0x02	/* Keyboard input buffer full */
 #define KBD_STAT_SELFTEST	0x04	/* Self test successful */
 #define KBD_STAT_CMD		0x08	/* Last write was a command write (0=data) */
 #define KBD_STAT_UNLOCKED	0x10	/* Zero if keyboard locked */
 #define KBD_STAT_MOUSE_OBF	0x20	/* Mouse output buffer full */
-#define KBD_STAT_GTO 		0x40	/* General receive/xmit timeout */
-#define KBD_STAT_PERR 		0x80	/* Parity error */
+#define KBD_STAT_GTO		0x40	/* General receive/xmit timeout */
+#define KBD_STAT_PERR		0x80	/* Parity error */
 
 #define AUX_STAT_OBF (KBD_STAT_OBF | KBD_STAT_MOUSE_OBF)
 
@@ -84,11 +84,11 @@ extern unsigned char aux_device_present;
  */
 #define KBD_MODE_KBD_INT	0x01	/* Keyboard data generate IRQ1 */
 #define KBD_MODE_MOUSE_INT	0x02	/* Mouse data generate IRQ12 */
-#define KBD_MODE_SYS 		0x04	/* The system flag (?) */
+#define KBD_MODE_SYS		0x04	/* The system flag (?) */
 #define KBD_MODE_NO_KEYLOCK	0x08	/* The keylock doesn't affect the keyboard if set */
 #define KBD_MODE_DISABLE_KBD	0x10	/* Disable keyboard interface */
 #define KBD_MODE_DISABLE_MOUSE	0x20	/* Disable mouse interface */
-#define KBD_MODE_KCC 		0x40	/* Scan code conversion to PC format */
+#define KBD_MODE_KCC		0x40	/* Scan code conversion to PC format */
 #define KBD_MODE_RFU		0x80
 
 /*
diff --git a/include/post.h b/include/post.h
index ee07d2caa2..123623f5c8 100644
--- a/include/post.h
+++ b/include/post.h
@@ -43,6 +43,7 @@
 #define POST_PREREL             0x1000  /* test runs before relocation */
 
 #define POST_CRITICAL		0x2000	/* Use failbootcmd if test failed */
+#define POST_STOP		0x4000	/* Interrupt POST sequence on fail */
 
 #define POST_MEM		(POST_RAM | POST_ROM)
 #define POST_ALWAYS		(POST_NORMAL	| \
@@ -94,7 +95,7 @@ extern int post_hotkeys_pressed(void);
 #define CFG_POST_SPR		0x00000400
 #define CFG_POST_SYSMON		0x00000800
 #define CFG_POST_DSP		0x00001000
-#define CFG_POST_CODEC		0x00002000
+#define CFG_POST_OCM		0x00002000
 #define CFG_POST_FPU		0x00004000
 #define CFG_POST_ECC		0x00008000
 #define CFG_POST_BSPEC1		0x00010000
@@ -102,6 +103,7 @@ extern int post_hotkeys_pressed(void);
 #define CFG_POST_BSPEC3		0x00040000
 #define CFG_POST_BSPEC4		0x00080000
 #define CFG_POST_BSPEC5		0x00100000
+#define CFG_POST_CODEC		0x00200000
 
 #endif /* CONFIG_POST */
 
diff --git a/include/ppc405.h b/include/ppc405.h
index 37b121c3dc..d953378c73 100644
--- a/include/ppc405.h
+++ b/include/ppc405.h
@@ -1,22 +1,22 @@
 /*----------------------------------------------------------------------------+
 |
-|       This source code has been made available to you by IBM on an AS-IS
-|       basis.  Anyone receiving this source is licensed under IBM
-|       copyrights to use it in any way he or she deems fit, including
-|       copying it, modifying it, compiling it, and redistributing it either
-|       with or without modifications.  No license under IBM patents or
-|       patent applications is to be implied by the copyright license.
+|	This source code has been made available to you by IBM on an AS-IS
+|	basis.	Anyone receiving this source is licensed under IBM
+|	copyrights to use it in any way he or she deems fit, including
+|	copying it, modifying it, compiling it, and redistributing it either
+|	with or without modifications.	No license under IBM patents or
+|	patent applications is to be implied by the copyright license.
 |
-|       Any user of this software should understand that IBM cannot provide
-|       technical support for this software and will not be responsible for
-|       any consequences resulting from the use of this software.
+|	Any user of this software should understand that IBM cannot provide
+|	technical support for this software and will not be responsible for
+|	any consequences resulting from the use of this software.
 |
-|       Any person who transfers this source code or any derivative work
-|       must include the IBM copyright notice, this paragraph, and the
-|       preceding two paragraphs in the transferred software.
+|	Any person who transfers this source code or any derivative work
+|	must include the IBM copyright notice, this paragraph, and the
+|	preceding two paragraphs in the transferred software.
 |
-|       COPYRIGHT   I B M   CORPORATION 1999
-|       LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
+|	COPYRIGHT   I B M   CORPORATION 1999
+|	LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
 +----------------------------------------------------------------------------*/
 
 #ifndef	__PPC405_H__
@@ -31,8 +31,8 @@
 /*--------------------------------------------------------------------- */
 /* Special Purpose Registers						*/
 /*--------------------------------------------------------------------- */
-	#define  srr2  0x3de      /* save/restore register 2 */
-	#define  srr3  0x3df      /* save/restore register 3 */
+	#define  srr2  0x3de	  /* save/restore register 2 */
+	#define  srr3  0x3df	  /* save/restore register 3 */
 
 	/*
 	 * 405 does not really have CSRR0/1 but SRR2/3 are used during critical
@@ -42,46 +42,46 @@
 	#define  csrr0 srr2
 	#define  csrr1 srr3
 
-	#define  dbsr  0x3f0      /* debug status register */
-	#define  dbcr0 0x3f2      /* debug control register 0 */
-	#define  dbcr1 0x3bd      /* debug control register 1 */
-	#define  iac1  0x3f4      /* instruction address comparator 1 */
-	#define  iac2  0x3f5      /* instruction address comparator 2 */
-	#define  iac3  0x3b4      /* instruction address comparator 3 */
-	#define  iac4  0x3b5      /* instruction address comparator 4 */
-	#define  dac1  0x3f6      /* data address comparator 1 */
-	#define  dac2  0x3f7      /* data address comparator 2 */
-	#define  dccr  0x3fa      /* data cache control register */
-	#define  iccr  0x3fb      /* instruction cache control register */
-	#define  esr   0x3d4      /* execption syndrome register */
-	#define  dear  0x3d5      /* data exeption address register */
-	#define  evpr  0x3d6      /* exeption vector prefix register */
-	#define  tsr   0x3d8      /* timer status register */
-	#define  tcr   0x3da      /* timer control register */
-	#define  pit   0x3db      /* programmable interval timer */
-	#define  sgr   0x3b9      /* storage guarded reg      */
-	#define  dcwr  0x3ba      /* data cache write-thru reg*/
-	#define  sler  0x3bb      /* storage little-endian reg */
-	#define  cdbcr 0x3d7      /* cache debug cntrl reg    */
-	#define  icdbdr 0x3d3     /* instr cache dbug data reg*/
-	#define  ccr0  0x3b3      /* core configuration register */
-	#define  dvc1  0x3b6      /* data value compare register 1 */
-	#define  dvc2  0x3b7      /* data value compare register 2 */
-	#define  pid   0x3b1      /* process ID */
-	#define  su0r  0x3bc      /* storage user-defined register 0 */
-	#define  zpr   0x3b0      /* zone protection regsiter */
-
-	#define  tbl   0x11c      /* time base lower - privileged write */
-	#define  tbu   0x11d      /* time base upper - privileged write */
-
-	#define  sprg4r 0x104     /* Special purpose general 4 - read only */
-	#define  sprg5r 0x105     /* Special purpose general 5 - read only */
-	#define  sprg6r 0x106     /* Special purpose general 6 - read only */
-	#define  sprg7r 0x107     /* Special purpose general 7 - read only */
-	#define  sprg4w 0x114     /* Special purpose general 4 - write only */
-	#define  sprg5w 0x115     /* Special purpose general 5 - write only */
-	#define  sprg6w 0x116     /* Special purpose general 6 - write only */
-	#define  sprg7w 0x117     /* Special purpose general 7 - write only */
+	#define  dbsr  0x3f0	  /* debug status register */
+	#define  dbcr0 0x3f2	  /* debug control register 0 */
+	#define  dbcr1 0x3bd	  /* debug control register 1 */
+	#define  iac1  0x3f4	  /* instruction address comparator 1 */
+	#define  iac2  0x3f5	  /* instruction address comparator 2 */
+	#define  iac3  0x3b4	  /* instruction address comparator 3 */
+	#define  iac4  0x3b5	  /* instruction address comparator 4 */
+	#define  dac1  0x3f6	  /* data address comparator 1 */
+	#define  dac2  0x3f7	  /* data address comparator 2 */
+	#define  dccr  0x3fa	  /* data cache control register */
+	#define  iccr  0x3fb	  /* instruction cache control register */
+	#define  esr   0x3d4	  /* execption syndrome register */
+	#define  dear  0x3d5	  /* data exeption address register */
+	#define  evpr  0x3d6	  /* exeption vector prefix register */
+	#define  tsr   0x3d8	  /* timer status register */
+	#define  tcr   0x3da	  /* timer control register */
+	#define  pit   0x3db	  /* programmable interval timer */
+	#define  sgr   0x3b9	  /* storage guarded reg      */
+	#define  dcwr  0x3ba	  /* data cache write-thru reg*/
+	#define  sler  0x3bb	  /* storage little-endian reg */
+	#define  cdbcr 0x3d7	  /* cache debug cntrl reg    */
+	#define  icdbdr 0x3d3	  /* instr cache dbug data reg*/
+	#define  ccr0  0x3b3	  /* core configuration register */
+	#define  dvc1  0x3b6	  /* data value compare register 1 */
+	#define  dvc2  0x3b7	  /* data value compare register 2 */
+	#define  pid   0x3b1	  /* process ID */
+	#define  su0r  0x3bc	  /* storage user-defined register 0 */
+	#define  zpr   0x3b0	  /* zone protection regsiter */
+
+	#define  tbl   0x11c	  /* time base lower - privileged write */
+	#define  tbu   0x11d	  /* time base upper - privileged write */
+
+	#define  sprg4r 0x104	  /* Special purpose general 4 - read only */
+	#define  sprg5r 0x105	  /* Special purpose general 5 - read only */
+	#define  sprg6r 0x106	  /* Special purpose general 6 - read only */
+	#define  sprg7r 0x107	  /* Special purpose general 7 - read only */
+	#define  sprg4w 0x114	  /* Special purpose general 4 - write only */
+	#define  sprg5w 0x115	  /* Special purpose general 5 - write only */
+	#define  sprg6w 0x116	  /* Special purpose general 6 - write only */
+	#define  sprg7w 0x117	  /* Special purpose general 7 - write only */
 
 /******************************************************************************
  * Special for PPC405GP
@@ -91,29 +91,29 @@
  * DMA
  ******************************************************************************/
 #define DMA_DCR_BASE 0x100
-#define dmacr0  (DMA_DCR_BASE+0x00)  /* DMA channel control register 0       */
-#define dmact0  (DMA_DCR_BASE+0x01)  /* DMA count register 0                 */
-#define dmada0  (DMA_DCR_BASE+0x02)  /* DMA destination address register 0   */
-#define dmasa0  (DMA_DCR_BASE+0x03)  /* DMA source address register 0        */
-#define dmasb0  (DMA_DCR_BASE+0x04)  /* DMA scatter/gather descriptor addr 0 */
-#define dmacr1  (DMA_DCR_BASE+0x08)  /* DMA channel control register 1       */
-#define dmact1  (DMA_DCR_BASE+0x09)  /* DMA count register 1                 */
-#define dmada1  (DMA_DCR_BASE+0x0a)  /* DMA destination address register 1   */
-#define dmasa1  (DMA_DCR_BASE+0x0b)  /* DMA source address register 1        */
-#define dmasb1  (DMA_DCR_BASE+0x0c)  /* DMA scatter/gather descriptor addr 1 */
-#define dmacr2  (DMA_DCR_BASE+0x10)  /* DMA channel control register 2       */
-#define dmact2  (DMA_DCR_BASE+0x11)  /* DMA count register 2                 */
-#define dmada2  (DMA_DCR_BASE+0x12)  /* DMA destination address register 2   */
-#define dmasa2  (DMA_DCR_BASE+0x13)  /* DMA source address register 2        */
-#define dmasb2  (DMA_DCR_BASE+0x14)  /* DMA scatter/gather descriptor addr 2 */
-#define dmacr3  (DMA_DCR_BASE+0x18)  /* DMA channel control register 3       */
-#define dmact3  (DMA_DCR_BASE+0x19)  /* DMA count register 3                 */
-#define dmada3  (DMA_DCR_BASE+0x1a)  /* DMA destination address register 3   */
-#define dmasa3  (DMA_DCR_BASE+0x1b)  /* DMA source address register 3        */
-#define dmasb3  (DMA_DCR_BASE+0x1c)  /* DMA scatter/gather descriptor addr 3 */
-#define dmasr   (DMA_DCR_BASE+0x20)  /* DMA status register                  */
-#define dmasgc  (DMA_DCR_BASE+0x23)  /* DMA scatter/gather command register  */
-#define dmaadr  (DMA_DCR_BASE+0x24)  /* DMA address decode register          */
+#define dmacr0	(DMA_DCR_BASE+0x00)  /* DMA channel control register 0	     */
+#define dmact0	(DMA_DCR_BASE+0x01)  /* DMA count register 0		     */
+#define dmada0	(DMA_DCR_BASE+0x02)  /* DMA destination address register 0   */
+#define dmasa0	(DMA_DCR_BASE+0x03)  /* DMA source address register 0	     */
+#define dmasb0	(DMA_DCR_BASE+0x04)  /* DMA scatter/gather descriptor addr 0 */
+#define dmacr1	(DMA_DCR_BASE+0x08)  /* DMA channel control register 1	     */
+#define dmact1	(DMA_DCR_BASE+0x09)  /* DMA count register 1		     */
+#define dmada1	(DMA_DCR_BASE+0x0a)  /* DMA destination address register 1   */
+#define dmasa1	(DMA_DCR_BASE+0x0b)  /* DMA source address register 1	     */
+#define dmasb1	(DMA_DCR_BASE+0x0c)  /* DMA scatter/gather descriptor addr 1 */
+#define dmacr2	(DMA_DCR_BASE+0x10)  /* DMA channel control register 2	     */
+#define dmact2	(DMA_DCR_BASE+0x11)  /* DMA count register 2		     */
+#define dmada2	(DMA_DCR_BASE+0x12)  /* DMA destination address register 2   */
+#define dmasa2	(DMA_DCR_BASE+0x13)  /* DMA source address register 2	     */
+#define dmasb2	(DMA_DCR_BASE+0x14)  /* DMA scatter/gather descriptor addr 2 */
+#define dmacr3	(DMA_DCR_BASE+0x18)  /* DMA channel control register 3	     */
+#define dmact3	(DMA_DCR_BASE+0x19)  /* DMA count register 3		     */
+#define dmada3	(DMA_DCR_BASE+0x1a)  /* DMA destination address register 3   */
+#define dmasa3	(DMA_DCR_BASE+0x1b)  /* DMA source address register 3	     */
+#define dmasb3	(DMA_DCR_BASE+0x1c)  /* DMA scatter/gather descriptor addr 3 */
+#define dmasr	(DMA_DCR_BASE+0x20)  /* DMA status register		     */
+#define dmasgc	(DMA_DCR_BASE+0x23)  /* DMA scatter/gather command register  */
+#define dmaadr	(DMA_DCR_BASE+0x24)  /* DMA address decode register	     */
 
 /******************************************************************************
  * Universal interrupt controller
@@ -129,49 +129,49 @@
 
 #define UIC_DCR_BASE 0xc0
 #define UIC0_DCR_BASE UIC_DCR_BASE
-#define uicsr        (UIC_DCR_BASE+0x0)  /* UIC status                       */
-#define uicsrs       (UIC_DCR_BASE+0x1)  /* UIC status set                   */
-#define uicer        (UIC_DCR_BASE+0x2)  /* UIC enable                       */
-#define uiccr        (UIC_DCR_BASE+0x3)  /* UIC critical                     */
-#define uicpr        (UIC_DCR_BASE+0x4)  /* UIC polarity                     */
-#define uictr        (UIC_DCR_BASE+0x5)  /* UIC triggering                   */
-#define uicmsr       (UIC_DCR_BASE+0x6)  /* UIC masked status                */
-#define uicvr        (UIC_DCR_BASE+0x7)  /* UIC vector                       */
-#define uicvcr       (UIC_DCR_BASE+0x8)  /* UIC vector configuration         */
+#define uicsr	     (UIC_DCR_BASE+0x0)  /* UIC status			     */
+#define uicsrs	     (UIC_DCR_BASE+0x1)  /* UIC status set		     */
+#define uicer	     (UIC_DCR_BASE+0x2)  /* UIC enable			     */
+#define uiccr	     (UIC_DCR_BASE+0x3)  /* UIC critical		     */
+#define uicpr	     (UIC_DCR_BASE+0x4)  /* UIC polarity		     */
+#define uictr	     (UIC_DCR_BASE+0x5)  /* UIC triggering		     */
+#define uicmsr	     (UIC_DCR_BASE+0x6)  /* UIC masked status		     */
+#define uicvr	     (UIC_DCR_BASE+0x7)  /* UIC vector			     */
+#define uicvcr	     (UIC_DCR_BASE+0x8)  /* UIC vector configuration	     */
 
 #if defined(CONFIG_405EX)
-#define uic0sr        uicsr		/* UIC status            */
-#define uic0srs       uicsrs		/* UIC status set        */
-#define uic0er        uicer		/* UIC enable            */
-#define uic0cr        uiccr		/* UIC critical          */
-#define uic0pr        uicpr		/* UIC polarity          */
-#define uic0tr        uictr		/* UIC triggering        */
-#define uic0msr       uicmsr		/* UIC masked status     */
-#define uic0vr        uicvr		/* UIC vector            */
+#define uic0sr	      uicsr		/* UIC status		 */
+#define uic0srs       uicsrs		/* UIC status set	 */
+#define uic0er	      uicer		/* UIC enable		 */
+#define uic0cr	      uiccr		/* UIC critical		 */
+#define uic0pr	      uicpr		/* UIC polarity		 */
+#define uic0tr	      uictr		/* UIC triggering	 */
+#define uic0msr       uicmsr		/* UIC masked status	 */
+#define uic0vr	      uicvr		/* UIC vector		 */
 #define uic0vcr       uicvcr		/* UIC vector configuration*/
 
 #define UIC_DCR_BASE1 0xd0
 #define UIC1_DCR_BASE 0xd0
-#define uic1sr        (UIC_DCR_BASE1+0x0)  /* UIC status            */
-#define uic1srs       (UIC_DCR_BASE1+0x1)  /* UIC status set        */
-#define uic1er        (UIC_DCR_BASE1+0x2)  /* UIC enable            */
-#define uic1cr        (UIC_DCR_BASE1+0x3)  /* UIC critical          */
-#define uic1pr        (UIC_DCR_BASE1+0x4)  /* UIC polarity          */
-#define uic1tr        (UIC_DCR_BASE1+0x5)  /* UIC triggering        */
+#define uic1sr	      (UIC_DCR_BASE1+0x0)  /* UIC status	    */
+#define uic1srs       (UIC_DCR_BASE1+0x1)  /* UIC status set	    */
+#define uic1er	      (UIC_DCR_BASE1+0x2)  /* UIC enable	    */
+#define uic1cr	      (UIC_DCR_BASE1+0x3)  /* UIC critical	    */
+#define uic1pr	      (UIC_DCR_BASE1+0x4)  /* UIC polarity	    */
+#define uic1tr	      (UIC_DCR_BASE1+0x5)  /* UIC triggering	    */
 #define uic1msr       (UIC_DCR_BASE1+0x6)  /* UIC masked status     */
-#define uic1vr        (UIC_DCR_BASE1+0x7)  /* UIC vector            */
+#define uic1vr	      (UIC_DCR_BASE1+0x7)  /* UIC vector	    */
 #define uic1vcr       (UIC_DCR_BASE1+0x8)  /* UIC vector configuration*/
 
 #define UIC_DCR_BASE2 0xe0
 #define UIC2_DCR_BASE 0xe0
-#define uic2sr        (UIC_DCR_BASE2+0x0)  /* UIC status            */
-#define uic2srs       (UIC_DCR_BASE2+0x1)  /* UIC status set        */
-#define uic2er        (UIC_DCR_BASE2+0x2)  /* UIC enable            */
-#define uic2cr        (UIC_DCR_BASE2+0x3)  /* UIC critical          */
-#define uic2pr        (UIC_DCR_BASE2+0x4)  /* UIC polarity          */
-#define uic2tr        (UIC_DCR_BASE2+0x5)  /* UIC triggering        */
+#define uic2sr	      (UIC_DCR_BASE2+0x0)  /* UIC status	    */
+#define uic2srs       (UIC_DCR_BASE2+0x1)  /* UIC status set	    */
+#define uic2er	      (UIC_DCR_BASE2+0x2)  /* UIC enable	    */
+#define uic2cr	      (UIC_DCR_BASE2+0x3)  /* UIC critical	    */
+#define uic2pr	      (UIC_DCR_BASE2+0x4)  /* UIC polarity	    */
+#define uic2tr	      (UIC_DCR_BASE2+0x5)  /* UIC triggering	    */
 #define uic2msr       (UIC_DCR_BASE2+0x6)  /* UIC masked status     */
-#define uic2vr        (UIC_DCR_BASE2+0x7)  /* UIC vector            */
+#define uic2vr	      (UIC_DCR_BASE2+0x7)  /* UIC vector	    */
 #define uic2vcr       (UIC_DCR_BASE2+0x8)  /* UIC vector configuration*/
 #endif
 
@@ -221,145 +221,145 @@
 #elif defined(CONFIG_405EX)
 
 /* UIC 0 */
-#define UIC_U0			0x80000000      /* */
-#define UIC_U1			0x40000000      /* */
-#define UIC_IIC0		0x20000000      /* */
-#define UIC_PKA			0x10000000      /* */
-#define UIC_TRNG		0x08000000      /* */
-#define UIC_EBM			0x04000000      /* */
-#define UIC_BGI			0x02000000      /* */
-#define UIC_IIC1		0x01000000      /* */
-#define UIC_SPI			0x00800000      /* */
-#define UIC_EIRQ0		0x00400000      /**/
-#define UIC_MTE			0x00200000      /*MAL Tx EOB */
-#define UIC_MRE			0x00100000      /*MAL Rx EOB */
-#define UIC_DMA0		0x00080000      /* */
-#define UIC_DMA1		0x00040000      /* */
-#define UIC_DMA2		0x00020000      /* */
-#define UIC_DMA3		0x00010000      /* */
-#define UIC_PCIE0AL		0x00008000      /* */
-#define UIC_PCIE0VPD		0x00004000      /* */
-#define UIC_RPCIE0HRST		0x00002000      /* */
-#define UIC_FPCIE0HRST		0x00001000      /* */
-#define UIC_PCIE0TCR		0x00000800      /* */
-#define UIC_PCIEMSI0		0x00000400      /* */
-#define UIC_PCIEMSI1		0x00000200      /* */
-#define UIC_SECURITY		0x00000100      /* */
-#define UIC_ENET		0x00000080      /* */
-#define UIC_ENET1		0x00000040      /* */
-#define UIC_PCIEMSI2		0x00000020      /* */
-#define UIC_EIRQ4		0x00000010      /**/
-#define UICB0_UIC2NCI		0x00000008      /* */
-#define UICB0_UIC2CI		0x00000004      /* */
-#define UICB0_UIC1NCI		0x00000002      /* */
-#define UICB0_UIC1CI		0x00000001      /* */
+#define UIC_U0			0x80000000	/* */
+#define UIC_U1			0x40000000	/* */
+#define UIC_IIC0		0x20000000	/* */
+#define UIC_PKA			0x10000000	/* */
+#define UIC_TRNG		0x08000000	/* */
+#define UIC_EBM			0x04000000	/* */
+#define UIC_BGI			0x02000000	/* */
+#define UIC_IIC1		0x01000000	/* */
+#define UIC_SPI			0x00800000	/* */
+#define UIC_EIRQ0		0x00400000	/**/
+#define UIC_MTE			0x00200000	/*MAL Tx EOB */
+#define UIC_MRE			0x00100000	/*MAL Rx EOB */
+#define UIC_DMA0		0x00080000	/* */
+#define UIC_DMA1		0x00040000	/* */
+#define UIC_DMA2		0x00020000	/* */
+#define UIC_DMA3		0x00010000	/* */
+#define UIC_PCIE0AL		0x00008000	/* */
+#define UIC_PCIE0VPD		0x00004000	/* */
+#define UIC_RPCIE0HRST		0x00002000	/* */
+#define UIC_FPCIE0HRST		0x00001000	/* */
+#define UIC_PCIE0TCR		0x00000800	/* */
+#define UIC_PCIEMSI0		0x00000400	/* */
+#define UIC_PCIEMSI1		0x00000200	/* */
+#define UIC_SECURITY		0x00000100	/* */
+#define UIC_ENET		0x00000080	/* */
+#define UIC_ENET1		0x00000040	/* */
+#define UIC_PCIEMSI2		0x00000020	/* */
+#define UIC_EIRQ4		0x00000010	/**/
+#define UICB0_UIC2NCI		0x00000008	/* */
+#define UICB0_UIC2CI		0x00000004	/* */
+#define UICB0_UIC1NCI		0x00000002	/* */
+#define UICB0_UIC1CI		0x00000001	/* */
 
 #define UICB0_ALL		(UICB0_UIC1CI | UICB0_UIC1NCI | \
 				 UICB0_UIC1CI | UICB0_UIC2NCI)
 
-#define UIC_MAL_TXEOB 		UIC_MTE/* MAL TXEOB                          */
-#define UIC_MAL_RXEOB 		UIC_MRE/* MAL RXEOB                          */
+#define UIC_MAL_TXEOB		UIC_MTE/* MAL TXEOB			     */
+#define UIC_MAL_RXEOB		UIC_MRE/* MAL RXEOB			     */
 /* UIC 1 */
-#define UIC_MS			0x80000000      /* MAL SERR */
-#define UIC_MTDE		0x40000000      /* MAL TXDE */
-#define UIC_MRDE		0x20000000      /* MAL RXDE */
-#define UIC_PCIE0BMVC0		0x10000000      /* */
-#define UIC_PCIE0DCRERR		0x08000000      /* */
-#define UIC_EBC			0x04000000      /* */
-#define UIC_NDFC		0x02000000      /* */
-#define UIC_PCEI1DCRERR		0x01000000      /* */
-#define UIC_GPTCMPT8		0x00800000      /* */
-#define UIC_GPTCMPT9		0x00400000      /* */
-#define UIC_PCIE1AL		0x00200000      /* */
-#define UIC_PCIE1VPD		0x00100000      /* */
-#define UIC_RPCE1HRST		0x00080000      /* */
-#define UIC_FPCE1HRST		0x00040000      /* */
-#define UIC_PCIE1TCR		0x00020000      /* */
-#define UIC_PCIE1VC0		0x00010000      /* */
-#define UIC_GPTCMPT3		0x00008000      /* */
-#define UIC_GPTCMPT4		0x00004000      /* */
-#define UIC_EIRQ7		0x00002000      /* */
-#define UIC_EIRQ8		0x00001000      /* */
-#define UIC_EIRQ9		0x00000800      /* */
-#define UIC_GPTCMP5		0x00000400      /* */
-#define UIC_GPTCMP6		0x00000200      /* */
-#define UIC_GPTCMP7		0x00000100      /* */
-#define UIC_SROM		0x00000080      /* SERIAL ROM*/
-#define UIC_GPTDECPULS		0x00000040      /* GPT Decrement pulse*/
-#define UIC_EIRQ2		0x00000020      /* */
-#define UIC_EIRQ5		0x00000010      /* */
-#define UIC_EIRQ6		0x00000008      /* */
-#define UIC_EMAC0WAKE		0x00000004      /* */
-#define UIC_EIRQ1		0x00000002      /* */
-#define UIC_EMAC1WAKE		0x00000001      /* */
-#define UIC_MAL_SERR		UIC_MS 		/* MAL SERR     */
-#define UIC_MAL_TXDE		UIC_MTDE		/* MAL TXDE     */
-#define UIC_MAL_RXDE		UIC_MRDE 		/* MAL RXDE     */
+#define UIC_MS			0x80000000	/* MAL SERR */
+#define UIC_MTDE		0x40000000	/* MAL TXDE */
+#define UIC_MRDE		0x20000000	/* MAL RXDE */
+#define UIC_PCIE0BMVC0		0x10000000	/* */
+#define UIC_PCIE0DCRERR		0x08000000	/* */
+#define UIC_EBC			0x04000000	/* */
+#define UIC_NDFC		0x02000000	/* */
+#define UIC_PCEI1DCRERR		0x01000000	/* */
+#define UIC_GPTCMPT8		0x00800000	/* */
+#define UIC_GPTCMPT9		0x00400000	/* */
+#define UIC_PCIE1AL		0x00200000	/* */
+#define UIC_PCIE1VPD		0x00100000	/* */
+#define UIC_RPCE1HRST		0x00080000	/* */
+#define UIC_FPCE1HRST		0x00040000	/* */
+#define UIC_PCIE1TCR		0x00020000	/* */
+#define UIC_PCIE1VC0		0x00010000	/* */
+#define UIC_GPTCMPT3		0x00008000	/* */
+#define UIC_GPTCMPT4		0x00004000	/* */
+#define UIC_EIRQ7		0x00002000	/* */
+#define UIC_EIRQ8		0x00001000	/* */
+#define UIC_EIRQ9		0x00000800	/* */
+#define UIC_GPTCMP5		0x00000400	/* */
+#define UIC_GPTCMP6		0x00000200	/* */
+#define UIC_GPTCMP7		0x00000100	/* */
+#define UIC_SROM		0x00000080	/* SERIAL ROM*/
+#define UIC_GPTDECPULS		0x00000040	/* GPT Decrement pulse*/
+#define UIC_EIRQ2		0x00000020	/* */
+#define UIC_EIRQ5		0x00000010	/* */
+#define UIC_EIRQ6		0x00000008	/* */
+#define UIC_EMAC0WAKE		0x00000004	/* */
+#define UIC_EIRQ1		0x00000002	/* */
+#define UIC_EMAC1WAKE		0x00000001	/* */
+#define UIC_MAL_SERR		UIC_MS		/* MAL SERR	*/
+#define UIC_MAL_TXDE		UIC_MTDE		/* MAL TXDE	*/
+#define UIC_MAL_RXDE		UIC_MRDE		/* MAL RXDE	*/
 /* UIC 2 */
-#define UIC_PCIE0INTA		0x80000000      /* PCIE0 INTA*/
-#define UIC_PCIE0INTB		0x40000000      /* PCIE0 INTB*/
-#define UIC_PCIE0INTC		0x20000000      /* PCIE0 INTC*/
-#define UIC_PCIE0INTD		0x10000000      /* PCIE0 INTD*/
-#define UIC_EIRQ3		0x08000000      /* External IRQ 3*/
-#define UIC_DDRMCUE		0x04000000      /* */
-#define UIC_DDRMCCE		0x02000000      /* */
-#define UIC_MALINTCOATX0	0x01000000      /* Interrupt coalecence TX0*/
-#define UIC_MALINTCOATX1	0x00800000      /* Interrupt coalecence TX1*/
-#define UIC_MALINTCOARX0	0x00400000      /* Interrupt coalecence RX0*/
-#define UIC_MALINTCOARX1	0x00200000      /* Interrupt coalecence RX1*/
-#define UIC_PCIE1INTA		0x00100000      /* PCIE0 INTA*/
-#define UIC_PCIE1INTB		0x00080000      /* PCIE0 INTB*/
-#define UIC_PCIE1INTC		0x00040000      /* PCIE0 INTC*/
-#define UIC_PCIE1INTD		0x00020000      /* PCIE0 INTD*/
-#define UIC_RPCIEMSI2		0x00010000      /* MSI level 2 Note this looks same as uic0-26*/
-#define UIC_PCIEMSI3		0x00008000      /* MSI level 2*/
-#define UIC_PCIEMSI4		0x00004000      /* MSI level 2*/
-#define UIC_PCIEMSI5		0x00002000      /* MSI level 2*/
-#define UIC_PCIEMSI6		0x00001000      /* MSI level 2*/
-#define UIC_PCIEMSI7		0x00000800      /* MSI level 2*/
-#define UIC_PCIEMSI8		0x00000400      /* MSI level 2*/
-#define UIC_PCIEMSI9		0x00000200      /* MSI level 2*/
-#define UIC_PCIEMSI10		0x00000100      /* MSI level 2*/
-#define UIC_PCIEMSI11		0x00000080      /* MSI level 2*/
-#define UIC_PCIEMSI12		0x00000040      /* MSI level 2*/
-#define UIC_PCIEMSI13		0x00000020      /* MSI level 2*/
-#define UIC_PCIEMSI14		0x00000010      /* MSI level 2*/
-#define UIC_PCIEMSI15		0x00000008      /* MSI level 2*/
-#define UIC_PLB4XAHB		0x00000004      /* PLBxAHB bridge*/
-#define UIC_USBWAKE		0x00000002      /* USB wakup*/
-#define UIC_USBOTG		0x00000001      /*  USB OTG*/
+#define UIC_PCIE0INTA		0x80000000	/* PCIE0 INTA*/
+#define UIC_PCIE0INTB		0x40000000	/* PCIE0 INTB*/
+#define UIC_PCIE0INTC		0x20000000	/* PCIE0 INTC*/
+#define UIC_PCIE0INTD		0x10000000	/* PCIE0 INTD*/
+#define UIC_EIRQ3		0x08000000	/* External IRQ 3*/
+#define UIC_DDRMCUE		0x04000000	/* */
+#define UIC_DDRMCCE		0x02000000	/* */
+#define UIC_MALINTCOATX0	0x01000000	/* Interrupt coalecence TX0*/
+#define UIC_MALINTCOATX1	0x00800000	/* Interrupt coalecence TX1*/
+#define UIC_MALINTCOARX0	0x00400000	/* Interrupt coalecence RX0*/
+#define UIC_MALINTCOARX1	0x00200000	/* Interrupt coalecence RX1*/
+#define UIC_PCIE1INTA		0x00100000	/* PCIE0 INTA*/
+#define UIC_PCIE1INTB		0x00080000	/* PCIE0 INTB*/
+#define UIC_PCIE1INTC		0x00040000	/* PCIE0 INTC*/
+#define UIC_PCIE1INTD		0x00020000	/* PCIE0 INTD*/
+#define UIC_RPCIEMSI2		0x00010000	/* MSI level 2 Note this looks same as uic0-26*/
+#define UIC_PCIEMSI3		0x00008000	/* MSI level 2*/
+#define UIC_PCIEMSI4		0x00004000	/* MSI level 2*/
+#define UIC_PCIEMSI5		0x00002000	/* MSI level 2*/
+#define UIC_PCIEMSI6		0x00001000	/* MSI level 2*/
+#define UIC_PCIEMSI7		0x00000800	/* MSI level 2*/
+#define UIC_PCIEMSI8		0x00000400	/* MSI level 2*/
+#define UIC_PCIEMSI9		0x00000200	/* MSI level 2*/
+#define UIC_PCIEMSI10		0x00000100	/* MSI level 2*/
+#define UIC_PCIEMSI11		0x00000080	/* MSI level 2*/
+#define UIC_PCIEMSI12		0x00000040	/* MSI level 2*/
+#define UIC_PCIEMSI13		0x00000020	/* MSI level 2*/
+#define UIC_PCIEMSI14		0x00000010	/* MSI level 2*/
+#define UIC_PCIEMSI15		0x00000008	/* MSI level 2*/
+#define UIC_PLB4XAHB		0x00000004	/* PLBxAHB bridge*/
+#define UIC_USBWAKE		0x00000002	/* USB wakup*/
+#define UIC_USBOTG		0x00000001	/*  USB OTG*/
 #define UIC_ETH0	UIC_ENET
 #define UIC_ETH1	UIC_ENET1
 
 #else	/* !defined(CONFIG_405EZ) */
 
-#define UIC_UART0     0x80000000      /* UART 0                             */
-#define UIC_UART1     0x40000000      /* UART 1                             */
-#define UIC_IIC       0x20000000      /* IIC                                */
-#define UIC_EXT_MAST  0x10000000      /* External Master                    */
-#define UIC_PCI       0x08000000      /* PCI write to command reg           */
-#define UIC_DMA0      0x04000000      /* DMA chan. 0                        */
-#define UIC_DMA1      0x02000000      /* DMA chan. 1                        */
-#define UIC_DMA2      0x01000000      /* DMA chan. 2                        */
-#define UIC_DMA3      0x00800000      /* DMA chan. 3                        */
-#define UIC_EMAC_WAKE 0x00400000      /* EMAC wake up                       */
-#define UIC_MAL_SERR  0x00200000      /* MAL SERR                           */
-#define UIC_MAL_TXEOB 0x00100000      /* MAL TXEOB                          */
-#define UIC_MAL_RXEOB 0x00080000      /* MAL RXEOB                          */
-#define UIC_MAL_TXDE  0x00040000      /* MAL TXDE                           */
-#define UIC_MAL_RXDE  0x00020000      /* MAL RXDE                           */
-#define UIC_ENET      0x00010000      /* Ethernet0                          */
-#define UIC_ENET1     0x00004000      /* Ethernet1 on 405EP                 */
+#define UIC_UART0     0x80000000      /* UART 0				    */
+#define UIC_UART1     0x40000000      /* UART 1				    */
+#define UIC_IIC       0x20000000      /* IIC				    */
+#define UIC_EXT_MAST  0x10000000      /* External Master		    */
+#define UIC_PCI       0x08000000      /* PCI write to command reg	    */
+#define UIC_DMA0      0x04000000      /* DMA chan. 0			    */
+#define UIC_DMA1      0x02000000      /* DMA chan. 1			    */
+#define UIC_DMA2      0x01000000      /* DMA chan. 2			    */
+#define UIC_DMA3      0x00800000      /* DMA chan. 3			    */
+#define UIC_EMAC_WAKE 0x00400000      /* EMAC wake up			    */
+#define UIC_MAL_SERR  0x00200000      /* MAL SERR			    */
+#define UIC_MAL_TXEOB 0x00100000      /* MAL TXEOB			    */
+#define UIC_MAL_RXEOB 0x00080000      /* MAL RXEOB			    */
+#define UIC_MAL_TXDE  0x00040000      /* MAL TXDE			    */
+#define UIC_MAL_RXDE  0x00020000      /* MAL RXDE			    */
+#define UIC_ENET      0x00010000      /* Ethernet0			    */
+#define UIC_ENET1     0x00004000      /* Ethernet1 on 405EP		    */
 #define UIC_ECC_CE    0x00004000      /* ECC Correctable Error on 405GP     */
-#define UIC_EXT_PCI_SERR 0x00008000   /* External PCI SERR#                 */
-#define UIC_PCI_PM    0x00002000      /* PCI Power Management               */
-#define UIC_EXT0      0x00000040      /* External  interrupt 0              */
-#define UIC_EXT1      0x00000020      /* External  interrupt 1              */
-#define UIC_EXT2      0x00000010      /* External  interrupt 2              */
-#define UIC_EXT3      0x00000008      /* External  interrupt 3              */
-#define UIC_EXT4      0x00000004      /* External  interrupt 4              */
-#define UIC_EXT5      0x00000002      /* External  interrupt 5              */
-#define UIC_EXT6      0x00000001      /* External  interrupt 6              */
+#define UIC_EXT_PCI_SERR 0x00008000   /* External PCI SERR#		    */
+#define UIC_PCI_PM    0x00002000      /* PCI Power Management		    */
+#define UIC_EXT0      0x00000040      /* External  interrupt 0		    */
+#define UIC_EXT1      0x00000020      /* External  interrupt 1		    */
+#define UIC_EXT2      0x00000010      /* External  interrupt 2		    */
+#define UIC_EXT3      0x00000008      /* External  interrupt 3		    */
+#define UIC_EXT4      0x00000004      /* External  interrupt 4		    */
+#define UIC_EXT5      0x00000002      /* External  interrupt 5		    */
+#define UIC_EXT6      0x00000001      /* External  interrupt 6		    */
 #endif	/* defined(CONFIG_405EZ) */
 
 /******************************************************************************
@@ -404,15 +404,15 @@
   #define kaddr0      0x04    /* address decode definition regsiter 0 */
   #define kaddr1      0x05    /* address decode definition regsiter 1 */
   #define kconf       0x40    /* decompression core config register   */
-  #define kid         0x41    /* decompression core ID     register   */
-  #define kver        0x42    /* decompression core version # reg     */
-  #define kpear       0x50    /* bus error addr reg (PLB addr)        */
+  #define kid	      0x41    /* decompression core ID	   register   */
+  #define kver	      0x42    /* decompression core version # reg     */
+  #define kpear       0x50    /* bus error addr reg (PLB addr)	      */
   #define kbear       0x51    /* bus error addr reg (DCP to EBIU addr)*/
   #define kesr0       0x52    /* bus error status reg 0  (R/clear)    */
-  #define kesr0s      0x53    /* bus error status reg 0  (set)        */
+  #define kesr0s      0x53    /* bus error status reg 0  (set)	      */
   /* There are 0x400 of the following registers, from krom0 to krom3ff*/
-  /* Only the first one is given here.                                */
-  #define krom0      0x400    /* SRAM/ROM read/write                  */
+  /* Only the first one is given here.				      */
+  #define krom0      0x400    /* SRAM/ROM read/write		      */
 #endif
 
 /******************************************************************************
@@ -423,23 +423,23 @@
 #else
 #define POWERMAN_DCR_BASE 0xb8
 #endif
-#define cpmsr (POWERMAN_DCR_BASE+0x0) /* Power management status             */
-#define cpmer (POWERMAN_DCR_BASE+0x1) /* Power management enable             */
-#define cpmfr (POWERMAN_DCR_BASE+0x2) /* Power management force              */
+#define cpmsr (POWERMAN_DCR_BASE+0x0) /* Power management status	     */
+#define cpmer (POWERMAN_DCR_BASE+0x1) /* Power management enable	     */
+#define cpmfr (POWERMAN_DCR_BASE+0x2) /* Power management force		     */
 
 /******************************************************************************
  * Extrnal Bus Controller
  ******************************************************************************/
   /* values for ebccfga register - indirect addressing of these regs */
-  #define pb0cr       0x00    /* periph bank 0 config reg            */
-  #define pb1cr       0x01    /* periph bank 1 config reg            */
-  #define pb2cr       0x02    /* periph bank 2 config reg            */
-  #define pb3cr       0x03    /* periph bank 3 config reg            */
-  #define pb4cr       0x04    /* periph bank 4 config reg            */
+  #define pb0cr       0x00    /* periph bank 0 config reg	     */
+  #define pb1cr       0x01    /* periph bank 1 config reg	     */
+  #define pb2cr       0x02    /* periph bank 2 config reg	     */
+  #define pb3cr       0x03    /* periph bank 3 config reg	     */
+  #define pb4cr       0x04    /* periph bank 4 config reg	     */
 #ifndef CONFIG_405EP
-  #define pb5cr       0x05    /* periph bank 5 config reg            */
-  #define pb6cr       0x06    /* periph bank 6 config reg            */
-  #define pb7cr       0x07    /* periph bank 7 config reg            */
+  #define pb5cr       0x05    /* periph bank 5 config reg	     */
+  #define pb6cr       0x06    /* periph bank 6 config reg	     */
+  #define pb7cr       0x07    /* periph bank 7 config reg	     */
 #endif
   #define pb0ap       0x10    /* periph bank 0 access parameters     */
   #define pb1ap       0x11    /* periph bank 1 access parameters     */
@@ -451,10 +451,10 @@
   #define pb6ap       0x16    /* periph bank 6 access parameters     */
   #define pb7ap       0x17    /* periph bank 7 access parameters     */
 #endif
-  #define pbear       0x20    /* periph bus error addr reg           */
-  #define pbesr0      0x21    /* periph bus error status reg 0       */
-  #define pbesr1      0x22    /* periph bus error status reg 1       */
-  #define epcr        0x23    /* external periph control reg         */
+  #define pbear       0x20    /* periph bus error addr reg	     */
+  #define pbesr0      0x21    /* periph bus error status reg 0	     */
+  #define pbesr1      0x22    /* periph bus error status reg 1	     */
+  #define epcr	      0x23    /* external periph control reg	     */
 #define EBC0_CFG	0x23	/* external bus configuration reg	*/
 
 #ifdef CONFIG_405EP
@@ -462,210 +462,210 @@
  * Control
  ******************************************************************************/
 #define CNTRL_DCR_BASE 0x0f0
-#define cpc0_pllmr0   (CNTRL_DCR_BASE+0x0)  /* PLL mode  register 0                */
-#define cpc0_boot     (CNTRL_DCR_BASE+0x1)  /* Clock status register               */
-#define cpc0_epctl    (CNTRL_DCR_BASE+0x3)  /* EMAC to PHY control register        */
-#define cpc0_pllmr1   (CNTRL_DCR_BASE+0x4)  /* PLL mode  register 1                */
-#define cpc0_ucr      (CNTRL_DCR_BASE+0x5)  /* UART control register               */
-#define cpc0_pci      (CNTRL_DCR_BASE+0x9)  /* PCI control register                */
-
-#define CPC0_PLLMR0  (CNTRL_DCR_BASE+0x0)  /* PLL mode 0 register          */
+#define cpc0_pllmr0   (CNTRL_DCR_BASE+0x0)  /* PLL mode  register 0		   */
+#define cpc0_boot     (CNTRL_DCR_BASE+0x1)  /* Clock status register		   */
+#define cpc0_epctl    (CNTRL_DCR_BASE+0x3)  /* EMAC to PHY control register	   */
+#define cpc0_pllmr1   (CNTRL_DCR_BASE+0x4)  /* PLL mode  register 1		   */
+#define cpc0_ucr      (CNTRL_DCR_BASE+0x5)  /* UART control register		   */
+#define cpc0_pci      (CNTRL_DCR_BASE+0x9)  /* PCI control register		   */
+
+#define CPC0_PLLMR0  (CNTRL_DCR_BASE+0x0)  /* PLL mode 0 register	   */
 #define CPC0_BOOT    (CNTRL_DCR_BASE+0x1)  /* Chip Clock Status register   */
-#define CPC0_CR1     (CNTRL_DCR_BASE+0x2)  /* Chip Control 1 register      */
+#define CPC0_CR1     (CNTRL_DCR_BASE+0x2)  /* Chip Control 1 register	   */
 #define CPC0_EPRCSR  (CNTRL_DCR_BASE+0x3)  /* EMAC PHY Rcv Clk Src register*/
-#define CPC0_PLLMR1  (CNTRL_DCR_BASE+0x4)  /* PLL mode 1 register          */
-#define CPC0_UCR     (CNTRL_DCR_BASE+0x5)  /* UART Control register        */
-#define CPC0_SRR     (CNTRL_DCR_BASE+0x6)  /* Soft Reset register          */
-#define CPC0_JTAGID  (CNTRL_DCR_BASE+0x7)  /* JTAG ID register             */
-#define CPC0_SPARE   (CNTRL_DCR_BASE+0x8)  /* Spare DCR                    */
-#define CPC0_PCI     (CNTRL_DCR_BASE+0x9)  /* PCI Control register         */
+#define CPC0_PLLMR1  (CNTRL_DCR_BASE+0x4)  /* PLL mode 1 register	   */
+#define CPC0_UCR     (CNTRL_DCR_BASE+0x5)  /* UART Control register	   */
+#define CPC0_SRR     (CNTRL_DCR_BASE+0x6)  /* Soft Reset register	   */
+#define CPC0_JTAGID  (CNTRL_DCR_BASE+0x7)  /* JTAG ID register		   */
+#define CPC0_SPARE   (CNTRL_DCR_BASE+0x8)  /* Spare DCR			   */
+#define CPC0_PCI     (CNTRL_DCR_BASE+0x9)  /* PCI Control register	   */
 
 /* Bit definitions */
-#define PLLMR0_CPU_DIV_MASK      0x00300000     /* CPU clock divider */
-#define PLLMR0_CPU_DIV_BYPASS    0x00000000
-#define PLLMR0_CPU_DIV_2         0x00100000
-#define PLLMR0_CPU_DIV_3         0x00200000
-#define PLLMR0_CPU_DIV_4         0x00300000
-
-#define PLLMR0_CPU_TO_PLB_MASK   0x00030000     /* CPU:PLB Frequency Divisor */
-#define PLLMR0_CPU_PLB_DIV_1     0x00000000
-#define PLLMR0_CPU_PLB_DIV_2     0x00010000
-#define PLLMR0_CPU_PLB_DIV_3     0x00020000
-#define PLLMR0_CPU_PLB_DIV_4     0x00030000
-
-#define PLLMR0_OPB_TO_PLB_MASK   0x00003000     /* OPB:PLB Frequency Divisor */
-#define PLLMR0_OPB_PLB_DIV_1     0x00000000
-#define PLLMR0_OPB_PLB_DIV_2     0x00001000
-#define PLLMR0_OPB_PLB_DIV_3     0x00002000
-#define PLLMR0_OPB_PLB_DIV_4     0x00003000
-
-#define PLLMR0_EXB_TO_PLB_MASK   0x00000300     /* External Bus:PLB Divisor  */
-#define PLLMR0_EXB_PLB_DIV_2     0x00000000
-#define PLLMR0_EXB_PLB_DIV_3     0x00000100
-#define PLLMR0_EXB_PLB_DIV_4     0x00000200
-#define PLLMR0_EXB_PLB_DIV_5     0x00000300
-
-#define PLLMR0_MAL_TO_PLB_MASK   0x00000030     /* MAL:PLB Divisor  */
-#define PLLMR0_MAL_PLB_DIV_1     0x00000000
-#define PLLMR0_MAL_PLB_DIV_2     0x00000010
-#define PLLMR0_MAL_PLB_DIV_3     0x00000020
-#define PLLMR0_MAL_PLB_DIV_4     0x00000030
-
-#define PLLMR0_PCI_TO_PLB_MASK   0x00000003     /* PCI:PLB Frequency Divisor */
-#define PLLMR0_PCI_PLB_DIV_1     0x00000000
-#define PLLMR0_PCI_PLB_DIV_2     0x00000001
-#define PLLMR0_PCI_PLB_DIV_3     0x00000002
-#define PLLMR0_PCI_PLB_DIV_4     0x00000003
-
-#define PLLMR1_SSCS_MASK         0x80000000     /* Select system clock source */
-#define PLLMR1_PLLR_MASK         0x40000000     /* PLL reset */
-#define PLLMR1_FBMUL_MASK        0x00F00000     /* PLL feedback multiplier value */
-#define PLLMR1_FBMUL_DIV_16      0x00000000
-#define PLLMR1_FBMUL_DIV_1       0x00100000
-#define PLLMR1_FBMUL_DIV_2       0x00200000
-#define PLLMR1_FBMUL_DIV_3       0x00300000
-#define PLLMR1_FBMUL_DIV_4       0x00400000
-#define PLLMR1_FBMUL_DIV_5       0x00500000
-#define PLLMR1_FBMUL_DIV_6       0x00600000
-#define PLLMR1_FBMUL_DIV_7       0x00700000
-#define PLLMR1_FBMUL_DIV_8       0x00800000
-#define PLLMR1_FBMUL_DIV_9       0x00900000
-#define PLLMR1_FBMUL_DIV_10      0x00A00000
-#define PLLMR1_FBMUL_DIV_11      0x00B00000
-#define PLLMR1_FBMUL_DIV_12      0x00C00000
-#define PLLMR1_FBMUL_DIV_13      0x00D00000
-#define PLLMR1_FBMUL_DIV_14      0x00E00000
-#define PLLMR1_FBMUL_DIV_15      0x00F00000
-
-#define PLLMR1_FWDVA_MASK        0x00070000     /* PLL forward divider A value */
-#define PLLMR1_FWDVA_DIV_8       0x00000000
-#define PLLMR1_FWDVA_DIV_7       0x00010000
-#define PLLMR1_FWDVA_DIV_6       0x00020000
-#define PLLMR1_FWDVA_DIV_5       0x00030000
-#define PLLMR1_FWDVA_DIV_4       0x00040000
-#define PLLMR1_FWDVA_DIV_3       0x00050000
-#define PLLMR1_FWDVA_DIV_2       0x00060000
-#define PLLMR1_FWDVA_DIV_1       0x00070000
-#define PLLMR1_FWDVB_MASK        0x00007000     /* PLL forward divider B value */
-#define PLLMR1_TUNING_MASK       0x000003FF     /* PLL tune bits */
+#define PLLMR0_CPU_DIV_MASK	 0x00300000	/* CPU clock divider */
+#define PLLMR0_CPU_DIV_BYPASS	 0x00000000
+#define PLLMR0_CPU_DIV_2	 0x00100000
+#define PLLMR0_CPU_DIV_3	 0x00200000
+#define PLLMR0_CPU_DIV_4	 0x00300000
+
+#define PLLMR0_CPU_TO_PLB_MASK	 0x00030000	/* CPU:PLB Frequency Divisor */
+#define PLLMR0_CPU_PLB_DIV_1	 0x00000000
+#define PLLMR0_CPU_PLB_DIV_2	 0x00010000
+#define PLLMR0_CPU_PLB_DIV_3	 0x00020000
+#define PLLMR0_CPU_PLB_DIV_4	 0x00030000
+
+#define PLLMR0_OPB_TO_PLB_MASK	 0x00003000	/* OPB:PLB Frequency Divisor */
+#define PLLMR0_OPB_PLB_DIV_1	 0x00000000
+#define PLLMR0_OPB_PLB_DIV_2	 0x00001000
+#define PLLMR0_OPB_PLB_DIV_3	 0x00002000
+#define PLLMR0_OPB_PLB_DIV_4	 0x00003000
+
+#define PLLMR0_EXB_TO_PLB_MASK	 0x00000300	/* External Bus:PLB Divisor  */
+#define PLLMR0_EXB_PLB_DIV_2	 0x00000000
+#define PLLMR0_EXB_PLB_DIV_3	 0x00000100
+#define PLLMR0_EXB_PLB_DIV_4	 0x00000200
+#define PLLMR0_EXB_PLB_DIV_5	 0x00000300
+
+#define PLLMR0_MAL_TO_PLB_MASK	 0x00000030	/* MAL:PLB Divisor  */
+#define PLLMR0_MAL_PLB_DIV_1	 0x00000000
+#define PLLMR0_MAL_PLB_DIV_2	 0x00000010
+#define PLLMR0_MAL_PLB_DIV_3	 0x00000020
+#define PLLMR0_MAL_PLB_DIV_4	 0x00000030
+
+#define PLLMR0_PCI_TO_PLB_MASK	 0x00000003	/* PCI:PLB Frequency Divisor */
+#define PLLMR0_PCI_PLB_DIV_1	 0x00000000
+#define PLLMR0_PCI_PLB_DIV_2	 0x00000001
+#define PLLMR0_PCI_PLB_DIV_3	 0x00000002
+#define PLLMR0_PCI_PLB_DIV_4	 0x00000003
+
+#define PLLMR1_SSCS_MASK	 0x80000000	/* Select system clock source */
+#define PLLMR1_PLLR_MASK	 0x40000000	/* PLL reset */
+#define PLLMR1_FBMUL_MASK	 0x00F00000	/* PLL feedback multiplier value */
+#define PLLMR1_FBMUL_DIV_16	 0x00000000
+#define PLLMR1_FBMUL_DIV_1	 0x00100000
+#define PLLMR1_FBMUL_DIV_2	 0x00200000
+#define PLLMR1_FBMUL_DIV_3	 0x00300000
+#define PLLMR1_FBMUL_DIV_4	 0x00400000
+#define PLLMR1_FBMUL_DIV_5	 0x00500000
+#define PLLMR1_FBMUL_DIV_6	 0x00600000
+#define PLLMR1_FBMUL_DIV_7	 0x00700000
+#define PLLMR1_FBMUL_DIV_8	 0x00800000
+#define PLLMR1_FBMUL_DIV_9	 0x00900000
+#define PLLMR1_FBMUL_DIV_10	 0x00A00000
+#define PLLMR1_FBMUL_DIV_11	 0x00B00000
+#define PLLMR1_FBMUL_DIV_12	 0x00C00000
+#define PLLMR1_FBMUL_DIV_13	 0x00D00000
+#define PLLMR1_FBMUL_DIV_14	 0x00E00000
+#define PLLMR1_FBMUL_DIV_15	 0x00F00000
+
+#define PLLMR1_FWDVA_MASK	 0x00070000	/* PLL forward divider A value */
+#define PLLMR1_FWDVA_DIV_8	 0x00000000
+#define PLLMR1_FWDVA_DIV_7	 0x00010000
+#define PLLMR1_FWDVA_DIV_6	 0x00020000
+#define PLLMR1_FWDVA_DIV_5	 0x00030000
+#define PLLMR1_FWDVA_DIV_4	 0x00040000
+#define PLLMR1_FWDVA_DIV_3	 0x00050000
+#define PLLMR1_FWDVA_DIV_2	 0x00060000
+#define PLLMR1_FWDVA_DIV_1	 0x00070000
+#define PLLMR1_FWDVB_MASK	 0x00007000	/* PLL forward divider B value */
+#define PLLMR1_TUNING_MASK	 0x000003FF	/* PLL tune bits */
 
 /* Defines for CPC0_EPRCSR register */
-#define CPC0_EPRCSR_E0NFE          0x80000000
-#define CPC0_EPRCSR_E1NFE          0x40000000
-#define CPC0_EPRCSR_E1RPP          0x00000080
-#define CPC0_EPRCSR_E0RPP          0x00000040
-#define CPC0_EPRCSR_E1ERP          0x00000020
-#define CPC0_EPRCSR_E0ERP          0x00000010
-#define CPC0_EPRCSR_E1PCI          0x00000002
-#define CPC0_EPRCSR_E0PCI          0x00000001
+#define CPC0_EPRCSR_E0NFE	   0x80000000
+#define CPC0_EPRCSR_E1NFE	   0x40000000
+#define CPC0_EPRCSR_E1RPP	   0x00000080
+#define CPC0_EPRCSR_E0RPP	   0x00000040
+#define CPC0_EPRCSR_E1ERP	   0x00000020
+#define CPC0_EPRCSR_E0ERP	   0x00000010
+#define CPC0_EPRCSR_E1PCI	   0x00000002
+#define CPC0_EPRCSR_E0PCI	   0x00000001
 
 /* Defines for CPC0_PCI Register */
-#define CPC0_PCI_SPE                       0x00000010 /* PCIINT/WE select       */
-#define CPC0_PCI_HOST_CFG_EN               0x00000008 /* PCI host config Enable */
-#define CPC0_PCI_ARBIT_EN                  0x00000001 /* PCI Internal Arb Enabled*/
+#define CPC0_PCI_SPE			   0x00000010 /* PCIINT/WE select	*/
+#define CPC0_PCI_HOST_CFG_EN		   0x00000008 /* PCI host config Enable */
+#define CPC0_PCI_ARBIT_EN		   0x00000001 /* PCI Internal Arb Enabled*/
 
 /* Defines for CPC0_BOOR Register */
-#define CPC0_BOOT_SEP                      0x00000002 /* serial EEPROM present  */
+#define CPC0_BOOT_SEP			   0x00000002 /* serial EEPROM present	*/
 
 /* Defines for CPC0_PLLMR1 Register fields */
-#define PLL_ACTIVE                 0x80000000
-#define CPC0_PLLMR1_SSCS           0x80000000
-#define PLL_RESET                  0x40000000
-#define CPC0_PLLMR1_PLLR           0x40000000
+#define PLL_ACTIVE		   0x80000000
+#define CPC0_PLLMR1_SSCS	   0x80000000
+#define PLL_RESET		   0x40000000
+#define CPC0_PLLMR1_PLLR	   0x40000000
     /* Feedback multiplier */
-#define PLL_FBKDIV                 0x00F00000
-#define CPC0_PLLMR1_FBDV           0x00F00000
-#define PLL_FBKDIV_16              0x00000000
-#define PLL_FBKDIV_1               0x00100000
-#define PLL_FBKDIV_2               0x00200000
-#define PLL_FBKDIV_3               0x00300000
-#define PLL_FBKDIV_4               0x00400000
-#define PLL_FBKDIV_5               0x00500000
-#define PLL_FBKDIV_6               0x00600000
-#define PLL_FBKDIV_7               0x00700000
-#define PLL_FBKDIV_8               0x00800000
-#define PLL_FBKDIV_9               0x00900000
-#define PLL_FBKDIV_10              0x00A00000
-#define PLL_FBKDIV_11              0x00B00000
-#define PLL_FBKDIV_12              0x00C00000
-#define PLL_FBKDIV_13              0x00D00000
-#define PLL_FBKDIV_14              0x00E00000
-#define PLL_FBKDIV_15              0x00F00000
+#define PLL_FBKDIV		   0x00F00000
+#define CPC0_PLLMR1_FBDV	   0x00F00000
+#define PLL_FBKDIV_16		   0x00000000
+#define PLL_FBKDIV_1		   0x00100000
+#define PLL_FBKDIV_2		   0x00200000
+#define PLL_FBKDIV_3		   0x00300000
+#define PLL_FBKDIV_4		   0x00400000
+#define PLL_FBKDIV_5		   0x00500000
+#define PLL_FBKDIV_6		   0x00600000
+#define PLL_FBKDIV_7		   0x00700000
+#define PLL_FBKDIV_8		   0x00800000
+#define PLL_FBKDIV_9		   0x00900000
+#define PLL_FBKDIV_10		   0x00A00000
+#define PLL_FBKDIV_11		   0x00B00000
+#define PLL_FBKDIV_12		   0x00C00000
+#define PLL_FBKDIV_13		   0x00D00000
+#define PLL_FBKDIV_14		   0x00E00000
+#define PLL_FBKDIV_15		   0x00F00000
     /* Forward A divisor */
-#define PLL_FWDDIVA                0x00070000
-#define CPC0_PLLMR1_FWDVA          0x00070000
-#define PLL_FWDDIVA_8              0x00000000
-#define PLL_FWDDIVA_7              0x00010000
-#define PLL_FWDDIVA_6              0x00020000
-#define PLL_FWDDIVA_5              0x00030000
-#define PLL_FWDDIVA_4              0x00040000
-#define PLL_FWDDIVA_3              0x00050000
-#define PLL_FWDDIVA_2              0x00060000
-#define PLL_FWDDIVA_1              0x00070000
+#define PLL_FWDDIVA		   0x00070000
+#define CPC0_PLLMR1_FWDVA	   0x00070000
+#define PLL_FWDDIVA_8		   0x00000000
+#define PLL_FWDDIVA_7		   0x00010000
+#define PLL_FWDDIVA_6		   0x00020000
+#define PLL_FWDDIVA_5		   0x00030000
+#define PLL_FWDDIVA_4		   0x00040000
+#define PLL_FWDDIVA_3		   0x00050000
+#define PLL_FWDDIVA_2		   0x00060000
+#define PLL_FWDDIVA_1		   0x00070000
     /* Forward B divisor */
-#define PLL_FWDDIVB                0x00007000
-#define CPC0_PLLMR1_FWDVB          0x00007000
-#define PLL_FWDDIVB_8              0x00000000
-#define PLL_FWDDIVB_7              0x00001000
-#define PLL_FWDDIVB_6              0x00002000
-#define PLL_FWDDIVB_5              0x00003000
-#define PLL_FWDDIVB_4              0x00004000
-#define PLL_FWDDIVB_3              0x00005000
-#define PLL_FWDDIVB_2              0x00006000
-#define PLL_FWDDIVB_1              0x00007000
+#define PLL_FWDDIVB		   0x00007000
+#define CPC0_PLLMR1_FWDVB	   0x00007000
+#define PLL_FWDDIVB_8		   0x00000000
+#define PLL_FWDDIVB_7		   0x00001000
+#define PLL_FWDDIVB_6		   0x00002000
+#define PLL_FWDDIVB_5		   0x00003000
+#define PLL_FWDDIVB_4		   0x00004000
+#define PLL_FWDDIVB_3		   0x00005000
+#define PLL_FWDDIVB_2		   0x00006000
+#define PLL_FWDDIVB_1		   0x00007000
     /* PLL tune bits */
-#define PLL_TUNE_MASK            0x000003FF
-#define PLL_TUNE_2_M_3           0x00000133     /*  2 <= M <= 3               */
-#define PLL_TUNE_4_M_6           0x00000134     /*  3 <  M <= 6               */
-#define PLL_TUNE_7_M_10          0x00000138     /*  6 <  M <= 10              */
-#define PLL_TUNE_11_M_14         0x0000013C     /* 10 <  M <= 14              */
-#define PLL_TUNE_15_M_40         0x0000023E     /* 14 <  M <= 40              */
-#define PLL_TUNE_VCO_LOW         0x00000000     /* 500MHz <= VCO <=  800MHz   */
-#define PLL_TUNE_VCO_HI          0x00000080     /* 800MHz <  VCO <= 1000MHz   */
+#define PLL_TUNE_MASK		 0x000003FF
+#define PLL_TUNE_2_M_3		 0x00000133	/*  2 <= M <= 3		      */
+#define PLL_TUNE_4_M_6		 0x00000134	/*  3 <  M <= 6		      */
+#define PLL_TUNE_7_M_10		 0x00000138	/*  6 <  M <= 10	      */
+#define PLL_TUNE_11_M_14	 0x0000013C	/* 10 <  M <= 14	      */
+#define PLL_TUNE_15_M_40	 0x0000023E	/* 14 <  M <= 40	      */
+#define PLL_TUNE_VCO_LOW	 0x00000000	/* 500MHz <= VCO <=  800MHz   */
+#define PLL_TUNE_VCO_HI		 0x00000080	/* 800MHz <  VCO <= 1000MHz   */
 
 /* Defines for CPC0_PLLMR0 Register fields */
     /* CPU divisor */
-#define PLL_CPUDIV                 0x00300000
-#define CPC0_PLLMR0_CCDV           0x00300000
-#define PLL_CPUDIV_1               0x00000000
-#define PLL_CPUDIV_2               0x00100000
-#define PLL_CPUDIV_3               0x00200000
-#define PLL_CPUDIV_4               0x00300000
+#define PLL_CPUDIV		   0x00300000
+#define CPC0_PLLMR0_CCDV	   0x00300000
+#define PLL_CPUDIV_1		   0x00000000
+#define PLL_CPUDIV_2		   0x00100000
+#define PLL_CPUDIV_3		   0x00200000
+#define PLL_CPUDIV_4		   0x00300000
     /* PLB divisor */
-#define PLL_PLBDIV                 0x00030000
-#define CPC0_PLLMR0_CBDV           0x00030000
-#define PLL_PLBDIV_1               0x00000000
-#define PLL_PLBDIV_2               0x00010000
-#define PLL_PLBDIV_3               0x00020000
-#define PLL_PLBDIV_4               0x00030000
+#define PLL_PLBDIV		   0x00030000
+#define CPC0_PLLMR0_CBDV	   0x00030000
+#define PLL_PLBDIV_1		   0x00000000
+#define PLL_PLBDIV_2		   0x00010000
+#define PLL_PLBDIV_3		   0x00020000
+#define PLL_PLBDIV_4		   0x00030000
     /* OPB divisor */
-#define PLL_OPBDIV                 0x00003000
-#define CPC0_PLLMR0_OPDV           0x00003000
-#define PLL_OPBDIV_1               0x00000000
-#define PLL_OPBDIV_2               0x00001000
-#define PLL_OPBDIV_3               0x00002000
-#define PLL_OPBDIV_4               0x00003000
+#define PLL_OPBDIV		   0x00003000
+#define CPC0_PLLMR0_OPDV	   0x00003000
+#define PLL_OPBDIV_1		   0x00000000
+#define PLL_OPBDIV_2		   0x00001000
+#define PLL_OPBDIV_3		   0x00002000
+#define PLL_OPBDIV_4		   0x00003000
     /* EBC divisor */
-#define PLL_EXTBUSDIV              0x00000300
-#define CPC0_PLLMR0_EPDV           0x00000300
-#define PLL_EXTBUSDIV_2            0x00000000
-#define PLL_EXTBUSDIV_3            0x00000100
-#define PLL_EXTBUSDIV_4            0x00000200
-#define PLL_EXTBUSDIV_5            0x00000300
+#define PLL_EXTBUSDIV		   0x00000300
+#define CPC0_PLLMR0_EPDV	   0x00000300
+#define PLL_EXTBUSDIV_2		   0x00000000
+#define PLL_EXTBUSDIV_3		   0x00000100
+#define PLL_EXTBUSDIV_4		   0x00000200
+#define PLL_EXTBUSDIV_5		   0x00000300
     /* MAL divisor */
-#define PLL_MALDIV                 0x00000030
-#define CPC0_PLLMR0_MPDV           0x00000030
-#define PLL_MALDIV_1               0x00000000
-#define PLL_MALDIV_2               0x00000010
-#define PLL_MALDIV_3               0x00000020
-#define PLL_MALDIV_4               0x00000030
+#define PLL_MALDIV		   0x00000030
+#define CPC0_PLLMR0_MPDV	   0x00000030
+#define PLL_MALDIV_1		   0x00000000
+#define PLL_MALDIV_2		   0x00000010
+#define PLL_MALDIV_3		   0x00000020
+#define PLL_MALDIV_4		   0x00000030
     /* PCI divisor */
-#define PLL_PCIDIV                 0x00000003
-#define CPC0_PLLMR0_PPFD           0x00000003
-#define PLL_PCIDIV_1               0x00000000
-#define PLL_PCIDIV_2               0x00000001
-#define PLL_PCIDIV_3               0x00000002
-#define PLL_PCIDIV_4               0x00000003
+#define PLL_PCIDIV		   0x00000003
+#define CPC0_PLLMR0_PPFD	   0x00000003
+#define PLL_PCIDIV_1		   0x00000000
+#define PLL_PCIDIV_2		   0x00000001
+#define PLL_PCIDIV_3		   0x00000002
+#define PLL_PCIDIV_4		   0x00000003
 
 /*
  *-------------------------------------------------------------------------------
@@ -681,37 +681,37 @@
 			    PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
 
 #define PLLMR0_133_66_66_33  (PLL_CPUDIV_1 | PLL_PLBDIV_1 |  \
-			      PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 |  \
+			      PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 |	\
 			      PLL_MALDIV_1 | PLL_PCIDIV_4)
 #define PLLMR1_133_66_66_33  (PLL_FBKDIV_4  |  \
 			      PLL_FWDDIVA_6 | PLL_FWDDIVB_6 |  \
 			      PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
 #define PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 |  \
-			      PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 |  \
+			      PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 |	\
 			      PLL_MALDIV_1 | PLL_PCIDIV_4)
 #define PLLMR1_200_100_50_33 (PLL_FBKDIV_6  |  \
 			      PLL_FWDDIVA_4 | PLL_FWDDIVB_4 |  \
 			      PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
 #define PLLMR0_266_133_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 |  \
-			      PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 |  \
+			      PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 |	\
 			      PLL_MALDIV_1 | PLL_PCIDIV_4)
 #define PLLMR1_266_133_66_33 (PLL_FBKDIV_8  |  \
 			      PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |  \
 			      PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
 #define PLLMR0_266_66_33_33 (PLL_CPUDIV_1 | PLL_PLBDIV_4 |  \
-			      PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 |  \
+			      PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 |	\
 			      PLL_MALDIV_1 | PLL_PCIDIV_2)
 #define PLLMR1_266_66_33_33 (PLL_FBKDIV_8  |  \
 			      PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |  \
 			      PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
 #define PLLMR0_333_111_55_37 (PLL_CPUDIV_1 | PLL_PLBDIV_3 |  \
-			      PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 |  \
+			      PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 |	\
 			      PLL_MALDIV_1 | PLL_PCIDIV_3)
-#define PLLMR1_333_111_55_37 (PLL_FBKDIV_10  |  \
+#define PLLMR1_333_111_55_37 (PLL_FBKDIV_10  |	\
 			      PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |  \
 			      PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
 #define PLLMR0_333_111_55_111 (PLL_CPUDIV_1 | PLL_PLBDIV_3 |  \
-			      PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 |  \
+			      PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 |	\
 			      PLL_MALDIV_1 | PLL_PCIDIV_1)
 #define PLLMR1_333_111_55_111 (PLL_FBKDIV_10  |  \
 			      PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |  \
@@ -758,23 +758,23 @@
  * Control
  ******************************************************************************/
 /* CPR Registers */
-#define cprclkupd       0x020		/* CPR_CLKUPD */
-#define cprpllc         0x040		/* CPR_PLLC */
-#define cprplld         0x060		/* CPR_PLLD */
-#define cprprimad       0x080		/* CPR_PRIMAD */
-#define cprperd0        0x0e0		/* CPR_PERD0 */
-#define cprperd1        0x0e1		/* CPR_PERD1 */
-#define cprperc0        0x180		/* CPR_PERC0 */
-#define cprmisc0        0x181		/* CPR_MISC0 */
-#define cprmisc1        0x182		/* CPR_MISC1 */
+#define cprclkupd	0x020		/* CPR_CLKUPD */
+#define cprpllc		0x040		/* CPR_PLLC */
+#define cprplld		0x060		/* CPR_PLLD */
+#define cprprimad	0x080		/* CPR_PRIMAD */
+#define cprperd0	0x0e0		/* CPR_PERD0 */
+#define cprperd1	0x0e1		/* CPR_PERD1 */
+#define cprperc0	0x180		/* CPR_PERC0 */
+#define cprmisc0	0x181		/* CPR_MISC0 */
+#define cprmisc1	0x182		/* CPR_MISC1 */
 
 #define CPR_CLKUPD_ENPLLCH_EN  0x40000000     /* Enable CPR PLL Changes */
 #define CPR_CLKUPD_ENDVCH_EN   0x20000000     /* Enable CPR Sys. Div. Changes */
 #define CPR_PERD0_SPIDV_MASK   0x000F0000     /* SPI Clock Divider */
 
-#define PLLC_SRC_MASK          0x20000000     /* PLL feedback source */
+#define PLLC_SRC_MASK	       0x20000000     /* PLL feedback source */
 
-#define PLLD_FBDV_MASK         0x1F000000     /* PLL feedback divider value */
+#define PLLD_FBDV_MASK	       0x1F000000     /* PLL feedback divider value */
 #define PLLD_FWDVA_MASK        0x000F0000     /* PLL forward divider A value */
 #define PLLD_FWDVB_MASK        0x00000700     /* PLL forward divider B value */
 
@@ -793,77 +793,77 @@
  * Control
  ******************************************************************************/
 #define CNTRL_DCR_BASE 0x0b0
-#define pllmd   (CNTRL_DCR_BASE+0x0)  /* PLL mode  register                  */
-#define cntrl0  (CNTRL_DCR_BASE+0x1)  /* Control 0 register                  */
-#define cntrl1  (CNTRL_DCR_BASE+0x2)  /* Control 1 register		     */
-#define reset   (CNTRL_DCR_BASE+0x3)  /* reset register			     */
-#define strap   (CNTRL_DCR_BASE+0x4)  /* strap register			     */
+#define pllmd	(CNTRL_DCR_BASE+0x0)  /* PLL mode  register		     */
+#define cntrl0	(CNTRL_DCR_BASE+0x1)  /* Control 0 register		     */
+#define cntrl1	(CNTRL_DCR_BASE+0x2)  /* Control 1 register		     */
+#define reset	(CNTRL_DCR_BASE+0x3)  /* reset register			     */
+#define strap	(CNTRL_DCR_BASE+0x4)  /* strap register			     */
 
-#define CPC0_CR0  (CNTRL_DCR_BASE+0x1)  /* chip control register 0	     */
-#define CPC0_CR1  (CNTRL_DCR_BASE+0x2)  /* chip control register 1	     */
-#define CPC0_PSR  (CNTRL_DCR_BASE+0x4)  /* chip pin strapping register	     */
+#define CPC0_CR0  (CNTRL_DCR_BASE+0x1)	/* chip control register 0	     */
+#define CPC0_CR1  (CNTRL_DCR_BASE+0x2)	/* chip control register 1	     */
+#define CPC0_PSR  (CNTRL_DCR_BASE+0x4)	/* chip pin strapping register	     */
 
 /* CPC0_ECR/CPC0_EIRR: PPC405GPr only */
 #define CPC0_EIRR (CNTRL_DCR_BASE+0x6)	/* external interrupt routing register */
 #define CPC0_ECR  (0xaa)		/* edge conditioner register */
 
-#define ecr     (0xaa)                /* edge conditioner register (405gpr)  */
+#define ecr	(0xaa)		      /* edge conditioner register (405gpr)  */
 
 /* Bit definitions */
-#define PLLMR_FWD_DIV_MASK      0xE0000000     /* Forward Divisor */
-#define PLLMR_FWD_DIV_BYPASS    0xE0000000
-#define PLLMR_FWD_DIV_3         0xA0000000
-#define PLLMR_FWD_DIV_4         0x80000000
-#define PLLMR_FWD_DIV_6         0x40000000
-
-#define PLLMR_FB_DIV_MASK       0x1E000000     /* Feedback Divisor */
-#define PLLMR_FB_DIV_1          0x02000000
-#define PLLMR_FB_DIV_2          0x04000000
-#define PLLMR_FB_DIV_3          0x06000000
-#define PLLMR_FB_DIV_4          0x08000000
-
-#define PLLMR_TUNING_MASK       0x01F80000
-
-#define PLLMR_CPU_TO_PLB_MASK   0x00060000     /* CPU:PLB Frequency Divisor */
-#define PLLMR_CPU_PLB_DIV_1     0x00000000
-#define PLLMR_CPU_PLB_DIV_2     0x00020000
-#define PLLMR_CPU_PLB_DIV_3     0x00040000
-#define PLLMR_CPU_PLB_DIV_4     0x00060000
-
-#define PLLMR_OPB_TO_PLB_MASK   0x00018000     /* OPB:PLB Frequency Divisor */
-#define PLLMR_OPB_PLB_DIV_1     0x00000000
-#define PLLMR_OPB_PLB_DIV_2     0x00008000
-#define PLLMR_OPB_PLB_DIV_3     0x00010000
-#define PLLMR_OPB_PLB_DIV_4     0x00018000
-
-#define PLLMR_PCI_TO_PLB_MASK   0x00006000     /* PCI:PLB Frequency Divisor */
-#define PLLMR_PCI_PLB_DIV_1     0x00000000
-#define PLLMR_PCI_PLB_DIV_2     0x00002000
-#define PLLMR_PCI_PLB_DIV_3     0x00004000
-#define PLLMR_PCI_PLB_DIV_4     0x00006000
-
-#define PLLMR_EXB_TO_PLB_MASK   0x00001800     /* External Bus:PLB Divisor  */
-#define PLLMR_EXB_PLB_DIV_2     0x00000000
-#define PLLMR_EXB_PLB_DIV_3     0x00000800
-#define PLLMR_EXB_PLB_DIV_4     0x00001000
-#define PLLMR_EXB_PLB_DIV_5     0x00001800
+#define PLLMR_FWD_DIV_MASK	0xE0000000     /* Forward Divisor */
+#define PLLMR_FWD_DIV_BYPASS	0xE0000000
+#define PLLMR_FWD_DIV_3		0xA0000000
+#define PLLMR_FWD_DIV_4		0x80000000
+#define PLLMR_FWD_DIV_6		0x40000000
+
+#define PLLMR_FB_DIV_MASK	0x1E000000     /* Feedback Divisor */
+#define PLLMR_FB_DIV_1		0x02000000
+#define PLLMR_FB_DIV_2		0x04000000
+#define PLLMR_FB_DIV_3		0x06000000
+#define PLLMR_FB_DIV_4		0x08000000
+
+#define PLLMR_TUNING_MASK	0x01F80000
+
+#define PLLMR_CPU_TO_PLB_MASK	0x00060000     /* CPU:PLB Frequency Divisor */
+#define PLLMR_CPU_PLB_DIV_1	0x00000000
+#define PLLMR_CPU_PLB_DIV_2	0x00020000
+#define PLLMR_CPU_PLB_DIV_3	0x00040000
+#define PLLMR_CPU_PLB_DIV_4	0x00060000
+
+#define PLLMR_OPB_TO_PLB_MASK	0x00018000     /* OPB:PLB Frequency Divisor */
+#define PLLMR_OPB_PLB_DIV_1	0x00000000
+#define PLLMR_OPB_PLB_DIV_2	0x00008000
+#define PLLMR_OPB_PLB_DIV_3	0x00010000
+#define PLLMR_OPB_PLB_DIV_4	0x00018000
+
+#define PLLMR_PCI_TO_PLB_MASK	0x00006000     /* PCI:PLB Frequency Divisor */
+#define PLLMR_PCI_PLB_DIV_1	0x00000000
+#define PLLMR_PCI_PLB_DIV_2	0x00002000
+#define PLLMR_PCI_PLB_DIV_3	0x00004000
+#define PLLMR_PCI_PLB_DIV_4	0x00006000
+
+#define PLLMR_EXB_TO_PLB_MASK	0x00001800     /* External Bus:PLB Divisor  */
+#define PLLMR_EXB_PLB_DIV_2	0x00000000
+#define PLLMR_EXB_PLB_DIV_3	0x00000800
+#define PLLMR_EXB_PLB_DIV_4	0x00001000
+#define PLLMR_EXB_PLB_DIV_5	0x00001800
 
 /* definitions for PPC405GPr (new mode strapping) */
-#define PLLMR_FWDB_DIV_MASK     0x00000007     /* Forward Divisor B */
-
-#define PSR_PLL_FWD_MASK        0xC0000000
-#define PSR_PLL_FDBACK_MASK     0x30000000
-#define PSR_PLL_TUNING_MASK     0x0E000000
-#define PSR_PLB_CPU_MASK        0x01800000
-#define PSR_OPB_PLB_MASK        0x00600000
-#define PSR_PCI_PLB_MASK        0x00180000
-#define PSR_EB_PLB_MASK         0x00060000
-#define PSR_ROM_WIDTH_MASK      0x00018000
-#define PSR_ROM_LOC             0x00004000
-#define PSR_PCI_ASYNC_EN        0x00001000
+#define PLLMR_FWDB_DIV_MASK	0x00000007     /* Forward Divisor B */
+
+#define PSR_PLL_FWD_MASK	0xC0000000
+#define PSR_PLL_FDBACK_MASK	0x30000000
+#define PSR_PLL_TUNING_MASK	0x0E000000
+#define PSR_PLB_CPU_MASK	0x01800000
+#define PSR_OPB_PLB_MASK	0x00600000
+#define PSR_PCI_PLB_MASK	0x00180000
+#define PSR_EB_PLB_MASK		0x00060000
+#define PSR_ROM_WIDTH_MASK	0x00018000
+#define PSR_ROM_LOC		0x00004000
+#define PSR_PCI_ASYNC_EN	0x00001000
 #define PSR_PERCLK_SYNC_MODE_EN 0x00000800     /* PPC405GPr only */
-#define PSR_PCI_ARBIT_EN        0x00000400
-#define PSR_NEW_MODE_EN         0x00000020     /* PPC405GPr only */
+#define PSR_PCI_ARBIT_EN	0x00000400
+#define PSR_NEW_MODE_EN		0x00000020     /* PPC405GPr only */
 
 #ifndef CONFIG_IOP480
 /*
@@ -994,44 +994,44 @@
 #else /* !defined(CONFIG_405EZ) */
 
 #define MAL_DCR_BASE 0x180
-#define malmcr  (MAL_DCR_BASE+0x00)  /* MAL Config reg                       */
-#define malesr  (MAL_DCR_BASE+0x01)  /* Error Status reg (Read/Clear)        */
-#define malier  (MAL_DCR_BASE+0x02)  /* Interrupt enable reg                 */
-#define maldbr  (MAL_DCR_BASE+0x03)  /* Mal Debug reg (Read only)            */
-#define maltxcasr  (MAL_DCR_BASE+0x04)  /* TX Channel active reg (set)       */
-#define maltxcarr  (MAL_DCR_BASE+0x05)  /* TX Channel active reg (Reset)     */
+#define malmcr	(MAL_DCR_BASE+0x00)  /* MAL Config reg			     */
+#define malesr	(MAL_DCR_BASE+0x01)  /* Error Status reg (Read/Clear)	     */
+#define malier	(MAL_DCR_BASE+0x02)  /* Interrupt enable reg		     */
+#define maldbr	(MAL_DCR_BASE+0x03)  /* Mal Debug reg (Read only)	     */
+#define maltxcasr  (MAL_DCR_BASE+0x04)	/* TX Channel active reg (set)	     */
+#define maltxcarr  (MAL_DCR_BASE+0x05)	/* TX Channel active reg (Reset)     */
 #define maltxeobisr (MAL_DCR_BASE+0x06) /* TX End of buffer int status reg   */
-#define maltxdeir  (MAL_DCR_BASE+0x07)  /* TX Descr. Error Int reg           */
-#define malrxcasr  (MAL_DCR_BASE+0x10)  /* RX Channel active reg (set)       */
-#define malrxcarr  (MAL_DCR_BASE+0x11)  /* RX Channel active reg (Reset)     */
+#define maltxdeir  (MAL_DCR_BASE+0x07)	/* TX Descr. Error Int reg	     */
+#define malrxcasr  (MAL_DCR_BASE+0x10)	/* RX Channel active reg (set)	     */
+#define malrxcarr  (MAL_DCR_BASE+0x11)	/* RX Channel active reg (Reset)     */
 #define malrxeobisr (MAL_DCR_BASE+0x12) /* RX End of buffer int status reg   */
-#define malrxdeir  (MAL_DCR_BASE+0x13)  /* RX Descr. Error Int reg           */
-#define maltxctp0r (MAL_DCR_BASE+0x20)  /* TX 0 Channel table pointer reg    */
-#define maltxctp1r (MAL_DCR_BASE+0x21)  /* TX 1 Channel table pointer reg    */
-#define maltxctp2r (MAL_DCR_BASE+0x22)  /* TX 2 Channel table pointer reg    */
-#define malrxctp0r (MAL_DCR_BASE+0x40)  /* RX 0 Channel table pointer reg    */
-#define malrxctp1r (MAL_DCR_BASE+0x41)  /* RX 1 Channel table pointer reg    */
-#define malrcbs0   (MAL_DCR_BASE+0x60)  /* RX 0 Channel buffer size reg      */
-#define malrcbs1   (MAL_DCR_BASE+0x61)  /* RX 1 Channel buffer size reg      */
+#define malrxdeir  (MAL_DCR_BASE+0x13)	/* RX Descr. Error Int reg	     */
+#define maltxctp0r (MAL_DCR_BASE+0x20)	/* TX 0 Channel table pointer reg    */
+#define maltxctp1r (MAL_DCR_BASE+0x21)	/* TX 1 Channel table pointer reg    */
+#define maltxctp2r (MAL_DCR_BASE+0x22)	/* TX 2 Channel table pointer reg    */
+#define malrxctp0r (MAL_DCR_BASE+0x40)	/* RX 0 Channel table pointer reg    */
+#define malrxctp1r (MAL_DCR_BASE+0x41)	/* RX 1 Channel table pointer reg    */
+#define malrcbs0   (MAL_DCR_BASE+0x60)	/* RX 0 Channel buffer size reg      */
+#define malrcbs1   (MAL_DCR_BASE+0x61)	/* RX 1 Channel buffer size reg      */
 #endif /* defined(CONFIG_405EZ) */
 
 /*-----------------------------------------------------------------------------
 | IIC Register Offsets
 '----------------------------------------------------------------------------*/
-#define    IICMDBUF         0x00
-#define    IICSDBUF         0x02
-#define    IICLMADR         0x04
-#define    IICHMADR         0x05
-#define    IICCNTL          0x06
-#define    IICMDCNTL        0x07
-#define    IICSTS           0x08
-#define    IICEXTSTS        0x09
-#define    IICLSADR         0x0A
-#define    IICHSADR         0x0B
-#define    IICCLKDIV        0x0C
-#define    IICINTRMSK       0x0D
-#define    IICXFRCNT        0x0E
-#define    IICXTCNTLSS      0x0F
+#define    IICMDBUF	    0x00
+#define    IICSDBUF	    0x02
+#define    IICLMADR	    0x04
+#define    IICHMADR	    0x05
+#define    IICCNTL	    0x06
+#define    IICMDCNTL	    0x07
+#define    IICSTS	    0x08
+#define    IICEXTSTS	    0x09
+#define    IICLSADR	    0x0A
+#define    IICHSADR	    0x0B
+#define    IICCLKDIV	    0x0C
+#define    IICINTRMSK	    0x0D
+#define    IICXFRCNT	    0x0E
+#define    IICXTCNTLSS	    0x0F
 #define    IICDIRECTCNTL    0x10
 
 /*-----------------------------------------------------------------------------
@@ -1040,40 +1040,40 @@
 #define		DATA_REG	0x00
 #define		DL_LSB		0x00
 #define		DL_MSB		0x01
-#define		INT_ENABLE      0x01
-#define		FIFO_CONTROL    0x02
-#define		LINE_CONTROL    0x03
-#define		MODEM_CONTROL   0x04
+#define		INT_ENABLE	0x01
+#define		FIFO_CONTROL	0x02
+#define		LINE_CONTROL	0x03
+#define		MODEM_CONTROL	0x04
 #define		LINE_STATUS	0x05
-#define		MODEM_STATUS    0x06
-#define		SCRATCH         0x07
+#define		MODEM_STATUS	0x06
+#define		SCRATCH		0x07
 
 /******************************************************************************
  * On Chip Memory
  ******************************************************************************/
 #if defined(CONFIG_405EZ)
 #define OCM_DCR_BASE 0x020
-#define ocmplb3cr1      (OCM_DCR_BASE+0x00)  /* OCM PLB3 Bank 1 Config Reg    */
-#define ocmplb3cr2      (OCM_DCR_BASE+0x01)  /* OCM PLB3 Bank 2 Config Reg    */
-#define ocmplb3bear     (OCM_DCR_BASE+0x02)  /* OCM PLB3 Bus Error Add Reg    */
-#define ocmplb3besr0    (OCM_DCR_BASE+0x03)  /* OCM PLB3 Bus Error Stat Reg 0 */
-#define ocmplb3besr1    (OCM_DCR_BASE+0x04)  /* OCM PLB3 Bus Error Stat Reg 1 */
-#define ocmcid          (OCM_DCR_BASE+0x05)  /* OCM Core ID                   */
-#define ocmrevid        (OCM_DCR_BASE+0x06)  /* OCM Revision ID               */
-#define ocmplb3dpc      (OCM_DCR_BASE+0x07)  /* OCM PLB3 Data Parity Check    */
-#define ocmdscr1        (OCM_DCR_BASE+0x08)  /* OCM D-side Bank 1 Config Reg  */
-#define ocmdscr2        (OCM_DCR_BASE+0x09)  /* OCM D-side Bank 2 Config Reg  */
-#define ocmiscr1        (OCM_DCR_BASE+0x0A)  /* OCM I-side Bank 1 Config Reg  */
-#define ocmiscr2        (OCM_DCR_BASE+0x0B)  /* OCM I-side Bank 2 Config Reg  */
-#define ocmdsisdpc      (OCM_DCR_BASE+0x0C)  /* OCM D-side/I-side Data Par Chk*/
-#define ocmdsisbear     (OCM_DCR_BASE+0x0D)  /* OCM D-side/I-side Bus Err Addr*/
-#define ocmdsisbesr     (OCM_DCR_BASE+0x0E)  /* OCM D-side/I-side Bus Err Stat*/
+#define ocmplb3cr1	(OCM_DCR_BASE+0x00)  /* OCM PLB3 Bank 1 Config Reg    */
+#define ocmplb3cr2	(OCM_DCR_BASE+0x01)  /* OCM PLB3 Bank 2 Config Reg    */
+#define ocmplb3bear	(OCM_DCR_BASE+0x02)  /* OCM PLB3 Bus Error Add Reg    */
+#define ocmplb3besr0	(OCM_DCR_BASE+0x03)  /* OCM PLB3 Bus Error Stat Reg 0 */
+#define ocmplb3besr1	(OCM_DCR_BASE+0x04)  /* OCM PLB3 Bus Error Stat Reg 1 */
+#define ocmcid		(OCM_DCR_BASE+0x05)  /* OCM Core ID		      */
+#define ocmrevid	(OCM_DCR_BASE+0x06)  /* OCM Revision ID		      */
+#define ocmplb3dpc	(OCM_DCR_BASE+0x07)  /* OCM PLB3 Data Parity Check    */
+#define ocmdscr1	(OCM_DCR_BASE+0x08)  /* OCM D-side Bank 1 Config Reg  */
+#define ocmdscr2	(OCM_DCR_BASE+0x09)  /* OCM D-side Bank 2 Config Reg  */
+#define ocmiscr1	(OCM_DCR_BASE+0x0A)  /* OCM I-side Bank 1 Config Reg  */
+#define ocmiscr2	(OCM_DCR_BASE+0x0B)  /* OCM I-side Bank 2 Config Reg  */
+#define ocmdsisdpc	(OCM_DCR_BASE+0x0C)  /* OCM D-side/I-side Data Par Chk*/
+#define ocmdsisbear	(OCM_DCR_BASE+0x0D)  /* OCM D-side/I-side Bus Err Addr*/
+#define ocmdsisbesr	(OCM_DCR_BASE+0x0E)  /* OCM D-side/I-side Bus Err Stat*/
 #else
 #define OCM_DCR_BASE 0x018
-#define ocmisarc   (OCM_DCR_BASE+0x00)  /* OCM I-side address compare reg    */
-#define ocmiscntl  (OCM_DCR_BASE+0x01)  /* OCM I-side control reg            */
-#define ocmdsarc   (OCM_DCR_BASE+0x02)  /* OCM D-side address compare reg    */
-#define ocmdscntl  (OCM_DCR_BASE+0x03)  /* OCM D-side control reg            */
+#define ocmisarc   (OCM_DCR_BASE+0x00)	/* OCM I-side address compare reg    */
+#define ocmiscntl  (OCM_DCR_BASE+0x01)	/* OCM I-side control reg	     */
+#define ocmdsarc   (OCM_DCR_BASE+0x02)	/* OCM D-side address compare reg    */
+#define ocmdscntl  (OCM_DCR_BASE+0x03)	/* OCM D-side control reg	     */
 #endif /* CONFIG_405EZ */
 
 /******************************************************************************
@@ -1121,40 +1121,40 @@
 
 #elif defined(CONFIG_405EX)
 #define GPIO_BASE  0xEF600800
-#define GPIO0_OR               (GPIO_BASE+0x0)
-#define GPIO0_TCR              (GPIO_BASE+0x4)
-#define GPIO0_OSRL             (GPIO_BASE+0x8)
-#define GPIO0_OSRH             (GPIO_BASE+0xC)
-#define GPIO0_TSRL             (GPIO_BASE+0x10)
-#define GPIO0_TSRH             (GPIO_BASE+0x14)
-#define GPIO0_ODR              (GPIO_BASE+0x18)
-#define GPIO0_IR               (GPIO_BASE+0x1C)
-#define GPIO0_RR1              (GPIO_BASE+0x20)
-#define GPIO0_RR2              (GPIO_BASE+0x24)
-#define GPIO0_ISR1L            (GPIO_BASE+0x30)
-#define GPIO0_ISR1H            (GPIO_BASE+0x34)
-#define GPIO0_ISR2L            (GPIO_BASE+0x38)
-#define GPIO0_ISR2H            (GPIO_BASE+0x3C)
-#define GPIO0_ISR3L            (GPIO_BASE+0x40)
-#define GPIO0_ISR3H            (GPIO_BASE+0x44)
+#define GPIO0_OR	       (GPIO_BASE+0x0)
+#define GPIO0_TCR	       (GPIO_BASE+0x4)
+#define GPIO0_OSRL	       (GPIO_BASE+0x8)
+#define GPIO0_OSRH	       (GPIO_BASE+0xC)
+#define GPIO0_TSRL	       (GPIO_BASE+0x10)
+#define GPIO0_TSRH	       (GPIO_BASE+0x14)
+#define GPIO0_ODR	       (GPIO_BASE+0x18)
+#define GPIO0_IR	       (GPIO_BASE+0x1C)
+#define GPIO0_RR1	       (GPIO_BASE+0x20)
+#define GPIO0_RR2	       (GPIO_BASE+0x24)
+#define GPIO0_ISR1L	       (GPIO_BASE+0x30)
+#define GPIO0_ISR1H	       (GPIO_BASE+0x34)
+#define GPIO0_ISR2L	       (GPIO_BASE+0x38)
+#define GPIO0_ISR2H	       (GPIO_BASE+0x3C)
+#define GPIO0_ISR3L	       (GPIO_BASE+0x40)
+#define GPIO0_ISR3H	       (GPIO_BASE+0x44)
 
 #else	/* !405EZ */
 
 #define GPIO_BASE  0xEF600700
-#define GPIO0_OR               (GPIO_BASE+0x0)
-#define GPIO0_TCR              (GPIO_BASE+0x4)
-#define GPIO0_OSRH             (GPIO_BASE+0x8)
-#define GPIO0_OSRL             (GPIO_BASE+0xC)
-#define GPIO0_TSRH             (GPIO_BASE+0x10)
-#define GPIO0_TSRL             (GPIO_BASE+0x14)
-#define GPIO0_ODR              (GPIO_BASE+0x18)
-#define GPIO0_IR               (GPIO_BASE+0x1C)
-#define GPIO0_RR1              (GPIO_BASE+0x20)
-#define GPIO0_RR2              (GPIO_BASE+0x24)
-#define GPIO0_ISR1H            (GPIO_BASE+0x30)
-#define GPIO0_ISR1L            (GPIO_BASE+0x34)
-#define GPIO0_ISR2H            (GPIO_BASE+0x38)
-#define GPIO0_ISR2L            (GPIO_BASE+0x3C)
+#define GPIO0_OR	       (GPIO_BASE+0x0)
+#define GPIO0_TCR	       (GPIO_BASE+0x4)
+#define GPIO0_OSRH	       (GPIO_BASE+0x8)
+#define GPIO0_OSRL	       (GPIO_BASE+0xC)
+#define GPIO0_TSRH	       (GPIO_BASE+0x10)
+#define GPIO0_TSRL	       (GPIO_BASE+0x14)
+#define GPIO0_ODR	       (GPIO_BASE+0x18)
+#define GPIO0_IR	       (GPIO_BASE+0x1C)
+#define GPIO0_RR1	       (GPIO_BASE+0x20)
+#define GPIO0_RR2	       (GPIO_BASE+0x24)
+#define GPIO0_ISR1H	       (GPIO_BASE+0x30)
+#define GPIO0_ISR1L	       (GPIO_BASE+0x34)
+#define GPIO0_ISR2H	       (GPIO_BASE+0x38)
+#define GPIO0_ISR2L	       (GPIO_BASE+0x3C)
 
 #endif /* CONFIG_405EZ */
 
@@ -1169,376 +1169,376 @@
 #define SDRAM_WMIRQ	0x06	/**/
 #define SDRAM_PLBOPT	0x08	/**/
 #define SDRAM_PUABA	0x09	/**/
-#define SDRAM_MCSTAT    0x1F    /* memory controller status           */
-#define SDRAM_MCOPT1    0x20    /* memory controller options 1        */
-#define SDRAM_MCOPT2    0x21    /* memory controller options 2        */
-#define SDRAM_MODT0     0x22    /* on die termination for bank 0      */
-#define SDRAM_MODT1     0x23    /* on die termination for bank 1      */
-#define SDRAM_MODT2     0x24    /* on die termination for bank 2      */
-#define SDRAM_MODT3     0x25    /* on die termination for bank 3      */
-#define SDRAM_CODT      0x26    /* on die termination for controller  */
-#define SDRAM_VVPR      0x27    /* variable VRef programmming         */
-#define SDRAM_OPARS     0x28    /* on chip driver control setup       */
-#define SDRAM_OPART     0x29    /* on chip driver control trigger     */
-#define SDRAM_RTR       0x30    /* refresh timer                      */
-#define SDRAM_PMIT      0x34    /* power management idle timer        */
-#define SDRAM_MB0CF     0x40    /* memory bank 0 configuration        */
-#define SDRAM_MB1CF     0x44    /* memory bank 1 configuration        */
-#define SDRAM_MB2CF     0x48    /* memory bank 2 configuration        */
-#define SDRAM_MB3CF     0x4C    /* memory bank 3 configuration        */
-#define SDRAM_INITPLR0  0x50    /* manual initialization control      */
-#define SDRAM_INITPLR1  0x51    /* manual initialization control      */
-#define SDRAM_INITPLR2  0x52    /* manual initialization control      */
-#define SDRAM_INITPLR3  0x53    /* manual initialization control      */
-#define SDRAM_INITPLR4  0x54    /* manual initialization control      */
-#define SDRAM_INITPLR5  0x55    /* manual initialization control      */
-#define SDRAM_INITPLR6  0x56    /* manual initialization control      */
-#define SDRAM_INITPLR7  0x57    /* manual initialization control      */
-#define SDRAM_INITPLR8  0x58    /* manual initialization control      */
-#define SDRAM_INITPLR9  0x59    /* manual initialization control      */
-#define SDRAM_INITPLR10 0x5a    /* manual initialization control      */
-#define SDRAM_INITPLR11 0x5b    /* manual initialization control      */
-#define SDRAM_INITPLR12 0x5c    /* manual initialization control      */
-#define SDRAM_INITPLR13 0x5d    /* manual initialization control      */
-#define SDRAM_INITPLR14 0x5e    /* manual initialization control      */
-#define SDRAM_INITPLR15 0x5f    /* manual initialization control      */
-#define SDRAM_RQDC      0x70    /* read DQS delay control             */
-#define SDRAM_RFDC      0x74    /* read feedback delay control        */
-#define SDRAM_RDCC      0x78    /* read data capture control          */
-#define SDRAM_DLCR      0x7A    /* delay line calibration             */
-#define SDRAM_CLKTR     0x80    /* DDR clock timing                   */
-#define SDRAM_WRDTR     0x81    /* write data, DQS, DM clock, timing  */
-#define SDRAM_SDTR1     0x85    /* DDR SDRAM timing 1                 */
-#define SDRAM_SDTR2     0x86    /* DDR SDRAM timing 2                 */
-#define SDRAM_SDTR3     0x87    /* DDR SDRAM timing 3                 */
-#define SDRAM_MMODE     0x88    /* memory mode                        */
-#define SDRAM_MEMODE    0x89    /* memory extended mode               */
-#define SDRAM_ECCCR     0x98    /* ECC error status                   */
-#define SDRAM_RID       0xF8    /* revision ID                        */
+#define SDRAM_MCSTAT	0x1F	/* memory controller status	      */
+#define SDRAM_MCOPT1	0x20	/* memory controller options 1	      */
+#define SDRAM_MCOPT2	0x21	/* memory controller options 2	      */
+#define SDRAM_MODT0	0x22	/* on die termination for bank 0      */
+#define SDRAM_MODT1	0x23	/* on die termination for bank 1      */
+#define SDRAM_MODT2	0x24	/* on die termination for bank 2      */
+#define SDRAM_MODT3	0x25	/* on die termination for bank 3      */
+#define SDRAM_CODT	0x26	/* on die termination for controller  */
+#define SDRAM_VVPR	0x27	/* variable VRef programmming	      */
+#define SDRAM_OPARS	0x28	/* on chip driver control setup       */
+#define SDRAM_OPART	0x29	/* on chip driver control trigger     */
+#define SDRAM_RTR	0x30	/* refresh timer		      */
+#define SDRAM_PMIT	0x34	/* power management idle timer	      */
+#define SDRAM_MB0CF	0x40	/* memory bank 0 configuration	      */
+#define SDRAM_MB1CF	0x44	/* memory bank 1 configuration	      */
+#define SDRAM_MB2CF	0x48	/* memory bank 2 configuration	      */
+#define SDRAM_MB3CF	0x4C	/* memory bank 3 configuration	      */
+#define SDRAM_INITPLR0	0x50	/* manual initialization control      */
+#define SDRAM_INITPLR1	0x51	/* manual initialization control      */
+#define SDRAM_INITPLR2	0x52	/* manual initialization control      */
+#define SDRAM_INITPLR3	0x53	/* manual initialization control      */
+#define SDRAM_INITPLR4	0x54	/* manual initialization control      */
+#define SDRAM_INITPLR5	0x55	/* manual initialization control      */
+#define SDRAM_INITPLR6	0x56	/* manual initialization control      */
+#define SDRAM_INITPLR7	0x57	/* manual initialization control      */
+#define SDRAM_INITPLR8	0x58	/* manual initialization control      */
+#define SDRAM_INITPLR9	0x59	/* manual initialization control      */
+#define SDRAM_INITPLR10 0x5a	/* manual initialization control      */
+#define SDRAM_INITPLR11 0x5b	/* manual initialization control      */
+#define SDRAM_INITPLR12 0x5c	/* manual initialization control      */
+#define SDRAM_INITPLR13 0x5d	/* manual initialization control      */
+#define SDRAM_INITPLR14 0x5e	/* manual initialization control      */
+#define SDRAM_INITPLR15 0x5f	/* manual initialization control      */
+#define SDRAM_RQDC	0x70	/* read DQS delay control	      */
+#define SDRAM_RFDC	0x74	/* read feedback delay control	      */
+#define SDRAM_RDCC	0x78	/* read data capture control	      */
+#define SDRAM_DLCR	0x7A	/* delay line calibration	      */
+#define SDRAM_CLKTR	0x80	/* DDR clock timing		      */
+#define SDRAM_WRDTR	0x81	/* write data, DQS, DM clock, timing  */
+#define SDRAM_SDTR1	0x85	/* DDR SDRAM timing 1		      */
+#define SDRAM_SDTR2	0x86	/* DDR SDRAM timing 2		      */
+#define SDRAM_SDTR3	0x87	/* DDR SDRAM timing 3		      */
+#define SDRAM_MMODE	0x88	/* memory mode			      */
+#define SDRAM_MEMODE	0x89	/* memory extended mode		      */
+#define SDRAM_ECCCR	0x98	/* ECC error status		      */
+#define SDRAM_RID	0xF8	/* revision ID			      */
 
 /*-----------------------------------------------------------------------------+
 |  Memory Bank 0-7 configuration
 +-----------------------------------------------------------------------------*/
-#define SDRAM_RXBAS_SDSZ_4         0x00000000      /*   4M                    */
-#define SDRAM_RXBAS_SDSZ_8         0x00001000      /*   8M                    */
-#define SDRAM_RXBAS_SDSZ_16        0x00002000      /*  16M                    */
-#define SDRAM_RXBAS_SDSZ_32        0x00003000      /*  32M                    */
-#define SDRAM_RXBAS_SDSZ_64        0x00004000      /*  64M                    */
-#define SDRAM_RXBAS_SDSZ_128       0x00005000      /* 128M                    */
-#define SDRAM_RXBAS_SDSZ_256       0x00006000      /* 256M                    */
-#define SDRAM_RXBAS_SDSZ_512       0x00007000      /* 512M                    */
-#define SDRAM_RXBAS_SDSZ_1024      0x00008000      /* 1024M                   */
-#define SDRAM_RXBAS_SDSZ_2048      0x00009000      /* 2048M                   */
-#define SDRAM_RXBAS_SDSZ_4096      0x0000a000      /* 4096M                   */
-#define SDRAM_RXBAS_SDSZ_8192      0x0000b000      /* 8192M                   */
+#define SDRAM_RXBAS_SDSZ_4	   0x00000000	   /*	4M		      */
+#define SDRAM_RXBAS_SDSZ_8	   0x00001000	   /*	8M		      */
+#define SDRAM_RXBAS_SDSZ_16	   0x00002000	   /*  16M		      */
+#define SDRAM_RXBAS_SDSZ_32	   0x00003000	   /*  32M		      */
+#define SDRAM_RXBAS_SDSZ_64	   0x00004000	   /*  64M		      */
+#define SDRAM_RXBAS_SDSZ_128	   0x00005000	   /* 128M		      */
+#define SDRAM_RXBAS_SDSZ_256	   0x00006000	   /* 256M		      */
+#define SDRAM_RXBAS_SDSZ_512	   0x00007000	   /* 512M		      */
+#define SDRAM_RXBAS_SDSZ_1024	   0x00008000	   /* 1024M		      */
+#define SDRAM_RXBAS_SDSZ_2048	   0x00009000	   /* 2048M		      */
+#define SDRAM_RXBAS_SDSZ_4096	   0x0000a000	   /* 4096M		      */
+#define SDRAM_RXBAS_SDSZ_8192	   0x0000b000	   /* 8192M		      */
 
 /*-----------------------------------------------------------------------------+
 |  Memory Controller Status
 +-----------------------------------------------------------------------------*/
-#define SDRAM_MCSTAT_MIC_MASK       0x80000000  /* Memory init status mask    */
-#define   SDRAM_MCSTAT_MIC_NOTCOMP  0x00000000  /* Mem init not complete      */
-#define   SDRAM_MCSTAT_MIC_COMP     0x80000000  /* Mem init complete          */
-#define SDRAM_MCSTAT_SRMS_MASK      0x80000000  /* Mem self refresh stat mask */
-#define   SDRAM_MCSTAT_SRMS_NOT_SF  0x00000000  /* Mem not in self refresh    */
-#define   SDRAM_MCSTAT_SRMS_SF      0x80000000  /* Mem in self refresh        */
+#define SDRAM_MCSTAT_MIC_MASK	    0x80000000	/* Memory init status mask    */
+#define   SDRAM_MCSTAT_MIC_NOTCOMP  0x00000000	/* Mem init not complete      */
+#define   SDRAM_MCSTAT_MIC_COMP     0x80000000	/* Mem init complete	      */
+#define SDRAM_MCSTAT_SRMS_MASK	    0x80000000	/* Mem self refresh stat mask */
+#define   SDRAM_MCSTAT_SRMS_NOT_SF  0x00000000	/* Mem not in self refresh    */
+#define   SDRAM_MCSTAT_SRMS_SF	    0x80000000	/* Mem in self refresh	      */
 
 /*-----------------------------------------------------------------------------+
 |  Memory Controller Options 1
 +-----------------------------------------------------------------------------*/
-#define SDRAM_MCOPT1_MCHK_MASK       0x30000000 /* Memory data err check mask */
-#define   SDRAM_MCOPT1_MCHK_NON      0x00000000 /* No ECC generation          */
-#define   SDRAM_MCOPT1_MCHK_GEN      0x20000000 /* ECC generation             */
+#define SDRAM_MCOPT1_MCHK_MASK	     0x30000000 /* Memory data err check mask */
+#define   SDRAM_MCOPT1_MCHK_NON      0x00000000 /* No ECC generation	      */
+#define   SDRAM_MCOPT1_MCHK_GEN      0x20000000 /* ECC generation	      */
 #define   SDRAM_MCOPT1_MCHK_CHK      0x10000000 /* ECC generation and check   */
 #define   SDRAM_MCOPT1_MCHK_CHK_REP  0x30000000 /* ECC generation, chk, report*/
 #define   SDRAM_MCOPT1_MCHK_CHK_DECODE(n)  ((((unsigned long)(n))>>28)&0x3)
-#define SDRAM_MCOPT1_RDEN_MASK       0x08000000 /* Registered DIMM mask       */
-#define   SDRAM_MCOPT1_RDEN          0x08000000 /* Registered DIMM enable     */
-#define SDRAM_MCOPT1_PMU_MASK        0x06000000 /* Page management unit mask  */
-#define   SDRAM_MCOPT1_PMU_CLOSE     0x00000000 /* PMU Close                  */
-#define   SDRAM_MCOPT1_PMU_OPEN      0x04000000 /* PMU Open                   */
-#define   SDRAM_MCOPT1_PMU_AUTOCLOSE 0x02000000 /* PMU AutoClose              */
-#define SDRAM_MCOPT1_DMWD_MASK       0x01000000 /* DRAM width mask            */
-#define   SDRAM_MCOPT1_DMWD_32       0x00000000 /* 32 bits                    */
-#define   SDRAM_MCOPT1_DMWD_64       0x01000000 /* 64 bits                    */
-#define SDRAM_MCOPT1_UIOS_MASK       0x00C00000 /* Unused IO State            */
-#define SDRAM_MCOPT1_BCNT_MASK       0x00200000 /* Bank count                 */
-#define   SDRAM_MCOPT1_4_BANKS       0x00000000 /* 4 Banks                    */
-#define   SDRAM_MCOPT1_8_BANKS       0x00200000 /* 8 Banks                    */
+#define SDRAM_MCOPT1_RDEN_MASK	     0x08000000 /* Registered DIMM mask       */
+#define   SDRAM_MCOPT1_RDEN	     0x08000000 /* Registered DIMM enable     */
+#define SDRAM_MCOPT1_PMU_MASK	     0x06000000 /* Page management unit mask  */
+#define   SDRAM_MCOPT1_PMU_CLOSE     0x00000000 /* PMU Close		      */
+#define   SDRAM_MCOPT1_PMU_OPEN      0x04000000 /* PMU Open		      */
+#define   SDRAM_MCOPT1_PMU_AUTOCLOSE 0x02000000 /* PMU AutoClose	      */
+#define SDRAM_MCOPT1_DMWD_MASK	     0x01000000 /* DRAM width mask	      */
+#define   SDRAM_MCOPT1_DMWD_32	     0x00000000 /* 32 bits		      */
+#define   SDRAM_MCOPT1_DMWD_64	     0x01000000 /* 64 bits		      */
+#define SDRAM_MCOPT1_UIOS_MASK	     0x00C00000 /* Unused IO State	      */
+#define SDRAM_MCOPT1_BCNT_MASK	     0x00200000 /* Bank count		      */
+#define   SDRAM_MCOPT1_4_BANKS	     0x00000000 /* 4 Banks		      */
+#define   SDRAM_MCOPT1_8_BANKS	     0x00200000 /* 8 Banks		      */
 #define SDRAM_MCOPT1_DDR_TYPE_MASK   0x00100000 /* DDR Memory Type mask       */
-#define   SDRAM_MCOPT1_DDR1_TYPE     0x00000000 /* DDR1 Memory Type           */
-#define   SDRAM_MCOPT1_DDR2_TYPE     0x00100000 /* DDR2 Memory Type           */
-#define   SDRAM_MCOPT1_QDEP          0x00020000 /* 4 commands deep            */
-#define SDRAM_MCOPT1_RWOO_MASK       0x00008000 /* Out of Order Read mask     */
-#define   SDRAM_MCOPT1_RWOO_DISABLED 0x00000000 /* disabled                   */
-#define   SDRAM_MCOPT1_RWOO_ENABLED  0x00008000 /* enabled                    */
-#define SDRAM_MCOPT1_WOOO_MASK       0x00004000 /* Out of Order Write mask    */
-#define   SDRAM_MCOPT1_WOOO_DISABLED 0x00000000 /* disabled                   */
-#define   SDRAM_MCOPT1_WOOO_ENABLED  0x00004000 /* enabled                    */
-#define SDRAM_MCOPT1_DCOO_MASK       0x00002000 /* All Out of Order mask      */
-#define   SDRAM_MCOPT1_DCOO_DISABLED 0x00002000 /* disabled                   */
-#define   SDRAM_MCOPT1_DCOO_ENABLED  0x00000000 /* enabled                    */
-#define SDRAM_MCOPT1_DREF_MASK       0x00001000 /* Deferred refresh mask      */
-#define   SDRAM_MCOPT1_DREF_NORMAL   0x00000000 /* normal refresh             */
+#define   SDRAM_MCOPT1_DDR1_TYPE     0x00000000 /* DDR1 Memory Type	      */
+#define   SDRAM_MCOPT1_DDR2_TYPE     0x00100000 /* DDR2 Memory Type	      */
+#define   SDRAM_MCOPT1_QDEP	     0x00020000 /* 4 commands deep	      */
+#define SDRAM_MCOPT1_RWOO_MASK	     0x00008000 /* Out of Order Read mask     */
+#define   SDRAM_MCOPT1_RWOO_DISABLED 0x00000000 /* disabled		      */
+#define   SDRAM_MCOPT1_RWOO_ENABLED  0x00008000 /* enabled		      */
+#define SDRAM_MCOPT1_WOOO_MASK	     0x00004000 /* Out of Order Write mask    */
+#define   SDRAM_MCOPT1_WOOO_DISABLED 0x00000000 /* disabled		      */
+#define   SDRAM_MCOPT1_WOOO_ENABLED  0x00004000 /* enabled		      */
+#define SDRAM_MCOPT1_DCOO_MASK	     0x00002000 /* All Out of Order mask      */
+#define   SDRAM_MCOPT1_DCOO_DISABLED 0x00002000 /* disabled		      */
+#define   SDRAM_MCOPT1_DCOO_ENABLED  0x00000000 /* enabled		      */
+#define SDRAM_MCOPT1_DREF_MASK	     0x00001000 /* Deferred refresh mask      */
+#define   SDRAM_MCOPT1_DREF_NORMAL   0x00000000 /* normal refresh	      */
 #define   SDRAM_MCOPT1_DREF_DEFER_4  0x00001000 /* defer up to 4 refresh cmd  */
 
 /*-----------------------------------------------------------------------------+
 |  Memory Controller Options 2
 +-----------------------------------------------------------------------------*/
-#define SDRAM_MCOPT2_SREN_MASK        0x80000000 /* Self Test mask            */
-#define   SDRAM_MCOPT2_SREN_EXIT      0x00000000 /* Self Test exit            */
-#define   SDRAM_MCOPT2_SREN_ENTER     0x80000000 /* Self Test enter           */
-#define SDRAM_MCOPT2_PMEN_MASK        0x40000000 /* Power Management mask     */
-#define   SDRAM_MCOPT2_PMEN_DISABLE   0x00000000 /* disable                   */
-#define   SDRAM_MCOPT2_PMEN_ENABLE    0x40000000 /* enable                    */
-#define SDRAM_MCOPT2_IPTR_MASK        0x20000000 /* Init Trigger Reg mask     */
-#define   SDRAM_MCOPT2_IPTR_IDLE      0x00000000 /* idle                      */
+#define SDRAM_MCOPT2_SREN_MASK	      0x80000000 /* Self Test mask	      */
+#define   SDRAM_MCOPT2_SREN_EXIT      0x00000000 /* Self Test exit	      */
+#define   SDRAM_MCOPT2_SREN_ENTER     0x80000000 /* Self Test enter	      */
+#define SDRAM_MCOPT2_PMEN_MASK	      0x40000000 /* Power Management mask     */
+#define   SDRAM_MCOPT2_PMEN_DISABLE   0x00000000 /* disable		      */
+#define   SDRAM_MCOPT2_PMEN_ENABLE    0x40000000 /* enable		      */
+#define SDRAM_MCOPT2_IPTR_MASK	      0x20000000 /* Init Trigger Reg mask     */
+#define   SDRAM_MCOPT2_IPTR_IDLE      0x00000000 /* idle		      */
 #define   SDRAM_MCOPT2_IPTR_EXECUTE   0x20000000 /* execute preloaded init    */
-#define SDRAM_MCOPT2_XSRP_MASK        0x10000000 /* Exit Self Refresh Prevent */
+#define SDRAM_MCOPT2_XSRP_MASK	      0x10000000 /* Exit Self Refresh Prevent */
 #define   SDRAM_MCOPT2_XSRP_ALLOW     0x00000000 /* allow self refresh exit   */
 #define   SDRAM_MCOPT2_XSRP_PREVENT   0x10000000 /* prevent self refresh exit */
-#define SDRAM_MCOPT2_DCEN_MASK        0x08000000 /* SDRAM Controller Enable   */
+#define SDRAM_MCOPT2_DCEN_MASK	      0x08000000 /* SDRAM Controller Enable   */
 #define   SDRAM_MCOPT2_DCEN_DISABLE   0x00000000 /* SDRAM Controller Enable   */
 #define   SDRAM_MCOPT2_DCEN_ENABLE    0x08000000 /* SDRAM Controller Enable   */
-#define SDRAM_MCOPT2_ISIE_MASK        0x04000000 /* Init Seq Interruptable mas*/
-#define   SDRAM_MCOPT2_ISIE_DISABLE   0x00000000 /* disable                   */
-#define   SDRAM_MCOPT2_ISIE_ENABLE    0x04000000 /* enable                    */
+#define SDRAM_MCOPT2_ISIE_MASK	      0x04000000 /* Init Seq Interruptable mas*/
+#define   SDRAM_MCOPT2_ISIE_DISABLE   0x00000000 /* disable		      */
+#define   SDRAM_MCOPT2_ISIE_ENABLE    0x04000000 /* enable		      */
 
 /*-----------------------------------------------------------------------------+
 |  SDRAM Refresh Timer Register
 +-----------------------------------------------------------------------------*/
-#define SDRAM_RTR_RINT_MASK       0xFFF80000
-#define   SDRAM_RTR_RINT_ENCODE(n)  ((((unsigned long)(n))&0xFFF8)<<16)
-#define   SDRAM_RTR_RINT_DECODE(n)  ((((unsigned long)(n))>>16)&0xFFF8)
+#define SDRAM_RTR_RINT_MASK		0xFFF80000
+#define   SDRAM_RTR_RINT_ENCODE(n)	((((unsigned long)(n))&0xFFF8)<<16)
+#define   SDRAM_RTR_RINT_DECODE(n)	((((unsigned long)(n))>>16)&0xFFF8)
 
 /*-----------------------------------------------------------------------------+
 |  SDRAM Read DQS Delay Control Register
 +-----------------------------------------------------------------------------*/
-#define SDRAM_RQDC_RQDE_MASK        0x80000000
-#define   SDRAM_RQDC_RQDE_DISABLE   0x00000000
-#define   SDRAM_RQDC_RQDE_ENABLE    0x80000000
-#define SDRAM_RQDC_RQFD_MASK        0x000001FF
-#define   SDRAM_RQDC_RQFD_ENCODE(n) ((((unsigned long)(n))&0x1FF)<<0)
+#define SDRAM_RQDC_RQDE_MASK		0x80000000
+#define   SDRAM_RQDC_RQDE_DISABLE	0x00000000
+#define   SDRAM_RQDC_RQDE_ENABLE	0x80000000
+#define SDRAM_RQDC_RQFD_MASK		0x000001FF
+#define   SDRAM_RQDC_RQFD_ENCODE(n)	((((unsigned long)(n))&0x1FF)<<0)
 
-#define SDRAM_RQDC_RQFD_MAX         0xFF
+#define SDRAM_RQDC_RQFD_MAX		0xFF
 
 /*-----------------------------------------------------------------------------+
 |  SDRAM Read Data Capture Control Register
 +-----------------------------------------------------------------------------*/
-#define SDRAM_RDCC_RDSS_MASK        0xC0000000
-#define   SDRAM_RDCC_RDSS_T1        0x00000000
-#define   SDRAM_RDCC_RDSS_T2        0x40000000
-#define   SDRAM_RDCC_RDSS_T3        0x80000000
-#define   SDRAM_RDCC_RDSS_T4        0xC0000000
-#define SDRAM_RDCC_RSAE_MASK        0x00000001
-#define   SDRAM_RDCC_RSAE_DISABLE   0x00000001
-#define   SDRAM_RDCC_RSAE_ENABLE    0x00000000
+#define SDRAM_RDCC_RDSS_MASK		0xC0000000
+#define   SDRAM_RDCC_RDSS_T1		0x00000000
+#define   SDRAM_RDCC_RDSS_T2		0x40000000
+#define   SDRAM_RDCC_RDSS_T3		0x80000000
+#define   SDRAM_RDCC_RDSS_T4		0xC0000000
+#define SDRAM_RDCC_RSAE_MASK		0x00000001
+#define   SDRAM_RDCC_RSAE_DISABLE	0x00000001
+#define   SDRAM_RDCC_RSAE_ENABLE	0x00000000
 
 /*-----------------------------------------------------------------------------+
 |  SDRAM Read Feedback Delay Control Register
 +-----------------------------------------------------------------------------*/
-#define SDRAM_RFDC_ARSE_MASK        0x80000000
-#define   SDRAM_RFDC_ARSE_DISABLE   0x80000000
-#define   SDRAM_RFDC_ARSE_ENABLE    0x00000000
-#define SDRAM_RFDC_RFOS_MASK        0x007F0000
-#define   SDRAM_RFDC_RFOS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
-#define SDRAM_RFDC_RFFD_MASK        0x000003FF
-#define   SDRAM_RFDC_RFFD_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0)
+#define SDRAM_RFDC_ARSE_MASK		0x80000000
+#define   SDRAM_RFDC_ARSE_DISABLE	0x80000000
+#define   SDRAM_RFDC_ARSE_ENABLE	0x00000000
+#define SDRAM_RFDC_RFOS_MASK		0x007F0000
+#define   SDRAM_RFDC_RFOS_ENCODE(n)	((((unsigned long)(n))&0x7F)<<16)
+#define SDRAM_RFDC_RFFD_MASK		0x000003FF
+#define   SDRAM_RFDC_RFFD_ENCODE(n)	((((unsigned long)(n))&0x3FF)<<0)
 
-#define SDRAM_RFDC_RFFD_MAX         0x4FF
+#define SDRAM_RFDC_RFFD_MAX		0x4FF
 
 /*-----------------------------------------------------------------------------+
 |  SDRAM Delay Line Calibration Register
 +-----------------------------------------------------------------------------*/
-#define SDRAM_DLCR_DCLM_MASK          0x80000000
-#define   SDRAM_DLCR_DCLM_MANUEL      0x80000000
-#define   SDRAM_DLCR_DCLM_AUTO        0x00000000
-#define SDRAM_DLCR_DLCR_MASK          0x08000000
-#define   SDRAM_DLCR_DLCR_CALIBRATE   0x08000000
-#define   SDRAM_DLCR_DLCR_IDLE        0x00000000
-#define SDRAM_DLCR_DLCS_MASK          0x07000000
-#define   SDRAM_DLCR_DLCS_NOT_RUN     0x00000000
-#define   SDRAM_DLCR_DLCS_IN_PROGRESS 0x01000000
-#define   SDRAM_DLCR_DLCS_COMPLETE    0x02000000
-#define   SDRAM_DLCR_DLCS_CONT_DONE   0x03000000
-#define   SDRAM_DLCR_DLCS_ERROR       0x04000000
-#define SDRAM_DLCR_DLCV_MASK          0x000001FF
-#define   SDRAM_DLCR_DLCV_ENCODE(n) ((((unsigned long)(n))&0x1FF)<<0)
-#define   SDRAM_DLCR_DLCV_DECODE(n) ((((unsigned long)(n))>>0)&0x1FF)
+#define SDRAM_DLCR_DCLM_MASK		0x80000000
+#define   SDRAM_DLCR_DCLM_MANUEL	0x80000000
+#define   SDRAM_DLCR_DCLM_AUTO		0x00000000
+#define SDRAM_DLCR_DLCR_MASK		0x08000000
+#define   SDRAM_DLCR_DLCR_CALIBRATE	0x08000000
+#define   SDRAM_DLCR_DLCR_IDLE		0x00000000
+#define SDRAM_DLCR_DLCS_MASK		0x07000000
+#define   SDRAM_DLCR_DLCS_NOT_RUN	0x00000000
+#define   SDRAM_DLCR_DLCS_IN_PROGRESS	0x01000000
+#define   SDRAM_DLCR_DLCS_COMPLETE	0x02000000
+#define   SDRAM_DLCR_DLCS_CONT_DONE	0x03000000
+#define   SDRAM_DLCR_DLCS_ERROR	0x04000000
+#define SDRAM_DLCR_DLCV_MASK		0x000001FF
+#define   SDRAM_DLCR_DLCV_ENCODE(n)	((((unsigned long)(n))&0x1FF)<<0)
+#define   SDRAM_DLCR_DLCV_DECODE(n)	((((unsigned long)(n))>>0)&0x1FF)
 
 /*-----------------------------------------------------------------------------+
 |  SDRAM Controller On Die Termination Register
 +-----------------------------------------------------------------------------*/
-#define   SDRAM_CODT_ODT_ON                   0x80000000
-#define   SDRAM_CODT_ODT_OFF                  0x00000000
-#define SDRAM_CODT_DQS_VOLTAGE_DDR_MASK       0x00000020
-#define   SDRAM_CODT_DQS_2_5_V_DDR1           0x00000000
-#define   SDRAM_CODT_DQS_1_8_V_DDR2           0x00000020
-#define SDRAM_CODT_DQS_MASK                   0x00000010
-#define   SDRAM_CODT_DQS_DIFFERENTIAL         0x00000000
-#define   SDRAM_CODT_DQS_SINGLE_END           0x00000010
-#define   SDRAM_CODT_CKSE_DIFFERENTIAL         	0x00000000
-#define   SDRAM_CODT_CKSE_SINGLE_END           	0x00000008
-#define   SDRAM_CODT_FEEBBACK_RCV_SINGLE_END  0x00000004
-#define   SDRAM_CODT_FEEBBACK_DRV_SINGLE_END  0x00000002
-#define   SDRAM_CODT_IO_HIZ  					0x00000000
-#define   SDRAM_CODT_IO_NMODE  					0x00000001
+#define   SDRAM_CODT_ODT_ON			0x80000000
+#define   SDRAM_CODT_ODT_OFF			0x00000000
+#define SDRAM_CODT_DQS_VOLTAGE_DDR_MASK	0x00000020
+#define   SDRAM_CODT_DQS_2_5_V_DDR1		0x00000000
+#define   SDRAM_CODT_DQS_1_8_V_DDR2		0x00000020
+#define SDRAM_CODT_DQS_MASK			0x00000010
+#define   SDRAM_CODT_DQS_DIFFERENTIAL		0x00000000
+#define   SDRAM_CODT_DQS_SINGLE_END		0x00000010
+#define   SDRAM_CODT_CKSE_DIFFERENTIAL		0x00000000
+#define   SDRAM_CODT_CKSE_SINGLE_END		0x00000008
+#define   SDRAM_CODT_FEEBBACK_RCV_SINGLE_END	0x00000004
+#define   SDRAM_CODT_FEEBBACK_DRV_SINGLE_END	0x00000002
+#define   SDRAM_CODT_IO_HIZ			0x00000000
+#define   SDRAM_CODT_IO_NMODE			0x00000001
 
 /*-----------------------------------------------------------------------------+
 |  SDRAM Mode Register
 +-----------------------------------------------------------------------------*/
-#define SDRAM_MMODE_WR_MASK              0x00000E00
-#define   SDRAM_MMODE_WR_DDR1            0x00000000
-#define   SDRAM_MMODE_WR_DDR2_3_CYC      0x00000400
-#define   SDRAM_MMODE_WR_DDR2_4_CYC      0x00000600
-#define   SDRAM_MMODE_WR_DDR2_5_CYC      0x00000800
-#define   SDRAM_MMODE_WR_DDR2_6_CYC      0x00000A00
-#define SDRAM_MMODE_DCL_MASK             0x00000070
-#define   SDRAM_MMODE_DCL_DDR1_2_0_CLK   0x00000020
-#define   SDRAM_MMODE_DCL_DDR1_2_5_CLK   0x00000060
-#define   SDRAM_MMODE_DCL_DDR1_3_0_CLK   0x00000030
-#define   SDRAM_MMODE_DCL_DDR2_2_0_CLK   0x00000020
-#define   SDRAM_MMODE_DCL_DDR2_3_0_CLK   0x00000030
-#define   SDRAM_MMODE_DCL_DDR2_4_0_CLK   0x00000040
-#define   SDRAM_MMODE_DCL_DDR2_5_0_CLK   0x00000050
-#define   SDRAM_MMODE_DCL_DDR2_6_0_CLK   0x00000060
-#define   SDRAM_MMODE_DCL_DDR2_7_0_CLK   0x00000070
+#define SDRAM_MMODE_WR_MASK			0x00000E00
+#define   SDRAM_MMODE_WR_DDR1			0x00000000
+#define   SDRAM_MMODE_WR_DDR2_3_CYC		0x00000400
+#define   SDRAM_MMODE_WR_DDR2_4_CYC		0x00000600
+#define   SDRAM_MMODE_WR_DDR2_5_CYC		0x00000800
+#define   SDRAM_MMODE_WR_DDR2_6_CYC		0x00000A00
+#define SDRAM_MMODE_DCL_MASK			0x00000070
+#define   SDRAM_MMODE_DCL_DDR1_2_0_CLK		0x00000020
+#define   SDRAM_MMODE_DCL_DDR1_2_5_CLK		0x00000060
+#define   SDRAM_MMODE_DCL_DDR1_3_0_CLK		0x00000030
+#define   SDRAM_MMODE_DCL_DDR2_2_0_CLK		0x00000020
+#define   SDRAM_MMODE_DCL_DDR2_3_0_CLK		0x00000030
+#define   SDRAM_MMODE_DCL_DDR2_4_0_CLK		0x00000040
+#define   SDRAM_MMODE_DCL_DDR2_5_0_CLK		0x00000050
+#define   SDRAM_MMODE_DCL_DDR2_6_0_CLK		0x00000060
+#define   SDRAM_MMODE_DCL_DDR2_7_0_CLK		0x00000070
 
 /*-----------------------------------------------------------------------------+
 |  SDRAM Extended Mode Register
 +-----------------------------------------------------------------------------*/
-#define SDRAM_MEMODE_DIC_MASK            0x00000002
-#define   SDRAM_MEMODE_DIC_NORMAL        0x00000000
-#define   SDRAM_MEMODE_DIC_WEAK          0x00000002
-#define SDRAM_MEMODE_DLL_MASK            0x00000001
-#define   SDRAM_MEMODE_DLL_DISABLE       0x00000001
-#define   SDRAM_MEMODE_DLL_ENABLE        0x00000000
-#define SDRAM_MEMODE_RTT_MASK 		     0x00000044
-#define   SDRAM_MEMODE_RTT_DISABLED      0x00000000
-#define   SDRAM_MEMODE_RTT_75OHM         0x00000004
-#define   SDRAM_MEMODE_RTT_150OHM        0x00000040
-#define SDRAM_MEMODE_DQS_MASK            0x00000400
-#define   SDRAM_MEMODE_DQS_DISABLE       0x00000400
-#define   SDRAM_MEMODE_DQS_ENABLE        0x00000000
+#define SDRAM_MEMODE_DIC_MASK			0x00000002
+#define   SDRAM_MEMODE_DIC_NORMAL		0x00000000
+#define   SDRAM_MEMODE_DIC_WEAK			0x00000002
+#define SDRAM_MEMODE_DLL_MASK			0x00000001
+#define   SDRAM_MEMODE_DLL_DISABLE		0x00000001
+#define   SDRAM_MEMODE_DLL_ENABLE		0x00000000
+#define SDRAM_MEMODE_RTT_MASK			0x00000044
+#define   SDRAM_MEMODE_RTT_DISABLED		0x00000000
+#define   SDRAM_MEMODE_RTT_75OHM		0x00000004
+#define   SDRAM_MEMODE_RTT_150OHM		0x00000040
+#define SDRAM_MEMODE_DQS_MASK			0x00000400
+#define   SDRAM_MEMODE_DQS_DISABLE		0x00000400
+#define   SDRAM_MEMODE_DQS_ENABLE		0x00000000
 
 /*-----------------------------------------------------------------------------+
 |  SDRAM Clock Timing Register
 +-----------------------------------------------------------------------------*/
-#define SDRAM_CLKTR_CLKP_MASK            0xC0000000
-#define   SDRAM_CLKTR_CLKP_0_DEG         0x00000000
-#define   SDRAM_CLKTR_CLKP_180_DEG_ADV   0x80000000
+#define SDRAM_CLKTR_CLKP_MASK			0xC0000000
+#define   SDRAM_CLKTR_CLKP_0_DEG		0x00000000
+#define   SDRAM_CLKTR_CLKP_180_DEG_ADV		0x80000000
 
 /*-----------------------------------------------------------------------------+
 |  SDRAM Write Timing Register
 +-----------------------------------------------------------------------------*/
-#define SDRAM_WRDTR_WDTP_1_CYC		 0x80000000
-#define SDRAM_WRDTR_LLWP_MASK            0x10000000
-#define   SDRAM_WRDTR_LLWP_DIS           0x10000000
-#define   SDRAM_WRDTR_LLWP_1_CYC         0x00000000
-#define SDRAM_WRDTR_WTR_MASK             0x0E000000
-#define   SDRAM_WRDTR_WTR_0_DEG          0x06000000
-#define   SDRAM_WRDTR_WTR_180_DEG_ADV    0x02000000
-#define   SDRAM_WRDTR_WTR_270_DEG_ADV    0x00000000
+#define SDRAM_WRDTR_WDTP_1_CYC			0x80000000
+#define SDRAM_WRDTR_LLWP_MASK			0x10000000
+#define   SDRAM_WRDTR_LLWP_DIS			0x10000000
+#define   SDRAM_WRDTR_LLWP_1_CYC		0x00000000
+#define SDRAM_WRDTR_WTR_MASK			0x0E000000
+#define   SDRAM_WRDTR_WTR_0_DEG			0x06000000
+#define   SDRAM_WRDTR_WTR_180_DEG_ADV		0x02000000
+#define   SDRAM_WRDTR_WTR_270_DEG_ADV		0x00000000
 
 /*-----------------------------------------------------------------------------+
 |  SDRAM SDTR1 Options
 +-----------------------------------------------------------------------------*/
-#define SDRAM_SDTR1_LDOF_MASK        0x80000000
-#define   SDRAM_SDTR1_LDOF_1_CLK     0x00000000
-#define   SDRAM_SDTR1_LDOF_2_CLK     0x80000000
-#define SDRAM_SDTR1_RTW_MASK         0x00F00000
-#define   SDRAM_SDTR1_RTW_2_CLK      0x00200000
-#define   SDRAM_SDTR1_RTW_3_CLK      0x00300000
-#define SDRAM_SDTR1_WTWO_MASK        0x000F0000
-#define   SDRAM_SDTR1_WTWO_0_CLK     0x00000000
-#define   SDRAM_SDTR1_WTWO_1_CLK     0x00010000
-#define SDRAM_SDTR1_RTRO_MASK        0x0000F000
-#define   SDRAM_SDTR1_RTRO_1_CLK     0x00000000
-#define   SDRAM_SDTR1_RTRO_2_CLK     0x00002000
+#define SDRAM_SDTR1_LDOF_MASK			0x80000000
+#define   SDRAM_SDTR1_LDOF_1_CLK		0x00000000
+#define   SDRAM_SDTR1_LDOF_2_CLK		0x80000000
+#define SDRAM_SDTR1_RTW_MASK			0x00F00000
+#define   SDRAM_SDTR1_RTW_2_CLK		0x00200000
+#define   SDRAM_SDTR1_RTW_3_CLK		0x00300000
+#define SDRAM_SDTR1_WTWO_MASK			0x000F0000
+#define   SDRAM_SDTR1_WTWO_0_CLK		0x00000000
+#define   SDRAM_SDTR1_WTWO_1_CLK		0x00010000
+#define SDRAM_SDTR1_RTRO_MASK			0x0000F000
+#define   SDRAM_SDTR1_RTRO_1_CLK		0x00000000
+#define   SDRAM_SDTR1_RTRO_2_CLK		0x00002000
 
 /*-----------------------------------------------------------------------------+
 |  SDRAM SDTR2 Options
 +-----------------------------------------------------------------------------*/
-#define SDRAM_SDTR2_RCD_MASK         0xF0000000
-#define   SDRAM_SDTR2_RCD_1_CLK      0x10000000
-#define   SDRAM_SDTR2_RCD_2_CLK      0x20000000
-#define   SDRAM_SDTR2_RCD_3_CLK      0x30000000
-#define   SDRAM_SDTR2_RCD_4_CLK      0x40000000
-#define   SDRAM_SDTR2_RCD_5_CLK      0x50000000
-#define SDRAM_SDTR2_WTR_MASK         0x0F000000
+#define SDRAM_SDTR2_RCD_MASK			0xF0000000
+#define   SDRAM_SDTR2_RCD_1_CLK		0x10000000
+#define   SDRAM_SDTR2_RCD_2_CLK		0x20000000
+#define   SDRAM_SDTR2_RCD_3_CLK		0x30000000
+#define   SDRAM_SDTR2_RCD_4_CLK		0x40000000
+#define   SDRAM_SDTR2_RCD_5_CLK		0x50000000
+#define SDRAM_SDTR2_WTR_MASK		0x0F000000
 #define   SDRAM_SDTR2_WTR_1_CLK      0x01000000
 #define   SDRAM_SDTR2_WTR_2_CLK      0x02000000
 #define   SDRAM_SDTR2_WTR_3_CLK      0x03000000
 #define   SDRAM_SDTR2_WTR_4_CLK      0x04000000
 #define   SDRAM_SDTR3_WTR_ENCODE(n)  ((((unsigned long)(n))&0xF)<<24)
-#define SDRAM_SDTR2_XSNR_MASK        0x00FF0000
+#define SDRAM_SDTR2_XSNR_MASK	     0x00FF0000
 #define   SDRAM_SDTR2_XSNR_8_CLK     0x00080000
 #define   SDRAM_SDTR2_XSNR_16_CLK    0x00100000
 #define   SDRAM_SDTR2_XSNR_32_CLK    0x00200000
 #define   SDRAM_SDTR2_XSNR_64_CLK    0x00400000
-#define SDRAM_SDTR2_WPC_MASK         0x0000F000
+#define SDRAM_SDTR2_WPC_MASK	     0x0000F000
 #define   SDRAM_SDTR2_WPC_2_CLK      0x00002000
 #define   SDRAM_SDTR2_WPC_3_CLK      0x00003000
 #define   SDRAM_SDTR2_WPC_4_CLK      0x00004000
 #define   SDRAM_SDTR2_WPC_5_CLK      0x00005000
 #define   SDRAM_SDTR2_WPC_6_CLK      0x00006000
 #define   SDRAM_SDTR3_WPC_ENCODE(n)  ((((unsigned long)(n))&0xF)<<12)
-#define SDRAM_SDTR2_RPC_MASK         0x00000F00
+#define SDRAM_SDTR2_RPC_MASK	     0x00000F00
 #define   SDRAM_SDTR2_RPC_2_CLK      0x00000200
 #define   SDRAM_SDTR2_RPC_3_CLK      0x00000300
 #define   SDRAM_SDTR2_RPC_4_CLK      0x00000400
-#define SDRAM_SDTR2_RP_MASK          0x000000F0
-#define   SDRAM_SDTR2_RP_3_CLK       0x00000030
-#define   SDRAM_SDTR2_RP_4_CLK       0x00000040
-#define   SDRAM_SDTR2_RP_5_CLK       0x00000050
-#define   SDRAM_SDTR2_RP_6_CLK       0x00000060
-#define   SDRAM_SDTR2_RP_7_CLK       0x00000070
-#define SDRAM_SDTR2_RRD_MASK         0x0000000F
+#define SDRAM_SDTR2_RP_MASK	     0x000000F0
+#define   SDRAM_SDTR2_RP_3_CLK	     0x00000030
+#define   SDRAM_SDTR2_RP_4_CLK	     0x00000040
+#define   SDRAM_SDTR2_RP_5_CLK	     0x00000050
+#define   SDRAM_SDTR2_RP_6_CLK	     0x00000060
+#define   SDRAM_SDTR2_RP_7_CLK	     0x00000070
+#define SDRAM_SDTR2_RRD_MASK	     0x0000000F
 #define   SDRAM_SDTR2_RRD_2_CLK      0x00000002
 #define   SDRAM_SDTR2_RRD_3_CLK      0x00000003
 
 /*-----------------------------------------------------------------------------+
 |  SDRAM SDTR3 Options
 +-----------------------------------------------------------------------------*/
-#define SDRAM_SDTR3_RAS_MASK         0x1F000000
+#define SDRAM_SDTR3_RAS_MASK	     0x1F000000
 #define   SDRAM_SDTR3_RAS_ENCODE(n)  ((((unsigned long)(n))&0x1F)<<24)
-#define SDRAM_SDTR3_RC_MASK          0x001F0000
+#define SDRAM_SDTR3_RC_MASK	     0x001F0000
 #define   SDRAM_SDTR3_RC_ENCODE(n)   ((((unsigned long)(n))&0x1F)<<16)
-#define SDRAM_SDTR3_XCS_MASK         0x00001F00
-#define SDRAM_SDTR3_XCS              0x00000D00
-#define SDRAM_SDTR3_RFC_MASK         0x0000003F
+#define SDRAM_SDTR3_XCS_MASK	     0x00001F00
+#define SDRAM_SDTR3_XCS		     0x00000D00
+#define SDRAM_SDTR3_RFC_MASK	     0x0000003F
 #define   SDRAM_SDTR3_RFC_ENCODE(n)  ((((unsigned long)(n))&0x3F)<<0)
 
 /*-----------------------------------------------------------------------------+
 |  Memory Bank 0-1 configuration
 +-----------------------------------------------------------------------------*/
-#define SDRAM_BXCF_M_AM_MASK      0x00000F00      /* Addressing mode          */
-#define   SDRAM_BXCF_M_AM_0       0x00000000      /*   Mode 0                 */
-#define   SDRAM_BXCF_M_AM_1       0x00000100      /*   Mode 1                 */
-#define   SDRAM_BXCF_M_AM_2       0x00000200      /*   Mode 2                 */
-#define   SDRAM_BXCF_M_AM_3       0x00000300      /*   Mode 3                 */
-#define   SDRAM_BXCF_M_AM_4       0x00000400      /*   Mode 4                 */
-#define   SDRAM_BXCF_M_AM_5       0x00000500      /*   Mode 5                 */
-#define   SDRAM_BXCF_M_AM_6       0x00000600      /*   Mode 6                 */
-#define   SDRAM_BXCF_M_AM_7       0x00000700      /*   Mode 7                 */
-#define   SDRAM_BXCF_M_AM_8       0x00000800      /*   Mode 8                 */
-#define   SDRAM_BXCF_M_AM_9       0x00000900      /*   Mode 9                 */
-#define SDRAM_BXCF_M_BE_MASK      0x00000001      /* Memory Bank Enable       */
-#define   SDRAM_BXCF_M_BE_DISABLE 0x00000000      /* Memory Bank Enable       */
-#define   SDRAM_BXCF_M_BE_ENABLE  0x00000001      /* Memory Bank Enable       */
+#define SDRAM_BXCF_M_AM_MASK	  0x00000F00	  /* Addressing mode	      */
+#define   SDRAM_BXCF_M_AM_0	  0x00000000	  /*   Mode 0		      */
+#define   SDRAM_BXCF_M_AM_1	  0x00000100	  /*   Mode 1		      */
+#define   SDRAM_BXCF_M_AM_2	  0x00000200	  /*   Mode 2		      */
+#define   SDRAM_BXCF_M_AM_3	  0x00000300	  /*   Mode 3		      */
+#define   SDRAM_BXCF_M_AM_4	  0x00000400	  /*   Mode 4		      */
+#define   SDRAM_BXCF_M_AM_5	  0x00000500	  /*   Mode 5		      */
+#define   SDRAM_BXCF_M_AM_6	  0x00000600	  /*   Mode 6		      */
+#define   SDRAM_BXCF_M_AM_7	  0x00000700	  /*   Mode 7		      */
+#define   SDRAM_BXCF_M_AM_8	  0x00000800	  /*   Mode 8		      */
+#define   SDRAM_BXCF_M_AM_9	  0x00000900	  /*   Mode 9		      */
+#define SDRAM_BXCF_M_BE_MASK	  0x00000001	  /* Memory Bank Enable       */
+#define   SDRAM_BXCF_M_BE_DISABLE 0x00000000	  /* Memory Bank Enable       */
+#define   SDRAM_BXCF_M_BE_ENABLE  0x00000001	  /* Memory Bank Enable       */
 
 #define sdr_uart0	0x0120	/* UART0 Config */
 #define sdr_uart1	0x0121	/* UART1 Config */
 #define sdr_mfr		0x4300	/* SDR0_MFR reg */
 
 /* Defines for CPC0_EPRCSR register */
-#define CPC0_EPRCSR_E0NFE          0x80000000
-#define CPC0_EPRCSR_E1NFE          0x40000000
-#define CPC0_EPRCSR_E1RPP          0x00000080
-#define CPC0_EPRCSR_E0RPP          0x00000040
-#define CPC0_EPRCSR_E1ERP          0x00000020
-#define CPC0_EPRCSR_E0ERP          0x00000010
-#define CPC0_EPRCSR_E1PCI          0x00000002
-#define CPC0_EPRCSR_E0PCI          0x00000001
+#define CPC0_EPRCSR_E0NFE	   0x80000000
+#define CPC0_EPRCSR_E1NFE	   0x40000000
+#define CPC0_EPRCSR_E1RPP	   0x00000080
+#define CPC0_EPRCSR_E0RPP	   0x00000040
+#define CPC0_EPRCSR_E1ERP	   0x00000020
+#define CPC0_EPRCSR_E0ERP	   0x00000010
+#define CPC0_EPRCSR_E1PCI	   0x00000002
+#define CPC0_EPRCSR_E0PCI	   0x00000001
 
 #define cpr0_clkupd	0x020
 #define cpr0_pllc	0x040
@@ -1556,7 +1556,7 @@
 #define SDR0_SDCS_SDD			(0x80000000 >> 31)
 
 /* CUST0 Customer Configuration Register0 */
-#define SDR0_CUST0                   0x4000
+#define SDR0_CUST0		     0x4000
 #define   SDR0_CUST0_MUX_E_N_G_MASK   0xC0000000     /* Mux_Emac_NDFC_GPIO */
 #define   SDR0_CUST0_MUX_EMAC_SEL     0x40000000       /* Emac Selection */
 #define   SDR0_CUST0_MUX_NDFC_SEL     0x80000000       /* NDFC Selection */
@@ -1582,9 +1582,9 @@
 #define   SDR0_CUST0_NDFC_ARE_ENABLE  0x00200000       /* NDFC Auto Read Enable */
 #define   SDR0_CUST0_NDFC_ARE_DISABLE 0x00000000       /* NDFC Auto Read Disable */
 
-#define   SDR0_CUST0_NRB_MASK         0x00100000     /* NDFC Ready / Busy */
-#define   SDR0_CUST0_NRB_BUSY         0x00100000       /* Busy */
-#define   SDR0_CUST0_NRB_READY        0x00000000       /* Ready */
+#define   SDR0_CUST0_NRB_MASK	      0x00100000     /* NDFC Ready / Busy */
+#define   SDR0_CUST0_NRB_BUSY	      0x00100000       /* Busy */
+#define   SDR0_CUST0_NRB_READY	      0x00000000       /* Ready */
 
 #define   SDR0_CUST0_NDRSC_MASK       0x0000FFF0     /* NDFC Device Reset Count Mask */
 #define   SDR0_CUST0_NDRSC_ENCODE(n) ((((unsigned long)(n))&0xFFF)<<4)
diff --git a/include/ppc440.h b/include/ppc440.h
index 2f6ed97a62..54b4553139 100644
--- a/include/ppc440.h
+++ b/include/ppc440.h
@@ -2163,7 +2163,7 @@
 #define UIC_UIC3NC	0x00008000	/* UIC3 non-critical interrupt	    */
 #define UIC_UIC3C	0x00004000	/* UIC3 critical interrupt	    */
 #define UIC_EIR1	0x00002000	/* External interrupt 1		    */
-#define UIC_TRNGDA	0x00001000	/* TRNG data available 		    */
+#define UIC_TRNGDA	0x00001000	/* TRNG data available		    */
 #define UIC_PKAR1	0x00000800	/* PKA ready (PKA[1])		    */
 #define UIC_D1CPFF	0x00000400	/* DMA1 cp fifo full		    */
 #define UIC_D1CSNS	0x00000200	/* DMA1 cs fifo needs service	    */
diff --git a/include/ppc4xx_enet.h b/include/ppc4xx_enet.h
index 89ff26f991..4c97b36c05 100644
--- a/include/ppc4xx_enet.h
+++ b/include/ppc4xx_enet.h
@@ -318,9 +318,9 @@ typedef struct emac_4xx_hw_st {
 #endif
 #else
 #if defined(CONFIG_405EZ) || defined(CONFIG_405EX)
-#define EMAC_BASE 		0xEF600900
+#define EMAC_BASE		0xEF600900
 #else
-#define EMAC_BASE 		0xEF600800
+#define EMAC_BASE		0xEF600800
 #endif
 #endif
 
diff --git a/include/rtc.h b/include/rtc.h
index 2995144a0d..df2d35fe49 100644
--- a/include/rtc.h
+++ b/include/rtc.h
@@ -35,7 +35,7 @@
  * Note that there are small but significant differences to the
  * common "struct time":
  *
- * 		struct time:		struct rtc_time:
+ *		struct time:		struct rtc_time:
  * tm_mon	0 ... 11		1 ... 12
  * tm_year	years since 1900	years since 0
  */
diff --git a/include/s_record.h b/include/s_record.h
index 07806d5cd8..29d40b3bb4 100644
--- a/include/s_record.h
+++ b/include/s_record.h
@@ -97,9 +97,9 @@
 #define SREC_DATA3	2	/* Data  Record with 3 byte address	    */
 #define SREC_DATA4	3	/* Data  Record with 4 byte address	    */
 #define SREC_COUNT	5	/* Count Record (previously transmitted)    */
-#define SREC_END4 	7	/* End   Record with 4 byte start address   */
-#define SREC_END3 	8	/* End   Record with 3 byte start address   */
-#define SREC_END2 	9	/* End   Record with 2 byte start address   */
+#define SREC_END4	7	/* End   Record with 4 byte start address   */
+#define SREC_END3	8	/* End   Record with 3 byte start address   */
+#define SREC_END2	9	/* End   Record with 2 byte start address   */
 #define SREC_EMPTY	10	/* Empty Record without any data	    */
 
 #define SREC_REC_OK  SREC_EMPTY /* last code without error condition	    */
diff --git a/include/scsi.h b/include/scsi.h
index 2be4d4014a..aaafc9ca79 100644
--- a/include/scsi.h
+++ b/include/scsi.h
@@ -32,7 +32,7 @@ typedef struct SCSI_cmd_block{
 	unsigned char		lun;							/* Target LUN        */
 	unsigned char		cmdlen;						/* command len				*/
 	unsigned long		datalen;					/* Total data length	*/
-	unsigned char	*	pdata; 						/* pointer to data		*/
+	unsigned char	*	pdata;						/* pointer to data		*/
 	unsigned char		msgout[12];				/* Messge out buffer (NOT USED) */
 	unsigned char		msgin[12];				/* Message in buffer	*/
 	unsigned char		sensecmdlen;			/* Sense command len	*/
@@ -77,7 +77,7 @@ typedef struct SCSI_cmd_block{
 #define	M_HEAD_TAG	(0x21)
 #define	M_ORDERED_TAG	(0x22)
 #define	M_IGN_RESIDUE	(0x23)
-#define	M_IDENTIFY   	(0x80)
+#define	M_IDENTIFY	(0x80)
 
 #define	M_X_MODIFY_DP	(0x00)
 #define	M_X_SYNC_REQ	(0x01)
@@ -192,7 +192,7 @@ void scsi_init(void);
 /* Hardware errors  */
 #define SCSI_SEL_TIME_OUT			 0x00000101	 /* Selection time out */
 #define SCSI_HNS_TIME_OUT			 0x00000102  /* Handshake */
-#define SCSI_MA_TIME_OUT	 		 0x00000103  /* Phase error */
+#define SCSI_MA_TIME_OUT			 0x00000103  /* Phase error */
 #define SCSI_UNEXP_DIS				 0x00000104  /* unexpected disconnect */
 
 #define SCSI_INT_STATE				 0x00010000  /* unknown Interrupt number is stored in 16 LSB */
diff --git a/include/sed13806.h b/include/sed13806.h
index 216e7880af..07f45760c3 100644
--- a/include/sed13806.h
+++ b/include/sed13806.h
@@ -34,7 +34,7 @@
 
 #define DEFAULT_VIDEO_MEMORY_SIZE  0x140000     /* Video Memory Size */
 
-#define HWCURSORSIZE 		   1024     /* Size of memory reserved
+#define HWCURSORSIZE		   1024     /* Size of memory reserved
 						   for HW cursor*/
 
 /* Offset of chipset registers                                               */
diff --git a/include/spartan2.h b/include/spartan2.h
index bd159e1823..7327857c12 100644
--- a/include/spartan2.h
+++ b/include/spartan2.h
@@ -47,7 +47,7 @@ typedef struct {
 	Xilinx_busy_fn	busy;
 	Xilinx_abort_fn	abort;
 	Xilinx_post_fn	post;
-	int           	relocated;
+	int		relocated;
 } Xilinx_Spartan2_Slave_Parallel_fns;
 
 /* Slave Serial Implementation function table */
@@ -59,18 +59,18 @@ typedef struct {
 	Xilinx_done_fn	done;
 	Xilinx_wr_fn	wr;
 	Xilinx_post_fn	post;
-	int           	relocated;
+	int		relocated;
 } Xilinx_Spartan2_Slave_Serial_fns;
 
 /* Device Image Sizes
  *********************************************************************/
 /* Spartan-II (2.5V) */
-#define XILINX_XC2S15_SIZE  	197728/8
-#define XILINX_XC2S30_SIZE  	336800/8
-#define XILINX_XC2S50_SIZE  	559232/8
-#define XILINX_XC2S100_SIZE 	781248/8
-#define XILINX_XC2S150_SIZE 	1040128/8
-#define XILINX_XC2S200_SIZE 	1335872/8
+#define XILINX_XC2S15_SIZE	197728/8
+#define XILINX_XC2S30_SIZE	336800/8
+#define XILINX_XC2S50_SIZE	559232/8
+#define XILINX_XC2S100_SIZE	781248/8
+#define XILINX_XC2S150_SIZE	1040128/8
+#define XILINX_XC2S200_SIZE	1335872/8
 
 /* Spartan-IIE (1.8V) */
 #define XILINX_XC2S50E_SIZE     630048/8
diff --git a/include/spartan3.h b/include/spartan3.h
index c203eeb580..9a3a5d49bc 100644
--- a/include/spartan3.h
+++ b/include/spartan3.h
@@ -47,7 +47,7 @@ typedef struct {
 	Xilinx_busy_fn	busy;
 	Xilinx_abort_fn	abort;
 	Xilinx_post_fn	post;
-	int           	relocated;
+	int		relocated;
 } Xilinx_Spartan3_Slave_Parallel_fns;
 
 /* Slave Serial Implementation function table */
@@ -59,20 +59,20 @@ typedef struct {
 	Xilinx_done_fn	done;
 	Xilinx_wr_fn	wr;
 	Xilinx_post_fn	post;
-	int           	relocated;
+	int		relocated;
 } Xilinx_Spartan3_Slave_Serial_fns;
 
 /* Device Image Sizes
  *********************************************************************/
 /* Spartan-III (1.2V) */
-#define XILINX_XC3S50_SIZE  	439264/8
-#define XILINX_XC3S200_SIZE  	1047616/8
-#define XILINX_XC3S400_SIZE  	1699136/8
-#define XILINX_XC3S1000_SIZE 	3223488/8
-#define XILINX_XC3S1500_SIZE 	5214784/8
-#define XILINX_XC3S2000_SIZE 	7673024/8
-#define XILINX_XC3S4000_SIZE 	11316864/8
-#define XILINX_XC3S5000_SIZE 	13271936/8
+#define XILINX_XC3S50_SIZE	439264/8
+#define XILINX_XC3S200_SIZE	1047616/8
+#define XILINX_XC3S400_SIZE	1699136/8
+#define XILINX_XC3S1000_SIZE	3223488/8
+#define XILINX_XC3S1500_SIZE	5214784/8
+#define XILINX_XC3S2000_SIZE	7673024/8
+#define XILINX_XC3S4000_SIZE	11316864/8
+#define XILINX_XC3S5000_SIZE	13271936/8
 
 /* Spartan-3E (v3.4) */
 #define	XILINX_XC3S100E_SIZE	581344/8
@@ -82,7 +82,7 @@ typedef struct {
 #define	XILINX_XC3S1600E_SIZE	5969696/8
 
 /* Spartan-IIIE (1.2V) */
-#define XILINX_XC3S1200E_SIZE  	3841184/8
+#define XILINX_XC3S1200E_SIZE	3841184/8
 
 /* Descriptor Macros
  *********************************************************************/
diff --git a/include/sym53c8xx.h b/include/sym53c8xx.h
index 0734fe4f0c..7d3ded5fe8 100644
--- a/include/sym53c8xx.h
+++ b/include/sym53c8xx.h
@@ -33,7 +33,7 @@
 #define SCNTL0		0x00    /* full arb., ena parity, par->ATN  */
 
 #define SCNTL1		0x01    /* no reset                         */
-  #define   ISCON   0x10  /* connected to scsi		    				*/
+  #define   ISCON   0x10  /* connected to scsi						*/
   #define   CRST    0x08  /* force reset                      */
   #define   IARB    0x02  /* immediate arbitration            */
 
@@ -128,7 +128,7 @@
 
 #define CTEST3		0x1b
 	#define   FLF     0x08  /* cmd: flush dma fifo              */
-	#define   CLF	  	0x04	/* cmd: clear dma fifo		    */
+	#define   CLF		0x04	/* cmd: clear dma fifo		    */
 	#define   FM      0x02  /* mod: fetch pin mode              */
 	#define   WRIE    0x01  /* mod: write and invalidate enable */
 				/* bits 4-7 rsvd for C1010          */
@@ -219,7 +219,7 @@
 
 #define SIDL			0x50	/* Lowlevel: latched from scsi data */
 #define STEST4		0x52
-	#define SMODE  	0xc0	/* SCSI bus mode      (895/6 only) */
+	#define SMODE	0xc0	/* SCSI bus mode      (895/6 only) */
 	#define SMODE_HVD 0x40	/* High Voltage Differential       */
 	#define SMODE_SE  0x80	/* Single Ended                    */
 	#define SMODE_LVD 0xc0	/* Low Voltage Differential        */
@@ -435,7 +435,7 @@
 **	LOAD_REG (reg, data)	  reg  = <data>
 **	<< 0 >>
 **
-**	LOAD_SFBR(data) 	  SFBR = <data>
+**	LOAD_SFBR(data)		  SFBR = <data>
 **	<< 0 >>
 **
 **-----------------------------------------------------------
diff --git a/include/usbdcore_mpc8xx.h b/include/usbdcore_mpc8xx.h
index 9df62f4ca5..039d245057 100644
--- a/include/usbdcore_mpc8xx.h
+++ b/include/usbdcore_mpc8xx.h
@@ -176,7 +176,7 @@ typedef struct endpoint_parameter_block_pointer{
 	char rfcr;	/* Rx Function code */
 	char tfcr;	/* Tx Function code */
 	ushort mrblr;	/* Maximum Receive Buffer Length */
-	ushort rbptr; 	/* RxBD pointer Next Buffer Descriptor */
+	ushort rbptr;	/* RxBD pointer Next Buffer Descriptor */
 	ushort tbptr;	/* TxBD pointer Next Buffer Descriptor  */
 	ulong tstate;	/* Transmit internal state */
 	ulong tptr;	/* Transmit internal data pointer */
diff --git a/include/video_easylogo.h b/include/video_easylogo.h
index 1e0081881f..ce93868da0 100644
--- a/include/video_easylogo.h
+++ b/include/video_easylogo.h
@@ -15,7 +15,7 @@
 #endif
 
 typedef struct {
-	unsigned char 	*data;
+	unsigned char	*data;
 	int		width;
 	int		height;
 	int		bpp;
diff --git a/include/video_logo.h b/include/video_logo.h
index c12e8f84ed..a0d2da4302 100644
--- a/include/video_logo.h
+++ b/include/video_logo.h
@@ -4,9 +4,9 @@
 /* To use this, include it and call: easylogo_plot(screen,&u_boot_logo, width,x,y) */
 /* */
 /* Where:	'screen'	is the pointer to the frame buffer */
-/* 		'width'	is the screen width */
-/* 		'x'		is the horizontal position */
-/* 		'y'		is the vertical position */
+/*		'width'	is the screen width */
+/*		'x'		is the horizontal position */
+/*		'y'		is the vertical position */
 /* */
 
 #include <video_easylogo.h>
diff --git a/include/virtex2.h b/include/virtex2.h
index f59227b1e7..d1166479c4 100644
--- a/include/virtex2.h
+++ b/include/virtex2.h
@@ -50,7 +50,7 @@ typedef struct {
 	Xilinx_busy_fn	busy;
 	Xilinx_abort_fn	abort;
 	Xilinx_post_fn	post;
-	int           	relocated;
+	int		relocated;
 } Xilinx_Virtex2_Slave_SelectMap_fns;
 
 /* Slave Serial Implementation function table */
@@ -59,7 +59,7 @@ typedef struct {
 	Xilinx_clk_fn	clk;
 	Xilinx_rdata_fn	rdata;
 	Xilinx_wdata_fn	wdata;
-	int           	relocated;
+	int		relocated;
 } Xilinx_Virtex2_Slave_Serial_fns;
 
 /* Device Image Sizes (in bytes)
@@ -116,5 +116,3 @@ typedef struct {
 { Xilinx_Virtex2, iface, XILINX_XC2V10000_SIZE, fn_table, cookie }
 
 #endif /* _VIRTEX2_H_ */
-
-/* vim: set ts=4 tw=78: */
diff --git a/include/xilinx.h b/include/xilinx.h
index 95ebe3d92b..ad33e1f288 100644
--- a/include/xilinx.h
+++ b/include/xilinx.h
@@ -29,55 +29,55 @@
 
 /* Xilinx Model definitions
  *********************************************************************/
-#define CFG_SPARTAN2 			CFG_FPGA_DEV( 0x1 )
-#define CFG_VIRTEX_E 			CFG_FPGA_DEV( 0x2 )
+#define CFG_SPARTAN2			CFG_FPGA_DEV( 0x1 )
+#define CFG_VIRTEX_E			CFG_FPGA_DEV( 0x2 )
 #define CFG_VIRTEX2			CFG_FPGA_DEV( 0x4 )
-#define CFG_SPARTAN3 			CFG_FPGA_DEV( 0x8 )
-#define CFG_XILINX_SPARTAN2 	(CFG_FPGA_XILINX | CFG_SPARTAN2)
-#define CFG_XILINX_VIRTEX_E 	(CFG_FPGA_XILINX | CFG_VIRTEX_E)
+#define CFG_SPARTAN3			CFG_FPGA_DEV( 0x8 )
+#define CFG_XILINX_SPARTAN2	(CFG_FPGA_XILINX | CFG_SPARTAN2)
+#define CFG_XILINX_VIRTEX_E	(CFG_FPGA_XILINX | CFG_VIRTEX_E)
 #define CFG_XILINX_VIRTEX2	(CFG_FPGA_XILINX | CFG_VIRTEX2)
-#define CFG_XILINX_SPARTAN3 	(CFG_FPGA_XILINX | CFG_SPARTAN3)
+#define CFG_XILINX_SPARTAN3	(CFG_FPGA_XILINX | CFG_SPARTAN3)
 /* XXX - Add new models here */
 
 
 /* Xilinx Interface definitions
  *********************************************************************/
-#define CFG_XILINX_IF_SS	CFG_FPGA_IF( 0x1 )	/* slave serial 	*/
+#define CFG_XILINX_IF_SS	CFG_FPGA_IF( 0x1 )	/* slave serial		*/
 #define CFG_XILINX_IF_MS	CFG_FPGA_IF( 0x2 )	/* master serial	*/
-#define CFG_XILINX_IF_SP	CFG_FPGA_IF( 0x4 )	/* slave parallel 	*/
-#define CFG_XILINX_IF_JTAG	CFG_FPGA_IF( 0x8 )	/* jtag				*/
+#define CFG_XILINX_IF_SP	CFG_FPGA_IF( 0x4 )	/* slave parallel	*/
+#define CFG_XILINX_IF_JTAG	CFG_FPGA_IF( 0x8 )	/* jtag			*/
 #define CFG_XILINX_IF_MSM	CFG_FPGA_IF( 0x10 )	/* master selectmap	*/
 #define CFG_XILINX_IF_SSM	CFG_FPGA_IF( 0x20 )	/* slave selectmap	*/
 
 /* Xilinx types
  *********************************************************************/
-typedef enum {					/* typedef Xilinx_iface	*/
-	min_xilinx_iface_type,		/* low range check value */
-    slave_serial,				/* serial data and external clock */
-    master_serial,				/* serial data w/ internal clock (not used) */
-    slave_parallel,				/* parallel data w/ external latch */
-    jtag_mode,					/* jtag/tap serial (not used ) */
-	master_selectmap,			/* master SelectMap (virtex2)		*/
-	slave_selectmap,			/* slave SelectMap (virtex2)		*/
-    max_xilinx_iface_type		/* insert all new types before this */
-} Xilinx_iface;					/* end, typedef Xilinx_iface */
+typedef enum {			/* typedef Xilinx_iface */
+	min_xilinx_iface_type,	/* low range check value */
+	slave_serial,		/* serial data and external clock */
+	master_serial,		/* serial data w/ internal clock (not used) */
+	slave_parallel,		/* parallel data w/ external latch */
+	jtag_mode,		/* jtag/tap serial (not used ) */
+	master_selectmap,	/* master SelectMap (virtex2)           */
+	slave_selectmap,	/* slave SelectMap (virtex2)            */
+	max_xilinx_iface_type	/* insert all new types before this */
+} Xilinx_iface;			/* end, typedef Xilinx_iface */
 
-typedef enum {					/* typedef Xilinx_Family */
-	min_xilinx_type,			/* low range check value */
-    Xilinx_Spartan2,			/* Spartan-II Family */
-    Xilinx_VirtexE,				/* Virtex-E Family */
-    Xilinx_Virtex2,				/* Virtex2 Family */
-    Xilinx_Spartan3,				/* Spartan-III Family */
-    max_xilinx_type				/* insert all new types before this */
-} Xilinx_Family;				/* end, typedef Xilinx_Family */
+typedef enum {			/* typedef Xilinx_Family */
+	min_xilinx_type,	/* low range check value */
+	Xilinx_Spartan2,	/* Spartan-II Family */
+	Xilinx_VirtexE,		/* Virtex-E Family */
+	Xilinx_Virtex2,		/* Virtex2 Family */
+	Xilinx_Spartan3,	/* Spartan-III Family */
+	max_xilinx_type		/* insert all new types before this */
+} Xilinx_Family;		/* end, typedef Xilinx_Family */
 
-typedef struct {				/* typedef Xilinx_desc */
-    Xilinx_Family    family;	/* part type */
-    Xilinx_iface     iface;		/* interface type */
-    size_t           size;		/* bytes of data part can accept */
-	void *           iface_fns;	/* interface function table */
-    int              cookie;	/* implementation specific cookie */
-} Xilinx_desc;					/* end, typedef Xilinx_desc */
+typedef struct {		/* typedef Xilinx_desc */
+	Xilinx_Family family;	/* part type */
+	Xilinx_iface iface;	/* interface type */
+	size_t size;		/* bytes of data part can accept */
+	void *iface_fns;	/* interface function table */
+	int cookie;		/* implementation specific cookie */
+} Xilinx_desc;			/* end, typedef Xilinx_desc */
 
 /* Generic Xilinx Functions
  *********************************************************************/
diff --git a/lib_arm/Makefile b/lib_arm/Makefile
index 12a8748d1c..c8795b2314 100644
--- a/lib_arm/Makefile
+++ b/lib_arm/Makefile
@@ -38,7 +38,7 @@ COBJS-y	+= cache.o
 COBJS-y	+= div0.o
 COBJS-y	+= interrupts.o
 
-SRCS 	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
 
 $(LIB):	$(obj).depend $(OBJS)
diff --git a/lib_arm/_udivsi3.S b/lib_arm/_udivsi3.S
index 2cdcd48b49..a3f9b5961c 100644
--- a/lib_arm/_udivsi3.S
+++ b/lib_arm/_udivsi3.S
@@ -61,7 +61,7 @@ Loop3:
 	bne	Loop3
 Lgot_result:
 	mov	r0, result
-	mov 	pc, lr
+	mov	pc, lr
 Ldiv0:
 	str	lr, [sp, #-4]!
 	bl	 __div0       (PLT)
diff --git a/lib_arm/_umodsi3.S b/lib_arm/_umodsi3.S
index e4aebe84ca..8465ef09d2 100644
--- a/lib_arm/_umodsi3.S
+++ b/lib_arm/_umodsi3.S
@@ -19,7 +19,7 @@ curbit		.req	r3
 	beq	Ldiv0
 	mov	curbit, #1
 	cmp	dividend, divisor
-	movcc  	pc, lr
+	movcc	pc, lr
 Loop1:
 	@ Unless the divisor is very big, shift it up in multiples of
 	@ four bits, since this is the amount of unwinding in the main
@@ -66,14 +66,14 @@ Loop3:
 	@ then none of the below will match, since the bit in ip will not be
 	@ in the bottom nibble.
 	ands	overdone, overdone, #0xe0000000
-	moveq  	pc, lr				@ No fixups needed
+	moveq	pc, lr				@ No fixups needed
 	tst	overdone, ip, ror #3
 	addne	dividend, dividend, divisor, lsr #3
 	tst	overdone, ip, ror #2
 	addne	dividend, dividend, divisor, lsr #2
 	tst	overdone, ip, ror #1
 	addne	dividend, dividend, divisor, lsr #1
-	mov 	pc, lr
+	mov	pc, lr
 Ldiv0:
 	str	lr, [sp, #-4]!
 	bl	 __div0       (PLT)
diff --git a/lib_blackfin/Makefile b/lib_blackfin/Makefile
index 36171048ac..3f69770d67 100644
--- a/lib_blackfin/Makefile
+++ b/lib_blackfin/Makefile
@@ -44,7 +44,7 @@ COBJS-y	+= post.o
 COBJS-y	+= string.o
 COBJS-y	+= tests.o
 
-SRCS 	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
 
 $(LIB):	$(obj).depend $(OBJS)
diff --git a/lib_generic/Makefile b/lib_generic/Makefile
index abee19a2bb..dca3a6cbdc 100644
--- a/lib_generic/Makefile
+++ b/lib_generic/Makefile
@@ -43,7 +43,7 @@ COBJS-y += vsprintf.o
 COBJS-y += zlib.o
 
 COBJS	:= $(COBJS-y)
-SRCS 	:= $(COBJS:.o=.c)
+SRCS	:= $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
 
 $(LIB):	$(obj).depend $(OBJS)
diff --git a/lib_generic/string.c b/lib_generic/string.c
index e0b793abbe..181eda6149 100644
--- a/lib_generic/string.c
+++ b/lib_generic/string.c
@@ -263,7 +263,7 @@ char * strdup(const char *s)
 #ifndef __HAVE_ARCH_STRSPN
 /**
  * strspn - Calculate the length of the initial substring of @s which only
- * 	contain letters in @accept
+ *	contain letters in @accept
  * @s: The string to be searched
  * @accept: The string to search for
  */
diff --git a/lib_generic/zlib.c b/lib_generic/zlib.c
index 668ac8f808..2b01c8f87d 100644
--- a/lib_generic/zlib.c
+++ b/lib_generic/zlib.c
@@ -1115,7 +1115,7 @@ z_stream *z;
 	n -= t;
 	z->total_out += t;
 	s->read = q;    /* drag read pointer forward */
-/*      WRAP  */ 	/* expand WRAP macro by hand to handle s->read */
+/*      WRAP  */	/* expand WRAP macro by hand to handle s->read */
 	if (q == s->end) {
 	    s->read = q = s->window;
 	    m = WAVAIL;
diff --git a/lib_i386/Makefile b/lib_i386/Makefile
index 4cc29f432a..4fbcd08b88 100644
--- a/lib_i386/Makefile
+++ b/lib_i386/Makefile
@@ -39,7 +39,7 @@ COBJS-y	+= video_bios.o
 COBJS-y	+= video.o
 COBJS-y	+= zimage.o
 
-SRCS 	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
 
 $(LIB):	$(obj).depend $(OBJS)
diff --git a/lib_i386/bios.S b/lib_i386/bios.S
index 4606419c1b..d6ca3e3159 100644
--- a/lib_i386/bios.S
+++ b/lib_i386/bios.S
@@ -248,7 +248,7 @@ Lhandeled:
 
 /*
  ************************************************************
- * BIOS 	interrupt 10h -- VGA services
+ * BIOS	interrupt 10h -- VGA services
  ************************************************************
  */
 bios_10h:
@@ -293,7 +293,7 @@ gs	movw	%ax, OFFS_AX(%bp)
 
 /*
  ************************************************************
- * BIOS 	interrupt 12h -- Get Memory Size
+ * BIOS	interrupt 12h -- Get Memory Size
  ************************************************************
  */
 bios_12h:
@@ -352,7 +352,7 @@ gs	movw	OFFS_AX(%bp), %ax
 	movw	$0xffff, %ax
 	ret
 
-Lfunc_c0h: 					/* Return System Configuration Parameters (PS2 only) */
+Lfunc_c0h:					/* Return System Configuration Parameters (PS2 only) */
 gs	movw	OFFS_FLAGS(%bp), %ax
 	orw	$1, %ax				/* return carry -- function not supported */
 gs	movw	%ax, OFFS_FLAGS(%bp)
@@ -377,7 +377,7 @@ cs	movw	ram_in_64kb_chunks, %ax
 	shlw	$6, %ax				/* multiply by 64 */
 	subw	$0x400, %ax			/* 1st meg does not count */
 
-gs	movw	%ax, OFFS_AX(%bp)   		/* return memory size between 1M and 16M in 1kb chunks in AX and CX */
+gs	movw	%ax, OFFS_AX(%bp)		/* return memory size between 1M and 16M in 1kb chunks in AX and CX */
 gs	movw	%ax, OFFS_CX(%bp)
 gs	movw	$0, OFFS_BX(%bp)		/* set BX and DX to 0*/
 gs	movw	$0, OFFS_DX(%bp)
@@ -455,8 +455,8 @@ Lfunc_b1h:
 
 .globl ram_in_64kb_chunks
 ram_in_64kb_chunks:
-	.word 	0
+	.word	0
 
 .globl bios_equipment
 bios_equipment:
-	.word 	0
+	.word	0
diff --git a/lib_i386/bios.h b/lib_i386/bios.h
index 59143dde41..4901f8917a 100644
--- a/lib_i386/bios.h
+++ b/lib_i386/bios.h
@@ -57,7 +57,7 @@
 #define OFFS_FLAGS   44    /* 16bit */
 
 #define SEGMENT      0x40
-#define STACK	     0x800  			/* stack at 0x40:0x800 -> 0x800 */
+#define STACK	     0x800			/* stack at 0x40:0x800 -> 0x800 */
 
 /* save general registers */
 /* save some segments     */
diff --git a/lib_i386/bios_pci.S b/lib_i386/bios_pci.S
index b57b7260a6..67fd00b834 100644
--- a/lib_i386/bios_pci.S
+++ b/lib_i386/bios_pci.S
@@ -84,14 +84,14 @@ gs	movb	%al, OFFS_AL(%bp)	/* We support cfg type 1 */
 gs	movw	%ax, OFFS_BX(%bp)
 cs	movb	pci_last_bus, %al       /* last bus number */
 gs	movb	%al, OFFS_CL(%bp)
-	jmp 	clear_carry
+	jmp	clear_carry
 
 /*****************************************************************************/
 
 /* device 0-31, function 0-7 */
 pci_bios_find_device:
 #ifdef PCI_BIOS_DEBUG
-cs	incl 	num_pci_bios_find_device
+cs	incl	num_pci_bios_find_device
 #endif
 gs	movw	OFFS_CX(%bp), %di
 	shll	$16, %edi
@@ -214,12 +214,12 @@ pci_bios_read_cfg_byte:
 cs	incl	num_pci_bios_read_cfg_byte
 #endif
 	call	pci_bios_select_register
-gs	movw 	OFFS_DI(%bp), %dx
+gs	movw	OFFS_DI(%bp), %dx
 	andw	$3, %dx
 	addw	$0xcfc, %dx
 	inb	%dx, %al
 gs	movb	%al, OFFS_CL(%bp)
-	jmp 	clear_carry
+	jmp	clear_carry
 
 /*****************************************************************************/
 
@@ -228,12 +228,12 @@ pci_bios_read_cfg_word:
 cs	incl	num_pci_bios_read_cfg_word
 #endif
 	call	pci_bios_select_register
-gs	movw 	OFFS_DI(%bp), %dx
+gs	movw	OFFS_DI(%bp), %dx
 	andw	$2, %dx
 	addw	$0xcfc, %dx
 	inw	%dx, %ax
 gs	movw	%ax, OFFS_CX(%bp)
-	jmp 	clear_carry
+	jmp	clear_carry
 
 
 /*****************************************************************************/
@@ -246,7 +246,7 @@ cs	incl	num_pci_bios_read_cfg_dword
 	movw	$0xcfc, %dx
 	inl	%dx, %eax
 gs	movl	%eax, OFFS_ECX(%bp)
-	jmp 	clear_carry
+	jmp	clear_carry
 
 /*****************************************************************************/
 
@@ -255,12 +255,12 @@ pci_bios_write_cfg_byte:
 cs	incl	num_pci_bios_write_cfg_byte
 #endif
 	call	pci_bios_select_register
-gs	movw 	OFFS_DI(%bp), %dx
+gs	movw	OFFS_DI(%bp), %dx
 gs	movb	OFFS_CL(%bp), %al
 	andw	$3, %dx
 	addw	$0xcfc, %dx
 	outb	%al, %dx
-	jmp 	clear_carry
+	jmp	clear_carry
 
 /*****************************************************************************/
 
@@ -269,12 +269,12 @@ pci_bios_write_cfg_word:
 cs	incl	num_pci_bios_write_cfg_word
 #endif
 	call	pci_bios_select_register
-gs	movw 	OFFS_DI(%bp), %dx
+gs	movw	OFFS_DI(%bp), %dx
 gs	movw	OFFS_CX(%bp), %ax
 	andw	$2, %dx
 	addw	$0xcfc, %dx
 	outw	%ax, %dx
-	jmp 	clear_carry
+	jmp	clear_carry
 
 /*****************************************************************************/
 
@@ -286,7 +286,7 @@ cs	incl	num_pci_bios_write_cfg_dword
 gs	movl	OFFS_ECX(%bp), %eax
 	movw	$0xcfc, %dx
 	outl	%eax, %dx
-	jmp 	clear_carry
+	jmp	clear_carry
 
 /*****************************************************************************/
 
@@ -318,8 +318,8 @@ cs	incl	num_pci_bios_unknown_function
 /*****************************************************************************/
 
 pci_bios_select_register:
-gs	movw 	OFFS_BX(%bp), %bx
-gs	movw 	OFFS_DI(%bp), %ax
+gs	movw	OFFS_BX(%bp), %bx
+gs	movw	OFFS_DI(%bp), %ax
 /* destroys eax, dx */
 __pci_bios_select_register:               /* BX holds device id, AX holds register index */
 	pushl	%ebx
@@ -354,20 +354,20 @@ gs	movw	%ax, OFFS_FLAGS(%bp)
 
 .globl pci_last_bus
 pci_last_bus:
-	.byte 	0
+	.byte	0
 
 #ifdef PCI_BIOS_DEBUG
 .globl num_pci_bios_present
 num_pci_bios_present:
-	.long 	0
+	.long	0
 
 .globl num_pci_bios_find_device
 num_pci_bios_find_device:
-	.long 	0
+	.long	0
 
 .globl num_pci_bios_find_class
 num_pci_bios_find_class:
-	.long 	0
+	.long	0
 
 .globl num_pci_bios_generate_special_cycle
 num_pci_bios_generate_special_cycle:
@@ -375,37 +375,37 @@ num_pci_bios_generate_special_cycle:
 
 .globl num_pci_bios_read_cfg_byte
 num_pci_bios_read_cfg_byte:
-	.long 	0
+	.long	0
 
 .globl num_pci_bios_read_cfg_word
 num_pci_bios_read_cfg_word:
-	.long 	0
+	.long	0
 
 .globl num_pci_bios_read_cfg_dword
 num_pci_bios_read_cfg_dword:
-	.long 	0
+	.long	0
 
 .globl num_pci_bios_write_cfg_byte
 num_pci_bios_write_cfg_byte:
-	.long 	0
+	.long	0
 
 .globl num_pci_bios_write_cfg_word
 num_pci_bios_write_cfg_word:
-	.long 	0
+	.long	0
 
 .globl num_pci_bios_write_cfg_dword
 num_pci_bios_write_cfg_dword:
-	.long 	0
+	.long	0
 
 .globl num_pci_bios_get_irq_routing
 num_pci_bios_get_irq_routing:
-	.long 	0
+	.long	0
 
 .globl num_pci_bios_set_irq
 num_pci_bios_set_irq:
-	.long 	0
+	.long	0
 
 .globl num_pci_bios_unknown_function
 num_pci_bios_unknown_function:
-	.long 	0
+	.long	0
 #endif
diff --git a/lib_i386/pci.c b/lib_i386/pci.c
index a7f16aa53b..4331b04418 100644
--- a/lib_i386/pci.c
+++ b/lib_i386/pci.c
@@ -52,7 +52,7 @@ int pci_shadow_rom(pci_dev_t dev, unsigned char *dest)
 	pci_read_config_word(dev, PCI_DEVICE_ID, &device);
 	pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_code);
 
- 	class_code &= 0xffffff00;
+	class_code &= 0xffffff00;
 	class_code >>= 8;
 
 #if 0
@@ -103,7 +103,7 @@ int pci_shadow_rom(pci_dev_t dev, unsigned char *dest)
 				printf("%s\n",
 				       (readw(pci_data+0x15) &0x80)?
 				       "Last image":"More images follow");
-				switch 	(readb(pci_data+0x14)) {
+				switch	(readb(pci_data+0x14)) {
 				case 0:
 					printf("X86 code\n");
 					break;
diff --git a/lib_i386/pci_type1.c b/lib_i386/pci_type1.c
index 5dfa8ab4fd..8da8c1ced7 100644
--- a/lib_i386/pci_type1.c
+++ b/lib_i386/pci_type1.c
@@ -20,14 +20,14 @@
 #define cfg_read(val, addr, op)	*val = op((int)(addr))
 #define cfg_write(val, addr, op)	op((val), (int)(addr))
 
-#define TYPE1_PCI_OP(rw, size, type, op, mask)			 \
-static int								 \
-type1_##rw##_config_##size(struct pci_controller *hose, 		 \
-			      pci_dev_t dev, int offset, type val)	 \
-{									 \
-	outl(dev | (offset & 0xfc) | 0x80000000, (int)hose->cfg_addr); 	 \
-	cfg_##rw(val, hose->cfg_data + (offset & mask), op);	 \
-	return 0;    					 		 \
+#define TYPE1_PCI_OP(rw, size, type, op, mask)				\
+static int								\
+type1_##rw##_config_##size(struct pci_controller *hose,			\
+			      pci_dev_t dev, int offset, type val)	\
+{									\
+	outl(dev | (offset & 0xfc) | 0x80000000, (int)hose->cfg_addr);	\
+	cfg_##rw(val, hose->cfg_data + (offset & mask), op);		\
+	return 0;							\
 }
 
 
diff --git a/lib_i386/realmode_switch.S b/lib_i386/realmode_switch.S
index 0433cd47c7..d6c74ecd79 100644
--- a/lib_i386/realmode_switch.S
+++ b/lib_i386/realmode_switch.S
@@ -26,7 +26,7 @@
 
 /*
  * Stack frame at 0xe00
- *      e00 ebx;
+ *	e00 ebx;
  *	e04 ecx;
  *	e08 edx;
  *	e0c esi;
@@ -56,13 +56,13 @@ realmode_enter:
 o32	pusha
 o32	pushf
 	cli
-	sidt   	saved_idt
-	sgdt    saved_gdt
-	movl    %esp, %eax
-	movl    %eax, saved_protected_mode_esp
+	sidt	saved_idt
+	sgdt	saved_gdt
+	movl	%esp, %eax
+	movl	%eax, saved_protected_mode_esp
 
 	movl	$0x10, %eax
-	movl    %eax, %esp
+	movl	%eax, %esp
 	movw	$0x28, %ax
 	movw	%ax, %ds
 	movw	%ax, %es
@@ -70,10 +70,10 @@ o32	pushf
 	movw	%ax, %gs
 
 	lidt	realmode_idt_ptr
-	movl	%cr0, %eax                	/* Go back into real mode by */
-	andl	$0x7ffffffe, %eax         	/* clearing PE to 0 */
+	movl	%cr0, %eax			/* Go back into real mode by */
+	andl	$0x7ffffffe, %eax		/* clearing PE to 0 */
 	movl	%eax, %cr0
-	ljmp	$0x0,$do_realmode             	/* switch to real mode */
+	ljmp	$0x0,$do_realmode		/* switch to real mode */
 
 do_realmode:					/* realmode code from here */
 	movw	%cs,%ax
@@ -115,20 +115,20 @@ o32	popf
 	popw	%ss
 	movl	%eax, %esp
 cs	movl	temp_eax, %eax
-	wbinvd                                  /* self-modifying code,
+	wbinvd					/* self-modifying code,
 						 * better flush the cache */
 
 	.byte	0x9a				/* lcall */
 temp_ip:
-	.word	0	     			/* new ip */
+	.word	0				/* new ip */
 temp_cs:
-	.word   0				/* new cs */
+	.word	0				/* new cs */
 realmode_ret:
 						/* save eax, esp and ss */
 cs	movl	%eax, saved_eax
 	movl	%esp, %eax
 cs	movl	%eax, saved_esp
-	movw    %ss, %ax
+	movw	%ss, %ax
 cs	movw	%ax, saved_ss
 
 	/* restore the stack, note that we set sp to 0x244;
@@ -170,26 +170,26 @@ cs	movw	temp_ip, %ax
 	pushl	%ebx
 
 o32 cs	lidt	saved_idt
-o32 cs	lgdt    saved_gdt			/* Set GDTR */
+o32 cs	lgdt	saved_gdt			/* Set GDTR */
 
-	movl    %cr0, %eax              	/* Go back into protected mode */
-	orl     $1,%eax                 	/* reset PE to 1 */
-	movl    %eax, %cr0
-	jmp     next_line               	/* flush prefetch queue */
+	movl	%cr0, %eax			/* Go back into protected mode */
+	orl	$1,%eax	/* reset PE to 1 */
+	movl	%eax, %cr0
+	jmp	next_line			/* flush prefetch queue */
 next_line:
 	movw	$return_ptr, %ax
-	movw    %ax,%bp
+	movw	%ax,%bp
 o32 cs	ljmp	*(%bp)
 
 .code32
 protected_mode:
-	movl    $0x18,%eax         		/* reload GDT[3] */
-	movw    %ax,%fs                 	/* reset FS */
-	movw	%ax,%ds                		/* reset DS */
-	movw    %ax,%gs                 	/* reset GS */
-	movw    %ax,%es                 	/* reset ES */
-	movw    %ax,%ss                 	/* reset SS */
-	movl    saved_protected_mode_esp, %eax
+	movl	$0x18,%eax			/* reload GDT[3] */
+	movw	%ax,%fs				/* reset FS */
+	movw	%ax,%ds				/* reset DS */
+	movw	%ax,%gs				/* reset GS */
+	movw	%ax,%es				/* reset ES */
+	movw	%ax,%ss				/* reset SS */
+	movl	saved_protected_mode_esp, %eax
 	movl	%eax, %esp
 	popf
 	popa
@@ -199,7 +199,7 @@ temp_eax:
 	.long	0
 
 saved_ss:
-	.word   0
+	.word	0
 saved_esp:
 	.long	0
 saved_eax:
@@ -210,12 +210,12 @@ realmode_idt_ptr:
 	.word	0x0, 0x0
 
 saved_gdt:
-	.word 	0, 0, 0, 0
+	.word	0, 0, 0, 0
 saved_idt:
-	.word 	0, 0, 0, 0
+	.word	0, 0, 0, 0
 
 saved_protected_mode_esp:
-	.long 	0
+	.long	0
 
 return_ptr:
 	.long	protected_mode
diff --git a/lib_m68k/Makefile b/lib_m68k/Makefile
index f6924cd0bd..6db35ed2c1 100644
--- a/lib_m68k/Makefile
+++ b/lib_m68k/Makefile
@@ -34,7 +34,7 @@ COBJS-y	+= interrupts.o
 COBJS-y	+= time.o
 COBJS-y	+= traps.o
 
-SRCS 	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
 
 $(LIB):	$(obj).depend $(OBJS)
diff --git a/lib_m68k/board.c b/lib_m68k/board.c
index 6654f971b2..ae942e5e57 100644
--- a/lib_m68k/board.c
+++ b/lib_m68k/board.c
@@ -354,7 +354,7 @@ board_init_f (ulong bootflag)
 	debug ("Reserving %d Bytes for Global Data at: %08lx\n",
 			sizeof (gd_t), addr_sp);
 
- 	/* Reserve memory for boot params. */
+	/* Reserve memory for boot params. */
 	addr_sp -= CFG_BOOTPARAMS_LEN;
 	bd->bi_boot_params = addr_sp;
 	debug ("Reserving %dk for boot parameters at: %08lx\n",
diff --git a/lib_microblaze/Makefile b/lib_microblaze/Makefile
index 141b08280a..9b0f296e3f 100644
--- a/lib_microblaze/Makefile
+++ b/lib_microblaze/Makefile
@@ -32,7 +32,7 @@ COBJS-y	+= bootm.o
 COBJS-y	+= cache.o
 COBJS-y	+= time.o
 
-SRCS 	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
 
 $(LIB):	$(obj).depend $(OBJS)
diff --git a/lib_mips/Makefile b/lib_mips/Makefile
index 799eaf2658..817643795e 100644
--- a/lib_mips/Makefile
+++ b/lib_mips/Makefile
@@ -31,7 +31,7 @@ COBJS-y	+= board.o
 COBJS-y	+= bootm.o
 COBJS-y	+= time.o
 
-SRCS 	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
 
 $(LIB):	$(obj).depend $(OBJS)
diff --git a/lib_nios/Makefile b/lib_nios/Makefile
index c41d981a3e..f66e9893ab 100644
--- a/lib_nios/Makefile
+++ b/lib_nios/Makefile
@@ -34,7 +34,7 @@ COBJS-y	+= divmod.o
 COBJS-y	+= mult.o
 COBJS-y	+= time.o
 
-SRCS 	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
 
 $(LIB):	$(obj).depend $(OBJS)
diff --git a/lib_nios/math.h b/lib_nios/math.h
index ccffbbc2e7..f0aed8edc3 100644
--- a/lib_nios/math.h
+++ b/lib_nios/math.h
@@ -1,6 +1,6 @@
 #define BITS_PER_UNIT	8
 
-typedef 	 int HItype		__attribute__ ((mode (HI)));
+typedef	 int HItype			__attribute__ ((mode (HI)));
 typedef unsigned int UHItype		__attribute__ ((mode (HI)));
 
 typedef		 int SItype		__attribute__ ((mode (SI)));
diff --git a/lib_nios2/Makefile b/lib_nios2/Makefile
index 717aa9bfbe..b69bc38850 100644
--- a/lib_nios2/Makefile
+++ b/lib_nios2/Makefile
@@ -33,7 +33,7 @@ COBJS-y	+= divmod.o
 COBJS-y	+= mult.o
 COBJS-y	+= time.o
 
-SRCS 	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
 
 $(LIB):	$(obj).depend $(OBJS)
diff --git a/lib_nios2/math.h b/lib_nios2/math.h
index ccffbbc2e7..f0aed8edc3 100644
--- a/lib_nios2/math.h
+++ b/lib_nios2/math.h
@@ -1,6 +1,6 @@
 #define BITS_PER_UNIT	8
 
-typedef 	 int HItype		__attribute__ ((mode (HI)));
+typedef	 int HItype			__attribute__ ((mode (HI)));
 typedef unsigned int UHItype		__attribute__ ((mode (HI)));
 
 typedef		 int SItype		__attribute__ ((mode (SI)));
diff --git a/lib_ppc/Makefile b/lib_ppc/Makefile
index 3d76b700e2..60ea0c9139 100644
--- a/lib_ppc/Makefile
+++ b/lib_ppc/Makefile
@@ -38,7 +38,7 @@ COBJS-y	+= interrupts.o
 COBJS-y	+= kgdb.o
 COBJS-y	+= time.o
 
-SRCS 	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
 
 $(LIB):	$(obj).depend $(OBJS)
diff --git a/lib_sh/Makefile b/lib_sh/Makefile
index a5772a013d..0e4fdee093 100644
--- a/lib_sh/Makefile
+++ b/lib_sh/Makefile
@@ -28,7 +28,7 @@ COBJS-y	+= board.o
 COBJS-y	+= bootm.o
 #COBJS-y	+= time.o
 
-SRCS 	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
 
 $(LIB):	$(obj).depend $(OBJS)
diff --git a/lib_sparc/Makefile b/lib_sparc/Makefile
index 1a354b6eab..040ca10d3b 100644
--- a/lib_sparc/Makefile
+++ b/lib_sparc/Makefile
@@ -29,7 +29,7 @@ SOBJS	=
 
 COBJS	= board.o cache.o interrupts.o time.o bootm.o
 
-SRCS 	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
 
 $(LIB):	$(obj).depend $(OBJS)
diff --git a/libfdt/Makefile b/libfdt/Makefile
index d166cce796..ca2ad76c88 100644
--- a/libfdt/Makefile
+++ b/libfdt/Makefile
@@ -30,7 +30,7 @@ SOBJS	=
 COBJS-$(CONFIG_OF_LIBFDT) += fdt.o fdt_ro.o fdt_rw.o fdt_strerror.o fdt_sw.o fdt_wip.o
 
 COBJS	:= $(COBJS-y)
-SRCS 	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
 
 $(LIB):	$(obj).depend $(OBJS)
diff --git a/libfdt/README b/libfdt/README
index f4cca3499c..e0598761f9 100644
--- a/libfdt/README
+++ b/libfdt/README
@@ -1,12 +1,12 @@
 The libfdt functionality was written by David Gibson.  The original
 source came from the git repository:
 
-URL: 		git://ozlabs.org/home/dgibson/git/libfdt.git
+URL:		git://ozlabs.org/home/dgibson/git/libfdt.git
 
 author		David Gibson <dgibson@sneetch.(none)>
 		Fri, 23 Mar 2007 04:16:54 +0000 (15:16 +1100)
 committer	David Gibson <dgibson@sneetch.(none)>
-	 	Fri, 23 Mar 2007 04:16:54 +0000 (15:16 +1100)
+		Fri, 23 Mar 2007 04:16:54 +0000 (15:16 +1100)
 commit		857f54e79f74429af20c2b5ecc00ee98af6a3b8b
 tree		2f648f0f88225a51ded452968d28b4402df8ade0
 parent		07a12a08005f3b5cd9337900a6551e450c07b515
diff --git a/net/net.c b/net/net.c
index b6dad89326..78128772fe 100644
--- a/net/net.c
+++ b/net/net.c
@@ -169,7 +169,7 @@ ushort		NetOurNativeVLAN = 0xFFFF;	/* ditto			*/
 char		BootFile[128];		/* Boot File name			*/
 
 #if defined(CONFIG_CMD_PING)
-IPaddr_t	NetPingIP;		/* the ip address to ping 		*/
+IPaddr_t	NetPingIP;		/* the ip address to ping		*/
 
 static void PingStart(void);
 #endif
@@ -207,7 +207,7 @@ IPaddr_t	NetArpWaitReplyIP;
 uchar	       *NetArpWaitPacketMAC;	/* MAC address of waiting packet's destination	*/
 uchar	       *NetArpWaitTxPacket;	/* THE transmit packet			*/
 int		NetArpWaitTxPacketSize;
-uchar 		NetArpWaitPacketBuf[PKTSIZE_ALIGN + PKTALIGN];
+uchar		NetArpWaitPacketBuf[PKTSIZE_ALIGN + PKTALIGN];
 ulong		NetArpWaitTimerStart;
 int		NetArpWaitTry;
 
@@ -751,7 +751,7 @@ int PingSend(void)
 	s = &ip->udp_src;		/* XXX ICMP starts here */
 	s[0] = htons(0x0800);		/* echo-request, code */
 	s[1] = 0;			/* checksum */
-	s[2] = 0; 			/* identifier */
+	s[2] = 0;			/* identifier */
 	s[3] = htons(PingSeqNo++);	/* sequence number */
 	s[1] = ~NetCksum((uchar *)s, 8/2);
 
diff --git a/post/cpu/ppc4xx/Makefile b/post/cpu/ppc4xx/Makefile
index f19dc5d3ce..1cfd3bb59c 100644
--- a/post/cpu/ppc4xx/Makefile
+++ b/post/cpu/ppc4xx/Makefile
@@ -29,6 +29,7 @@ COBJS-$(CONFIG_HAS_POST)	+= cache.o
 COBJS-$(CONFIG_HAS_POST)	+= denali_ecc.o
 COBJS-$(CONFIG_HAS_POST)	+= ether.o
 COBJS-$(CONFIG_HAS_POST)	+= fpu.o
+COBJS-$(CONFIG_HAS_POST)	+= ocm.o
 COBJS-$(CONFIG_HAS_POST)	+= spr.o
 COBJS-$(CONFIG_HAS_POST)	+= uart.o
 COBJS-$(CONFIG_HAS_POST)	+= watchdog.o
diff --git a/post/cpu/ppc4xx/ocm.c b/post/cpu/ppc4xx/ocm.c
new file mode 100644
index 0000000000..88aa93ea1e
--- /dev/null
+++ b/post/cpu/ppc4xx/ocm.c
@@ -0,0 +1,89 @@
+/*
+ * (C) Copyright 2008 Ilya Yanok, EmCraft Systems, yanok@emcraft.com
+ *
+ * Developed for DENX Software Engineering GmbH
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+
+/*
+ * This test attempts to verify on-chip memory (OCM). Result is written
+ * to the scratch register and if test succeed it won't be run till next
+ * power on.
+ */
+
+#include <post.h>
+
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define OCM_TEST_PATTERN1	0x55555555
+#define OCM_TEST_PATTERN2	0xAAAAAAAA
+
+#if CONFIG_POST & CFG_POST_OCM
+
+static uint ocm_status_read(void)
+{
+	return in_be32((void *)CFG_OCM_STATUS_ADDR) &
+		CFG_OCM_STATUS_MASK;
+}
+
+static void ocm_status_write(uint value)
+{
+	out_be32((void *)CFG_OCM_STATUS_ADDR, value |
+		(in_be32((void *)CFG_OCM_STATUS_ADDR) &
+			~CFG_OCM_STATUS_MASK));
+}
+
+static inline int ocm_test_word(uint value, uint *address)
+{
+	uint read_value;
+
+	*address = value;
+	sync();
+	read_value = *address;
+
+	return (read_value != value);
+}
+
+int ocm_post_test(int flags)
+{
+	uint   old_value;
+	int    ret = 0;
+	uint  *address = (uint*)CFG_OCM_BASE;
+
+	if (ocm_status_read() == CFG_OCM_STATUS_OK)
+		return 0;
+	for (; address < (uint*)(CFG_OCM_BASE + CFG_OCM_SIZE); address++) {
+		old_value = *address;
+		if (ocm_test_word(OCM_TEST_PATTERN1, address) ||
+				ocm_test_word(OCM_TEST_PATTERN2, address)) {
+			ret = 1;
+			*address = old_value;
+			printf("OCM POST failed at %p!\n", address);
+			break;
+		}
+		*address = old_value;
+	}
+	ocm_status_write(ret ? CFG_OCM_STATUS_FAIL : CFG_OCM_STATUS_OK);
+	return ret;
+}
+#endif /* CONFIG_POST & CFG_POST_OCM */
diff --git a/post/drivers/memory.c b/post/drivers/memory.c
index e94d92c08b..e32020f823 100644
--- a/post/drivers/memory.c
+++ b/post/drivers/memory.c
@@ -282,7 +282,7 @@ static int memory_post_addrline(ulong *testaddr, ulong *base, ulong size)
 #endif
 			if(readback == *testaddr) {
 				post_log ("Memory (address line) error at %08x<->%08x, "
-				  	"XOR value %08x !\n",
+					"XOR value %08x !\n",
 					testaddr, target, xor);
 				ret = -1;
 			}
diff --git a/post/lib_ppc/andi.c b/post/lib_ppc/andi.c
index e3315bf15e..75ba7a66a2 100644
--- a/post/lib_ppc/andi.c
+++ b/post/lib_ppc/andi.c
@@ -49,13 +49,13 @@ static struct cpu_post_andi_s
 } cpu_post_andi_table[] =
 {
     {
-    	OP_ANDI_,
+	OP_ANDI_,
 	0x80008000,
 	0xffff,
 	0x00008000
     },
     {
-    	OP_ANDIS_,
+	OP_ANDIS_,
 	0x80008000,
 	0xffff,
 	0x80000000
@@ -79,7 +79,7 @@ int cpu_post_test_andi (void)
 	    unsigned int reg0 = (reg + 0) % 32;
 	    unsigned int reg1 = (reg + 1) % 32;
 	    unsigned int stk = reg < 16 ? 31 : 15;
-    	    unsigned long codecr[] =
+	    unsigned long codecr[] =
 	    {
 		ASM_STW(stk, 1, -4),
 		ASM_ADDI(stk, 1, -16),
@@ -112,7 +112,7 @@ int cpu_post_test_andi (void)
     }
 
     if (flag)
-    	enable_interrupts();
+	enable_interrupts();
 
     return ret;
 }
diff --git a/post/lib_ppc/cmp.c b/post/lib_ppc/cmp.c
index 89f754a0b1..8d80f86aaf 100644
--- a/post/lib_ppc/cmp.c
+++ b/post/lib_ppc/cmp.c
@@ -106,7 +106,7 @@ int cpu_post_test_cmp (void)
     for (i = 0; i < cpu_post_cmp_size && ret == 0; i++)
     {
 	struct cpu_post_cmp_s *test = cpu_post_cmp_table + i;
-    	unsigned long code[] =
+	unsigned long code[] =
 	{
 	    ASM_2C(test->cmd, test->cr, 3, 4),
 	    ASM_MFCR(3),
diff --git a/post/lib_ppc/cmpi.c b/post/lib_ppc/cmpi.c
index 0afdd71152..92b4d57b1f 100644
--- a/post/lib_ppc/cmpi.c
+++ b/post/lib_ppc/cmpi.c
@@ -106,7 +106,7 @@ int cpu_post_test_cmpi (void)
     for (i = 0; i < cpu_post_cmpi_size && ret == 0; i++)
     {
 	struct cpu_post_cmpi_s *test = cpu_post_cmpi_table + i;
-    	unsigned long code[] =
+	unsigned long code[] =
 	{
 	    ASM_1IC(test->cmd, test->cr, 3, test->op2),
 	    ASM_MFCR(3),
diff --git a/post/lib_ppc/cpu_asm.h b/post/lib_ppc/cpu_asm.h
index 1cbaf4121f..ef6fe61eff 100644
--- a/post/lib_ppc/cpu_asm.h
+++ b/post/lib_ppc/cpu_asm.h
@@ -191,7 +191,7 @@
 					 ((imm2) << 6) +	\
 					 ((imm3) << 1))
 #define ASM_1O(opcode, off)		((opcode) + (off))
-#define ASM_3O(opcode, bo, bi, off)	((opcode) + 		\
+#define ASM_3O(opcode, bo, bi, off)	((opcode) +		\
 					 ((bo) << 21) +		\
 					 ((bi) << 16) +		\
 					 (off))
diff --git a/post/lib_ppc/rlwimi.c b/post/lib_ppc/rlwimi.c
index 1d8e61ec1f..8662db16cd 100644
--- a/post/lib_ppc/rlwimi.c
+++ b/post/lib_ppc/rlwimi.c
@@ -53,7 +53,7 @@ static struct cpu_post_rlwimi_s
 } cpu_post_rlwimi_table[] =
 {
     {
-    	OP_RLWIMI,
+	OP_RLWIMI,
 	0xff00ffff,
 	0x0000aa00,
 	8,
@@ -80,7 +80,7 @@ int cpu_post_test_rlwimi (void)
 	    unsigned int reg0 = (reg + 0) % 32;
 	    unsigned int reg1 = (reg + 1) % 32;
 	    unsigned int stk = reg < 16 ? 31 : 15;
-    	    unsigned long code[] =
+	    unsigned long code[] =
 	    {
 		ASM_STW(stk, 1, -4),
 		ASM_ADDI(stk, 1, -20),
@@ -99,7 +99,7 @@ int cpu_post_test_rlwimi (void)
 		ASM_LWZ(stk, 1, -4),
 		ASM_BLR,
 	    };
-    	    unsigned long codecr[] =
+	    unsigned long codecr[] =
 	    {
 		ASM_STW(stk, 1, -4),
 		ASM_ADDI(stk, 1, -20),
@@ -124,26 +124,26 @@ int cpu_post_test_rlwimi (void)
 
 	    if (ret == 0)
 	    {
- 	    	cr = 0;
-	    	cpu_post_exec_22 (code, & cr, & res, test->op0, test->op1);
+		cr = 0;
+		cpu_post_exec_22 (code, & cr, & res, test->op0, test->op1);
 
-	    	ret = res == test->res && cr == 0 ? 0 : -1;
+		ret = res == test->res && cr == 0 ? 0 : -1;
 
-	    	if (ret != 0)
-	    	{
+		if (ret != 0)
+		{
 	            post_log ("Error at rlwimi test %d !\n", i);
-	    	}
+		}
 	    }
 
 	    if (ret == 0)
 	    {
-	    	cpu_post_exec_22 (codecr, & cr, & res, test->op0, test->op1);
+		cpu_post_exec_22 (codecr, & cr, & res, test->op0, test->op1);
 
-	    	ret = res == test->res &&
+		ret = res == test->res &&
 		      (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1;
 
-	    	if (ret != 0)
-	    	{
+		if (ret != 0)
+		{
 	            post_log ("Error at rlwimi test %d !\n", i);
 	        }
 	    }
@@ -151,7 +151,7 @@ int cpu_post_test_rlwimi (void)
     }
 
     if (flag)
-    	enable_interrupts();
+	enable_interrupts();
 
     return ret;
 }
diff --git a/post/lib_ppc/rlwinm.c b/post/lib_ppc/rlwinm.c
index 113e79d00a..4398a101ab 100644
--- a/post/lib_ppc/rlwinm.c
+++ b/post/lib_ppc/rlwinm.c
@@ -51,7 +51,7 @@ static struct cpu_post_rlwinm_s
 } cpu_post_rlwinm_table[] =
 {
    {
-   	OP_RLWINM,
+	OP_RLWINM,
 	0xffff0000,
 	24,
 	16,
@@ -77,7 +77,7 @@ int cpu_post_test_rlwinm (void)
 	    unsigned int reg0 = (reg + 0) % 32;
 	    unsigned int reg1 = (reg + 1) % 32;
 	    unsigned int stk = reg < 16 ? 31 : 15;
-    	    unsigned long code[] =
+	    unsigned long code[] =
 	    {
 		ASM_STW(stk, 1, -4),
 		ASM_ADDI(stk, 1, -16),
@@ -94,7 +94,7 @@ int cpu_post_test_rlwinm (void)
 		ASM_LWZ(stk, 1, -4),
 		ASM_BLR,
 	    };
-    	    unsigned long codecr[] =
+	    unsigned long codecr[] =
 	    {
 		ASM_STW(stk, 1, -4),
 		ASM_ADDI(stk, 1, -16),
@@ -117,26 +117,26 @@ int cpu_post_test_rlwinm (void)
 
 	    if (ret == 0)
 	    {
- 	    	cr = 0;
-	    	cpu_post_exec_21 (code, & cr, & res, test->op1);
+		cr = 0;
+		cpu_post_exec_21 (code, & cr, & res, test->op1);
 
-	    	ret = res == test->res && cr == 0 ? 0 : -1;
+		ret = res == test->res && cr == 0 ? 0 : -1;
 
-	    	if (ret != 0)
-	    	{
+		if (ret != 0)
+		{
 	            post_log ("Error at rlwinm test %d !\n", i);
-	    	}
+		}
 	    }
 
 	    if (ret == 0)
 	    {
-	    	cpu_post_exec_21 (codecr, & cr, & res, test->op1);
+		cpu_post_exec_21 (codecr, & cr, & res, test->op1);
 
-	    	ret = res == test->res &&
+		ret = res == test->res &&
 		      (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1;
 
-	    	if (ret != 0)
-	    	{
+		if (ret != 0)
+		{
 	            post_log ("Error at rlwinm test %d !\n", i);
 	        }
 	    }
@@ -144,7 +144,7 @@ int cpu_post_test_rlwinm (void)
     }
 
     if (flag)
-    	enable_interrupts();
+	enable_interrupts();
 
     return ret;
 }
diff --git a/post/lib_ppc/rlwnm.c b/post/lib_ppc/rlwnm.c
index a6684bf60b..c547bd779c 100644
--- a/post/lib_ppc/rlwnm.c
+++ b/post/lib_ppc/rlwnm.c
@@ -52,7 +52,7 @@ static struct cpu_post_rlwnm_s
 } cpu_post_rlwnm_table[] =
 {
    {
-   	OP_RLWNM,
+	OP_RLWNM,
 	0xffff0000,
 	24,
 	16,
@@ -79,7 +79,7 @@ int cpu_post_test_rlwnm (void)
 	    unsigned int reg1 = (reg + 1) % 32;
 	    unsigned int reg2 = (reg + 2) % 32;
 	    unsigned int stk = reg < 16 ? 31 : 15;
-    	    unsigned long code[] =
+	    unsigned long code[] =
 	    {
 		ASM_STW(stk, 1, -4),
 		ASM_ADDI(stk, 1, -24),
@@ -100,7 +100,7 @@ int cpu_post_test_rlwnm (void)
 		ASM_LWZ(stk, 1, -4),
 		ASM_BLR,
 	    };
-    	    unsigned long codecr[] =
+	    unsigned long codecr[] =
 	    {
 		ASM_STW(stk, 1, -4),
 		ASM_ADDI(stk, 1, -24),
@@ -127,26 +127,26 @@ int cpu_post_test_rlwnm (void)
 
 	    if (ret == 0)
 	    {
- 	    	cr = 0;
-	    	cpu_post_exec_22 (code, & cr, & res, test->op1, test->op2);
+		cr = 0;
+		cpu_post_exec_22 (code, & cr, & res, test->op1, test->op2);
 
-	    	ret = res == test->res && cr == 0 ? 0 : -1;
+		ret = res == test->res && cr == 0 ? 0 : -1;
 
-	    	if (ret != 0)
-	    	{
+		if (ret != 0)
+		{
 	            post_log ("Error at rlwnm test %d !\n", i);
-	    	}
+		}
 	    }
 
 	    if (ret == 0)
 	    {
-	    	cpu_post_exec_22 (codecr, & cr, & res, test->op1, test->op2);
+		cpu_post_exec_22 (codecr, & cr, & res, test->op1, test->op2);
 
-	    	ret = res == test->res &&
+		ret = res == test->res &&
 		      (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1;
 
-	    	if (ret != 0)
-	    	{
+		if (ret != 0)
+		{
 	            post_log ("Error at rlwnm test %d !\n", i);
 	        }
 	    }
@@ -154,7 +154,7 @@ int cpu_post_test_rlwnm (void)
     }
 
     if (flag)
-    	enable_interrupts();
+	enable_interrupts();
 
     return ret;
 }
diff --git a/post/lib_ppc/srawi.c b/post/lib_ppc/srawi.c
index 8c70007c54..4a3dddb92e 100644
--- a/post/lib_ppc/srawi.c
+++ b/post/lib_ppc/srawi.c
@@ -49,13 +49,13 @@ static struct cpu_post_srawi_s
 } cpu_post_srawi_table[] =
 {
     {
-    	OP_SRAWI,
+	OP_SRAWI,
 	0x8000,
 	3,
 	0x1000
     },
     {
-    	OP_SRAWI,
+	OP_SRAWI,
 	0x80000000,
 	3,
 	0xf0000000
@@ -79,7 +79,7 @@ int cpu_post_test_srawi (void)
 	    unsigned int reg0 = (reg + 0) % 32;
 	    unsigned int reg1 = (reg + 1) % 32;
 	    unsigned int stk = reg < 16 ? 31 : 15;
-    	    unsigned long code[] =
+	    unsigned long code[] =
 	    {
 		ASM_STW(stk, 1, -4),
 		ASM_ADDI(stk, 1, -16),
@@ -96,7 +96,7 @@ int cpu_post_test_srawi (void)
 		ASM_LWZ(stk, 1, -4),
 		ASM_BLR,
 	    };
-    	    unsigned long codecr[] =
+	    unsigned long codecr[] =
 	    {
 		ASM_STW(stk, 1, -4),
 		ASM_ADDI(stk, 1, -16),
@@ -118,26 +118,26 @@ int cpu_post_test_srawi (void)
 
 	    if (ret == 0)
 	    {
- 	    	cr = 0;
-	    	cpu_post_exec_21 (code, & cr, & res, test->op1);
+		cr = 0;
+		cpu_post_exec_21 (code, & cr, & res, test->op1);
 
-	    	ret = res == test->res && cr == 0 ? 0 : -1;
+		ret = res == test->res && cr == 0 ? 0 : -1;
 
-	    	if (ret != 0)
-	    	{
+		if (ret != 0)
+		{
 	            post_log ("Error at srawi test %d !\n", i);
-	    	}
+		}
 	    }
 
 	    if (ret == 0)
 	    {
-	    	cpu_post_exec_21 (codecr, & cr, & res, test->op1);
+		cpu_post_exec_21 (codecr, & cr, & res, test->op1);
 
-	    	ret = res == test->res &&
+		ret = res == test->res &&
 		      (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1;
 
-	    	if (ret != 0)
-	    	{
+		if (ret != 0)
+		{
 	            post_log ("Error at srawi test %d !\n", i);
 	        }
 	    }
@@ -145,7 +145,7 @@ int cpu_post_test_srawi (void)
     }
 
     if (flag)
-    	enable_interrupts();
+	enable_interrupts();
 
     return ret;
 }
diff --git a/post/lib_ppc/three.c b/post/lib_ppc/three.c
index a7f1a866fd..3fa513b91d 100644
--- a/post/lib_ppc/three.c
+++ b/post/lib_ppc/three.c
@@ -53,103 +53,103 @@ static struct cpu_post_three_s
 } cpu_post_three_table[] =
 {
     {
-    	OP_ADD,
+	OP_ADD,
 	100,
 	200,
 	300
     },
     {
-    	OP_ADD,
+	OP_ADD,
 	100,
 	-200,
 	-100
     },
     {
-    	OP_ADDC,
+	OP_ADDC,
 	100,
 	200,
 	300
     },
     {
-    	OP_ADDC,
+	OP_ADDC,
 	100,
 	-200,
 	-100
     },
     {
-    	OP_ADDE,
+	OP_ADDE,
 	100,
 	200,
 	300
     },
     {
-    	OP_ADDE,
+	OP_ADDE,
 	100,
 	-200,
 	-100
     },
     {
-    	OP_SUBF,
+	OP_SUBF,
 	100,
 	200,
 	100
     },
     {
-    	OP_SUBF,
+	OP_SUBF,
 	300,
 	200,
 	-100
     },
     {
-    	OP_SUBFC,
+	OP_SUBFC,
 	100,
 	200,
 	100
     },
     {
-    	OP_SUBFC,
+	OP_SUBFC,
 	300,
 	200,
 	-100
     },
     {
-    	OP_SUBFE,
+	OP_SUBFE,
 	100,
 	200,
 	200 + ~100
     },
     {
-    	OP_SUBFE,
+	OP_SUBFE,
 	300,
 	200,
 	200 + ~300
     },
     {
-    	OP_MULLW,
+	OP_MULLW,
 	200,
 	300,
 	200 * 300
     },
     {
-    	OP_MULHW,
+	OP_MULHW,
 	0x10000000,
 	0x10000000,
 	0x1000000
     },
     {
-    	OP_MULHWU,
+	OP_MULHWU,
 	0x80000000,
 	0x80000000,
 	0x40000000
     },
     {
-    	OP_DIVW,
+	OP_DIVW,
 	-20,
 	5,
 	-4
     },
     {
-    	OP_DIVWU,
+	OP_DIVWU,
 	0x8000,
 	0x200,
 	0x40
@@ -174,7 +174,7 @@ int cpu_post_test_three (void)
 	    unsigned int reg1 = (reg + 1) % 32;
 	    unsigned int reg2 = (reg + 2) % 32;
 	    unsigned int stk = reg < 16 ? 31 : 15;
-    	    unsigned long code[] =
+	    unsigned long code[] =
 	    {
 		ASM_STW(stk, 1, -4),
 		ASM_ADDI(stk, 1, -24),
@@ -195,7 +195,7 @@ int cpu_post_test_three (void)
 		ASM_LWZ(stk, 1, -4),
 		ASM_BLR,
 	    };
-    	    unsigned long codecr[] =
+	    unsigned long codecr[] =
 	    {
 		ASM_STW(stk, 1, -4),
 		ASM_ADDI(stk, 1, -24),
@@ -221,26 +221,26 @@ int cpu_post_test_three (void)
 
 	    if (ret == 0)
 	    {
- 	    	cr = 0;
-	    	cpu_post_exec_22 (code, & cr, & res, test->op1, test->op2);
+		cr = 0;
+		cpu_post_exec_22 (code, & cr, & res, test->op1, test->op2);
 
-	    	ret = res == test->res && cr == 0 ? 0 : -1;
+		ret = res == test->res && cr == 0 ? 0 : -1;
 
-	    	if (ret != 0)
-	    	{
+		if (ret != 0)
+		{
 	            post_log ("Error at three test %d !\n", i);
-	    	}
+		}
 	    }
 
 	    if (ret == 0)
 	    {
-	    	cpu_post_exec_22 (codecr, & cr, & res, test->op1, test->op2);
+		cpu_post_exec_22 (codecr, & cr, & res, test->op1, test->op2);
 
-	    	ret = res == test->res &&
+		ret = res == test->res &&
 		      (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1;
 
-	    	if (ret != 0)
-	    	{
+		if (ret != 0)
+		{
 	            post_log ("Error at three test %d !\n", i);
 	        }
 	    }
@@ -248,7 +248,7 @@ int cpu_post_test_three (void)
     }
 
     if (flag)
-    	enable_interrupts();
+	enable_interrupts();
 
     return ret;
 }
diff --git a/post/lib_ppc/threei.c b/post/lib_ppc/threei.c
index bbb4f50b7a..89f8fc8466 100644
--- a/post/lib_ppc/threei.c
+++ b/post/lib_ppc/threei.c
@@ -51,25 +51,25 @@ static struct cpu_post_threei_s
 } cpu_post_threei_table[] =
 {
     {
-    	OP_ORI,
+	OP_ORI,
 	0x80000000,
 	0xffff,
 	0x8000ffff
     },
     {
-    	OP_ORIS,
+	OP_ORIS,
 	0x00008000,
 	0xffff,
 	0xffff8000
     },
     {
-    	OP_XORI,
+	OP_XORI,
 	0x8000ffff,
 	0xffff,
 	0x80000000
     },
     {
-    	OP_XORIS,
+	OP_XORIS,
 	0x00008000,
 	0xffff,
 	0xffff8000
@@ -93,7 +93,7 @@ int cpu_post_test_threei (void)
 	    unsigned int reg0 = (reg + 0) % 32;
 	    unsigned int reg1 = (reg + 1) % 32;
 	    unsigned int stk = reg < 16 ? 31 : 15;
-    	    unsigned long code[] =
+	    unsigned long code[] =
 	    {
 		ASM_STW(stk, 1, -4),
 		ASM_ADDI(stk, 1, -16),
@@ -113,7 +113,7 @@ int cpu_post_test_threei (void)
 	    ulong res;
 	    ulong cr;
 
- 	    cr = 0;
+	    cr = 0;
 	    cpu_post_exec_21 (code, & cr, & res, test->op1);
 
 	    ret = res == test->res && cr == 0 ? 0 : -1;
@@ -126,7 +126,7 @@ int cpu_post_test_threei (void)
     }
 
     if (flag)
-    	enable_interrupts();
+	enable_interrupts();
 
     return ret;
 }
diff --git a/post/lib_ppc/threex.c b/post/lib_ppc/threex.c
index 6aac937890..1dfcc2ce06 100644
--- a/post/lib_ppc/threex.c
+++ b/post/lib_ppc/threex.c
@@ -53,73 +53,73 @@ static struct cpu_post_threex_s
 } cpu_post_threex_table[] =
 {
     {
-    	OP_OR,
+	OP_OR,
 	0x1234,
 	0x5678,
 	0x1234 | 0x5678
     },
     {
-    	OP_ORC,
+	OP_ORC,
 	0x1234,
 	0x5678,
 	0x1234 | ~0x5678
     },
     {
-    	OP_XOR,
+	OP_XOR,
 	0x1234,
 	0x5678,
 	0x1234 ^ 0x5678
     },
     {
-    	OP_NAND,
+	OP_NAND,
 	0x1234,
 	0x5678,
 	~(0x1234 & 0x5678)
     },
     {
-    	OP_NOR,
+	OP_NOR,
 	0x1234,
 	0x5678,
 	~(0x1234 | 0x5678)
     },
     {
-    	OP_EQV,
+	OP_EQV,
 	0x1234,
 	0x5678,
 	~(0x1234 ^ 0x5678)
     },
     {
-    	OP_SLW,
+	OP_SLW,
 	0x80,
 	16,
 	0x800000
     },
     {
-    	OP_SLW,
+	OP_SLW,
 	0x80,
 	32,
 	0
     },
     {
-    	OP_SRW,
+	OP_SRW,
 	0x800000,
 	16,
 	0x80
     },
     {
-    	OP_SRW,
+	OP_SRW,
 	0x800000,
 	32,
 	0
     },
     {
-    	OP_SRAW,
+	OP_SRAW,
 	0x80000000,
 	3,
 	0xf0000000
     },
     {
-    	OP_SRAW,
+	OP_SRAW,
 	0x8000,
 	3,
 	0x1000
@@ -144,7 +144,7 @@ int cpu_post_test_threex (void)
 	    unsigned int reg1 = (reg + 1) % 32;
 	    unsigned int reg2 = (reg + 2) % 32;
 	    unsigned int stk = reg < 16 ? 31 : 15;
-    	    unsigned long code[] =
+	    unsigned long code[] =
 	    {
 		ASM_STW(stk, 1, -4),
 		ASM_ADDI(stk, 1, -24),
@@ -165,7 +165,7 @@ int cpu_post_test_threex (void)
 		ASM_LWZ(stk, 1, -4),
 		ASM_BLR,
 	    };
-    	    unsigned long codecr[] =
+	    unsigned long codecr[] =
 	    {
 		ASM_STW(stk, 1, -4),
 		ASM_ADDI(stk, 1, -24),
@@ -191,26 +191,26 @@ int cpu_post_test_threex (void)
 
 	    if (ret == 0)
 	    {
- 	    	cr = 0;
-	    	cpu_post_exec_22 (code, & cr, & res, test->op1, test->op2);
+		cr = 0;
+		cpu_post_exec_22 (code, & cr, & res, test->op1, test->op2);
 
-	    	ret = res == test->res && cr == 0 ? 0 : -1;
+		ret = res == test->res && cr == 0 ? 0 : -1;
 
-	    	if (ret != 0)
-	    	{
+		if (ret != 0)
+		{
 	            post_log ("Error at threex test %d !\n", i);
-	    	}
+		}
 	    }
 
 	    if (ret == 0)
 	    {
-	    	cpu_post_exec_22 (codecr, & cr, & res, test->op1, test->op2);
+		cpu_post_exec_22 (codecr, & cr, & res, test->op1, test->op2);
 
-	    	ret = res == test->res &&
+		ret = res == test->res &&
 		      (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1;
 
-	    	if (ret != 0)
-	    	{
+		if (ret != 0)
+		{
 	            post_log ("Error at threex test %d !\n", i);
 	        }
 	    }
@@ -218,7 +218,7 @@ int cpu_post_test_threex (void)
     }
 
     if (flag)
-    	enable_interrupts();
+	enable_interrupts();
 
     return ret;
 }
diff --git a/post/lib_ppc/twox.c b/post/lib_ppc/twox.c
index 7417a36808..519b432002 100644
--- a/post/lib_ppc/twox.c
+++ b/post/lib_ppc/twox.c
@@ -51,32 +51,32 @@ static struct cpu_post_twox_s
 } cpu_post_twox_table[] =
 {
     {
-    	OP_EXTSB,
+	OP_EXTSB,
 	3,
 	3
     },
     {
-    	OP_EXTSB,
+	OP_EXTSB,
 	0xff,
 	-1
     },
     {
-    	OP_EXTSH,
+	OP_EXTSH,
 	3,
 	3
     },
     {
-    	OP_EXTSH,
+	OP_EXTSH,
 	0xff,
 	0xff
     },
     {
-    	OP_EXTSH,
+	OP_EXTSH,
 	0xffff,
 	-1
     },
     {
-    	OP_CNTLZW,
+	OP_CNTLZW,
 	0x000fffff,
 	12
     },
@@ -99,7 +99,7 @@ int cpu_post_test_twox (void)
 	    unsigned int reg0 = (reg + 0) % 32;
 	    unsigned int reg1 = (reg + 1) % 32;
 	    unsigned int stk = reg < 16 ? 31 : 15;
-    	    unsigned long code[] =
+	    unsigned long code[] =
 	    {
 		ASM_STW(stk, 1, -4),
 		ASM_ADDI(stk, 1, -16),
@@ -116,7 +116,7 @@ int cpu_post_test_twox (void)
 		ASM_LWZ(stk, 1, -4),
 		ASM_BLR,
 	    };
-    	    unsigned long codecr[] =
+	    unsigned long codecr[] =
 	    {
 		ASM_STW(stk, 1, -4),
 		ASM_ADDI(stk, 1, -16),
@@ -138,26 +138,26 @@ int cpu_post_test_twox (void)
 
 	    if (ret == 0)
 	    {
- 	    	cr = 0;
-	    	cpu_post_exec_21 (code, & cr, & res, test->op);
+		cr = 0;
+		cpu_post_exec_21 (code, & cr, & res, test->op);
 
-	    	ret = res == test->res && cr == 0 ? 0 : -1;
+		ret = res == test->res && cr == 0 ? 0 : -1;
 
-	    	if (ret != 0)
-	    	{
+		if (ret != 0)
+		{
 	            post_log ("Error at twox test %d !\n", i);
-	    	}
+		}
 	    }
 
 	    if (ret == 0)
 	    {
-	    	cpu_post_exec_21 (codecr, & cr, & res, test->op);
+		cpu_post_exec_21 (codecr, & cr, & res, test->op);
 
-	    	ret = res == test->res &&
+		ret = res == test->res &&
 		      (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1;
 
-	    	if (ret != 0)
-	    	{
+		if (ret != 0)
+		{
 	            post_log ("Error at twox test %d !\n", i);
 	        }
 	    }
@@ -165,7 +165,7 @@ int cpu_post_test_twox (void)
     }
 
     if (flag)
-    	enable_interrupts();
+	enable_interrupts();
 
     return ret;
 }
diff --git a/post/post.c b/post/post.c
index c016c3ae40..d31829ba16 100644
--- a/post/post.c
+++ b/post/post.c
@@ -238,14 +238,20 @@ static int post_run_single (struct post_test *test,
 		if (test_flags & POST_PREREL) {
 			if ((*test->test) (flags) == 0)
 				post_log_mark_succ ( test->testid );
-			else if (test_flags & POST_CRITICAL)
-				gd->flags |= GD_FLG_POSTFAIL;
+			else {
+				if (test_flags & POST_CRITICAL)
+					gd->flags |= GD_FLG_POSTFAIL;
+				if (test_flags & POST_STOP)
+					gd->flags |= GD_FLG_POSTSTOP;
+			}
 		} else {
 		if ((*test->test) (flags) != 0) {
 			post_log ("FAILED\n");
 			show_boot_progress (-32);
 			if (test_flags & POST_CRITICAL)
 				gd->flags |= GD_FLG_POSTFAIL;
+			if (test_flags & POST_STOP)
+				gd->flags |= GD_FLG_POSTSTOP;
 		}
 		else
 			post_log ("PASSED\n");
@@ -271,6 +277,9 @@ int post_run (char *name, int flags)
 	if (name == NULL) {
 		unsigned int last;
 
+		if (gd->flags & GD_FLG_POSTSTOP)
+			return 0;
+
 		if (post_bootmode_get (&last) & POST_POWERTEST) {
 			if (last & POST_FAIL_SAVE) {
 				last &= ~POST_FAIL_SAVE;
@@ -285,6 +294,8 @@ int post_run (char *name, int flags)
 						 flags | POST_REBOOT, last);
 
 				for (i = last + 1; i < post_list_size; i++) {
+					if (gd->flags & GD_FLG_POSTSTOP)
+						break;
 					post_run_single (post_list + i,
 							 test_flags[i],
 							 flags, i);
@@ -292,6 +303,8 @@ int post_run (char *name, int flags)
 			}
 		} else {
 			for (i = 0; i < post_list_size; i++) {
+				if (gd->flags & GD_FLG_POSTSTOP)
+					break;
 				post_run_single (post_list + i,
 						 test_flags[i],
 						 flags, i);
diff --git a/post/rules.mk b/post/rules.mk
index 94e72bec62..1efc9c7d97 100644
--- a/post/rules.mk
+++ b/post/rules.mk
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
 
 COBJS	:= $(COBJS-y)
 AOBJS	:= $(AOBJS-y)
-SRCS 	:= $(AOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS	:= $(AOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(AOBJS) $(COBJS))
 LIB	:= $(obj)$(LIB)
 
diff --git a/post/tests.c b/post/tests.c
index 36473e311f..a790c789d6 100644
--- a/post/tests.c
+++ b/post/tests.c
@@ -29,6 +29,7 @@
 
 #include <post.h>
 
+extern int ocm_post_test (int flags);
 extern int cache_post_test (int flags);
 extern int watchdog_post_test (int flags);
 extern int i2c_post_test (int flags);
@@ -60,6 +61,18 @@ extern void sysmon_reloc (void);
 
 struct post_test post_list[] =
 {
+#if CONFIG_POST & CFG_POST_OCM
+    {
+	"OCM test",
+	"ocm",
+	"This test checks on chip memory (OCM).",
+	POST_ROM | POST_ALWAYS | POST_PREREL | POST_CRITICAL | POST_STOP,
+	&ocm_post_test,
+	NULL,
+	NULL,
+	CFG_POST_OCM
+    },
+#endif
 #if CONFIG_POST & CFG_POST_CACHE
     {
 	"Cache test",
@@ -270,7 +283,7 @@ struct post_test post_list[] =
 #if CONFIG_POST & CFG_POST_BSPEC4
 	CONFIG_POST_BSPEC4,
 #endif
-#if CONFIG_POST & CFG_POST_BSPEC4
+#if CONFIG_POST & CFG_POST_BSPEC5
 	CONFIG_POST_BSPEC5,
 #endif
 };
diff --git a/tools/Makefile b/tools/Makefile
index b89792327d..5285055dc8 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -224,7 +224,7 @@ else
 			HOSTOS=$(HOSTOS) \
 			HOSTARCH=$(HOSTARCH) \
 			HOST_CFLAGS="$(HOST_CFLAGS)" \
-		   	HOST_LDFLAGS="$(HOST_LDFLAGS)" \
+			HOST_LDFLAGS="$(HOST_LDFLAGS)" \
 			-C $$dir || exit 1 ; \
 		done
 endif
diff --git a/tools/easylogo/easylogo.c b/tools/easylogo/easylogo.c
index c20e6a717c..00a1e4ed16 100644
--- a/tools/easylogo/easylogo.c
+++ b/tools/easylogo/easylogo.c
@@ -332,7 +332,7 @@ int image_save_header (image_t * image, char *filename, char *varname)
 	if (col)
 		fprintf (file, "%s\n", str);
 
-	/* 	End of declaration */
+	/*	End of declaration */
 	fprintf (file, "};\n\n");
 	/*	Variable */
 	fprintf (file, "fastimage_t %s = {\n", varname);
diff --git a/tools/env/fw_env.h b/tools/env/fw_env.h
index 248f58c4a0..c04da541fb 100644
--- a/tools/env/fw_env.h
+++ b/tools/env/fw_env.h
@@ -42,9 +42,9 @@
 #define CONFIG_BAUDRATE		115200
 #define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
 #define CONFIG_BOOTCOMMAND							\
-	"bootp; " 								\
-	"setenv bootargs root=/dev/nfs nfsroot=${serverip}:${rootpath} " 	\
-	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " 	\
+	"bootp; "								\
+	"setenv bootargs root=/dev/nfs nfsroot=${serverip}:${rootpath} "	\
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "	\
 	"bootm"
 
 extern int   fw_printenv(int argc, char *argv[]);
diff --git a/tools/gdb/remote.c b/tools/gdb/remote.c
index f40b6c6386..c76a7ba19b 100644
--- a/tools/gdb/remote.c
+++ b/tools/gdb/remote.c
@@ -268,7 +268,7 @@ remote_continue(void)
 
 	remote restart	RXX		Restart the remote server
 
-	extended ops 	!		Use the extended remote protocol.
+	extended ops	!		Use the extended remote protocol.
 					Sticky -- only needs to be set once.
 
 	kill request	k