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authorAnurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com>2017-07-04 20:03:42 +0530
committerMichal Simek <michal.simek@xilinx.com>2017-11-28 16:09:08 +0100
commit110d06b2e35f7e7b7c36cd5cbc48ed9f09f15b9e (patch)
tree31a62d7b38f1e987c3ff62f5edbf345e7bd3bd60
parentec2b2d4c535f62833b5354c64ca181fac6cf6577 (diff)
arm64: zynqmp: Add SMMU support for SATA IP
AXI master interface in CEVA AHCI controller requires two unique Write/Read ID tags per port. This is because, ahci controller uses different AXI ID[3:0] bits for identifying non-data transfers(like reading descriptors, updating PRD tables, etc) and data transfers (like sending/receiving FIS).To make SMMU work with SATA we need to add correct SMMU stream id for SATA. SMMU stream id for SATA is determined based on the AXI ID[1:0] as shown below SATA SMMU ID = <TBU number>, 0011, 00, 00, AXI ID[1:0] Note: SATA in ZynqMp uses TBU1 so TBU number = 0x1, so SMMU ID = 001, 0011, 00, 00, AXI ID[1:0] Since we have four different AXI ID[3:0] (2 for port0 & 2 for port1 as said above) we get four different SMMU stream id's combinations for SATA. These AXI ID can be configured using PAXIC register. In this patch we assumed the below AXI ID values Read ID/ Write ID for Non-Data Port0 transfers = 0 Read ID/ Write ID for Data Port0 transfers = 1 Read ID/ Write ID for Non-Data Port1 transfers = 2 Read ID/ Write ID for Data Port1 transfers = 3 Based on the above values,SMMU stream ID's for SATA will be 0x4c0 & 0x4c1 for PORT0, 0x4c2 & 0x4c3 for PORT1. These values needed to be added to iommus dts property. This patch does the same. Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
-rw-r--r--arch/arm/dts/zynqmp.dtsi4
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index c1900e9c95..f2c0b5ebf9 100644
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -796,6 +796,10 @@
interrupt-parent = <&gic>;
interrupts = <0 133 4>;
power-domains = <&pd_sata>;
+ #stream-id-cells = <4>;
+ iommus = <&smmu 0x4c0>, <&smmu 0x4c1>,
+ <&smmu 0x4c2>, <&smmu 0x4c3>;
+ /* dma-coherent; */
};
sdhci0: sdhci@ff160000 {