diff options
| author | Mingkai Hu <mingkai.hu@nxp.com> | 2016-09-07 17:56:08 +0800 |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2016-09-14 14:10:02 -0700 |
| commit | 13f7988067856845ef593795003160db5ccf43cd (patch) | |
| tree | a5bc36d5777e7938a0c7198fd9e94b3d9174f70e | |
| parent | 9578c4273d4b9d24403bf4e03d7729f381527cd8 (diff) | |
armv8: fsl-layerscape: Increase L2 Data RAM latency and L2 Tag RAM latency
According to design specification, the L2 cache operates at the same
frequency as the A72 CPUs in the cluster with a 3-cycle latency, so
increase the L2 Data RAM and Tag RAM latency to 3 cycles, or else,
will run into different call trace issues.
Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S index 5af6b73bc9..6451a36e54 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S @@ -179,6 +179,21 @@ ENTRY(lowlevel_init) isb dsb sy #endif + +#ifdef CONFIG_LS1046A + /* Initialize the L2 RAM latency */ + mrs x1, S3_1_c11_c0_2 + mov x0, #0x1C7 + /* Clear L2 Tag RAM latency and L2 Data RAM latency */ + bic x1, x1, x0 + /* Set L2 data ram latency bits [2:0] */ + orr x1, x1, #0x2 + /* set L2 tag ram latency bits [8:6] */ + orr x1, x1, #0x80 + msr S3_1_c11_c0_2, x1 + isb +#endif + mov lr, x29 /* Restore LR */ ret ENDPROC(lowlevel_init) |