diff options
| author | Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> | 2017-04-13 16:59:38 +0530 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2017-08-02 09:11:52 +0200 |
| commit | 154799ac956ac991249366801b70c9714a21e533 (patch) | |
| tree | c9c5ccbbedf33f73d1efe1e09701cd816dd5e494 | |
| parent | ad76f8cedf61fa1e307a4b4243e3ff58ade8ec9e (diff) | |
clk: zynqmp: Dont panic incase of mmio write/read failures
Dont panic incase of mmio write/read failures instead return
error and let the peripheral driver take care of clock get
and set failures.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
| -rw-r--r-- | drivers/clk/clk_zynqmp.c | 63 |
1 files changed, 44 insertions, 19 deletions
diff --git a/drivers/clk/clk_zynqmp.c b/drivers/clk/clk_zynqmp.c index 247b55e850..b5469f73ee 100644 --- a/drivers/clk/clk_zynqmp.c +++ b/drivers/clk/clk_zynqmp.c @@ -318,8 +318,10 @@ static ulong zynqmp_clk_get_pll_rate(struct zynqmp_clk_priv *priv, int ret; ret = zynqmp_mmio_read(zynqmp_clk_get_register(id), &clk_ctrl); - if (ret) - panic("%s mio read fail\n", __func__); + if (ret) { + printf("%s mio read fail\n", __func__); + return -EIO; + } if (clk_ctrl & PLLCTRL_BYPASS_MASK) freq = zynqmp_clk_get_pll_src(clk_ctrl, priv, 0); @@ -346,17 +348,22 @@ static ulong zynqmp_clk_get_cpu_rate(struct zynqmp_clk_priv *priv, u32 clk_ctrl, div; enum zynqmp_clk pll; int ret; + unsigned long pllrate; ret = zynqmp_mmio_read(CRF_APB_ACPU_CTRL, &clk_ctrl); - if (ret) - panic("%s mio read fail\n", __func__); - + if (ret) { + printf("%s mio read fail\n", __func__); + return -EIO; + } div = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT; pll = zynqmp_clk_get_cpu_pll(clk_ctrl); + pllrate = zynqmp_clk_get_pll_rate(priv, pll); + if (IS_ERR_VALUE(pllrate)) + return pllrate; - return DIV_ROUND_CLOSEST(zynqmp_clk_get_pll_rate(priv, pll), div); + return DIV_ROUND_CLOSEST(pllrate, div); } static ulong zynqmp_clk_get_ddr_rate(struct zynqmp_clk_priv *priv) @@ -364,16 +371,22 @@ static ulong zynqmp_clk_get_ddr_rate(struct zynqmp_clk_priv *priv) u32 clk_ctrl, div; enum zynqmp_clk pll; int ret; + ulong pllrate; ret = zynqmp_mmio_read(CRF_APB_DDR_CTRL, &clk_ctrl); - if (ret) - panic("%s mio read fail\n", __func__); + if (ret) { + printf("%s mio read fail\n", __func__); + return -EIO; + } div = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT; pll = zynqmp_clk_get_ddr_pll(clk_ctrl); + pllrate = zynqmp_clk_get_pll_rate(priv, pll); + if (IS_ERR_VALUE(pllrate)) + return pllrate; - return DIV_ROUND_CLOSEST(zynqmp_clk_get_pll_rate(priv, pll), div); + return DIV_ROUND_CLOSEST(pllrate, div); } static ulong zynqmp_clk_get_peripheral_rate(struct zynqmp_clk_priv *priv, @@ -383,10 +396,13 @@ static ulong zynqmp_clk_get_peripheral_rate(struct zynqmp_clk_priv *priv, u32 clk_ctrl, div0; u32 div1 = 1; int ret; + ulong pllrate; ret = zynqmp_mmio_read(zynqmp_clk_get_register(id), &clk_ctrl); - if (ret) - panic("%s mio read fail\n", __func__); + if (ret) { + printf("%s mio read fail\n", __func__); + return -EIO; + } div0 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT; if (!div0) @@ -399,12 +415,13 @@ static ulong zynqmp_clk_get_peripheral_rate(struct zynqmp_clk_priv *priv, } pll = zynqmp_clk_get_peripheral_pll(clk_ctrl); + pllrate = zynqmp_clk_get_pll_rate(priv, pll); + if (IS_ERR_VALUE(pllrate)) + return pllrate; return DIV_ROUND_CLOSEST( - DIV_ROUND_CLOSEST( - zynqmp_clk_get_pll_rate(priv, pll), div0), - div1); + DIV_ROUND_CLOSEST(pllrate, div0), div1); } static unsigned long zynqmp_clk_calc_peripheral_two_divs(ulong rate, @@ -446,11 +463,16 @@ static ulong zynqmp_clk_set_peripheral_rate(struct zynqmp_clk_priv *priv, reg = zynqmp_clk_get_register(id); ret = zynqmp_mmio_read(reg, &clk_ctrl); - if (ret) - panic("%s mio read fail\n", __func__); + if (ret) { + printf("%s mio read fail\n", __func__); + return -EIO; + } pll = zynqmp_clk_get_peripheral_pll(clk_ctrl); pll_rate = zynqmp_clk_get_pll_rate(priv, pll); + if (IS_ERR_VALUE(pll_rate)) + return pll_rate; + clk_ctrl &= ~CLK_CTRL_DIV0_MASK; if (two_divs) { clk_ctrl &= ~CLK_CTRL_DIV1_MASK; @@ -469,8 +491,10 @@ static ulong zynqmp_clk_set_peripheral_rate(struct zynqmp_clk_priv *priv, (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV1_SHIFT); ret = zynqmp_mmio_write(reg, mask, clk_ctrl); - if (ret) - panic("%s mio write fail\n", __func__); + if (ret) { + printf("%s mio write fail\n", __func__); + return -EIO; + } return new_rate; } @@ -540,7 +564,8 @@ int soc_clk_dump(void) clk_free(&clk); if ((rate == (unsigned long)-ENOSYS) || - (rate == (unsigned long)-ENXIO)) + (rate == (unsigned long)-ENXIO) || + (rate == (unsigned long)-EIO)) printf("%10s%20s\n", name, "unknown"); else printf("%10s%20lu\n", name, rate); |