diff options
| author | Dirk Eibach <dirk.eibach@gdsys.cc> | 2015-10-28 11:46:29 +0100 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2015-11-12 15:59:04 -0500 |
| commit | 1c7639ae8a7bc7b4475bd45dc2c44e59467f9a70 (patch) | |
| tree | a1b7f2103c2ad991d7d22e9aef4138ae049c3f32 | |
| parent | e1d1127a9a8547ad9a7bda14285e97d6cc4be6dd (diff) | |
controlcenterd: Disable sideband clocks
Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
| -rw-r--r-- | board/gdsys/p1022/controlcenterd.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/board/gdsys/p1022/controlcenterd.c b/board/gdsys/p1022/controlcenterd.c index 64d90dd3fd..2f98e4757f 100644 --- a/board/gdsys/p1022/controlcenterd.c +++ b/board/gdsys/p1022/controlcenterd.c @@ -57,6 +57,8 @@ struct ihs_fpga { u32 versions; /* 0x0004 */ u32 fpga_version; /* 0x0008 */ u32 fpga_features; /* 0x000c */ + u32 reserved[4]; /* 0x0010 */ + u32 control; /* 0x0020 */ }; #ifndef CONFIG_TRAILBLAZER @@ -384,6 +386,9 @@ static void hydra_initialize(void) fpga = pci_map_bar(devno, PCI_BASE_ADDRESS_0, PCI_REGION_MEM); + /* disable sideband clocks */ + writel(1, &fpga->control); + versions = readl(&fpga->versions); fpga_version = readl(&fpga->fpga_version); fpga_features = readl(&fpga->fpga_features); |