diff options
author | Tom Rini <trini@konsulko.com> | 2016-09-22 16:51:19 -0400 |
---|---|---|
committer | Tom Rini <trini@konsulko.com> | 2016-09-22 16:51:19 -0400 |
commit | 201c9d884dcadb4e76981c30e9915f73de2d09b5 (patch) | |
tree | af1030f3a441f1538085eaa586e0e8392f2429ab | |
parent | 82f5279b0cd99a9163d34cfe926d0316d9dc0d37 (diff) | |
parent | 4f0b8efa50a543efd407fb8b2e9ad0de49467a15 (diff) |
Merge git://git.denx.de/u-boot-rockchip
26 files changed, 1391 insertions, 26 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 5de3bfcc9f..0083bf9ef0 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -898,6 +898,7 @@ config ARCH_ROCKCHIP select DM_SERIAL select DM_SPI select DM_SPI_FLASH + select DM_USB if USB config TARGET_THUNDERX_88XX bool "Support ThunderX 88xx" diff --git a/arch/arm/dts/rk3399-evb.dts b/arch/arm/dts/rk3399-evb.dts index e92a492545..bd7801b9a5 100644 --- a/arch/arm/dts/rk3399-evb.dts +++ b/arch/arm/dts/rk3399-evb.dts @@ -43,6 +43,12 @@ regulator-always-on; regulator-boot-on; }; + + vcc5v0_host: vcc5v0-host-en { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>; + }; }; &emmc_phy { @@ -85,6 +91,10 @@ status = "okay"; }; +&dwc3_typec0 { + status = "okay"; +}; + &usb_host1_ehci { status = "okay"; }; @@ -93,6 +103,10 @@ status = "okay"; }; +&dwc3_typec1 { + status = "okay"; +}; + &pinctrl { pmic { pmic_int_l: pmic-int-l { diff --git a/arch/arm/dts/rk3399.dtsi b/arch/arm/dts/rk3399.dtsi index a4c6e27b39..179860c900 100644 --- a/arch/arm/dts/rk3399.dtsi +++ b/arch/arm/dts/rk3399.dtsi @@ -9,6 +9,7 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/pinctrl/rockchip.h> +#define USB_CLASS_HUB 9 / { compatible = "rockchip,rk3399"; @@ -175,6 +176,8 @@ clocks = <&cru SCLK_SDMMC>, <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; clock-names = "ciu", "biu", "ciu-drive", "ciu-sample"; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk>; fifo-depth = <0x100>; status = "disabled"; }; @@ -228,6 +231,50 @@ status = "disabled"; }; + dwc3_typec0: usb@fe800000 { + compatible = "rockchip,rk3399-xhci"; + reg = <0x0 0xfe800000 0x0 0x100000>; + status = "disabled"; + rockchip,vbus-gpio = <&gpio1 3 GPIO_ACTIVE_HIGH>; + snps,dis-enblslpm-quirk; + snps,phyif-utmi-bits = <16>; + snps,dis-u2-freeclk-exists-quirk; + snps,dis-u2-susphy-quirk; + + #address-cells = <2>; + #size-cells = <2>; + hub { + compatible = "usb-hub"; + usb,device-class = <USB_CLASS_HUB>; + }; + typec_phy0 { + compatible = "rockchip,rk3399-usb3-phy"; + reg = <0x0 0xff7c0000 0x0 0x40000>; + }; + }; + + dwc3_typec1: usb@fe900000 { + compatible = "rockchip,rk3399-xhci"; + reg = <0x0 0xfe900000 0x0 0x100000>; + status = "disabled"; + rockchip,vbus-gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>; + snps,dis-enblslpm-quirk; + snps,phyif-utmi-bits = <16>; + snps,dis-u2-freeclk-exists-quirk; + snps,dis-u2-susphy-quirk; + + #address-cells = <2>; + #size-cells = <2>; + hub { + compatible = "usb-hub"; + usb,device-class = <USB_CLASS_HUB>; + }; + typec_phy1 { + compatible = "rockchip,rk3399-usb3-phy"; + reg = <0x0 0xff800000 0x0 0x40000>; + }; + }; + gic: interrupt-controller@fee00000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; @@ -771,6 +818,41 @@ }; }; + sdmmc { + sdmmc_bus1: sdmmc-bus1 { + rockchip,pins = + <4 8 RK_FUNC_1 &pcfg_pull_up>; + }; + + sdmmc_bus4: sdmmc-bus4 { + rockchip,pins = + <4 8 RK_FUNC_1 &pcfg_pull_up>, + <4 9 RK_FUNC_1 &pcfg_pull_up>, + <4 10 RK_FUNC_1 &pcfg_pull_up>, + <4 11 RK_FUNC_1 &pcfg_pull_up>; + }; + + sdmmc_clk: sdmmc-clk { + rockchip,pins = + <4 12 RK_FUNC_1 &pcfg_pull_none>; + }; + + sdmmc_cmd: sdmmc-cmd { + rockchip,pins = + <4 13 RK_FUNC_1 &pcfg_pull_up>; + }; + + sdmmc_cd: sdmcc-cd { + rockchip,pins = + <0 7 RK_FUNC_1 &pcfg_pull_up>; + }; + + sdmmc_wp: sdmmc-wp { + rockchip,pins = + <0 8 RK_FUNC_1 &pcfg_pull_up>; + }; + }; + spdif { spdif_bus: spdif-bus { rockchip,pins = diff --git a/arch/arm/include/asm/arch-rockchip/clock.h b/arch/arm/include/asm/arch-rockchip/clock.h index 21edbc2f89..804c77beaa 100644 --- a/arch/arm/include/asm/arch-rockchip/clock.h +++ b/arch/arm/include/asm/arch-rockchip/clock.h @@ -16,6 +16,7 @@ enum { ROCKCHIP_SYSCON_GRF, ROCKCHIP_SYSCON_SGRF, ROCKCHIP_SYSCON_PMU, + ROCKCHIP_SYSCON_PMUGRF, }; /* Standard Rockchip clock numbers */ diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h new file mode 100644 index 0000000000..d3d1467ea4 --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h @@ -0,0 +1,321 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __SOC_ROCKCHIP_RK3399_GRF_H__ +#define __SOC_ROCKCHIP_RK3399_GRF_H__ + +struct rk3399_grf_regs { + u32 reserved[0x800]; + u32 usb3_perf_con0; + u32 usb3_perf_con1; + u32 usb3_perf_con2; + u32 usb3_perf_rd_max_latency_num; + u32 usb3_perf_rd_latency_samp_num; + u32 usb3_perf_rd_latency_acc_num; + u32 usb3_perf_rd_axi_total_byte; + u32 usb3_perf_wr_axi_total_byte; + u32 usb3_perf_working_cnt; + u32 reserved1[0x103]; + u32 usb3otg0_con0; + u32 usb3otg0_con1; + u32 reserved2[2]; + u32 usb3otg1_con0; + u32 usb3otg1_con1; + u32 reserved3[2]; + u32 usb3otg0_status_lat0; + u32 usb3otg0_status_lat1; + u32 usb3otg0_status_cb; + u32 reserved4; + u32 usb3otg1_status_lat0; + u32 usb3otg1_status_lat1; + u32 usb3ogt1_status_cb; + u32 reserved5[0x6e5]; + u32 pcie_perf_con0; + u32 pcie_perf_con1; + u32 pcie_perf_con2; + u32 pcie_perf_rd_max_latency_num; + u32 pcie_perf_rd_latency_samp_num; + u32 pcie_perf_rd_laterncy_acc_num; + u32 pcie_perf_rd_axi_total_byte; + u32 pcie_perf_wr_axi_total_byte; + u32 pcie_perf_working_cnt; + u32 reserved6[0x37]; + u32 usb20_host0_con0; + u32 usb20_host0_con1; + u32 reserved7[2]; + u32 usb20_host1_con0; + u32 usb20_host1_con1; + u32 reserved8[2]; + u32 hsic_con0; + u32 hsic_con1; + u32 reserved9[6]; + u32 grf_usbhost0_status; + u32 grf_usbhost1_Status; + u32 grf_hsic_status; + u32 reserved10[0xc9]; + u32 hsicphy_con0; + u32 reserved11[3]; + u32 usbphy0_ctrl[26]; + u32 reserved12[6]; + u32 usbphy1[26]; + u32 reserved13[0x72f]; + u32 soc_con9; + u32 reserved14[0x0a]; + u32 soc_con20; + u32 soc_con21; + u32 soc_con22; + u32 soc_con23; + u32 soc_con24; + u32 soc_con25; + u32 soc_con26; + u32 reserved15[0xf65]; + u32 cpu_con[4]; + u32 reserved16[0x1c]; + u32 cpu_status[6]; + u32 reserved17[0x1a]; + u32 a53_perf_con[4]; + u32 a53_perf_rd_mon_st; + u32 a53_perf_rd_mon_end; + u32 a53_perf_wr_mon_st; + u32 a53_perf_wr_mon_end; + u32 a53_perf_rd_max_latency_num; + u32 a53_perf_rd_latency_samp_num; + u32 a53_perf_rd_laterncy_acc_num; + u32 a53_perf_rd_axi_total_byte; + u32 a53_perf_wr_axi_total_byte; + u32 a53_perf_working_cnt; + u32 a53_perf_int_status; + u32 reserved18[0x31]; + u32 a72_perf_con[4]; + u32 a72_perf_rd_mon_st; + u32 a72_perf_rd_mon_end; + u32 a72_perf_wr_mon_st; + u32 a72_perf_wr_mon_end; + u32 a72_perf_rd_max_latency_num; + u32 a72_perf_rd_latency_samp_num; + u32 a72_perf_rd_laterncy_acc_num; + u32 a72_perf_rd_axi_total_byte; + u32 a72_perf_wr_axi_total_byte; + u32 a72_perf_working_cnt; + u32 a72_perf_int_status; + u32 reserved19[0x7f6]; + u32 soc_con5; + u32 soc_con6; + u32 reserved20[0x779]; + u32 gpio2a_iomux; + union { + u32 iomux_spi2; + u32 gpio2b_iomux; + }; + union { + u32 gpio2c_iomux; + u32 iomux_spi5; + }; + u32 gpio2d_iomux; + union { + u32 gpio3a_iomux; + u32 iomux_spi0; + }; + u32 gpio3b_iomux; + u32 gpio3c_iomux; + union { + u32 iomux_i2s0; + u32 gpio3d_iomux; + }; + union { + u32 iomux_i2sclk; + u32 gpio4a_iomux; + }; + union { + u32 iomux_sdmmc; + u32 iomux_uart2a; + u32 gpio4b_iomux; + }; + union { + u32 iomux_pwm_0; + u32 iomux_pwm_1; + u32 iomux_uart2b; + u32 iomux_uart2c; + u32 iomux_edp_hotplug; + u32 gpio4c_iomux; + }; + u32 gpio4d_iomux; + u32 reserved21[4]; + u32 gpio2_p[3][4]; + u32 reserved22[4]; + u32 gpio2_sr[3][4]; + u32 reserved23[4]; + u32 gpio2_smt[3][4]; + u32 reserved24[(0xe130 - 0xe0ec)/4 - 1]; + u32 gpio4b_e01; + u32 gpio4b_e2; + u32 reserved24a[(0xe200 - 0xe134)/4 - 1]; + u32 soc_con0; + u32 soc_con1; + u32 soc_con2; + u32 soc_con3; + u32 soc_con4; + u32 soc_con5_pcie; + u32 reserved25; + u32 soc_con7; + u32 soc_con8; + u32 soc_con9_pcie; + u32 reserved26[0x1e]; + u32 soc_status[6]; + u32 reserved27[0x32]; + u32 ddrc0_con0; + u32 ddrc0_con1; + u32 ddrc1_con0; + u32 ddrc1_con1; + u32 reserved28[0xac]; + u32 io_vsel; + u32 saradc_testbit; + u32 tsadc_testbit_l; + u32 tsadc_testbit_h; + u32 reserved29[0x6c]; + u32 chip_id_addr; + u32 reserved30[0x1f]; + u32 fast_boot_addr; + u32 reserved31[0x1df]; + u32 emmccore_con[12]; + u32 reserved32[4]; + u32 emmccore_status[4]; + u32 reserved33[0x1cc]; + u32 emmcphy_con[7]; + u32 reserved34; + u32 emmcphy_status; +}; +check_member(rk3399_grf_regs, emmcphy_status, 0xf7a0); + +struct rk3399_pmugrf_regs { + union { + u32 iomux_pwm_3a; + u32 gpio0a_iomux; + }; + u32 gpio0b_iomux; + u32 reserved0[2]; + union { + u32 spi1_rxd; + u32 tsadc_int; + u32 gpio1a_iomux; + }; + union { + u32 spi1_csclktx; + u32 iomux_pwm_3b; + u32 iomux_i2c0_sda; + u32 gpio1b_iomux; + }; + union { + u32 iomux_pwm_2; + u32 iomux_i2c0_scl; + u32 gpio1c_iomux; + }; + u32 gpio1d_iomux; + u32 reserved1[8]; + u32 gpio0_p[2][4]; + u32 reserved3[8]; + u32 gpio0a_e; + u32 reserved4; + u32 gpio0b_e; + u32 reserved5[5]; + u32 gpio1a_e; + u32 reserved6; + u32 gpio1b_e; + u32 reserved7; + u32 gpio1c_e; + u32 reserved8; + u32 gpio1d_e; + u32 reserved9[0x11]; + u32 gpio0l_sr; + u32 reserved10; + u32 gpio1l_sr; + u32 gpio1h_sr; + u32 reserved11[4]; + u32 gpio0a_smt; + u32 gpio0b_smt; + u32 reserved12[2]; + u32 gpio1a_smt; + u32 gpio1b_smt; + u32 gpio1c_smt; + u32 gpio1d_smt; + u32 reserved13[8]; + u32 gpio0l_he; + u32 reserved14; + u32 gpio1l_he; + u32 gpio1h_he; + u32 reserved15[4]; + u32 soc_con0; + u32 reserved16[9]; + u32 soc_con10; + u32 soc_con11; + u32 reserved17[0x24]; + u32 pmupvtm_con0; + u32 pmupvtm_con1; + u32 pmupvtm_status0; + u32 pmupvtm_status1; + u32 grf_osc_e; + u32 reserved18[0x2b]; + u32 os_reg0; + u32 os_reg1; + u32 os_reg2; + u32 os_reg3; +}; +check_member(rk3399_pmugrf_regs, os_reg3, 0x30c); + +struct rk3399_pmusgrf_regs { + u32 ddr_rgn_con[35]; + u32 reserved[0x1fe5]; + u32 soc_con8; + u32 soc_con9; + u32 soc_con10; + u32 soc_con11; + u32 soc_con12; + u32 soc_con13; + u32 soc_con14; + u32 soc_con15; + u32 reserved1[3]; + u32 soc_con19; + u32 soc_con20; + u32 soc_con21; + u32 soc_con22; + u32 reserved2[0x29]; + u32 perilp_con[9]; + u32 reserved4[7]; + u32 perilp_status; + u32 reserved5[0xfaf]; + u32 soc_con0; + u32 soc_con1; + u32 reserved6[0x3e]; + u32 pmu_con[9]; + u32 reserved7[0x17]; + u32 fast_boot_addr; + u32 reserved8[0x1f]; + u32 efuse_prg_mask; + u32 efuse_read_mask; + u32 reserved9[0x0e]; + u32 pmu_slv_con0; + u32 pmu_slv_con1; + u32 reserved10[0x771]; + u32 soc_con3; + u32 soc_con4; + u32 soc_con5; + u32 soc_con6; + u32 soc_con7; + u32 reserved11[8]; + u32 soc_con16; + u32 soc_con17; + u32 soc_con18; + u32 reserved12[0xdd]; + u32 slv_secure_con0; + u32 slv_secure_con1; + u32 reserved13; + u32 slv_secure_con2; + u32 slv_secure_con3; + u32 slv_secure_con4; +}; +check_member(rk3399_pmusgrf_regs, slv_secure_con4, 0xe3d4); + +#endif /* __SOC_ROCKCHIP_RK3399_GRF_H__ */ diff --git a/arch/arm/include/asm/arch-rockchip/sdram.h b/arch/arm/include/asm/arch-rockchip/sdram.h index e08e28f4f0..82c3d07cbb 100644 --- a/arch/arm/include/asm/arch-rockchip/sdram.h +++ b/arch/arm/include/asm/arch-rockchip/sdram.h @@ -24,12 +24,16 @@ struct rk3288_sdram_channel { u8 row_3_4; u8 cs0_row; u8 cs1_row; +#if CONFIG_IS_ENABLED(OF_PLATDATA) /* * For of-platdata, which would otherwise convert this into two * byte-swapped integers. With a size of 9 bytes, this struct will * appear in of-platdata as a byte array. + * + * If OF_PLATDATA enabled, need to add a dummy byte in dts.(i.e 0xff) */ u8 dummy; +#endif }; struct rk3288_sdram_pctl_timing { diff --git a/arch/arm/include/asm/arch-rockchip/sys_proto.h b/arch/arm/include/asm/arch-rockchip/sys_proto.h new file mode 100644 index 0000000000..35423e1ba0 --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/sys_proto.h @@ -0,0 +1,10 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co.,Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_ARCH_SYS_PROTO_H +#define _ASM_ARCH_SYS_PROTO_H + +#endif /* _ASM_ARCH_SYS_PROTO_H */ diff --git a/arch/arm/mach-rockchip/board.c b/arch/arm/mach-rockchip/board.c index bec756d7ac..6c36bf9397 100644 --- a/arch/arm/mach-rockchip/board.c +++ b/arch/arm/mach-rockchip/board.c @@ -81,10 +81,6 @@ void enable_caches(void) } #endif -void lowlevel_init(void) -{ -} - #if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG) #include <usb.h> #include <usb/dwc2_udc.h> diff --git a/arch/arm/mach-rockchip/rk3288-board-spl.c b/arch/arm/mach-rockchip/rk3288-board-spl.c index e0d92a66b3..ae509ffab2 100644 --- a/arch/arm/mach-rockchip/rk3288-board-spl.c +++ b/arch/arm/mach-rockchip/rk3288-board-spl.c @@ -280,7 +280,3 @@ err: /* No way to report error here */ hang(); } - -void lowlevel_init(void) -{ -} diff --git a/arch/arm/mach-rockchip/rk3288/Makefile b/arch/arm/mach-rockchip/rk3288/Makefile index 5ec3f0d7e2..b5b28efbe8 100644 --- a/arch/arm/mach-rockchip/rk3288/Makefile +++ b/arch/arm/mach-rockchip/rk3288/Makefile @@ -5,5 +5,6 @@ # obj-y += clk_rk3288.o +obj-y += rk3288.o obj-y += sdram_rk3288.o obj-y += syscon_rk3288.o diff --git a/arch/arm/mach-rockchip/rk3288/rk3288.c b/arch/arm/mach-rockchip/rk3288/rk3288.c new file mode 100644 index 0000000000..92f34bbbcb --- /dev/null +++ b/arch/arm/mach-rockchip/rk3288/rk3288.c @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <asm/io.h> +#include <asm/arch/hardware.h> + +#define GRF_SOC_CON2 0x24c + +int arch_cpu_init(void) +{ + /* We do some SoC one time setting here. */ + + /* Use rkpwm by default */ + rk_setreg(GRF_SOC_CON2, 1 << 0); + + return 0; +} diff --git a/arch/arm/mach-rockchip/rk3399/syscon_rk3399.c b/arch/arm/mach-rockchip/rk3399/syscon_rk3399.c index 2d81c55cd2..2cef68bc4d 100644 --- a/arch/arm/mach-rockchip/rk3399/syscon_rk3399.c +++ b/arch/arm/mach-rockchip/rk3399/syscon_rk3399.c @@ -11,6 +11,7 @@ static const struct udevice_id rk3399_syscon_ids[] = { { .compatible = "rockchip,rk3399-grf", .data = ROCKCHIP_SYSCON_GRF }, + { .compatible = "rockchip,rk3399-pmugrf", .data = ROCKCHIP_SYSCON_PMUGRF }, }; U_BOOT_DRIVER(syscon_rk3399) = { diff --git a/board/rockchip/evb_rk3399/evb-rk3399.c b/board/rockchip/evb_rk3399/evb-rk3399.c index cb2d97dfb9..2580b389ac 100644 --- a/board/rockchip/evb_rk3399/evb-rk3399.c +++ b/board/rockchip/evb_rk3399/evb-rk3399.c @@ -4,12 +4,54 @@ * SPDX-License-Identifier: GPL-2.0+ */ #include <common.h> -#include <asm/armv8/mmu.h> +#include <dm.h> +#include <dm/pinctrl.h> +#include <asm/arch/periph.h> +#include <power/regulator.h> DECLARE_GLOBAL_DATA_PTR; int board_init(void) { + struct udevice *pinctrl, *regulator; + int ret; + + /* + * The PWM do not have decicated interrupt number in dts and can + * not get periph_id by pinctrl framework, so let's init them here. + * The PWM2 and PWM3 are for pwm regulater. + */ + ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); + if (ret) { + debug("%s: Cannot find pinctrl device\n", __func__); + goto out; + } + + ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_PWM2); + if (ret) { + debug("%s PWM2 pinctrl init fail!\n", __func__); + goto out; + } + + ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_PWM3); + if (ret) { + debug("%s PWM3 pinctrl init fail!\n", __func__); + goto out; + } + + ret = regulator_get_by_platname("vcc5v0_host", ®ulator); + if (ret) { + debug("%s vcc5v0_host init fail! ret %d\n", __func__, ret); + goto out; + } + + ret = regulator_set_enable(regulator, true); + if (ret) { + debug("%s vcc5v0-host-en set fail!\n", __func__); + goto out; + } + +out: return 0; } diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig index fbc23efb67..25e89394f9 100644 --- a/configs/evb-rk3399_defconfig +++ b/configs/evb-rk3399_defconfig @@ -14,12 +14,15 @@ CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_USB=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_CLK=y CONFIG_ROCKCHIP_DWMMC=y CONFIG_ROCKCHIP_SDHCI=y +CONFIG_ROCKCHIP_GPIO=y CONFIG_PINCTRL=y +CONFIG_ROCKCHIP_RK3399_PINCTRL=y CONFIG_RAM=y CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_BASE=0xFF1A0000 @@ -29,3 +32,11 @@ CONFIG_SYS_NS16550=y CONFIG_SYSRESET=y CONFIG_USE_TINY_PRINTF=y CONFIG_ERRNO_STR=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y diff --git a/drivers/clk/rockchip/clk_rk3288.c b/drivers/clk/rockchip/clk_rk3288.c index c07203d84b..bd71a96927 100644 --- a/drivers/clk/rockchip/clk_rk3288.c +++ b/drivers/clk/rockchip/clk_rk3288.c @@ -695,6 +695,8 @@ static ulong rk3288_clk_get_rate(struct clk *clk) case PCLK_I2C4: case PCLK_I2C5: return gclk_rate; + case PCLK_PWM: + return PD_BUS_PCLK_HZ; default: return -ENOENT; } diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index 0b4ea828f6..ea0ce2aab1 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -23,6 +23,10 @@ struct rk3399_clk_priv { ulong rate; }; +struct rk3399_pmuclk_priv { + struct rk3399_pmucru *pmucru; +}; + struct pll_div { u32 refdiv; u32 fbdiv; @@ -95,11 +99,11 @@ enum { /* PMUCRU_CLKSEL_CON2 */ I2C_DIV_CON_MASK = 0x7f, - I2C8_DIV_CON_SHIFT = 8, - I2C0_DIV_CON_SHIFT = 0, + CLK_I2C8_DIV_CON_SHIFT = 8, + CLK_I2C0_DIV_CON_SHIFT = 0, /* PMUCRU_CLKSEL_CON3 */ - I2C4_DIV_CON_SHIFT = 0, + CLK_I2C4_DIV_CON_SHIFT = 0, /* CLKSEL_CON0 */ ACLKM_CORE_L_DIV_CON_SHIFT = 8, @@ -507,6 +511,14 @@ void rk3399_configure_cpu(struct rk3399_cru *cru, (con >> CLK_I2C ##bus## _DIV_CON_SHIFT) & \ I2C_DIV_CON_MASK; +#define I2C_PMUCLK_REG_MASK(bus) \ + (I2C_DIV_CON_MASK << \ + CLK_I2C ##bus## _DIV_CON_SHIFT) + +#define I2C_PMUCLK_REG_VALUE(bus, clk_div) \ + ((clk_div - 1) << \ + CLK_I2C ##bus## _DIV_CON_SHIFT) + static ulong rk3399_i2c_get_clk(struct rk3399_cru *cru, ulong clk_id) { u32 div, con; @@ -754,7 +766,7 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate) break; case DCLK_VOP0: case DCLK_VOP1: - rate = rk3399_vop_set_clk(priv->cru, clk->id, rate); + ret = rk3399_vop_set_clk(priv->cru, clk->id, rate); break; default: return -ENOENT; @@ -830,3 +842,160 @@ U_BOOT_DRIVER(clk_rk3399) = { .bind = rk3399_clk_bind, .probe = rk3399_clk_probe, }; + +static ulong rk3399_i2c_get_pmuclk(struct rk3399_pmucru *pmucru, ulong clk_id) +{ + u32 div, con; + + switch (clk_id) { + case SCLK_I2C0_PMU: + con = readl(&pmucru->pmucru_clksel[2]); + div = I2C_CLK_DIV_VALUE(con, 0); + break; + case SCLK_I2C4_PMU: + con = readl(&pmucru->pmucru_clksel[3]); + div = I2C_CLK_DIV_VALUE(con, 4); + break; + case SCLK_I2C8_PMU: + con = readl(&pmucru->pmucru_clksel[2]); + div = I2C_CLK_DIV_VALUE(con, 8); + break; + default: + printf("do not support this i2c bus\n"); + return -EINVAL; + } + + return DIV_TO_RATE(PPLL_HZ, div); +} + +static ulong rk3399_i2c_set_pmuclk(struct rk3399_pmucru *pmucru, ulong clk_id, + uint hz) +{ + int src_clk_div; + + src_clk_div = PPLL_HZ / hz; + assert(src_clk_div - 1 < 127); + + switch (clk_id) { + case SCLK_I2C0_PMU: + rk_clrsetreg(&pmucru->pmucru_clksel[2], I2C_PMUCLK_REG_MASK(0), + I2C_PMUCLK_REG_VALUE(0, src_clk_div)); + break; + case SCLK_I2C4_PMU: + rk_clrsetreg(&pmucru->pmucru_clksel[3], I2C_PMUCLK_REG_MASK(4), + I2C_PMUCLK_REG_VALUE(4, src_clk_div)); + break; + case SCLK_I2C8_PMU: + rk_clrsetreg(&pmucru->pmucru_clksel[2], I2C_PMUCLK_REG_MASK(8), + I2C_PMUCLK_REG_VALUE(8, src_clk_div)); + break; + default: + printf("do not support this i2c bus\n"); + return -EINVAL; + } + + return DIV_TO_RATE(PPLL_HZ, src_clk_div); +} + +static ulong rk3399_pwm_get_clk(struct rk3399_pmucru *pmucru) +{ + u32 div, con; + + /* PWM closk rate is same as pclk_pmu */ + con = readl(&pmucru->pmucru_clksel[0]); + div = con & PMU_PCLK_DIV_CON_MASK; + + return DIV_TO_RATE(PPLL_HZ, div); +} + +static ulong rk3399_pmuclk_get_rate(struct clk *clk) +{ + struct rk3399_pmuclk_priv *priv = dev_get_priv(clk->dev); + ulong rate = 0; + + switch (clk->id) { + case PCLK_RKPWM_PMU: + rate = rk3399_pwm_get_clk(priv->pmucru); + break; + case SCLK_I2C0_PMU: + case SCLK_I2C4_PMU: + case SCLK_I2C8_PMU: + rate = rk3399_i2c_get_pmuclk(priv->pmucru, clk->id); + break; + default: + return -ENOENT; + } + + return rate; +} + +static ulong rk3399_pmuclk_set_rate(struct clk *clk, ulong rate) +{ + struct rk3399_pmuclk_priv *priv = dev_get_priv(clk->dev); + ulong ret = 0; + + switch (clk->id) { + case SCLK_I2C0_PMU: + case SCLK_I2C4_PMU: + case SCLK_I2C8_PMU: + ret = rk3399_i2c_set_pmuclk(priv->pmucru, clk->id, rate); + break; + default: + return -ENOENT; + } + + return ret; +} + +static struct clk_ops rk3399_pmuclk_ops = { + .get_rate = rk3399_pmuclk_get_rate, + .set_rate = rk3399_pmuclk_set_rate, +}; + +static void pmuclk_init(struct rk3399_pmucru *pmucru) +{ + u32 pclk_div; + + /* configure pmu pll(ppll) */ + rkclk_set_pll(&pmucru->ppll_con[0], &ppll_init_cfg); + + /* configure pmu pclk */ + pclk_div = PPLL_HZ / PMU_PCLK_HZ - 1; + assert((pclk_div + 1) * PMU_PCLK_HZ == PPLL_HZ && pclk_div < 0x1f); + rk_clrsetreg(&pmucru->pmucru_clksel[0], + PMU_PCLK_DIV_CON_MASK, + pclk_div << PMU_PCLK_DIV_CON_SHIFT); +} + +static int rk3399_pmuclk_probe(struct udevice *dev) +{ + struct rk3399_pmuclk_priv *priv = dev_get_priv(dev); + + pmuclk_init(priv->pmucru); + + return 0; +} + +static int rk3399_pmuclk_ofdata_to_platdata(struct udevice *dev) +{ + struct rk3399_pmuclk_priv *priv = dev_get_priv(dev); + + priv->pmucru = (struct rk3399_pmucru *)dev_get_addr(dev); + + return 0; +} + +static const struct udevice_id rk3399_pmuclk_ids[] = { + { .compatible = "rockchip,rk3399-pmucru" }, + { } +}; + +U_BOOT_DRIVER(pmuclk_rk3399) = { + .name = "pmuclk_rk3399", + .id = UCLASS_CLK, + .of_match = rk3399_pmuclk_ids, + .priv_auto_alloc_size = sizeof(struct rk3399_pmuclk_priv), + .ofdata_to_platdata = rk3399_pmuclk_ofdata_to_platdata, + .ops = &rk3399_pmuclk_ops, + .probe = rk3399_pmuclk_probe, +}; diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index f8cfd4bb24..12be3cfe0b 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -148,6 +148,15 @@ config PINCTRL_AT91PIO4 This option is to enable the AT91 pinctrl driver for AT91 PIO4 controller which is available on SAMA5D2 SoC. +config ROCKCHIP_RK3399_PINCTRL + bool "Rockchip pin control driver" + depends on DM + help + Support pin multiplexing control on Rockchip rk3399 SoCs. The driver + is controlled by a device tree node which contains both the GPIO + definitions and pin control functions for each available multiplex + function. + config PINCTRL_SANDBOX bool "Sandbox pinctrl driver" depends on SANDBOX diff --git a/drivers/pinctrl/rockchip/Makefile b/drivers/pinctrl/rockchip/Makefile index 64e9587cce..805c833ec9 100644 --- a/drivers/pinctrl/rockchip/Makefile +++ b/drivers/pinctrl/rockchip/Makefile @@ -7,3 +7,4 @@ obj-$(CONFIG_ROCKCHIP_RK3036_PINCTRL) += pinctrl_rk3036.o obj-$(CONFIG_ROCKCHIP_RK3288_PINCTRL) += pinctrl_rk3288.o +obj-$(CONFIG_ROCKCHIP_RK3399_PINCTRL) += pinctrl_rk3399.o diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3399.c b/drivers/pinctrl/rockchip/pinctrl_rk3399.c new file mode 100644 index 0000000000..17ea165eda --- /dev/null +++ b/drivers/pinctrl/rockchip/pinctrl_rk3399.c @@ -0,0 +1,439 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <syscon.h> +#include <asm/io.h> +#include <asm/arch/grf_rk3399.h> +#include <asm/arch/hardware.h> +#include <asm/arch/periph.h> +#include <asm/arch/clock.h> +#include <dm/pinctrl.h> + +DECLARE_GLOBAL_DATA_PTR; + +struct rk3399_pinctrl_priv { + struct rk3399_grf_regs *grf; + struct rk3399_pmugrf_regs *pmugrf; +}; + +enum { + /* GRF_GPIO2B_IOMUX */ + GRF_GPIO2B1_SEL_SHIFT = 0, + GRF_GPIO2B1_SEL_MASK = 3 << GRF_GPIO2B1_SEL_SHIFT, + GRF_SPI2TPM_RXD = 1, + GRF_GPIO2B2_SEL_SHIFT = 2, + GRF_GPIO2B2_SEL_MASK = 3 << GRF_GPIO2B2_SEL_SHIFT, + GRF_SPI2TPM_TXD = 1, + GRF_GPIO2B3_SEL_SHIFT = 6, + GRF_GPIO2B3_SEL_MASK = 3 << GRF_GPIO2B3_SEL_SHIFT, + GRF_SPI2TPM_CLK = 1, + GRF_GPIO2B4_SEL_SHIFT = 8, + GRF_GPIO2B4_SEL_MASK = 3 << GRF_GPIO2B4_SEL_SHIFT, + GRF_SPI2TPM_CSN0 = 1, + + /* GRF_GPIO3A_IOMUX */ + GRF_GPIO3A4_SEL_SHIFT = 8, + GRF_GPIO3A4_SEL_MASK = 3 << GRF_GPIO3A4_SEL_SHIFT, + GRF_SPI0NORCODEC_RXD = 2, + GRF_GPIO3A5_SEL_SHIFT = 10, + GRF_GPIO3A5_SEL_MASK = 3 << GRF_GPIO3A5_SEL_SHIFT, + GRF_SPI0NORCODEC_TXD = 2, + GRF_GPIO3A6_SEL_SHIFT = 12, + GRF_GPIO3A6_SEL_MASK = 3 << GRF_GPIO3A6_SEL_SHIFT, + GRF_SPI0NORCODEC_CLK = 2, + GRF_GPIO3A7_SEL_SHIFT = 14, + GRF_GPIO3A7_SEL_MASK = 3 << GRF_GPIO3A7_SEL_SHIFT, + GRF_SPI0NORCODEC_CSN0 = 2, + + /* GRF_GPIO3B_IOMUX */ + GRF_GPIO3B0_SEL_SHIFT = 0, + GRF_GPIO3B0_SEL_MASK = 3 << GRF_GPIO3B0_SEL_SHIFT, + GRF_SPI0NORCODEC_CSN1 = 2, + + /* GRF_GPIO4B_IOMUX */ + GRF_GPIO4B0_SEL_SHIFT = 0, + GRF_GPIO4B0_SEL_MASK = 3 << GRF_GPIO4B0_SEL_SHIFT, + GRF_SDMMC_DATA0 = 1, + GRF_UART2DBGA_SIN = 2, + GRF_GPIO4B1_SEL_SHIFT = 2, + GRF_GPIO4B1_SEL_MASK = 3 << GRF_GPIO4B1_SEL_SHIFT, + GRF_SDMMC_DATA1 = 1, + GRF_UART2DBGA_SOUT = 2, + GRF_GPIO4B2_SEL_SHIFT = 4, + GRF_GPIO4B2_SEL_MASK = 3 << GRF_GPIO4B2_SEL_SHIFT, + GRF_SDMMC_DATA2 = 1, + GRF_GPIO4B3_SEL_SHIFT = 6, + GRF_GPIO4B3_SEL_MASK = 3 << GRF_GPIO4B3_SEL_SHIFT, + GRF_SDMMC_DATA3 = 1, + GRF_GPIO4B4_SEL_SHIFT = 8, + GRF_GPIO4B4_SEL_MASK = 3 << GRF_GPIO4B4_SEL_SHIFT, + GRF_SDMMC_CLKOUT = 1, + GRF_GPIO4B5_SEL_SHIFT = 10, + GRF_GPIO4B5_SEL_MASK = 3 << GRF_GPIO4B5_SEL_SHIFT, + GRF_SDMMC_CMD = 1, + + /* GRF_GPIO4C_IOMUX */ + GRF_GPIO4C2_SEL_SHIFT = 4, + GRF_GPIO4C2_SEL_MASK = 3 << GRF_GPIO4C2_SEL_SHIFT, + GRF_PWM_0 = 1, + GRF_GPIO4C3_SEL_SHIFT = 6, + GRF_GPIO4C3_SEL_MASK = 3 << GRF_GPIO4C3_SEL_SHIFT, + GRF_UART2DGBC_SIN = 1, + GRF_GPIO4C4_SEL_SHIFT = 8, + GRF_GPIO4C4_SEL_MASK = 3 << GRF_GPIO4C4_SEL_SHIFT, + GRF_UART2DBGC_SOUT = 1, + GRF_GPIO4C6_SEL_SHIFT = 12, + GRF_GPIO4C6_SEL_MASK = 3 << GRF_GPIO4C6_SEL_SHIFT, + GRF_PWM_1 = 1, + + /* PMUGRF_GPIO0A_IOMUX */ + PMUGRF_GPIO0A6_SEL_SHIFT = 12, + PMUGRF_GPIO0A6_SEL_MASK = 3 << PMUGRF_GPIO0A6_SEL_SHIFT, + PMUGRF_PWM_3A = 1, + + /* PMUGRF_GPIO1A_IOMUX */ + PMUGRF_GPIO1A7_SEL_SHIFT = 14, + PMUGRF_GPIO1A7_SEL_MASK = 3 << PMUGRF_GPIO1A7_SEL_SHIFT, + PMUGRF_SPI1EC_RXD = 2, + + /* PMUGRF_GPIO1B_IOMUX */ + PMUGRF_GPIO1B0_SEL_SHIFT = 0, + PMUGRF_GPIO1B0_SEL_MASK = 3 << PMUGRF_GPIO1B0_SEL_SHIFT, + PMUGRF_SPI1EC_TXD = 2, + PMUGRF_GPIO1B1_SEL_SHIFT = 2, + PMUGRF_GPIO1B1_SEL_MASK = 3 << PMUGRF_GPIO1B1_SEL_SHIFT, + PMUGRF_SPI1EC_CLK = 2, + PMUGRF_GPIO1B2_SEL_SHIFT = 4, + PMUGRF_GPIO1B2_SEL_MASK = 3 << PMUGRF_GPIO1B2_SEL_SHIFT, + PMUGRF_SPI1EC_CSN0 = 2, + PMUGRF_GPIO1B6_SEL_SHIFT = 12, + PMUGRF_GPIO1B6_SEL_MASK = 3 << PMUGRF_GPIO1B6_SEL_SHIFT, + PMUGRF_PWM_3B = 1, + PMUGRF_GPIO1B7_SEL_SHIFT = 14, + PMUGRF_GPIO1B7_SEL_MASK = 3 << PMUGRF_GPIO1B7_SEL_SHIFT, + PMUGRF_I2C0PMU_SDA = 2, + + /* PMUGRF_GPIO1C_IOMUX */ + PMUGRF_GPIO1C0_SEL_SHIFT = 0, + PMUGRF_GPIO1C0_SEL_MASK = 3 << PMUGRF_GPIO1C0_SEL_SHIFT, + PMUGRF_I2C0PMU_SCL = 2, + PMUGRF_GPIO1C3_SEL_SHIFT = 6, + PMUGRF_GPIO1C3_SEL_MASK = 3 << PMUGRF_GPIO1C3_SEL_SHIFT, + PMUGRF_PWM_2 = 1, + +}; +static void pinctrl_rk3399_pwm_config(struct rk3399_grf_regs *grf, + struct rk3399_pmugrf_regs *pmugrf, int pwm_id) +{ + switch (pwm_id) { + case PERIPH_ID_PWM0: + rk_clrsetreg(&grf->gpio4c_iomux, + GRF_GPIO4C2_SEL_MASK, + GRF_PWM_0 << GRF_GPIO4C2_SEL_SHIFT); + break; + case PERIPH_ID_PWM1: + rk_clrsetreg(&grf->gpio4c_iomux, + GRF_GPIO4C6_SEL_MASK, + GRF_PWM_1 << GRF_GPIO4C6_SEL_SHIFT); + break; + case PERIPH_ID_PWM2: + rk_clrsetreg(&pmugrf->gpio1c_iomux, + PMUGRF_GPIO1C3_SEL_MASK, + PMUGRF_PWM_2 << PMUGRF_GPIO1C3_SEL_SHIFT); + break; + case PERIPH_ID_PWM3: + if (readl(&pmugrf->soc_con0) & (1 << 5)) + rk_clrsetreg(&pmugrf->gpio1b_iomux, + PMUGRF_GPIO1B6_SEL_MASK, + PMUGRF_PWM_3B << PMUGRF_GPIO1B6_SEL_SHIFT); + else + rk_clrsetreg(&pmugrf->gpio0a_iomux, + PMUGRF_GPIO0A6_SEL_MASK, + PMUGRF_PWM_3A << PMUGRF_GPIO0A6_SEL_SHIFT); + break; + default: + debug("pwm id = %d iomux error!\n", pwm_id); + break; + } +} + +static void pinctrl_rk3399_i2c_config(struct rk3399_grf_regs *grf, + struct rk3399_pmugrf_regs *pmugrf, + int i2c_id) +{ + switch (i2c_id) { + case PERIPH_ID_I2C0: + rk_clrsetreg(&pmugrf->gpio1b_iomux, + PMUGRF_GPIO1B7_SEL_MASK, + PMUGRF_I2C0PMU_SDA << PMUGRF_GPIO1B7_SEL_SHIFT); + rk_clrsetreg(&pmugrf->gpio1c_iomux, + PMUGRF_GPIO1C0_SEL_MASK, + PMUGRF_I2C0PMU_SCL << PMUGRF_GPIO1C0_SEL_SHIFT); + break; + case PERIPH_ID_I2C1: + case PERIPH_ID_I2C2: + case PERIPH_ID_I2C3: + case PERIPH_ID_I2C4: + case PERIPH_ID_I2C5: + default: + debug("i2c id = %d iomux error!\n", i2c_id); + break; + } +} + +static void pinctrl_rk3399_lcdc_config(struct rk3399_grf_regs *grf, int lcd_id) +{ + switch (lcd_id) { + case PERIPH_ID_LCDC0: + break; + default: + debug("lcdc id = %d iomux error!\n", lcd_id); + break; + } +} + +static int pinctrl_rk3399_spi_config(struct rk3399_grf_regs *grf, + struct rk3399_pmugrf_regs *pmugrf, + enum periph_id spi_id, int cs) +{ + switch (spi_id) { + case PERIPH_ID_SPI0: + switch (cs) { + case 0: + rk_clrsetreg(&grf->gpio3a_iomux, + GRF_GPIO3A7_SEL_MASK, + GRF_SPI0NORCODEC_CSN0 + << GRF_GPIO3A7_SEL_SHIFT); + break; + case 1: + rk_clrsetreg(&grf->gpio3b_iomux, + GRF_GPIO3B0_SEL_MASK, + GRF_SPI0NORCODEC_CSN1 + << GRF_GPIO3B0_SEL_SHIFT); + break; + default: + goto err; + } + rk_clrsetreg(&grf->gpio3a_iomux, + GRF_GPIO3A4_SEL_MASK | GRF_GPIO3A5_SEL_SHIFT + | GRF_GPIO3A6_SEL_SHIFT, + GRF_SPI0NORCODEC_RXD << GRF_GPIO3A4_SEL_SHIFT + | GRF_SPI0NORCODEC_RXD << GRF_GPIO3A5_SEL_SHIFT + | GRF_SPI0NORCODEC_RXD << GRF_GPIO3A6_SEL_SHIFT); + break; + case PERIPH_ID_SPI1: + if (cs != 0) + goto err; + rk_clrsetreg(&pmugrf->gpio1a_iomux, + PMUGRF_GPIO1A7_SEL_MASK, + PMUGRF_SPI1EC_RXD << PMUGRF_GPIO1A7_SEL_SHIFT); + rk_clrsetreg(&pmugrf->gpio1b_iomux, + PMUGRF_GPIO1B0_SEL_MASK | PMUGRF_GPIO1B1_SEL_MASK + | PMUGRF_GPIO1B2_SEL_MASK, + PMUGRF_SPI1EC_TXD << PMUGRF_GPIO1B0_SEL_SHIFT + | PMUGRF_SPI1EC_CLK << PMUGRF_GPIO1B1_SEL_SHIFT + | PMUGRF_SPI1EC_CSN0 << PMUGRF_GPIO1B2_SEL_SHIFT); + break; + case PERIPH_ID_SPI2: + if (cs != 0) + goto err; + rk_clrsetreg(&grf->gpio2b_iomux, + GRF_GPIO2B1_SEL_MASK | GRF_GPIO2B2_SEL_MASK + | GRF_GPIO2B3_SEL_MASK | GRF_GPIO2B4_SEL_MASK, + GRF_SPI2TPM_RXD << GRF_GPIO2B1_SEL_SHIFT + | GRF_SPI2TPM_TXD << GRF_GPIO2B2_SEL_SHIFT + | GRF_SPI2TPM_CLK << GRF_GPIO2B3_SEL_SHIFT + | GRF_SPI2TPM_CSN0 << GRF_GPIO2B4_SEL_SHIFT); + break; + default: + goto err; + } + + return 0; +err: + debug("rkspi: periph%d cs=%d not supported", spi_id, cs); + return -ENOENT; +} + +static void pinctrl_rk3399_uart_config(struct rk3399_grf_regs *grf, + struct rk3399_pmugrf_regs *pmugrf, + int uart_id) +{ + switch (uart_id) { + case PERIPH_ID_UART2: + /* Using channel-C by default */ + rk_clrsetreg(&grf->gpio4c_iomux, + GRF_GPIO4C3_SEL_MASK, + GRF_UART2DGBC_SIN << GRF_GPIO4C3_SEL_SHIFT); + rk_clrsetreg(&grf->gpio4c_iomux, + GRF_GPIO4C4_SEL_MASK, + GRF_UART2DBGC_SOUT << GRF_GPIO4C4_SEL_SHIFT); + break; + case PERIPH_ID_UART0: + case PERIPH_ID_UART1: + case PERIPH_ID_UART3: + case PERIPH_ID_UART4: + default: + debug("uart id = %d iomux error!\n", uart_id); + break; + } +} + +static void pinctrl_rk3399_sdmmc_config(struct rk3399_grf_regs *grf, int mmc_id) +{ + switch (mmc_id) { + case PERIPH_ID_EMMC: + break; + case PERIPH_ID_SDCARD: + rk_clrsetreg(&grf->gpio4b_iomux, + GRF_GPIO4B0_SEL_MASK | GRF_GPIO4B1_SEL_MASK + | GRF_GPIO4B2_SEL_MASK | GRF_GPIO4B3_SEL_MASK + | GRF_GPIO4B4_SEL_MASK | GRF_GPIO4B5_SEL_MASK, + GRF_SDMMC_DATA0 << GRF_GPIO4B0_SEL_SHIFT + | GRF_SDMMC_DATA1 << GRF_GPIO4B1_SEL_SHIFT + | GRF_SDMMC_DATA2 << GRF_GPIO4B2_SEL_SHIFT + | GRF_SDMMC_DATA3 << GRF_GPIO4B3_SEL_SHIFT + | GRF_SDMMC_CLKOUT << GRF_GPIO4B4_SEL_SHIFT + | GRF_SDMMC_CMD << GRF_GPIO4B5_SEL_SHIFT); + break; + default: + debug("mmc id = %d iomux error!\n", mmc_id); + break; + } +} + +static int rk3399_pinctrl_request(struct udevice *dev, int func, int flags) +{ + struct rk3399_pinctrl_priv *priv = dev_get_priv(dev); + + debug("%s: func=%x, flags=%x\n", __func__, func, flags); + switch (func) { + case PERIPH_ID_PWM0: + case PERIPH_ID_PWM1: + case PERIPH_ID_PWM2: + case PERIPH_ID_PWM3: + case PERIPH_ID_PWM4: + pinctrl_rk3399_pwm_config(priv->grf, priv->pmugrf, func); + break; + case PERIPH_ID_I2C0: + case PERIPH_ID_I2C1: + case PERIPH_ID_I2C2: + case PERIPH_ID_I2C3: + case PERIPH_ID_I2C4: + case PERIPH_ID_I2C5: + pinctrl_rk3399_i2c_config(priv->grf, priv->pmugrf, func); + break; + case PERIPH_ID_SPI0: + case PERIPH_ID_SPI1: + case PERIPH_ID_SPI2: + pinctrl_rk3399_spi_config(priv->grf, priv->pmugrf, func, flags); + break; + case PERIPH_ID_UART0: + case PERIPH_ID_UART1: + case PERIPH_ID_UART2: + case PERIPH_ID_UART3: + case PERIPH_ID_UART4: + pinctrl_rk3399_uart_config(priv->grf, priv->pmugrf, func); + break; + case PERIPH_ID_LCDC0: + case PERIPH_ID_LCDC1: + pinctrl_rk3399_lcdc_config(priv->grf, func); + break; + case PERIPH_ID_SDMMC0: + case PERIPH_ID_SDMMC1: + pinctrl_rk3399_sdmmc_config(priv->grf, func); + break; + default: + return -EINVAL; + } + + return 0; +} + +static int rk3399_pinctrl_get_periph_id(struct udevice *dev, + struct udevice *periph) +{ + u32 cell[3]; + int ret; + + ret = fdtdec_get_int_array(gd->fdt_blob, periph->of_offset, + "interrupts", cell, ARRAY_SIZE(cell)); + if (ret < 0) + return -EINVAL; + + switch (cell[1]) { + case 68: + return PERIPH_ID_SPI0; + case 53: + return PERIPH_ID_SPI1; + case 52: + return PERIPH_ID_SPI2; + case 57: + return PERIPH_ID_I2C0; + case 59: /* Note strange order */ + return PERIPH_ID_I2C1; + case 35: + return PERIPH_ID_I2C2; + case 34: + return PERIPH_ID_I2C3; + case 56: + return PERIPH_ID_I2C4; + case 38: + return PERIPH_ID_I2C5; + case 65: + return PERIPH_ID_SDMMC1; + } + + return -ENOENT; +} + +static int rk3399_pinctrl_set_state_simple(struct udevice *dev, + struct udevice *periph) +{ + int func; + + func = rk3399_pinctrl_get_periph_id(dev, periph); + if (func < 0) + return func; + + return rk3399_pinctrl_request(dev, func, 0); +} + +static struct pinctrl_ops rk3399_pinctrl_ops = { + .set_state_simple = rk3399_pinctrl_set_state_simple, + .request = rk3399_pinctrl_request, + .get_periph_id = rk3399_pinctrl_get_periph_id, +}; + +static int rk3399_pinctrl_probe(struct udevice *dev) +{ + struct rk3399_pinctrl_priv *priv = dev_get_priv(dev); + int ret = 0; + + priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF); + debug("%s: grf=%p, pmugrf=%p\n", __func__, priv->grf, priv->pmugrf); + + return ret; +} + +static const struct udevice_id rk3399_pinctrl_ids[] = { + { .compatible = "rockchip,rk3399-pinctrl" }, + { } +}; + +U_BOOT_DRIVER(pinctrl_rk3399) = { + .name = "rockchip_rk3399_pinctrl", + .id = UCLASS_PINCTRL, + .of_match = rk3399_pinctrl_ids, + .priv_auto_alloc_size = sizeof(struct rk3399_pinctrl_priv), + .ops = &rk3399_pinctrl_ops, + .bind = dm_scan_fdt_dev, + .probe = rk3399_pinctrl_probe, +}; diff --git a/drivers/pwm/rk_pwm.c b/drivers/pwm/rk_pwm.c index 2d289a4c07..9254f5bc39 100644 --- a/drivers/pwm/rk_pwm.c +++ b/drivers/pwm/rk_pwm.c @@ -6,15 +6,13 @@ */ #include <common.h> +#include <clk.h> #include <div64.h> #include <dm.h> #include <pwm.h> #include <regmap.h> #include <syscon.h> #include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/cru_rk3288.h> -#include <asm/arch/grf_rk3288.h> #include <asm/arch/pwm.h> #include <power/regulator.h> @@ -22,7 +20,7 @@ DECLARE_GLOBAL_DATA_PTR; struct rk_pwm_priv { struct rk3288_pwm *regs; - struct rk3288_grf *grf; + ulong freq; }; static int rk_pwm_set_config(struct udevice *dev, uint channel, uint period_ns, @@ -38,8 +36,8 @@ static int rk_pwm_set_config(struct udevice *dev, uint channel, uint period_ns, RK_PWM_DISABLE, ®s->ctrl); - period = lldiv((uint64_t)(PD_BUS_PCLK_HZ / 1000) * period_ns, 1000000); - duty = lldiv((uint64_t)(PD_BUS_PCLK_HZ / 1000) * duty_ns, 1000000); + period = lldiv((uint64_t)(priv->freq / 1000) * period_ns, 1000000); + duty = lldiv((uint64_t)(priv->freq / 1000) * duty_ns, 1000000); writel(period, ®s->period_hpr); writel(duty, ®s->duty_lpr); @@ -62,13 +60,8 @@ static int rk_pwm_set_enable(struct udevice *dev, uint channel, bool enable) static int rk_pwm_ofdata_to_platdata(struct udevice *dev) { struct rk_pwm_priv *priv = dev_get_priv(dev); - struct regmap *map; priv->regs = (struct rk3288_pwm *)dev_get_addr(dev); - map = syscon_get_regmap_by_driver_data(ROCKCHIP_SYSCON_GRF); - if (IS_ERR(map)) - return PTR_ERR(map); - priv->grf = regmap_get_range(map, 0); return 0; } @@ -76,8 +69,15 @@ static int rk_pwm_ofdata_to_platdata(struct udevice *dev) static int rk_pwm_probe(struct udevice *dev) { struct rk_pwm_priv *priv = dev_get_priv(dev); - - rk_setreg(&priv->grf->soc_con2, 1 << 0); + struct clk clk; + int ret = 0; + + ret = clk_get_by_index(dev, 0, &clk); + if (ret < 0) { + debug("%s get clock fail!\n", __func__); + return -EINVAL; + } + priv->freq = clk_get_rate(&clk); return 0; } diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 42e8a9f934..61e13d76e6 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -21,6 +21,13 @@ config USB_XHCI_DWC3 Say Y or if your system has a Dual Role SuperSpeed USB controller based on the DesignWare USB3 IP Core. +config USB_XHCI_ROCKCHIP + bool "Support for Rockchip on-chip xHCI USB controller" + depends on ARCH_ROCKCHIP + default y + help + Enables support for the on-chip xHCI controller on Rockchip SoCs. + endif # USB_XHCI_HCD config USB_EHCI_HCD diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index 55190bb667..de253284fb 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -56,6 +56,7 @@ obj-$(CONFIG_USB_EHCI_ZYNQ) += ehci-zynq.o # xhci obj-$(CONFIG_USB_XHCI_HCD) += xhci.o xhci-mem.o xhci-ring.o obj-$(CONFIG_USB_XHCI_DWC3) += xhci-dwc3.o +obj-$(CONFIG_USB_XHCI_ROCKCHIP) += xhci-rockchip.o obj-$(CONFIG_USB_XHCI_ZYNQMP) += xhci-zynqmp.o obj-$(CONFIG_USB_XHCI_KEYSTONE) += xhci-keystone.o obj-$(CONFIG_USB_XHCI_EXYNOS) += xhci-exynos5.o diff --git a/drivers/usb/host/xhci-rockchip.c b/drivers/usb/host/xhci-rockchip.c new file mode 100644 index 0000000000..561bf86702 --- /dev/null +++ b/drivers/usb/host/xhci-rockchip.c @@ -0,0 +1,211 @@ +/* + * Copyright (c) 2016 Rockchip, Inc. + * Authors: Daniel Meng <daniel.meng@rock-chips.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> +#include <dm.h> +#include <fdtdec.h> +#include <libfdt.h> +#include <malloc.h> +#include <usb.h> +#include <watchdog.h> +#include <asm/gpio.h> +#include <asm-generic/errno.h> +#include <linux/compat.h> +#include <linux/usb/dwc3.h> + +#include "xhci.h" + +DECLARE_GLOBAL_DATA_PTR; + +struct rockchip_xhci_platdata { + fdt_addr_t hcd_base; + fdt_addr_t phy_base; + struct gpio_desc vbus_gpio; +}; + +/* + * Contains pointers to register base addresses + * for the usb controller. + */ +struct rockchip_xhci { + struct usb_platdata usb_plat; + struct xhci_ctrl ctrl; + struct xhci_hccr *hcd; + struct dwc3 *dwc3_reg; +}; + +static int xhci_usb_ofdata_to_platdata(struct udevice *dev) +{ + struct rockchip_xhci_platdata *plat = dev_get_platdata(dev); + struct udevice *child; + int ret = 0; + + /* + * Get the base address for XHCI controller from the device node + */ + plat->hcd_base = dev_get_addr(dev); + if (plat->hcd_base == FDT_ADDR_T_NONE) { + debug("Can't get the XHCI register base address\n"); + return -ENXIO; + } + + /* Get the base address for usbphy from the device node */ + for (device_find_first_child(dev, &child); child; + device_find_next_child(&child)) { + if (!of_device_is_compatible(child, "rockchip,rk3399-usb3-phy")) + continue; + plat->phy_base = dev_get_addr(child); + break; + } + + if (plat->phy_base == FDT_ADDR_T_NONE) { + debug("Can't get the usbphy register address\n"); + return -ENXIO; + } + + /* Vbus gpio */ + ret = gpio_request_by_name(dev, "rockchip,vbus-gpio", 0, + &plat->vbus_gpio, GPIOD_IS_OUT); + if (ret) + debug("rockchip,vbus-gpio node missing!"); + + return 0; +} + +/* + * rockchip_dwc3_phy_setup() - Configure USB PHY Interface of DWC3 Core + * @dwc: Pointer to our controller context structure + * @dev: Pointer to ulcass device + */ +static void rockchip_dwc3_phy_setup(struct dwc3 *dwc3_reg, + struct udevice *dev) +{ + u32 reg; + const void *blob = gd->fdt_blob; + u32 utmi_bits; + + /* Set dwc3 usb2 phy config */ + reg = readl(&dwc3_reg->g_usb2phycfg[0]); + + if (fdtdec_get_bool(blob, dev->of_offset, + "snps,dis-enblslpm-quirk")) + reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; + + utmi_bits = fdtdec_get_int(blob, dev->of_offset, + "snps,phyif-utmi-bits", -1); + if (utmi_bits == 16) { + reg |= DWC3_GUSB2PHYCFG_PHYIF; + reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK; + reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_16BIT; + } else if (utmi_bits == 8) { + reg &= ~DWC3_GUSB2PHYCFG_PHYIF; + reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK; + reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_8BIT; + } + + if (fdtdec_get_bool(blob, dev->of_offset, + "snps,dis-u2-freeclk-exists-quirk")) + reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS; + + if (fdtdec_get_bool(blob, dev->of_offset, + "snps,dis-u2-susphy-quirk")) + reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; + + writel(reg, &dwc3_reg->g_usb2phycfg[0]); +} + +static int rockchip_xhci_core_init(struct rockchip_xhci *rkxhci, + struct udevice *dev) +{ + int ret; + + ret = dwc3_core_init(rkxhci->dwc3_reg); + if (ret) { + debug("failed to initialize core\n"); + return ret; + } + + rockchip_dwc3_phy_setup(rkxhci->dwc3_reg, dev); + + /* We are hard-coding DWC3 core to Host Mode */ + dwc3_set_mode(rkxhci->dwc3_reg, DWC3_GCTL_PRTCAP_HOST); + + return 0; +} + +static int rockchip_xhci_core_exit(struct rockchip_xhci *rkxhci) +{ + return 0; +} + +static int xhci_usb_probe(struct udevice *dev) +{ + struct rockchip_xhci_platdata *plat = dev_get_platdata(dev); + struct rockchip_xhci *ctx = dev_get_priv(dev); + struct xhci_hcor *hcor; + int ret; + + ctx->hcd = (struct xhci_hccr *)plat->hcd_base; + ctx->dwc3_reg = (struct dwc3 *)((char *)(ctx->hcd) + DWC3_REG_OFFSET); + hcor = (struct xhci_hcor *)((uint64_t)ctx->hcd + + HC_LENGTH(xhci_readl(&ctx->hcd->cr_capbase))); + + /* setup the Vbus gpio here */ + if (dm_gpio_is_valid(&plat->vbus_gpio)) + dm_gpio_set_value(&plat->vbus_gpio, 1); + + ret = rockchip_xhci_core_init(ctx, dev); + if (ret) { + debug("XHCI: failed to initialize controller\n"); + return ret; + } + + return xhci_register(dev, ctx->hcd, hcor); +} + +static int xhci_usb_remove(struct udevice *dev) +{ + struct rockchip_xhci *ctx = dev_get_priv(dev); + int ret; + + ret = xhci_deregister(dev); + if (ret) + return ret; + ret = rockchip_xhci_core_exit(ctx); + if (ret) + return ret; + + return 0; +} + +static const struct udevice_id xhci_usb_ids[] = { + { .compatible = "rockchip,rk3399-xhci" }, + { } +}; + +U_BOOT_DRIVER(usb_xhci) = { + .name = "xhci_rockchip", + .id = UCLASS_USB, + .of_match = xhci_usb_ids, + .ofdata_to_platdata = xhci_usb_ofdata_to_platdata, + .probe = xhci_usb_probe, + .remove = xhci_usb_remove, + .ops = &xhci_usb_ops, + .bind = dm_scan_fdt_dev, + .platdata_auto_alloc_size = sizeof(struct rockchip_xhci_platdata), + .priv_auto_alloc_size = sizeof(struct rockchip_xhci), + .flags = DM_FLAG_ALLOC_PRIV_DMA, +}; + +static const struct udevice_id usb_phy_ids[] = { + { .compatible = "rockchip,rk3399-usb3-phy" }, + { } +}; + +U_BOOT_DRIVER(usb_phy) = { + .name = "usb_phy_rockchip", + .of_match = usb_phy_ids, +}; diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h index 21b60828bb..e8bf9878f2 100644 --- a/include/configs/rk3288_common.h +++ b/include/configs/rk3288_common.h @@ -9,6 +9,7 @@ #include <asm/arch/hardware.h> +#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY #define CONFIG_SYS_NO_FLASH #define CONFIG_NR_DRAM_BANKS 1 #define CONFIG_ENV_SIZE 0x2000 diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h index e9626a5e39..b026122f52 100644 --- a/include/configs/rk3399_common.h +++ b/include/configs/rk3399_common.h @@ -83,4 +83,16 @@ #endif +/* enable usb config for usb ether */ +#define CONFIG_USB_HOST_ETHER + +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_USB_ETHER_ASIX88179 +#define CONFIG_USB_ETHER_MCS7830 +#define CONFIG_USB_ETHER_SMSC95XX +#define CONFIG_USB_ETHER_RTL8152 + +/* rockchip xhci host driver */ +#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 + #endif diff --git a/include/linux/usb/dwc3.h b/include/linux/usb/dwc3.h index 6d1e36505d..a0274461cc 100644 --- a/include/linux/usb/dwc3.h +++ b/include/linux/usb/dwc3.h @@ -180,7 +180,21 @@ struct dwc3 { /* offset: 0xC100 */ /* Global USB2 PHY Configuration Register */ #define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31) +#define DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS (1 << 30) +#define DWC3_GUSB2PHYCFG_ENBLSLPM (1 << 8) #define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6) +#define DWC3_GUSB2PHYCFG_PHYIF (1 << 3) + +/* Global USB2 PHY Configuration Mask */ +#define DWC3_GUSB2PHYCFG_USBTRDTIM_MASK (0xf << 10) + +/* Global USB2 PHY Configuration Offset */ +#define DWC3_GUSB2PHYCFG_USBTRDTIM_OFFSET 10 + +#define DWC3_GUSB2PHYCFG_USBTRDTIM_16BIT (0x5 << \ + DWC3_GUSB2PHYCFG_USBTRDTIM_OFFSET) +#define DWC3_GUSB2PHYCFG_USBTRDTIM_8BIT (0x9 << \ + DWC3_GUSB2PHYCFG_USBTRDTIM_OFFSET) /* Global USB3 PIPE Control Register */ #define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31) |