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authorLey Foon Tan <ley.foon.tan@intel.com>2019-11-27 15:55:14 +0800
committerMarek Vasut <marex@denx.de>2020-01-07 14:38:33 +0100
commit2145e611fc9906b8df41aff3c3f6f93aa400e2c0 (patch)
tree77f36bd31873eb91992053bec4e77961faa4ddb9
parent94172c7961124a4abf1aeedb1705a88a77744103 (diff)
arm: socfpga: agilex: Add base address for Intel Agilex SoC
Add base address for Intel Agilex SoC. Reuse base_addr_s10.h for Agilex, only one base address is different from S10. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
-rw-r--r--arch/arm/mach-socfpga/include/mach/base_addr_s10.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_s10.h b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
index 1f549d7e70..d3eca65e97 100644
--- a/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
+++ b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
@@ -10,7 +10,11 @@
#define SOCFPGA_SDR_SCHEDULER_ADDRESS 0xf8000400
#define SOCFPGA_HMC_MMR_IO48_ADDRESS 0xf8010000
#define SOCFPGA_SDR_ADDRESS 0xf8011000
+#ifdef CONFIG_TARGET_SOCFPGA_AGILEX
+#define SOCFPGA_FW_MPU_DDR_SCR_ADDRESS 0xf8020200
+#else
#define SOCFPGA_FW_MPU_DDR_SCR_ADDRESS 0xf8020100
+#endif
#define SOCFPGA_SMMU_ADDRESS 0xfa000000
#define SOCFPGA_MAILBOX_ADDRESS 0xffa30000
#define SOCFPGA_UART0_ADDRESS 0xffc02000