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authorLukas Auer <lukas.auer@aisec.fraunhofer.de>2018-11-22 11:26:25 +0100
committerAndes <uboot@andestech.com>2018-11-26 13:57:31 +0800
commit2a23ac610709bc18b2becebb45abc7596b4d1e9c (patch)
treea9ca7b04151fcbda9a104cc43e70604e3fe376df
parentc55309c091853531ffa21937e652b321c4b650bb (diff)
riscv: align mtvec on a 4-byte boundary
The machine trap-vector base address (mtvec) must be aligned on a 4-byte boundary. Add the necessary align directive to trap_entry. This patch also removes the global directive for trap_entry, which is not required. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
-rw-r--r--arch/riscv/cpu/start.S2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index bd5904500c..88b4aaa1c0 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -42,7 +42,6 @@ nmi_vector:
trap_vector:
j trap_entry
-.global trap_entry
handle_reset:
li t0, CONFIG_SYS_SDRAM_BASE
SREG a2, 0(t0)
@@ -208,6 +207,7 @@ call_board_init_r:
/*
* trap entry
*/
+.align 2
trap_entry:
addi sp, sp, -32*REGBYTES
SREG x1, 1*REGBYTES(sp)