diff options
| author | Simon South <simon@simonsouth.net> | 2019-10-10 15:28:36 -0400 |
|---|---|---|
| committer | Kever Yang <kever.yang@rock-chips.com> | 2019-11-10 20:40:20 +0800 |
| commit | 2cbdb6e051c4a59335101f5ef2084c838b9b5399 (patch) | |
| tree | afcded6c1241a02f210f906a48ea311e93c55a58 | |
| parent | a4bbc662fc7cea596e94ad8623202df7a2c50e27 (diff) | |
clk: rockchip: rk3328: Configure CPU clock
Add a call to rk3328_configure_cpu() during initialization to set the
CPU-clock frequency.
Signed-off-by: Simon South <simon@simonsouth.net>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| -rw-r--r-- | arch/arm/include/asm/arch-rockchip/cru_rk3328.h | 3 | ||||
| -rw-r--r-- | drivers/clk/rockchip/clk_rk3328.c | 2 |
2 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3328.h b/arch/arm/include/asm/arch-rockchip/cru_rk3328.h index 15b9788d9c..4bf69dbe08 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rk3328.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3328.h @@ -66,4 +66,7 @@ enum apll_frequencies { APLL_600_MHZ, }; +void rk3328_configure_cpu(struct rk3328_cru *cru, + enum apll_frequencies apll_freq); + #endif /* __ASM_ARCH_CRU_RK3328_H_ */ diff --git a/drivers/clk/rockchip/clk_rk3328.c b/drivers/clk/rockchip/clk_rk3328.c index a89e2ecc4a..4331048a87 100644 --- a/drivers/clk/rockchip/clk_rk3328.c +++ b/drivers/clk/rockchip/clk_rk3328.c @@ -282,6 +282,8 @@ static void rkclk_init(struct rk3328_cru *cru) u32 hclk_div; u32 pclk_div; + rk3328_configure_cpu(cru, APLL_600_MHZ); + /* configure gpll cpll */ rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg); rkclk_set_pll(cru, CLK_CODEC, &cpll_init_cfg); |