diff options
author | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2013-11-07 09:32:16 +0100 |
---|---|---|
committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2013-11-07 09:32:16 +0100 |
commit | 3285d4ca197928a048d3dda86751b5d26e6e0e86 (patch) | |
tree | c1ab908fb4fac09839c672c765b98a0512d1e9d1 | |
parent | c0e5dd88c438a41bf180dde0c2dc4c67dcd8058d (diff) | |
parent | c93addb5635630847e8a33f6dba4afef78a6d180 (diff) |
Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'
-rw-r--r-- | arch/arm/cpu/arm926ejs/mxs/Makefile | 11 | ||||
-rw-r--r-- | arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg | 4 | ||||
-rw-r--r-- | arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg | 4 | ||||
-rw-r--r-- | arch/arm/cpu/arm926ejs/mxs/spl_power_init.c | 2 | ||||
-rw-r--r-- | arch/arm/cpu/arm926ejs/mxs/start.S | 9 | ||||
-rw-r--r-- | arch/arm/cpu/armv7/mx5/lowlevel_init.S | 12 | ||||
-rw-r--r-- | arch/arm/cpu/armv7/mx6/clock.c | 56 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-mx6/crm_regs.h | 11 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-mx6/mx6dl_pins.h | 2 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-mxs/sys_proto.h | 2 | ||||
-rw-r--r-- | board/boundary/nitrogen6x/6x_upgrade.txt | 2 | ||||
-rw-r--r-- | board/ppcag/bg0900/Makefile | 31 | ||||
-rw-r--r-- | board/ppcag/bg0900/bg0900.c | 86 | ||||
-rw-r--r-- | board/ppcag/bg0900/spl_boot.c | 153 | ||||
-rw-r--r-- | board/udoo/Makefile | 26 | ||||
-rw-r--r-- | board/udoo/udoo.c | 110 | ||||
-rw-r--r-- | board/wandboard/README | 4 | ||||
-rw-r--r-- | boards.cfg | 2 | ||||
-rw-r--r-- | doc/README.mxs | 39 | ||||
-rw-r--r-- | drivers/watchdog/imx_watchdog.c | 3 | ||||
-rw-r--r-- | include/configs/bg0900.h | 97 | ||||
-rw-r--r-- | include/configs/udoo.h | 206 |
22 files changed, 819 insertions, 53 deletions
diff --git a/arch/arm/cpu/arm926ejs/mxs/Makefile b/arch/arm/cpu/arm926ejs/mxs/Makefile index 3d6689252b..ea397c7f2a 100644 --- a/arch/arm/cpu/arm926ejs/mxs/Makefile +++ b/arch/arm/cpu/arm926ejs/mxs/Makefile @@ -25,14 +25,15 @@ $(LIB): $(OBJS) $(call cmd_link_o_target, $(OBJS)) # Specify the target for use in elftosb call -ELFTOSB_TARGET-$(CONFIG_MX23) = imx23 -ELFTOSB_TARGET-$(CONFIG_MX28) = imx28 +MKIMAGE_TARGET-$(CONFIG_MX23) = mx23 +MKIMAGE_TARGET-$(CONFIG_MX28) = mx28 -$(OBJTREE)/u-boot.bd: $(SRCTREE)/$(CPUDIR)/$(SOC)/u-boot-$(ELFTOSB_TARGET-y).bd +$(OBJTREE)/mxsimage.cfg: $(SRCTREE)/$(CPUDIR)/$(SOC)/mxsimage.$(MKIMAGE_TARGET-y).cfg sed "s@OBJTREE@$(OBJTREE)@g" $^ > $@ -$(OBJTREE)/u-boot.sb: $(OBJTREE)/u-boot.bin $(OBJTREE)/spl/u-boot-spl.bin $(OBJTREE)/u-boot.bd - elftosb -zf $(ELFTOSB_TARGET-y) -c $(OBJTREE)/u-boot.bd -o $(OBJTREE)/u-boot.sb +$(OBJTREE)/u-boot.sb: $(OBJTREE)/u-boot.bin $(OBJTREE)/spl/u-boot-spl.bin $(OBJTREE)/mxsimage.cfg + $(OBJTREE)/tools/mkimage -n $(OBJTREE)/mxsimage.cfg -T mxsimage $@ + ######################################################################### diff --git a/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg b/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg index 811876736c..c9cf4b3629 100644 --- a/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg +++ b/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg @@ -1,6 +1,6 @@ SECTION 0x0 BOOTABLE TAG LAST - LOAD 0x0 spl/u-boot-spl.bin + LOAD 0x0 OBJTREE/spl/u-boot-spl.bin CALL 0x14 0x0 - LOAD 0x40000100 u-boot.bin + LOAD 0x40000100 OBJTREE/u-boot.bin CALL 0x40000100 0x0 diff --git a/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg b/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg index ea772f0c86..676f5c8f77 100644 --- a/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg +++ b/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg @@ -1,8 +1,8 @@ SECTION 0x0 BOOTABLE TAG LAST - LOAD 0x0 spl/u-boot-spl.bin + LOAD 0x0 OBJTREE/spl/u-boot-spl.bin LOAD IVT 0x8000 0x14 CALL HAB 0x8000 0x0 - LOAD 0x40000100 u-boot.bin + LOAD 0x40000100 OBJTREE/u-boot.bin LOAD IVT 0x8000 0x40000100 CALL HAB 0x8000 0x0 diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c index 8ea45be1d2..d25019a51e 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c @@ -654,6 +654,8 @@ static void mxs_batt_boot(void) clrsetbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK, 0x8 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET); + + mxs_power_enable_4p2(); } /** diff --git a/arch/arm/cpu/arm926ejs/mxs/start.S b/arch/arm/cpu/arm926ejs/mxs/start.S index 3e454ae1bc..5de2bad584 100644 --- a/arch/arm/cpu/arm926ejs/mxs/start.S +++ b/arch/arm/cpu/arm926ejs/mxs/start.S @@ -150,6 +150,15 @@ IRQ_STACK_START_IN: _reset: /* + * If the CPU is configured in "Wait JTAG connection mode", the stack + * pointer is not configured and is zero. This will cause crash when + * trying to push data onto stack right below here. Load the SP and make + * it point to the end of OCRAM if the SP is zero. + */ + cmp sp, #0x00000000 + ldreq sp, =CONFIG_SYS_INIT_SP_ADDR + + /* * Store all registers on old stack pointer, this will allow us later to * return to the BootROM and let the BootROM load U-Boot into RAM. * diff --git a/arch/arm/cpu/armv7/mx5/lowlevel_init.S b/arch/arm/cpu/armv7/mx5/lowlevel_init.S index 25fadf6487..f5bc6728b7 100644 --- a/arch/arm/cpu/armv7/mx5/lowlevel_init.S +++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S @@ -45,6 +45,12 @@ #endif mcr 15, 1, r0, c9, c0, 2 + + /* enable L2 cache */ + mrc 15, 0, r0, c1, c0, 1 + orr r0, r0, #2 + mcr 15, 0, r0, c1, c0, 1 + .endm /* init_l2cc */ /* AIPS setup - Only setup MPROTx registers. @@ -369,12 +375,6 @@ setup_pll_func: #endif /* CONFIG_MX53 */ .endm -.macro setup_wdog - ldr r0, =WDOG1_BASE_ADDR - mov r1, #0x30 - strh r1, [r0] -.endm - ENTRY(lowlevel_init) mov r10, lr mov r4, #0 /* Fix R4 to 0 */ diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index df11678609..3bf80e2b01 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -100,6 +100,32 @@ static u32 decode_pll(enum pll_clocks pll, u32 infreq) } /* NOTREACHED */ } +static u32 mxc_get_pll_pfd(enum pll_clocks pll, int pfd_num) +{ + u32 div; + u64 freq; + + switch (pll) { + case PLL_BUS: + if (pfd_num == 3) { + /* No PFD3 on PPL2 */ + return 0; + } + div = __raw_readl(&imx_ccm->analog_pfd_528); + freq = (u64)decode_pll(PLL_BUS, MXC_HCLK); + break; + case PLL_USBOTG: + div = __raw_readl(&imx_ccm->analog_pfd_480); + freq = (u64)decode_pll(PLL_USBOTG, MXC_HCLK); + break; + default: + /* No PFD on other PLL */ + return 0; + } + + return (freq * 18) / ((div & ANATOP_PFD_FRAC_MASK(pfd_num)) >> + ANATOP_PFD_FRAC_SHIFT(pfd_num)); +} static u32 get_mcu_main_clk(void) { @@ -144,13 +170,14 @@ u32 get_periph_clk(void) freq = decode_pll(PLL_BUS, MXC_HCLK); break; case 1: - freq = PLL2_PFD2_FREQ; + freq = mxc_get_pll_pfd(PLL_BUS, 2); break; case 2: - freq = PLL2_PFD0_FREQ; + freq = mxc_get_pll_pfd(PLL_BUS, 0); break; case 3: - freq = PLL2_PFD2_DIV_FREQ; + /* static / 2 divider */ + freq = mxc_get_pll_pfd(PLL_BUS, 2) / 2; break; default: break; @@ -184,7 +211,7 @@ static u32 get_ipg_per_clk(void) static u32 get_uart_clk(void) { u32 reg, uart_podf; - u32 freq = PLL3_80M; + u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */ reg = __raw_readl(&imx_ccm->cscdr1); #ifdef CONFIG_MX6SL if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL) @@ -204,7 +231,7 @@ static u32 get_cspi_clk(void) reg &= MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK; cspi_podf = reg >> MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET; - return PLL3_60M / (cspi_podf + 1); + return decode_pll(PLL_USBOTG, MXC_HCLK) / (8 * (cspi_podf + 1)); } static u32 get_axi_clk(void) @@ -217,9 +244,9 @@ static u32 get_axi_clk(void) if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) { if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL) - root_freq = PLL2_PFD2_FREQ; + root_freq = mxc_get_pll_pfd(PLL_BUS, 2); else - root_freq = PLL3_PFD1_FREQ; + root_freq = mxc_get_pll_pfd(PLL_USBOTG, 1); } else root_freq = get_periph_clk(); @@ -244,10 +271,10 @@ static u32 get_emi_slow_clk(void) root_freq = decode_pll(PLL_USBOTG, MXC_HCLK); break; case 2: - root_freq = PLL2_PFD2_FREQ; + root_freq = mxc_get_pll_pfd(PLL_BUS, 2); break; case 3: - root_freq = PLL2_PFD0_FREQ; + root_freq = mxc_get_pll_pfd(PLL_BUS, 0); break; } @@ -270,13 +297,14 @@ static u32 get_mmdc_ch0_clk(void) freq = decode_pll(PLL_BUS, MXC_HCLK); break; case 1: - freq = PLL2_PFD2_FREQ; + freq = mxc_get_pll_pfd(PLL_BUS, 2); break; case 2: - freq = PLL2_PFD0_FREQ; + freq = mxc_get_pll_pfd(PLL_BUS, 0); break; case 3: - freq = PLL2_PFD2_DIV_FREQ; + /* static / 2 divider */ + freq = mxc_get_pll_pfd(PLL_BUS, 2) / 2; } return freq / (podf + 1); @@ -359,9 +387,9 @@ static u32 get_usdhc_clk(u32 port) } if (clk_sel) - root_freq = PLL2_PFD0_FREQ; + root_freq = mxc_get_pll_pfd(PLL_BUS, 0); else - root_freq = PLL2_PFD2_FREQ; + root_freq = mxc_get_pll_pfd(PLL_BUS, 2); return root_freq / (usdhc_podf + 1); } diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h index 2813593e25..720207303b 100644 --- a/arch/arm/include/asm/arch-mx6/crm_regs.h +++ b/arch/arm/include/asm/arch-mx6/crm_regs.h @@ -890,15 +890,4 @@ struct mxc_ccm_reg { #define BF_ANADIG_PFD_528_PFD0_FRAC(v) \ (((v) << 0) & BM_ANADIG_PFD_528_PFD0_FRAC) -#define PLL2_PFD0_FREQ 352000000 -#define PLL2_PFD1_FREQ 594000000 -#define PLL2_PFD2_FREQ 396000000 -#define PLL2_PFD2_DIV_FREQ 200000000 -#define PLL3_PFD0_FREQ 720000000 -#define PLL3_PFD1_FREQ 540000000 -#define PLL3_PFD2_FREQ 508200000 -#define PLL3_PFD3_FREQ 454700000 -#define PLL3_80M 80000000 -#define PLL3_60M 60000000 - #endif /*__ARCH_ARM_MACH_MX6_CCM_REGS_H__ */ diff --git a/arch/arm/include/asm/arch-mx6/mx6dl_pins.h b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h index b5df68afc6..73734078e9 100644 --- a/arch/arm/include/asm/arch-mx6/mx6dl_pins.h +++ b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h @@ -210,7 +210,7 @@ enum { MX6_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3 = IOMUX_PAD(0x03BC, 0x00A8, 6, 0x0000, 0, 0), MX6_PAD_DI0_PIN3__PL301_SIM_MX6DL_PER1_HADDR_10 = IOMUX_PAD(0x03BC, 0x00A8, 7, 0x0000, 0, 0), MX6_PAD_DI0_PIN3__LCDIF_CS = IOMUX_PAD(0x03BC, 0x00A8, 8, 0x0000, 0, 0), - MX6_PAD_DI0_PIN4__IPU1_DI0_PIN4 = IOMUX_PAD(0x03C0, 0x00AC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DI0_PIN4__IPU1_DI0_PIN4 = IOMUX_PAD(0x03C0, 0x00AC, 0, 0x0000, 0, 0), MX6_PAD_DI0_PIN4__LCDIF_BUSY = IOMUX_PAD(0x03C0, 0x00AC, 1, 0x08D8, 1, 0), MX6_PAD_DI0_PIN4__AUDMUX_AUD6_RXD = IOMUX_PAD(0x03C0, 0x00AC, 2, 0x0000, 0, 0), MX6_PAD_DI0_PIN4__USDHC1_WP = IOMUX_PAD(0x03C0, 0x00AC, 3, 0x092C, 0, 0), diff --git a/arch/arm/include/asm/arch-mxs/sys_proto.h b/arch/arm/include/asm/arch-mxs/sys_proto.h index 43c7dd6bf1..09dfc90a9b 100644 --- a/arch/arm/include/asm/arch-mxs/sys_proto.h +++ b/arch/arm/include/asm/arch-mxs/sys_proto.h @@ -46,6 +46,7 @@ static const struct mxs_pair mxs_boot_modes[] = { { 0x02, 0x1f, "SSP SPI #1, master, NOR" }, { 0x03, 0x1f, "SSP SPI #2, master, NOR" }, { 0x04, 0x1f, "NAND" }, + { 0x06, 0x1f, "JTAG" }, { 0x08, 0x1f, "SSP SPI #3, master, EEPROM" }, { 0x09, 0x1f, "SSP SD/MMC #0" }, { 0x0a, 0x1f, "SSP SD/MMC #1" }, @@ -60,6 +61,7 @@ static const struct mxs_pair mxs_boot_modes[] = { { 0x13, 0x1f, "SSP SPI #3, master, 1V8 NOR" }, { 0x04, 0x1f, "NAND, 3V3" }, { 0x14, 0x1f, "NAND, 1V8" }, + { 0x06, 0x1f, "JTAG" }, { 0x08, 0x1f, "SSP SPI #3, master, 3V3 EEPROM" }, { 0x18, 0x1f, "SSP SPI #3, master, 1V8 EEPROM" }, { 0x09, 0x1f, "SSP SD/MMC #0, 3V3" }, diff --git a/board/boundary/nitrogen6x/6x_upgrade.txt b/board/boundary/nitrogen6x/6x_upgrade.txt index 1f9a889554..1a62bbf12e 100644 --- a/board/boundary/nitrogen6x/6x_upgrade.txt +++ b/board/boundary/nitrogen6x/6x_upgrade.txt @@ -17,7 +17,7 @@ if ${fs}load ${dtype} ${disk}:1 12000000 u-boot.imx || ${fs}load ${dtype} ${disk sleep 1 ; done echo "erasing" ; - sf erase 0 0x50000 ; + sf erase 0 0xC0000 ; # two steps to prevent bricking echo "programming" ; sf write 0x12000000 $offset $filesize ; diff --git a/board/ppcag/bg0900/Makefile b/board/ppcag/bg0900/Makefile new file mode 100644 index 0000000000..e17c0a5991 --- /dev/null +++ b/board/ppcag/bg0900/Makefile @@ -0,0 +1,31 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +ifndef CONFIG_SPL_BUILD +COBJS := bg0900.o +else +COBJS := spl_boot.o +endif + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/ppcag/bg0900/bg0900.c b/board/ppcag/bg0900/bg0900.c new file mode 100644 index 0000000000..06612fa34d --- /dev/null +++ b/board/ppcag/bg0900/bg0900.c @@ -0,0 +1,86 @@ +/* + * PPC-AG BG0900 board + * + * Copyright (C) 2013 Marek Vasut <marex@denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/gpio.h> +#include <asm/io.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/iomux-mx28.h> +#include <asm/arch/clock.h> +#include <asm/arch/sys_proto.h> +#include <linux/mii.h> +#include <miiphy.h> +#include <netdev.h> +#include <errno.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Functions + */ +int board_early_init_f(void) +{ + /* IO0 clock at 480MHz */ + mxs_set_ioclk(MXC_IOCLK0, 480000); + /* IO1 clock at 480MHz */ + mxs_set_ioclk(MXC_IOCLK1, 480000); + + /* SSP2 clock at 160MHz */ + mxs_set_sspclk(MXC_SSPCLK2, 160000, 0); + + return 0; +} + +int dram_init(void) +{ + return mxs_dram_init(); +} + +int board_init(void) +{ + /* Adress of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + + return 0; +} + +#ifdef CONFIG_CMD_NET +int board_eth_init(bd_t *bis) +{ + struct mxs_clkctrl_regs *clkctrl_regs = + (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; + struct eth_device *dev; + int ret; + + ret = cpu_eth_init(bis); + + /* BG0900 uses ENET_CLK PAD to drive FEC clock */ + writel(CLKCTRL_ENET_TIME_SEL_RMII_CLK | CLKCTRL_ENET_CLK_OUT_EN, + &clkctrl_regs->hw_clkctrl_enet); + + /* Reset FEC PHYs */ + gpio_direction_output(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 0); + udelay(200); + gpio_set_value(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 1); + + ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE); + if (ret) { + puts("FEC MXS: Unable to init FEC0\n"); + return ret; + } + + dev = eth_get_dev_by_name("FEC0"); + if (!dev) { + puts("FEC MXS: Unable to get FEC0 device entry\n"); + return -EINVAL; + } + + return ret; +} + +#endif diff --git a/board/ppcag/bg0900/spl_boot.c b/board/ppcag/bg0900/spl_boot.c new file mode 100644 index 0000000000..a04c9553e4 --- /dev/null +++ b/board/ppcag/bg0900/spl_boot.c @@ -0,0 +1,153 @@ +/* + * PPC-AG BG0900 Boot setup + * + * Copyright (C) 2013 Marek Vasut <marex@denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <config.h> +#include <asm/io.h> +#include <asm/arch/iomux-mx28.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/sys_proto.h> + +#define MUX_CONFIG_GPMI (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL) +#define MUX_CONFIG_ENET (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP) +#define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL) +#define MUX_CONFIG_SSP2 (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP) + +const iomux_cfg_t iomux_setup[] = { + /* DUART */ + MX28_PAD_PWM0__DUART_RX, + MX28_PAD_PWM1__DUART_TX, + + /* GPMI NAND */ + MX28_PAD_GPMI_D00__GPMI_D0 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_D01__GPMI_D1 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_D02__GPMI_D2 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_D03__GPMI_D3 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_D04__GPMI_D4 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_D05__GPMI_D5 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_D06__GPMI_D6 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_D07__GPMI_D7 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_CE0N__GPMI_CE0N | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_RDY0__GPMI_READY0 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_RDN__GPMI_RDN | + (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP), + MX28_PAD_GPMI_WRN__GPMI_WRN | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_ALE__GPMI_ALE | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_CLE__GPMI_CLE | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_RESETN__GPMI_RESETN | MUX_CONFIG_GPMI, + + /* FEC0 */ + MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET, + MX28_PAD_ENET0_MDIO__ENET0_MDIO | MUX_CONFIG_ENET, + MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MUX_CONFIG_ENET, + MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MUX_CONFIG_ENET, + MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MUX_CONFIG_ENET, + MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MUX_CONFIG_ENET, + MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MUX_CONFIG_ENET, + MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MUX_CONFIG_ENET, + MX28_PAD_ENET_CLK__CLKCTRL_ENET | MUX_CONFIG_ENET, + + /* FEC0 Reset */ + MX28_PAD_ENET0_RX_CLK__GPIO_4_13 | + (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + + /* EMI */ + MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI, + MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_ODT1__EMI_ODT1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI, + MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI, + MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI, + + MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI, + MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI, + MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI, + MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI, + MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI, + MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI, + MX28_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI, + MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI, + + /* SPI2 (for SPI flash) */ + MX28_PAD_SSP2_SCK__SSP2_SCK | MUX_CONFIG_SSP2, + MX28_PAD_SSP2_MOSI__SSP2_CMD | MUX_CONFIG_SSP2, + MX28_PAD_SSP2_MISO__SSP2_D0 | MUX_CONFIG_SSP2, + MX28_PAD_SSP2_SS0__SSP2_D3 | + (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP), +}; + +void mxs_adjust_memory_params(uint32_t *dram_vals) +{ + /* + * DDR Controller Registers + * Manufacturer: Winbond + * Device Part Number: W972GG6JB-25I + * Clock Freq.: 200MHz + * Density: 2Gb + * Chip Selects: 1 + * Number of Banks: 8 + * Row address: 14 + * Column address: 10 + */ + + dram_vals[0x74 / 4] = 0x0102010A; + dram_vals[0x98 / 4] = 0x04005003; + dram_vals[0x9c / 4] = 0x090000c8; + + dram_vals[0xa8 / 4] = 0x0036b009; + dram_vals[0xac / 4] = 0x03270612; + + dram_vals[0xb0 / 4] = 0x02020202; + dram_vals[0xb4 / 4] = 0x00c80029; + + dram_vals[0xc0 / 4] = 0x00011900; + + dram_vals[0x12c / 4] = 0x07400300; + dram_vals[0x130 / 4] = 0x07400300; + dram_vals[0x2c4 / 4] = 0x02030303; +} + +void board_init_ll(const uint32_t arg, const uint32_t *resptr) +{ + mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup)); +} diff --git a/board/udoo/Makefile b/board/udoo/Makefile new file mode 100644 index 0000000000..1f0f6c760f --- /dev/null +++ b/board/udoo/Makefile @@ -0,0 +1,26 @@ +# +# (C) Copyright 2013 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := udoo.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/udoo/udoo.c b/board/udoo/udoo.c new file mode 100644 index 0000000000..e9d63750a8 --- /dev/null +++ b/board/udoo/udoo.c @@ -0,0 +1,110 @@ +/* + * Copyright (C) 2013 Freescale Semiconductor, Inc. + * + * Author: Fabio Estevam <fabio.estevam@freescale.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/arch/clock.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/iomux.h> +#include <asm/arch/mx6-pins.h> +#include <asm/errno.h> +#include <asm/gpio.h> +#include <asm/imx-common/iomux-v3.h> +#include <mmc.h> +#include <fsl_esdhc.h> +#include <asm/arch/crm_regs.h> +#include <asm/io.h> +#include <asm/arch/sys_proto.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ + PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define WDT_EN IMX_GPIO_NR(5, 4) +#define WDT_TRG IMX_GPIO_NR(3, 19) + +int dram_init(void) +{ + gd->ram_size = (phys_size_t)CONFIG_DDR_MB * 1024 * 1024; + + return 0; +} + +static iomux_v3_cfg_t const uart2_pads[] = { + MX6_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc3_pads[] = { + MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +static iomux_v3_cfg_t const wdog_pads[] = { + MX6_PAD_EIM_A24__GPIO_5_4 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_EIM_D19__GPIO_3_19, +}; + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); +} + +static void setup_iomux_wdog(void) +{ + imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); + gpio_direction_output(WDT_TRG, 0); + gpio_direction_output(WDT_EN, 1); +} + +static struct fsl_esdhc_cfg usdhc_cfg = { USDHC3_BASE_ADDR }; + +int board_mmc_getcd(struct mmc *mmc) +{ + return 1; /* Always present */ +} + +int board_mmc_init(bd_t *bis) +{ + imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); + usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + usdhc_cfg.max_bus_width = 4; + + return fsl_esdhc_initialize(bis, &usdhc_cfg); +} + +int board_early_init_f(void) +{ + setup_iomux_wdog(); + setup_iomux_uart(); + + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + return 0; +} + +int checkboard(void) +{ + puts("Board: Udoo\n"); + + return 0; +} diff --git a/board/wandboard/README b/board/wandboard/README index 498db2fd47..1f678e16a9 100644 --- a/board/wandboard/README +++ b/board/wandboard/README @@ -3,8 +3,8 @@ U-Boot for Wandboard This file contains information for the port of U-Boot to the Wandboard. -Wandboard is a development board that has two variants: one version based -on mx6 dual lite and another one based on mx6 solo. +Wandboard is a development board that has three variants based on the following +SoCs: mx6 quad, mx6 dual lite and mx6 solo. For more details about Wandboard, please refer to: http://www.wandboard.org/ diff --git a/boards.cfg b/boards.cfg index 3a56eab28e..97c3b43c27 100644 --- a/boards.cfg +++ b/boards.cfg @@ -207,6 +207,7 @@ Active arm arm926ejs mxs freescale mx28evk Active arm arm926ejs mxs freescale mx28evk mx28evk_auart_console mx28evk:MXS_AUART,MXS_AUART_BASE=MXS_UARTAPP3_BASE,ENV_IS_IN_MMC Fabio Estevam <fabio.estevam@freescale.com> Active arm arm926ejs mxs freescale mx28evk mx28evk_nand mx28evk:ENV_IS_IN_NAND Fabio Estevam <fabio.estevam@freescale.com> Active arm arm926ejs mxs olimex mx23_olinuxino mx23_olinuxino mx23_olinuxino Marek Vasut <marek.vasut@gmail.com> +Active arm arm926ejs mxs ppcag bg0900 bg0900 bg0900 Marek Vasut <marex@denx.de> Active arm arm926ejs mxs sandisk sansa_fuze_plus sansa_fuze_plus - Marek Vasut <marek.vasut@gmail.com> Active arm arm926ejs mxs schulercontrol sc_sps_1 sc_sps_1 - Marek Vasut <marek.vasut@gmail.com> Active arm arm926ejs nomadik st nhk8815 nhk8815 - Nomadik Linux Team <STN_WMM_nomadik_linux@list.st.com>:Alessandro Rubini <rubini@unipv.it> @@ -287,6 +288,7 @@ Active arm armv7 mx5 freescale mx53smd Active arm armv7 mx5 genesi mx51_efikamx mx51_efikamx mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKAMX,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_mx.cfg - Active arm armv7 mx5 genesi mx51_efikamx mx51_efikasb mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKASB,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_sb.cfg - Active arm armv7 mx5 ttcontrol vision2 vision2 vision2:IMX_CONFIG=board/ttcontrol/vision2/imximage_hynix.cfg Stefano Babic <sbabic@denx.de> +Active arm armv7 mx6 - udoo udoo_quad udoo:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024 Fabio Estevam <fabio.estevam@freescale.com> Active arm armv7 mx6 - wandboard wandboard_dl wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024 Fabio Estevam <fabio.estevam@freescale.com> Active arm armv7 mx6 - wandboard wandboard_quad wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q,DDR_MB=2048 Fabio Estevam <fabio.estevam@freescale.com> Active arm armv7 mx6 - wandboard wandboard_solo wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,MX6S,DDR_MB=512 Fabio Estevam <fabio.estevam@freescale.com> diff --git a/doc/README.mxs b/doc/README.mxs index 2919bbfee1..0235a5aeaf 100644 --- a/doc/README.mxs +++ b/doc/README.mxs @@ -27,9 +27,25 @@ Contents 1) Prerequisites ---------------- -To make a MXS based board bootable, some tools are necessary. The first one is -the "elftosb" tool distributed by Freescale Semiconductor. The other one is the -"mxsboot" tool found in U-Boot source tree. +To make a MXS based board bootable, some tools are necessary. The only +mandatory tool is the "mxsboot" tool found in U-Boot source tree. The +tool is built automatically when compiling U-Boot for i.MX23 or i.MX28. + +The production of BootStream image is handled via "mkimage", which is +also part of the U-Boot source tree. The "mkimage" requires OpenSSL +development libraries to be installed. In case of Debian and derivates, +this is installed by running: + + $ sudo apt-get install libssl-dev + +NOTE: The "elftosb" tool distributed by Freescale Semiconductor is no + longer necessary for general use of U-Boot on i.MX23 and i.MX28. + The mkimage supports generation of BootStream images encrypted + with a zero key, which is the vast majority of use-cases. In + case you do need to produce image encrypted with non-zero key + or other special features, please use the "elftosb" tool, + otherwise continue to section 2). The installation procedure of + the "elftosb" is outlined below: Firstly, obtain the elftosb archive from the following location: @@ -63,11 +79,6 @@ copy the binary by hand: Make sure the "elftosb" binary can be found in your $PATH, in this case this means "/usr/local/bin/" has to be in your $PATH. -Install the 'libssl-dev' package as well. On a Debian-based distribution, this -package can be installed as follows: - - $ sudo apt-get install libssl-dev - 2) Compiling U-Boot for a MXS based board ------------------------------------------- @@ -112,6 +123,18 @@ The code produces "u-boot.sb" file. This file needs to be augmented with a proper header to allow successful boot from SD or NAND. Adding the header is discussed in the following chapters. +NOTE: The process that produces u-boot.sb uses the mkimage to generate the + BootStream. The BootStream is encrypted with zero key. In case you need + some special features of the BootStream and plan on using the "elftosb" + tool instead, the invocation to produce a compatible BootStream with the + one produced by mkimage is outlined below. For further details, refer to + the documentation bundled with the "elftosb" package. + + $ elftosb -zf imx23 -c arch/arm/cpu/arm926ejs/mxs/u-boot-imx23.bd \ + -o u-boot.sb + $ elftosb -zf imx28 -c arch/arm/cpu/arm926ejs/mxs/u-boot-imx28.bd \ + -o u-boot.sb + 3) Installation of U-Boot for a MXS based board to SD card ---------------------------------------------------------- diff --git a/drivers/watchdog/imx_watchdog.c b/drivers/watchdog/imx_watchdog.c index 50e602af12..d5993b4d26 100644 --- a/drivers/watchdog/imx_watchdog.c +++ b/drivers/watchdog/imx_watchdog.c @@ -19,6 +19,7 @@ struct watchdog_regs { #define WCR_WDBG 0x02 #define WCR_WDE 0x04 /* WDOG enable */ #define WCR_WDT 0x08 +#define WCR_SRS 0x10 #define WCR_WDW 0x80 #define SET_WCR_WT(x) (x << 8) @@ -45,7 +46,7 @@ void hw_watchdog_init(void) #define CONFIG_WATCHDOG_TIMEOUT_MSECS 128000 #endif timeout = (CONFIG_WATCHDOG_TIMEOUT_MSECS / 500) - 1; - writew(WCR_WDZST | WCR_WDBG | WCR_WDE | WCR_WDT | + writew(WCR_WDZST | WCR_WDBG | WCR_WDE | WCR_WDT | WCR_SRS | WCR_WDW | SET_WCR_WT(timeout), &wdog->wcr); hw_watchdog_reset(); } diff --git a/include/configs/bg0900.h b/include/configs/bg0900.h new file mode 100644 index 0000000000..507d972f34 --- /dev/null +++ b/include/configs/bg0900.h @@ -0,0 +1,97 @@ +/* + * Copyright (C) 2013 Marek Vasut <marex@denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __CONFIGS_BG0900_H__ +#define __CONFIGS_BG0900_H__ + +/* System configurations */ +#define CONFIG_MX28 /* i.MX28 SoC */ + +/* U-Boot Commands */ +#define CONFIG_SYS_NO_FLASH +#include <config_cmd_default.h> +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DOS_PARTITION + +#define CONFIG_CMD_BOOTZ +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_GPIO +#define CONFIG_CMD_MII +#define CONFIG_CMD_NAND +#define CONFIG_CMD_NAND_TRIMFFS +#define CONFIG_CMD_NET +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PING +#define CONFIG_CMD_SAVEENV +#define CONFIG_CMD_SETEXPR +#define CONFIG_CMD_SF +#define CONFIG_CMD_SPI + +/* Memory configuration */ +#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */ +#define PHYS_SDRAM_1 0x40000000 /* Base address */ +#define PHYS_SDRAM_1_SIZE 0x10000000 /* Max 256 MB RAM */ +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 + +/* Environment */ +#define CONFIG_ENV_SIZE (16 * 1024) +#define CONFIG_ENV_OVERWRITE +#define CONFIG_ENV_IS_NOWHERE + +/* FEC Ethernet on SoC */ +#ifdef CONFIG_CMD_NET +#define CONFIG_FEC_MXC +#define CONFIG_NET_MULTI +#endif + +/* SPI */ +#ifdef CONFIG_CMD_SPI +#define CONFIG_DEFAULT_SPI_BUS 2 +#define CONFIG_DEFAULT_SPI_CS 0 +#define CONFIG_DEFAULT_SPI_MODE SPI_MODE_0 + +/* SPI FLASH */ +#ifdef CONFIG_CMD_SF +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_BAR +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_SF_DEFAULT_BUS 2 +#define CONFIG_SF_DEFAULT_CS 0 +#define CONFIG_SF_DEFAULT_SPEED 40000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 + +#define CONFIG_ENV_SPI_BUS 2 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_MAX_HZ 40000000 +#define CONFIG_ENV_SPI_MODE SPI_MODE_0 +#endif + +#endif + +/* Boot Linux */ +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_BOOTARGS "console=ttyAMA0,115200" +#define CONFIG_BOOTCOMMAND "bootm" +#define CONFIG_LOADADDR 0x42000000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +/* Extra Environment */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "update_spi_firmware_filename=u-boot.sb\0" \ + "update_spi_firmware_maxsz=0x80000\0" \ + "update_spi_firmware=" /* Update the SPI flash firmware */ \ + "if sf probe 2:0 ; then " \ + "if tftp ${update_spi_firmware_filename} ; then " \ + "sf erase 0x0 +${filesize} ; " \ + "sf write ${loadaddr} 0x0 ${filesize} ; " \ + "fi ; " \ + "fi\0" + +/* The rest of the configuration is shared */ +#include <configs/mxs.h> + +#endif /* __CONFIGS_BG0900_H__ */ diff --git a/include/configs/udoo.h b/include/configs/udoo.h new file mode 100644 index 0000000000..78df071795 --- /dev/null +++ b/include/configs/udoo.h @@ -0,0 +1,206 @@ +/* + * Copyright (C) 2013 Freescale Semiconductor, Inc. + * + * Configuration settings for Udoo board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <asm/arch/imx-regs.h> +#include <asm/imx-common/gpio.h> +#include <asm/sizes.h> + +#define CONFIG_MX6 +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +#define MACH_TYPE_UDOO 4800 +#define CONFIG_MACH_TYPE MACH_TYPE_UDOO + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (2 * SZ_1M) + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_MXC_GPIO + +#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART2_BASE + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 + +/* Command definition */ +#include <config_cmd_default.h> + +#undef CONFIG_CMD_IMLS + +#define CONFIG_CMD_BMODE +#define CONFIG_CMD_SETEXPR + +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_SYS_MEMTEST_START 0x10000000 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 500 * SZ_1M) +#define CONFIG_LOADADDR 0x12000000 +#define CONFIG_SYS_TEXT_BASE 0x17800000 + +/* MMC Configuration */ +#define CONFIG_FSL_ESDHC +#define CONFIG_FSL_USDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 + +#define CONFIG_MMC +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_BOUNCE_BUFFER +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION + +#define CONFIG_DEFAULT_FDT_FILE "imx6q-udoo.dtb" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "script=boot.scr\0" \ + "uimage=uImage\0" \ + "console=ttymxc1\0" \ + "splashpos=m,m\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "fdt_addr=0x11000000\0" \ + "boot_fdt=try\0" \ + "ip_dyn=yes\0" \ + "mmcdev=0\0" \ + "mmcpart=1\0" \ + "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \ + "update_sd_firmware_filename=u-boot.imx\0" \ + "update_sd_firmware=" \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "if mmc dev ${mmcdev}; then " \ + "if ${get_cmd} ${update_sd_firmware_filename}; then " \ + "setexpr fw_sz ${filesize} / 0x200; " \ + "setexpr fw_sz ${fw_sz} + 1; " \ + "mmc write ${loadaddr} 0x2 ${fw_sz}; " \ + "fi; " \ + "fi\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} " \ + "root=${mmcroot}\0" \ + "loadbootscript=" \ + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootm ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootm; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootm; " \ + "fi;\0" \ + "netargs=setenv bootargs console=${console},${baudrate} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${uimage}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "bootm ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootm; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootm; " \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loaduimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else run netboot; fi" + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT "=> " +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_CBSIZE 256 + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_CMDLINE_EDITING + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* FLASH and environment organization */ +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_ENV_SIZE (8 * 1024) + +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_ENV_OFFSET (6 * 64 * 1024) +#define CONFIG_SYS_MMC_ENV_DEV 0 + +#define CONFIG_OF_LIBFDT +#define CONFIG_CMD_BOOTZ + +#ifndef CONFIG_SYS_DCACHE_OFF +#define CONFIG_CMD_CACHE +#endif + +#endif /* __CONFIG_H * */ |