diff options
| author | Hongbo Zhang <hongbo.zhang@nxp.com> | 2016-08-19 17:20:31 +0800 |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2016-09-14 14:07:35 -0700 |
| commit | 349cfc973f8470a7839d762c25b62b4c4f4e8683 (patch) | |
| tree | e41b21c8037866479d95b4169958ac77186eeda6 | |
| parent | d38def1f34c7c282cd1c2f4ec6d99349bb1c1552 (diff) | |
nxp: ls102xa: add registers definition for system sleep
This patch adds definitions of all the regesters necessary for
system sleep.
Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
| -rw-r--r-- | arch/arm/include/asm/arch-ls102xa/config.h | 2 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 52 | ||||
| -rw-r--r-- | include/configs/ls1021aqds.h | 7 |
3 files changed, 60 insertions, 1 deletions
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index b0bf92e44c..ab9493f01c 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -16,7 +16,9 @@ #define CONFIG_SYS_DCSRBAR 0x20000000 #define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00220000) +#define CONFIG_SYS_DCSR_RCPM_ADDR (CONFIG_SYS_DCSRBAR + 0x00222000) +#define CONFIG_SYS_GIC_ADDR (CONFIG_SYS_IMMR + 0x00400000) #define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000) #define CONFIG_SYS_CCI400_ADDR (CONFIG_SYS_IMMR + 0x00180000) #define CONFIG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000) diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h index 0a80772b51..c34fd63e66 100644 --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h @@ -161,6 +161,17 @@ struct ccsr_gur { #define SCFG_SNPCNFGCR_DBG_RD_WR 0x000c0000 #define SCFG_SNPCNFGCR_EDMA_SNP 0x00020000 #define SCFG_ENDIANCR_LE 0x80000000 +#define SCFG_DPSLPCR_WDRR_EN 0x00000001 +#define SCFG_PMCINTECR_LPUART 0x40000000 +#define SCFG_PMCINTECR_FTM 0x20000000 +#define SCFG_PMCINTECR_GPIO 0x10000000 +#define SCFG_PMCINTECR_IRQ0 0x08000000 +#define SCFG_PMCINTECR_IRQ1 0x04000000 +#define SCFG_PMCINTECR_ETSECRXG0 0x00800000 +#define SCFG_PMCINTECR_ETSECRXG1 0x00400000 +#define SCFG_PMCINTECR_ETSECERRG0 0x00080000 +#define SCFG_PMCINTECR_ETSECERRG1 0x00040000 +#define SCFG_CLUSTERPMCR_WFIL2EN 0x80000000 /* Supplemental Configuration Unit */ struct ccsr_scfg { @@ -226,7 +237,7 @@ struct ccsr_scfg { u32 debug_streamid; u32 resv10[5]; u32 snpcnfgcr; - u32 resv11[1]; + u32 hrstcr; u32 intpcr; u32 resv12[20]; u32 scfgrevcr; @@ -243,6 +254,9 @@ struct ccsr_scfg { u32 sdhciovserlcr; u32 resv14[61]; u32 sparecr[8]; + u32 resv15[248]; + u32 core0sftrstsr; + u32 clusterpmcr; }; /* Clocking */ @@ -433,6 +447,42 @@ struct ccsr_ahci { u32 cmds; /* port 0/1 CMD status error */ }; +#define RCPM_POWMGTCSR 0x130 +#define RCPM_POWMGTCSR_SERDES_PW 0x80000000 +#define RCPM_POWMGTCSR_LPM20_REQ 0x00100000 +#define RCPM_POWMGTCSR_LPM20_ST 0x00000200 +#define RCPM_POWMGTCSR_P_LPM20_ST 0x00000100 +#define RCPM_IPPDEXPCR0 0x140 +#define RCPM_IPPDEXPCR0_ETSEC 0x80000000 +#define RCPM_IPPDEXPCR0_GPIO 0x00000040 +#define RCPM_IPPDEXPCR1 0x144 +#define RCPM_IPPDEXPCR1_LPUART 0x40000000 +#define RCPM_IPPDEXPCR1_FLEXTIMER 0x20000000 +#define RCPM_IPPDEXPCR1_OCRAM1 0x10000000 +#define RCPM_NFIQOUTR 0x15c +#define RCPM_NIRQOUTR 0x16c +#define RCPM_DSIMSKR 0x18c +#define RCPM_CLPCL10SETR 0x1c4 +#define RCPM_CLPCL10SETR_C0 0x00000001 + +struct ccsr_rcpm { + u8 rev1[0x4c]; + u32 twaitsr; + u8 rev2[0xe0]; + u32 powmgtcsr; + u8 rev3[0xc]; + u32 ippdexpcr0; + u32 ippdexpcr1; + u8 rev4[0x14]; + u32 nfiqoutr; + u8 rev5[0xc]; + u32 nirqoutr; + u8 rev6[0x1c]; + u32 dsimskr; + u8 rev7[0x34]; + u32 clpcl10setr; +}; + uint get_svr(void); #endif /* __ASM_ARCH_LS102XA_IMMAP_H_ */ diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 105702d22e..7a256da1f2 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -287,6 +287,13 @@ unsigned long get_board_ddr_clk(void); #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 +#define QIXIS_CTL_SYS 0x5 +#define QIXIS_CTL_SYS_EVTSW_MASK 0x0c +#define QIXIS_CTL_SYS_EVTSW_IRQ 0x04 +#define QIXIS_RST_FORCE_3 0x45 +#define QIXIS_RST_FORCE_3_PCIESLOT1 0x80 +#define QIXIS_PWR_CTL2 0x21 +#define QIXIS_PWR_CTL2_PCTL 0x2 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ |