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authorIcenowy Zheng <icenowy@aosc.io>2017-07-20 14:00:31 +0800
committerJagan Teki <jagan@amarulasolutions.com>2017-08-11 15:49:39 +0530
commit39858b12cceed3894cc62d194f098396f4306c0c (patch)
tree2dc0166b2a3f27fd131cf19880be12db121bcb6d
parent8792a64d87708139bc0cf8b48d4a580a39167473 (diff)
sunxi: add PRCM secure switch register definition
Some new Allwinner SoCs' PRCM has a secure switch register, which controls the access to some clock and power registers in PRCM block. Add the definition of this register and its bits in the PRCM header file. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Tested-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Jagan Teki <jagan@openedev.com>
-rw-r--r--arch/arm/include/asm/arch-sunxi/prcm.h6
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-sunxi/prcm.h b/arch/arm/include/asm/arch-sunxi/prcm.h
index ae3880b13b..ba4427c925 100644
--- a/arch/arm/include/asm/arch-sunxi/prcm.h
+++ b/arch/arm/include/asm/arch-sunxi/prcm.h
@@ -196,6 +196,10 @@
#define PRCM_CPU3_PWR_CLAMP(n) (((n) & 0xff) << 0)
#define PRCM_CPU3_PWR_CLAMP_MASK PRCM_CPU3_PWR_CLAMP(0xff)
+#define PRCM_SEC_SWITCH_APB0_CLK_NONSEC (0x1 << 0)
+#define PRCM_SEC_SWITCH_PLL_CFG_NONSEC (0x1 << 1)
+#define PRCM_SEC_SWITCH_PWR_GATE_NONSEC (0x1 << 2)
+
#ifndef __ASSEMBLY__
#include <linux/compiler.h>
@@ -233,6 +237,8 @@ struct __packed sunxi_prcm_reg {
u32 dram_pwr; /* 0x180 */
u8 res12[0xc]; /* 0x184 */
u32 dram_tst; /* 0x190 */
+ u8 res13[0x3c]; /* 0x194 */
+ u32 prcm_sec_switch; /* 0x1d0 */
};
void prcm_apb0_enable(u32 flags);