diff options
| author | Fabio Estevam <fabio.estevam@freescale.com> | 2012-11-15 11:23:24 +0000 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2012-11-19 08:49:00 +0100 |
| commit | 3cea335c3410f71524b50263b8af0e7eb69ebbe4 (patch) | |
| tree | 8bd13629d47da2981d0ff603fdd3b2812c8a94c4 | |
| parent | de5bf02cb1f61de0c65a539cd0083ac8ab07ec50 (diff) | |
spi: mxc_spi: Fix spi clock glitch durant reset
Measuring the spi clock line on a scope shows a 'glitch' during the reset of the
spi.
Fix this by toggling only the MXC_CSPICTRL_EN bit, so that the clock line becomes
always stable.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
| -rw-r--r-- | drivers/spi/mxc_spi.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c index b6bad98952..859c43fee2 100644 --- a/drivers/spi/mxc_spi.c +++ b/drivers/spi/mxc_spi.c @@ -140,8 +140,8 @@ static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs, reg_ctrl = reg_read(®s->ctrl); /* Reset spi */ - reg_write(®s->ctrl, 0); - reg_write(®s->ctrl, (reg_ctrl | 0x1)); + reg_write(®s->ctrl, (reg_ctrl & ~MXC_CSPICTRL_EN)); + reg_write(®s->ctrl, (reg_ctrl | MXC_CSPICTRL_EN)); /* * The following computation is taken directly from Freescale's code. |