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authorBin Meng <bmeng.cn@gmail.com>2017-08-15 22:41:50 -0700
committerBin Meng <bmeng.cn@gmail.com>2017-09-16 14:57:44 +0800
commit3df39ef10704e82a61972fe2f71b6ff4466b7724 (patch)
tree60fe4bddcf5c5c9571f3f5afaf5ac93db0d47e1a
parent079c92b0a77b9a9bf237a9430ed16cf81d43ce5d (diff)
x86: tsc: Add Airmont reference clock values
Per the Intel 64 and IA-32 Architecture Software Developer's Manual, add the reference clock for Intel Atom Processors based on the Airmont Microarchitecture (Braswell). This keeps in sync with Linux kernel commit: 6fcb41c: x86/tsc_msr: Add Airmont reference clock values Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
-rw-r--r--drivers/timer/tsc_timer.c17
1 files changed, 10 insertions, 7 deletions
diff --git a/drivers/timer/tsc_timer.c b/drivers/timer/tsc_timer.c
index 4d1fc9cd13..77040afafe 100644
--- a/drivers/timer/tsc_timer.c
+++ b/drivers/timer/tsc_timer.c
@@ -18,7 +18,7 @@
#include <asm/msr.h>
#include <asm/u-boot-x86.h>
-#define MAX_NUM_FREQS 8
+#define MAX_NUM_FREQS 9
DECLARE_GLOBAL_DATA_PTR;
@@ -40,17 +40,20 @@ struct freq_desc {
static struct freq_desc freq_desc_tables[] = {
/* PNW */
- { 6, 0x27, 0, { 0, 0, 0, 0, 0, 99840, 0, 83200 } },
+ { 6, 0x27, 0, { 0, 0, 0, 0, 0, 99840, 0, 83200, 0 } },
/* CLV+ */
- { 6, 0x35, 0, { 0, 133200, 0, 0, 0, 99840, 0, 83200 } },
+ { 6, 0x35, 0, { 0, 133200, 0, 0, 0, 99840, 0, 83200, 0 } },
/* TNG - Intel Atom processor Z3400 series */
- { 6, 0x4a, 1, { 0, 100000, 133300, 0, 0, 0, 0, 0 } },
+ { 6, 0x4a, 1, { 0, 100000, 133300, 0, 0, 0, 0, 0, 0 } },
/* VLV2 - Intel Atom processor E3000, Z3600, Z3700 series */
- { 6, 0x37, 1, { 83300, 100000, 133300, 116700, 80000, 0, 0, 0 } },
+ { 6, 0x37, 1, { 83300, 100000, 133300, 116700, 80000, 0, 0, 0, 0 } },
/* ANN - Intel Atom processor Z3500 series */
- { 6, 0x5a, 1, { 83300, 100000, 133300, 100000, 0, 0, 0, 0 } },
+ { 6, 0x5a, 1, { 83300, 100000, 133300, 100000, 0, 0, 0, 0, 0 } },
+ /* AMT - Intel Atom processor X7-Z8000 and X5-Z8000 series */
+ { 6, 0x4c, 1, { 83300, 100000, 133300, 116700,
+ 80000, 93300, 90000, 88900, 87500 } },
/* Ivybridge */
- { 6, 0x3a, 2, { 0, 0, 0, 0, 0, 0, 0, 0 } },
+ { 6, 0x3a, 2, { 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
};
static int match_cpu(u8 family, u8 model)