diff options
| author | wdenk <wdenk> | 2003-04-05 00:53:31 +0000 |
|---|---|---|
| committer | wdenk <wdenk> | 2003-04-05 00:53:31 +0000 |
| commit | 3e38691e8f7aa0d9b498d76c7279ddec6e4946f3 (patch) | |
| tree | bec2e661298847dc5bcf9335ef31259686e882e1 | |
| parent | 36c05a80ecbe3997abd9aa628a68dd6c0bacf681 (diff) | |
* Patch by Arun Dharankar, 4 Apr 2003:
Add IDMA example code (tested on 8260 only)
* Add support for Purple Board (MIPS64 5Kc)
* Add support for MIPS64 5Kc CPUs
* Fix missing setting of "loadaddr" and "bootfile" on ARM and MIPS
* Patch by Denis Peter, 04 Apr 2003:
- update MIP405-4 board
* Patches by Denis Peter, 03 April 2003:
- fix PCI IRQs on MPL boards
- fix two more un-relocated pointer problems
* Fix behaviour of "run" command:
- print error message iv variable does not exist
- terminate processing of arguments in case of error
* Patches by Peter Figuli, 10 Mar 2003
- Add support for BTUART on PXA platform
- Add support for WEP EP250 (PXA) board
* Fix flash problems on INCA-IP; add tool to allow bruning images to
flash using a BDI2000
* Implement fix for I2C Edge Conditions problem for all boards that
use the bit-banging driver (common/soft_i2c.c)
* Add patches by Robert Schwebel, 31 Mar 2003:
- csb226 board: bring in sync with innokom/memsetup.S
- csb226 board: fix MDREFR handling
- misc doc fixes / extensions
- innokom board: cleanup, MDREFR fix in memsetup.S, config update
- add BOOT_PROGRESS to armlinux.c
52 files changed, 2061 insertions, 448 deletions
@@ -2,12 +2,42 @@ Changes since U-Boot 0.2.2: ====================================================================== +* Patch by Arun Dharankar, 4 Apr 2003: + Add IDMA example code (tested on 8260 only) + +* Add support for Purple Board (MIPS64 5Kc) + +* Add support for MIPS64 5Kc CPUs + +* Fix missing setting of "loadaddr" and "bootfile" on ARM and MIPS + +* Patch by Denis Peter, 04 Apr 2003: + - update MIP405-4 board + * Patch by Stefan Roese, 4 Apr 2003: - U-Boot version environment variable "ver" added (CONFIG_VERSION_VARIABLE). - Changed PPC405GPr version from A to B. - Changed CPCI405 to use CTS instead of DSR on PPC405 UART1. +* Patches by Denis Peter, 03 April 2003: + - fix PCI IRQs on MPL boards + - fix two more un-relocated pointer problems + +* Fix behaviour of "run" command: + - print error message iv variable does not exist + - terminate processing of arguments in case of error + +* Patches by Peter Figuli, 10 Mar 2003 + - Add support for BTUART on PXA platform + - Add support for WEP EP250 (PXA) board + +* Fix flash problems on INCA-IP; add tool to allow bruning images to + flash using a BDI2000 + +* Implement fix for I2C Edge Conditions problem for all boards that + use the bit-banging driver (common/soft_i2c.c) + * Patch by Martin Winistoerfer, 23 Mar 2003 - Add port to MPC555/556 microcontrollers - Add support for cmi customer board with @@ -22,6 +52,11 @@ Changes since U-Boot 0.2.2: * Add patches by Robert Schwebel, 31 Mar 2003: - add ctrl-c support for kermit download - align bdinfo output on ARM + - csb226 board: bring in sync with innokom/memsetup.S + - csb226 board: fix MDREFR handling + - misc doc fixes / extensions + - innokom board: cleanup, MDREFR fix in memsetup.S, config update + - add BOOT_PROGRESS to armlinux.c * Add CPU ID, version, and clock speed for INCA-IP @@ -104,6 +104,10 @@ E: wg@denx.de D: Support for Interphase 4539 T1/E1/J1 PMC, PN62, CCM, SCM boards W: www.denx.de +N: Peter Figuli +E: peposh@etc.sk +D: Support for WEP EP250 (PXA) board + N: Thomas Frieden E: ThomasF@hyperion-entertainment.com D: Support for AmigaOne diff --git a/MAINTAINERS b/MAINTAINERS index 56f296d725..332e413756 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -241,6 +241,10 @@ Unknown / orphaned boards: # Board CPU # ######################################################################### +Peter Figuli <peposh@etc.sk> + + wepep250 xscale + Marius Gröger <mag@sysgo.de> impa7 ARM720T (EP7211) @@ -296,6 +300,7 @@ Daniel Engström <daniel@omicron.se> Wolfgang Denk <wd@denx.de> incaip MIPS32 4Kc + purple MIPS64 5Kc ######################################################################### # End of MAINTAINERS list # @@ -112,7 +112,7 @@ LIST_ARM9="at91rm9200dk smdk2400 smdk2410 trab VCMA9" ## Xscale Systems ######################################################################### -LIST_xscale="cradle csb226 innokom lubbock" +LIST_xscale="cradle csb226 innokom lubbock wepep250" LIST_arm="${LIST_SA} ${LIST_ARM7} ${LIST_ARM9} ${LIST_xscale}" @@ -123,7 +123,9 @@ LIST_arm="${LIST_SA} ${LIST_ARM7} ${LIST_ARM9} ${LIST_xscale}" LIST_mips4kc="incaip" -LIST_mips="${LIST_mips4kc}" +LIST_mips5kc="purple" + +LIST_mips="${LIST_mips4kc} ${LIST_mips5kc}" #----- for now, just run PPC by default ----- @@ -629,7 +629,6 @@ BAB7xx_config: unconfig ELPPC_config: unconfig @./mkconfig $(@:_config=) ppc 74xx_7xx elppc eltec - #======================================================================== # ARM #======================================================================== @@ -699,6 +698,9 @@ innokom_config : unconfig lubbock_config : unconfig @./mkconfig $(@:_config=) arm xscale lubbock +wepep250_config : unconfig + @./mkconfig $(@:_config=) arm xscale wepep250 + #======================================================================== # i386 #======================================================================== @@ -718,7 +720,11 @@ sc520_cdp_config : unconfig incaip_config : unconfig @./mkconfig $(@:_config=) mips mips incaip +purple_config : unconfig + @./mkconfig $(@:_config=) mips mips purple +######################################################################### +######################################################################### clean: find . -type f \ @@ -726,7 +732,8 @@ clean: -o -name '*.o' -o -name '*.a' \) -print \ | xargs rm -f rm -f examples/hello_world examples/timer \ - examples/eepro100_eeprom examples/sched + examples/eepro100_eeprom examples/sched \ + examples/mem_to_mem_idma2intr rm -f tools/img2srec tools/mkimage tools/envcrc tools/gen_eth_addr rm -f tools/easylogo/easylogo tools/bmp_logo rm -f tools/gdb/astest tools/gdb/gdbcont tools/gdb/gdbsend @@ -741,7 +748,7 @@ clobber: clean rm -fr *.*~ rm -f u-boot u-boot.bin u-boot.elf u-boot.srec u-boot.map System.map rm -f tools/crc32.c tools/environment.c tools/env/crc32.c - rm -f cpu/mpc824x/bedbug_603e.c + rm -f tools/inca-swap-bytes cpu/mpc824x/bedbug_603e.c rm -f include/asm/arch include/asm mrproper \ @@ -1462,7 +1462,7 @@ following configurations: These settings describe a second storage area used to hold a redundand copy of the environment data, so that there is - a valid backup copy in case there is a power failur during + a valid backup copy in case there is a power failure during a "saveenv" operation. BE CAREFUL! Any changes to the flash layout, and some changes to the diff --git a/board/csb226/memsetup.S b/board/csb226/memsetup.S index 65671842aa..60f9d50b58 100644 --- a/board/csb226/memsetup.S +++ b/board/csb226/memsetup.S @@ -38,6 +38,9 @@ DRAM_SIZE: .long CFG_DRAM_SIZE sub pc,pc,#4 .endm +_TEXT_BASE: + .word TEXT_BASE + /* * Memory setup @@ -222,23 +225,28 @@ mem_init: /* Step 2c: Write FLYCNFG FIXME: what's that??? */ /* ---------------------------------------------------------------- */ + /* test if we run from flash or RAM - RAM/BDI: don't setup RAM */ + adr r3, mem_init /* r0 <- current position of code */ + ldr r2, =mem_init + cmp r3, r2 /* skip init if in place */ + beq initirqs + /* ---------------------------------------------------------------- */ /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */ /* ---------------------------------------------------------------- */ /* Before accessing MDREFR we need a valid DRI field, so we set */ - /* this to power on defaults + DIR field. */ + /* this to power on defaults + DRI field. */ - ldr r4, =0x03ca4fff - str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ - ldr r4, [r1, #MDREFR_OFFSET] + ldr r3, =CFG_MDREFR_VAL + ldr r2, =0xFFF + and r3, r3, r2 + ldr r4, =0x03ca4000 + orr r4, r4, r3 - ldr r4, =0x03ca4030 str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ - ldr r4, [r1, #MDREFR_OFFSET] - - /* Note: preserve the mdrefr value in r4 */ + ldr r4, [r1, #MDREFR_OFFSET] /* ---------------------------------------------------------------- */ @@ -258,18 +266,16 @@ mem_init: /* Step 4: Initialize SDRAM */ /* ---------------------------------------------------------------- */ - /* Step 4a: assert MDREFR:K1RUN and MDREFR:K2RUN and configure */ + /* Step 4a: assert MDREFR:K?RUN and configure */ /* MDREFR:K1DB2 and MDREFR:K2DB2 as desired. */ - orr r4, r4, #(MDREFR_K1RUN|MDREFR_K0RUN) - - str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ - ldr r4, [r1, #MDREFR_OFFSET] - + ldr r4, =CFG_MDREFR_VAL + str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ + ldr r4, [r1, #MDREFR_OFFSET] /* Step 4b: de-assert MDREFR:SLFRSH. */ - bic r4, r4, #(MDREFR_SLFRSH) + bic r4, r4, #(MDREFR_SLFRSH) str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ ldr r4, [r1, #MDREFR_OFFSET] diff --git a/board/innokom/flash.c b/board/innokom/flash.c index 32c57d8d96..b7c2072e70 100644 --- a/board/innokom/flash.c +++ b/board/innokom/flash.c @@ -10,7 +10,8 @@ * Robert Schwebel, Pengutronix, <r.schwebel@pengutronix.de> * * (C) Copyright 2002 - * Kai-Uwe Bloem, GDS, <kai-uwe.bloem@auerswald.de> + * Auerswald GmbH & Co KG, Germany + * Kai-Uwe Bloem <kai-uwe.bloem@auerswald.de> * * See file CREDITS for list of people who contributed to this * project. diff --git a/board/innokom/innokom.c b/board/innokom/innokom.c index 5ee511764a..da238da6c7 100644 --- a/board/innokom/innokom.c +++ b/board/innokom/innokom.c @@ -48,7 +48,7 @@ int i2c_init_board(void) icr = ICR; ICR &= ~(ICR_SCLE | ICR_IUE); /* set gpio pin low _before_ we change direction to output */ - GPCR(70) = GPIO_bit(70); + GPCR(70) = GPIO_bit(70); /* now toggle between output=low and high-impedance */ for (i = 0; i < 20; i++) { @@ -100,13 +100,8 @@ int board_init (void) /* memory and cpu-speed are setup before relocation */ /* so we do _nothing_ here */ - /* arch number of Innokom board */ gd->bd->bi_arch_number = MACH_TYPE_INNOKOM; - - /* adress of boot parameters */ gd->bd->bi_boot_params = 0xa0000100; - - /* baud rate */ gd->bd->bi_baudrate = CONFIG_BAUDRATE; return 0; diff --git a/board/innokom/memsetup.S b/board/innokom/memsetup.S index a2bc99d12d..60f9d50b58 100644 --- a/board/innokom/memsetup.S +++ b/board/innokom/memsetup.S @@ -237,17 +237,16 @@ mem_init: /* ---------------------------------------------------------------- */ /* Before accessing MDREFR we need a valid DRI field, so we set */ - /* this to power on defaults + DIR field. */ + /* this to power on defaults + DRI field. */ - ldr r4, =0x03ca4fff - str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ - ldr r4, [r1, #MDREFR_OFFSET] + ldr r3, =CFG_MDREFR_VAL + ldr r2, =0xFFF + and r3, r3, r2 + ldr r4, =0x03ca4000 + orr r4, r4, r3 - ldr r4, =0x03ca4030 str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ - ldr r4, [r1, #MDREFR_OFFSET] - - /* Note: preserve the mdrefr value in r4 */ + ldr r4, [r1, #MDREFR_OFFSET] /* ---------------------------------------------------------------- */ @@ -267,18 +266,16 @@ mem_init: /* Step 4: Initialize SDRAM */ /* ---------------------------------------------------------------- */ - /* Step 4a: assert MDREFR:K1RUN and MDREFR:K2RUN and configure */ + /* Step 4a: assert MDREFR:K?RUN and configure */ /* MDREFR:K1DB2 and MDREFR:K2DB2 as desired. */ - orr r4, r4, #(MDREFR_K1RUN|MDREFR_K0RUN) - - str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ - ldr r4, [r1, #MDREFR_OFFSET] - + ldr r4, =CFG_MDREFR_VAL + str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ + ldr r4, [r1, #MDREFR_OFFSET] /* Step 4b: de-assert MDREFR:SLFRSH. */ - bic r4, r4, #(MDREFR_SLFRSH) + bic r4, r4, #(MDREFR_SLFRSH) str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ ldr r4, [r1, #MDREFR_OFFSET] diff --git a/board/mpl/common/pci.c b/board/mpl/common/pci.c index a26f542eb3..692930b416 100644 --- a/board/mpl/common/pci.c +++ b/board/mpl/common/pci.c @@ -65,21 +65,22 @@ void pci_pip405_write_regs(struct pci_controller *hose, pci_dev_t dev, static void pci_pip405_fixup_irq(struct pci_controller *hose, pci_dev_t dev) { unsigned char int_line = 0xff; + unsigned char pin; /* * Write pci interrupt line register */ if(PCI_DEV(dev)==0) /* Device0 = PPC405 -> skip */ return; - if(PCI_FUNC(dev)==0) - { - /* assuming all function 0 are using their INTA# Pin*/ - int_line=PCI_IRQ_VECTOR(dev); - pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line); + pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &pin); + if ((pin == 0) || (pin > 4)) + return; + + int_line = ((PCI_DEV(dev) + (pin-1) + 10) % 4) + 28; + pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line); #ifdef DEBUG - printf("Fixup IRQ: dev %d (%x) int line %d 0x%x\n", - PCI_DEV(dev),dev,int_line,int_line); + printf("Fixup IRQ: dev %d (%x) int line %d 0x%x\n", + PCI_DEV(dev),dev,int_line,int_line); #endif - } } extern void pci_405gp_init(struct pci_controller *hose); @@ -90,11 +91,34 @@ static struct pci_controller hose = { fixup_irq: pci_pip405_fixup_irq, }; + +static void reloc_pci_cfg_table(struct pci_config_table *table) +{ + DECLARE_GLOBAL_DATA_PTR; + unsigned long addr; + + for (; table && table->vendor; table++) { + addr = (ulong) (table->config_device) + gd->reloc_off; +#ifdef DEBUG + printf ("device \"%d\": 0x%08lx => 0x%08lx\n", + table->device, (ulong) (table->config_device), addr); +#endif + table->config_device = + (void (*)(struct pci_controller* hose, pci_dev_t dev, + struct pci_config_table *))addr; + table->priv[0]+=gd->reloc_off; + } +} + void pci_init_board(void) { /*we want the ptrs to RAM not flash (ie don't use init list)*/ hose.fixup_irq = pci_pip405_fixup_irq; hose.config_table = pci_pip405_config_table; + reloc_pci_cfg_table(hose.config_table); +#ifdef DEBUG + printf("Init PCI: fixup_irq=%p config_table=%p hose=%p\n",pci_pip405_fixup_irq,pci_pip405_config_table,hose); +#endif pci_405gp_init(&hose); } diff --git a/board/mpl/mip405/mip405.c b/board/mpl/mip405/mip405.c index 8bab47c107..95ad97c589 100644 --- a/board/mpl/mip405/mip405.c +++ b/board/mpl/mip405/mip405.c @@ -128,6 +128,15 @@ const sdram_t sdram_table[] = { 2, /* Address Mode = 2 */ 4, /* size value */ 1}, /* ECC enabled */ + { 0x03, /* Rev A, 128MByte -4 Board */ + 3, /* Case Latenty = 3 */ + 3, /* trp 20ns / 7.5 ns datain[27] */ + 3, /* trcd 20ns /7.5 ns (datain[29]) */ + 6, /* tras 44ns /7.5 ns (datain[30]) */ + 4, /* tcpt 44 - 20ns = 24ns */ + 3, /* Address Mode = 3 */ + 5, /* size value */ + 1}, /* ECC enabled */ { 0xff, /* terminator */ 0xff, 0xff, @@ -616,9 +625,15 @@ void print_mip405_rev (void) int last_stage_init (void) { + /* write correct LED configuration */ if (miiphy_write (0x1, 0x14, 0x2402) != 0) { printf ("Error writing to the PHY\n"); } + /* since LED/CFG2 is not connected on the -2, + * write to correct capability information */ + if (miiphy_write (0x1, 0x4, 0x01E1) != 0) { + printf ("Error writing to the PHY\n"); + } print_mip405_rev (); show_stdio_dev (); check_env (); diff --git a/board/svm_sc8xx/ppcboot.lds b/board/svm_sc8xx/ppcboot.lds deleted file mode 100644 index 5f5e2e4280..0000000000 --- a/board/svm_sc8xx/ppcboot.lds +++ /dev/null @@ -1,133 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - ppc/ppcstring.o (.text) - ppc/vsprintf.o (.text) - ppc/crc32.o (.text) - ppc/zlib.o (.text) - - . = env_offset; - common/environment.o(.text) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} - diff --git a/board/svm_sc8xx/ppcboot.lds.debug b/board/svm_sc8xx/ppcboot.lds.debug deleted file mode 100644 index f230a6b493..0000000000 --- a/board/svm_sc8xx/ppcboot.lds.debug +++ /dev/null @@ -1,131 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - ppc/vsprintf.o (.text) - ppc/crc32.o (.text) - - . = env_offset; - common/environment.o(.text) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} - diff --git a/board/wepep250/Makefile b/board/wepep250/Makefile new file mode 100644 index 0000000000..d4314d76af --- /dev/null +++ b/board/wepep250/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2000, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := wepep250.o flash.o +SOBJS := memsetup.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $^ + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/wepep250/config.mk b/board/wepep250/config.mk new file mode 100644 index 0000000000..792f0ee97c --- /dev/null +++ b/board/wepep250/config.mk @@ -0,0 +1,11 @@ +# +# This is config used for compilation of WEP EP250 sources +# +# You might change location of U-Boot in memory by setting right TEXT_BASE. +# This allows for example having one copy located at the end of ram and stored +# in flash device and later on while developing use other location to test +# the code in RAM device only. +# + +TEXT_BASE = 0xa1fe0000 +#TEXT_BASE = 0xa1001000
\ No newline at end of file diff --git a/board/wepep250/flash.c b/board/wepep250/flash.c new file mode 100644 index 0000000000..319dddc4b2 --- /dev/null +++ b/board/wepep250/flash.c @@ -0,0 +1,321 @@ +/* + * Copyright (C) 2003 ETC s.r.o. + * + * This code was inspired by Marius Groeger and Kyle Harris code + * available in other board ports for U-Boot + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Written by Peter Figuli <peposh@etc.sk>, 2003. + * + */ + +#include <common.h> +#include "intel.h" + + +/* + * This code should handle CFI FLASH memory device. This code is very + * minimalistic approach without many essential error handling code as well. + * Because U-Boot actually is missing smart handling of FLASH device, + * we just set flash_id to anything else to FLASH_UNKNOW, so common code + * can call us without any restrictions. + * TODO: Add CFI Query, to be able to determine FLASH device. + * TODO: Add error handling code + * NOTE: This code was tested with BUS_WIDTH 4 and ITERLEAVE 2 only, but + * hopefully may work with other configurations. + */ + +#if ( WEP_FLASH_BUS_WIDTH == 1 ) +# define FLASH_BUS vu_char +# if ( WEP_FLASH_INTERLEAVE == 1 ) +# define FLASH_CMD( x ) x +# else +# error "With 8bit bus only one chip is allowed" +# endif + + +#elif ( WEP_FLASH_BUS_WIDTH == 2 ) +# define FLASH_BUS vu_short +# if ( WEP_FLASH_INTERLEAVE == 1 ) +# define FLASH_CMD( x ) x +# elif ( WEP_FLASH_INTERLEAVE == 2 ) +# define FLASH_CMD( x ) (( x << 8 )| x ) +# else +# error "With 16bit bus only 1 or 2 chip(s) are allowed" +# endif + + +#elif ( WEP_FLASH_BUS_WIDTH == 4 ) +# define FLASH_BUS vu_long +# if ( WEP_FLASH_INTERLEAVE == 1 ) +# define FLASH_CMD( x ) x +# elif ( WEP_FLASH_INTERLEAVE == 2 ) +# define FLASH_CMD( x ) (( x << 16 )| x ) +# elif ( WEP_FLASH_INTERLEAVE == 4 ) +# define FLASH_CMD( x ) (( x << 24 )|( x << 16 ) ( x << 8 )| x ) +# else +# error "With 32bit bus only 1,2 or 4 chip(s) are allowed" +# endif + +#else +# error "Flash bus width might be 1,2,4 for 8,16,32 bit configuration" +#endif + + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; + +static FLASH_BUS flash_status_reg (void) +{ + + FLASH_BUS *addr = (FLASH_BUS *) 0; + + *addr = FLASH_CMD (CFI_INTEL_CMD_READ_STATUS_REGISTER); + + return *addr; +} + +static int flash_ready (ulong timeout) +{ + int ok = 1; + + reset_timer_masked (); + while ((flash_status_reg () & FLASH_CMD (CFI_INTEL_SR_READY)) != + FLASH_CMD (CFI_INTEL_SR_READY)) { + if (get_timer_masked () > timeout && timeout != 0) { + ok = 0; + break; + } + } + return ok; +} + +#if ( CFG_MAX_FLASH_BANKS != 1 ) +# error "WEP platform has only one flash bank!" +#endif + + +ulong flash_init (void) +{ + int i; + FLASH_BUS address = WEP_FLASH_BASE; + + flash_info[0].size = WEP_FLASH_BANK_SIZE; + flash_info[0].sector_count = CFG_MAX_FLASH_SECT; + flash_info[0].flash_id = INTEL_MANUFACT; + memset (flash_info[0].protect, 0, CFG_MAX_FLASH_SECT); + + for (i = 0; i < CFG_MAX_FLASH_SECT; i++) { + flash_info[0].start[i] = address; +#ifdef WEP_FLASH_UNLOCK + /* Some devices are hw locked after start. */ + *((FLASH_BUS *) address) = FLASH_CMD (CFI_INTEL_CMD_LOCK_SETUP); + *((FLASH_BUS *) address) = FLASH_CMD (CFI_INTEL_CMD_UNLOCK_BLOCK); + flash_ready (0); + *((FLASH_BUS *) address) = FLASH_CMD (CFI_INTEL_CMD_READ_ARRAY); +#endif + address += WEP_FLASH_SECT_SIZE; + } + + flash_protect (FLAG_PROTECT_SET, + CFG_FLASH_BASE, + CFG_FLASH_BASE + _armboot_end_data - _armboot_start, + &flash_info[0]); + + flash_protect (FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); + + return WEP_FLASH_BANK_SIZE; +} + +void flash_print_info (flash_info_t * info) +{ + int i; + + printf (" Intel vendor\n"); + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; i++) { + if (!(i % 5)) { + printf ("\n"); + } + + printf (" %08lX%s", info->start[i], + info->protect[i] ? " (RO)" : " "); + } + printf ("\n"); +} + + +int flash_erase (flash_info_t * info, int s_first, int s_last) +{ + int flag, non_protected = 0, sector; + int rc = ERR_OK; + + FLASH_BUS *address; + + for (sector = s_first; sector <= s_last; sector++) { + if (!info->protect[sector]) { + non_protected++; + } + } + + if (!non_protected) { + return ERR_PROTECTED; + } + + /* + * Disable interrupts which might cause a timeout + * here. Remember that our exception vectors are + * at address 0 in the flash, and we don't want a + * (ticker) exception to happen while the flash + * chip is in programming mode. + */ + flag = disable_interrupts (); + + + /* Start erase on unprotected sectors */ + for (sector = s_first; sector <= s_last && !ctrlc (); sector++) { + if (info->protect[sector]) { + printf ("Protected sector %2d skipping...\n", sector); + continue; + } else { + printf ("Erasing sector %2d ... ", sector); + } + + address = (FLASH_BUS *) (info->start[sector]); + + *address = FLASH_CMD (CFI_INTEL_CMD_BLOCK_ERASE); + *address = FLASH_CMD (CFI_INTEL_CMD_CONFIRM); + if (flash_ready (CFG_FLASH_ERASE_TOUT)) { + *address = FLASH_CMD (CFI_INTEL_CMD_CLEAR_STATUS_REGISTER); + printf ("ok.\n"); + } else { + *address = FLASH_CMD (CFI_INTEL_CMD_SUSPEND); + rc = ERR_TIMOUT; + printf ("timeout! Aborting...\n"); + break; + } + *address = FLASH_CMD (CFI_INTEL_CMD_READ_ARRAY); + } + if (ctrlc ()) + printf ("User Interrupt!\n"); + + /* allow flash to settle - wait 10 ms */ + udelay_masked (10000); + if (flag) { + enable_interrupts (); + } + + return rc; +} + +static int write_data (flash_info_t * info, ulong dest, FLASH_BUS data) +{ + FLASH_BUS *address = (FLASH_BUS *) dest; + int rc = ERR_OK; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*address & data) != data) { + return ERR_NOT_ERASED; + } + + /* + * Disable interrupts which might cause a timeout + * here. Remember that our exception vectors are + * at address 0 in the flash, and we don't want a + * (ticker) exception to happen while the flash + * chip is in programming mode. + */ + + flag = disable_interrupts (); + + *address = FLASH_CMD (CFI_INTEL_CMD_CLEAR_STATUS_REGISTER); + *address = FLASH_CMD (CFI_INTEL_CMD_PROGRAM1); + *address = data; + + if (!flash_ready (CFG_FLASH_WRITE_TOUT)) { + *address = FLASH_CMD (CFI_INTEL_CMD_SUSPEND); + rc = ERR_TIMOUT; + printf ("timeout! Aborting...\n"); + } + + *address = FLASH_CMD (CFI_INTEL_CMD_READ_ARRAY); + if (flag) { + enable_interrupts (); + } + + return rc; +} + +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + ulong read_addr, write_addr; + FLASH_BUS data; + int i, result = ERR_OK; + + + read_addr = addr & ~(sizeof (FLASH_BUS) - 1); + write_addr = read_addr; + if (read_addr != addr) { + data = 0; + for (i = 0; i < sizeof (FLASH_BUS); i++) { + if (read_addr < addr || cnt == 0) { + data |= *((uchar *) read_addr) << i * 8; + } else { + data |= (*src++) << i * 8; + cnt--; + } + read_addr++; + } + if ((result = write_data (info, write_addr, data)) != ERR_OK) { + return result; + } + write_addr += sizeof (FLASH_BUS); + } + for (; cnt >= sizeof (FLASH_BUS); cnt -= sizeof (FLASH_BUS)) { + if ((result = write_data (info, write_addr, + *((FLASH_BUS *) src))) != ERR_OK) { + return result; + } + write_addr += sizeof (FLASH_BUS); + src += sizeof (FLASH_BUS); + } + if (cnt > 0) { + read_addr = write_addr; + data = 0; + for (i = 0; i < sizeof (FLASH_BUS); i++) { + if (cnt > 0) { + data |= (*src++) << i * 8; + cnt--; + } else { + data |= *((uchar *) read_addr) << i * 8; + } + read_addr++; + } + if ((result = write_data (info, write_addr, data)) != 0) { + return result; + } + } + return ERR_OK; +} diff --git a/board/wepep250/intel.h b/board/wepep250/intel.h new file mode 100644 index 0000000000..f622590107 --- /dev/null +++ b/board/wepep250/intel.h @@ -0,0 +1,100 @@ +/* + * Copyright (C) 2002 ETC s.r.o. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the ETC s.r.o. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Written by Marcel Telka <marcel@telka.sk>, 2002. + * + * Documentation: + * [1] Intel Corporation, "3 Volt Intel Strata Flash Memory 28F128J3A, 28F640J3A, + * 28F320J3A (x8/x16)", April 2002, Order Number: 290667-011 + * [2] Intel Corporation, "3 Volt Synchronous Intel Strata Flash Memory 28F640K3, 28F640K18, + * 28F128K3, 28F128K18, 28F256K3, 28F256K18 (x16)", June 2002, Order Number: 290737-005 + * + * This file is taken from OpenWinCE project hosted by SourceForge.net + * + */ + +#ifndef FLASH_INTEL_H +#define FLASH_INTEL_H + +#include <common.h> + +/* Intel CFI commands - see Table 4. in [1] and Table 3. in [2] */ + +#define CFI_INTEL_CMD_READ_ARRAY 0xFF /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_READ_IDENTIFIER 0x90 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_READ_QUERY 0x98 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_READ_STATUS_REGISTER 0x70 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_CLEAR_STATUS_REGISTER 0x50 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_PROGRAM1 0x40 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_PROGRAM2 0x10 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_WRITE_TO_BUFFER 0xE8 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_CONFIRM 0xD0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_BLOCK_ERASE 0x20 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_SUSPEND 0xB0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_RESUME 0xD0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_LOCK_SETUP 0x60 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_LOCK_BLOCK 0x01 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_UNLOCK_BLOCK 0xD0 /* 28FxxxJ3A - unlocks all blocks, 28FFxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_LOCK_DOWN_BLOCK 0x2F /* 28FxxxK3, 28FxxxK18 */ + +/* Intel CFI Status Register bits - see Table 6. in [1] and Table 7. in [2] */ + +#define CFI_INTEL_SR_READY 1 << 7 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_SR_ERASE_SUSPEND 1 << 6 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_SR_ERASE_ERROR 1 << 5 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_SR_PROGRAM_ERROR 1 << 4 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_SR_VPEN_ERROR 1 << 3 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_SR_PROGRAM_SUSPEND 1 << 2 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_SR_BLOCK_LOCKED 1 << 1 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_SR_BEFP 1 << 0 /* 28FxxxK3, 28FxxxK18 */ + +/* Intel flash device ID codes for 28FxxxJ3A - see Table 5. in [1] */ + +#define CFI_CHIP_INTEL_28F320J3A 0x0016 +#define CFI_CHIPN_INTEL_28F320J3A "28F320J3A" +#define CFI_CHIP_INTEL_28F640J3A 0x0017 +#define CFI_CHIPN_INTEL_28F640J3A "28F640J3A" +#define CFI_CHIP_INTEL_28F128J3A 0x0018 +#define CFI_CHIPN_INTEL_28F128J3A "28F128J3A" + +/* Intel flash device ID codes for 28FxxxK3 and 28FxxxK18 - see Table 8. in [2] */ + +#define CFI_CHIP_INTEL_28F640K3 0x8801 +#define CFI_CHIPN_INTEL_28F640K3 "28F640K3" +#define CFI_CHIP_INTEL_28F128K3 0x8802 +#define CFI_CHIPN_INTEL_28F128K3 "28F128K3" +#define CFI_CHIP_INTEL_28F256K3 0x8803 +#define CFI_CHIPN_INTEL_28F256K3 "28F256K3" +#define CFI_CHIP_INTEL_28F640K18 0x8805 +#define CFI_CHIPN_INTEL_28F640K18 "28F640K18" +#define CFI_CHIP_INTEL_28F128K18 0x8806 +#define CFI_CHIPN_INTEL_28F128K18 "28F128K18" +#define CFI_CHIP_INTEL_28F256K18 0x8807 +#define CFI_CHIPN_INTEL_28F256K18 "28F256K18" + +#endif /* FLASH_INTEL_H */ + diff --git a/board/wepep250/memsetup.S b/board/wepep250/memsetup.S new file mode 100644 index 0000000000..8a5d42fc4b --- /dev/null +++ b/board/wepep250/memsetup.S @@ -0,0 +1,147 @@ +/* + * Copyright (C) 2001, 2002 ETC s.r.o. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA + * 02111-1307, USA. + * + * Written by Marcel Telka <marcel@telka.sk>, 2001, 2002. + * Changes for U-Boot Peter Figuli <peposh@etc.sk>, 2003. + * + * This file is taken from OpenWinCE project hosted by SourceForge.net + * + * Documentation: + * [1] Intel Corporation, "Intel PXA250 and PXA210 Application Processors + * Developer's Manual", February 2002, Order Number: 278522-001 + * [2] Samsung Electronics, "8Mx16 SDRAM 54CSP K4S281633D-RL/N/P", + * Revision 1.0, February 2002 + * [3] Samsung Electronics, "16Mx16 SDRAM 54CSP K4S561633C-RL(N)", + * Revision 1.0, February 2002 + * +*/ + +#include <config.h> +#include <version.h> +#include <asm/arch/pxa-regs.h> + +.globl memsetup +memsetup: + + mov r10, lr + +/* setup memory - see 6.12 in [1] + * Step 1 - wait 200 us + */ + mov r0,#0x2700 /* wait 200 us @ 99.5 MHz */ +1: subs r0, r0, #1 + bne 1b +/* TODO: complete step 1 for Synchronous Static memory*/ + + ldr r0, =0x48000000 /* MC_BASE */ + + + +/* step 1.a - setup MSCx + */ + ldr r1, =0x000012B3 /* MSC0_RRR0(1) | MSC0_RDN0(2) | MSC0_RDF0(11) | MSC0_RT0(3) */ + str r1, [r0, #0x8] /* MSC0_OFFSET */ + +/* step 1.c - clear MDREFR:K1FREE, set MDREFR:DRI + * see AUTO REFRESH chapter in section D. in [2] and in [3] + * DRI = (64ms / 4096) * 99.53MHz / 32 = 48 for K4S281633 + * DRI = (64ms / 8192) * 99.52MHz / 32 = 24 for K4S561633 + * TODO: complete for Synchronous Static memory + */ + ldr r1, [r0, #4] /* MDREFR_OFFSET */ + ldr r2, =0x01000FFF /* MDREFR_K1FREE | MDREFR_DRI_MASK */ + bic r1, r1, r2 +#if defined( WEP_SDRAM_K4S281633 ) + orr r1, r1, #48 /* MDREFR_DRI(48) */ +#elif defined( WEP_SDRAM_K4S561633 ) + orr r1, r1, #24 /* MDREFR_DRI(24) */ +#else +#error SDRAM chip is not defined +#endif + + str r1, [r0, #4] /* MDREFR_OFFSET */ + +/* Step 2 - only for Synchronous Static memory (TODO) + * + * Step 3 - same as step 4 + * + * Step 4 + * + * Step 4.a - set MDREFR:K1RUN, clear MDREFR:K1DB2 + */ + orr r1, r1, #0x00010000 /* MDREFR_K1RUN */ + bic r1, r1, #0x00020000 /* MDREFR_K1DB2 */ + str r1, [r0, #4] /* MDREFR_OFFSET */ + +/* Step 4.b - clear MDREFR:SLFRSH */ + bic r1, r1, #0x00400000 /* MDREFR_SLFRSH */ + str r1, [r0, #4] /* MDREFR_OFFSET */ + +/* Step 4.c - set MDREFR:E1PIN */ + orr r1, r1, #0x00008000 /* MDREFR_E1PIN */ + str r1, [r0, #4] /* MDREFR_OFFSET */ + +/* Step 4.d - automatically done + * + * Steps 4.e and 4.f - configure SDRAM + */ +#if defined( WEP_SDRAM_K4S281633 ) + ldr r1, =0x00000AA8 /* MDCNFG_DTC0(2) | MDCNFG_DLATCH0 | MDCNFG_DCAC0(1) | MDCNFG_DRAC0(1) | MDCNFG_DNB0 */ +#elif defined( WEP_SDRAM_K4S561633 ) + ldr r1, =0x00000AC8 /* MDCNFG_DTC0(2) | MDCNFG_DLATCH0 | MDCNFG_DCAC0(1) | MDCNFG_DRAC0(2) | MDCNFG_DNB0 */ +#else +#error SDRAM chip is not defined +#endif + str r1, [r0, #0] /* MDCNFG_OFFSET */ + +/* Step 5 - wait at least 200 us for SDRAM + * see section B. in [2] + */ + mov r2,#0x2700 /* wait 200 us @ 99.5 MHz */ +1: subs r2, r2, #1 + bne 1b + +/* Step 6 - after reset dcache is disabled, so automatically done + * + * Step 7 - eight refresh cycles + */ + mov r2, #0xA0000000 + ldr r3, [r2] + ldr r3, [r2] + ldr r3, [r2] + ldr r3, [r2] + ldr r3, [r2] + ldr r3, [r2] + ldr r3, [r2] + ldr r3, [r2] + +/* Step 8 - we don't need dcache now + * + * Step 9 - enable SDRAM partition 0 + */ + orr r1, r1, #1 /* MDCNFG_DE0 */ + str r1, [r0, #0] /* MDCNFG_OFFSET */ + +/* Step 10 - write MDMRS */ + mov r1, #0 + str r1, [r0, #0x40] /* MDMRS_OFFSET */ + +/* Step 11 - optional (TODO) */ + + mov pc,r10 + diff --git a/board/wepep250/u-boot.lds b/board/wepep250/u-boot.lds new file mode 100644 index 0000000000..280fc48ace --- /dev/null +++ b/board/wepep250/u-boot.lds @@ -0,0 +1,55 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/xscale/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + armboot_end_data = .; + + . = ALIGN(4); + bss_start = .; + .bss : { *(.bss) } + bss_end = .; + + armboot_end = .; +} diff --git a/board/wepep250/wepep250.c b/board/wepep250/wepep250.c new file mode 100644 index 0000000000..ebf75d745d --- /dev/null +++ b/board/wepep250/wepep250.c @@ -0,0 +1,77 @@ +/* + * Copyright (C) 2003 ETC s.r.o. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Written by Peter Figuli <peposh@etc.sk>, 2003. + * + */ + +#include <common.h> +#include <asm/arch/pxa-regs.h> + +int board_init( void ){ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_arch_number = 288; + gd->bd->bi_boot_params = 0xa0000000; +/* + * Setup GPIO stuff to get serial working + */ +#if defined( CONFIG_FFUART ) + GPDR1 = 0x80; + GAFR1_L = 0x8010; +#elif defined( CONFIG_BTUART ) + GPDR1 = 0x800; + GAFR1_L = 0x900000; +#endif + PSSR = 0x20; + +/* + * Following code is just bug workaround, remove it if not neccessary + */ + + /* cpu/xscale/cpu.c do not set armboot_real_end that is used for + malloc pool.*/ + if( _armboot_real_end == 0xbadc0de ){ + _armboot_real_end = _armboot_end; + } + return 0; +} + +int dram_init( void ){ + DECLARE_GLOBAL_DATA_PTR; + +#if ( CONFIG_NR_DRAM_BANKS > 0 ) + gd->bd->bi_dram[0].start = WEP_SDRAM_1; + gd->bd->bi_dram[0].size = WEP_SDRAM_1_SIZE; +#endif +#if ( CONFIG_NR_DRAM_BANKS > 1 ) + gd->bd->bi_dram[1].start = WEP_SDRAM_2; + gd->bd->bi_dram[1].size = WEP_SDRAM_2_SIZE; +#endif +#if ( CONFIG_NR_DRAM_BANKS > 2 ) + gd->bd->bi_dram[2].start = WEP_SDRAM_3; + gd->bd->bi_dram[2].size = WEP_SDRAM_3_SIZE; +#endif +#if ( CONFIG_NR_DRAM_BANKS > 3 ) + gd->bd->bi_dram[3].start = WEP_SDRAM_4; + gd->bd->bi_dram[3].size = WEP_SDRAM_4_SIZE; +#endif + + return 0; +} + diff --git a/common/cmd_date.c b/common/cmd_date.c index 1472e3f1aa..2139cebf83 100644 --- a/common/cmd_date.c +++ b/common/cmd_date.c @@ -34,10 +34,13 @@ const char *weekdays[] = { "Sun", "Mon", "Tues", "Wednes", "Thurs", "Fri", "Satur", }; +#define RELOC(a) ((typeof(a))((unsigned long)(a) + gd->reloc_off)) + int mk_date (char *, struct rtc_time *); int do_date (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { + DECLARE_GLOBAL_DATA_PTR; struct rtc_time tm; int rcode = 0; @@ -64,7 +67,7 @@ int do_date (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) printf ("Date: %4d-%02d-%02d (%sday) Time: %2d:%02d:%02d\n", tm.tm_year, tm.tm_mon, tm.tm_mday, (tm.tm_wday<0 || tm.tm_wday>6) ? - "unknown " : weekdays[tm.tm_wday], + "unknown " : RELOC(weekdays[tm.tm_wday]), tm.tm_hour, tm.tm_min, tm.tm_sec); return 0; diff --git a/common/hush.c b/common/hush.c index fcc3559235..19933980e7 100644 --- a/common/hush.c +++ b/common/hush.c @@ -2357,34 +2357,35 @@ static void initialize_context(struct p_context *ctx) * should handle if, then, elif, else, fi, for, while, until, do, done. * case, function, and select are obnoxious, save those for later. */ +struct reserved_combo { + char *literal; + int code; + long flag; +}; +/* Mostly a list of accepted follow-up reserved words. + * FLAG_END means we are done with the sequence, and are ready + * to turn the compound list into a command. + * FLAG_START means the word must start a new compound list. + */ +static struct reserved_combo reserved_list[] = { + { "if", RES_IF, FLAG_THEN | FLAG_START }, + { "then", RES_THEN, FLAG_ELIF | FLAG_ELSE | FLAG_FI }, + { "elif", RES_ELIF, FLAG_THEN }, + { "else", RES_ELSE, FLAG_FI }, + { "fi", RES_FI, FLAG_END }, + { "for", RES_FOR, FLAG_IN | FLAG_START }, + { "while", RES_WHILE, FLAG_DO | FLAG_START }, + { "until", RES_UNTIL, FLAG_DO | FLAG_START }, + { "in", RES_IN, FLAG_DO }, + { "do", RES_DO, FLAG_DONE }, + { "done", RES_DONE, FLAG_END } +}; +#define NRES (sizeof(reserved_list)/sizeof(struct reserved_combo)) + int reserved_word(o_string *dest, struct p_context *ctx) { - struct reserved_combo { - char *literal; - int code; - long flag; - }; - /* Mostly a list of accepted follow-up reserved words. - * FLAG_END means we are done with the sequence, and are ready - * to turn the compound list into a command. - * FLAG_START means the word must start a new compound list. - */ - static struct reserved_combo reserved_list[] = { - { "if", RES_IF, FLAG_THEN | FLAG_START }, - { "then", RES_THEN, FLAG_ELIF | FLAG_ELSE | FLAG_FI }, - { "elif", RES_ELIF, FLAG_THEN }, - { "else", RES_ELSE, FLAG_FI }, - { "fi", RES_FI, FLAG_END }, - { "for", RES_FOR, FLAG_IN | FLAG_START }, - { "while", RES_WHILE, FLAG_DO | FLAG_START }, - { "until", RES_UNTIL, FLAG_DO | FLAG_START }, - { "in", RES_IN, FLAG_DO }, - { "do", RES_DO, FLAG_DONE }, - { "done", RES_DONE, FLAG_END } - }; struct reserved_combo *r; for (r=reserved_list; -#define NRES sizeof(reserved_list)/sizeof(struct reserved_combo) r<reserved_list+NRES; r++) { if (strcmp(dest->data, r->literal) == 0) { debug_printf("found reserved word %s, code %d\n",r->literal,r->code); @@ -3169,6 +3170,18 @@ int parse_file_outer(void) } #ifdef __U_BOOT__ +static void u_boot_hush_reloc(void) +{ + DECLARE_GLOBAL_DATA_PTR; + unsigned long addr; + struct reserved_combo *r; + + for (r=reserved_list; r<reserved_list+NRES; r++) { + addr = (ulong) (r->literal) + gd->reloc_off; + r->literal = (char *)addr; + } +} + int u_boot_hush_start(void) { top_vars = malloc(sizeof(struct variables)); @@ -3177,6 +3190,7 @@ int u_boot_hush_start(void) top_vars->next = 0; top_vars->flg_export = 0; top_vars->flg_read_only = 1; + u_boot_hush_reloc(); return 0; } diff --git a/common/main.c b/common/main.c index e32845e471..33d871771b 100644 --- a/common/main.c +++ b/common/main.c @@ -862,7 +862,6 @@ int run_command (const char *cmd, int flag) int do_run (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) { int i; - int rcode = 1; if (argc < 2) { printf ("Usage:\n%s\n", cmdtp->usage); @@ -870,13 +869,21 @@ int do_run (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) } for (i=1; i<argc; ++i) { + char *arg; + + if ((arg = getenv (argv[i])) == NULL) { + printf ("## Error: \"%s\" not defined\n", argv[i]); + return 1; + } #ifndef CFG_HUSH_PARSER - if (run_command (getenv (argv[i]), flag) != -1) ++rcode; + if (run_command (arg, flag) == -1) + return 1; #else - if (parse_string_outer(getenv (argv[i]), - FLAG_PARSE_SEMICOLON | FLAG_EXIT_FROM_LOOP) == 0) ++rcode; + if (parse_string_outer(arg, + FLAG_PARSE_SEMICOLON | FLAG_EXIT_FROM_LOOP) == 0) + return 1; #endif } - return ((rcode == i) ? 0 : 1); + return 0; } -#endif +#endif /* CFG_CMD_RUN */ diff --git a/cpu/mips/cache.S b/cpu/mips/cache.S index aeb04b3790..2715b9b025 100644 --- a/cpu/mips/cache.S +++ b/cpu/mips/cache.S @@ -253,9 +253,9 @@ dcache_disable: .globl mips_cache_lock .ent mips_cache_lock mips_cache_lock: - li a1, K0BASE - CFG_DCACHE_SIZE + li a1, K0BASE - CFG_DCACHE_SIZE/2 addu a0, a1 - li a2, CFG_DCACHE_SIZE + li a2, CFG_DCACHE_SIZE/2 li a3, CFG_CACHELINE_SIZE move a1, a2 icacheop(a0,a1,a2,a3,0x1d) diff --git a/cpu/mips/cpu.c b/cpu/mips/cpu.c index 3fc3916b4e..e9676c1288 100644 --- a/cpu/mips/cpu.c +++ b/cpu/mips/cpu.c @@ -27,8 +27,12 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { -#ifdef CONFIG_INCA_IP +#if defined(CONFIG_INCA_IP) *INCA_IP_WDT_RST_REQ = 0x3f; +#elif defined(CONFIG_PURPLE) + void (*f)(void) = (void *) 0xbfc00000; + + f(); #endif fprintf(stderr, "*** reset failed ***\n"); return 0; diff --git a/cpu/mips/serial.c b/cpu/mips/serial.c index ebda509b11..b26f41d0c8 100644 --- a/cpu/mips/serial.c +++ b/cpu/mips/serial.c @@ -2,10 +2,49 @@ * (INCA) ASC UART support */ +#include <config.h> + +#ifdef CONFIG_PURPLE +#define serial_init asc_serial_init +#define serial_putc asc_serial_putc +#define serial_puts asc_serial_puts +#define serial_getc asc_serial_getc +#define serial_tstc asc_serial_tstc +#define serial_setbrg asc_serial_setbrg +#endif + #include <common.h> #include <asm/inca-ip.h> #include "serial.h" +#ifdef CONFIG_PURPLE + +#undef ASC_FIFO_PRESENT +#define TOUT_LOOP 100000 + +/* Set base address for second FPI interrupt control register bank */ +#define SFPI_INTCON_BASEADDR 0xBF0F0000 + +/* Register offset from base address */ +#define FBS_ISR 0x00000000 /* Interrupt status register */ +#define FBS_IMR 0x00000008 /* Interrupt mask register */ +#define FBS_IDIS 0x00000010 /* Interrupt disable register */ + +/* Interrupt status register bits */ +#define FBS_ISR_AT 0x00000040 /* ASC transmit interrupt */ +#define FBS_ISR_AR 0x00000020 /* ASC receive interrupt */ +#define FBS_ISR_AE 0x00000010 /* ASC error interrupt */ +#define FBS_ISR_AB 0x00000008 /* ASC transmit buffer interrupt */ +#define FBS_ISR_AS 0x00000004 /* ASC start of autobaud detection interrupt */ +#define FBS_ISR_AF 0x00000002 /* ASC end of autobaud detection interrupt */ + +#else + +#define ASC_FIFO_PRESENT + +#endif + + #define SET_BIT(reg, mask) reg |= (mask) #define CLEAR_BIT(reg, mask) reg &= (~mask) #define CLEAR_BITS(reg, mask) CLEAR_BIT(reg, mask) @@ -32,8 +71,10 @@ static volatile incaAsc_t *pAsc = (incaAsc_t *)INCA_IP_ASC; int serial_init (void) { +#ifdef CONFIG_INCA_IP /* we have to set PMU.EN13 bit to enable an ASC device*/ INCAASC_PMU_ENABLE(13); +#endif /* and we have to set CLC register*/ CLEAR_BIT(pAsc->asc_clc, ASCCLC_DISS); @@ -45,6 +86,7 @@ int serial_init (void) /* select input port */ pAsc->asc_pisel = (CONSOLE_TTY & 0x1); +#ifdef ASC_FIFO_PRESENT /* TXFIFO's filling level */ SET_BITFIELD(pAsc->asc_txfcon, ASCTXFCON_TXFITLMASK, ASCTXFCON_TXFITLOFF, INCAASC_TXFIFO_FL); @@ -56,20 +98,25 @@ int serial_init (void) ASCRXFCON_RXFITLOFF, INCAASC_RXFIFO_FL); /* enable RXFIFO */ SET_BIT(pAsc->asc_rxfcon, ASCRXFCON_RXFEN); +#endif /* enable error signals */ SET_BIT(pAsc->asc_con, ASCCON_FEN); SET_BIT(pAsc->asc_con, ASCCON_OEN); +#ifdef CONFIG_INCA_IP /* acknowledge ASC interrupts */ ASC_INTERRUPTS_CLEAR(INCAASC_IRQ_LINE_ALL); /* disable ASC interrupts */ ASC_INTERRUPTS_DISABLE(INCAASC_IRQ_LINE_ALL); +#endif +#ifdef ASC_FIFO_PRESENT /* set FIFOs into the transparent mode */ SET_BIT(pAsc->asc_txfcon, ASCTXFCON_TXTMEN); SET_BIT(pAsc->asc_rxfcon, ASCRXFCON_RXTMEN); +#endif /* set baud rate */ serial_setbrg(); @@ -85,7 +132,11 @@ void serial_setbrg (void) ulong uiReloadValue, fdv; ulong f_ASC; +#ifdef CONFIG_INCA_IP f_ASC = incaip_get_fpiclk(); +#else + f_ASC = ASC_CLOCK_RATE; +#endif #ifndef INCAASC_USE_FDV fdv = 2; @@ -210,10 +261,15 @@ static int serial_setopt (void) void serial_putc (const char c) { +#ifdef ASC_FIFO_PRESENT uint txFl = 0; +#else + uint timeout = 0; +#endif if (c == '\n') serial_putc ('\r'); +#ifdef ASC_FIFO_PRESENT /* check do we have a free space in the TX FIFO */ /* get current filling level */ do @@ -221,8 +277,25 @@ void serial_putc (const char c) txFl = ( pAsc->asc_fstat & ASCFSTAT_TXFFLMASK ) >> ASCFSTAT_TXFFLOFF; } while ( txFl == INCAASC_TXFIFO_FULL ); +#else + + while(!(*(volatile unsigned long*)(SFPI_INTCON_BASEADDR + FBS_ISR) & + FBS_ISR_AB)) + { + if (timeout++ > TOUT_LOOP) + { + break; + } + } +#endif pAsc->asc_tbuf = c; /* write char to Transmit Buffer Register */ + +#ifndef ASC_FIFO_PRESENT + *(volatile unsigned long*)(SFPI_INTCON_BASEADDR + FBS_ISR) = FBS_ISR_AB | + FBS_ISR_AT; +#endif + /* check for errors */ if ( pAsc->asc_con & ASCCON_OE ) { @@ -251,6 +324,10 @@ int serial_getc (void) c = (char)(pAsc->asc_rbuf & symbol_mask); +#ifndef ASC_FIFO_PRESENT + *(volatile unsigned long*)(SFPI_INTCON_BASEADDR + FBS_ISR) = FBS_ISR_AR; +#endif + return c; } @@ -258,10 +335,19 @@ int serial_tstc (void) { int res = 1; +#ifdef ASC_FIFO_PRESENT if ( (pAsc->asc_fstat & ASCFSTAT_RXFFLMASK) == 0 ) { res = 0; } +#else + if (!(*(volatile unsigned long*)(SFPI_INTCON_BASEADDR + FBS_ISR) & + FBS_ISR_AR)) + + { + res = 0; + } +#endif else if ( pAsc->asc_con & ASCCON_FE ) { SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLRFE); diff --git a/cpu/mips/start.S b/cpu/mips/start.S index bf11655617..86a8407f61 100644 --- a/cpu/mips/start.S +++ b/cpu/mips/start.S @@ -42,9 +42,12 @@ _start: RVECENT(reset,0) /* U-boot entry point */ RVECENT(reset,1) /* software reboot */ -#ifdef CONFIG_INCA_IP - .word 0x000020C4 /* EBU init code, fetched during booting */ - .word 0x00000000 /* phase of the flash */ +#if defined(CONFIG_INCA_IP) + .word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */ + .word 0x00000000 /* phase of the flash */ +#elif defined(CONFIG_PURPLE) + .word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */ + .word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */ #else RVECENT(romReserved,2) #endif @@ -178,6 +181,30 @@ _start: * 128 * 8 == 1024 == 0x400 * so this is address R_VEC+0x400 == 0xbfc00400 */ +#ifdef CONFIG_PURPLE +/* 0xbfc00400 */ + .word 0xdc870000 + .word 0xfca70000 + .word 0x20840008 + .word 0x20a50008 + .word 0x20c6ffff + .word 0x14c0fffa + .word 0x00000000 + .word 0x03e00008 + .word 0x00000000 + .word 0x00000000 +/* 0xbfc00428 */ + .word 0xdc870000 + .word 0xfca70000 + .word 0x20840008 + .word 0x20a50008 + .word 0x20c6ffff + .word 0x14c0fffa + .word 0x00000000 + .word 0x03e00008 + .word 0x00000000 + .word 0x00000000 +#endif /* CONFIG_PURPLE */ .align 4 reset: @@ -283,12 +310,17 @@ relocate_code: * t1 = target address * t2 = source end address */ + /* On the purple board we copy the code earlier in a special way + * in order to solve flash problems + */ +#ifndef CONFIG_PURPLE 1: lw t3, 0(t0) sw t3, 0(t1) addu t0, 4 ble t0, t2, 1b addu t1, 4 /* delay slot */ +#endif /* If caches were enabled, we would have to flush them here. */ diff --git a/cpu/xscale/serial.c b/cpu/xscale/serial.c index 35302a7761..c9d5f70bc4 100644 --- a/cpu/xscale/serial.c +++ b/cpu/xscale/serial.c @@ -67,7 +67,21 @@ void serial_setbrg (void) FFIER = IER_UUE; /* Enable FFUART */ -#elif CONFIG_STUART +#elif defined(CONFIG_BTUART) + CKEN |= CKEN7_BTUART; + + BTIER = 0; + BTFCR = 0; + + /* set baud rate */ + BTLCR = LCR_DLAB; + BTDLL = quot & 0xff; + BTDLH = quot >> 8; + BTLCR = LCR_WLS0 | LCR_WLS1; + + BTIER = IER_UUE; /* Enable BFUART */ + +#elif defined(CONFIG_STUART) #error "Bad: not implemented yet!" #else #error "Bad: you didn't configured serial ..." @@ -98,7 +112,10 @@ void serial_putc (const char c) while ((FFLSR & LSR_TEMT) == 0); FFTHR = c; -#elif CONFIG_STUART +#elif defined(CONFIG_BTUART) + while ((BTLSR & LSR_TEMT ) == 0 ); + BTTHR = c; +#elif defined(CONFIG_STUART) #endif /* If \n, also do \r */ @@ -115,7 +132,9 @@ int serial_tstc (void) { #ifdef CONFIG_FFUART return FFLSR & LSR_DR; -#elif CONFIG_STUART +#elif defined(CONFIG_BTUART) + return BTLSR & LSR_DR; +#elif defined(CONFIG_STUART) #endif } @@ -130,7 +149,11 @@ int serial_getc (void) while (!(FFLSR & LSR_DR)); return (char) FFRBR & 0xff; -#elif CONFIG_STUART +#elif defined(CONFIG_BTUART) + while (!(BTLSR & LSR_DR)); + + return (char) BTRBR & 0xff; +#elif defined(CONFIG_STUART) #endif } diff --git a/doc/I2C_Edge_Conditions b/doc/I2C_Edge_Conditions index 91557a3ca9..be7f1bee1f 100644 --- a/doc/I2C_Edge_Conditions +++ b/doc/I2C_Edge_Conditions @@ -31,8 +31,13 @@ Notes !!!THIS IS AN UNDOCUMENTED I2C BUS BUG, NOT A IBM 4xx BUG!!! This reset edge condition could possibly be present in every I2C -controller and device available. We should probably have a bus reset -function for all our target CPUs. +controller and device available. For boards where a I2C bus reset +function can be implemented a i2c_init_board() function should be +provided and enabled by #define'ing CFG_I2C_INIT_BOARD in your +board's config file. Note that this is NOT necessary when using the +bit-banging I2C driver (common/soft_i2c.c) as this already includes +the I2C bus reset sequence. + Many thanks to Bill Hunter for finding this serious BUG. email to: <williamhunter@attbi.com> diff --git a/doc/README.INCA-IP b/doc/README.INCA-IP new file mode 100644 index 0000000000..517eec0401 --- /dev/null +++ b/doc/README.INCA-IP @@ -0,0 +1,44 @@ + +Flash programming on the INCA-IP board is complicated because of the +EBU swapping unit. A BDI2000 can be used for flash programming only +if the EBU swapping unit is enabled; otherwise it will not detect the +flash memory. But the EBU swapping unit is disadbled after reset, so +if you program some code to flash with the swapping unit on, it will +not be runnable with the swapping unit off. + +The consequence is that you have to write a pre-swapped image to +flash using the BDI2000. A simple host-side tool "inca-swap-bytes" is +provided in the "tools/" directory. Use it as follows: + + bash$ ./inca-swap-bytes <u-boot.bin >u-boot.bin.swp + +Note that the current BDI config file _disables_ the EBU swapping +unit for the flash bank 0. To enable it, (this is required for the +BDI flash commands to work) uncomment the following line in the +config file: + + ;WM32 0xb8000260 0x404161ff ; Swapping unit enabled + +and comment out + + WM32 0xb8000260 0x004161ff ; Swapping unit disabled + +Alternatively, you can use "mm 0xb8000260 <value>" commands to +enable/disable the swapping unit manually. + +Just for reference, here is the complete sequence of actions we took +to install a U-Boot image into flash. + + 1. ./inca-swap-bytes <u-boot.bin >u-boot.bin.swp + + 2. From BDI: + + mm 0xb8000260 0x404161ff + erase 0xb0000000 + erase 0xb0010000 + prog 0xb0000000 /tftpboot/INCA/u-boot.bin.swp bin + mm 0xb8000260 0x004161ff + go 0xb0000000 + + +(C) 2003 Wolfgang Denk diff --git a/doc/README.idma2intr b/doc/README.idma2intr new file mode 100644 index 0000000000..1828b51302 --- /dev/null +++ b/doc/README.idma2intr @@ -0,0 +1,10 @@ +(C) 2003 Arun Dharankar <ADharankar@ATTBI.Com> + +Attached is an IDMA example code for MPC8260/PPCBoot. I had tried to +search around and could not find any for implementing IDMA, so +implemented one. Its not coded in the best way, but works. + +Also, I was able to test the IDMA specific code under Linux also +(with modifications). My requirement was to implement it for +CompactFlash implemented in memory mode, and it works for it under +PPCBoot and Linux. diff --git a/doc/README.sched b/doc/README.sched new file mode 100644 index 0000000000..3aa89e6d39 --- /dev/null +++ b/doc/README.sched @@ -0,0 +1,53 @@ +Notes on the scheduler in sched.c: +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + 'sched.c' provides an very simplistic multi-threading scheduler. + See the example, function 'sched(...)', in the same file for its + API usage. + + Until an exhaustive testing can be done, the implementation cannot + qualify as that of production quality. It works with the example + in 'sched.c', it may or may not work in other cases. + + +Limitations: +~~~~~~~~~~~~ + + - There are NO primitives for thread synchronization (locking, + notify etc). + + - Only the GPRs and FPRs context is saved during a thread context + switch. Other registers on the PowerPC processor (60x, 7xx, 7xxx + etc) are NOT saved. + + - The scheduler is NOT transparent to the user. The user + applications must invoke thread_yield() to allow other threads to + scheduler. + + - There are NO priorities, and the scheduling policy is round-robin + based. + + - There are NO capabilities to collect thread CPU usage, scheduler + stats, thread status etc. + + - The semantics are somewhat based on those of pthreads, but NOT + the same. + + - Only seven threads are allowed. These can be easily increased by + changing "#define MAX_THREADS" depending on the available memory. + + - The stack size of each thread is 8KBytes. This can be easily + increased depending on the requirement and the available memory, + by increasing "#define STK_SIZE". + + - Only one master/parent thread is allowed, and it cannot be + stopped or deleted. Any given thread is NOT allowed to stop or + delete itself. + + - There NOT enough safety checks as are probably in the other + threads implementations. + + - There is no parent-child relationship between threads. Only one + thread may thread_join, preferably the master/parent thread. + +(C) 2003 Arun Dharankar <ADharankar@ATTBI.Com> diff --git a/drivers/ct69000.c b/drivers/ct69000.c index 7962f74d6c..563556285b 100644 --- a/drivers/ct69000.c +++ b/drivers/ct69000.c @@ -830,6 +830,7 @@ FindAndSetPllParamIntoXrRegs (unsigned int pixelclock, unsigned int m, n, vld, pd, PD, fref, xr_cb; unsigned int fvcomin, fvcomax, pclckmin, pclckmax, pclk; unsigned int pfreq, fvco, new_pixclock; + unsigned int D,nback,mback; fref = VIDEO_FREF; pd = 1; @@ -850,10 +851,19 @@ FindAndSetPllParamIntoXrRegs (unsigned int pixelclock, PD++; } /* fvco is exactly pd * pixelclock and higher than the ninmal VCO frequency */ - vld = (param->vld_set > param->vld_not_set) ? - param->vld_not_set : param->vld_set; - /* start with lower VLD (higher VLD is NOT yet implemented */ - FindBestPQFittingMN (fvco / vld, fref, param->mn_min, param->mn_max, &m, &n); /* rds = 1 */ + /* first try */ + vld = param->vld_set; + D=FindBestPQFittingMN (fvco / vld, fref, param->mn_min, param->mn_max, &m, &n); /* rds = 1 */ + mback=m; + nback=n; + /* second try */ + vld = param->vld_not_set; + if(D<FindBestPQFittingMN (fvco / vld, fref, param->mn_min, param->mn_max, &m, &n)) { /* rds = 1 */ + /* first try was better */ + m=mback; + n=nback; + vld = param->vld_set; + } m += param->mn_diff; n += param->mn_diff; PRINTF ("VCO %d, pd %d, m %d n %d vld %d \n", fvco, pd, m, n, vld); diff --git a/examples/Makefile b/examples/Makefile index 163b404e40..b690fa0702 100644 --- a/examples/Makefile +++ b/examples/Makefile @@ -33,7 +33,7 @@ SREC += sched.srec BIN += sched.bin endif -ifeq ($(CPU),mips) +ifeq ($(ARCH),mips) SREC = BIN = endif @@ -44,6 +44,12 @@ SREC += timer.srec BIN += timer.bin endif +# The following example is 8260 specific... +ifeq ($(CPU),mpc8260) +SREC += mem_to_mem_idma2intr.srec +BIN += mem_to_mem_idma2intr.bin +endif + # Utility for resetting i82559 EEPROM ifeq ($(BOARD),oxc) SREC += eepro100_eeprom.srec diff --git a/examples/mem_to_mem_idma2intr.c b/examples/mem_to_mem_idma2intr.c new file mode 100644 index 0000000000..93c6f77ca5 --- /dev/null +++ b/examples/mem_to_mem_idma2intr.c @@ -0,0 +1,391 @@ +/* The dpalloc function used and implemented in this file was derieved + * from PPCBoot/U-Boot file "cpu/mpc8260/commproc.c". + */ + +/* Author: Arun Dharankar <ADharankar@ATTBI.Com> + * This example is meant to only demonstrate how the IDMA could be used. + */ + +/* + * This file is based on "arch/ppc/8260_io/commproc.c" - here is it's + * copyright notice: + * + * General Purpose functions for the global management of the + * 8260 Communication Processor Module. + * Copyright (c) 1999 Dan Malek (dmalek@jlc.net) + * Copyright (c) 2000 MontaVista Software, Inc (source@mvista.com) + * 2.3.99 Updates + * + * In addition to the individual control of the communication + * channels, there are a few functions that globally affect the + * communication processor. + * + * Buffer descriptors must be allocated from the dual ported memory + * space. The allocator for that is here. When the communication + * process is reset, we reclaim the memory available. There is + * currently no deallocator for this memory. + */ + + + +#include <common.h> +#include <syscall.h> + +#define STANDALONE + +#ifndef STANDALONE /* Linked into/Part of PPCBoot */ +#include <command.h> +#include <watchdog.h> +#else /* Standalone app of PPCBoot */ +#include <syscall.h> +#define printf mon_printf +#define tstc mon_tstc +#define getc mon_getc +#define putc mon_putc +#define udelay mon_udelay +#define malloc mon_malloc +#define WATCHDOG_RESET() { \ + *(ushort *)(CFG_IMMR + 0x1000E) = 0x556c; \ + *(ushort *)(CFG_IMMR + 0x1000E) = 0xaa39; \ + } +#endif /* STANDALONE */ + +static int debug = 1; + +#define DEBUG(fmt, args...) { \ + if(debug != 0) { \ + printf("[%s %d %s]: ",__FILE__,__LINE__,__FUNCTION__); \ + printf(fmt, ##args); \ + } \ +} + +#define CPM_CR_IDMA1_SBLOCK (0x14) +#define CPM_CR_IDMA2_SBLOCK (0x15) +#define CPM_CR_IDMA3_SBLOCK (0x16) +#define CPM_CR_IDMA4_SBLOCK (0x17) +#define CPM_CR_IDMA1_PAGE (0x07) +#define CPM_CR_IDMA2_PAGE (0x08) +#define CPM_CR_IDMA3_PAGE (0x09) +#define CPM_CR_IDMA4_PAGE (0x0a) +#define PROFF_IDMA1_BASE ((uint)0x87fe) +#define PROFF_IDMA2_BASE ((uint)0x88fe) +#define PROFF_IDMA3_BASE ((uint)0x89fe) +#define PROFF_IDMA4_BASE ((uint)0x8afe) + +#define CPM_CR_INIT_TRX ((ushort)0x0000) +#define CPM_CR_FLG ((ushort)0x0001) + +#define mk_cr_cmd(PG, SBC, MCN, OP) \ + ((PG << 26) | (SBC << 21) | (MCN << 6) | OP) + + +#pragma pack(1) +typedef struct ibdbits { + unsigned b_valid:1; + unsigned b_resv1:1; + unsigned b_wrap:1; + unsigned b_interrupt:1; + unsigned b_last:1; + unsigned b_resv2:1; + unsigned b_cm:1; + unsigned b_resv3:2; + unsigned b_sdn:1; + unsigned b_ddn:1; + unsigned b_dgbl:1; + unsigned b_dbo:2; + unsigned b_resv4:1; + unsigned b_ddtb:1; + unsigned b_resv5:2; + unsigned b_sgbl:1; + unsigned b_sbo:2; + unsigned b_resv6:1; + unsigned b_sdtb:1; + unsigned b_resv7:9; +} ibdbits_t; + +#pragma pack(1) +typedef union ibdbitsu { + ibdbits_t b; + uint i; +} ibdbitsu_t; + +#pragma pack(1) +typedef struct idma_buf_desc { + ibdbitsu_t ibd_bits; /* Status and Control */ + uint ibd_datlen; /* Data length in buffer */ + uint ibd_sbuf; /* Source buffer addr in host mem */ + uint ibd_dbuf; /* Destination buffer addr in host mem */ +} ibd_t; + + +#pragma pack(1) +typedef struct dcmbits { + unsigned b_fb:1; + unsigned b_lp:1; + unsigned b_resv1:3; + unsigned b_tc2:1; + unsigned b_resv2:1; + unsigned b_wrap:3; + unsigned b_sinc:1; + unsigned b_dinc:1; + unsigned b_erm:1; + unsigned b_dt:1; + unsigned b_sd:2; +} dcmbits_t; + +#pragma pack(1) +typedef union dcmbitsu { + dcmbits_t b; + ushort i; +} dcmbitsu_t; + +#pragma pack(1) +typedef struct pram_idma { + ushort pi_ibase; + dcmbitsu_t pi_dcmbits; + ushort pi_ibdptr; + ushort pi_dprbuf; + ushort pi_bufinv; /* internal to CPM */ + ushort pi_ssmax; + ushort pi_dprinptr; /* internal to CPM */ + ushort pi_sts; + ushort pi_dproutptr; /* internal to CPM */ + ushort pi_seob; + ushort pi_deob; + ushort pi_dts; + ushort pi_retadd; + ushort pi_resv1; /* internal to CPM */ + uint pi_bdcnt; + uint pi_sptr; + uint pi_dptr; + uint pi_istate; +} pram_idma_t; + + +volatile immap_t *immap = (immap_t *) CFG_IMMR; +volatile ibd_t *bdf; +volatile pram_idma_t *piptr; + +volatile int dmadone; +volatile int *dmadonep = &dmadone; +void dmadone_handler (void *); + +int idma_init (void); +void idma_start (int, int, int, uint, uint, int); +uint dpalloc (uint, uint); + + +uint dpinit_done = 0; + + +#ifdef STANDALONE +int ctrlc (void) +{ + if (mon_tstc()) { + switch (mon_getc ()) { + case 0x03: /* ^C - Control C */ + return 1; + default: + break; + } + } + return 0; +} +void * memset(void * s,int c,size_t count) +{ + char *xs = (char *) s; + while (count--) + *xs++ = c; + return s; +} +int memcmp(const void * cs,const void * ct,size_t count) +{ + const unsigned char *su1, *su2; + int res = 0; + for( su1 = cs, su2 = ct; 0 < count; ++su1, ++su2, count--) + if ((res = *su1 - *su2) != 0) + break; + return res; +} +#endif /* STANDALONE */ + +#ifdef STANDALONE +int mem_to_mem_idma2intr (bd_t * bd, int argc, char *argv[]) +#else +int do_idma (bd_t * bd, int argc, char *argv[]) +#endif /* STANDALONE */ +{ + int i; + + dpinit_done = 0; + + idma_init (); + + DEBUG ("Installing dma handler\n"); + mon_install_hdlr (7, dmadone_handler, (void *) bdf); + + memset ((void *) 0x100000, 'a', 512); + memset ((void *) 0x200000, 'b', 512); + + for (i = 0; i < 32; i++) { + printf ("Startin IDMA, iteration=%d\n", i); + idma_start (1, 1, 512, 0x100000, 0x200000, 3); + } + + DEBUG ("Uninstalling dma handler\n"); + mon_free_hdlr (7); + + return 0; +} + +void +idma_start (int sinc, int dinc, int sz, uint sbuf, uint dbuf, int ttype) +{ + /* ttype is for M-M, M-P, P-M or P-P: not used for now */ + + piptr->pi_istate = 0; /* manual says: clear it before every START_IDMA */ + piptr->pi_dcmbits.b.b_resv1 = 0; + + if (sinc == 1) + piptr->pi_dcmbits.b.b_sinc = 1; + else + piptr->pi_dcmbits.b.b_sinc = 0; + + if (dinc == 1) + piptr->pi_dcmbits.b.b_dinc = 1; + else + piptr->pi_dcmbits.b.b_dinc = 0; + + piptr->pi_dcmbits.b.b_erm = 0; + piptr->pi_dcmbits.b.b_sd = 0x00; /* M-M */ + + bdf->ibd_sbuf = sbuf; + bdf->ibd_dbuf = dbuf; + bdf->ibd_bits.b.b_cm = 0; + bdf->ibd_bits.b.b_interrupt = 1; + bdf->ibd_bits.b.b_wrap = 1; + bdf->ibd_bits.b.b_last = 1; + bdf->ibd_bits.b.b_sdn = 0; + bdf->ibd_bits.b.b_ddn = 0; + bdf->ibd_bits.b.b_dgbl = 0; + bdf->ibd_bits.b.b_ddtb = 0; + bdf->ibd_bits.b.b_sgbl = 0; + bdf->ibd_bits.b.b_sdtb = 0; + bdf->ibd_bits.b.b_dbo = 1; + bdf->ibd_bits.b.b_sbo = 1; + bdf->ibd_bits.b.b_valid = 1; + bdf->ibd_datlen = 512; + + *dmadonep = 0; + + immap->im_sdma.sdma_idmr2 = (uchar) 0xf; + + immap->im_cpm.cp_cpcr = mk_cr_cmd (CPM_CR_IDMA2_PAGE, + CPM_CR_IDMA2_SBLOCK, 0x0, + 0x9) | 0x00010000; + + while (*dmadonep != 1) { + if (ctrlc ()) { + DEBUG ("\nInterrupted waiting for DMA interrupt.\n"); + goto done; + } + printf ("Waiting for DMA interrupt (dmadone=%d b_valid = %d)...\n", + dmadone, bdf->ibd_bits.b.b_valid); + udelay (1000000); + } + printf ("DMA complete notification received!\n"); + + done: + DEBUG ("memcmp(0x%08x, 0x%08x, 512) = %d\n", + sbuf, dbuf, memcmp ((void *) sbuf, (void *) dbuf, 512)); + + return; +} + +#define MAX_INT_BUFSZ 64 +#define DCM_WRAP 0 /* MUST be consistant with MAX_INT_BUFSZ */ + +int idma_init (void) +{ + uint memaddr; + + immap->im_cpm.cp_rccr &= ~0x00F3FFFF; + immap->im_cpm.cp_rccr |= 0x00A00A00; + + memaddr = dpalloc (sizeof (pram_idma_t), 64); + + *(volatile ushort *) &immap->im_dprambase[PROFF_IDMA2_BASE] = memaddr; + piptr = (volatile pram_idma_t *) ((uint) (immap) + memaddr); + + piptr->pi_resv1 = 0; /* manual says: clear it */ + piptr->pi_dcmbits.b.b_fb = 0; + piptr->pi_dcmbits.b.b_lp = 1; + piptr->pi_dcmbits.b.b_erm = 0; + piptr->pi_dcmbits.b.b_dt = 0; + + memaddr = (uint) dpalloc (sizeof (ibd_t), 64); + piptr->pi_ibase = piptr->pi_ibdptr = (volatile short) memaddr; + bdf = (volatile ibd_t *) ((uint) (immap) + memaddr); + bdf->ibd_bits.b.b_valid = 0; + + memaddr = (uint) dpalloc (64, 64); + piptr->pi_dprbuf = (volatile ushort) memaddr; + piptr->pi_dcmbits.b.b_wrap = 4; + piptr->pi_ssmax = 32; + + piptr->pi_sts = piptr->pi_ssmax; + piptr->pi_dts = piptr->pi_ssmax; + + return 1; +} + +void dmadone_handler (void *arg) +{ + immap->im_sdma.sdma_idmr2 = (uchar) 0x0; + + *dmadonep = 1; + + return; +} + + +static uint dpbase = 0; + +uint dpalloc (uint size, uint align) +{ + DECLARE_GLOBAL_DATA_PTR; + + volatile immap_t *immr = (immap_t *) CFG_IMMR; + uint retloc; + uint align_mask, off; + uint savebase; + + /* Pointer to initial global data area */ + + if (dpinit_done == 0) { + dpbase = gd->dp_alloc_base; + dpinit_done = 1; + } + + align_mask = align - 1; + savebase = dpbase; + + if ((off = (dpbase & align_mask)) != 0) + dpbase += (align - off); + + if ((off = size & align_mask) != 0) + size += align - off; + + if ((dpbase + size) >= gd->dp_alloc_top) { + dpbase = savebase; + printf ("dpalloc: ran out of dual port ram!"); + return 0; + } + + retloc = dpbase; + dpbase += size; + + memset ((void *) &immr->im_dprambase[retloc], 0, size); + + return (retloc); +} diff --git a/examples/ppc_longjmp.S b/examples/ppc_longjmp.S index ad8285a86b..5ca6f6f3da 100644 --- a/examples/ppc_longjmp.S +++ b/examples/ppc_longjmp.S @@ -30,9 +30,9 @@ #define FP(x...) x #define FP(x...) x -.globl longjmp; +.globl ppc_longjmp; -longjmp: +ppc_longjmp: lwz r1,(JB_GPR1*4)(r3) lwz r2,(JB_GPR2*4)(r3) lwz r0,(JB_LR*4)(r3) diff --git a/examples/ppc_setjmp.S b/examples/ppc_setjmp.S index b718113023..421abfd6eb 100644 --- a/examples/ppc_setjmp.S +++ b/examples/ppc_setjmp.S @@ -34,8 +34,8 @@ setctxsp: mr r1, r3 blr -.globl _setjmp; -_setjmp: +.globl ppc_setjmp; +ppc_setjmp: stw r1,(JB_GPR1*4)(3) mflr r0 stw r2,(JB_GPR2*4)(3) diff --git a/examples/sched.c b/examples/sched.c index 4f6f98e78f..ceb5c1f08e 100644 --- a/examples/sched.c +++ b/examples/sched.c @@ -3,12 +3,12 @@ * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. - * + * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * + * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, @@ -17,7 +17,6 @@ #include <common.h> #include <syscall.h> -#include <setjmp.h> /* * Author: Arun Dharankar <ADharankar@ATTBI.Com> @@ -54,6 +53,13 @@ #define RC_FAILURE (-1) #define RC_SUCCESS (0) +typedef vu_char *jmp_ctx; +unsigned long setctxsp (vu_char *sp); +int ppc_setjmp(jmp_ctx env); +void ppc_longjmp(jmp_ctx env, int val); +#define setjmp ppc_setjmp +#define longjmp ppc_longjmp + struct lthread { int state; int retval; @@ -68,13 +74,13 @@ static volatile int current_tid = MASTER_THREAD; static uchar dbg = 0; -#define DEBUG(fmt, args...) { \ - if(dbg != 0) { \ - mon_printf("[%s %d %s]: ", __FILE__, __LINE__, __FUNCTION__); \ - mon_printf(fmt, ##args); \ - mon_printf("\n"); \ - } \ - } +#define PDEBUG(fmt, args...) { \ + if(dbg != 0) { \ + mon_printf("[%s %d %s]: ",__FILE__,__LINE__,__FUNCTION__);\ + mon_printf(fmt, ##args); \ + mon_printf("\n"); \ + } \ +} static int testthread (void *); static void sched_init (void); @@ -83,14 +89,15 @@ static int thread_start (int id); static void thread_yield (void); static int thread_delete (int id); static int thread_join (int *ret); -#if 0 /* not used yet */ + +#if 0 /* not used yet */ static int thread_stop (int id); -#endif /* not used yet */ +#endif /* not used yet */ /* An example of schedular test */ #define NUMTHREADS 7 -int sched (bd_t *bd, int ac, char *av[]) +int sched (bd_t * bd, int ac, char *av[]) { int i, j; int tid[NUMTHREADS]; @@ -102,11 +109,10 @@ int sched (bd_t *bd, int ac, char *av[]) names[i] = i; j = thread_create (testthread, (void *) &names[i]); if (j == RC_FAILURE) - mon_printf ("schedtest: Failed to create thread %d\n", - i); + mon_printf ("schedtest: Failed to create thread %d\n", i); if (j > 0) { mon_printf ("schedtest: Created thread with id %d, name %d\n", - j, i); + j, i); tid[i] = j; } } @@ -125,8 +131,7 @@ int sched (bd_t *bd, int ac, char *av[]) if (mon_tstc () && mon_getc () == 0x3) { mon_printf ("schedtest: Aborting threads...\n"); for (i = 0; i < NUMTHREADS; i++) { - mon_printf ("schedtest: Deleting thread %d\n", - tid[i]); + mon_printf ("schedtest: Deleting thread %d\n", tid[i]); thread_delete (tid[i]); } return RC_SUCCESS; @@ -135,11 +140,10 @@ int sched (bd_t *bd, int ac, char *av[]) i = thread_join (&j); if (i == RC_FAILURE) { mon_printf ("schedtest: No threads pending, " - "exiting schedular test\n"); + "exiting schedular test\n"); return RC_SUCCESS; } - mon_printf ("schedtest: thread is %d returned %d\n", i, - j); + mon_printf ("schedtest: thread is %d returned %d\n", i, j); thread_yield (); } @@ -151,14 +155,14 @@ static int testthread (void *name) int i; mon_printf ("testthread: Begin executing thread, myname %d, &i=0x%08x\n", - *(int *) name, &i); + *(int *) name, &i); mon_printf ("Thread %02d, i=%d\n", *(int *) name); for (i = 0; i < 0xffff * (*(int *) name + 1); i++) { if (mon_tstc () && mon_getc () == 0x3) { mon_printf ("testthread: myname %d terminating.\n", - *(int *) name); + *(int *) name); return *(int *) name + 1; } @@ -167,7 +171,7 @@ static int testthread (void *name) } mon_printf ("testthread: returning %d, i=0x%x\n", - *(int *) name + 1, i); + *(int *) name + 1, i); return *(int *) name + 1; } @@ -182,8 +186,8 @@ static void sched_init (void) current_tid = MASTER_THREAD; lthreads[current_tid].state = STATE_RUNNABLE; - DEBUG ("sched_init: master context = 0x%08x", - lthreads[current_tid].context); + PDEBUG ("sched_init: master context = 0x%08x", + lthreads[current_tid].context); return; } @@ -191,19 +195,19 @@ static void thread_yield (void) { static int i; - DEBUG ("thread_yield: current tid=%d", current_tid); + PDEBUG ("thread_yield: current tid=%d", current_tid); #define SWITCH(new) \ if(lthreads[new].state == STATE_RUNNABLE) { \ - DEBUG("thread_yield: %d match, ctx=0x%08x", \ + PDEBUG("thread_yield: %d match, ctx=0x%08x", \ new, lthreads[current_tid].context); \ if(setjmp(lthreads[current_tid].context) == 0) { \ current_tid = new; \ - DEBUG("thread_yield: tid %d returns 0", \ + PDEBUG("thread_yield: tid %d returns 0", \ new); \ longjmp(lthreads[new].context, 1); \ } else { \ - DEBUG("thread_yield: tid %d returns 1", \ + PDEBUG("thread_yield: tid %d returns 1", \ new); \ return; \ } \ @@ -219,7 +223,7 @@ static void thread_yield (void) } } - DEBUG ("thread_yield: returning from thread_yield"); + PDEBUG ("thread_yield: returning from thread_yield"); return; } @@ -232,12 +236,12 @@ static int thread_create (int (*func) (void *), void *arg) lthreads[i].state = STATE_STOPPED; lthreads[i].func = func; lthreads[i].arg = arg; - DEBUG ("thread_create: returns new tid %d", i); + PDEBUG ("thread_create: returns new tid %d", i); return i; } } - DEBUG ("thread_create: returns failure"); + PDEBUG ("thread_create: returns failure"); return RC_FAILURE; } @@ -255,13 +259,13 @@ static int thread_delete (int id) static void thread_launcher (void) { - DEBUG ("thread_launcher: invoking func=0x%08x", + PDEBUG ("thread_launcher: invoking func=0x%08x", lthreads[current_tid].func); lthreads[current_tid].retval = - lthreads[current_tid].func(lthreads[current_tid].arg); + lthreads[current_tid].func (lthreads[current_tid].arg); - DEBUG ("thread_launcher: tid %d terminated", current_tid); + PDEBUG ("thread_launcher: tid %d terminated", current_tid); lthreads[current_tid].state = STATE_TERMINATED; thread_yield (); @@ -272,7 +276,7 @@ static void thread_launcher (void) static int thread_start (int id) { - DEBUG ("thread_start: id=%d", id); + PDEBUG ("thread_start: id=%d", id); if (id <= MASTER_THREAD || id > MAX_THREADS) { return RC_FAILURE; } @@ -283,17 +287,17 @@ static int thread_start (int id) if (setjmp (lthreads[current_tid].context) == 0) { lthreads[id].state = STATE_RUNNABLE; current_tid = id; - DEBUG ("thread_start: to be stack=0%08x", lthreads[id].stack); + PDEBUG ("thread_start: to be stack=0%08x", lthreads[id].stack); setctxsp (<hreads[id].stack[STK_SIZE]); thread_launcher (); } - DEBUG ("thread_start: Thread id=%d started, parent returns", id); + PDEBUG ("thread_start: Thread id=%d started, parent returns", id); return RC_SUCCESS; } -#if 0 /* not used so far */ +#if 0 /* not used so far */ static int thread_stop (int id) { if (id <= MASTER_THREAD || id >= MAX_THREADS) @@ -305,46 +309,46 @@ static int thread_stop (int id) lthreads[id].state = STATE_STOPPED; return RC_SUCCESS; } -#endif /* not used so far */ +#endif /* not used so far */ static int thread_join (int *ret) { int i, j = 0; - DEBUG ("thread_join: *ret = %d", *ret); + PDEBUG ("thread_join: *ret = %d", *ret); if (!(*ret == -1 || *ret > MASTER_THREAD || *ret < MAX_THREADS)) { - DEBUG ("thread_join: invalid tid %d", *ret); + PDEBUG ("thread_join: invalid tid %d", *ret); return RC_FAILURE; } if (*ret == -1) { - DEBUG ("Checking for tid = -1"); + PDEBUG ("Checking for tid = -1"); while (1) { - /* DEBUG("thread_join: start while-loopn"); */ + /* PDEBUG("thread_join: start while-loopn"); */ j = 0; for (i = MASTER_THREAD + 1; i < MAX_THREADS; i++) { if (lthreads[i].state == STATE_TERMINATED) { *ret = lthreads[i].retval; lthreads[i].state = STATE_EMPTY; - /* DEBUG("thread_join: returning retval %d of tid %d", - ret, i); */ + /* PDEBUG("thread_join: returning retval %d of tid %d", + ret, i); */ return RC_SUCCESS; } if (lthreads[i].state != STATE_EMPTY) { - DEBUG ("thread_join: %d used slots tid %d state=%d", - j, i, lthreads[i].state); + PDEBUG ("thread_join: %d used slots tid %d state=%d", + j, i, lthreads[i].state); j++; } } if (j == 0) { - DEBUG ("thread_join: all slots empty!"); + PDEBUG ("thread_join: all slots empty!"); return RC_FAILURE; } - /* DEBUG("thread_join: yielding"); */ + /* PDEBUG("thread_join: yielding"); */ thread_yield (); - /* DEBUG("thread_join: back from yield"); */ + /* PDEBUG("thread_join: back from yield"); */ } } @@ -352,10 +356,10 @@ static int thread_join (int *ret) i = *ret; *ret = lthreads[*ret].retval; lthreads[*ret].state = STATE_EMPTY; - DEBUG ("thread_join: returing %d for tid %d", *ret, i); + PDEBUG ("thread_join: returing %d for tid %d", *ret, i); return RC_SUCCESS; } - DEBUG ("thread_join: thread %d is not terminated!", *ret); + PDEBUG ("thread_join: thread %d is not terminated!", *ret); return RC_FAILURE; } diff --git a/include/asm-mips/inca-ip.h b/include/asm-mips/inca-ip.h index dbacb33f80..0c5f1d73cb 100644 --- a/include/asm-mips/inca-ip.h +++ b/include/asm-mips/inca-ip.h @@ -894,7 +894,12 @@ /* Module : EBU register address and bits */ /***********************************************************************/ +#if defined(CONFIG_INCA_IP) #define INCA_IP_EBU (0xB8000200) +#elif defined(CONFIG_PURPLE) +#define INCA_IP_EBU (0xB800D800) +#endif + /***********************************************************************/ @@ -1490,7 +1495,12 @@ If set and clear bit are written concurrently with 1, the associated bit is not /* Module : ASC register address and bits */ /***********************************************************************/ +#if defined(CONFIG_INCA_IP) #define INCA_IP_ASC (0xB8000400) +#elif defined(CONFIG_PURPLE) +#define INCA_IP_ASC (0xBE500000) +#endif + /***********************************************************************/ diff --git a/include/cmd_net.h b/include/cmd_net.h index 2fa848bb68..e9ca5c5bc8 100644 --- a/include/cmd_net.h +++ b/include/cmd_net.h @@ -56,7 +56,7 @@ int do_rarpb (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); #define CMD_TBL_DHCP MK_CMD_TBL_ENTRY( \ "dhcp", 4, 3, 1, do_dhcp, \ "dhcp - invoke DHCP client to obtain IP/boot params\n", \ - "\n" \ + "[loadAddress] [bootfilename]\n" \ ), int do_dhcp (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); diff --git a/include/configs/MIP405.h b/include/configs/MIP405.h index 1dd7f3a4a1..477be52d31 100644 --- a/include/configs/MIP405.h +++ b/include/configs/MIP405.h @@ -109,7 +109,7 @@ #define CONFIG_BOOT_RETRY_TIME -10 /* feature is avaiable but not enabled */ #define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */ -#define CONFIG_BOOTCOMMAND "diskboot 200000 0:1; bootm" /* autoboot command */ +#define CONFIG_BOOTCOMMAND "diskboot 400000 0:1; bootm" /* autoboot command */ #define CONFIG_BOOTARGS "console=ttyS0,9600 root=/dev/hda5" /* boot arguments */ #define CONFIG_IPADDR 10.0.0.100 @@ -162,7 +162,7 @@ { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ 57600, 115200, 230400, 460800, 921600 } -#define CFG_LOAD_ADDR 0x200000 /* default load address */ +#define CFG_LOAD_ADDR 0x400000 /* default load address */ #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ diff --git a/include/configs/PIP405.h b/include/configs/PIP405.h index a5fc8d9aa2..5ecb537be0 100644 --- a/include/configs/PIP405.h +++ b/include/configs/PIP405.h @@ -113,7 +113,7 @@ #define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */ -#define CONFIG_BOOTCOMMAND "diskboot 200000 0:1; bootm" /* autoboot command */ +#define CONFIG_BOOTCOMMAND "diskboot 400000 0:1; bootm" /* autoboot command */ #define CONFIG_BOOTARGS "console=ttyS0,9600 root=/dev/hda5" /* boot arguments */ #define CONFIG_IPADDR 10.0.0.100 @@ -166,7 +166,7 @@ { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ 57600, 115200, 230400, 460800, 921600 } -#define CFG_LOAD_ADDR 0x200000 /* default load address */ +#define CFG_LOAD_ADDR 0x400000 /* default load address */ #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ diff --git a/include/configs/incaip.h b/include/configs/incaip.h index bc0db84e23..3b648c1b57 100644 --- a/include/configs/incaip.h +++ b/include/configs/incaip.h @@ -34,18 +34,60 @@ /* allowed values: 100000000 and 150000000 */ #define CPU_CLOCK_RATE 150000000 /* 150 MHz clock for the MIPS core */ -#define CONFIG_BAUDRATE 115200 +#if CPU_CLOCK_RATE == 100000000 +#define INFINEON_EBU_BOOTCFG 0x20C4 /* CMULT = 4 for 100 MHz */ +#else +#define INFINEON_EBU_BOOTCFG 0x40C4 /* CMULT = 8 for 150 MHz */ +#endif -#define CFG_SDRAM_BASE 0x80000000 -#define CFG_MALLOC_LEN 128*1024 +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#define CFG_BOOTPARAMS_LEN 128*1024 +#define CONFIG_BAUDRATE 115200 /* valid baudrates */ #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_ELF) +#define CONFIG_TIMESTAMP /* Print image info with timestamp */ + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$(serverip):$(rootpath)\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs $(bootargs) " \ + "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ + ":$(hostname):$(netdev):off\0" \ + "addmisc=setenv bootargs $(bootargs) " \ + "console=ttyS0,$(baudrate) " \ + "ethaddr=$(ethaddr) " \ + "panic=1\0" \ + "flash_nfs=run nfsargs addip addmisc;" \ + "bootm $(kernel_addr)\0" \ + "flash_self=run ramargs addip addmisc;" \ + "bootm $(kernel_addr) $(ramdisk_addr)\0" \ + "net_nfs=tftp 80500000 $(bootfile);" \ + "run nfsargs addip addmisc;bootm\0" \ + "rootpath=/opt/eldk/mips_4KC\0" \ + "bootfile=/tftpboot/INCA/uImage\0" \ + "kernel_addr=B0040000\0" \ + "ramdisk_addr=B0100000\0" \ + "u-boot=/tftpboot/INCA/u-boot.bin\0" \ + "load=tftp 80500000 $(u-boot)\0" \ + "update=protect off 1:0-2;era 1:0-2;" \ + "cp.b 80500000 B0000000 $(filesize)\0" \ + "" +#define CONFIG_BOOTCOMMAND "run flash_self" + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DHCP | \ + CFG_CMD_ELF ) #include <cmd_confdefs.h> /* @@ -55,12 +97,19 @@ #define CFG_PROMPT "INCA-IP # " /* Monitor Command Prompt */ #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_HZ (CPU_CLOCK_RATE/2) #define CFG_MAXARGS 16 /* max number of command args*/ +#define CFG_MALLOC_LEN 128*1024 + +#define CFG_BOOTPARAMS_LEN 128*1024 + +#define CFG_HZ (CPU_CLOCK_RATE/2) + +#define CFG_SDRAM_BASE 0x80000000 + #define CFG_LOAD_ADDR 0x80100000 /* default load address */ -#define CFG_MEMTEST_START 0x80200000 +#define CFG_MEMTEST_START 0x80100000 #define CFG_MEMTEST_END 0x80800000 /*----------------------------------------------------------------------- diff --git a/include/configs/innokom.h b/include/configs/innokom.h index c2267bd86d..312c854b67 100644 --- a/include/configs/innokom.h +++ b/include/configs/innokom.h @@ -62,7 +62,8 @@ #define CONFIG_BAUDRATE 19200 #define CONFIG_MISC_INIT_R 1 /* we have a misc_init_r() function */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL|CFG_CMD_I2C|CFG_CMD_EEPROM|CFG_CMD_NET|CFG_CMD_JFFS2|CFG_CMD_DHCP) +#define CONFIG_COMMANDS (CFG_CMD_BDI|CFG_CMD_LOADB|CFG_CMD_IMI|CFG_CMD_FLASH|CFG_CMD_MEMORY|CFG_CMD_NET|CFG_CMD_ENV|CFG_CMD_RUN|CFG_CMD_ASKENV|CFG_CMD_ECHO|CFG_CMD_I2C|CFG_CMD_DHCP) +/* CONFIG_CMD_DFL|CFG_CMD_I2C|CFG_CMD_EEPROM|CFG_CMD_NET|CFG_CMD_JFFS2|CFG_CMD_DHCP) */ /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include <cmd_confdefs.h> @@ -78,11 +79,6 @@ #define CONFIG_CMDLINE_TAG 1 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 19200 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - /* * Miscellaneous configurable options */ @@ -186,7 +182,7 @@ /* - * GPIO settings; see BDI2000 config file for details + * GPIO settings * * GP15 == nCS1 is 1 * GP24 == SFRM is 1 @@ -391,7 +387,7 @@ * [32:26] 0 - reserved * [25] 0 - K2FREE: not free running * [24] 0 - K1FREE: not free running - * [23] 0 - K0FREE: not free running + * [23] 1 - K0FREE: not free running * [22] 0 - SLFRSH: self refresh disabled * [21] 0 - reserved * [20] 0 - APD: no auto power down @@ -401,11 +397,11 @@ * [16] 1 - K1RUN: enable SDCLK1 * [15] 1 - E1PIN: SDRAM clock enable * [14] 1 - K0DB2: SDCLK0 is MemClk - * [13] 1 - K0RUN: disable SDCLK0 + * [13] 0 - K0RUN: disable SDCLK0 * [12] 1 - E0PIN: disable SDCKE0 * [11:00] 000000011000 - (64ms/8192)*MemClkFreq/32 = 24 */ -#define CFG_MDREFR_VAL 0x0001F018 +#define CFG_MDREFR_VAL 0x0081D018 /* MDMRS: Mode Register Set Configuration Register * diff --git a/include/configs/wepep250.h b/include/configs/wepep250.h new file mode 100644 index 0000000000..c88c4ab5ce --- /dev/null +++ b/include/configs/wepep250.h @@ -0,0 +1,188 @@ +/* + * Copyright (C) 2003 ETC s.r.o. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Written by Peter Figuli <peposh@etc.sk>, 2003. + * + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_PXA250 1 /* this is an PXA250 CPU */ +#define CONFIG_WEPEP250 1 /* config for wepep250 board */ +#undef CONFIG_USE_IRQ /* don't need use IRQ/FIQ */ + + +/* + * Select serial console configuration + */ +#define CONFIG_BTUART 1 /* BTUART is default on WEP dev board */ +#define CONFIG_BAUDRATE 115200 + + +/* + * Definition of u-boot build in commands. Check out CONFIG_CMD_DFL if + * neccessary in include/cmd_confdefs.h file. (Un)comment for getting + * functionality or size of u-boot code. + */ +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + & ~CFG_CMD_NET \ + & ~CFG_CMD_LOADS \ + & ~CFG_CMD_CONSOLE \ + & ~CFG_CMD_AUTOSCRIPT \ +/* | CFG_CMD_JFFS2 */ \ + ) +#include <cmd_confdefs.h> + +/* + * Boot options. Setting delay to -1 stops autostart count down. + * NOTE: Sending parameters to kernel depends on kernel version and + * 2.4.19-rmk6-pxa1 patch used while my u-boot coding didn't accept + * parameters at all! Do not get confused by them so. + */ +#define CONFIG_BOOTDELAY -1 +#define CONFIG_BOOTARGS "root=/dev/mtdblock2 mem=32m console=ttyS01,115200n8" +#define CONFIG_BOOTCOMMAND "bootm 40000" + + +/* + * General options for u-boot. Modify to save memory foot print + */ +#define CFG_LONGHELP /* undef saves memory */ +#define CFG_PROMPT "WEP> " /* prompt string */ +#define CFG_CBSIZE 256 /* console I/O buffer */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* print buffer size */ +#define CFG_MAXARGS 16 /* max command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* boot args buf size */ + +#define CFG_MEMTEST_START 0xa0400000 /* memtest test area */ +#define CFG_MEMTEST_END 0xa0800000 + +#undef CFG_CLKS_IN_HZ /* use HZ for freq. display */ + +#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ +#define CFG_CPUSPEED 0x141 /* core clock - register value */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Definitions related to passing arguments to kernel. + */ +#define CONFIG_CMDLINE_TAG 1 /* send commandline to Kernel */ +#define CONFIG_SETUP_MEMORY_TAGS 1 /* send memory definition to kernel */ +#undef CONFIG_INITRD_TAG /* do not send initrd params */ +#undef CONFIG_VFD /* do not send framebuffer setup */ + + +/* + * Malloc pool need to host env + 128 Kb reserve for other allocations. + */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + (128<<10) ) + +#define CONFIG_STACKSIZE (120<<10) /* stack size */ + +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4<<10) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4<<10) /* FIQ stack */ +#endif + +/* + * SDRAM Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of SDRAM */ +#define WEP_SDRAM_1 0xa0000000 /* SDRAM bank #1 */ +#define WEP_SDRAM_1_SIZE 0x02000000 /* 32 MB ( 2 chip ) */ +#define WEP_SDRAM_2 0xa2000000 /* SDRAM bank #2 */ +#define WEP_SDRAM_2_SIZE 0x00000000 /* 0 MB */ +#define WEP_SDRAM_3 0xa8000000 /* SDRAM bank #3 */ +#define WEP_SDRAM_3_SIZE 0x00000000 /* 0 MB */ +#define WEP_SDRAM_4 0xac000000 /* SDRAM bank #4 */ +#define WEP_SDRAM_4_SIZE 0x00000000 /* 0 MB */ + +#define CFG_DRAM_BASE 0xa0000000 +#define CFG_DRAM_SIZE 0x02000000 + +/* Uncomment used SDRAM chip */ +#define WEP_SDRAM_K4S281633 +/*#define WEP_SDRAM_K4S561633*/ + + +/* + * Configuration for FLASH memory + */ +#define CFG_MAX_FLASH_BANKS 1 /* FLASH banks count (not chip count)*/ +#define CFG_MAX_FLASH_SECT 128 /* number of sector in FLASH bank */ +#define WEP_FLASH_BUS_WIDTH 4 /* we use 32 bit FLASH memory... */ +#define WEP_FLASH_INTERLEAVE 2 /* ... made of 2 chips */ +#define WEP_FLASH_BANK_SIZE 0x2000000 /* size of one flash bank*/ +#define WEP_FLASH_SECT_SIZE 0x0040000 /* size of erase sector */ +#define WEP_FLASH_BASE 0x0000000 /* location of flash memory */ +#define WEP_FLASH_UNLOCK 1 /* perform hw unlock first */ + + +/* This should be defined if CFI FLASH device is present. Actually benefit + is not so clear to me. In other words we can provide more informations + to user, but this expects more complex flash handling we do not provide + now.*/ +#undef CFG_FLASH_CFI + +#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* timeout for Erase operation */ +#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* timeout for Write operation */ + +#define CFG_FLASH_BASE WEP_FLASH_BASE + +/* + * This is setting for JFFS2 support in u-boot. + * Right now there is no gain for user, but later on booting kernel might be + * possible. Consider using XIP kernel running from flash to save RAM + * footprint. + * NOTE: Enable CFG_CMD_JFFS2 for JFFS2 support. + */ +#define CFG_JFFS2_FIRST_BANK 0 +#define CFG_JFFS2_FIRST_SECTOR 5 +#define CFG_JFFS2_NUM_BANKS 1 + +/* + * Environment setup. Definitions of monitor location and size with + * definition of environment setup ends up in 2 possibilities. + * 1. Embeded environment - in u-boot code is space for environment + * 2. Environment is read from predefined sector of flash + * Right now we support 2. possiblity, but expecting no env placed + * on mentioned address right now. This also needs to provide whole + * sector for it - for us 256Kb is really waste of memory. U-boot uses + * default env. and until kernel parameters could be sent to kernel + * env. has no sense to us. + */ + +#define CFG_MONITOR_BASE PHYS_FLASH_1 +#define CFG_MONITOR_LEN 0x20000 /* 128kb ( 1 flash sector ) */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR 0x20000 /* absolute address for now */ +#define CFG_ENV_SIZE 0x2000 + +#undef CONFIG_ENV_OVERWRITE /* env is not writable now */ + +/* + * Well this has to be defined, but on the other hand it is used differently + * one may expect. For instance loadb command do not cares :-) + * So advice is - do not relay on this... + */ +#define CFG_LOAD_ADDR 0x40000 + +#endif /* __CONFIG_H */ + diff --git a/lib_arm/board.c b/lib_arm/board.c index 828c2f2054..a725c2425e 100644 --- a/lib_arm/board.c +++ b/lib_arm/board.c @@ -190,6 +190,7 @@ void start_armboot (void) gd_t gd_data; bd_t bd_data; init_fnc_t **init_fnc_ptr; + char *s; #if defined(CONFIG_VFD) unsigned long addr; #endif @@ -274,6 +275,16 @@ void start_armboot (void) cs8900_get_enetaddr (gd->bd->bi_enetaddr); #endif + /* Initialize from environment */ + if ((s = getenv ("loadaddr")) != NULL) { + load_addr = simple_strtoul (s, NULL, 16); + } +#if (CONFIG_COMMANDS & CFG_CMD_NET) + if ((s = getenv ("bootfile")) != NULL) { + copy_filename (BootFile, s, sizeof (BootFile)); + } +#endif /* CFG_CMD_NET */ + #ifdef BOARD_POST_INIT board_post_init (); #endif diff --git a/lib_mips/board.c b/lib_mips/board.c index a07cb3fe4a..4bab3c5855 100644 --- a/lib_mips/board.c +++ b/lib_mips/board.c @@ -177,6 +177,9 @@ void board_init_f(ulong bootflag) bd_t *bd; init_fnc_t **init_fnc_ptr; ulong addr, addr_sp, len = CFG_MONITOR_LEN; +#ifdef CONFIG_PURPLE + void copy_code (ulong); +#endif /* Pointer is writable since we allocated a register for it. */ @@ -271,6 +274,14 @@ void board_init_f(ulong bootflag) bd->bi_baudrate = gd->baudrate; /* Console Baudrate */ memcpy (id, gd, sizeof (gd_t)); + + /* On the purple board we copy the code in a special way + * in order to solve flash problems + */ +#ifdef CONFIG_PURPLE + copy_code(addr); +#endif + relocate_code (addr_sp, id, addr); /* NOTREACHED - relocate_code() does not return */ @@ -383,6 +394,21 @@ void board_init_r (gd_t *id, ulong dest_addr) console_init_r (); /** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** **/ + /* Initialize from environment */ + if ((s = getenv ("loadaddr")) != NULL) { + load_addr = simple_strtoul (s, NULL, 16); + } +#if (CONFIG_COMMANDS & CFG_CMD_NET) + if ((s = getenv ("bootfile")) != NULL) { + copy_filename (BootFile, s, sizeof (BootFile)); + } +#endif /* CFG_CMD_NET */ + +#if defined(CONFIG_MISC_INIT_R) + /* miscellaneous platform dependent initialisations */ + misc_init_r (); +#endif + #if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) puts ("Net: "); eth_initialize(gd->bd); diff --git a/net/bootp.c b/net/bootp.c index ef8cd605b5..ee9656cb3e 100644 --- a/net/bootp.c +++ b/net/bootp.c @@ -59,7 +59,8 @@ unsigned int dhcp_leasetime = 0; static void DhcpHandler(uchar * pkt, unsigned dest, unsigned src, unsigned len); /* For Debug */ -char *dhcpmsg2str(int type) +#if 0 +static char *dhcpmsg2str(int type) { switch (type) { case 1: return "DHCPDISCOVER"; break; @@ -72,6 +73,7 @@ char *dhcpmsg2str(int type) default: return "UNKNOWN/INVALID MSG TYPE"; break; } } +#endif #if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_VENDOREX) extern u8 *dhcp_vendorex_prep (u8 *e); /*rtn new e after add own opts. */ @@ -112,7 +114,7 @@ static int BootpCheckPkt(uchar *pkt, unsigned dest, unsigned src, unsigned len) /* * Copy parameters of interest from BOOTP_REPLY/DHCP_OFFER packet */ -void BootpCopyNetParams(Bootp_t *bp) +static void BootpCopyNetParams(Bootp_t *bp) { NetCopyIP(&NetOurIP, &bp->bp_yiaddr); NetCopyIP(&NetServerIP, &bp->bp_siaddr); @@ -675,9 +677,9 @@ BootpRequest (void) } #if (CONFIG_COMMANDS & CFG_CMD_DHCP) -void DhcpOptionsProcess(char *popt) +static void DhcpOptionsProcess(uchar *popt) { - char *end = popt + BOOTP_HDR_SIZE; + uchar *end = popt + BOOTP_HDR_SIZE; int oplen, size; while ( popt < end && *popt != 0xff ) { @@ -747,7 +749,7 @@ static int DhcpMessageType(unsigned char *popt) return -1; } -void DhcpSendRequestPkt(Bootp_t *bp_offer) +static void DhcpSendRequestPkt(Bootp_t *bp_offer) { volatile uchar *pkt, *iphdr; Bootp_t *bp; @@ -40,6 +40,7 @@ extern int pcnet_initialize(bd_t*); extern int fec_initialize(bd_t*); extern int scc_initialize(bd_t*); extern int inca_switch_initialize(bd_t*); +extern int plb2800_eth_initialize(bd_t*); static struct eth_device *eth_devices, *eth_current; @@ -99,6 +100,9 @@ int eth_initialize(bd_t *bis) #ifdef CONFIG_INCA_IP_SWITCH inca_switch_initialize(bis); #endif +#ifdef CONFIG_PLB2800_ETHER + plb2800_eth_initialize(bis); +#endif #ifdef CONFIG_EEPRO100 eepro100_initialize(bis); #endif diff --git a/tools/Makefile b/tools/Makefile index 41bcc59d16..35c60b6b51 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -25,6 +25,11 @@ BINS = img2srec$(SFX) mkimage$(SFX) envcrc$(SFX) gen_eth_addr$(SFX) bmp_logo$(SF OBJS = environment.o img2srec.o mkimage.o crc32.o envcrc.o gen_eth_addr.o bmp_logo.o +ifeq ($(ARCH),mips) +BINS += inca-swap-bytes$(SFX) +OBJS += inca-swap-bytes.o +endif + LOGO_H = $(TOPDIR)/include/bmp_logo.h ifeq ($(LOGO_BMP),) @@ -133,6 +138,10 @@ bmp_logo$(SFX): bmp_logo.o $(CC) $(CFLAGS) $(HOST_LDFLAGS) -o $@ $^ $(STRIP) $@ +inca-swap-bytes$(SFX): inca-swap-bytes.o + $(CC) $(CFLAGS) $(HOST_LDFLAGS) -o $@ $^ + $(STRIP) $@ + envcrc.o: envcrc.c $(CC) -g $(CFLAGS) -c $< @@ -145,6 +154,9 @@ mkimage.o: mkimage.c gen_eth_addr.o: gen_eth_addr.c $(CC) -g $(CFLAGS) -c $< +inca-swap-bytes.o: inca-swap-bytes.c + $(CC) -g $(CFLAGS) -c $< + subdirs: @for dir in $(TOOLSUBDIRS) ; do \ $(MAKE) \ diff --git a/tools/inca-swap-bytes.c b/tools/inca-swap-bytes.c new file mode 100644 index 0000000000..3a6d82d54a --- /dev/null +++ b/tools/inca-swap-bytes.c @@ -0,0 +1,38 @@ +#include <stdio.h> +#include <stdlib.h> +#include <string.h> +#include <unistd.h> + +#ifndef BUFSIZ +# define BUFSIZ 4096 +#endif + +#undef BUFSIZ +# define BUFSIZ 64 +int main (void) +{ + short ibuff[BUFSIZ], obuff[BUFSIZ]; + int rc, i, len; + + while ((rc = read (0, ibuff, sizeof (ibuff))) > 0) { + memset (obuff, 0, sizeof (obuff)); + for (i = 0; i < (rc + 1) / 2; i++) { + obuff[i] = ibuff[i ^ 1]; + } + + len = (rc + 1) & ~1; + + if (write (1, obuff, len) != len) { + perror ("read error"); + return (EXIT_FAILURE); + } + + memset (ibuff, 0, sizeof (ibuff)); + } + + if (rc < 0) { + perror ("read error"); + return (EXIT_FAILURE); + } + return (EXIT_SUCCESS); +} |