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authorHou Zhiqiang <Zhiqiang.Hou@nxp.com>2019-08-27 11:03:47 +0000
committerPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>2019-08-28 13:47:45 +0530
commit3e89360e115e5aece681f7aec22f40258abc7fa2 (patch)
treee8c147543a92bb0eff742333ffc568449ba7380c
parent4392ddbbbba50df69687a4ea0e043d25c944835f (diff)
t104x: dts: Added PCIe DT nodes
T104x integrated 4 PCIe controllers, which is compatible with the PCI Express™ Base Specification, Revision 2.0, and this patch is to add DT node for each PCIe controller. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
-rw-r--r--arch/powerpc/dts/t104x.dtsi48
1 files changed, 48 insertions, 0 deletions
diff --git a/arch/powerpc/dts/t104x.dtsi b/arch/powerpc/dts/t104x.dtsi
index ff0da9397e..59989677a2 100644
--- a/arch/powerpc/dts/t104x.dtsi
+++ b/arch/powerpc/dts/t104x.dtsi
@@ -59,4 +59,52 @@
clock-frequency = <0x0>;
};
};
+
+ pcie@ffe240000 {
+ compatible = "fsl,pcie-t104x", "fsl,pcie-fsl-qoriq";
+ reg = <0xf 0xfe240000 0x0 0x1000>; /* registers */
+ law_trgt_if = <0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000 /* downstream I/O */
+ 0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x10000000>; /* non-prefetchable memory */
+ };
+
+ pcie@ffe250000 {
+ compatible = "fsl,pcie-t104x", "fsl,pcie-fsl-qoriq";
+ reg = <0xf 0xfe250000 0x0 0x1000>; /* registers */
+ law_trgt_if = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000 /* downstream I/O */
+ 0x02000000 0x0 0xe0000000 0xc 0x10000000 0x0 0x10000000>; /* non-prefetchable memory */
+ };
+
+ pcie@ffe260000 {
+ compatible = "fsl,pcie-t104x", "fsl,pcie-fsl-qoriq";
+ reg = <0xf 0xfe260000 0x0 0x1000>; /* registers */
+ law_trgt_if = <2>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000 /* downstream I/O */
+ 0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x10000000>; /* non-prefetchable memory */
+ };
+
+ pcie@ffe270000 {
+ compatible = "fsl,pcie-t104x", "fsl,pcie-fsl-qoriq";
+ reg = <0xf 0xfe270000 0x0 0x1000>; /* registers */
+ law_trgt_if = <3>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x01000000 0x0 0x00000000 0xf 0xf8030000 0x0 0x00010000 /* downstream I/O */
+ 0x02000000 0x0 0xe0000000 0xc 0x30000000 0x0 0x10000000>; /* non-prefetchable memory */
+ };
};