diff options
| author | Wadim Egorov <w.egorov@phytec.de> | 2017-08-21 13:36:57 +0200 |
|---|---|---|
| committer | Philipp Tomsich <philipp.tomsich@theobroma-systems.com> | 2017-09-05 11:04:35 +0200 |
| commit | 40d4f79b819588751a07a01c40bab5173f4e5a73 (patch) | |
| tree | 8060696b90c3a3b71ead285a44fca415ea6426f2 | |
| parent | 32191a3912018b2dd3645cfe9c52ae3eb1031e30 (diff) | |
rockchip: rk3288: Add reset reason detection
Sometimes it's helpful to know the reset reason caused in the SoC.
Add reset reason detection for the RK3288 SoC.
This will set an environment variable which represents the reset reason.
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| -rw-r--r-- | arch/arm/include/asm/arch-rockchip/cru_rk3288.h | 12 | ||||
| -rw-r--r-- | arch/arm/mach-rockchip/rk3288-board.c | 39 |
2 files changed, 51 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3288.h b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h index c7e21bd605..79a6d6db80 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rk3288.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h @@ -220,4 +220,16 @@ enum { CLKF_MASK = 0x1fff << CLKF_SHIFT, }; +/* CRU_GLB_RST_ST */ +enum { + GLB_POR_RST, + FST_GLB_RST_ST = BIT(0), + SND_GLB_RST_ST = BIT(1), + FST_GLB_TSADC_RST_ST = BIT(2), + SND_GLB_TSADC_RST_ST = BIT(3), + FST_GLB_WDT_RST_ST = BIT(4), + SND_GLB_WDT_RST_ST = BIT(5), + GLB_RST_ST_MASK = GENMASK(5, 0), +}; + #endif diff --git a/arch/arm/mach-rockchip/rk3288-board.c b/arch/arm/mach-rockchip/rk3288-board.c index 74c6cc14a1..278bb406f0 100644 --- a/arch/arm/mach-rockchip/rk3288-board.c +++ b/arch/arm/mach-rockchip/rk3288-board.c @@ -11,6 +11,7 @@ #include <syscon.h> #include <asm/io.h> #include <asm/arch/clock.h> +#include <asm/arch/cru_rk3288.h> #include <asm/arch/periph.h> #include <asm/arch/pmu_rk3288.h> #include <asm/arch/qos_rk3288.h> @@ -70,10 +71,48 @@ int rk3288_qos_init(void) return 0; } +static void rk3288_detect_reset_reason(void) +{ + struct rk3288_cru *cru = rockchip_get_cru(); + const char *reason; + + if (IS_ERR(cru)) + return; + + switch (cru->cru_glb_rst_st) { + case GLB_POR_RST: + reason = "POR"; + break; + case FST_GLB_RST_ST: + case SND_GLB_RST_ST: + reason = "RST"; + break; + case FST_GLB_TSADC_RST_ST: + case SND_GLB_TSADC_RST_ST: + reason = "THERMAL"; + break; + case FST_GLB_WDT_RST_ST: + case SND_GLB_WDT_RST_ST: + reason = "WDOG"; + break; + default: + reason = "unknown reset"; + } + + env_set("reset_reason", reason); + + /* + * Clear cru_glb_rst_st, so we can determine the last reset cause + * for following resets. + */ + rk_clrreg(&cru->cru_glb_rst_st, GLB_RST_ST_MASK); +} + int board_late_init(void) { setup_boot_mode(); rk3288_qos_init(); + rk3288_detect_reset_reason(); return rk_board_late_init(); } |