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authorYork Sun <york.sun@nxp.com>2017-09-08 09:33:49 -0700
committerYork Sun <york.sun@nxp.com>2017-09-11 08:02:13 -0700
commit42f43aa25876d1c77002ee5f333ab36dcb01d719 (patch)
tree5841dcef0e5745e02dd16b8f9c9fe89c541e2d92
parent4950eb4a48623d8ad013c1f37097906ec52040d1 (diff)
armv8: fsl-layerscape: Add back L3 flushing for all exception levels
CCN-504 HPF registers were believed to be accessible only from EL3. However, recent tests proved otherwise. Remove checking for exception level to re-enable L3 cache flushing for all levels. Signed-off-by: York Sun <york.sun@nxp.com> Tested-by: Zhao Qiang <qiang.zhao@nxp.com>
-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S4
1 files changed, 0 insertions, 4 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
index 5ff01a0e1b..fa93096c68 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
+++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
@@ -396,9 +396,6 @@ ENTRY(__asm_flush_l3_dcache)
mov x29, lr
mov x8, #0
- switch_el x0, 1f, 100f, 100f /* skip if not in EL3 */
-
-1:
dsb sy
mov x0, #0x1 /* HNFPSTAT_SFONLY */
bl hnf_set_pstate
@@ -416,7 +413,6 @@ ENTRY(__asm_flush_l3_dcache)
bl hnf_pstate_poll
cbz x0, 1f
add x8, x8, #0x2
-100:
1:
mov x0, x8
mov lr, x29