drivers/misc: Share qbman init between archs

This patch adds changes necessary to move functionality present in
PowerPC folders with ARM architectures that have DPAA1 QBMan hardware

- Create new board/freescale/common/fsl_portals.c to house shared
  device tree fixups for DPAA1 devices with ARM and PowerPC cores
- Add new header file to top includes directory to allow files in
  both architectures to grab the function prototypes
- Port inhibit_portals() from PowerPC to ARM. This function is used in
  setup to disable interrupts on all QMan and BMan portals. It is
  needed because the interrupts are enabled by default for all portals
  including unused/uninitialised portals. When the kernel attempts to
  go to deep sleep the unused portals prevent it from doing so

Signed-off-by: Ahmed Mansour <ahmed.mansour@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

18 files changed, 454 insertions, 351 deletions

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 00d2564c79..1e0030cbfb 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -30,6 +30,7 @@
 #endif
 #include <asm/arch/clock.h>
 #include <hwconfig.h>
+#include <fsl_qbman.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -565,6 +566,9 @@ int arch_early_init_r(void)
 #ifdef CONFIG_FMAN_ENET
 	fman_enet_init();
 #endif
+#ifdef CONFIG_SYS_DPAA_QBMAN
+	setup_qbman_portals();
+#endif
 	return 0;
 }
 
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
index 39ffe1ab4d..80af318822 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
@@ -26,6 +26,8 @@
 #ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
 #include <asm/armv8/sec_firmware.h>
 #endif
+#include <asm/arch/speed.h>
+#include <fsl_qbman.h>
 
 int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc)
 {
@@ -442,6 +444,13 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 	fdt_fixup_esdhc(blob, bd);
 #endif
 
+#ifdef CONFIG_SYS_DPAA_QBMAN
+	fdt_fixup_bportals(blob);
+	fdt_fixup_qportals(blob);
+	do_fixup_by_compat_u32(blob, "fsl,qman",
+			       "clock-frequency", get_qman_freq(), 1);
+#endif
+
 #ifdef CONFIG_SYS_DPAA_FMAN
 	fdt_fixup_fman_firmware(blob);
 #endif
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
index 2d7775e54f..5f23aadc2c 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
@@ -155,8 +155,22 @@ void get_sys_info(struct sys_info *sys_info)
 	sys_info->freq_localbus = sys_info->freq_systembus /
 						CONFIG_SYS_FSL_IFC_CLK_DIV;
 #endif
+#ifdef CONFIG_SYS_DPAA_QBMAN
+	sys_info->freq_qman = sys_info->freq_systembus;
+#endif
 }
 
+#ifdef CONFIG_SYS_DPAA_QBMAN
+unsigned long get_qman_freq(void)
+{
+	struct sys_info sys_info;
+
+	get_sys_info(&sys_info);
+
+	return sys_info.freq_qman;
+}
+#endif
+
 int get_clocks(void)
 {
 	struct sys_info sys_info;
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 2561ead7c3..1ff5cac344 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -23,6 +23,8 @@
 #define CONFIG_SYS_FSL_GUTS_ADDR		(CONFIG_SYS_IMMR + 0x00ee0000)
 #define CONFIG_SYS_FSL_RST_ADDR			(CONFIG_SYS_IMMR + 0x00ee00b0)
 #define CONFIG_SYS_FSL_SCFG_ADDR		(CONFIG_SYS_IMMR + 0x00570000)
+#define CONFIG_SYS_FSL_BMAN_ADDR		(CONFIG_SYS_IMMR + 0x00890000)
+#define CONFIG_SYS_FSL_QMAN_ADDR		(CONFIG_SYS_IMMR + 0x00880000)
 #define CONFIG_SYS_FSL_FMAN_ADDR		(CONFIG_SYS_IMMR + 0x00a00000)
 #define CONFIG_SYS_FSL_SERDES_ADDR		(CONFIG_SYS_IMMR + 0x00ea0000)
 #define CONFIG_SYS_FSL_DCFG_ADDR		(CONFIG_SYS_IMMR + 0x00ee0000)
@@ -41,6 +43,33 @@
 #define CONFIG_SYS_SEC_MON_ADDR			(CONFIG_SYS_IMMR + 0xe90000)
 #define CONFIG_SYS_SFP_ADDR			(CONFIG_SYS_IMMR + 0xe80200)
 
+#define CONFIG_SYS_BMAN_NUM_PORTALS	10
+#define CONFIG_SYS_BMAN_MEM_BASE	0x508000000
+#define CONFIG_SYS_BMAN_MEM_PHYS	(0xf00000000ull + \
+						CONFIG_SYS_BMAN_MEM_BASE)
+#define CONFIG_SYS_BMAN_MEM_SIZE	0x08000000
+#define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x10000
+#define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x10000
+#define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
+#define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
+					CONFIG_SYS_BMAN_CENA_SIZE)
+#define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_BMAN_SWP_ISDR_REG    0x3E80
+#define CONFIG_SYS_QMAN_NUM_PORTALS	10
+#define CONFIG_SYS_QMAN_MEM_BASE	0x500000000
+#define CONFIG_SYS_QMAN_MEM_PHYS	(0xf00000000ull + \
+						CONFIG_SYS_QMAN_MEM_BASE)
+#define CONFIG_SYS_QMAN_MEM_SIZE	0x08000000
+#define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x10000
+#define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x10000
+#define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
+#define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
+					CONFIG_SYS_QMAN_CENA_SIZE)
+#define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_QMAN_SWP_ISDR_REG	0x3680
+
 #define CONFIG_SYS_FSL_TIMER_ADDR		0x02b00000
 
 #define I2C1_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01180000)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/speed.h b/arch/arm/include/asm/arch-fsl-layerscape/speed.h
index de795f6056..e94fe8e254 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/speed.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/speed.h
@@ -7,4 +7,7 @@
 #ifndef _FSL_LAYERSCAPE_SPEED_H
 #define _FSL_LAYERSCAPE_SPEED_H
 void get_sys_info(struct sys_info *sys_info);
+#ifdef CONFIG_SYS_DPAA_QBMAN
+unsigned long get_qman_freq(void);
+#endif
 #endif /* _FSL_LAYERSCAPE_SPEED_H */
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index ea46e49853..b350bfeb06 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -26,6 +26,7 @@
 #ifdef CONFIG_FSL_CORENET
 #include <asm/fsl_portals.h>
 #include <asm/fsl_liodn.h>
+#include <fsl_qbman.h>
 #endif
 #include <fsl_usb.h>
 #include <hwconfig.h>
@@ -804,7 +805,7 @@ int cpu_init_r(void)
 #ifdef CONFIG_FSL_CORENET
 	set_liodns();
 #ifdef CONFIG_SYS_DPAA_QBMAN
-	setup_portals();
+	setup_qbman_portals();
 #endif
 #endif
 
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index 297dc4af48..1159f06ee3 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -15,6 +15,7 @@
 #include <asm/io.h>
 #include <asm/fsl_fdt.h>
 #include <asm/fsl_portals.h>
+#include <fsl_qbman.h>
 #include <hwconfig.h>
 #ifdef CONFIG_FSL_ESDHC
 #include <fsl_esdhc.h>
diff --git a/arch/powerpc/cpu/mpc85xx/portals.c b/arch/powerpc/cpu/mpc85xx/portals.c
index 3777c6faa1..b298d11b9d 100644
--- a/arch/powerpc/cpu/mpc85xx/portals.c
+++ b/arch/powerpc/cpu/mpc85xx/portals.c
@@ -14,75 +14,6 @@
 #include <asm/fsl_portals.h>
 #include <asm/fsl_liodn.h>
 
-#define MAX_BPORTALS (CONFIG_SYS_BMAN_CINH_SIZE / CONFIG_SYS_BMAN_SP_CINH_SIZE)
-#define MAX_QPORTALS (CONFIG_SYS_QMAN_CINH_SIZE / CONFIG_SYS_QMAN_SP_CINH_SIZE)
-static void inhibit_portals(void __iomem *addr, int max_portals,
-			int arch_max_portals, int portal_cinh_size)
-{
-	uint32_t val;
-	int i;
-
-	/* arch_max_portals is the maximum based on memory size. This includes
-	 * the reserved memory in the SoC.  max_portals the number of physical
-	 * portals in the SoC */
-	if (max_portals > arch_max_portals) {
-		printf("ERROR: portal config error\n");
-		max_portals = arch_max_portals;
-	}
-
-	for (i = 0; i < max_portals; i++) {
-		out_be32(addr, -1);
-		val = in_be32(addr);
-		if (!val) {
-			printf("ERROR: Stopped after %d portals\n", i);
-			goto done;
-		}
-		addr += portal_cinh_size;
-	}
-#ifdef DEBUG
-	printf("Cleared %d portals\n", i);
-#endif
-done:
-
-	return;
-}
-
-void setup_portals(void)
-{
-	ccsr_qman_t *qman = (void *)CONFIG_SYS_FSL_QMAN_ADDR;
-	void __iomem *bpaddr = (void *)CONFIG_SYS_BMAN_CINH_BASE +
-				CONFIG_SYS_BMAN_SWP_ISDR_REG;
-	void __iomem *qpaddr = (void *)CONFIG_SYS_QMAN_CINH_BASE +
-				CONFIG_SYS_QMAN_SWP_ISDR_REG;
-#ifdef CONFIG_FSL_CORENET
-	int i;
-
-	for (i = 0; i < CONFIG_SYS_QMAN_NUM_PORTALS; i++) {
-		u8 sdest = qp_info[i].sdest;
-		u16 fliodn = qp_info[i].fliodn;
-		u16 dliodn = qp_info[i].dliodn;
-		u16 liodn_off = qp_info[i].liodn_offset;
-
-		out_be32(&qman->qcsp[i].qcsp_lio_cfg, (liodn_off << 16) |
-					dliodn);
-		/* set frame liodn */
-		out_be32(&qman->qcsp[i].qcsp_io_cfg, (sdest << 16) | fliodn);
-	}
-#endif
-
-	/* Set the Qman initiator BAR to match the LAW (for DQRR stashing) */
-#ifdef CONFIG_PHYS_64BIT
-	out_be32(&qman->qcsp_bare, (u32)(CONFIG_SYS_QMAN_MEM_PHYS >> 32));
-#endif
-	out_be32(&qman->qcsp_bar, (u32)CONFIG_SYS_QMAN_MEM_PHYS);
-
-	/* Change default state of BMan ISDR portals to all 1s */
-	inhibit_portals(bpaddr, CONFIG_SYS_BMAN_NUM_PORTALS, MAX_BPORTALS,
-			CONFIG_SYS_BMAN_SP_CINH_SIZE);
-	inhibit_portals(qpaddr, CONFIG_SYS_QMAN_NUM_PORTALS, MAX_QPORTALS,
-			CONFIG_SYS_QMAN_SP_CINH_SIZE);
-}
-
 /* Update portal containter to match LAW setup of portal in phy map */
 void fdt_portal(void *blob, const char *compat, const char *container,
 			u64 addr, u32 size)
@@ -142,215 +73,3 @@ void fdt_portal(void *blob, const char *compat, const char *container,
 
 	printf("ERROR: %s isn't in a container.  Not supported\n", compat);
 }
-
-static int fdt_qportal(void *blob, int off, int id, char *name,
-		       enum fsl_dpaa_dev dev, int create)
-{
-	int childoff, dev_off, ret = 0;
-	uint32_t dev_handle;
-#ifdef CONFIG_FSL_CORENET
-	int num;
-	u32 liodns[2];
-#endif
-
-	childoff = fdt_subnode_offset(blob, off, name);
-	if (create) {
-		char handle[64], *p;
-
-		strncpy(handle, name, sizeof(handle));
-		p = strchr(handle, '@');
-		if (!strncmp(name, "fman", 4)) {
-			*p = *(p + 1);
-			p++;
-		}
-		*p = '\0';
-
-		dev_off = fdt_path_offset(blob, handle);
-		/* skip this node if alias is not found */
-		if (dev_off == -FDT_ERR_BADPATH)
-			return 0;
-		if (dev_off < 0)
-			return dev_off;
-
-		if (childoff <= 0)
-			childoff = fdt_add_subnode(blob, off, name);
-
-		/* need to update the dev_off after adding a subnode */
-		dev_off = fdt_path_offset(blob, handle);
-		if (dev_off < 0)
-			return dev_off;
-
-		if (childoff > 0) {
-			dev_handle = fdt_get_phandle(blob, dev_off);
-			if (dev_handle <= 0) {
-				dev_handle = fdt_alloc_phandle(blob);
-				ret = fdt_set_phandle(blob, dev_off,
-							 dev_handle);
-				if (ret < 0)
-					return ret;
-			}
-
-			ret = fdt_setprop(blob, childoff, "dev-handle",
-					  &dev_handle, sizeof(dev_handle));
-			if (ret < 0)
-				return ret;
-
-#ifdef CONFIG_FSL_CORENET
-			num = get_dpaa_liodn(dev, &liodns[0], id);
-			ret = fdt_setprop(blob, childoff, "fsl,liodn",
-					  &liodns[0], sizeof(u32) * num);
-			if (!strncmp(name, "pme", 3)) {
-				u32 pme_rev1, pme_rev2;
-				ccsr_pme_t *pme_regs =
-					(void *)CONFIG_SYS_FSL_CORENET_PME_ADDR;
-
-				pme_rev1 = in_be32(&pme_regs->pm_ip_rev_1);
-				pme_rev2 = in_be32(&pme_regs->pm_ip_rev_2);
-				ret = fdt_setprop(blob, childoff,
-					"fsl,pme-rev1", &pme_rev1, sizeof(u32));
-				if (ret < 0)
-					return ret;
-				ret = fdt_setprop(blob, childoff,
-					"fsl,pme-rev2", &pme_rev2, sizeof(u32));
-			}
-#endif
-		} else {
-			return childoff;
-		}
-	} else {
-		if (childoff > 0)
-			ret = fdt_del_node(blob, childoff);
-	}
-
-	return ret;
-}
-
-void fdt_fixup_qportals(void *blob)
-{
-	int off, err;
-	unsigned int maj, min;
-	unsigned int ip_cfg;
-	ccsr_qman_t *qman = (void *)CONFIG_SYS_FSL_QMAN_ADDR;
-	u32 rev_1 = in_be32(&qman->ip_rev_1);
-	u32 rev_2 = in_be32(&qman->ip_rev_2);
-	char compat[64];
-	int compat_len;
-
-	maj = (rev_1 >> 8) & 0xff;
-	min = rev_1 & 0xff;
-	ip_cfg = rev_2 & 0xff;
-
-	compat_len = sprintf(compat, "fsl,qman-portal-%u.%u.%u",
-					maj, min, ip_cfg) + 1;
-	compat_len += sprintf(compat + compat_len, "fsl,qman-portal") + 1;
-
-	off = fdt_node_offset_by_compatible(blob, -1, "fsl,qman-portal");
-	while (off != -FDT_ERR_NOTFOUND) {
-#ifdef CONFIG_FSL_CORENET
-		u32 liodns[2];
-#endif
-		const int *ci = fdt_getprop(blob, off, "cell-index", &err);
-		int i;
-
-		if (!ci)
-			goto err;
-
-		i = *ci;
-#ifdef CONFIG_SYS_DPAA_FMAN
-		int j;
-#endif
-
-		err = fdt_setprop(blob, off, "compatible", compat, compat_len);
-		if (err < 0)
-			goto err;
-
-#ifdef CONFIG_FSL_CORENET
-		liodns[0] = qp_info[i].dliodn;
-		liodns[1] = qp_info[i].fliodn;
-
-		err = fdt_setprop(blob, off, "fsl,liodn",
-				  &liodns, sizeof(u32) * 2);
-		if (err < 0)
-			goto err;
-#endif
-
-		i++;
-
-		err = fdt_qportal(blob, off, i, "crypto@0", FSL_HW_PORTAL_SEC,
-				  IS_E_PROCESSOR(get_svr()));
-		if (err < 0)
-			goto err;
-
-#ifdef CONFIG_FSL_CORENET
-#ifdef CONFIG_SYS_DPAA_PME
-		err = fdt_qportal(blob, off, i, "pme@0", FSL_HW_PORTAL_PME, 1);
-		if (err < 0)
-			goto err;
-#else
-		fdt_qportal(blob, off, i, "pme@0", FSL_HW_PORTAL_PME, 0);
-#endif
-#endif
-
-#ifdef CONFIG_SYS_DPAA_FMAN
-		for (j = 0; j < CONFIG_SYS_NUM_FMAN; j++) {
-			char name[] = "fman@0";
-
-			name[sizeof(name) - 2] = '0' + j;
-			err = fdt_qportal(blob, off, i, name,
-					  FSL_HW_PORTAL_FMAN1 + j, 1);
-			if (err < 0)
-				goto err;
-		}
-#endif
-#ifdef CONFIG_SYS_DPAA_RMAN
-		err = fdt_qportal(blob, off, i, "rman@0",
-				  FSL_HW_PORTAL_RMAN, 1);
-		if (err < 0)
-			goto err;
-#endif
-
-err:
-		if (err < 0) {
-			printf("ERROR: unable to create props for %s: %s\n",
-				fdt_get_name(blob, off, NULL), fdt_strerror(err));
-			return;
-		}
-
-		off = fdt_node_offset_by_compatible(blob, off, "fsl,qman-portal");
-	}
-}
-
-void fdt_fixup_bportals(void *blob)
-{
-	int off, err;
-	unsigned int maj, min;
-	unsigned int ip_cfg;
-	ccsr_bman_t *bman = (void *)CONFIG_SYS_FSL_BMAN_ADDR;
-	u32 rev_1 = in_be32(&bman->ip_rev_1);
-	u32 rev_2 = in_be32(&bman->ip_rev_2);
-	char compat[64];
-	int compat_len;
-
-	maj = (rev_1 >> 8) & 0xff;
-	min = rev_1 & 0xff;
-
-	ip_cfg = rev_2 & 0xff;
-
-	compat_len = sprintf(compat, "fsl,bman-portal-%u.%u.%u",
-				 maj, min, ip_cfg) + 1;
-	compat_len += sprintf(compat + compat_len, "fsl,bman-portal") + 1;
-
-	off = fdt_node_offset_by_compatible(blob, -1, "fsl,bman-portal");
-	while (off != -FDT_ERR_NOTFOUND) {
-		err = fdt_setprop(blob, off, "compatible", compat, compat_len);
-		if (err < 0) {
-			printf("ERROR: unable to create props for %s: %s\n",
-				fdt_get_name(blob, off, NULL),
-						 fdt_strerror(err));
-			return;
-		}
-
-		off = fdt_node_offset_by_compatible(blob, off, "fsl,bman-portal");
-	}
-
-}
diff --git a/arch/powerpc/include/asm/fsl_liodn.h b/arch/powerpc/include/asm/fsl_liodn.h
index 8c91e722f4..0ccb79c7e7 100644
--- a/arch/powerpc/include/asm/fsl_liodn.h
+++ b/arch/powerpc/include/asm/fsl_liodn.h
@@ -8,6 +8,7 @@
 #define _FSL_LIODN_H_
 
 #include <asm/types.h>
+#include <fsl_qbman.h>
 
 struct srio_liodn_id_table {
 	u32 id[2];
@@ -128,12 +129,14 @@ extern void fdt_fixup_liodn(void *blob);
 		CONFIG_SYS_MPC85xx_TDM_OFFSET)
 
 #define SET_QMAN_LIODN(liodn) \
-	SET_LIODN_ENTRY_1("fsl,qman", liodn, offsetof(ccsr_qman_t, liodnr) + \
+	SET_LIODN_ENTRY_1("fsl,qman", liodn, \
+		offsetof(struct ccsr_qman, liodnr) + \
 		CONFIG_SYS_FSL_QMAN_OFFSET, \
 		CONFIG_SYS_FSL_QMAN_OFFSET)
 
 #define SET_BMAN_LIODN(liodn) \
-	SET_LIODN_ENTRY_1("fsl,bman", liodn, offsetof(ccsr_bman_t, liodnr) + \
+	SET_LIODN_ENTRY_1("fsl,bman", liodn, \
+		offsetof(struct ccsr_bman, liodnr) + \
 		CONFIG_SYS_FSL_BMAN_OFFSET, \
 		CONFIG_SYS_FSL_BMAN_OFFSET)
 
diff --git a/arch/powerpc/include/asm/fsl_portals.h b/arch/powerpc/include/asm/fsl_portals.h
index f13ba14579..10d459e2bc 100644
--- a/arch/powerpc/include/asm/fsl_portals.h
+++ b/arch/powerpc/include/asm/fsl_portals.h
@@ -41,10 +41,6 @@ struct qportal_info {
 
 extern int get_dpaa_liodn(enum fsl_dpaa_dev dpaa_dev,
 			  u32 *liodns, int liodn_offset);
-extern void setup_portals(void);
-extern void fdt_fixup_qportals(void *blob);
-extern void fdt_fixup_bportals(void *blob);
-
 extern struct qportal_info qp_info[];
 extern void fdt_portal(void *blob, const char *compat, const char *container,
 			u64 addr, u32 size);
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index ee537f4ac9..841f3d95c1 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -2702,66 +2702,6 @@ enum {
 	FSL_SRDS_B3_LANE_D = 23,
 };
 
-typedef struct ccsr_qman {
-#ifdef CONFIG_SYS_FSL_QMAN_V3
-	u8	res0[0x200];
-#else
-	struct {
-		u32	qcsp_lio_cfg;	/* 0x0 - SW Portal n LIO cfg */
-		u32	qcsp_io_cfg;	/* 0x4 - SW Portal n IO cfg */
-		u32	res;
-		u32	qcsp_dd_cfg;	/* 0xc - SW Portal n Dynamic Debug cfg */
-	} qcsp[32];
-#endif
-	/* Not actually reserved, but irrelevant to u-boot */
-	u8	res[0xbf8 - 0x200];
-	u32	ip_rev_1;
-	u32	ip_rev_2;
-	u32	fqd_bare;	/* FQD Extended Base Addr Register */
-	u32	fqd_bar;	/* FQD Base Addr Register */
-	u8	res1[0x8];
-	u32	fqd_ar;		/* FQD Attributes Register */
-	u8	res2[0xc];
-	u32	pfdr_bare;	/* PFDR Extended Base Addr Register */
-	u32	pfdr_bar;	/* PFDR Base Addr Register */
-	u8	res3[0x8];
-	u32	pfdr_ar;	/* PFDR Attributes Register */
-	u8	res4[0x4c];
-	u32	qcsp_bare;	/* QCSP Extended Base Addr Register */
-	u32	qcsp_bar;	/* QCSP Base Addr Register */
-	u8	res5[0x78];
-	u32	ci_sched_cfg;	/* Initiator Scheduling Configuration */
-	u32	srcidr;		/* Source ID Register */
-	u32	liodnr;		/* LIODN Register */
-	u8	res6[4];
-	u32	ci_rlm_cfg;	/* Initiator Read Latency Monitor Cfg */
-	u32	ci_rlm_avg;	/* Initiator Read Latency Monitor Avg */
-	u8	res7[0x2e8];
-#ifdef CONFIG_SYS_FSL_QMAN_V3
-	struct {
-		u32	qcsp_lio_cfg;	/* 0x0 - SW Portal n LIO cfg */
-		u32	qcsp_io_cfg;	/* 0x4 - SW Portal n IO cfg */
-		u32	res;
-		u32	qcsp_dd_cfg;	/* 0xc - SW Portal n Dynamic Debug cfg*/
-	} qcsp[50];
-#endif
-} ccsr_qman_t;
-
-typedef struct ccsr_bman {
-	/* Not actually reserved, but irrelevant to u-boot */
-	u8	res[0xbf8];
-	u32	ip_rev_1;
-	u32	ip_rev_2;
-	u32	fbpr_bare;	/* FBPR Extended Base Addr Register */
-	u32	fbpr_bar;	/* FBPR Base Addr Register */
-	u8	res1[0x8];
-	u32	fbpr_ar;	/* FBPR Attributes Register */
-	u8	res2[0xf0];
-	u32	srcidr;		/* Source ID Register */
-	u32	liodnr;		/* LIODN Register */
-	u8	res7[0x2f4];
-} ccsr_bman_t;
-
 typedef struct ccsr_pme {
 	u8	res0[0x804];
 	u32	liodnbr;	/* LIODN Base Register */
diff --git a/board/freescale/p1023rdb/p1023rdb.c b/board/freescale/p1023rdb/p1023rdb.c
index ccda824125..a23a5d5078 100644
--- a/board/freescale/p1023rdb/p1023rdb.c
+++ b/board/freescale/p1023rdb/p1023rdb.c
@@ -18,6 +18,7 @@
 #include <asm/fsl_pci.h>
 #include <fsl_ddr_sdram.h>
 #include <asm/fsl_portals.h>
+#include <fsl_qbman.h>
 #include <libfdt.h>
 #include <fdt_support.h>
 #include <netdev.h>
@@ -81,7 +82,7 @@ int board_early_init_r(void)
 		MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		0, flash_esel, BOOKE_PAGESZ_256M, 1);
 
-	setup_portals();
+	setup_qbman_portals();
 
 	return 0;
 }
diff --git a/board/keymile/kmp204x/kmp204x.c b/board/keymile/kmp204x/kmp204x.c
index 8c9d6b167d..d70b1d1393 100644
--- a/board/keymile/kmp204x/kmp204x.c
+++ b/board/keymile/kmp204x/kmp204x.c
@@ -126,7 +126,7 @@ int board_early_init_r(void)
 	invalidate_icache();
 
 	set_liodns();
-	setup_portals();
+	setup_qbman_portals();
 
 	ret = trigger_fpga_config();
 	if (ret)
diff --git a/board/varisys/cyrus/cyrus.c b/board/varisys/cyrus/cyrus.c
index 30f518abe8..f4586272b1 100644
--- a/board/varisys/cyrus/cyrus.c
+++ b/board/varisys/cyrus/cyrus.c
@@ -69,7 +69,7 @@ int board_early_init_r(void)
 	set_liodns();
 
 #ifdef CONFIG_SYS_DPAA_QBMAN
-	setup_portals();
+	setup_qbman_portals();
 #endif
 	print_lbc_regs();
 	return 0;
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index ada7624417..e8d598cd47 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -53,3 +53,4 @@ obj-$(CONFIG_WINBOND_W83627) += winbond_w83627.o
 obj-$(CONFIG_QFW) += qfw.o
 obj-$(CONFIG_ROCKCHIP_EFUSE) += rockchip-efuse.o
 obj-$(CONFIG_STM32_RCC) += stm32_rcc.o
+obj-$(CONFIG_SYS_DPAA_QBMAN) += fsl_portals.o
diff --git a/drivers/misc/fsl_portals.c b/drivers/misc/fsl_portals.c
new file mode 100644
index 0000000000..3b3dd023bb
--- /dev/null
+++ b/drivers/misc/fsl_portals.c
@@ -0,0 +1,305 @@
+/*
+ * Copyright 2008-2011 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+
+#include <asm/processor.h>
+#include <asm/io.h>
+#ifdef CONFIG_PPC
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+#endif
+#include <fsl_qbman.h>
+
+#define MAX_BPORTALS (CONFIG_SYS_BMAN_CINH_SIZE / CONFIG_SYS_BMAN_SP_CINH_SIZE)
+#define MAX_QPORTALS (CONFIG_SYS_QMAN_CINH_SIZE / CONFIG_SYS_QMAN_SP_CINH_SIZE)
+void setup_qbman_portals(void)
+{
+	void __iomem *bpaddr = (void *)CONFIG_SYS_BMAN_CINH_BASE +
+				CONFIG_SYS_BMAN_SWP_ISDR_REG;
+	void __iomem *qpaddr = (void *)CONFIG_SYS_QMAN_CINH_BASE +
+				CONFIG_SYS_QMAN_SWP_ISDR_REG;
+#ifdef CONFIG_PPC
+	struct ccsr_qman *qman = (void *)CONFIG_SYS_FSL_QMAN_ADDR;
+
+	/* Set the Qman initiator BAR to match the LAW (for DQRR stashing) */
+#ifdef CONFIG_PHYS_64BIT
+	out_be32(&qman->qcsp_bare, (u32)(CONFIG_SYS_QMAN_MEM_PHYS >> 32));
+#endif
+	out_be32(&qman->qcsp_bar, (u32)CONFIG_SYS_QMAN_MEM_PHYS);
+#endif
+#ifdef CONFIG_FSL_CORENET
+	int i;
+
+	for (i = 0; i < CONFIG_SYS_QMAN_NUM_PORTALS; i++) {
+		u8 sdest = qp_info[i].sdest;
+		u16 fliodn = qp_info[i].fliodn;
+		u16 dliodn = qp_info[i].dliodn;
+		u16 liodn_off = qp_info[i].liodn_offset;
+
+		out_be32(&qman->qcsp[i].qcsp_lio_cfg, (liodn_off << 16) |
+					dliodn);
+		/* set frame liodn */
+		out_be32(&qman->qcsp[i].qcsp_io_cfg, (sdest << 16) | fliodn);
+	}
+#endif
+
+	/* Change default state of BMan ISDR portals to all 1s */
+	inhibit_portals(bpaddr, CONFIG_SYS_BMAN_NUM_PORTALS, MAX_BPORTALS,
+			CONFIG_SYS_BMAN_SP_CINH_SIZE);
+	inhibit_portals(qpaddr, CONFIG_SYS_QMAN_NUM_PORTALS, MAX_QPORTALS,
+			CONFIG_SYS_QMAN_SP_CINH_SIZE);
+}
+
+void inhibit_portals(void __iomem *addr, int max_portals,
+		     int arch_max_portals, int portal_cinh_size)
+{
+	u32 val;
+	int i;
+
+	/* arch_max_portals is the maximum based on memory size. This includes
+	 * the reserved memory in the SoC.  max_portals the number of physical
+	 * portals in the SoC
+	 */
+	if (max_portals > arch_max_portals) {
+		printf("ERROR: portal config error\n");
+		max_portals = arch_max_portals;
+	}
+
+	for (i = 0; i < max_portals; i++) {
+		out_be32(addr, -1);
+		val = in_be32(addr);
+		if (!val) {
+			printf("ERROR: Stopped after %d portals\n", i);
+			return;
+		}
+		addr += portal_cinh_size;
+	}
+	debug("Cleared %d portals\n", i);
+}
+
+#ifdef CONFIG_PPC
+static int fdt_qportal(void *blob, int off, int id, char *name,
+		       enum fsl_dpaa_dev dev, int create)
+{
+	int childoff, dev_off, ret = 0;
+	u32 dev_handle;
+#ifdef CONFIG_FSL_CORENET
+	int num;
+	u32 liodns[2];
+#endif
+
+	childoff = fdt_subnode_offset(blob, off, name);
+	if (create) {
+		char handle[64], *p;
+
+		strncpy(handle, name, sizeof(handle));
+		p = strchr(handle, '@');
+		if (!strncmp(name, "fman", 4)) {
+			*p = *(p + 1);
+			p++;
+		}
+		*p = '\0';
+
+		dev_off = fdt_path_offset(blob, handle);
+		/* skip this node if alias is not found */
+		if (dev_off == -FDT_ERR_BADPATH)
+			return 0;
+		if (dev_off < 0)
+			return dev_off;
+
+		if (childoff <= 0)
+			childoff = fdt_add_subnode(blob, off, name);
+
+		/* need to update the dev_off after adding a subnode */
+		dev_off = fdt_path_offset(blob, handle);
+		if (dev_off < 0)
+			return dev_off;
+
+		if (childoff > 0) {
+			dev_handle = fdt_get_phandle(blob, dev_off);
+			if (dev_handle <= 0) {
+				dev_handle = fdt_alloc_phandle(blob);
+				ret = fdt_set_phandle(blob, dev_off,
+						      dev_handle);
+				if (ret < 0)
+					return ret;
+			}
+
+			ret = fdt_setprop(blob, childoff, "dev-handle",
+					  &dev_handle, sizeof(dev_handle));
+			if (ret < 0)
+				return ret;
+
+#ifdef CONFIG_FSL_CORENET
+			num = get_dpaa_liodn(dev, &liodns[0], id);
+			ret = fdt_setprop(blob, childoff, "fsl,liodn",
+					  &liodns[0], sizeof(u32) * num);
+			if (!strncmp(name, "pme", 3)) {
+				u32 pme_rev1, pme_rev2;
+				ccsr_pme_t *pme_regs =
+					(void *)CONFIG_SYS_FSL_CORENET_PME_ADDR;
+
+				pme_rev1 = in_be32(&pme_regs->pm_ip_rev_1);
+				pme_rev2 = in_be32(&pme_regs->pm_ip_rev_2);
+				ret = fdt_setprop(blob, childoff,
+						  "fsl,pme-rev1", &pme_rev1,
+						  sizeof(u32));
+				if (ret < 0)
+					return ret;
+				ret = fdt_setprop(blob, childoff,
+						  "fsl,pme-rev2", &pme_rev2,
+						  sizeof(u32));
+			}
+#endif
+		} else {
+			return childoff;
+		}
+	} else {
+		if (childoff > 0)
+			ret = fdt_del_node(blob, childoff);
+	}
+
+	return ret;
+}
+#endif /* CONFIG_PPC */
+
+void fdt_fixup_qportals(void *blob)
+{
+	int off, err;
+	unsigned int maj, min;
+	unsigned int ip_cfg;
+	struct ccsr_qman *qman = (void *)CONFIG_SYS_FSL_QMAN_ADDR;
+	u32 rev_1 = in_be32(&qman->ip_rev_1);
+	u32 rev_2 = in_be32(&qman->ip_rev_2);
+	char compat[64];
+	int compat_len;
+
+	maj = (rev_1 >> 8) & 0xff;
+	min = rev_1 & 0xff;
+	ip_cfg = rev_2 & 0xff;
+
+	compat_len = sprintf(compat, "fsl,qman-portal-%u.%u.%u",
+			     maj, min, ip_cfg) + 1;
+	compat_len += sprintf(compat + compat_len, "fsl,qman-portal") + 1;
+
+	off = fdt_node_offset_by_compatible(blob, -1, "fsl,qman-portal");
+	while (off != -FDT_ERR_NOTFOUND) {
+#ifdef CONFIG_PPC
+#ifdef CONFIG_FSL_CORENET
+		u32 liodns[2];
+#endif
+		const int *ci = fdt_getprop(blob, off, "cell-index", &err);
+		int i;
+
+		if (!ci)
+			goto err;
+
+		i = *ci;
+#ifdef CONFIG_SYS_DPAA_FMAN
+		int j;
+#endif
+
+#endif /* CONFIG_PPC */
+		err = fdt_setprop(blob, off, "compatible", compat, compat_len);
+		if (err < 0)
+			goto err;
+#ifdef CONFIG_PPC
+#ifdef CONFIG_FSL_CORENET
+		liodns[0] = qp_info[i].dliodn;
+		liodns[1] = qp_info[i].fliodn;
+		err = fdt_setprop(blob, off, "fsl,liodn",
+				  &liodns, sizeof(u32) * 2);
+		if (err < 0)
+			goto err;
+#endif
+
+		i++;
+
+		err = fdt_qportal(blob, off, i, "crypto@0", FSL_HW_PORTAL_SEC,
+				  IS_E_PROCESSOR(get_svr()));
+		if (err < 0)
+			goto err;
+
+#ifdef CONFIG_FSL_CORENET
+#ifdef CONFIG_SYS_DPAA_PME
+		err = fdt_qportal(blob, off, i, "pme@0", FSL_HW_PORTAL_PME, 1);
+		if (err < 0)
+			goto err;
+#else
+		fdt_qportal(blob, off, i, "pme@0", FSL_HW_PORTAL_PME, 0);
+#endif
+#endif
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+		for (j = 0; j < CONFIG_SYS_NUM_FMAN; j++) {
+			char name[] = "fman@0";
+
+			name[sizeof(name) - 2] = '0' + j;
+			err = fdt_qportal(blob, off, i, name,
+					  FSL_HW_PORTAL_FMAN1 + j, 1);
+			if (err < 0)
+				goto err;
+		}
+#endif
+#ifdef CONFIG_SYS_DPAA_RMAN
+		err = fdt_qportal(blob, off, i, "rman@0",
+				  FSL_HW_PORTAL_RMAN, 1);
+		if (err < 0)
+			goto err;
+#endif
+#endif /* CONFIG_PPC */
+
+err:
+		if (err < 0) {
+			printf("ERROR: unable to create props for %s: %s\n",
+			       fdt_get_name(blob, off, NULL),
+			       fdt_strerror(err));
+			return;
+		}
+
+		off = fdt_node_offset_by_compatible(blob, off,
+						    "fsl,qman-portal");
+	}
+}
+
+void fdt_fixup_bportals(void *blob)
+{
+	int off, err;
+	unsigned int maj, min;
+	unsigned int ip_cfg;
+	struct ccsr_bman *bman = (void *)CONFIG_SYS_FSL_BMAN_ADDR;
+	u32 rev_1 = in_be32(&bman->ip_rev_1);
+	u32 rev_2 = in_be32(&bman->ip_rev_2);
+	char compat[64];
+	int compat_len;
+
+	maj = (rev_1 >> 8) & 0xff;
+	min = rev_1 & 0xff;
+
+	ip_cfg = rev_2 & 0xff;
+
+	compat_len = sprintf(compat, "fsl,bman-portal-%u.%u.%u",
+			     maj, min, ip_cfg) + 1;
+	compat_len += sprintf(compat + compat_len, "fsl,bman-portal") + 1;
+
+	off = fdt_node_offset_by_compatible(blob, -1, "fsl,bman-portal");
+	while (off != -FDT_ERR_NOTFOUND) {
+		err = fdt_setprop(blob, off, "compatible", compat, compat_len);
+		if (err < 0) {
+			printf("ERROR: unable to create props for %s: %s\n",
+			       fdt_get_name(blob, off, NULL),
+			       fdt_strerror(err));
+			return;
+		}
+
+		off = fdt_node_offset_by_compatible(blob, off,
+						    "fsl,bman-portal");
+	}
+}
diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h
index 67b5ea715e..1a7ff56b86 100644
--- a/include/configs/ls1043a_common.h
+++ b/include/configs/ls1043a_common.h
@@ -194,6 +194,8 @@
 #endif
 #endif
 
+#define CONFIG_SYS_DPAA_QBMAN		/* Support Q/Bman */
+
 /* FMan ucode */
 #ifndef SPL_NO_FMAN
 #define CONFIG_SYS_DPAA_FMAN
diff --git a/include/fsl_qbman.h b/include/fsl_qbman.h
new file mode 100644
index 0000000000..06262ec00f
--- /dev/null
+++ b/include/fsl_qbman.h
@@ -0,0 +1,75 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __FSL_QBMAN_H__
+#define __FSL_QBMAN_H__
+void fdt_fixup_qportals(void *blob);
+void fdt_fixup_bportals(void *blob);
+void inhibit_portals(void __iomem *addr, int max_portals,
+		     int arch_max_portals, int portal_cinh_size);
+void setup_qbman_portals(void);
+
+struct ccsr_qman {
+#ifdef CONFIG_SYS_FSL_QMAN_V3
+	u8	res0[0x200];
+#else
+	struct {
+		u32	qcsp_lio_cfg;	/* 0x0 - SW Portal n LIO cfg */
+		u32	qcsp_io_cfg;	/* 0x4 - SW Portal n IO cfg */
+		u32	res;
+		u32	qcsp_dd_cfg;	/* 0xc - SW Portal Dynamic Debug cfg */
+	} qcsp[32];
+#endif
+	/* Not actually reserved, but irrelevant to u-boot */
+	u8	res[0xbf8 - 0x200];
+	u32	ip_rev_1;
+	u32	ip_rev_2;
+	u32	fqd_bare;	/* FQD Extended Base Addr Register */
+	u32	fqd_bar;	/* FQD Base Addr Register */
+	u8	res1[0x8];
+	u32	fqd_ar;		/* FQD Attributes Register */
+	u8	res2[0xc];
+	u32	pfdr_bare;	/* PFDR Extended Base Addr Register */
+	u32	pfdr_bar;	/* PFDR Base Addr Register */
+	u8	res3[0x8];
+	u32	pfdr_ar;	/* PFDR Attributes Register */
+	u8	res4[0x4c];
+	u32	qcsp_bare;	/* QCSP Extended Base Addr Register */
+	u32	qcsp_bar;	/* QCSP Base Addr Register */
+	u8	res5[0x78];
+	u32	ci_sched_cfg;	/* Initiator Scheduling Configuration */
+	u32	srcidr;		/* Source ID Register */
+	u32	liodnr;		/* LIODN Register */
+	u8	res6[4];
+	u32	ci_rlm_cfg;	/* Initiator Read Latency Monitor Cfg */
+	u32	ci_rlm_avg;	/* Initiator Read Latency Monitor Avg */
+	u8	res7[0x2e8];
+#ifdef CONFIG_SYS_FSL_QMAN_V3
+	struct {
+		u32	qcsp_lio_cfg;	/* 0x0 - SW Portal n LIO cfg */
+		u32	qcsp_io_cfg;	/* 0x4 - SW Portal n IO cfg */
+		u32	res;
+		u32	qcsp_dd_cfg;	/* 0xc - SW Portal n Dynamic Debug cfg*/
+	} qcsp[50];
+#endif
+};
+
+struct ccsr_bman {
+	/* Not actually reserved, but irrelevant to u-boot */
+	u8	res[0xbf8];
+	u32	ip_rev_1;
+	u32	ip_rev_2;
+	u32	fbpr_bare;	/* FBPR Extended Base Addr Register */
+	u32	fbpr_bar;	/* FBPR Base Addr Register */
+	u8	res1[0x8];
+	u32	fbpr_ar;	/* FBPR Attributes Register */
+	u8	res2[0xf0];
+	u32	srcidr;		/* Source ID Register */
+	u32	liodnr;		/* LIODN Register */
+	u8	res7[0x2f4];
+};
+
+#endif /* __FSL_QBMAN_H__ */