diff options
| author | Gregory CLEMENT <gregory.clement@bootlin.com> | 2018-12-14 16:16:46 +0100 |
|---|---|---|
| committer | Daniel Schwierzeck <daniel.schwierzeck@gmail.com> | 2018-12-19 15:23:01 +0100 |
| commit | 464b96bb8094a359f7b27027319eda64a961c5af (patch) | |
| tree | cb5519d5797426d9bdbf9d7be344522836de58f2 | |
| parent | 48ee7b68533b7f007c337d9a606eb52c975445ad (diff) | |
MIPS: Allow to prefetch and lock instructions into cache
This path add a new helper allowing to prefetch and lock instructions
into cache. This is useful very early in the boot when no RAM is
available yet.
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
| -rw-r--r-- | arch/mips/include/asm/cacheops.h | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/arch/mips/include/asm/cacheops.h b/arch/mips/include/asm/cacheops.h index 3161875441..98b67ccc8e 100644 --- a/arch/mips/include/asm/cacheops.h +++ b/arch/mips/include/asm/cacheops.h @@ -19,6 +19,25 @@ static inline void mips_cache(int op, const volatile void *addr) #endif } +#define MIPS32_WHICH_ICACHE 0x0 +#define MIPS32_FETCH_AND_LOCK 0x7 + +#define ICACHE_LOAD_LOCK (MIPS32_WHICH_ICACHE | (MIPS32_FETCH_AND_LOCK << 2)) + +/* Prefetch and lock instructions into cache */ +static inline void icache_lock(void *func, size_t len) +{ + int i, lines = ((len - 1) / ARCH_DMA_MINALIGN) + 1; + + for (i = 0; i < lines; i++) { + asm volatile (" cache %0, %1(%2)" + : /* No Output */ + : "I" ICACHE_LOAD_LOCK, + "n" (i * ARCH_DMA_MINALIGN), + "r" (func) + : /* No Clobbers */); + } +} #endif /* !__ASSEMBLY__ */ /* |