diff options
| author | Haavard Skinnemoen <haavard.skinnemoen@atmel.com> | 2008-06-20 12:44:28 +0200 |
|---|---|---|
| committer | Haavard Skinnemoen <haavard.skinnemoen@atmel.com> | 2008-06-20 12:46:43 +0200 |
| commit | 5605ef6b5802921cbefe6a933a9dea3497396b5c (patch) | |
| tree | a48e023f54b03db2c2023c4f0372eb909e144f24 | |
| parent | 4688f9e34a87e825aed34d07c9ca7a273e6fc8ab (diff) | |
avr32: Fix SPI portmux initialization
Use the new GPIO manipulation functions to set up the chip select lines,
and make sure both busses use GPIO for chip select control.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
| -rw-r--r-- | cpu/at32ap/at32ap700x/gpio.c | 56 |
1 files changed, 34 insertions, 22 deletions
diff --git a/cpu/at32ap/at32ap700x/gpio.c b/cpu/at32ap/at32ap700x/gpio.c index 3da35d4fe2..56ba2f90c6 100644 --- a/cpu/at32ap/at32ap700x/gpio.c +++ b/cpu/at32ap/at32ap700x/gpio.c @@ -149,24 +149,27 @@ void gpio_enable_mmci(void) #ifdef AT32AP700x_CHIP_HAS_SPI void gpio_enable_spi0(unsigned long cs_mask) { - u32 pa_mask = 0; - gpio_select_periph_A(GPIO_PIN_PA0, 0); /* MISO */ gpio_select_periph_A(GPIO_PIN_PA1, 0); /* MOSI */ gpio_select_periph_A(GPIO_PIN_PA2, 0); /* SCK */ - if (cs_mask & (1 << 0)) - pa_mask |= 1 << 3; /* NPCS0 */ - if (cs_mask & (1 << 1)) - pa_mask |= 1 << 4; /* NPCS1 */ - if (cs_mask & (1 << 2)) - pa_mask |= 1 << 5; /* NPCS2 */ - if (cs_mask & (1 << 3)) - pa_mask |= 1 << 20; /* NPCS3 */ - - __raw_writel(pa_mask, PIOA_BASE + 0x00); - __raw_writel(pa_mask, PIOA_BASE + 0x30); - __raw_writel(pa_mask, PIOA_BASE + 0x10); + /* Set up NPCSx as GPIO outputs, initially high */ + if (cs_mask & (1 << 0)) { + gpio_set_value(GPIO_PIN_PA3, 1); + gpio_select_pio(GPIO_PIN_PA3, GPIOF_OUTPUT); + } + if (cs_mask & (1 << 1)) { + gpio_set_value(GPIO_PIN_PA4, 1); + gpio_select_pio(GPIO_PIN_PA4, GPIOF_OUTPUT); + } + if (cs_mask & (1 << 2)) { + gpio_set_value(GPIO_PIN_PA5, 1); + gpio_select_pio(GPIO_PIN_PA5, GPIOF_OUTPUT); + } + if (cs_mask & (1 << 3)) { + gpio_set_value(GPIO_PIN_PA20, 1); + gpio_select_pio(GPIO_PIN_PA20, GPIOF_OUTPUT); + } } void gpio_enable_spi1(unsigned long cs_mask) @@ -175,13 +178,22 @@ void gpio_enable_spi1(unsigned long cs_mask) gpio_select_periph_B(GPIO_PIN_PB1, 0); /* MOSI */ gpio_select_periph_B(GPIO_PIN_PB5, 0); /* SCK */ - if (cs_mask & (1 << 0)) - gpio_select_periph_B(GPIO_PIN_PB2, 0); /* NPCS0 */ - if (cs_mask & (1 << 1)) - gpio_select_periph_B(GPIO_PIN_PB3, 0); /* NPCS1 */ - if (cs_mask & (1 << 2)) - gpio_select_periph_B(GPIO_PIN_PB4, 0); /* NPCS2 */ - if (cs_mask & (1 << 3)) - gpio_select_periph_A(GPIO_PIN_PA27, 0); /* NPCS3 */ + /* Set up NPCSx as GPIO outputs, initially high */ + if (cs_mask & (1 << 0)) { + gpio_set_value(GPIO_PIN_PB2, 1); + gpio_select_pio(GPIO_PIN_PB2, GPIOF_OUTPUT); + } + if (cs_mask & (1 << 1)) { + gpio_set_value(GPIO_PIN_PB3, 1); + gpio_select_pio(GPIO_PIN_PB3, GPIOF_OUTPUT); + } + if (cs_mask & (1 << 2)) { + gpio_set_value(GPIO_PIN_PB4, 1); + gpio_select_pio(GPIO_PIN_PB4, GPIOF_OUTPUT); + } + if (cs_mask & (1 << 3)) { + gpio_set_value(GPIO_PIN_PA27, 1); + gpio_select_pio(GPIO_PIN_PA27, GPIOF_OUTPUT); + } } #endif |