diff options
| author | Wolfgang Denk <wd@denx.de> | 2007-08-16 12:04:37 +0200 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2007-08-16 12:04:37 +0200 |
| commit | 592391a6e5c8999e546671ac8efd71a311a03f07 (patch) | |
| tree | 5bc810c997cd2a0be418eadaae85caa17102d444 | |
| parent | 002275a3ed8b114885f6702d6d544d0780dfe689 (diff) | |
| parent | a5a38f4fd7e5366d706ff6a985f9b6715ddbc98b (diff) | |
Merge with /home/wd/git/u-boot/master
33 files changed, 826 insertions, 477 deletions
@@ -1,3 +1,91 @@ +commit 2d78074d2e806edc380c1464eb9e5df335ece65e +Author: Stefan Roese <sr@denx.de> +Date: Fri Jun 22 17:32:28 2007 +0200 + + ppc7xx: Update CPCI750 board + + This small CPCI750 update extends the board specific command + "show_config" to display the Marvell strapping registers and + extends the PCI IDE controller. + + Signed-off-by: Reinhard Arlt <reinhard.arlt@esd-electronics.com> + Signed-off-by: Stefan Roese <sr@denx.de> + +commit 30b52df9e906bf0e465916c2c6bb5192b438e0b8 +Author: Jon Loeliger <jdl@freescale.com> +Date: Wed Aug 15 11:55:35 2007 -0500 + + 86xx: Fix lingering CFG_CMD_* references in sbc8641d.h + + Remove a leftover in net/tftp.c while we're at it. + + Signed-off-by: Jon Loeliger <jdl@freescale.com> + +commit 4ce917742b1e48faa9bf9a9757545e56fb4cfe44 +Author: Jon Loeliger <jdl@freescale.com> +Date: Wed Aug 15 12:20:40 2007 -0500 + + Move the MPC8641HPCN board under board/freescale. + + Minor path corrections needed to ensure buildability. + + Signed-off-by: Jon Loeliger <jdl@freescale.com> + +commit 8662577fe36fdb6a44b55b998d9daac6392a736a +Author: Jon Loeliger <jdl@freescale.com> +Date: Wed Aug 15 11:46:22 2007 -0500 + + 86xx: Fix lingering CFG_CMD_* references in sbc8641d.h + + Remove a leftover in net/tftp.c while we're at it. + + Signed-off-by: Jon Loeliger <jdl@freescale.com> + +commit 210f463c71917b7a4495c2103c228b9c179ae64d +Author: Jerry Van Baren <gvb.uboot@gmail.com> +Date: Wed Aug 15 11:13:15 2007 -0400 + + Fix where the #ifdef CFG_BOOTMAPSZ is placed. + + Commit 073e1b509980cefe6f53c2d7fbbcd135df1e3924 "Fix initrd/dtb + interaction" put the new code outside of the #if defined(CONFIG_OF_LIBFDT) + when it should have gone inside of the conditional. As a result, it + broke non-LIBFDT board builds. + + Also added a missing "not." to the comment. + + Signed-off-by: Gerald Van Baren <vanbaren@cideas.com> + +commit 594e79838ce5078a90d0c27abb2b2d61d5f8e8a7 +Author: Ed Swarthout <Ed.Swarthout@freescale.com> +Date: Tue Aug 14 14:06:45 2007 -0500 + + Fix malloc size error in ahci_init_one. + + Typically this causes scsi init to corrupt the + devlist and break the coninfo command. + Fix a compiler size warning. + + Signed-off-by: Jason Jin <jason.jin@freescale.com> + Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> + Acked-by: Andy Fleming <afleming@freescale.com> + +commit b361acd64fd2525c081b9b288b0804efe209c0e9 +Author: ksi@koi8.net <ksi@koi8.net> +Date: Tue Aug 14 10:02:16 2007 -0700 + + TI DaVinci - fix unsupported %hhx format + + Signed-off-by: Sergey Kubushyn <ksi@koi8.net> + +commit f01dbb5424a81453c81190dd30e945891466f621 +Author: Wolfgang Denk <wd@denx.de> +Date: Tue Aug 14 18:42:36 2007 +0200 + + Coding style cleanup. Update CHANGELOG. + + Signed-off-by: Wolfgang Denk <wd@denx.de> + commit 073e1b509980cefe6f53c2d7fbbcd135df1e3924 Author: Andy Fleming <afleming@freescale.com> Date: Tue Aug 14 10:32:59 2007 -0500 @@ -20,6 +108,50 @@ Date: Tue Aug 14 15:40:00 2007 +0100 Supply spi interface in at45.c +commit 4ce846ec59f36b85d6644a769690ad3feb667575 +Author: Stefan Roese <sr@denx.de> +Date: Tue Aug 14 15:12:01 2007 +0200 + + POST: Fix merge problem + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit 429d9571f60631ae8a2fe12b11be4c75b0c2b37c +Author: Stefan Roese <sr@denx.de> +Date: Tue Aug 14 15:03:17 2007 +0200 + + Coding style cleanup + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit 779e975117a75e91fcebe226a63104dbfb924ab1 +Author: Stefan Roese <sr@denx.de> +Date: Tue Aug 14 14:44:41 2007 +0200 + + ppc4xx: Add initial Zeus (PPC405EP) board support + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit c5a172a5fd636c12467429e3f7910e53773979c6 +Author: Stefan Roese <sr@denx.de> +Date: Tue Aug 14 14:41:55 2007 +0200 + + POST: Add option for external ethernet loopback test + + When CFG_POST_ETHER_EXT_LOOPBACK is defined, the ethernet POST + is not done using an internal loopback connection, but by assuming + that an external loopback connector is plugged into the board. + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit eb2b4010ae426245172988804ee8d9193fb41038 +Author: Stefan Roese <sr@denx.de> +Date: Tue Aug 14 14:39:44 2007 +0200 + + POST: Add ppc405 support to cache and UART POST + + Signed-off-by: Stefan Roese <sr@denx.de> + commit 0c42f36f15074bd9808a7dbd7ef611fad9bf537c Author: Peter Pearse <peter.pearse@arm.com> Date: Tue Aug 14 10:46:32 2007 +0100 @@ -391,6 +523,17 @@ Date: Wed Jun 27 13:34:26 2007 +0200 Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com> Acked-by: Hans-Christian Egtvedt <hcegtvedt@atmel.com> +commit 273db7e1bdd1937e32f1d4507321bb721ebd3118 +Author: Stefan Roese <sr@denx.de> +Date: Mon Aug 13 09:05:33 2007 +0200 + + ppc4xx: Fix problem in PLL clock calculation + + This patch was originall provided by David Mitchell <dmitchell@amcc.com> + and fixes a bug in the PLL clock calculation. + + Signed-off-by: Stefan Roese <sr@denx.de> + commit 9986bc3e40e899bea372a99a2bca4071bdf2e24b Author: Wolfgang Denk <wd@denx.de> Date: Sun Aug 12 21:34:50 2007 +0200 @@ -849,6 +992,14 @@ Date: Thu Aug 2 14:42:20 2007 -0500 Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com> +commit 35d22f957a85a22bb3cd1ad084fa5404620d1c42 +Author: Stefan Roese <sr@denx.de> +Date: Fri Aug 10 10:42:25 2007 +0200 + + Coding style cleanup + + Signed-off-by: Stefan Roese <sr@denx.de> + commit 3a6d56c20989fe27360afe743bd2a7ad4d76e48f Author: Dirk Behme <dirk.behme@googlemail.com> Date: Thu Aug 2 17:42:08 2007 +0200 @@ -873,6 +1024,105 @@ Date: Thu Aug 2 17:41:14 2007 +0200 Signed-off-by: Dirk Behme <dirk.behme@gmail.com> +commit 157cda4d0c3d592ccbb19bbfc07d9251894f0894 +Author: Niklaus Giger <niklausgiger@gmx.ch> +Date: Fri Jul 27 11:31:22 2007 +0200 + + Add PPC4xx-HCU4 and HCU5 boards: HCU5 files + + Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com> + +commit 6e5de26c6e7580faf16e87745cd488b92b492d0c +Author: Niklaus Giger <niklausgiger@gmx.ch> +Date: Fri Jul 27 11:30:33 2007 +0200 + + Add PPC4xx-HCU4 and HCU5 boards: HCU4 files + + Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com> + +commit e8397fc78c9394d71de233a4d810fbc9047e4c76 +Author: Niklaus Giger <niklausgiger@gmx.ch> +Date: Fri Jul 27 11:38:26 2007 +0200 + + Add PPC4xx-HCU4 and HCU5 boards: common files + + Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com> + +commit ac982ea5a4f2f993efcf52dca122f5a59df047d8 +Author: Niklaus Giger <niklausgiger@gmx.ch> +Date: Fri Jul 27 11:28:44 2007 +0200 + + Add PPC4xx-HCU4 and HCU5 boards: make related + + Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com> + +commit 137fdd9f474ecb853efdace5200576308c67f18d +Author: Niklaus Giger <niklausgiger@gmx.ch> +Date: Fri Jul 27 11:28:03 2007 +0200 + + Add PPC4xx-HCU4 and HCU5 boards: HCU5 config + + Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com> + +commit 714bc55b35b6f6a65cc8740a3842a543e88cdef2 +Author: Niklaus Giger <niklausgiger@gmx.ch> +Date: Fri Jul 27 11:27:15 2007 +0200 + + Add PPC4xx-HCU4 and HCU5 boards: HCU4 config + + Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com> + +commit 1894dd381124bdbfbdae7cf3a6ca52a8eb1f4421 +Author: Niklaus Giger <niklausgiger@gmx.ch> +Date: Fri Jul 27 11:25:31 2007 +0200 + + Add PPC4xx-HCU4 and HCU5 boards: READMEs + + Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com> + +commit 641cca9569ce351ddb287fd3343d8b1dcb591db4 +Author: Niklaus Giger <niklausgiger@gmx.ch> +Date: Fri Jul 27 11:37:40 2007 +0200 + + Add PPC4xx-HCU4 and HCU5 boards: Infrastructure + + This series of patches adds support for 2 boards from Netstal Maschinen. + + The HCU4 has a PPC405Gpr and + the HCU5 has a PPC440EPX. + + The HCU4 has a somehow complicated flash setup, as the booteprom is + only 8 bits and the CFI 16 bits wide, which makes it impossible to use a more + elegant solution. + + The HCU5 has only a booteprom as the whole code will be downloaded from a + different board which has HD, CD-ROM, etc and where all code is stored. + + This is my third try. I incorporated all suggestions made by Wolfgang and Stefan. + Thanks them a lot. + + Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com> + +commit 3e4c90c6233618fc1806e63fde68df5f3d6a0171 +Author: Stefan Roese <sr@denx.de> +Date: Fri Aug 10 08:42:55 2007 +0200 + + ppc4xx: Update lwmon5 POST configuration + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit 29cb25da56afe18cf5e7072a92a9d98ea8af1fd4 +Author: Yuri Tikhonov <yur@emcraft.com> +Date: Fri Aug 10 08:25:22 2007 +0200 + + POST: Add ppc4xx UART POST support without external uart clock (lwmon5) + + The patch adds support for UART POST on ppc44x-based boards with no + external serial clocks installed. + + Signed-off-by: Yuri Tikhonov <yur@emcraft.com> + Acked-by: Stefan Roese <sr@denx.de> + commit 99c2fdab91bc633e46fb41dbaa629f87ccf6e00f Author: Kim Phillips <kim.phillips@freescale.com> Date: Mon Aug 6 18:18:34 2007 -0500 @@ -1169,6 +1419,17 @@ Date: Mon Aug 6 23:21:05 2007 +0200 Signed-off-by: Wolfgang Denk <wd@denx.de> +commit 537223afa61f64480df31ce440a9cb386df4a814 +Author: Stefan Roese <sr@denx.de> +Date: Mon Aug 6 21:10:17 2007 +0200 + + ppc4xx: Update AMCC Bamboo README doc/README.bamboo + + As suggested by Eugene O'Brien <Eugene.O'Brien@advantechamt.com>, + here an updated Bamboo README. + + Signed-off-by: Stefan Roese <sr@denx.de> + commit 9c7e4b06214db61bb21f1bcbe57c97519669baae Author: Wolfgang Denk <wd@denx.de> Date: Mon Aug 6 02:17:36 2007 +0200 @@ -1316,6 +1577,42 @@ Date: Thu Aug 2 10:11:18 2007 +0200 Minor cleanup of <board>_nand build rules. +commit 9ca8d79de096c65b9b9c867259b3ff4685f775ef +Author: Stefan Roese <sr@denx.de> +Date: Thu Aug 2 08:33:56 2007 +0200 + + ppc4xx: Code cleanup + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit c92409812206ac67a7fa7aae298539a9c3804a46 +Author: Grzegorz Bernacki <gjb@semihalf.com> +Date: Tue Jul 31 18:51:48 2007 +0200 + + [ppc440SPe] Graceful recovery from machine check during PCIe configuration + + During config transactions on the PCIe bus an attempt to scan for a + non-existent device can lead to a machine check exception with certain + peripheral devices. In order to avoid crashing in such scenarios the + instrumented versions of the config cycle read routines are introduced, so + the exceptions fixups framework can gracefully recover. + + Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com> + Acked-by: Rafal Jaworowski <raj@semihalf.com> + +commit dec99558b9ea75a37940d07f41a3565a50b54ad1 +Author: Rafal Jaworowski <raj@semihalf.com> +Date: Tue Jul 31 18:19:54 2007 +0200 + + [ppc4xx] Separate settings for PCIe bus numbering on 440SPe rev.A + + This brings back separate settings for PCIe bus numbers depending on chip + revision, which got eliminated in 2b393b0f0af8402ef43b25c1968bfd29714ddffa + commit. 440SPe rev. A does NOT work properly with the same settings as for + the rev. B (no devices are seen on the bus during enumeration). + + Signed-off-by: Rafal Jaworowski <raj@semihalf.com> + commit cdd917a43da6fa7fc8f54a3cc9f420ce5ecf3197 Author: Wolfgang Denk <wd@denx.de> Date: Thu Aug 2 00:48:45 2007 +0200 @@ -1324,6 +1621,55 @@ Date: Thu Aug 2 00:48:45 2007 +0200 Signed-off-by: Wolfgang Denk <wd@denx.de> +commit d2f68006627eda6cb6c7f364bddf621dbfd2fc68 +Author: Eugene OBrien <eugene.obrien@advantechamt.com> +Date: Tue Jul 31 10:24:56 2007 +0200 + + ppc4xx: Update AMCC Bamboo 440EP support + + Changed storage type of cfg_simulate_spd_eeprom to const + Changed storage type of gpio_tab to stack storage + (Cannot access global data declarations in .bss until afer code relocation) + + Improved SDRAM tests to catch problems where data is not uniquely addressable + (e.g. incorrectly programmed SDRAM row or columns) + + Added CONFIG_PROG_SDRAM_TLB to support Bamboo SIMM/DIMM modules + Fixed AM29LV320DT (OpCode Flash) sector map + + Signed-off-by: Eugene OBrien <eugene.obrien@advantechamt.com> + Signed-off-by: Stefan Roese <sr@denx.de> + +commit ea9f6bce383cc9fbcdee28b5836109b1a6dba574 +Author: Stefan Roese <sr@denx.de> +Date: Tue Jul 31 08:37:01 2007 +0200 + + ppc4xx: Update 440EPx lwmon5 board support + + - Clear ECC status regs after ECC POST test + - Set dcbz for ECC generation with caches enabled as default + - Code cleanup + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit 27a528fb41433c4c1e2b5d6bd3fd8d78606fc724 +Author: Stefan Roese <sr@denx.de> +Date: Mon Jul 30 11:04:57 2007 +0200 + + ppc4xx: Only print ECC related info when the error bis are set + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit e36220a4baf1f188ba60f17e9d0f043069b1362a +Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com> +Date: Fri Jul 27 16:44:31 2007 +0200 + + new FPGA image for PLU405 board + + new FPGA image for PLU405 board with improved CompactFlash timing + + Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com> + commit 8993e54b6f397973794f3d6f47d3b3c0c98dd4f6 Author: Rafal Jaworowski <raj@semihalf.com> Date: Fri Jul 27 14:43:59 2007 +0200 @@ -1351,6 +1697,73 @@ Date: Fri Jul 27 14:22:04 2007 +0200 Signed-off-by: Rafal Jaworowski <raj@semihalf.com> +commit d4024bb72dd81695ec099b2199eda0d27c623e62 +Author: John Otken <john@softadvances.com> +Date: Thu Jul 26 17:49:11 2007 +0200 + + ppc4xx: Add support for AMCC 405EP Taihu board + + Signed-off-by: John Otken <john@softadvances.com> + +commit b66091de6c7390620312c2501db23d8391e7cabb +Author: Anatolij Gustschin <agust@denx.de> +Date: Thu Jul 26 15:08:01 2007 +0200 + + ppc4xx: lwmon5: Update Lime initialization + + Change Lime SDRAM initialization to now support 100MHz and + 133MHz (if enabled). Also the framebuffer is initialized to + display a blue rectangle with a white border. + + Signed-off-by: Anatolij Gustschin <agust@denx.de> + Signed-off-by: Stefan Roese <sr@denx.de> + +commit 9f24a808f17fc0f37b7fb4805f734741335caecc +Author: Stefan Roese <sr@denx.de> +Date: Tue Jul 24 09:52:52 2007 +0200 + + ppc4xx: lwmon5: Support for 128 MByte NOR FLASH added + + The used Intel NOR FLASH chips have internally two dies, and are now + treated as two seperate chips. + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit aedf5bde179ecfbd0a96130d18996a96518b785f +Author: Stefan Roese <sr@denx.de> +Date: Tue Jul 24 07:20:09 2007 +0200 + + ppc4xx: Fix lwmon5 interrupt controller setup (polarity, trigger...) + + As suggested by Hakan Eryigit, here an updated setup for the lwmon5 + interrupt controller. + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit a71d96eac8130b53a91f93cd10c70fca0db18d52 +Author: Stefan Roese <sr@denx.de> +Date: Fri Jul 20 15:03:44 2007 +0200 + + ppc4xx: Fix bug with default GPIO output value + + As spotted by Matthias Fuchs, the default output values for all GPIO1 + outputs were not setup correctly. This patch fixes this issue. + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit 531e3e8b831f357056448fa573137d5fb37000fd +Author: Pavel Kolesnikov <concord@emcraft.com> +Date: Fri Jul 20 15:03:03 2007 +0200 + + POST: Add ECC POST for the lwmon5 board + + This patch adds ECC Post test for the Lwmon5 board based + on PPC440EPx to U-Boot. + + Signed-off-by: Pavel Kolesnikov <concord@emcraft.com> + Acked-by: Yuri Tikhonov <yur@emcraft.com> + Acked-by: Stefan Roese <sr@denx.de> + commit cc3023b9f95d7ac959a764471a65001062aecf41 Author: Rafal Jaworowski <raj@semihalf.com> Date: Thu Jul 19 17:12:28 2007 +0200 @@ -1362,6 +1775,58 @@ Date: Thu Jul 19 17:12:28 2007 +0200 Signed-off-by: Rafal Jaworowski <raj@semihalf.com> +commit 8848ec858f74ed6dab06fb6d5ddc933e0a1328bf +Author: Stefan Roese <sr@denx.de> +Date: Mon Jul 16 10:02:12 2007 +0200 + + ppc4xx: Code cleanup + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit 2a49fc17d09020e7ebd9536694d99d20e419fcb8 +Author: Stefan Roese <sr@denx.de> +Date: Mon Jul 16 10:01:38 2007 +0200 + + ppc4xx: AMCC Luan uses the new boardspecific DDR2 controller setup + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit df3f17422aeb03fb81a7ac8c78d2b05d05aa4cf9 +Author: Stefan Roese <sr@denx.de> +Date: Mon Jul 16 10:00:43 2007 +0200 + + ppc4xx: Support for Yucca board with 440SPe Rev A added to 44x_spd_ddr2.c + + The new boardspecific DDR2 controller configuration is used for the Yucca + board. Now the Yucca board with 440SPe Rev. A chips is also supported. + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit 6ed14addf97c8cd8f531e9ae7b2d3e222fffd53e +Author: Stefan Roese <sr@denx.de> +Date: Mon Jul 16 09:57:00 2007 +0200 + + ppc4xx: Add new weak functions to support boardspecific DDR2 configuration + + The new "weak" functions ddr_wrdtr() and ddr_clktr() are added to better + support non default, boardspecific DDR(2) controller configuration. + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit 5743a9207a370b90f09b20ebd61167c806b937f3 +Author: Stefan Roese <sr@denx.de> +Date: Mon Jul 16 08:53:51 2007 +0200 + + ppc4xx: Add remove_tlb() function to remove a mem area from TLB setup + + The new function remove_tlb() can be used to remove the TLB's used to + map a specific memory region. This is especially useful for the DDR(2) + setup routines which configure the SDRAM area temporarily as a cached + area (for speedup on auto-calibration and ECC generation) and later + need this area uncached for normal usage. + + Signed-off-by: Stefan Roese <sr@denx.de> + commit 3a6cab844cf74f76639d795e0be8717e02c86af7 Author: Wolfgang Denk <wd@denx.de> Date: Sat Jul 14 22:51:02 2007 +0200 @@ -1393,6 +1858,17 @@ Date: Fri Jul 13 08:26:05 2007 +0200 Signed-off-by: Heiko Schocher <hs@denx.de> +commit a2e1c7098cf9574386b0c96841dfc8ea5cc93578 +Author: Stefan Roese <sr@denx.de> +Date: Thu Jul 12 16:32:08 2007 +0200 + + ppc4xx: Change receive buffer handling in the 4xx emac driver + + This change fixes a bug in the receive buffer handling, that + could lead to problems upon high network traffic (broadcasts...). + + Signed-off-by: Stefan Roese <sr@denx.de> + commit 239f05ee4dd4cfe0b50f251b533dcebe9e67c360 Author: Wolfgang Denk <wd@denx.de> Date: Thu Jul 12 01:45:34 2007 +0200 @@ -1975,6 +2451,50 @@ Date: Tue Jul 10 00:01:28 2007 +0200 Signed-off-by: Wolfgang Denk <wd@denx.de> +commit c8603cfbd4573379a6076c9c208545ba2bbf019a +Author: Stefan Roese <sr@denx.de> +Date: Mon Jul 9 11:00:24 2007 +0200 + + Small coding style cleanup + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit 0f92c7e7c9a62755b1457d3c46f93c8c1f6c19fc +Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com> +Date: Mon Jul 9 10:10:08 2007 +0200 + + Migrate esd 405EP boards to new NAND subsystem + + Remove unused CFG_NAND_LEGACY define + + These boards to not have NAND. + + Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com> + +commit bd84ee4c2020c3a6861f4bb2e7ea0fb49f82e803 +Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com> +Date: Mon Jul 9 10:10:06 2007 +0200 + + Migrate esd 405EP boards to new NAND subsystem + + Migrate esd 405EP boards to new NAND subsystem + + -cleanup + -use correct io accessors (in/out_be32()) + + Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com> + +commit e09f7ab5749c345f924da272bea0521a73af5b11 +Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com> +Date: Mon Jul 9 10:10:04 2007 +0200 + + Migrate esd 405EP boards to new NAND subsystem + + This patch prepares the migration from the legacy NAND driver + to U-Boot's new NAND subsystem for esd boards. + + Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com> + commit c3517f919d0f61650cf3027fd4faf0f631142f6c Author: Jon Loeliger <jdl@freescale.com> Date: Sun Jul 8 18:10:08 2007 -0500 @@ -2162,6 +2682,41 @@ Date: Thu Jul 5 19:13:52 2007 -0500 Signed-off-by: Jon Loeliger <jdl@freescale.com> +commit 10e038932f22ee80ebd53de312531e70e6590a2f +Author: Thomas Knobloch <knobloch@siemens.com> +Date: Fri Jul 6 14:58:39 2007 +0200 + + [NAND] Bad block skipping for command nboot + + The old implementation of command nboot does not support reading the image from + NAND flash with skipping of bad blocks. The patch implements a new version of + the nboot command: by calling nboot.jffs2 from the u-boot command line the + command will load the image from NAND flash with respect to bad blocks (by using + nand_read_opts()). This is similar to e.g. the NAND read command: "nand + read.jffs2 ...". + + Signed-off-by: Thomas Knobloch <knobloch@siemens.com> + Signed-off-by: Stefan Roese <sr@denx.de> + +commit 334043f601a90ac53e5ecc846fbb73a1ef38cb1f +Author: Stefan Roese <sr@denx.de> +Date: Fri Jul 6 12:26:51 2007 +0200 + + ppc4xx: Update lwmon5 default environment + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit 5d187430a055d62f17ca84d75e7245439d1f7e75 +Author: Stefan Roese <sr@denx.de> +Date: Fri Jul 6 11:48:24 2007 +0200 + + ppc4xx: Update lwmon5 board + + Add unlock=yes environment variable to default variables to unlock + the CFI flash by default. + + Signed-off-by: Stefan Roese <sr@denx.de> + commit 6b0a174a1e6f55e1f5a1fbb223cdad7645a4646e Author: Stefan Roese <sr@denx.de> Date: Fri Jul 6 09:45:47 2007 +0200 @@ -3151,6 +3706,18 @@ Date: Fri Jun 22 14:58:04 2007 +0200 - adapt to the more generic EXCEPTION_PROLOG and CRIT_EXCEPTION macros - minor 4xx cleanup +commit d677b32855f577ae2690dcd64a172cdd706e0ffc +Author: Mike Frysinger <vapier@gentoo.org> +Date: Fri Jun 22 10:34:12 2007 +0200 + + [patch] add nand_init() prototype to nand.h + + since nand_init() is expected to be called by other parts of u-boot, there + should be a prototype for it in nand.h + + Signed-off-by: Mike Frysinger <vapier@gentoo.org> + Signed-off-by: Stefan Roese <sr@denx.de> + commit 83b4cfa3d629dff0264366263c5e94d9a50ad80b Author: Wolfgang Denk <wd@denx.de> Date: Wed Jun 20 18:14:24 2007 +0200 @@ -3767,6 +4334,16 @@ Date: Sun May 27 16:51:48 2007 +0200 Signed-off-by: Marian Balakowicz <m8@semihalf.com> Acked-by: Bartlomiej Sieka <tur@semihalf.com> +commit 7ebb4479b07ff294eb4d76e420753a0349f7c93b +Author: Ulf Samuelsson <ulf@atmel.com> +Date: Thu May 24 12:12:47 2007 +0200 + + [PATCH][NAND] Define the Vendor Id for Micron NAND Flash + + Signed-off-by: Ulf Samuelsson <ulf@atmel.com> + Signed-off-by: Ladislav Michl <ladis@linux-mips.org> + Signed-off-by: Stefan Roese <sr@denx.de> + commit d756894722c888d09a9fa1df8323753772d3dcce Author: Stefan Roese <sr@denx.de> Date: Thu May 24 09:49:00 2007 +0200 diff --git a/MAINTAINERS b/MAINTAINERS index f812431b82..d5249e5155 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -158,12 +158,12 @@ Matthias Fuchs <matthias.fuchs@esd-electronics.com> VOH405 PPC405EP VOM405 PPC405EP WUH405 PPC405EP - CMS700 PPC405EP + CMS700 PPC405EP Niklaus Giger <niklaus.giger@netstal.com> - HCU4 PPC405GPr - HCU5 PPC440EPx + HCU4 PPC405GPr + HCU5 PPC440EPx Frank Gottschling <fgottschling@eltec.de> diff --git a/board/esd/ash405/Makefile b/board/esd/ash405/Makefile index 4d75868ea8..308f752d09 100644 --- a/board/esd/ash405/Makefile +++ b/board/esd/ash405/Makefile @@ -28,7 +28,9 @@ endif LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o flash.o ../common/misc.o +COBJS = $(BOARD).o flash.o \ + ../common/misc.o \ + ../common/esd405ep_nand.o \ SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/esd/ash405/ash405.c b/board/esd/ash405/ash405.c index f41eb7b22c..8a5b03bced 100644 --- a/board/esd/ash405/ash405.c +++ b/board/esd/ash405/ash405.c @@ -23,6 +23,7 @@ #include <common.h> #include <asm/processor.h> +#include <asm/io.h> #include <command.h> #include <malloc.h> @@ -33,6 +34,7 @@ #endif extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); +extern void lxt971_no_sleep(void); /* fpga configuration data - gzip compressed and generated by bin2c */ const unsigned char fpgadata[] = @@ -164,18 +166,12 @@ int misc_init_r (void) /* * Reset external DUARTs */ - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_DUART_RST); /* set reset to high */ + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_DUART_RST); udelay(10); /* wait 10us */ - out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */ + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_DUART_RST); udelay(1000); /* wait 1ms */ /* - * Set NAND-FLASH GPIO signals to default - */ - out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE)); - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE); - - /* * Enable interrupts in exar duart mcr[3] */ *duart0_mcr = 0x08; @@ -218,35 +214,17 @@ long int initdram (int board_type) mtdcr(memcfga, mem_mb0cf); val = mfdcr(memcfgd); -#if 0 - printf("\nmb0cf=%x\n", val); /* test-only */ - printf("strap=%x\n", mfdcr(strap)); /* test-only */ -#endif - return (4*1024*1024 << ((val & 0x000e0000) >> 17)); } /* ------------------------------------------------------------------------- */ -int testdram (void) +void reset_phy(void) { - /* TODO: XXX XXX XXX */ - printf ("test: 16 MB - ok\n"); - - return (0); -} - -/* ------------------------------------------------------------------------- */ - -#if defined(CONFIG_CMD_NAND) -#include <linux/mtd/nand_legacy.h> -extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; - -void nand_init(void) -{ - nand_probe(CFG_NAND_BASE); - if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) { - print_size(nand_dev_desc[0].totlen, "\n"); - } -} +#ifdef CONFIG_LXT971_NO_SLEEP + /* + * Disable sleep mode in LXT971 + */ + lxt971_no_sleep(); #endif +} diff --git a/board/esd/cms700/Makefile b/board/esd/cms700/Makefile index df487662fd..0d4ab2d13a 100644 --- a/board/esd/cms700/Makefile +++ b/board/esd/cms700/Makefile @@ -33,7 +33,10 @@ CPLD = ../common/xilinx_jtag/lenval.o \ ../common/xilinx_jtag/micro.o \ ../common/xilinx_jtag/ports.o -COBJS = $(BOARD).o flash.o ../common/misc.o $(CPLD) +COBJS = $(BOARD).o flash.o \ + ../common/misc.o \ + $(CPLD) \ + ../common/esd405ep_nand.o \ SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/esd/cms700/cms700.c b/board/esd/cms700/cms700.c index 635ba2fdb9..2cdd7be360 100644 --- a/board/esd/cms700/cms700.c +++ b/board/esd/cms700/cms700.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2005 + * (C) Copyright 2005-2007 * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com * * See file CREDITS for list of people who contributed to this @@ -23,6 +23,7 @@ #include <common.h> #include <asm/processor.h> +#include <asm/io.h> #include <command.h> #include <malloc.h> @@ -68,9 +69,9 @@ int board_early_init_f (void) /* * Reset CPLD via GPIO12 (CS3) pin */ - out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_PLD_RESET); + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_PLD_RESET); udelay(1000); /* wait 1ms */ - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_PLD_RESET); + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_PLD_RESET); udelay(1000); /* wait 1ms */ return 0; @@ -94,13 +95,7 @@ int misc_init_r (void) /* * Setup and enable EEPROM write protection */ - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP); - - /* - * Set NAND-FLASH GPIO signals to default - */ - out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE)); - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE); + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_EEPROM_WP); return (0); } @@ -153,11 +148,6 @@ long int initdram (int board_type) mtdcr(memcfga, mem_mb0cf); val = mfdcr(memcfgd); -#if 0 - printf("\nmb0cf=%x\n", val); /* test-only */ - printf("strap=%x\n", mfdcr(strap)); /* test-only */ -#endif - return (4*1024*1024 << ((val & 0x000e0000) >> 17)); } @@ -180,17 +170,17 @@ int eeprom_write_enable (unsigned dev_addr, int state) switch (state) { case 1: /* Enable write access, clear bit GPIO_SINT2. */ - out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_EEPROM_WP); + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_EEPROM_WP); state = 0; break; case 0: /* Disable write access, set bit GPIO_SINT2. */ - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP); + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_EEPROM_WP); state = 0; break; default: /* Read current status back. */ - state = (0 == (in32(GPIO0_OR) & CFG_EEPROM_WP)); + state = (0 == (in_be32((void *)GPIO0_OR) & CFG_EEPROM_WP)); break; } } @@ -235,19 +225,6 @@ U_BOOT_CMD(eepwren, 2, 0, do_eep_wren, /* ------------------------------------------------------------------------- */ -#if defined(CONFIG_CMD_NAND) -#include <linux/mtd/nand_legacy.h> -extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; - -void nand_init(void) -{ - nand_probe(CFG_NAND_BASE); - if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) { - print_size(nand_dev_desc[0].totlen, "\n"); - } -} -#endif - void reset_phy(void) { #ifdef CONFIG_LXT971_NO_SLEEP diff --git a/board/esd/common/auto_update.c b/board/esd/common/auto_update.c index 62f6c20434..da147ee550 100644 --- a/board/esd/common/auto_update.c +++ b/board/esd/common/auto_update.c @@ -31,7 +31,9 @@ #include <command.h> #include <image.h> #include <asm/byteorder.h> +#if defined(CFG_NAND_LEGACY) #include <linux/mtd/nand_legacy.h> +#endif #include <fat.h> #include <part.h> @@ -294,6 +296,8 @@ int au_do_update(int i, long sz) rc = nand_legacy_rw(nand_dev_desc, NANDRW_WRITE | NANDRW_JFFS2, start, nbytes, (size_t *)&total, (uchar *)addr); debug ("nand_legacy_rw: ret=%x total=%d nbytes=%d\n", rc, total, nbytes); +#else + rc = -1; #endif } if (rc != 0) { diff --git a/board/esd/common/esd405ep_nand.c b/board/esd/common/esd405ep_nand.c new file mode 100644 index 0000000000..7bf68473d2 --- /dev/null +++ b/board/esd/common/esd405ep_nand.c @@ -0,0 +1,87 @@ +/* + * (C) Copyright 2007 + * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +#if defined(CONFIG_CMD_NAND) +#include <asm/io.h> +#include <nand.h> + +/* + * hardware specific access to control-lines + */ +static void esd405ep_nand_hwcontrol(struct mtd_info *mtdinfo, int cmd) +{ + switch(cmd) { + case NAND_CTL_SETCLE: + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_CLE); + break; + case NAND_CTL_CLRCLE: + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_NAND_CLE); + break; + case NAND_CTL_SETALE: + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_ALE); + break; + case NAND_CTL_CLRALE: + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_NAND_ALE); + break; + case NAND_CTL_SETNCE: + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_NAND_CE); + break; + case NAND_CTL_CLRNCE: + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_CE); + break; + } +} + + +/* + * read device ready pin + */ +static int esd405ep_nand_device_ready(struct mtd_info *mtdinfo) +{ + if (in_be32((void *)GPIO0_IR) & CFG_NAND_RDY) + return 1; + return 0; +} + + +int board_nand_init(struct nand_chip *nand) +{ + /* + * Set NAND-FLASH GPIO signals to defaults + */ + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE)); + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_CE); + + /* + * Initialize nand_chip structure + */ + nand->hwcontrol = esd405ep_nand_hwcontrol; + nand->dev_ready = esd405ep_nand_device_ready; + nand->eccmode = NAND_ECC_SOFT; + nand->chip_delay = NAND_BIG_DELAY_US; + nand->options = NAND_SAMSUNG_LP_OPTIONS; + return 0; +} +#endif diff --git a/board/esd/hh405/Makefile b/board/esd/hh405/Makefile index ce7876c414..0e5e57a5ad 100644 --- a/board/esd/hh405/Makefile +++ b/board/esd/hh405/Makefile @@ -28,7 +28,10 @@ endif LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o flash.o ../common/misc.o ../common/auto_update.o +COBJS = $(BOARD).o flash.o \ + ../common/misc.o \ + ../common/esd405ep_nand.o \ + ../common/auto_update.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/esd/hh405/hh405.c b/board/esd/hh405/hh405.c index 9ef5907cdd..67b5d5406d 100644 --- a/board/esd/hh405/hh405.c +++ b/board/esd/hh405/hh405.c @@ -5,7 +5,7 @@ * (C) Copyright 2005 * Stefan Roese, DENX Software Engineering, sr@denx.de. * - * (C) Copyright 2006 + * (C) Copyright 2006-2007 * Matthias Fuchs, esd GmbH, matthias.fuchs@esd-electronics.com * * See file CREDITS for list of people who contributed to this @@ -477,12 +477,6 @@ int misc_init_r (void) out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP); /* - * Set NAND-FLASH GPIO signals to default - */ - out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE)); - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE); - - /* * Reset touch-screen controller */ out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_TOUCH_RST); @@ -690,20 +684,6 @@ void ide_set_reset(int on) #endif /* CONFIG_IDE_RESET */ -#if defined(CONFIG_CMD_NAND) -#include <linux/mtd/nand_legacy.h> -extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; - -void nand_init(void) -{ - nand_probe(CFG_NAND_BASE); - if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) { - print_size(nand_dev_desc[0].totlen, "\n"); - } -} -#endif - - #if defined(CFG_EEPROM_WREN) /* Input: <dev_addr> I2C address of EEPROM device to enable. * <state> -1: deliver current state diff --git a/board/esd/hub405/Makefile b/board/esd/hub405/Makefile index 4d75868ea8..308f752d09 100644 --- a/board/esd/hub405/Makefile +++ b/board/esd/hub405/Makefile @@ -28,7 +28,9 @@ endif LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o flash.o ../common/misc.o +COBJS = $(BOARD).o flash.o \ + ../common/misc.o \ + ../common/esd405ep_nand.o \ SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/esd/hub405/hub405.c b/board/esd/hub405/hub405.c index dd3706e1a8..25c8068fde 100644 --- a/board/esd/hub405/hub405.c +++ b/board/esd/hub405/hub405.c @@ -153,12 +153,6 @@ int misc_init_r (void) out32(GPIO0_OR, val); /* - * Set NAND-FLASH GPIO signals to default - */ - out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE)); - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE); - - /* * check board type and setup AP power */ str = getenv("bd_type"); /* this is only set on non prototype hardware */ @@ -242,33 +236,5 @@ long int initdram (int board_type) mtdcr(memcfga, mem_mb0cf); val = mfdcr(memcfgd); -#if 0 - printf("\nmb0cf=%x\n", val); /* test-only */ - printf("strap=%x\n", mfdcr(strap)); /* test-only */ -#endif - return (4*1024*1024 << ((val & 0x000e0000) >> 17)); } - - -int testdram (void) -{ - /* TODO: XXX XXX XXX */ - printf ("test: 16 MB - ok\n"); - - return (0); -} - - -#if defined(CONFIG_CMD_NAND) -#include <linux/mtd/nand_legacy.h> -extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; - -void nand_init(void) -{ - nand_probe(CFG_NAND_BASE); - if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) { - print_size(nand_dev_desc[0].totlen, "\n"); - } -} -#endif diff --git a/board/esd/plu405/Makefile b/board/esd/plu405/Makefile index ce7876c414..0e5e57a5ad 100644 --- a/board/esd/plu405/Makefile +++ b/board/esd/plu405/Makefile @@ -28,7 +28,10 @@ endif LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o flash.o ../common/misc.o ../common/auto_update.o +COBJS = $(BOARD).o flash.o \ + ../common/misc.o \ + ../common/esd405ep_nand.o \ + ../common/auto_update.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/esd/plu405/plu405.c b/board/esd/plu405/plu405.c index 920f7178ae..f026a7ac3b 100644 --- a/board/esd/plu405/plu405.c +++ b/board/esd/plu405/plu405.c @@ -23,6 +23,7 @@ #include <common.h> #include <asm/processor.h> +#include <asm/io.h> #include <command.h> #include <malloc.h> @@ -31,6 +32,8 @@ #define FPGA_DEBUG #endif +DECLARE_GLOBAL_DATA_PTR; + extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); extern void lxt971_no_sleep(void); @@ -114,6 +117,10 @@ int misc_init_r (void) int index; int i; + /* adjust flash start and offset */ + gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; + gd->bd->bi_flashoffset = 0; + dst = malloc(CFG_FPGA_MAX_SIZE); if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { printf ("GUNZIP ERROR - must RESET board to recover\n"); @@ -177,18 +184,12 @@ int misc_init_r (void) /* * Reset external DUARTs */ - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_DUART_RST); /* set reset to high */ + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_DUART_RST); udelay(10); /* wait 10us */ - out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */ + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_DUART_RST); udelay(1000); /* wait 1ms */ /* - * Set NAND-FLASH GPIO signals to default - */ - out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE)); - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE); - - /* * Enable interrupts in exar duart mcr[3] */ *duart0_mcr = 0x08; @@ -226,24 +227,10 @@ long int initdram (int board_type) mtdcr(memcfga, mem_mb0cf); val = mfdcr(memcfgd); -#if 0 - printf("\nmb0cf=%x\n", val); /* test-only */ - printf("strap=%x\n", mfdcr(strap)); /* test-only */ -#endif - return (4*1024*1024 << ((val & 0x000e0000) >> 17)); } -int testdram (void) -{ - /* TODO: XXX XXX XXX */ - printf ("test: 16 MB - ok\n"); - - return (0); -} - - #ifdef CONFIG_IDE_RESET void ide_set_reset(int on) { @@ -262,31 +249,6 @@ void ide_set_reset(int on) #endif /* CONFIG_IDE_RESET */ -#if defined(CONFIG_CMD_NAND) -#include <linux/mtd/nand_legacy.h> -extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; - -void nand_init(void) -{ - nand_probe(CFG_NAND_BASE); - if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) { - print_size(nand_dev_desc[0].totlen, "\n"); - } -} -#endif - - -#ifdef CONFIG_AUTO_UPDATE_SHOW -void board_auto_update_show(int au_active) -{ - if (au_active) { - printf("\n Dies ist die board-funktion: Updating!!!\n"); - } else { - printf("\n Dies ist die board-funktion: Updating done!!!\n"); - } -} -#endif - void reset_phy(void) { #ifdef CONFIG_LXT971_NO_SLEEP diff --git a/board/esd/voh405/Makefile b/board/esd/voh405/Makefile index 4d75868ea8..308f752d09 100644 --- a/board/esd/voh405/Makefile +++ b/board/esd/voh405/Makefile @@ -28,7 +28,9 @@ endif LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o flash.o ../common/misc.o +COBJS = $(BOARD).o flash.o \ + ../common/misc.o \ + ../common/esd405ep_nand.o \ SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/esd/voh405/voh405.c b/board/esd/voh405/voh405.c index 3e118e7655..2857a0bef5 100644 --- a/board/esd/voh405/voh405.c +++ b/board/esd/voh405/voh405.c @@ -195,12 +195,6 @@ int misc_init_r (void) udelay(1000); /* wait 1ms */ /* - * Set NAND-FLASH GPIO signals to default - */ - out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE)); - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE); - - /* * Enable interrupts in exar duart mcr[3] */ *duart0_mcr = 0x08; @@ -340,17 +334,3 @@ void ide_set_reset(int on) } } #endif /* CONFIG_IDE_RESET */ - - -#if defined(CONFIG_CMD_NAND) -#include <linux/mtd/nand_legacy.h> -extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; - -void nand_init(void) -{ - nand_probe(CFG_NAND_BASE); - if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) { - print_size(nand_dev_desc[0].totlen, "\n"); - } -} -#endif diff --git a/board/esd/wuh405/Makefile b/board/esd/wuh405/Makefile index 4d75868ea8..308f752d09 100644 --- a/board/esd/wuh405/Makefile +++ b/board/esd/wuh405/Makefile @@ -28,7 +28,9 @@ endif LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o flash.o ../common/misc.o +COBJS = $(BOARD).o flash.o \ + ../common/misc.o \ + ../common/esd405ep_nand.o \ SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/esd/wuh405/wuh405.c b/board/esd/wuh405/wuh405.c index 61d1d6c0ce..dba3ce8884 100644 --- a/board/esd/wuh405/wuh405.c +++ b/board/esd/wuh405/wuh405.c @@ -170,12 +170,6 @@ int misc_init_r (void) udelay(1000); /* wait 1ms */ /* - * Set NAND-FLASH GPIO signals to default - */ - out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE)); - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE); - - /* * Enable interrupts in exar duart mcr[3] */ *duart0_mcr = 0x08; @@ -218,35 +212,5 @@ long int initdram (int board_type) mtdcr(memcfga, mem_mb0cf); val = mfdcr(memcfgd); -#if 0 - printf("\nmb0cf=%x\n", val); /* test-only */ - printf("strap=%x\n", mfdcr(strap)); /* test-only */ -#endif - return (4*1024*1024 << ((val & 0x000e0000) >> 17)); } - -/* ------------------------------------------------------------------------- */ - -int testdram (void) -{ - /* TODO: XXX XXX XXX */ - printf ("test: 16 MB - ok\n"); - - return (0); -} - -/* ------------------------------------------------------------------------- */ - -#if defined(CONFIG_CMD_NAND) -#include <linux/mtd/nand_legacy.h> -extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; - -void nand_init(void) -{ - nand_probe(CFG_NAND_BASE); - if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) { - print_size(nand_dev_desc[0].totlen, "\n"); - } -} -#endif diff --git a/common/cmd_nand.c b/common/cmd_nand.c index c72612d0d6..254a7755fc 100644 --- a/common/cmd_nand.c +++ b/common/cmd_nand.c @@ -468,14 +468,31 @@ static int nand_load_image(cmd_tbl_t *cmdtp, nand_info_t *nand, ulong offset, ulong addr, char *cmd) { int r; - char *ep; + char *ep, *s; ulong cnt; image_header_t *hdr; + int jffs2 = 0; + + s = strchr(cmd, '.'); + if (s != NULL && + (!strcmp(s, ".jffs2") || !strcmp(s, ".e") || !strcmp(s, ".i"))) + jffs2 = 1; printf("\nLoading from %s, offset 0x%lx\n", nand->name, offset); cnt = nand->oobblock; - r = nand_read(nand, offset, &cnt, (u_char *) addr); + if (jffs2) { + nand_read_options_t opts; + memset(&opts, 0, sizeof(opts)); + opts.buffer = (u_char*) addr; + opts.length = cnt; + opts.offset = offset; + opts.quiet = 1; + r = nand_read_opts(nand, &opts); + } else { + r = nand_read(nand, offset, &cnt, (u_char *) addr); + } + if (r) { puts("** Read error\n"); show_boot_progress (-56); @@ -495,8 +512,18 @@ static int nand_load_image(cmd_tbl_t *cmdtp, nand_info_t *nand, print_image_hdr(hdr); cnt = (ntohl(hdr->ih_size) + sizeof (image_header_t)); + if (jffs2) { + nand_read_options_t opts; + memset(&opts, 0, sizeof(opts)); + opts.buffer = (u_char*) addr; + opts.length = cnt; + opts.offset = offset; + opts.quiet = 1; + r = nand_read_opts(nand, &opts); + } else { + r = nand_read(nand, offset, &cnt, (u_char *) addr); + } - r = nand_read(nand, offset, &cnt, (u_char *) addr); if (r) { puts("** Read error\n"); show_boot_progress (-58); @@ -545,7 +572,7 @@ int do_nandboot(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) if (argc > 3) goto usage; if (argc == 3) - addr = simple_strtoul(argv[2], NULL, 16); + addr = simple_strtoul(argv[1], NULL, 16); else addr = CFG_LOAD_ADDR; return nand_load_image(cmdtp, &nand_info[dev->id->num], @@ -604,7 +631,7 @@ usage: U_BOOT_CMD(nboot, 4, 1, do_nandboot, "nboot - boot from NAND device\n", - "[partition] | [[[loadAddr] dev] offset]\n"); + "[.jffs2] [partition] | [[[loadAddr] dev] offset]\n"); #endif diff --git a/drivers/nand/nand_ids.c b/drivers/nand/nand_ids.c index 075cae66b0..6d7e347fba 100644 --- a/drivers/nand/nand_ids.c +++ b/drivers/nand/nand_ids.c @@ -123,6 +123,7 @@ struct nand_manufacturers nand_manuf_ids[] = { {NAND_MFR_NATIONAL, "National"}, {NAND_MFR_RENESAS, "Renesas"}, {NAND_MFR_STMICRO, "ST Micro"}, + {NAND_MFR_MICRON, "Micron"}, {0x0, "Unknown"} }; #endif diff --git a/include/configs/ASH405.h b/include/configs/ASH405.h index 9e0ee371c2..0718c85745 100644 --- a/include/configs/ASH405.h +++ b/include/configs/ASH405.h @@ -53,9 +53,13 @@ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ +#define CONFIG_NET_MULTI 1 +#undef CONFIG_HAS_ETH1 + #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 0 /* PHY address */ #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ +#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */ #define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/ @@ -144,39 +148,16 @@ * NAND-FLASH stuff *----------------------------------------------------------------------- */ +#define CFG_NAND_BASE_LIST { CFG_NAND_BASE } +#define NAND_MAX_CHIPS 1 +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define NAND_BIG_DELAY_US 25 -#define CFG_NAND_LEGACY - -#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define SECTORSIZE 512 - -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 - -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 - -#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ -#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ -#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ -#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ - -#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0) -#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0) -#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0) -#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0) -#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0) -#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0) -#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY)) - -#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) -#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) -#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) -#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) +#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ +#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ +#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ +#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ -#define CONFIG_MTD_NAND_VERIFY_WRITE 1 /* verify all writes!!! */ #define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ /*----------------------------------------------------------------------- diff --git a/include/configs/CMS700.h b/include/configs/CMS700.h index 08ef9b5da6..1fd2b53974 100644 --- a/include/configs/CMS700.h +++ b/include/configs/CMS700.h @@ -90,8 +90,6 @@ #define CONFIG_CMD_EEPROM -#define CFG_NAND_LEGACY - #undef CONFIG_WATCHDOG /* watchdog disabled */ #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ @@ -157,34 +155,15 @@ * NAND-FLASH stuff *----------------------------------------------------------------------- */ -#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define SECTORSIZE 512 - -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 - -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 - -#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ -#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ -#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ -#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ - -#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0) -#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0) -#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0) -#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0) -#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0) -#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0) -#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY)) - -#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) -#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) -#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) -#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) +#define CFG_NAND_BASE_LIST { CFG_NAND_BASE } +#define NAND_MAX_CHIPS 1 +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define NAND_BIG_DELAY_US 25 + +#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ +#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ +#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ +#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ #define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ diff --git a/include/configs/CPCI405.h b/include/configs/CPCI405.h index 0a4e1e9d30..1b948f6382 100644 --- a/include/configs/CPCI405.h +++ b/include/configs/CPCI405.h @@ -92,8 +92,6 @@ #define CONFIG_SUPPORT_VFAT -#define CFG_NAND_LEGACY - #undef CONFIG_WATCHDOG /* watchdog disabled */ #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ diff --git a/include/configs/CPCI4052.h b/include/configs/CPCI4052.h index ceeba6e122..fb71c5fb04 100644 --- a/include/configs/CPCI4052.h +++ b/include/configs/CPCI4052.h @@ -114,8 +114,6 @@ #define CONFIG_AUTO_UPDATE 1 /* autoupdate via compactflash */ #endif -#define CFG_NAND_LEGACY - #undef CONFIG_WATCHDOG /* watchdog disabled */ #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ diff --git a/include/configs/CPCI405AB.h b/include/configs/CPCI405AB.h index 1aefbbac68..49943195b7 100644 --- a/include/configs/CPCI405AB.h +++ b/include/configs/CPCI405AB.h @@ -100,9 +100,6 @@ #define CONFIG_SUPPORT_VFAT -#define CFG_NAND_LEGACY - - #undef CONFIG_WATCHDOG /* watchdog disabled */ #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ diff --git a/include/configs/CPCI405DT.h b/include/configs/CPCI405DT.h index e2652e6aa6..29f9292447 100644 --- a/include/configs/CPCI405DT.h +++ b/include/configs/CPCI405DT.h @@ -111,8 +111,6 @@ #undef CONFIG_AUTO_UPDATE /* autoupdate via compactflash */ -#define CFG_NAND_LEGACY - #undef CONFIG_WATCHDOG /* watchdog disabled */ #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ diff --git a/include/configs/HH405.h b/include/configs/HH405.h index 00f481c4b5..ea8e61a764 100644 --- a/include/configs/HH405.h +++ b/include/configs/HH405.h @@ -141,8 +141,6 @@ #define CONFIG_AUTO_UPDATE 1 /* autoupdate via compactflash */ #undef CONFIG_AUTO_UPDATE_SHOW /* use board show routine */ -#define CFG_NAND_LEGACY - #undef CONFIG_BZIP2 /* include support for bzip2 compressed images */ #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -209,34 +207,15 @@ * NAND-FLASH stuff *----------------------------------------------------------------------- */ -#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define SECTORSIZE 512 - -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 - -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 - -#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ -#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ -#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ -#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ - -#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0) -#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0) -#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0) -#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0) -#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0) -#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0) -#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY)) - -#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) -#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) -#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) -#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) +#define CFG_NAND_BASE_LIST { CFG_NAND_BASE } +#define NAND_MAX_CHIPS 1 +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define NAND_BIG_DELAY_US 25 + +#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ +#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ +#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ +#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ #define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ diff --git a/include/configs/HUB405.h b/include/configs/HUB405.h index 661b895f9a..ed669c51da 100644 --- a/include/configs/HUB405.h +++ b/include/configs/HUB405.h @@ -147,36 +147,15 @@ * NAND-FLASH stuff *----------------------------------------------------------------------- */ -#define CFG_NAND_LEGACY - -#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define SECTORSIZE 512 - -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 - -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 - -#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ -#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ -#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ -#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ - -#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0) -#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0) -#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0) -#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0) -#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0) -#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0) -#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY)) - -#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) -#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) -#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) -#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) +#define CFG_NAND_BASE_LIST { CFG_NAND_BASE } +#define NAND_MAX_CHIPS 1 +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define NAND_BIG_DELAY_US 25 + +#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ +#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ +#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ +#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ #define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ diff --git a/include/configs/PLU405.h b/include/configs/PLU405.h index 54703731af..4acbcd5e1c 100644 --- a/include/configs/PLU405.h +++ b/include/configs/PLU405.h @@ -96,7 +96,6 @@ #define CONFIG_SUPPORT_VFAT #define CONFIG_AUTO_UPDATE 1 /* autoupdate via compactflash */ -#define CONFIG_AUTO_UPDATE_SHOW 1 /* use board show routine */ #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -168,36 +167,15 @@ * NAND-FLASH stuff *----------------------------------------------------------------------- */ -#define CFG_NAND_LEGACY +#define CFG_NAND_BASE_LIST { CFG_NAND_BASE } +#define NAND_MAX_CHIPS 1 +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define NAND_BIG_DELAY_US 25 -#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define SECTORSIZE 512 - -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 - -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 - -#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ -#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ -#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ -#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ - -#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0) -#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0) -#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0) -#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0) -#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0) -#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0) -#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY)) - -#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) -#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) -#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) -#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) +#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ +#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ +#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ +#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ #define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ @@ -276,11 +254,6 @@ #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ -#if 0 /* test-only */ -#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */ -#define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */ -#endif - /*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) @@ -306,9 +279,6 @@ #define CFG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/ /* total size of a CAT24WC16 is 2048 bytes */ -#define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */ -#define CFG_NVRAM_SIZE 242 /* NVRAM size */ - /*----------------------------------------------------------------------- * I2C EEPROM (CAT24WC16) for environment */ @@ -317,7 +287,7 @@ #define CFG_I2C_SLAVE 0x7F #define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT24WC08 */ -#if 1 /* test-only */ + /* CAT24WC08/16... */ #define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ /* mask of address bits that overflow into the "EEPROM chip address" */ @@ -325,15 +295,6 @@ #define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ /* 16 byte page write mode using*/ /* last 4 bits of the address */ -#else -/* CAT24WC32/64... */ -#define CFG_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x01 -#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* The Catalyst CAT24WC32 has */ - /* 32 byte page write mode using*/ - /* last 5 bits of the address */ -#endif #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ #define CFG_EEPROM_PAGE_WRITE_ENABLE diff --git a/include/configs/VOH405.h b/include/configs/VOH405.h index 34f0ebdcfa..3880ec7476 100644 --- a/include/configs/VOH405.h +++ b/include/configs/VOH405.h @@ -153,36 +153,15 @@ * NAND-FLASH stuff *----------------------------------------------------------------------- */ -#define CFG_NAND_LEGACY - -#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define SECTORSIZE 512 - -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 - -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 - -#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ -#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ -#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ -#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ - -#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0) -#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0) -#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0) -#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0) -#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0) -#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0) -#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY)) - -#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) -#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) -#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) -#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) +#define CFG_NAND_BASE_LIST { CFG_NAND_BASE } +#define NAND_MAX_CHIPS 1 +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define NAND_BIG_DELAY_US 25 + +#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ +#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ +#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ +#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ #define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ diff --git a/include/configs/WUH405.h b/include/configs/WUH405.h index c1b3da863e..656784aa0c 100644 --- a/include/configs/WUH405.h +++ b/include/configs/WUH405.h @@ -145,38 +145,16 @@ * NAND-FLASH stuff *----------------------------------------------------------------------- */ -#define CFG_NAND_LEGACY - -#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define SECTORSIZE 512 - -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 - -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 - -#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ -#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ -#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ -#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ - -#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0) -#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0) -#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0) -#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0) -#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0) -#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0) -#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY)) - -#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) -#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) -#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) -#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) - -#define CONFIG_MTD_NAND_VERIFY_WRITE 1 /* verify all writes!!! */ +#define CFG_NAND_BASE_LIST { CFG_NAND_BASE } +#define NAND_MAX_CHIPS 1 +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define NAND_BIG_DELAY_US 25 + +#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ +#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ +#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ +#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ + #define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ /*----------------------------------------------------------------------- diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h index 4b485643a1..49ff80fd3a 100644 --- a/include/linux/mtd/nand.h +++ b/include/linux/mtd/nand.h @@ -348,6 +348,7 @@ struct nand_chip { #define NAND_MFR_NATIONAL 0x8f #define NAND_MFR_RENESAS 0x07 #define NAND_MFR_STMICRO 0x20 +#define NAND_MFR_MICRON 0x2c /** * struct nand_flash_dev - NAND Flash Device ID Structure diff --git a/include/nand.h b/include/nand.h index 23493f7e98..3c0752ea12 100644 --- a/include/nand.h +++ b/include/nand.h @@ -32,6 +32,7 @@ typedef struct mtd_info nand_info_t; extern int nand_curr_device; extern nand_info_t nand_info[]; +extern void nand_init(void); static inline int nand_read(nand_info_t *info, ulong ofs, ulong *len, u_char *buf) { |