diff options
| author | Grygorii Strashko <grygorii.strashko@ti.com> | 2019-11-18 23:04:47 +0200 |
|---|---|---|
| committer | Joe Hershberger <joe.hershberger@ni.com> | 2019-12-09 09:47:42 -0600 |
| commit | 5efb69298be40b1f277157b41e38442ab50eb4f2 (patch) | |
| tree | f36623aefb594c90547a9d44a6f4749a9f0674ef | |
| parent | 37d6265f2bfa216e97324837471cb78cafe7b57f (diff) | |
arm: dts: k3-am654-base-board-u-boot: change cpsw2g interface mode to rgmii-rxid
The AM654 SoC doesn't allow to disabling RGMII TX internal delay in CPSW2G
MAC. Hence, change CPSW2G interface mode to "rgmii-rxid" - RGMII with
internal RX delay provided by the PHY, the MAC will add an TX delay in this
case.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| -rw-r--r-- | arch/arm/dts/k3-am654-base-board-u-boot.dtsi | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi index 8589f76d23..bea80c5d00 100644 --- a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi +++ b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi @@ -336,13 +336,12 @@ reg = <0>; /* TODO: phy reset: TCA9555RTWR(i2c:0x21)[p04].GPIO_MCU_RGMII_RSTN */ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; - ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; }; }; &cpsw_port1 { - phy-mode = "rgmii-id"; + phy-mode = "rgmii-rxid"; phy-handle = <&phy0>; }; |