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authorVasily Khoruzhick <anarsoul@gmail.com>2018-11-09 20:41:45 -0800
committerJagan Teki <jagan@amarulasolutions.com>2018-11-22 13:19:42 +0530
commit629d267a9738f0214853493968f114962de54642 (patch)
tree1a523baf2edcc7ebfcff3b3e0200c5d141e7f308
parent2a8882ecefdeb9eb7ea2ea21427460e773a00e5a (diff)
sunxi-mmc: don't double clock for new mode unconditionally
Comment in Linux driver says that clock needs to be doubled only if we use DDR modes, moreover divider has to be set accordingly. U-boot driver doesn't declare support for any DDR modes and doesn't set internal clock divider in CLKCR, so it doubles clock unconditionally when new mode is used. Some cards can't handle that and as result SPL fails to load u-boot. Fixes: de9b1771c3b ("mmc: sunxi: Support new mode") Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> # Amarula A64-Relic
-rw-r--r--drivers/mmc/sunxi_mmc.c7
1 files changed, 0 insertions, 7 deletions
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index b3526f5e3f..e50b2c3343 100644
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers/mmc/sunxi_mmc.c
@@ -109,13 +109,6 @@ static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)
calibrate = true;
#endif
- /*
- * The MMC clock has an extra /2 post-divider when operating in the new
- * mode.
- */
- if (new_mode)
- hz = hz * 2;
-
if (hz <= 24000000) {
pll = CCM_MMC_CTRL_OSCM24;
pll_hz = 24000000;