x86: Clean up lapic codes

This commit cleans up the lapic codes:
- Delete arch/x86/include/asm/lapic_def.h, and move register and bit
  defines into arch/x86/include/asm/lapic.h
- Use MSR defines from msr-index.h in enable_lapic() and disable_lapic()
- Remove unnecessary stuff like NEED_LAPIC, X86_GOOD_APIC and
  CONFIG_AP_IN_SIPI_WAIT
- Move struct x86_cpu_priv defines to asm/arch-ivybridge/bd82x6x.h, as
  it is not apic related and only used by ivybridge
- Fix coding convention issues

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>

5 files changed, 103 insertions, 183 deletions

diff --git a/arch/x86/cpu/ivybridge/model_206ax.c b/arch/x86/cpu/ivybridge/model_206ax.c
index 8b08c40bcb..fd7db97cbd 100644
--- a/arch/x86/cpu/ivybridge/model_206ax.c
+++ b/arch/x86/cpu/ivybridge/model_206ax.c
@@ -13,12 +13,12 @@
 #include <asm/acpi.h>
 #include <asm/cpu.h>
 #include <asm/lapic.h>
-#include <asm/lapic_def.h>
 #include <asm/msr.h>
 #include <asm/mtrr.h>
 #include <asm/processor.h>
 #include <asm/speedstep.h>
 #include <asm/turbo.h>
+#include <asm/arch/bd82x6x.h>
 #include <asm/arch/model_206ax.h>
 
 static void enable_vmx(void)
diff --git a/arch/x86/cpu/lapic.c b/arch/x86/cpu/lapic.c
index 4690603c75..6769ae53ae 100644
--- a/arch/x86/cpu/lapic.c
+++ b/arch/x86/cpu/lapic.c
@@ -8,50 +8,46 @@
  */
 
 #include <common.h>
-#include <asm/msr.h>
-#include <asm/io.h>
 #include <asm/lapic.h>
 #include <asm/post.h>
 
 void lapic_setup(void)
 {
-#if NEED_LAPIC == 1
+#ifdef CONFIG_SMP
 	/* Only Pentium Pro and later have those MSR stuff */
 	debug("Setting up local apic: ");
 
 	/* Enable the local apic */
 	enable_lapic();
 
-	/*
-	 * Set Task Priority to 'accept all'.
-	 */
+	/* Set Task Priority to 'accept all' */
 	lapic_write_around(LAPIC_TASKPRI,
 			   lapic_read_around(LAPIC_TASKPRI) & ~LAPIC_TPRI_MASK);
 
 	/* Put the local apic in virtual wire mode */
 	lapic_write_around(LAPIC_SPIV, (lapic_read_around(LAPIC_SPIV) &
-				~(LAPIC_VECTOR_MASK)) | LAPIC_SPIV_ENABLE);
+			   ~(LAPIC_VECTOR_MASK)) | LAPIC_SPIV_ENABLE);
 	lapic_write_around(LAPIC_LVT0, (lapic_read_around(LAPIC_LVT0) &
-			~(LAPIC_LVT_MASKED | LAPIC_LVT_LEVEL_TRIGGER |
-			  LAPIC_LVT_REMOTE_IRR | LAPIC_INPUT_POLARITY |
-			  LAPIC_SEND_PENDING | LAPIC_LVT_RESERVED_1 |
-			  LAPIC_DELIVERY_MODE_MASK)) |
-			(LAPIC_LVT_REMOTE_IRR | LAPIC_SEND_PENDING |
-			 LAPIC_DELIVERY_MODE_EXTINT));
+			   ~(LAPIC_LVT_MASKED | LAPIC_LVT_LEVEL_TRIGGER |
+			   LAPIC_LVT_REMOTE_IRR | LAPIC_INPUT_POLARITY |
+			   LAPIC_SEND_PENDING | LAPIC_LVT_RESERVED_1 |
+			   LAPIC_DELIVERY_MODE_MASK)) |
+			   (LAPIC_LVT_REMOTE_IRR | LAPIC_SEND_PENDING |
+			   LAPIC_DELIVERY_MODE_EXTINT));
 	lapic_write_around(LAPIC_LVT1, (lapic_read_around(LAPIC_LVT1) &
-			~(LAPIC_LVT_MASKED | LAPIC_LVT_LEVEL_TRIGGER |
-			  LAPIC_LVT_REMOTE_IRR | LAPIC_INPUT_POLARITY |
-			  LAPIC_SEND_PENDING | LAPIC_LVT_RESERVED_1 |
-			  LAPIC_DELIVERY_MODE_MASK)) |
-		(LAPIC_LVT_REMOTE_IRR | LAPIC_SEND_PENDING |
-			LAPIC_DELIVERY_MODE_NMI));
+			   ~(LAPIC_LVT_MASKED | LAPIC_LVT_LEVEL_TRIGGER |
+			   LAPIC_LVT_REMOTE_IRR | LAPIC_INPUT_POLARITY |
+			   LAPIC_SEND_PENDING | LAPIC_LVT_RESERVED_1 |
+			   LAPIC_DELIVERY_MODE_MASK)) |
+			   (LAPIC_LVT_REMOTE_IRR | LAPIC_SEND_PENDING |
+			   LAPIC_DELIVERY_MODE_NMI));
 
 	debug("apic_id: 0x%02lx, ", lapicid());
-#else /* !NEED_LLAPIC */
+#else /* !CONFIG_SMP */
 	/* Only Pentium Pro and later have those MSR stuff */
 	debug("Disabling local apic: ");
 	disable_lapic();
-#endif /* !NEED_LAPIC */
+#endif /* CONFIG_SMP */
 	debug("done.\n");
 	post_code(POST_LAPIC);
 }
diff --git a/arch/x86/include/asm/arch-ivybridge/bd82x6x.h b/arch/x86/include/asm/arch-ivybridge/bd82x6x.h
index 5ae32f7883..7786493be7 100644
--- a/arch/x86/include/asm/arch-ivybridge/bd82x6x.h
+++ b/arch/x86/include/asm/arch-ivybridge/bd82x6x.h
@@ -16,7 +16,19 @@ int gma_func0_init(pci_dev_t dev, struct pci_controller *hose,
 		   const void *blob, int node);
 int bd82x6x_init(void);
 
-struct x86_cpu_priv;
+/**
+ * struct x86_cpu_priv - Information about a single CPU
+ *
+ * @apic_id: Advanced Programmable Interrupt Controller Identifier, which is
+ * just a number representing the CPU core
+ *
+ * TODO: Move this to driver model once lifecycle is understood
+ */
+struct x86_cpu_priv {
+	int apic_id;
+	int start_err;
+};
+
 int model_206ax_init(struct x86_cpu_priv *cpu);
 
 #endif
diff --git a/arch/x86/include/asm/lapic.h b/arch/x86/include/asm/lapic.h
index 0a7f443195..f60974a878 100644
--- a/arch/x86/include/asm/lapic.h
+++ b/arch/x86/include/asm/lapic.h
@@ -1,5 +1,5 @@
 /*
- * From Coreboot file of same name
+ * From coreboot file of same name
  *
  * Copyright (C) 2014 Google, Inc
  *
@@ -10,16 +10,61 @@
 #define _ARCH_ASM_LAPIC_H
 
 #include <asm/io.h>
-#include <asm/lapic_def.h>
 #include <asm/msr.h>
+#include <asm/msr-index.h>
 #include <asm/processor.h>
 
-/* See if I need to initialize the local apic */
-#if CONFIG_SMP || CONFIG_IOAPIC
-#  define NEED_LAPIC 1
-#else
-#  define NEED_LAPIC 0
-#endif
+#define LAPIC_DEFAULT_BASE		0xfee00000
+
+#define LAPIC_ID			0x020
+#define LAPIC_LVR			0x030
+
+#define LAPIC_TASKPRI			0x080
+#define LAPIC_TPRI_MASK			0xff
+
+#define LAPIC_RRR			0x0c0
+
+#define LAPIC_SPIV			0x0f0
+#define LAPIC_SPIV_ENABLE		0x100
+
+#define LAPIC_ICR			0x300
+#define LAPIC_DEST_SELF			0x40000
+#define LAPIC_DEST_ALLINC		0x80000
+#define LAPIC_DEST_ALLBUT		0xc0000
+#define LAPIC_ICR_RR_MASK		0x30000
+#define LAPIC_ICR_RR_INVALID		0x00000
+#define LAPIC_ICR_RR_INPROG		0x10000
+#define LAPIC_ICR_RR_VALID		0x20000
+#define LAPIC_INT_LEVELTRIG		0x08000
+#define LAPIC_INT_ASSERT		0x04000
+#define LAPIC_ICR_BUSY			0x01000
+#define LAPIC_DEST_LOGICAL		0x00800
+#define LAPIC_DM_FIXED			0x00000
+#define LAPIC_DM_LOWEST			0x00100
+#define LAPIC_DM_SMI			0x00200
+#define LAPIC_DM_REMRD			0x00300
+#define LAPIC_DM_NMI			0x00400
+#define LAPIC_DM_INIT			0x00500
+#define LAPIC_DM_STARTUP		0x00600
+#define LAPIC_DM_EXTINT			0x00700
+#define LAPIC_VECTOR_MASK		0x000ff
+
+#define LAPIC_ICR2			0x310
+#define GET_LAPIC_DEST_FIELD(x)		(((x) >> 24) & 0xff)
+#define SET_LAPIC_DEST_FIELD(x)		((x) << 24)
+
+#define LAPIC_LVT0			0x350
+#define LAPIC_LVT1			0x360
+#define LAPIC_LVT_MASKED		(1 << 16)
+#define LAPIC_LVT_LEVEL_TRIGGER		(1 << 15)
+#define LAPIC_LVT_REMOTE_IRR		(1 << 14)
+#define LAPIC_INPUT_POLARITY		(1 << 13)
+#define LAPIC_SEND_PENDING		(1 << 12)
+#define LAPIC_LVT_RESERVED_1		(1 << 11)
+#define LAPIC_DELIVERY_MODE_MASK	(7 << 8)
+#define LAPIC_DELIVERY_MODE_FIXED	(0 << 8)
+#define LAPIC_DELIVERY_MODE_NMI		(4 << 8)
+#define LAPIC_DELIVERY_MODE_EXTINT	(7 << 8)
 
 static inline __attribute__((always_inline))
 		unsigned long lapic_read(unsigned long reg)
@@ -42,21 +87,21 @@ static inline void enable_lapic(void)
 {
 	msr_t msr;
 
-	msr = msr_read(LAPIC_BASE_MSR);
+	msr = msr_read(MSR_IA32_APICBASE);
 	msr.hi &= 0xffffff00;
-	msr.lo |= LAPIC_BASE_MSR_ENABLE;
-	msr.lo &= ~LAPIC_BASE_MSR_ADDR_MASK;
+	msr.lo |= MSR_IA32_APICBASE_ENABLE;
+	msr.lo &= ~MSR_IA32_APICBASE_BASE;
 	msr.lo |= LAPIC_DEFAULT_BASE;
-	msr_write(LAPIC_BASE_MSR, msr);
+	msr_write(MSR_IA32_APICBASE, msr);
 }
 
 static inline void disable_lapic(void)
 {
 	msr_t msr;
 
-	msr = msr_read(LAPIC_BASE_MSR);
-	msr.lo &= ~(1 << 11);
-	msr_write(LAPIC_BASE_MSR, msr);
+	msr = msr_read(MSR_IA32_APICBASE);
+	msr.lo &= ~MSR_IA32_APICBASE_ENABLE;
+	msr_write(MSR_IA32_APICBASE, msr);
 }
 
 static inline __attribute__((always_inline)) unsigned long lapicid(void)
@@ -64,30 +109,24 @@ static inline __attribute__((always_inline)) unsigned long lapicid(void)
 	return lapic_read(LAPIC_ID) >> 24;
 }
 
-#if !CONFIG_AP_IN_SIPI_WAIT
-/* If we need to go back to sipi wait, we use the long non-inlined version of
- * this function in lapic_cpu_init.c
- */
 static inline __attribute__((always_inline)) void stop_this_cpu(void)
 {
 	/* Called by an AP when it is ready to halt and wait for a new task */
 	for (;;)
 		cpu_hlt();
 }
-#else
-void stop_this_cpu(void);
-#endif
 
-#define xchg(ptr, v) ((__typeof__(*(ptr)))__xchg((unsigned long)(v), (ptr), \
-							sizeof(*(ptr))))
+#define xchg(ptr, v)	((__typeof__(*(ptr)))__xchg((unsigned long)(v), (ptr), \
+						    sizeof(*(ptr))))
 
-struct __xchg_dummy { unsigned long a[100]; };
-#define __xg(x) ((struct __xchg_dummy *)(x))
+struct __xchg_dummy	{ unsigned long a[100]; };
+#define __xg(x)		((struct __xchg_dummy *)(x))
 
 /*
- * Note: no "lock" prefix even on SMP: xchg always implies lock anyway
+ * Note: no "lock" prefix even on SMP. xchg always implies lock anyway.
+ *
  * Note 2: xchg has side effect, so that attribute volatile is necessary,
- *	  but generally the primitive is invalid, *ptr is output argument. --ANK
+ *         but generally the primitive is invalid, *ptr is output argument.
  */
 static inline unsigned long __xchg(unsigned long x, volatile void *ptr,
 				   int size)
@@ -121,25 +160,19 @@ static inline void lapic_write_atomic(unsigned long reg, unsigned long v)
 	(void)xchg((volatile unsigned long *)(LAPIC_DEFAULT_BASE + reg), v);
 }
 
-
-#ifdef X86_GOOD_APIC
-# define FORCE_READ_AROUND_WRITE 0
-# define lapic_read_around(x) lapic_read(x)
-# define lapic_write_around(x, y) lapic_write((x), (y))
-#else
-# define FORCE_READ_AROUND_WRITE 1
-# define lapic_read_around(x) lapic_read(x)
-# define lapic_write_around(x, y) lapic_write_atomic((x), (y))
-#endif
+#define lapic_read_around(x)		lapic_read(x)
+#define lapic_write_around(x, y)	lapic_write_atomic((x), (y))
 
 static inline int lapic_remote_read(int apicid, int reg, unsigned long *pvalue)
 {
 	int timeout;
 	unsigned long status;
 	int result;
+
 	lapic_wait_icr_idle();
 	lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid));
 	lapic_write_around(LAPIC_ICR, LAPIC_DM_REMRD | (reg >> 4));
+
 	timeout = 0;
 	do {
 		status = lapic_read(LAPIC_ICR) & LAPIC_ICR_RR_MASK;
@@ -150,30 +183,10 @@ static inline int lapic_remote_read(int apicid, int reg, unsigned long *pvalue)
 		*pvalue = lapic_read(LAPIC_RRR);
 		result = 0;
 	}
+
 	return result;
 }
 
-
 void lapic_setup(void);
 
-#if CONFIG_SMP
-struct device;
-int start_cpu(struct device *cpu);
-#endif /* CONFIG_SMP */
-
-int boot_cpu(void);
-
-/**
- * struct x86_cpu_priv - Information about a single CPU
- *
- * @apic_id: Advanced Programmable Interrupt Controller Identifier, which is
- * just a number representing the CPU core
- *
- * TODO: Move this to driver model once lifecycle is understood
- */
-struct x86_cpu_priv {
-	int apic_id;
-	int start_err;
-};
-
 #endif
diff --git a/arch/x86/include/asm/lapic_def.h b/arch/x86/include/asm/lapic_def.h
deleted file mode 100644
index 722ceadaa4..0000000000
--- a/arch/x86/include/asm/lapic_def.h
+++ /dev/null
@@ -1,101 +0,0 @@
-/*
- * Taken from the Coreboot file of the same name
- *
- * (C) Copyright 2014 Google, Inc
- *
- * SPDX-License-Identifier:	GPL-2.0
- */
-
-#ifndef _ASM_LAPIC_DEF_H
-#define _ASM_LAPIC_DEF_H
-
-#define LAPIC_BASE_MSR			0x1B
-#define LAPIC_BASE_MSR_BOOTSTRAP_PROCESSOR	(1 << 8)
-#define LAPIC_BASE_MSR_ENABLE		(1 << 11)
-#define LAPIC_BASE_MSR_ADDR_MASK	0xFFFFF000
-
-#define LOCAL_APIC_ADDR			0xfee00000
-#define LAPIC_DEFAULT_BASE		LOCAL_APIC_ADDR
-
-#define LAPIC_ID			0x020
-#define LAPIC_LVR			0x030
-#define LAPIC_TASKPRI			0x80
-#define LAPIC_TPRI_MASK			0xFF
-#define LAPIC_ARBID			0x090
-#define LAPIC_RRR			0x0C0
-#define LAPIC_SVR			0x0f0
-#define LAPIC_SPIV			0x0f0
-#define LAPIC_SPIV_ENABLE		0x100
-#define LAPIC_ESR			0x280
-#define LAPIC_ESR_SEND_CS		0x00001
-#define LAPIC_ESR_RECV_CS		0x00002
-#define LAPIC_ESR_SEND_ACC		0x00004
-#define LAPIC_ESR_RECV_ACC		0x00008
-#define LAPIC_ESR_SENDILL		0x00020
-#define LAPIC_ESR_RECVILL		0x00040
-#define LAPIC_ESR_ILLREGA		0x00080
-#define LAPIC_ICR			0x300
-#define LAPIC_DEST_SELF			0x40000
-#define LAPIC_DEST_ALLINC		0x80000
-#define LAPIC_DEST_ALLBUT		0xC0000
-#define LAPIC_ICR_RR_MASK		0x30000
-#define LAPIC_ICR_RR_INVALID		0x00000
-#define LAPIC_ICR_RR_INPROG		0x10000
-#define LAPIC_ICR_RR_VALID		0x20000
-#define LAPIC_INT_LEVELTRIG		0x08000
-#define LAPIC_INT_ASSERT		0x04000
-#define LAPIC_ICR_BUSY			0x01000
-#define LAPIC_DEST_LOGICAL		0x00800
-#define LAPIC_DM_FIXED			0x00000
-#define LAPIC_DM_LOWEST			0x00100
-#define LAPIC_DM_SMI			0x00200
-#define LAPIC_DM_REMRD			0x00300
-#define LAPIC_DM_NMI			0x00400
-#define LAPIC_DM_INIT			0x00500
-#define LAPIC_DM_STARTUP		0x00600
-#define LAPIC_DM_EXTINT			0x00700
-#define LAPIC_VECTOR_MASK		0x000FF
-#define LAPIC_ICR2			0x310
-#define GET_LAPIC_DEST_FIELD(x)		(((x) >> 24) & 0xFF)
-#define SET_LAPIC_DEST_FIELD(x)		((x) << 24)
-#define LAPIC_LVTT			0x320
-#define LAPIC_LVTPC			0x340
-#define LAPIC_LVT0			0x350
-#define LAPIC_LVT_TIMER_BASE_MASK	(0x3 << 18)
-#define GET_LAPIC_TIMER_BASE(x)		(((x) >> 18) & 0x3)
-#define SET_LAPIC_TIMER_BASE(x)		(((x) << 18))
-#define LAPIC_TIMER_BASE_CLKIN		0x0
-#define LAPIC_TIMER_BASE_TMBASE		0x1
-#define LAPIC_TIMER_BASE_DIV		0x2
-#define LAPIC_LVT_TIMER_PERIODIC	(1 << 17)
-#define LAPIC_LVT_MASKED		(1 << 16)
-#define LAPIC_LVT_LEVEL_TRIGGER		(1 << 15)
-#define LAPIC_LVT_REMOTE_IRR		(1 << 14)
-#define LAPIC_INPUT_POLARITY		(1 << 13)
-#define LAPIC_SEND_PENDING		(1 << 12)
-#define LAPIC_LVT_RESERVED_1		(1 << 11)
-#define LAPIC_DELIVERY_MODE_MASK	(7 << 8)
-#define LAPIC_DELIVERY_MODE_FIXED	(0 << 8)
-#define LAPIC_DELIVERY_MODE_NMI		(4 << 8)
-#define LAPIC_DELIVERY_MODE_EXTINT	(7 << 8)
-#define GET_LAPIC_DELIVERY_MODE(x)	(((x) >> 8) & 0x7)
-#define SET_LAPIC_DELIVERY_MODE(x, y)	(((x) & ~0x700)|((y) << 8))
-#define LAPIC_MODE_FIXED		0x0
-#define LAPIC_MODE_NMI			0x4
-#define LAPIC_MODE_EXINT		0x7
-#define LAPIC_LVT1			0x360
-#define LAPIC_LVTERR			0x370
-#define LAPIC_TMICT			0x380
-#define LAPIC_TMCCT			0x390
-#define LAPIC_TDCR			0x3E0
-#define LAPIC_TDR_DIV_TMBASE		(1 << 2)
-#define LAPIC_TDR_DIV_1			0xB
-#define LAPIC_TDR_DIV_2			0x0
-#define LAPIC_TDR_DIV_4			0x1
-#define LAPIC_TDR_DIV_8			0x2
-#define LAPIC_TDR_DIV_16		0x3
-#define LAPIC_TDR_DIV_32		0x8
-#define LAPIC_TDR_DIV_64		0x9
-#define LAPIC_TDR_DIV_128		0xA
-
-#endif